From nobody Mon Nov 25 08:36:39 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1716752629; cv=none; d=zohomail.com; s=zohoarc; b=bMAMr/d0yWBuTOQ5onTim1AMMueAWN3EgpCgygj3HvE42CTUW8DLyvPKyvE5s3sZMrQ5yBYB1xbuF6GoKgtK5KsdQCrnR98IeL7d5HZTPu3cYjww7huSPOPCnODuoIFM22l+LBrevQdwmCx9m6a/Z43Cs9uIGzwyiRH9HVDWQeY= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1716752629; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=QyfYhcDz9GxZwfZD6zLLHvsedkNWvuKT9dIKJJP5Q0E=; b=Zw6RMDy+55/ltU/KUPLZaWlXwflw9mXgEGU5ukdxWIiby57AIZcglSlRQVDZrx7pBohg7T4I+v0FymJpG5M5ORPDvwk1D1xjSwS+eDaShQ2m3QnvqFIzkbryVupk/n/3fL13wem1sznOIBqpu29j8ScAAd4tsARN9LBcZO6By2s= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1716752629463327.2391559766845; Sun, 26 May 2024 12:43:49 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1sBJlk-0008A4-Oe; Sun, 26 May 2024 15:43:00 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1sBJlj-00089h-Lg for qemu-devel@nongnu.org; Sun, 26 May 2024 15:42:59 -0400 Received: from mail-pl1-x633.google.com ([2607:f8b0:4864:20::633]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1sBJlh-0007cX-Ry for qemu-devel@nongnu.org; Sun, 26 May 2024 15:42:59 -0400 Received: by mail-pl1-x633.google.com with SMTP id d9443c01a7336-1f4a0050b9aso1324795ad.2 for ; Sun, 26 May 2024 12:42:57 -0700 (PDT) Received: from stoup.. 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[174.21.72.5]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-1f46ad93c2esm28165935ad.263.2024.05.26.12.42.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 26 May 2024 12:42:55 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1716752576; x=1717357376; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=QyfYhcDz9GxZwfZD6zLLHvsedkNWvuKT9dIKJJP5Q0E=; b=NW5SmKS+mx3nr8EF/p2dXGCHrz7oyxF+p/XM5q1XAkwpmTeAEI2AmISN2WmGc10YBe uOna6uh7HjN0B95zIylg0AbJLIJYdoMudwR6TWzN+NKc/QIUnnhIqsP6JkF5mIu1HryG kw7NPxrPPSwwnSn9m/OGEP4RrFm+iS3pHxMmR2ZCoqZE7WFWo/IYRDO2F2WAmdsvra8N CG7qHTNn4jFJYIHDTFf80by6Rpgy5yoWQrPPh0YXCnKbE2FWqV0IQ1gqzZP2fXBjmUTF pTMPV+NpWZ1Dl/Xm2mKX7N/ulWhyZ5U1epHlphOlg79KEpoyu1q+BohKZmHK6JrqOSGj 8ifg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1716752576; x=1717357376; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=QyfYhcDz9GxZwfZD6zLLHvsedkNWvuKT9dIKJJP5Q0E=; b=bhPlh3uUVa6/AnysUXPJa/tvuVDE0srvzdUNN8050HBSGeLyVpxP84hkOwMzoQs/2s b7VNbDrwtlTdoC/RkGfxwNYLcPBEYTxAcFC8HOhMbs9nC7kWOLl529NulNyzLS7wV3Mn t4Sxm+7id3vWCPoW5R4uhc/cY2eVK6er4gHElJC7tayfG0PBy8EtQLTyoMPDaRKf55Oe e2W3N0P4Anma2uElXjmdYcgChgGKKjB05+OFc598ZHfpc68SpaFn0plxrFFDyqS2P7hT yRhwJAj/agqynbQfi9CohfU50BAFR/a0WjXD1+IeSDOBZKg41kccg0R1LsE8rkC8NKk/ ElAA== X-Gm-Message-State: AOJu0YxWhI3ap21EDj4wAi0iCZy6k3WXwDZWiJAu5NT363YpE1XKXnGZ EHtcVN8ok2Ocx+iCUiUsYKurxL3txUUBB77YNjH1l1RBu69fApyM4o9pDGLdz1DSiWyWAf/s83J H X-Google-Smtp-Source: AGHT+IFP3t4op3u6JPOrG8yYwAm3/CBbeGyR1hIM4RlvTxWv53PnT4hMaUZeyJJq+dk8YdxjpqbmRw== X-Received: by 2002:a17:903:245:b0:1f3:903:5c9a with SMTP id d9443c01a7336-1f4497e5d05mr85622535ad.58.1716752576243; Sun, 26 May 2024 12:42:56 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: mark.cave-ayland@ilande.co.uk Subject: [PATCH v2 01/37] target/sparc: Fix ARRAY8 Date: Sun, 26 May 2024 12:42:18 -0700 Message-Id: <20240526194254.459395-2-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240526194254.459395-1-richard.henderson@linaro.org> References: <20240526194254.459395-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::633; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x633.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1716752629846100003 Content-Type: text/plain; charset="utf-8" Follow the Oracle Sparc 2015 implementation note and bound the input value of N to 5 from the lower 3 bits of rs2. Spell out all of the intermediate values, matching the diagram in the manual. Fix extraction of upper_x and upper_y for N=3D0. Signed-off-by: Richard Henderson Tested-by: Mark Cave-Ayland --- target/sparc/vis_helper.c | 53 ++++++++++++++++++++++++++------------- 1 file changed, 35 insertions(+), 18 deletions(-) diff --git a/target/sparc/vis_helper.c b/target/sparc/vis_helper.c index e15c6bb34e..f46fcf1f6a 100644 --- a/target/sparc/vis_helper.c +++ b/target/sparc/vis_helper.c @@ -21,25 +21,42 @@ #include "cpu.h" #include "exec/helper-proto.h" =20 -/* This function uses non-native bit order */ -#define GET_FIELD(X, FROM, TO) \ - ((X) >> (63 - (TO)) & ((1ULL << ((TO) - (FROM) + 1)) - 1)) - -/* This function uses the order in the manuals, i.e. bit 0 is 2^0 */ -#define GET_FIELD_SP(X, FROM, TO) \ - GET_FIELD(X, 63 - (TO), 63 - (FROM)) - -target_ulong helper_array8(target_ulong pixel_addr, target_ulong cubesize) +target_ulong helper_array8(target_ulong rs1, target_ulong rs2) { - return (GET_FIELD_SP(pixel_addr, 60, 63) << (17 + 2 * cubesize)) | - (GET_FIELD_SP(pixel_addr, 39, 39 + cubesize - 1) << (17 + cubesize= )) | - (GET_FIELD_SP(pixel_addr, 17 + cubesize - 1, 17) << 17) | - (GET_FIELD_SP(pixel_addr, 56, 59) << 13) | - (GET_FIELD_SP(pixel_addr, 35, 38) << 9) | - (GET_FIELD_SP(pixel_addr, 13, 16) << 5) | - (((pixel_addr >> 55) & 1) << 4) | - (GET_FIELD_SP(pixel_addr, 33, 34) << 2) | - GET_FIELD_SP(pixel_addr, 11, 12); + /* + * From Oracle SPARC Architecture 2015: + * Architecturally, an illegal R[rs2] value (>5) causes the array + * instructions to produce undefined results. For historic reference, + * past implementations of these instructions have ignored R[rs2]{63:3} + * and have treated R[rs2] values of 6 and 7 as if they were 5. + */ + target_ulong n =3D MIN(rs2 & 7, 5); + + target_ulong x_int =3D (rs1 >> 11) & 0x7ff; + target_ulong y_int =3D (rs1 >> 33) & 0x7ff; + target_ulong z_int =3D rs1 >> 55; + + target_ulong lower_x =3D x_int & 3; + target_ulong lower_y =3D y_int & 3; + target_ulong lower_z =3D z_int & 1; + + target_ulong middle_x =3D (x_int >> 2) & 15; + target_ulong middle_y =3D (y_int >> 2) & 15; + target_ulong middle_z =3D (z_int >> 1) & 15; + + target_ulong upper_x =3D (x_int >> 6) & ((1 << n) - 1); + target_ulong upper_y =3D (y_int >> 6) & ((1 << n) - 1); + target_ulong upper_z =3D z_int >> 5; + + return (upper_z << (17 + 2 * n)) + | (upper_y << (17 + n)) + | (upper_x << 17) + | (middle_z << 13) + | (middle_y << 9) + | (middle_x << 5) + | (lower_z << 4) + | (lower_y << 2) + | lower_x; } =20 #if HOST_BIG_ENDIAN --=20 2.34.1 From nobody Mon Nov 25 08:36:39 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1716752730; cv=none; d=zohomail.com; s=zohoarc; b=i03f+d/8WL3eOKKOVpv3HfKHYu3siUFnhk3tbAEknbqyQ9j687XxaEc16Nd+YNlea+s/ZNxvmBZsc4zPna1r5Xu/OW4Fk6diymGK6zgsNHUCGT49Nk9N72wrgx1HvyvjoZZGWzwAhtIUzNn8JhStF1NDbaGkNJFZHHhGwjgdzJo= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1716752730; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=9GjOknDfw6CA/cxmtAArnOVpVQknG/Iz5WJ6byoYh9I=; b=kwyEbEb1TW3Fq5pdFAV+RcTsAxyDzQvUU2Cewc5CmMoKtHdVBwTdIyn+xNWtFjw4DYEZ72I1tAz0Lu5DNCWPwYYIUdTEqJFXpqGNsipDvXhKNcBzbSvhCdOs3NwnHnbp92QMV1vX/EtVpkrNR+YEHynYNXKp+jqiAZUj535NucQ= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1716752730854719.3083664493068; Sun, 26 May 2024 12:45:30 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1sBJll-0008Aw-VN; Sun, 26 May 2024 15:43:01 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1sBJlk-00089q-5V for qemu-devel@nongnu.org; Sun, 26 May 2024 15:43:00 -0400 Received: from mail-pl1-x636.google.com ([2607:f8b0:4864:20::636]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1sBJli-0007cc-C7 for qemu-devel@nongnu.org; Sun, 26 May 2024 15:42:59 -0400 Received: by mail-pl1-x636.google.com with SMTP id d9443c01a7336-1f47f0d8ec9so6124565ad.3 for ; Sun, 26 May 2024 12:42:57 -0700 (PDT) Received: from stoup.. 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[174.21.72.5]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-1f46ad93c2esm28165935ad.263.2024.05.26.12.42.56 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 26 May 2024 12:42:56 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1716752577; x=1717357377; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=9GjOknDfw6CA/cxmtAArnOVpVQknG/Iz5WJ6byoYh9I=; b=fHj1fi10z9afJk+niE4Tr1g69sFWAwxo4M/rzWfvRNDicgudvjBu58iubavjzUQrc6 bQw7XXQ3VBE1xGH4Z0Zeftxs1CprM2BhIMT/XzCfzkrfKtgknXCsQQWybiRfLUGI8AjF MnWUc4X0zS0nec4Rct7ipssmq3aSQKUWov+AOxyTIotmn4YQx+gaIHbJ8mFA+bfWB64W TXQKrqzKgD4lcZZZk2BjbtmdY4QZbKB12uUT9dyxTuZYC+TY2mcqy0RuZh6szfYnNuox y0RGvFRLN5j1Rniwd5/aLO8LHPsiJXip8TxzQ4oyQliWx+R8bM9fls63RfvRg/amRtuo i9UA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1716752577; x=1717357377; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=9GjOknDfw6CA/cxmtAArnOVpVQknG/Iz5WJ6byoYh9I=; b=LZsuo5kUaCiA+hRqHGranEq7+Kb3Xhc0hNj9hYlpMJ60z8FHQRVvemvoP6nsXhcc8F 3JjSxJaO1hQVa9sui92dargV5f47zhVtqBlZ5mdtyGIz6kII66TtRg9odl7tyJ8yGl/M /srnSz7TaJyajWI6WTkCWTackVOM6ih8YW+F6CPmn7ZeLRf+zJQUvdJQ+CNb2Cqmr+z8 hPeYi4zrYEOqDWPEOTwF3aO+1Hdp3T/kou0a5dApk3tgGiuqp3ezWT5hgIRJOOcQcnVW IUaFt2gsv9TfE6JIE+RV8zv4DAdHxPzz+d+nJCDxPzMHGqPX4yPH623Vi22SNcpWC3I6 D1jQ== X-Gm-Message-State: AOJu0Yyzwv9fhrIERnDXS5VF/hf0K0W3p1kESZIL1VR4eRZhYFVZFgHH C7m1aQrpUNWF5iOHkdeX1qnebMshXg30nG1LAZbQa0YcCiJrqYWEUG6OJVPncFz7YXiL4mXP9rC x X-Google-Smtp-Source: AGHT+IEsRGohjHX8Df/j+T2Roo3PFyAPDP27dNMKXytRDC86w5WqyYEKkmdPec4tH354ZHticb4SWg== X-Received: by 2002:a17:902:fa46:b0:1f3:4232:76df with SMTP id d9443c01a7336-1f4487400b4mr66133285ad.36.1716752577046; Sun, 26 May 2024 12:42:57 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: mark.cave-ayland@ilande.co.uk Subject: [PATCH v2 02/37] target/sparc: Rewrite gen_edge Date: Sun, 26 May 2024 12:42:19 -0700 Message-Id: <20240526194254.459395-3-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240526194254.459395-1-richard.henderson@linaro.org> References: <20240526194254.459395-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::636; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x636.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1716752732212100007 Content-Type: text/plain; charset="utf-8" Drop the tables and compute the left and right edges directly. Signed-off-by: Richard Henderson Tested-by: Mark Cave-Ayland --- target/sparc/translate.c | 98 +++++++++++++++------------------------- 1 file changed, 37 insertions(+), 61 deletions(-) diff --git a/target/sparc/translate.c b/target/sparc/translate.c index dca072888a..00c2a11353 100644 --- a/target/sparc/translate.c +++ b/target/sparc/translate.c @@ -3519,11 +3519,10 @@ static bool trans_SDIVX(DisasContext *dc, arg_r_r_r= i *a) } =20 static bool gen_edge(DisasContext *dc, arg_r_r_r *a, - int width, bool cc, bool left) + int width, bool cc, bool little_endian) { - TCGv dst, s1, s2, lo1, lo2; - uint64_t amask, tabl, tabr; - int shift, imask, omask; + TCGv dst, s1, s2, l, r, t, m; + uint64_t amask =3D address_mask_i(dc, -8); =20 dst =3D gen_dest_gpr(dc, a->rd); s1 =3D gen_load_gpr(dc, a->rs1); @@ -3533,75 +3532,52 @@ static bool gen_edge(DisasContext *dc, arg_r_r_r *a, gen_op_subcc(cpu_cc_N, s1, s2); } =20 - /* - * Theory of operation: there are two tables, left and right (not to - * be confused with the left and right versions of the opcode). These - * are indexed by the low 3 bits of the inputs. To make things "easy", - * these tables are loaded into two constants, TABL and TABR below. - * The operation index =3D (input & imask) << shift calculates the ind= ex - * into the constant, while val =3D (table >> index) & omask calculates - * the value we're looking for. - */ + l =3D tcg_temp_new(); + r =3D tcg_temp_new(); + t =3D tcg_temp_new(); + switch (width) { case 8: - imask =3D 0x7; - shift =3D 3; - omask =3D 0xff; - if (left) { - tabl =3D 0x80c0e0f0f8fcfeffULL; - tabr =3D 0xff7f3f1f0f070301ULL; - } else { - tabl =3D 0x0103070f1f3f7fffULL; - tabr =3D 0xfffefcf8f0e0c080ULL; - } + tcg_gen_andi_tl(l, s1, 7); + tcg_gen_andi_tl(r, s2, 7); + tcg_gen_xori_tl(r, r, 7); + m =3D tcg_constant_tl(0xff); break; case 16: - imask =3D 0x6; - shift =3D 1; - omask =3D 0xf; - if (left) { - tabl =3D 0x8cef; - tabr =3D 0xf731; - } else { - tabl =3D 0x137f; - tabr =3D 0xfec8; - } + tcg_gen_extract_tl(l, s1, 1, 2); + tcg_gen_extract_tl(r, s2, 1, 2); + tcg_gen_xori_tl(r, r, 3); + m =3D tcg_constant_tl(0xf); break; case 32: - imask =3D 0x4; - shift =3D 0; - omask =3D 0x3; - if (left) { - tabl =3D (2 << 2) | 3; - tabr =3D (3 << 2) | 1; - } else { - tabl =3D (1 << 2) | 3; - tabr =3D (3 << 2) | 2; - } + tcg_gen_extract_tl(l, s1, 2, 1); + tcg_gen_extract_tl(r, s2, 2, 1); + tcg_gen_xori_tl(r, r, 1); + m =3D tcg_constant_tl(0x3); break; default: abort(); } =20 - lo1 =3D tcg_temp_new(); - lo2 =3D tcg_temp_new(); - tcg_gen_andi_tl(lo1, s1, imask); - tcg_gen_andi_tl(lo2, s2, imask); - tcg_gen_shli_tl(lo1, lo1, shift); - tcg_gen_shli_tl(lo2, lo2, shift); + /* Compute Left Edge */ + if (little_endian) { + tcg_gen_shl_tl(l, m, l); + tcg_gen_and_tl(l, l, m); + } else { + tcg_gen_shr_tl(l, m, l); + } + /* Compute Right Edge */ + if (little_endian) { + tcg_gen_shr_tl(r, m, r); + } else { + tcg_gen_shl_tl(r, m, r); + tcg_gen_and_tl(r, r, m); + } =20 - tcg_gen_shr_tl(lo1, tcg_constant_tl(tabl), lo1); - tcg_gen_shr_tl(lo2, tcg_constant_tl(tabr), lo2); - tcg_gen_andi_tl(lo1, lo1, omask); - tcg_gen_andi_tl(lo2, lo2, omask); - - amask =3D address_mask_i(dc, -8); - tcg_gen_andi_tl(s1, s1, amask); - tcg_gen_andi_tl(s2, s2, amask); - - /* Compute dst =3D (s1 =3D=3D s2 ? lo1 : lo1 & lo2). */ - tcg_gen_and_tl(lo2, lo2, lo1); - tcg_gen_movcond_tl(TCG_COND_EQ, dst, s1, s2, lo1, lo2); + /* Compute dst =3D (s1 =3D=3D s2 under amask ? l : l & r) */ + tcg_gen_xor_tl(t, s1, s2); + tcg_gen_and_tl(r, r, l); + tcg_gen_movcond_tl(TCG_COND_TSTEQ, dst, t, tcg_constant_tl(amask), r, = l); =20 gen_store_gpr(dc, a->rd, dst); return advance_pc(dc); --=20 2.34.1 From nobody Mon Nov 25 08:36:39 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1716752608; cv=none; d=zohomail.com; s=zohoarc; b=ZtzzPV8lht9jbSdOWZ0+io82MmLqCGoQuknl0fpGy1yp+NMAg6MG+HTI9kNzXBdMN+bsPVh6jPMiWJ072NuUCmH5M81aGq8eluovpJl5+dHTAxp/AC2T1j/QppD0FIVPVGl2uCJtxgmdji8544HFnLm904ddhNprcqxbBH0q+sM= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1716752608; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=eYP1yN4ZKgW4BIdLMmHOja0Hfuxd6mArjAtvAgL/GVQ=; b=bEC2rHl/tj9O7QbuJrJMUUHu47nz2gco95E5KvH7LzcpL7UT8XvERhxyLj/5hGNhLoZ+YgE27VEn8WseYmtx+Pidi6vZYBo6ZCqnVcb4B+nf6hYnTLg46oQE1XHJrC3FIfM4yc6oQdI16s1EttIGqLOJUkLEH9RWgA/5/AKXpYc= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1716752608593154.2308246136539; Sun, 26 May 2024 12:43:28 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1sBJln-0008BE-0p; Sun, 26 May 2024 15:43:03 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1sBJll-0008AW-3c for qemu-devel@nongnu.org; Sun, 26 May 2024 15:43:01 -0400 Received: from mail-pl1-x629.google.com ([2607:f8b0:4864:20::629]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1sBJlj-0007cp-G1 for qemu-devel@nongnu.org; Sun, 26 May 2024 15:43:00 -0400 Received: by mail-pl1-x629.google.com with SMTP id d9443c01a7336-1f480624d10so5999215ad.1 for ; Sun, 26 May 2024 12:42:59 -0700 (PDT) Received: from stoup.. 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[174.21.72.5]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-1f46ad93c2esm28165935ad.263.2024.05.26.12.42.57 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 26 May 2024 12:42:57 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1716752578; x=1717357378; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=eYP1yN4ZKgW4BIdLMmHOja0Hfuxd6mArjAtvAgL/GVQ=; b=uT9/Ac/xBKvWqk5vdLKi0wQ1xvlqfWz5uFdWhAGNcJILaeV3OWnKHZ62HJ79zM1+Os UqO2mpHkk5RKxsrBGTKw6NNUChoAqnaY43mUCOpRABebxpG2Y6QTMIAZiZ95f0c2A5bO 2TgWa4Hl3Lzj0t5DCSxQFSadPYONu841DTWHJa+SplZUyAyGHyGzGsKj5xU09t8nduOk YFfol899bSpjo19iBCO9eyzOhpfypCdfr0W57+LXinGwxuAJ83OFTBEOyFeLF+2gt/6I dhGmiWpBEjnMo+x8MWxt7hgF/OxP9CREqKEldXRY313JLz/VRYHh7H97Vxo+RfVSTwBO Sg/Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1716752578; x=1717357378; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=eYP1yN4ZKgW4BIdLMmHOja0Hfuxd6mArjAtvAgL/GVQ=; b=s8m6dPvM+qbwmhbmq51JDQQt4+x67GttF3RWcxeaf2urII8tm5TpQH+56Hnp7Uj6g0 nsWA7Z6g37CtiCM7XeeWyzup6xZZ+J7W30e+TZbaFqDuvZ3RwUC1cDfnh2fkEUyVapFW MwwLaQ4LP9gzXQo4et5AaHMc8KU1cXb8R7dj/Hh8tKmuLW3PiWO4fBFv19W47yDXyuWR r4FGbaAAAifULn0iDubLD4k2HyS8I+JPl0dwhsXpFWtQS1CvNkrRLRYrjqNcv9xZk4vM WIQoXWTnvpTlYzVQLbraQNlej18fP04pNpfvfEDBVMjfEKk+wH4YX0wXwD3cf0TOnnT1 1bEQ== X-Gm-Message-State: AOJu0Yzs3ycF7grMloVwYLZPYLeyzaodlcAaEXm4wp+qCl470c/ruyWf DZrQiYDRc3qdgqG79QXfKmXkn88BtXpvYxKdgV4je5PzGFXptc2k9xtV/E1ac6aRvTLVY+Zw0So O X-Google-Smtp-Source: AGHT+IHdCAXcIOX+JeXzZaxFfgHNay43edgYv3NeaVGqbcSZufY8qBU8aOaPkRryZ+5M1gCB/Wc/gQ== X-Received: by 2002:a17:902:cecd:b0:1f3:35e8:d309 with SMTP id d9443c01a7336-1f4486d9f35mr86120695ad.20.1716752577827; Sun, 26 May 2024 12:42:57 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: mark.cave-ayland@ilande.co.uk Subject: [PATCH v2 03/37] target/sparc: Fix do_dc Date: Sun, 26 May 2024 12:42:20 -0700 Message-Id: <20240526194254.459395-4-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240526194254.459395-1-richard.henderson@linaro.org> References: <20240526194254.459395-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::629; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x629.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1716752609774100003 Content-Type: text/plain; charset="utf-8" Apply DFPREG to compute the register number. Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daud=C3=A9 Tested-by: Mark Cave-Ayland --- target/sparc/translate.c | 1 + 1 file changed, 1 insertion(+) diff --git a/target/sparc/translate.c b/target/sparc/translate.c index 00c2a11353..1eb1a6decf 100644 --- a/target/sparc/translate.c +++ b/target/sparc/translate.c @@ -4253,6 +4253,7 @@ static bool do_dc(DisasContext *dc, int rd, int64_t c) return true; } =20 + rd =3D DFPREG(rd); tcg_gen_movi_i64(cpu_fpr[rd / 2], c); gen_update_fprs_dirty(dc, rd); return advance_pc(dc); --=20 2.34.1 From nobody Mon Nov 25 08:36:39 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1716752732; cv=none; d=zohomail.com; s=zohoarc; b=REwp8NqlxeV2/jiJvP/D0DVJrHu4BoEzXGvuDz58sxfm14I7YnTrfZLXtI8pEpgnoyVPdg8/5ZTKLwW1wNUYYsPKSC385u5p2po4joeQQsKcnLqBPt8TrF8paCT/fqTUritw/Vnrp3W05fcLfdzEkzKn4I6yC9MVDNBwV3fw/pg= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1716752732; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=iPN2ZXnJH67ylasvW5ASBChVEwpUinMe7ale/dDDPYY=; b=Uww2I7w/hGTfv5sP8FrtKhzX6s49GXBPJYEaztR7IaYySG1AfrKdw2isi7Lv5XtAzDb5xqLjhFiQpPxLXI8+dHDDFKKKZvsGB3fxKN/1Jd0/qZNHssPbJ0nQPYeGb0MuRR8CRTRPhdqqgZX7mZ1nK9oyFum4VGwTtL+J6YDdg1Y= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1716752732780983.4382917442763; Sun, 26 May 2024 12:45:32 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1sBJln-0008Bs-MG; Sun, 26 May 2024 15:43:03 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1sBJll-0008Ap-Ov for qemu-devel@nongnu.org; Sun, 26 May 2024 15:43:01 -0400 Received: from mail-pl1-x62f.google.com ([2607:f8b0:4864:20::62f]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1sBJlk-0007d4-7g for qemu-devel@nongnu.org; Sun, 26 May 2024 15:43:01 -0400 Received: by mail-pl1-x62f.google.com with SMTP id d9443c01a7336-1f44b5b9de6so18160385ad.3 for ; Sun, 26 May 2024 12:42:59 -0700 (PDT) Received: from stoup.. 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[174.21.72.5]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-1f46ad93c2esm28165935ad.263.2024.05.26.12.42.58 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 26 May 2024 12:42:58 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1716752579; x=1717357379; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=iPN2ZXnJH67ylasvW5ASBChVEwpUinMe7ale/dDDPYY=; b=OC2N/L3kh37rbQxVLUd8fGeYrjhCmHpKZ911PeMao5+XwAV+O5pH/mcb6q1gmCzzTr veg9WaD8LsG5Mo7bDfsQdu8m4o5t84cEUDGiE8lpH3KJtq/hXHIXX64Cx2yuayXEhocA dulAUg0edLqS3YdV70jtK3h9BJlgTm7zqs9/gpFncZQSPnKTlv/HBQw7jGqyKG5EXnTZ utklhEajMXISha6Cf6ORweQnTUph+BKmOoYuJ1E2XoYO22JgaPJBNM6Rxc0x1tRG6TBJ zVZ7VuDT2j+zb7DzySqHS4qmC9OUmFbvSc3FI4oGkmZYujLLvdFYsByMEXzM+0xWunCB GRlA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1716752579; x=1717357379; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=iPN2ZXnJH67ylasvW5ASBChVEwpUinMe7ale/dDDPYY=; b=uNE2lkQyLnz51HyROpx28JtIL04uHcobdwd1U//g8EEgN3bMVvvUEfusXyDqwcDBD8 gEmuk4jB6bkMuYQnb19Rn5x962L/sAz3nOArjxW5MQIpp1WbU4LKhGvq2KymagpPhIdH aJoNtdPmJcKbt3vtWV1Gc9momXiaDjOlaUzrLyWggwrVC8IOCeQEPUZP31GPO4Az3pFj juWgTQFg+1KdLPsywR6BK7q84sllYzaCDMupssL3j16AQPY8aKHZXvZ72se9clDPJjGI iGLlEYykHz2frQFnzbZ9p2Vw8LMvL++jfoKjBvx2LS2BMxqB5fhnB8zKFQM/tNvYQ+j6 tKdw== X-Gm-Message-State: AOJu0YyzJf6LNdlaqXHUG6pWfbGcgGTrhcgpM85q/e6Vf5NFOIIvY3Uu 6A0gCD4afdZPDLvW04yeFdS62n67UyQmdT8hiXNFRXyY2KQhwypJo/yMqjLEAG87iM04LJClrcE I X-Google-Smtp-Source: AGHT+IGvzHlUqqqOxBpKCROMgnuJzwnE89oFomLBBSJ3s6CesbH/Ck/yvHhQb4Eru7CCpgRBSr7KkQ== X-Received: by 2002:a17:902:c943:b0:1f4:64ba:af9f with SMTP id d9443c01a7336-1f464bab2f7mr53644085ad.48.1716752578869; Sun, 26 May 2024 12:42:58 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: mark.cave-ayland@ilande.co.uk Subject: [PATCH v2 04/37] target/sparc: Fix helper_fmul8ulx16 Date: Sun, 26 May 2024 12:42:21 -0700 Message-Id: <20240526194254.459395-5-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240526194254.459395-1-richard.henderson@linaro.org> References: <20240526194254.459395-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::62f; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1716752734219100019 Content-Type: text/plain; charset="utf-8" This operation returns the high 16 bits of a 24-bit multiply that has been sign-extended to 32 bits. Signed-off-by: Richard Henderson Tested-by: Mark Cave-Ayland --- target/sparc/vis_helper.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/target/sparc/vis_helper.c b/target/sparc/vis_helper.c index f46fcf1f6a..41312deda4 100644 --- a/target/sparc/vis_helper.c +++ b/target/sparc/vis_helper.c @@ -174,10 +174,10 @@ uint64_t helper_fmul8ulx16(uint64_t src1, uint64_t sr= c2) s.ll =3D src1; d.ll =3D src2; =20 - d.VIS_W64(0) =3D do_ms16b(s.VIS_B64(0), d.VIS_SW64(0)); - d.VIS_W64(1) =3D do_ms16b(s.VIS_B64(2), d.VIS_SW64(1)); - d.VIS_W64(2) =3D do_ms16b(s.VIS_B64(4), d.VIS_SW64(2)); - d.VIS_W64(3) =3D do_ms16b(s.VIS_B64(6), d.VIS_SW64(3)); + d.VIS_W64(0) =3D (s.VIS_B64(0) * d.VIS_SW64(0) + 0x8000) >> 16; + d.VIS_W64(1) =3D (s.VIS_B64(2) * d.VIS_SW64(1) + 0x8000) >> 16; + d.VIS_W64(2) =3D (s.VIS_B64(4) * d.VIS_SW64(2) + 0x8000) >> 16; + d.VIS_W64(3) =3D (s.VIS_B64(6) * d.VIS_SW64(3) + 0x8000) >> 16; =20 return d.ll; } --=20 2.34.1 From nobody Mon Nov 25 08:36:39 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1716752732; cv=none; d=zohomail.com; s=zohoarc; b=NGmWwvyN1uIkpgNicZtTO3epvZA6+J7IMC6XAX5vaItUL1Fl0DvvtasJwI18iowYiWlIF6K10ZpaU8NVX/YB5aLRq24FDiYwRbu27Nl26xDti/TcoIhXLnlorniE47DIgDiDXbUeX7GdOlMexEZMwS/d1uU8Gd3JOSo6NRy3gAc= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1716752732; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=L/Kek+OpRexEIhDigfP9w9ns/xyOmoQXE9H2AlFSUfI=; b=TKYXb26CVy5E6bMhBwHeKq3Aa25IQJhVLFuxO3DYNklKbkA5xtI3Yefo/6/bi/pq5Lo05ElTU2GdFdSvCFG4TEr7OlxDUQXwCpb1pZjY8w7gOKjSxIUEVfmHVgwGWqSDCuJNeVcp06bD9mmyWxyNN0/b9kOIH34sWymGlUoUTUY= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1716752732715335.6790713606208; Sun, 26 May 2024 12:45:32 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1sBJlr-0008DG-8J; Sun, 26 May 2024 15:43:07 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1sBJlo-0008CC-8q for qemu-devel@nongnu.org; Sun, 26 May 2024 15:43:04 -0400 Received: from mail-pl1-x636.google.com ([2607:f8b0:4864:20::636]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1sBJll-0007dU-Fy for qemu-devel@nongnu.org; Sun, 26 May 2024 15:43:04 -0400 Received: by mail-pl1-x636.google.com with SMTP id d9443c01a7336-1f4a0050b9aso1325105ad.2 for ; Sun, 26 May 2024 12:43:01 -0700 (PDT) Received: from stoup.. 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[174.21.72.5]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-1f46ad93c2esm28165935ad.263.2024.05.26.12.42.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 26 May 2024 12:42:59 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1716752580; x=1717357380; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=L/Kek+OpRexEIhDigfP9w9ns/xyOmoQXE9H2AlFSUfI=; b=RgA8aguVq5sdD+K0mym2BGJuazTgrNq+btYogslKQ7Eo57MwuRpkTVG7pKPl9FDZHI MK/D86uO0uv6PTX1eze/qm9DP0Yca5lOKb9C5dxAi5yg/cRoTC7G4tsSDIHlB53eoOxD F/Ci/IGSZsZnO7gSd/iGCZXMN+FUvzoxa10afHRFCUTR8glWc7iBkeW4Y1QhZ4gqgXI8 jJVdmuaOLmV47oSuxnVfcIqa+b1YUIupHsxRv2mx7Umxhk6dG10JIFAH0HtBNKQRKByI mg+XcEvYtNGcS/GzFOQm2jEyY+6Zv+rFCzMnAI+wkdAgszBBUCInBsvCVRPz9OP/0rZ8 gVBA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1716752580; x=1717357380; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=L/Kek+OpRexEIhDigfP9w9ns/xyOmoQXE9H2AlFSUfI=; b=AszVaS+21I1uDM08+rM6rSFNYbnzfJooyRvghoNSoBvtDjUeoVTZM1h1w3j9dhMSGj zYZy6KEmmK+habqYnwD4tPP0wLcLVxP+8Jg7HUlN/oChFodzm0OMv7gnrIUR3R1nTTTM NEIXqRY+bzPbbAMsX2ziB4FK1Ufv8F1lv4rh1UzTP0cVWA+mzlg3pJDmyrjXBEZapQDp vcE3pfmRtLb9J0EC5glC2vdUAhhRdTfe6Dl3Y/SWOGy/PQA1UhbPyuqmqiJdB640znW7 fdhYtn1pPYNEVhYlMhYlJdzsK9QiXSz0u0L4EzIp2qLp4P4MYKbuaVuFToXVVduifPAC 5JWQ== X-Gm-Message-State: AOJu0Yx4icED33AMcZkUn8hOPSPuJwdwvGUxyaNj+sX8XagqfXH9fIY3 tB9a6Oosyww/C7cvsCo/E39IGK0U/QpyZcjenVBq2YlOEv0rSfyt/tPsIjJQs63Jz2CajBTp0TA O X-Google-Smtp-Source: AGHT+IF9XTda19mDevpvl+aBScAEbnuucSQmAwRDCA8vnm6w4oFrXx7GHxMIkzkFGjB/EdD1Yfc5Dg== X-Received: by 2002:a17:903:2447:b0:1f2:f8b7:60d4 with SMTP id d9443c01a7336-1f4497daf6cmr87578305ad.52.1716752579740; Sun, 26 May 2024 12:42:59 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: mark.cave-ayland@ilande.co.uk, =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH v2 05/37] target/sparc: Perform DFPREG/QFPREG in decodetree Date: Sun, 26 May 2024 12:42:22 -0700 Message-Id: <20240526194254.459395-6-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240526194254.459395-1-richard.henderson@linaro.org> References: <20240526194254.459395-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::636; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x636.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1716752734237100021 Form the proper register decoding from the start. Because we're removing the translation from the inner-most gen_load_fpr_* and gen_store_fpr_* routines, this must be done for all insns at once. Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Richard Henderson Tested-by: Mark Cave-Ayland --- target/sparc/insns.decode | 220 +++++++++++++++++++++++--------------- target/sparc/translate.c | 39 +++---- 2 files changed, 148 insertions(+), 111 deletions(-) diff --git a/target/sparc/insns.decode b/target/sparc/insns.decode index e2d8a07dc4..02fa505b49 100644 --- a/target/sparc/insns.decode +++ b/target/sparc/insns.decode @@ -26,6 +26,14 @@ CALL 01 i:s30 ## Major Opcode 10 -- integer, floating-point, vis, and system insns. ## =20 +%dfp_rd 25:5 !function=3Dextract_dfpreg +%dfp_rs1 14:5 !function=3Dextract_dfpreg +%dfp_rs2 0:5 !function=3Dextract_dfpreg + +%qfp_rd 25:5 !function=3Dextract_qfpreg +%qfp_rs1 14:5 !function=3Dextract_qfpreg +%qfp_rs2 0:5 !function=3Dextract_qfpreg + &r_r_ri rd rs1 rs2_or_imm imm:bool @n_r_ri .. ..... ...... rs1:5 imm:1 rs2_or_imm:s13 &r_r_ri rd=3D0 @r_r_ri .. rd:5 ...... rs1:5 imm:1 rs2_or_imm:s13 &r_r_ri @@ -37,11 +45,40 @@ CALL 01 i:s30 =20 &r_r_r rd rs1 rs2 @r_r_r .. rd:5 ...... rs1:5 . ........ rs2:5 &r_r_r +@d_r_r .. ..... ...... rs1:5 . ........ rs2:5 \ + &r_r_r rd=3D%dfp_rd +@r_d_d .. rd:5 ...... ..... . ........ ..... \ + &r_r_r rs1=3D%dfp_rs1 rs2=3D%dfp_rs2 +@d_r_d .. ..... ...... rs1:5 . ........ ..... \ + &r_r_r rd=3D%dfp_rd rs2=3D%dfp_rs2 +@d_d_d .. ..... ...... ..... . ........ ..... \ + &r_r_r rd=3D%dfp_rd rs1=3D%dfp_rs1 rs2=3D%dfp_rs2 +@q_q_q .. ..... ...... ..... . ........ ..... \ + &r_r_r rd=3D%qfp_rd rs1=3D%qfp_rs1 rs2=3D%qfp_rs2 +@q_d_d .. ..... ...... ..... . ........ ..... \ + &r_r_r rd=3D%qfp_rd rs1=3D%dfp_rs1 rs2=3D%dfp_rs2 + @r_r_r_swap .. rd:5 ...... rs2:5 . ........ rs1:5 &r_r_r +@d_d_d_swap .. ..... ...... ..... . ........ ..... \ + &r_r_r rd=3D%dfp_rd rs1=3D%dfp_rs2 rs2=3D%dfp_rs1 =20 &r_r rd rs @r_r1 .. rd:5 ...... rs:5 . ........ ..... &r_r @r_r2 .. rd:5 ...... ..... . ........ rs:5 &r_r +@r_d2 .. rd:5 ...... ..... . ........ ..... &r_r rs=3D%dfp_= rs2 +@r_q2 .. rd:5 ...... ..... . ........ ..... &r_r rs=3D%qfp_= rs2 +@d_r2 .. ..... ...... ..... . ........ rs:5 &r_r rd=3D%dfp_= rd +@q_r2 .. ..... ...... ..... . ........ rs:5 &r_r rd=3D%qfp_= rd +@d_d1 .. ..... ...... ..... . ........ ..... \ + &r_r rd=3D%dfp_rd rs=3D%dfp_rs1 +@d_d2 .. ..... ...... ..... . ........ ..... \ + &r_r rd=3D%dfp_rd rs=3D%dfp_rs2 +@d_q2 .. ..... ...... ..... . ........ ..... \ + &r_r rd=3D%dfp_rd rs=3D%qfp_rs2 +@q_q2 .. ..... ...... ..... . ........ ..... \ + &r_r rd=3D%qfp_rd rs=3D%qfp_rs2 +@q_d2 .. ..... ...... ..... . ........ ..... \ + &r_r rd=3D%qfp_rd rs=3D%dfp_rs2 =20 { [ @@ -241,68 +278,78 @@ DONE 10 00000 111110 00000 0 0000000000000 RETRY 10 00001 111110 00000 0 0000000000000 =20 FMOVs 10 ..... 110100 00000 0 0000 0001 ..... @r_r2 -FMOVd 10 ..... 110100 00000 0 0000 0010 ..... @r_r2 -FMOVq 10 ..... 110100 00000 0 0000 0011 ..... @r_r2 +FMOVd 10 ..... 110100 00000 0 0000 0010 ..... @d_d2 +FMOVq 10 ..... 110100 00000 0 0000 0011 ..... @q_q2 FNEGs 10 ..... 110100 00000 0 0000 0101 ..... @r_r2 -FNEGd 10 ..... 110100 00000 0 0000 0110 ..... @r_r2 -FNEGq 10 ..... 110100 00000 0 0000 0111 ..... @r_r2 +FNEGd 10 ..... 110100 00000 0 0000 0110 ..... @d_d2 +FNEGq 10 ..... 110100 00000 0 0000 0111 ..... @q_q2 FABSs 10 ..... 110100 00000 0 0000 1001 ..... @r_r2 -FABSd 10 ..... 110100 00000 0 0000 1010 ..... @r_r2 -FABSq 10 ..... 110100 00000 0 0000 1011 ..... @r_r2 +FABSd 10 ..... 110100 00000 0 0000 1010 ..... @d_d2 +FABSq 10 ..... 110100 00000 0 0000 1011 ..... @q_q2 FSQRTs 10 ..... 110100 00000 0 0010 1001 ..... @r_r2 -FSQRTd 10 ..... 110100 00000 0 0010 1010 ..... @r_r2 -FSQRTq 10 ..... 110100 00000 0 0010 1011 ..... @r_r2 +FSQRTd 10 ..... 110100 00000 0 0010 1010 ..... @d_d2 +FSQRTq 10 ..... 110100 00000 0 0010 1011 ..... @q_q2 FADDs 10 ..... 110100 ..... 0 0100 0001 ..... @r_r_r -FADDd 10 ..... 110100 ..... 0 0100 0010 ..... @r_r_r -FADDq 10 ..... 110100 ..... 0 0100 0011 ..... @r_r_r +FADDd 10 ..... 110100 ..... 0 0100 0010 ..... @d_d_d +FADDq 10 ..... 110100 ..... 0 0100 0011 ..... @q_q_q FSUBs 10 ..... 110100 ..... 0 0100 0101 ..... @r_r_r -FSUBd 10 ..... 110100 ..... 0 0100 0110 ..... @r_r_r -FSUBq 10 ..... 110100 ..... 0 0100 0111 ..... @r_r_r +FSUBd 10 ..... 110100 ..... 0 0100 0110 ..... @d_d_d +FSUBq 10 ..... 110100 ..... 0 0100 0111 ..... @q_q_q FMULs 10 ..... 110100 ..... 0 0100 1001 ..... @r_r_r -FMULd 10 ..... 110100 ..... 0 0100 1010 ..... @r_r_r -FMULq 10 ..... 110100 ..... 0 0100 1011 ..... @r_r_r +FMULd 10 ..... 110100 ..... 0 0100 1010 ..... @d_d_d +FMULq 10 ..... 110100 ..... 0 0100 1011 ..... @q_q_q FDIVs 10 ..... 110100 ..... 0 0100 1101 ..... @r_r_r -FDIVd 10 ..... 110100 ..... 0 0100 1110 ..... @r_r_r -FDIVq 10 ..... 110100 ..... 0 0100 1111 ..... @r_r_r -FsMULd 10 ..... 110100 ..... 0 0110 1001 ..... @r_r_r -FdMULq 10 ..... 110100 ..... 0 0110 1110 ..... @r_r_r +FDIVd 10 ..... 110100 ..... 0 0100 1110 ..... @d_d_d +FDIVq 10 ..... 110100 ..... 0 0100 1111 ..... @q_q_q +FsMULd 10 ..... 110100 ..... 0 0110 1001 ..... @d_r_r +FdMULq 10 ..... 110100 ..... 0 0110 1110 ..... @q_d_d FsTOx 10 ..... 110100 00000 0 1000 0001 ..... @r_r2 -FdTOx 10 ..... 110100 00000 0 1000 0010 ..... @r_r2 -FqTOx 10 ..... 110100 00000 0 1000 0011 ..... @r_r2 +FdTOx 10 ..... 110100 00000 0 1000 0010 ..... @r_d2 +FqTOx 10 ..... 110100 00000 0 1000 0011 ..... @r_q2 FxTOs 10 ..... 110100 00000 0 1000 0100 ..... @r_r2 -FxTOd 10 ..... 110100 00000 0 1000 1000 ..... @r_r2 -FxTOq 10 ..... 110100 00000 0 1000 1100 ..... @r_r2 +FxTOd 10 ..... 110100 00000 0 1000 1000 ..... @d_r2 +FxTOq 10 ..... 110100 00000 0 1000 1100 ..... @q_r2 FiTOs 10 ..... 110100 00000 0 1100 0100 ..... @r_r2 -FdTOs 10 ..... 110100 00000 0 1100 0110 ..... @r_r2 -FqTOs 10 ..... 110100 00000 0 1100 0111 ..... @r_r2 -FiTOd 10 ..... 110100 00000 0 1100 1000 ..... @r_r2 -FsTOd 10 ..... 110100 00000 0 1100 1001 ..... @r_r2 -FqTOd 10 ..... 110100 00000 0 1100 1011 ..... @r_r2 -FiTOq 10 ..... 110100 00000 0 1100 1100 ..... @r_r2 -FsTOq 10 ..... 110100 00000 0 1100 1101 ..... @r_r2 -FdTOq 10 ..... 110100 00000 0 1100 1110 ..... @r_r2 +FdTOs 10 ..... 110100 00000 0 1100 0110 ..... @r_d2 +FqTOs 10 ..... 110100 00000 0 1100 0111 ..... @r_q2 +FiTOd 10 ..... 110100 00000 0 1100 1000 ..... @d_r2 +FsTOd 10 ..... 110100 00000 0 1100 1001 ..... @d_r2 +FqTOd 10 ..... 110100 00000 0 1100 1011 ..... @d_q2 +FiTOq 10 ..... 110100 00000 0 1100 1100 ..... @q_r2 +FsTOq 10 ..... 110100 00000 0 1100 1101 ..... @q_r2 +FdTOq 10 ..... 110100 00000 0 1100 1110 ..... @q_d2 FsTOi 10 ..... 110100 00000 0 1101 0001 ..... @r_r2 -FdTOi 10 ..... 110100 00000 0 1101 0010 ..... @r_r2 -FqTOi 10 ..... 110100 00000 0 1101 0011 ..... @r_r2 +FdTOi 10 ..... 110100 00000 0 1101 0010 ..... @r_d2 +FqTOi 10 ..... 110100 00000 0 1101 0011 ..... @r_q2 =20 FMOVscc 10 rd:5 110101 0 cond:4 1 cc:1 0 000001 rs2:5 -FMOVdcc 10 rd:5 110101 0 cond:4 1 cc:1 0 000010 rs2:5 -FMOVqcc 10 rd:5 110101 0 cond:4 1 cc:1 0 000011 rs2:5 +FMOVdcc 10 ..... 110101 0 cond:4 1 cc:1 0 000010 ..... \ + rd=3D%dfp_rd rs2=3D%dfp_rs2 +FMOVqcc 10 ..... 110101 0 cond:4 1 cc:1 0 000011 ..... \ + rd=3D%qfp_rd rs2=3D%qfp_rs2 =20 FMOVsfcc 10 rd:5 110101 0 cond:4 0 cc:2 000001 rs2:5 -FMOVdfcc 10 rd:5 110101 0 cond:4 0 cc:2 000010 rs2:5 -FMOVqfcc 10 rd:5 110101 0 cond:4 0 cc:2 000011 rs2:5 +FMOVdfcc 10 ..... 110101 0 cond:4 0 cc:2 000010 ..... \ + rd=3D%dfp_rd rs2=3D%dfp_rs2 +FMOVqfcc 10 ..... 110101 0 cond:4 0 cc:2 000011 ..... \ + rd=3D%qfp_rd rs2=3D%qfp_rs2 =20 FMOVRs 10 rd:5 110101 rs1:5 0 cond:3 00101 rs2:5 -FMOVRd 10 rd:5 110101 rs1:5 0 cond:3 00110 rs2:5 -FMOVRq 10 rd:5 110101 rs1:5 0 cond:3 00111 rs2:5 +FMOVRd 10 ..... 110101 rs1:5 0 cond:3 00110 ..... \ + rd=3D%dfp_rd rs2=3D%dfp_rs2 +FMOVRq 10 ..... 110101 rs1:5 0 cond:3 00111 ..... \ + rd=3D%qfp_rd rs2=3D%qfp_rs2 =20 FCMPs 10 000 cc:2 110101 rs1:5 0 0101 0001 rs2:5 -FCMPd 10 000 cc:2 110101 rs1:5 0 0101 0010 rs2:5 -FCMPq 10 000 cc:2 110101 rs1:5 0 0101 0011 rs2:5 +FCMPd 10 000 cc:2 110101 ..... 0 0101 0010 ..... \ + rs1=3D%dfp_rs1 rs2=3D%dfp_rs2 +FCMPq 10 000 cc:2 110101 ..... 0 0101 0011 ..... \ + rs1=3D%qfp_rs1 rs2=3D%qfp_rs2 FCMPEs 10 000 cc:2 110101 rs1:5 0 0101 0101 rs2:5 -FCMPEd 10 000 cc:2 110101 rs1:5 0 0101 0110 rs2:5 -FCMPEq 10 000 cc:2 110101 rs1:5 0 0101 0111 rs2:5 +FCMPEd 10 000 cc:2 110101 ..... 0 0101 0110 ..... \ + rs1=3D%dfp_rs1 rs2=3D%dfp_rs2 +FCMPEq 10 000 cc:2 110101 ..... 0 0101 0111 ..... \ + rs1=3D%qfp_rs1 rs2=3D%qfp_rs2 =20 { [ @@ -328,74 +375,74 @@ FCMPEq 10 000 cc:2 110101 rs1:5 0 0101 0111 rs2= :5 =20 BMASK 10 ..... 110110 ..... 0 0001 1001 ..... @r_r_r =20 - FPCMPLE16 10 ..... 110110 ..... 0 0010 0000 ..... @r_r_r - FPCMPNE16 10 ..... 110110 ..... 0 0010 0010 ..... @r_r_r - FPCMPGT16 10 ..... 110110 ..... 0 0010 1000 ..... @r_r_r - FPCMPEQ16 10 ..... 110110 ..... 0 0010 1010 ..... @r_r_r - FPCMPLE32 10 ..... 110110 ..... 0 0010 0100 ..... @r_r_r - FPCMPNE32 10 ..... 110110 ..... 0 0010 0110 ..... @r_r_r - FPCMPGT32 10 ..... 110110 ..... 0 0010 1100 ..... @r_r_r - FPCMPEQ32 10 ..... 110110 ..... 0 0010 1110 ..... @r_r_r + FPCMPLE16 10 ..... 110110 ..... 0 0010 0000 ..... @r_d_d + FPCMPNE16 10 ..... 110110 ..... 0 0010 0010 ..... @r_d_d + FPCMPGT16 10 ..... 110110 ..... 0 0010 1000 ..... @r_d_d + FPCMPEQ16 10 ..... 110110 ..... 0 0010 1010 ..... @r_d_d + FPCMPLE32 10 ..... 110110 ..... 0 0010 0100 ..... @r_d_d + FPCMPNE32 10 ..... 110110 ..... 0 0010 0110 ..... @r_d_d + FPCMPGT32 10 ..... 110110 ..... 0 0010 1100 ..... @r_d_d + FPCMPEQ32 10 ..... 110110 ..... 0 0010 1110 ..... @r_d_d =20 - FMUL8x16 10 ..... 110110 ..... 0 0011 0001 ..... @r_r_r - FMUL8x16AU 10 ..... 110110 ..... 0 0011 0011 ..... @r_r_r - FMUL8x16AL 10 ..... 110110 ..... 0 0011 0101 ..... @r_r_r - FMUL8SUx16 10 ..... 110110 ..... 0 0011 0110 ..... @r_r_r - FMUL8ULx16 10 ..... 110110 ..... 0 0011 0111 ..... @r_r_r - FMULD8SUx16 10 ..... 110110 ..... 0 0011 1000 ..... @r_r_r - FMULD8ULx16 10 ..... 110110 ..... 0 0011 1001 ..... @r_r_r - FPACK32 10 ..... 110110 ..... 0 0011 1010 ..... @r_r_r - FPACK16 10 ..... 110110 00000 0 0011 1011 ..... @r_r2 - FPACKFIX 10 ..... 110110 00000 0 0011 1101 ..... @r_r2 - PDIST 10 ..... 110110 ..... 0 0011 1110 ..... @r_r_r + FMUL8x16 10 ..... 110110 ..... 0 0011 0001 ..... @d_r_d + FMUL8x16AU 10 ..... 110110 ..... 0 0011 0011 ..... @d_r_r + FMUL8x16AL 10 ..... 110110 ..... 0 0011 0101 ..... @d_r_r + FMUL8SUx16 10 ..... 110110 ..... 0 0011 0110 ..... @d_d_d + FMUL8ULx16 10 ..... 110110 ..... 0 0011 0111 ..... @d_d_d + FMULD8SUx16 10 ..... 110110 ..... 0 0011 1000 ..... @d_r_r + FMULD8ULx16 10 ..... 110110 ..... 0 0011 1001 ..... @d_r_r + FPACK32 10 ..... 110110 ..... 0 0011 1010 ..... @d_d_d + FPACK16 10 ..... 110110 00000 0 0011 1011 ..... @r_d2 + FPACKFIX 10 ..... 110110 00000 0 0011 1101 ..... @r_d2 + PDIST 10 ..... 110110 ..... 0 0011 1110 ..... @d_d_d =20 - FALIGNDATAg 10 ..... 110110 ..... 0 0100 1000 ..... @r_r_r - FPMERGE 10 ..... 110110 ..... 0 0100 1011 ..... @r_r_r - BSHUFFLE 10 ..... 110110 ..... 0 0100 1100 ..... @r_r_r - FEXPAND 10 ..... 110110 00000 0 0100 1101 ..... @r_r2 + FALIGNDATAg 10 ..... 110110 ..... 0 0100 1000 ..... @d_d_d + FPMERGE 10 ..... 110110 ..... 0 0100 1011 ..... @d_r_r + BSHUFFLE 10 ..... 110110 ..... 0 0100 1100 ..... @d_d_d + FEXPAND 10 ..... 110110 00000 0 0100 1101 ..... @d_r2 =20 - FSRCd 10 ..... 110110 ..... 0 0111 0100 00000 @r_r1 # FSRC1d + FSRCd 10 ..... 110110 ..... 0 0111 0100 00000 @d_d1 # FSRC1d FSRCs 10 ..... 110110 ..... 0 0111 0101 00000 @r_r1 # FSRC1s - FSRCd 10 ..... 110110 00000 0 0111 1000 ..... @r_r2 # FSRC2d + FSRCd 10 ..... 110110 00000 0 0111 1000 ..... @d_d2 # FSRC2d FSRCs 10 ..... 110110 00000 0 0111 1001 ..... @r_r2 # FSRC2s - FNOTd 10 ..... 110110 ..... 0 0110 1010 00000 @r_r1 # FNOT1d + FNOTd 10 ..... 110110 ..... 0 0110 1010 00000 @d_d1 # FNOT1d FNOTs 10 ..... 110110 ..... 0 0110 1011 00000 @r_r1 # FNOT1s - FNOTd 10 ..... 110110 00000 0 0110 0110 ..... @r_r2 # FNOT2d + FNOTd 10 ..... 110110 00000 0 0110 0110 ..... @d_d2 # FNOT2d FNOTs 10 ..... 110110 00000 0 0110 0111 ..... @r_r2 # FNOT2s =20 - FPADD16 10 ..... 110110 ..... 0 0101 0000 ..... @r_r_r + FPADD16 10 ..... 110110 ..... 0 0101 0000 ..... @d_d_d FPADD16s 10 ..... 110110 ..... 0 0101 0001 ..... @r_r_r - FPADD32 10 ..... 110110 ..... 0 0101 0010 ..... @r_r_r + FPADD32 10 ..... 110110 ..... 0 0101 0010 ..... @d_d_d FPADD32s 10 ..... 110110 ..... 0 0101 0011 ..... @r_r_r - FPSUB16 10 ..... 110110 ..... 0 0101 0100 ..... @r_r_r + FPSUB16 10 ..... 110110 ..... 0 0101 0100 ..... @d_d_d FPSUB16s 10 ..... 110110 ..... 0 0101 0101 ..... @r_r_r - FPSUB32 10 ..... 110110 ..... 0 0101 0110 ..... @r_r_r + FPSUB32 10 ..... 110110 ..... 0 0101 0110 ..... @d_d_d FPSUB32s 10 ..... 110110 ..... 0 0101 0111 ..... @r_r_r =20 - FNORd 10 ..... 110110 ..... 0 0110 0010 ..... @r_r_r + FNORd 10 ..... 110110 ..... 0 0110 0010 ..... @d_d_d FNORs 10 ..... 110110 ..... 0 0110 0011 ..... @r_r_r - FANDNOTd 10 ..... 110110 ..... 0 0110 0100 ..... @r_r_r # FAND= NOT2d + FANDNOTd 10 ..... 110110 ..... 0 0110 0100 ..... @d_d_d # FAND= NOT2d FANDNOTs 10 ..... 110110 ..... 0 0110 0101 ..... @r_r_r # FAND= NOT2s - FANDNOTd 10 ..... 110110 ..... 0 0110 1000 ..... @r_r_r_swap # .= .. 1d + FANDNOTd 10 ..... 110110 ..... 0 0110 1000 ..... @d_d_d_swap # .= .. 1d FANDNOTs 10 ..... 110110 ..... 0 0110 1001 ..... @r_r_r_swap # .= .. 1s - FXORd 10 ..... 110110 ..... 0 0110 1100 ..... @r_r_r + FXORd 10 ..... 110110 ..... 0 0110 1100 ..... @d_d_d FXORs 10 ..... 110110 ..... 0 0110 1101 ..... @r_r_r - FNANDd 10 ..... 110110 ..... 0 0110 1110 ..... @r_r_r + FNANDd 10 ..... 110110 ..... 0 0110 1110 ..... @d_d_d FNANDs 10 ..... 110110 ..... 0 0110 1111 ..... @r_r_r - FANDd 10 ..... 110110 ..... 0 0111 0000 ..... @r_r_r + FANDd 10 ..... 110110 ..... 0 0111 0000 ..... @d_d_d FANDs 10 ..... 110110 ..... 0 0111 0001 ..... @r_r_r - FXNORd 10 ..... 110110 ..... 0 0111 0010 ..... @r_r_r + FXNORd 10 ..... 110110 ..... 0 0111 0010 ..... @d_d_d FXNORs 10 ..... 110110 ..... 0 0111 0011 ..... @r_r_r - FORNOTd 10 ..... 110110 ..... 0 0111 0110 ..... @r_r_r # FOR= NOT2d + FORNOTd 10 ..... 110110 ..... 0 0111 0110 ..... @d_d_d # FOR= NOT2d FORNOTs 10 ..... 110110 ..... 0 0111 0111 ..... @r_r_r # FOR= NOT2s - FORNOTd 10 ..... 110110 ..... 0 0111 1010 ..... @r_r_r_swap # .= .. 1d + FORNOTd 10 ..... 110110 ..... 0 0111 1010 ..... @d_d_d_swap # .= .. 1d FORNOTs 10 ..... 110110 ..... 0 0111 1011 ..... @r_r_r_swap # .= .. 1s - FORd 10 ..... 110110 ..... 0 0111 1100 ..... @r_r_r + FORd 10 ..... 110110 ..... 0 0111 1100 ..... @d_d_d FORs 10 ..... 110110 ..... 0 0111 1101 ..... @r_r_r =20 - FZEROd 10 rd:5 110110 00000 0 0110 0000 00000 + FZEROd 10 ..... 110110 00000 0 0110 0000 00000 rd=3D%dfp_rd FZEROs 10 rd:5 110110 00000 0 0110 0001 00000 - FONEd 10 rd:5 110110 00000 0 0111 1110 00000 + FONEd 10 ..... 110110 00000 0 0111 1110 00000 rd=3D%dfp_rd FONEs 10 rd:5 110110 00000 0 0111 1111 00000 ] NCP 10 ----- 110110 ----- --------- ----- # v8 CPop1 @@ -407,9 +454,6 @@ NCP 10 ----- 110111 ----- --------- ----- = # v8 CPop2 ## Major Opcode 11 -- load and store instructions ## =20 -%dfp_rd 25:5 !function=3Dextract_dfpreg -%qfp_rd 25:5 !function=3Dextract_qfpreg - &r_r_ri_asi rd rs1 rs2_or_imm asi imm:bool @r_r_ri_na .. rd:5 ...... rs1:5 imm:1 rs2_or_imm:s13 &r_r_ri_asi asi= =3D-1 @d_r_ri_na .. ..... ...... rs1:5 imm:1 rs2_or_imm:s13 \ diff --git a/target/sparc/translate.c b/target/sparc/translate.c index 1eb1a6decf..f3c52c7c48 100644 --- a/target/sparc/translate.c +++ b/target/sparc/translate.c @@ -190,14 +190,6 @@ typedef struct DisasContext { #define GET_FIELDs(x,a,b) sign_extend (GET_FIELD(x,a,b), (b) - (a) + 1) #define GET_FIELD_SPs(x,a,b) sign_extend (GET_FIELD_SP(x,a,b), ((b) - (a) = + 1)) =20 -#ifdef TARGET_SPARC64 -#define DFPREG(r) (((r & 1) << 5) | (r & 0x1e)) -#define QFPREG(r) (((r & 1) << 5) | (r & 0x1c)) -#else -#define DFPREG(r) (r & 0x1e) -#define QFPREG(r) (r & 0x1c) -#endif - #define UA2005_HTRAP_MASK 0xff #define V8_TRAP_MASK 0x7f =20 @@ -240,34 +232,30 @@ static void gen_store_fpr_F(DisasContext *dc, unsigne= d int dst, TCGv_i32 v) =20 static TCGv_i64 gen_load_fpr_D(DisasContext *dc, unsigned int src) { - src =3D DFPREG(src); return cpu_fpr[src / 2]; } =20 static void gen_store_fpr_D(DisasContext *dc, unsigned int dst, TCGv_i64 v) { - dst =3D DFPREG(dst); tcg_gen_mov_i64(cpu_fpr[dst / 2], v); gen_update_fprs_dirty(dc, dst); } =20 static TCGv_i64 gen_dest_fpr_D(DisasContext *dc, unsigned int dst) { - return cpu_fpr[DFPREG(dst) / 2]; + return cpu_fpr[dst / 2]; } =20 static TCGv_i128 gen_load_fpr_Q(DisasContext *dc, unsigned int src) { TCGv_i128 ret =3D tcg_temp_new_i128(); =20 - src =3D QFPREG(src); tcg_gen_concat_i64_i128(ret, cpu_fpr[src / 2 + 1], cpu_fpr[src / 2]); return ret; } =20 static void gen_store_fpr_Q(DisasContext *dc, unsigned int dst, TCGv_i128 = v) { - dst =3D DFPREG(dst); tcg_gen_extr_i128_i64(cpu_fpr[dst / 2 + 1], cpu_fpr[dst / 2], v); gen_update_fprs_dirty(dc, dst); } @@ -2045,16 +2033,14 @@ static void gen_fmovd(DisasContext *dc, DisasCompar= e *cmp, int rd, int rs) static void gen_fmovq(DisasContext *dc, DisasCompare *cmp, int rd, int rs) { #ifdef TARGET_SPARC64 - int qd =3D QFPREG(rd); - int qs =3D QFPREG(rs); TCGv c2 =3D tcg_constant_tl(cmp->c2); =20 - tcg_gen_movcond_i64(cmp->cond, cpu_fpr[qd / 2], cmp->c1, c2, - cpu_fpr[qs / 2], cpu_fpr[qd / 2]); - tcg_gen_movcond_i64(cmp->cond, cpu_fpr[qd / 2 + 1], cmp->c1, c2, - cpu_fpr[qs / 2 + 1], cpu_fpr[qd / 2 + 1]); + tcg_gen_movcond_i64(cmp->cond, cpu_fpr[rd / 2], cmp->c1, c2, + cpu_fpr[rs / 2], cpu_fpr[rd / 2]); + tcg_gen_movcond_i64(cmp->cond, cpu_fpr[rd / 2 + 1], cmp->c1, c2, + cpu_fpr[rs / 2 + 1], cpu_fpr[rd / 2 + 1]); =20 - gen_update_fprs_dirty(dc, qd); + gen_update_fprs_dirty(dc, rd); #else qemu_build_not_reached(); #endif @@ -2086,12 +2072,20 @@ static void gen_load_trap_state_at_tl(TCGv_ptr r_ts= ptr) =20 static int extract_dfpreg(DisasContext *dc, int x) { - return DFPREG(x); + int r =3D x & 0x1e; +#ifdef TARGET_SPARC64 + r |=3D (x & 1) << 5; +#endif + return r; } =20 static int extract_qfpreg(DisasContext *dc, int x) { - return QFPREG(x); + int r =3D x & 0x1c; +#ifdef TARGET_SPARC64 + r |=3D (x & 1) << 5; +#endif + return r; } =20 /* Include the auto-generated decoder. */ @@ -4253,7 +4247,6 @@ static bool do_dc(DisasContext *dc, int rd, int64_t c) return true; } =20 - rd =3D DFPREG(rd); tcg_gen_movi_i64(cpu_fpr[rd / 2], c); gen_update_fprs_dirty(dc, rd); return advance_pc(dc); --=20 2.34.1 From nobody Mon Nov 25 08:36:39 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1716752732; cv=none; d=zohomail.com; s=zohoarc; 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[174.21.72.5]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-1f46ad93c2esm28165935ad.263.2024.05.26.12.42.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 26 May 2024 12:43:00 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1716752580; x=1717357380; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=Fljjc+vgV8n9jaU2H17cE0qlx4ZtzSc/592LQHPcA70=; b=S1bNyqfqGeg9NlnJTHPOq4n9WRZX84kdeEiYcFJ0MemjlMxk6JV/vCugv2XiHjdAPx AqRYBkK1+mdEGjY0cYWxDMZt/XieaZidyGnTmZL8uNqioljgwYKVquQNSDwsLcNTAikz 22P4HfQW7Qj7RQ9w2+/r7ve0VMsgT3IgkM7oxidtlTv0llu7mhr3Dfvb8C+oZg/FmJLI MqhOBqKgE3DSesFcdRdRpouCiowCczGniuSrUW/n4ZzWhFD4BRb9T772HUdd5Qnl1pIp /dF3g0RP0+RG1soVxV1Z4kEy/pvMxUw0MDRa9y7cM8I8R4gGEXNzDKcHo1DG+eU//yUt 8Qcw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1716752580; x=1717357380; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=Fljjc+vgV8n9jaU2H17cE0qlx4ZtzSc/592LQHPcA70=; b=hY5h9S23+3l2E0luFZDt0/7Pb+DuBOH++DRom8rqV/tI55GsDQJbv2L35J32h9+YtZ 6QJla/NhZ/Zd+hpfrjCRAEQxTMEFb8AvH7YLfFUs6Rn+TkTBXa65mrwhqEtVJjv3B0lA E6W44AmO6JPEO9i/zwn+z4NPu6oTP2AojH4BsFiZALnxfGhK5RUk6N79qzG2Nr8bCCWK uOg06Su0kztktbH53RzCMzqTx8koLiIfVEzNJuJFJr9ECZ+vLARkGzEpEr454W4ha27z ehifJ9Et96IN38uYybLQkkqzBtO9OMLpljuD/nft4SRCqruoDfLfRkoPWxDqbTIAKodf +fSQ== X-Gm-Message-State: AOJu0YwcAjCzv1lTgrQg34wB4z6axTpVU4eWuhF4OoGsJmf1e8lt6JII IEiBiADAMYpzIBi/Kcap8E8YVcbazS1nzFoYT9kceuuuFsNI3C+gRa9cilrSlJN3vT6bHDbTgzE 0 X-Google-Smtp-Source: AGHT+IEWd9dYp8/ZrRJTdG9KpyZQG3cP9ywbsIYY8U9KHeYkRz2LId/I19luPJdtSMrTQFgP2pNIxw== X-Received: by 2002:a17:903:189:b0:1f4:6970:b70 with SMTP id d9443c01a7336-1f469701579mr64319505ad.32.1716752580523; Sun, 26 May 2024 12:43:00 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: mark.cave-ayland@ilande.co.uk, =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH v2 06/37] target/sparc: Remove gen_dest_fpr_D Date: Sun, 26 May 2024 12:42:23 -0700 Message-Id: <20240526194254.459395-7-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240526194254.459395-1-richard.henderson@linaro.org> References: <20240526194254.459395-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::629; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x629.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1716752732201100006 Replace with tcg_temp_new_i64. Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Richard Henderson Tested-by: Mark Cave-Ayland --- target/sparc/translate.c | 27 +++++++++++---------------- 1 file changed, 11 insertions(+), 16 deletions(-) diff --git a/target/sparc/translate.c b/target/sparc/translate.c index f3c52c7c48..750a3e6554 100644 --- a/target/sparc/translate.c +++ b/target/sparc/translate.c @@ -241,11 +241,6 @@ static void gen_store_fpr_D(DisasContext *dc, unsigned= int dst, TCGv_i64 v) gen_update_fprs_dirty(dc, dst); } =20 -static TCGv_i64 gen_dest_fpr_D(DisasContext *dc, unsigned int dst) -{ - return cpu_fpr[dst / 2]; -} - static TCGv_i128 gen_load_fpr_Q(DisasContext *dc, unsigned int src) { TCGv_i128 ret =3D tcg_temp_new_i128(); @@ -2020,7 +2015,7 @@ static void gen_fmovs(DisasContext *dc, DisasCompare = *cmp, int rd, int rs) static void gen_fmovd(DisasContext *dc, DisasCompare *cmp, int rd, int rs) { #ifdef TARGET_SPARC64 - TCGv_i64 dst =3D gen_dest_fpr_D(dc, rd); + TCGv_i64 dst =3D tcg_temp_new_i64(); tcg_gen_movcond_i64(cmp->cond, dst, cmp->c1, tcg_constant_tl(cmp->c2), gen_load_fpr_D(dc, rs), gen_load_fpr_D(dc, rd)); @@ -4345,7 +4340,7 @@ static bool do_dd(DisasContext *dc, arg_r_r *a, return true; } =20 - dst =3D gen_dest_fpr_D(dc, a->rd); + dst =3D tcg_temp_new_i64(); src =3D gen_load_fpr_D(dc, a->rs); func(dst, src); gen_store_fpr_D(dc, a->rd, dst); @@ -4367,7 +4362,7 @@ static bool do_env_dd(DisasContext *dc, arg_r_r *a, return true; } =20 - dst =3D gen_dest_fpr_D(dc, a->rd); + dst =3D tcg_temp_new_i64(); src =3D gen_load_fpr_D(dc, a->rs); func(dst, tcg_env, src); gen_store_fpr_D(dc, a->rd, dst); @@ -4407,7 +4402,7 @@ static bool do_env_df(DisasContext *dc, arg_r_r *a, return true; } =20 - dst =3D gen_dest_fpr_D(dc, a->rd); + dst =3D tcg_temp_new_i64(); src =3D gen_load_fpr_F(dc, a->rs); func(dst, tcg_env, src); gen_store_fpr_D(dc, a->rd, dst); @@ -4498,7 +4493,7 @@ static bool do_env_dq(DisasContext *dc, arg_r_r *a, } =20 src =3D gen_load_fpr_Q(dc, a->rs); - dst =3D gen_dest_fpr_D(dc, a->rd); + dst =3D tcg_temp_new_i64(); func(dst, tcg_env, src); gen_store_fpr_D(dc, a->rd, dst); return advance_pc(dc); @@ -4613,7 +4608,7 @@ static bool do_dff(DisasContext *dc, arg_r_r_r *a, return true; } =20 - dst =3D gen_dest_fpr_D(dc, a->rd); + dst =3D tcg_temp_new_i64(); src1 =3D gen_load_fpr_F(dc, a->rs1); src2 =3D gen_load_fpr_F(dc, a->rs2); func(dst, src1, src2); @@ -4637,7 +4632,7 @@ static bool do_dfd(DisasContext *dc, arg_r_r_r *a, return true; } =20 - dst =3D gen_dest_fpr_D(dc, a->rd); + dst =3D tcg_temp_new_i64(); src1 =3D gen_load_fpr_F(dc, a->rs1); src2 =3D gen_load_fpr_D(dc, a->rs2); func(dst, src1, src2); @@ -4656,7 +4651,7 @@ static bool do_ddd(DisasContext *dc, arg_r_r_r *a, return true; } =20 - dst =3D gen_dest_fpr_D(dc, a->rd); + dst =3D tcg_temp_new_i64(); src1 =3D gen_load_fpr_D(dc, a->rs1); src2 =3D gen_load_fpr_D(dc, a->rs2); func(dst, src1, src2); @@ -4721,7 +4716,7 @@ static bool do_env_ddd(DisasContext *dc, arg_r_r_r *a, return true; } =20 - dst =3D gen_dest_fpr_D(dc, a->rd); + dst =3D tcg_temp_new_i64(); src1 =3D gen_load_fpr_D(dc, a->rs1); src2 =3D gen_load_fpr_D(dc, a->rs2); func(dst, tcg_env, src1, src2); @@ -4746,7 +4741,7 @@ static bool trans_FsMULd(DisasContext *dc, arg_r_r_r = *a) return raise_unimpfpop(dc); } =20 - dst =3D gen_dest_fpr_D(dc, a->rd); + dst =3D tcg_temp_new_i64(); src1 =3D gen_load_fpr_F(dc, a->rs1); src2 =3D gen_load_fpr_F(dc, a->rs2); gen_helper_fsmuld(dst, tcg_env, src1, src2); @@ -4763,7 +4758,7 @@ static bool do_dddd(DisasContext *dc, arg_r_r_r *a, return true; } =20 - dst =3D gen_dest_fpr_D(dc, a->rd); + dst =3D tcg_temp_new_i64(); src0 =3D gen_load_fpr_D(dc, a->rd); src1 =3D gen_load_fpr_D(dc, a->rs1); src2 =3D gen_load_fpr_D(dc, a->rs2); --=20 2.34.1 From nobody Mon Nov 25 08:36:39 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; 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[174.21.72.5]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-1f46ad93c2esm28165935ad.263.2024.05.26.12.43.00 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 26 May 2024 12:43:00 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1716752581; x=1717357381; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=XV0zqgdiizZid+l8CktjOn6UyrHM7Afq3vRi3rtAjaU=; b=vSFoAkvijZ6el7vOnkYi+oqvKA5Ih772P++mG9hz4Gzc7P4P+vXfl7egthVGvcqQCD GklbOJGt3TxFy9dk1Ioqmzwf8BcETdHY2R+bwJSG8D/e2fKEtD6b+FRyiyYkCYYrMmpk 6VMogoz6hypg+XL3s3fKZMDdvPqTAHfEsF4+ajDhr3PeiiNEzl5DNf5u+PWbzgdGAqwq O5SpiS4vP/Y4vdPGGlfW4PQd0PWQxW5XVP7kg2jEC58HBCtF7+QP2SF3Oznef9HWIKE4 qefsDWUIoq6f3e8l8GLZDr96U3oNIkdMMJHPlzaY8+5wg9gZHYhhdjJxI2+HU5xGF1xe NxwQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1716752581; x=1717357381; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=XV0zqgdiizZid+l8CktjOn6UyrHM7Afq3vRi3rtAjaU=; b=O4qIbbICIQJwALlbdI2HAczMh9LQ6BvFwFgEBfpepenkZ0ZbRDdRdqbeqfYMaripEj m9sjnSLo+OHTwGaweUWc+t9WeqSyJ7YjikyrdoxyZmflvtOWLDn2IEydZv+sYKI2I/iu Hl922G2GrsQryVr7S37FqrU/i8Y7PqalKayNmgj263MHu51U87awTME3pnb4oGwd7W50 7kJ4SC8sbgnrL9H7Pu44E2fo9jYNRUXVadAf6WQre0qtFkorMvem1SxHoI3T21fgwc0d QRVy1rxPLmciZHG2WK0EnXmiw3epfJZA39iHgtoRvKxBW3BqLcAfjtxLiJsuFWszj8bP NfHA== X-Gm-Message-State: AOJu0YzjF1Q3B5WOkEpqnwVJhVva2rs3jhDMsBW/Ls+khGeT6v1+ie4m YbHFJxpn02h9Rh+nMxK7CXAQAg5AbYsZmjSCkSEydLc2EJSTObYEM4a/VrCsgAI1xp41q4FnqTA 3 X-Google-Smtp-Source: AGHT+IE0o5X7oGyp+tjO1OwH/YtrQ4OnKpK9Gd1cj0dGawbIhkrHUwUt5TxCw6aaCUz40fzQCnygNw== X-Received: by 2002:a17:902:d486:b0:1f3:1cb9:47a0 with SMTP id d9443c01a7336-1f44870a07cmr94766695ad.27.1716752581249; Sun, 26 May 2024 12:43:01 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: mark.cave-ayland@ilande.co.uk Subject: [PATCH v2 07/37] target/sparc: Remove cpu_fpr[] Date: Sun, 26 May 2024 12:42:24 -0700 Message-Id: <20240526194254.459395-8-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240526194254.459395-1-richard.henderson@linaro.org> References: <20240526194254.459395-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::62a; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1716752732258100011 Content-Type: text/plain; charset="utf-8" Use explicit loads and stores to env instead. Signed-off-by: Richard Henderson Tested-by: Mark Cave-Ayland --- target/sparc/translate.c | 158 +++++++++++++++++++++------------------ 1 file changed, 84 insertions(+), 74 deletions(-) diff --git a/target/sparc/translate.c b/target/sparc/translate.c index 750a3e6554..362e88de18 100644 --- a/target/sparc/translate.c +++ b/target/sparc/translate.c @@ -123,8 +123,7 @@ static TCGv cpu_gsr; #define cpu_xcc_C ({ qemu_build_not_reached(); NULL; }) #endif =20 -/* Floating point registers */ -static TCGv_i64 cpu_fpr[TARGET_DPREGS]; +/* Floating point comparison registers */ static TCGv_i32 cpu_fcc[TARGET_FCCREGS]; =20 #define env_field_offsetof(X) offsetof(CPUSPARCState, X) @@ -209,50 +208,72 @@ static void gen_update_fprs_dirty(DisasContext *dc, i= nt rd) } =20 /* floating point registers moves */ + +static int gen_offset_fpr_F(unsigned int reg) +{ + int ret; + + tcg_debug_assert(reg < 32); + ret=3D offsetof(CPUSPARCState, fpr[reg / 2]); + if (reg & 1) { + ret +=3D offsetof(CPU_DoubleU, l.lower); + } else { + ret +=3D offsetof(CPU_DoubleU, l.upper); + } + return ret; +} + static TCGv_i32 gen_load_fpr_F(DisasContext *dc, unsigned int src) { TCGv_i32 ret =3D tcg_temp_new_i32(); - if (src & 1) { - tcg_gen_extrl_i64_i32(ret, cpu_fpr[src / 2]); - } else { - tcg_gen_extrh_i64_i32(ret, cpu_fpr[src / 2]); - } + tcg_gen_ld_i32(ret, tcg_env, gen_offset_fpr_F(src)); return ret; } =20 static void gen_store_fpr_F(DisasContext *dc, unsigned int dst, TCGv_i32 v) { - TCGv_i64 t =3D tcg_temp_new_i64(); - - tcg_gen_extu_i32_i64(t, v); - tcg_gen_deposit_i64(cpu_fpr[dst / 2], cpu_fpr[dst / 2], t, - (dst & 1 ? 0 : 32), 32); + tcg_gen_st_i32(v, tcg_env, gen_offset_fpr_F(dst)); gen_update_fprs_dirty(dc, dst); } =20 +static int gen_offset_fpr_D(unsigned int reg) +{ + tcg_debug_assert(reg < 64); + tcg_debug_assert(reg % 2 =3D=3D 0); + return offsetof(CPUSPARCState, fpr[reg / 2]); +} + static TCGv_i64 gen_load_fpr_D(DisasContext *dc, unsigned int src) { - return cpu_fpr[src / 2]; + TCGv_i64 ret =3D tcg_temp_new_i64(); + tcg_gen_ld_i64(ret, tcg_env, gen_offset_fpr_D(src)); + return ret; } =20 static void gen_store_fpr_D(DisasContext *dc, unsigned int dst, TCGv_i64 v) { - tcg_gen_mov_i64(cpu_fpr[dst / 2], v); + tcg_gen_st_i64(v, tcg_env, gen_offset_fpr_D(dst)); gen_update_fprs_dirty(dc, dst); } =20 static TCGv_i128 gen_load_fpr_Q(DisasContext *dc, unsigned int src) { TCGv_i128 ret =3D tcg_temp_new_i128(); + TCGv_i64 h =3D gen_load_fpr_D(dc, src); + TCGv_i64 l =3D gen_load_fpr_D(dc, src + 2); =20 - tcg_gen_concat_i64_i128(ret, cpu_fpr[src / 2 + 1], cpu_fpr[src / 2]); + tcg_gen_concat_i64_i128(ret, l, h); return ret; } =20 static void gen_store_fpr_Q(DisasContext *dc, unsigned int dst, TCGv_i128 = v) { - tcg_gen_extr_i128_i64(cpu_fpr[dst / 2 + 1], cpu_fpr[dst / 2], v); - gen_update_fprs_dirty(dc, dst); + TCGv_i64 h =3D tcg_temp_new_i64(); + TCGv_i64 l =3D tcg_temp_new_i64(); + + tcg_gen_extr_i128_i64(l, h, v); + gen_store_fpr_D(dc, dst, h); + gen_store_fpr_D(dc, dst + 2, l); } =20 /* moves */ @@ -1610,7 +1631,7 @@ static void gen_ldf_asi(DisasContext *dc, DisasASI *d= a, MemOp orig_size, MemOp memop =3D da->memop; MemOp size =3D memop & MO_SIZE; TCGv_i32 d32; - TCGv_i64 d64; + TCGv_i64 d64, l64; TCGv addr_tmp; =20 /* TODO: Use 128-bit load/store below. */ @@ -1632,16 +1653,20 @@ static void gen_ldf_asi(DisasContext *dc, DisasASI = *da, MemOp orig_size, break; =20 case MO_64: - tcg_gen_qemu_ld_i64(cpu_fpr[rd / 2], addr, da->mem_idx, memop); + d64 =3D tcg_temp_new_i64(); + tcg_gen_qemu_ld_i64(d64, addr, da->mem_idx, memop); + gen_store_fpr_D(dc, rd, d64); break; =20 case MO_128: d64 =3D tcg_temp_new_i64(); + l64 =3D tcg_temp_new_i64(); tcg_gen_qemu_ld_i64(d64, addr, da->mem_idx, memop); addr_tmp =3D tcg_temp_new(); tcg_gen_addi_tl(addr_tmp, addr, 8); - tcg_gen_qemu_ld_i64(cpu_fpr[rd / 2 + 1], addr_tmp, da->mem_idx= , memop); - tcg_gen_mov_i64(cpu_fpr[rd / 2], d64); + tcg_gen_qemu_ld_i64(l64, addr_tmp, da->mem_idx, memop); + gen_store_fpr_D(dc, rd, d64); + gen_store_fpr_D(dc, rd + 2, l64); break; default: g_assert_not_reached(); @@ -1653,9 +1678,11 @@ static void gen_ldf_asi(DisasContext *dc, DisasASI *= da, MemOp orig_size, if (orig_size =3D=3D MO_64 && (rd & 7) =3D=3D 0) { /* The first operation checks required alignment. */ addr_tmp =3D tcg_temp_new(); + d64 =3D tcg_temp_new_i64(); for (int i =3D 0; ; ++i) { - tcg_gen_qemu_ld_i64(cpu_fpr[rd / 2 + i], addr, da->mem_idx, + tcg_gen_qemu_ld_i64(d64, addr, da->mem_idx, memop | (i =3D=3D 0 ? MO_ALIGN_64 : 0)= ); + gen_store_fpr_D(dc, rd + 2 * i, d64); if (i =3D=3D 7) { break; } @@ -1670,8 +1697,9 @@ static void gen_ldf_asi(DisasContext *dc, DisasASI *d= a, MemOp orig_size, case GET_ASI_SHORT: /* Valid for lddfa only. */ if (orig_size =3D=3D MO_64) { - tcg_gen_qemu_ld_i64(cpu_fpr[rd / 2], addr, da->mem_idx, - memop | MO_ALIGN); + d64 =3D tcg_temp_new_i64(); + tcg_gen_qemu_ld_i64(d64, addr, da->mem_idx, memop | MO_ALIGN); + gen_store_fpr_D(dc, rd, d64); } else { gen_exception(dc, TT_ILL_INSN); } @@ -1696,17 +1724,19 @@ static void gen_ldf_asi(DisasContext *dc, DisasASI = *da, MemOp orig_size, gen_store_fpr_F(dc, rd, d32); break; case MO_64: - gen_helper_ld_asi(cpu_fpr[rd / 2], tcg_env, addr, - r_asi, r_mop); + d64 =3D tcg_temp_new_i64(); + gen_helper_ld_asi(d64, tcg_env, addr, r_asi, r_mop); + gen_store_fpr_D(dc, rd, d64); break; case MO_128: d64 =3D tcg_temp_new_i64(); + l64 =3D tcg_temp_new_i64(); gen_helper_ld_asi(d64, tcg_env, addr, r_asi, r_mop); addr_tmp =3D tcg_temp_new(); tcg_gen_addi_tl(addr_tmp, addr, 8); - gen_helper_ld_asi(cpu_fpr[rd / 2 + 1], tcg_env, addr_tmp, - r_asi, r_mop); - tcg_gen_mov_i64(cpu_fpr[rd / 2], d64); + gen_helper_ld_asi(l64, tcg_env, addr_tmp, r_asi, r_mop); + gen_store_fpr_D(dc, rd, d64); + gen_store_fpr_D(dc, rd + 2, l64); break; default: g_assert_not_reached(); @@ -1722,6 +1752,7 @@ static void gen_stf_asi(DisasContext *dc, DisasASI *d= a, MemOp orig_size, MemOp memop =3D da->memop; MemOp size =3D memop & MO_SIZE; TCGv_i32 d32; + TCGv_i64 d64; TCGv addr_tmp; =20 /* TODO: Use 128-bit load/store below. */ @@ -1741,8 +1772,8 @@ static void gen_stf_asi(DisasContext *dc, DisasASI *d= a, MemOp orig_size, tcg_gen_qemu_st_i32(d32, addr, da->mem_idx, memop | MO_ALIGN); break; case MO_64: - tcg_gen_qemu_st_i64(cpu_fpr[rd / 2], addr, da->mem_idx, - memop | MO_ALIGN_4); + d64 =3D gen_load_fpr_D(dc, rd); + tcg_gen_qemu_st_i64(d64, addr, da->mem_idx, memop | MO_ALIGN_4= ); break; case MO_128: /* Only 4-byte alignment required. However, it is legal for t= he @@ -1750,11 +1781,12 @@ static void gen_stf_asi(DisasContext *dc, DisasASI = *da, MemOp orig_size, required to fix it up. Requiring 16-byte alignment here av= oids having to probe the second page before performing the first write. */ - tcg_gen_qemu_st_i64(cpu_fpr[rd / 2], addr, da->mem_idx, - memop | MO_ALIGN_16); + d64 =3D gen_load_fpr_D(dc, rd); + tcg_gen_qemu_st_i64(d64, addr, da->mem_idx, memop | MO_ALIGN_1= 6); addr_tmp =3D tcg_temp_new(); tcg_gen_addi_tl(addr_tmp, addr, 8); - tcg_gen_qemu_st_i64(cpu_fpr[rd / 2 + 1], addr_tmp, da->mem_idx= , memop); + d64 =3D gen_load_fpr_D(dc, rd + 2); + tcg_gen_qemu_st_i64(d64, addr_tmp, da->mem_idx, memop); break; default: g_assert_not_reached(); @@ -1767,7 +1799,8 @@ static void gen_stf_asi(DisasContext *dc, DisasASI *d= a, MemOp orig_size, /* The first operation checks required alignment. */ addr_tmp =3D tcg_temp_new(); for (int i =3D 0; ; ++i) { - tcg_gen_qemu_st_i64(cpu_fpr[rd / 2 + i], addr, da->mem_idx, + d64 =3D gen_load_fpr_D(dc, rd + 2 * i); + tcg_gen_qemu_st_i64(d64, addr, da->mem_idx, memop | (i =3D=3D 0 ? MO_ALIGN_64 : 0)= ); if (i =3D=3D 7) { break; @@ -1783,8 +1816,8 @@ static void gen_stf_asi(DisasContext *dc, DisasASI *d= a, MemOp orig_size, case GET_ASI_SHORT: /* Valid for stdfa only. */ if (orig_size =3D=3D MO_64) { - tcg_gen_qemu_st_i64(cpu_fpr[rd / 2], addr, da->mem_idx, - memop | MO_ALIGN); + d64 =3D gen_load_fpr_D(dc, rd); + tcg_gen_qemu_st_i64(d64, addr, da->mem_idx, memop | MO_ALIGN); } else { gen_exception(dc, TT_ILL_INSN); } @@ -2029,13 +2062,17 @@ static void gen_fmovq(DisasContext *dc, DisasCompar= e *cmp, int rd, int rs) { #ifdef TARGET_SPARC64 TCGv c2 =3D tcg_constant_tl(cmp->c2); + TCGv_i64 h =3D tcg_temp_new_i64(); + TCGv_i64 l =3D tcg_temp_new_i64(); =20 - tcg_gen_movcond_i64(cmp->cond, cpu_fpr[rd / 2], cmp->c1, c2, - cpu_fpr[rs / 2], cpu_fpr[rd / 2]); - tcg_gen_movcond_i64(cmp->cond, cpu_fpr[rd / 2 + 1], cmp->c1, c2, - cpu_fpr[rs / 2 + 1], cpu_fpr[rd / 2 + 1]); - - gen_update_fprs_dirty(dc, rd); + tcg_gen_movcond_i64(cmp->cond, h, cmp->c1, c2, + gen_load_fpr_D(dc, rs), + gen_load_fpr_D(dc, rd)); + tcg_gen_movcond_i64(cmp->cond, l, cmp->c1, c2, + gen_load_fpr_D(dc, rs + 2), + gen_load_fpr_D(dc, rd + 2)); + gen_store_fpr_D(dc, rd, h); + gen_store_fpr_D(dc, rd + 2, l); #else qemu_build_not_reached(); #endif @@ -4211,39 +4248,24 @@ static bool do_stfsr(DisasContext *dc, arg_r_r_ri *= a, MemOp mop) TRANS(STFSR, ALL, do_stfsr, a, MO_TEUL) TRANS(STXFSR, 64, do_stfsr, a, MO_TEUQ) =20 -static bool do_fc(DisasContext *dc, int rd, bool c) +static bool do_fc(DisasContext *dc, int rd, int32_t c) { - uint64_t mask; - if (gen_trap_ifnofpu(dc)) { return true; } - - if (rd & 1) { - mask =3D MAKE_64BIT_MASK(0, 32); - } else { - mask =3D MAKE_64BIT_MASK(32, 32); - } - if (c) { - tcg_gen_ori_i64(cpu_fpr[rd / 2], cpu_fpr[rd / 2], mask); - } else { - tcg_gen_andi_i64(cpu_fpr[rd / 2], cpu_fpr[rd / 2], ~mask); - } - gen_update_fprs_dirty(dc, rd); + gen_store_fpr_F(dc, rd, tcg_constant_i32(c)); return advance_pc(dc); } =20 TRANS(FZEROs, VIS1, do_fc, a->rd, 0) -TRANS(FONEs, VIS1, do_fc, a->rd, 1) +TRANS(FONEs, VIS1, do_fc, a->rd, -1) =20 static bool do_dc(DisasContext *dc, int rd, int64_t c) { if (gen_trap_ifnofpu(dc)) { return true; } - - tcg_gen_movi_i64(cpu_fpr[rd / 2], c); - gen_update_fprs_dirty(dc, rd); + gen_store_fpr_D(dc, rd, tcg_constant_i64(c)); return advance_pc(dc); } =20 @@ -5137,12 +5159,6 @@ void sparc_tcg_init(void) "l0", "l1", "l2", "l3", "l4", "l5", "l6", "l7", "i0", "i1", "i2", "i3", "i4", "i5", "i6", "i7", }; - static const char fregnames[32][4] =3D { - "f0", "f2", "f4", "f6", "f8", "f10", "f12", "f14", - "f16", "f18", "f20", "f22", "f24", "f26", "f28", "f30", - "f32", "f34", "f36", "f38", "f40", "f42", "f44", "f46", - "f48", "f50", "f52", "f54", "f56", "f58", "f60", "f62", - }; =20 static const struct { TCGv_i32 *ptr; int off; const char *name; } r32[= ] =3D { #ifdef TARGET_SPARC64 @@ -5199,12 +5215,6 @@ void sparc_tcg_init(void) (i - 8) * sizeof(target_ulong), gregnames[i]); } - - for (i =3D 0; i < TARGET_DPREGS; i++) { - cpu_fpr[i] =3D tcg_global_mem_new_i64(tcg_env, - offsetof(CPUSPARCState, fpr[i]= ), - fregnames[i]); - } } =20 void sparc_restore_state_to_opc(CPUState *cs, --=20 2.34.1 From nobody Mon Nov 25 08:36:39 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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[174.21.72.5]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-1f46ad93c2esm28165935ad.263.2024.05.26.12.43.01 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 26 May 2024 12:43:01 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1716752582; x=1717357382; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=4OF6NAHLFk8bx77QH1kehHlo2DsgfnveZ/OaIZj+BNU=; b=VPZvVVqv2rv18id5zBjeHfgQTr8t/sDIOmfg8bLy8pJ00YqK3v/zTmD8i1sPzKp4pb d5wFa8YJxHHGEjXgL8KQrFPQwwSQ+5P6+9NTgLk3ze71dOSDGSvaPlQZ05kyOxOpyMlr qh0tppaWtJhBFme9bQLvNOtSyydUYnZRL0/niJISV4qv7a8vZbZHzn4y1CegXWVWM0Y/ 0lJrp28QlyIdFxulnRmT77HFWP1wXgtt6F3MDgmNAe858qJU08pYSTbi4QKJnhQ9wX83 Hjbw8Vo4EYSouoztwHyJOE+BVxYiNmKYp0gLv3JtWOl+R72lK9xDT3iJXtXE/5fj220x RMvg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1716752582; x=1717357382; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::533; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x533.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1716752961139100009 Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Richard Henderson Tested-by: Mark Cave-Ayland --- target/sparc/translate.c | 18 ++++++++++++++---- 1 file changed, 14 insertions(+), 4 deletions(-) diff --git a/target/sparc/translate.c b/target/sparc/translate.c index 362e88de18..8731e4f8bb 100644 --- a/target/sparc/translate.c +++ b/target/sparc/translate.c @@ -4664,6 +4664,20 @@ static bool do_dfd(DisasContext *dc, arg_r_r_r *a, =20 TRANS(FMUL8x16, VIS1, do_dfd, a, gen_helper_fmul8x16) =20 +static bool do_gvec_ddd(DisasContext *dc, arg_r_r_r *a, MemOp vece, + void (*func)(unsigned, uint32_t, uint32_t, + uint32_t, uint32_t, uint32_t)) +{ + func(vece, gen_offset_fpr_D(a->rd), gen_offset_fpr_D(a->rs1), + gen_offset_fpr_D(a->rs2), 8, 8); + return advance_pc(dc); +} + +TRANS(FPADD16, VIS1, do_gvec_ddd, a, MO_16, tcg_gen_gvec_add) +TRANS(FPADD32, VIS1, do_gvec_ddd, a, MO_32, tcg_gen_gvec_add) +TRANS(FPSUB16, VIS1, do_gvec_ddd, a, MO_16, tcg_gen_gvec_sub) +TRANS(FPSUB32, VIS1, do_gvec_ddd, a, MO_32, tcg_gen_gvec_sub) + static bool do_ddd(DisasContext *dc, arg_r_r_r *a, void (*func)(TCGv_i64, TCGv_i64, TCGv_i64)) { @@ -4684,10 +4698,6 @@ static bool do_ddd(DisasContext *dc, arg_r_r_r *a, TRANS(FMUL8SUx16, VIS1, do_ddd, a, gen_helper_fmul8sux16) TRANS(FMUL8ULx16, VIS1, do_ddd, a, gen_helper_fmul8ulx16) =20 -TRANS(FPADD16, VIS1, do_ddd, a, tcg_gen_vec_add16_i64) -TRANS(FPADD32, VIS1, do_ddd, a, tcg_gen_vec_add32_i64) -TRANS(FPSUB16, VIS1, do_ddd, a, tcg_gen_vec_sub16_i64) -TRANS(FPSUB32, VIS1, do_ddd, a, tcg_gen_vec_sub32_i64) TRANS(FNORd, VIS1, do_ddd, a, tcg_gen_nor_i64) TRANS(FANDNOTd, VIS1, do_ddd, a, tcg_gen_andc_i64) TRANS(FXORd, VIS1, do_ddd, a, tcg_gen_xor_i64) --=20 2.34.1 From nobody Mon Nov 25 08:36:39 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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[174.21.72.5]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-1f46ad93c2esm28165935ad.263.2024.05.26.12.43.02 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 26 May 2024 12:43:02 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1716752583; x=1717357383; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=GEgwyjfYUpjpgksh4f7RMr8DpQgZ1vbOcktVy9KndOk=; b=E42/AWhiCdUCoagduvCK/qMhaCjmDR+Gfjo8RB9XH9Kp3pARHoyK8R4NdW8NqwsKK5 jH773WDwStmy0rd44bGTz2pRbLU4oNGMB4AL8ocWxBO56AC/G7ypSbRvVVdzNTkz/ISL 5XP0TVBs4QrbI0GHabvV4bvDbEfydBgu/YdBdPnolVeMO24txOlhZKHXMZd6zpGesp1a JVotFvanVIvyP9+voj7lKDr/g9RlvwmMsMAJFPJKeZtHrUm2Wk5Z0iV3SgOVos1LPpKB 6NbFqV/+YVYR/ckMTPYmJ5bbAfD2nxAzrPc3kZIY0QRvhFumfkWubbV8U72seF5+Q++8 EoKw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1716752583; x=1717357383; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=GEgwyjfYUpjpgksh4f7RMr8DpQgZ1vbOcktVy9KndOk=; b=jzhNR6VtEMj2nKNjr44sSsr3e6XnL5IgPN45/12EWy9Fd2HioZ4C1j2klB5hMkJtZu lzX6/2uOHsxCZcbnx2MJLZYjuD1EAkAEaDO8C2Es0YfcdwTsD5uQdx0fQsSHrDfC5hO7 lZ2V1Q/J1gQe+1beXw3prAxnj3OypkZXx3rFnviB1GT/bEnpx8DAwyUIabAdlgnxWb04 eAcOBAqj4wu9CwM1I5za8b6aBePzM0v/LYM0IzKKmH1sgcNnduD2QA3X/w0vPlm80KU4 Tri+oC/zeTfjtu2VenH1GXs3k38KmrjyVtInSXiRl2Yb8JFbr+GT70mtcIiQy5Mad6aL bEcw== X-Gm-Message-State: AOJu0Yz4vHBUeSfLkn86K+0sATe4wYQrQFB6kz1sWxcQXXP4IyqoO19+ Y80l1Ce70cDfWiUp7vufj0ieyIZUMLfayhBW0OCedE2+P71lX9t0caoenQgJ4KDt7dbqs3df4uK s X-Google-Smtp-Source: AGHT+IFXSVZ6z6gyurRthlApEn58DTnn5LeI/ENoP7kX0yCtF1hKggayTtNYLzu+2XBzlPbePCnShQ== X-Received: by 2002:a17:902:ea0a:b0:1f2:fd9a:dbf3 with SMTP id d9443c01a7336-1f4486d1fa4mr88471905ad.11.1716752582696; Sun, 26 May 2024 12:43:02 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: mark.cave-ayland@ilande.co.uk Subject: [PATCH v2 09/37] target/sparc: Implement FMAf extension Date: Sun, 26 May 2024 12:42:26 -0700 Message-Id: <20240526194254.459395-10-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240526194254.459395-1-richard.henderson@linaro.org> References: <20240526194254.459395-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::62d; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1716752718340100003 Content-Type: text/plain; charset="utf-8" Rearrange PDIST so that do_dddd is general purpose and may be re-used for FMADDd etc. Add pickNaN and pickNaNMulAdd. Signed-off-by: Richard Henderson Tested-by: Mark Cave-Ayland --- target/sparc/helper.h | 2 + target/sparc/cpu-feature.h.inc | 1 + target/sparc/insns.decode | 23 +++++++++- linux-user/elfload.c | 1 + target/sparc/cpu.c | 3 ++ target/sparc/fop_helper.c | 16 +++++++ target/sparc/translate.c | 84 ++++++++++++++++++++++++++++++++-- fpu/softfloat-specialize.c.inc | 31 +++++++++++++ 8 files changed, 155 insertions(+), 6 deletions(-) diff --git a/target/sparc/helper.h b/target/sparc/helper.h index 97fbf6f66c..f4d3311ac4 100644 --- a/target/sparc/helper.h +++ b/target/sparc/helper.h @@ -56,6 +56,7 @@ DEF_HELPER_FLAGS_3(faddd, TCG_CALL_NO_WG, f64, env, f64, = f64) DEF_HELPER_FLAGS_3(fsubd, TCG_CALL_NO_WG, f64, env, f64, f64) DEF_HELPER_FLAGS_3(fmuld, TCG_CALL_NO_WG, f64, env, f64, f64) DEF_HELPER_FLAGS_3(fdivd, TCG_CALL_NO_WG, f64, env, f64, f64) +DEF_HELPER_FLAGS_5(fmaddd, TCG_CALL_NO_WG, f64, env, f64, f64, f64, i32) =20 DEF_HELPER_FLAGS_3(faddq, TCG_CALL_NO_WG, i128, env, i128, i128) DEF_HELPER_FLAGS_3(fsubq, TCG_CALL_NO_WG, i128, env, i128, i128) @@ -66,6 +67,7 @@ DEF_HELPER_FLAGS_3(fadds, TCG_CALL_NO_WG, f32, env, f32, = f32) DEF_HELPER_FLAGS_3(fsubs, TCG_CALL_NO_WG, f32, env, f32, f32) DEF_HELPER_FLAGS_3(fmuls, TCG_CALL_NO_WG, f32, env, f32, f32) DEF_HELPER_FLAGS_3(fdivs, TCG_CALL_NO_WG, f32, env, f32, f32) +DEF_HELPER_FLAGS_5(fmadds, TCG_CALL_NO_WG, f32, env, f32, f32, f32, i32) =20 DEF_HELPER_FLAGS_3(fsmuld, TCG_CALL_NO_WG, f64, env, f32, f32) DEF_HELPER_FLAGS_3(fdmulq, TCG_CALL_NO_WG, i128, env, f64, f64) diff --git a/target/sparc/cpu-feature.h.inc b/target/sparc/cpu-feature.h.inc index d800f18c4e..a30b9255b2 100644 --- a/target/sparc/cpu-feature.h.inc +++ b/target/sparc/cpu-feature.h.inc @@ -12,3 +12,4 @@ FEATURE(ASR17) FEATURE(CACHE_CTRL) FEATURE(POWERDOWN) FEATURE(CASA) +FEATURE(FMAF) diff --git a/target/sparc/insns.decode b/target/sparc/insns.decode index 02fa505b49..056fba98f9 100644 --- a/target/sparc/insns.decode +++ b/target/sparc/insns.decode @@ -29,6 +29,7 @@ CALL 01 i:s30 %dfp_rd 25:5 !function=3Dextract_dfpreg %dfp_rs1 14:5 !function=3Dextract_dfpreg %dfp_rs2 0:5 !function=3Dextract_dfpreg +%dfp_rs3 9:5 !function=3Dextract_dfpreg =20 %qfp_rd 25:5 !function=3Dextract_qfpreg %qfp_rs1 14:5 !function=3Dextract_qfpreg @@ -80,6 +81,11 @@ CALL 01 i:s30 @q_d2 .. ..... ...... ..... . ........ ..... \ &r_r rd=3D%qfp_rd rs=3D%dfp_rs2 =20 +&r_r_r_r rd rs1 rs2 rs3 +@r_r_r_r .. rd:5 ...... rs1:5 rs3:5 .... rs2:5 &r_r_r_r +@d_d_d_d .. ..... ...... ..... ..... .... ..... \ + &r_r_r_r rd=3D%dfp_rd rs1=3D%dfp_rs1 rs2=3D%dfp_rs2 rs3=3D%dfp= _rs3 + { [ STBAR 10 00000 101000 01111 0 0000000000000 @@ -394,7 +400,8 @@ FCMPEq 10 000 cc:2 110101 ..... 0 0101 0111 .....= \ FPACK32 10 ..... 110110 ..... 0 0011 1010 ..... @d_d_d FPACK16 10 ..... 110110 00000 0 0011 1011 ..... @r_d2 FPACKFIX 10 ..... 110110 00000 0 0011 1101 ..... @r_d2 - PDIST 10 ..... 110110 ..... 0 0011 1110 ..... @d_d_d + PDIST 10 ..... 110110 ..... 0 0011 1110 ..... \ + &r_r_r_r rd=3D%dfp_rd rs1=3D%dfp_rd rs2=3D%dfp_rs1 rs3=3D%= dfp_rs2 =20 FALIGNDATAg 10 ..... 110110 ..... 0 0100 1000 ..... @d_d_d FPMERGE 10 ..... 110110 ..... 0 0100 1011 ..... @d_r_r @@ -448,7 +455,19 @@ FCMPEq 10 000 cc:2 110101 ..... 0 0101 0111 ....= . \ NCP 10 ----- 110110 ----- --------- ----- # v8 CPop1 } =20 -NCP 10 ----- 110111 ----- --------- ----- # v8 CPop2 +{ + [ + FMADDs 10 ..... 110111 ..... ..... 0001 ..... @r_r_r_r + FMADDd 10 ..... 110111 ..... ..... 0010 ..... @d_d_d_d + FMSUBs 10 ..... 110111 ..... ..... 0101 ..... @r_r_r_r + FMSUBd 10 ..... 110111 ..... ..... 0110 ..... @d_d_d_d + FNMSUBs 10 ..... 110111 ..... ..... 1001 ..... @r_r_r_r + FNMSUBd 10 ..... 110111 ..... ..... 1010 ..... @d_d_d_d + FNMADDs 10 ..... 110111 ..... ..... 1101 ..... @r_r_r_r + FNMADDd 10 ..... 110111 ..... ..... 1110 ..... @d_d_d_d + ] + NCP 10 ----- 110111 ----- --------- ----- # v8 CPop2 +} =20 ## ## Major Opcode 11 -- load and store instructions diff --git a/linux-user/elfload.c b/linux-user/elfload.c index c1e1511ff2..6a1457346a 100644 --- a/linux-user/elfload.c +++ b/linux-user/elfload.c @@ -1003,6 +1003,7 @@ static uint32_t get_elf_hwcap(void) r |=3D features & CPU_FEATURE_FSMULD ? HWCAP_SPARC_FSMULD : 0; r |=3D features & CPU_FEATURE_VIS1 ? HWCAP_SPARC_VIS : 0; r |=3D features & CPU_FEATURE_VIS2 ? HWCAP_SPARC_VIS2 : 0; + r |=3D features & CPU_FEATURE_FMAF ? HWCAP_SPARC_FMAF : 0; #endif =20 return r; diff --git a/target/sparc/cpu.c b/target/sparc/cpu.c index 5be1592e66..ed9238a69d 100644 --- a/target/sparc/cpu.c +++ b/target/sparc/cpu.c @@ -549,6 +549,7 @@ static const char * const feature_name[] =3D { [CPU_FEATURE_BIT_HYPV] =3D "hypv", [CPU_FEATURE_BIT_VIS1] =3D "vis1", [CPU_FEATURE_BIT_VIS2] =3D "vis2", + [CPU_FEATURE_BIT_FMAF] =3D "fmaf", #else [CPU_FEATURE_BIT_MUL] =3D "mul", [CPU_FEATURE_BIT_DIV] =3D "div", @@ -877,6 +878,8 @@ static Property sparc_cpu_properties[] =3D { CPU_FEATURE_BIT_VIS1, false), DEFINE_PROP_BIT("vis2", SPARCCPU, env.def.features, CPU_FEATURE_BIT_VIS2, false), + DEFINE_PROP_BIT("fmaf", SPARCCPU, env.def.features, + CPU_FEATURE_BIT_FMAF, false), #else DEFINE_PROP_BIT("mul", SPARCCPU, env.def.features, CPU_FEATURE_BIT_MUL, false), diff --git a/target/sparc/fop_helper.c b/target/sparc/fop_helper.c index 1205a599ef..1de44d79c1 100644 --- a/target/sparc/fop_helper.c +++ b/target/sparc/fop_helper.c @@ -343,6 +343,22 @@ Int128 helper_fsqrtq(CPUSPARCState *env, Int128 src) return f128_ret(ret); } =20 +float32 helper_fmadds(CPUSPARCState *env, float32 s1, + float32 s2, float32 s3, uint32_t op) +{ + float32 ret =3D float32_muladd(s1, s2, s3, op, &env->fp_status); + check_ieee_exceptions(env, GETPC()); + return ret; +} + +float64 helper_fmaddd(CPUSPARCState *env, float64 s1, + float64 s2, float64 s3, uint32_t op) +{ + float64 ret =3D float64_muladd(s1, s2, s3, op, &env->fp_status); + check_ieee_exceptions(env, GETPC()); + return ret; +} + static uint32_t finish_fcmp(CPUSPARCState *env, FloatRelation r, uintptr_t= ra) { check_ieee_exceptions(env, ra); diff --git a/target/sparc/translate.c b/target/sparc/translate.c index 8731e4f8bb..378da991eb 100644 --- a/target/sparc/translate.c +++ b/target/sparc/translate.c @@ -28,6 +28,7 @@ #include "exec/helper-gen.h" #include "exec/translator.h" #include "exec/log.h" +#include "fpu/softfloat.h" #include "asi.h" =20 #define HELPER_H "helper.h" @@ -1142,6 +1143,52 @@ static void gen_op_fabsq(TCGv_i128 dst, TCGv_i128 sr= c) tcg_gen_concat_i64_i128(dst, l, h); } =20 +static void gen_op_fmadds(TCGv_i32 d, TCGv_i32 s1, TCGv_i32 s2, TCGv_i32 s= 3) +{ + gen_helper_fmadds(d, tcg_env, s1, s2, s3, tcg_constant_i32(0)); +} + +static void gen_op_fmaddd(TCGv_i64 d, TCGv_i64 s1, TCGv_i64 s2, TCGv_i64 s= 3) +{ + gen_helper_fmaddd(d, tcg_env, s1, s2, s3, tcg_constant_i32(0)); +} + +static void gen_op_fmsubs(TCGv_i32 d, TCGv_i32 s1, TCGv_i32 s2, TCGv_i32 s= 3) +{ + int op =3D float_muladd_negate_c; + gen_helper_fmadds(d, tcg_env, s1, s2, s3, tcg_constant_i32(op)); +} + +static void gen_op_fmsubd(TCGv_i64 d, TCGv_i64 s1, TCGv_i64 s2, TCGv_i64 s= 3) +{ + int op =3D float_muladd_negate_c; + gen_helper_fmaddd(d, tcg_env, s1, s2, s3, tcg_constant_i32(op)); +} + +static void gen_op_fnmsubs(TCGv_i32 d, TCGv_i32 s1, TCGv_i32 s2, TCGv_i32 = s3) +{ + int op =3D float_muladd_negate_c | float_muladd_negate_result; + gen_helper_fmadds(d, tcg_env, s1, s2, s3, tcg_constant_i32(op)); +} + +static void gen_op_fnmsubd(TCGv_i64 d, TCGv_i64 s1, TCGv_i64 s2, TCGv_i64 = s3) +{ + int op =3D float_muladd_negate_c | float_muladd_negate_result; + gen_helper_fmaddd(d, tcg_env, s1, s2, s3, tcg_constant_i32(op)); +} + +static void gen_op_fnmadds(TCGv_i32 d, TCGv_i32 s1, TCGv_i32 s2, TCGv_i32 = s3) +{ + int op =3D float_muladd_negate_result; + gen_helper_fmadds(d, tcg_env, s1, s2, s3, tcg_constant_i32(op)); +} + +static void gen_op_fnmaddd(TCGv_i64 d, TCGv_i64 s1, TCGv_i64 s2, TCGv_i64 = s3) +{ + int op =3D float_muladd_negate_result; + gen_helper_fmaddd(d, tcg_env, s1, s2, s3, tcg_constant_i32(op)); +} + static void gen_op_fpexception_im(DisasContext *dc, int ftt) { /* @@ -2136,6 +2183,7 @@ static int extract_qfpreg(DisasContext *dc, int x) # define avail_MUL(C) true # define avail_POWERDOWN(C) false # define avail_64(C) true +# define avail_FMAF(C) ((C)->def->features & CPU_FEATURE_FMAF) # define avail_GL(C) ((C)->def->features & CPU_FEATURE_GL) # define avail_HYPV(C) ((C)->def->features & CPU_FEATURE_HYPV) # define avail_VIS1(C) ((C)->def->features & CPU_FEATURE_VIS1) @@ -2148,6 +2196,7 @@ static int extract_qfpreg(DisasContext *dc, int x) # define avail_MUL(C) ((C)->def->features & CPU_FEATURE_MUL) # define avail_POWERDOWN(C) ((C)->def->features & CPU_FEATURE_POWERDOWN) # define avail_64(C) false +# define avail_FMAF(C) false # define avail_GL(C) false # define avail_HYPV(C) false # define avail_VIS1(C) false @@ -4781,25 +4830,52 @@ static bool trans_FsMULd(DisasContext *dc, arg_r_r_= r *a) return advance_pc(dc); } =20 -static bool do_dddd(DisasContext *dc, arg_r_r_r *a, +static bool do_ffff(DisasContext *dc, arg_r_r_r_r *a, + void (*func)(TCGv_i32, TCGv_i32, TCGv_i32, TCGv_i32)) +{ + TCGv_i32 dst, src1, src2, src3; + + if (gen_trap_ifnofpu(dc)) { + return true; + } + + src1 =3D gen_load_fpr_F(dc, a->rs1); + src2 =3D gen_load_fpr_F(dc, a->rs2); + src3 =3D gen_load_fpr_F(dc, a->rs3); + dst =3D tcg_temp_new_i32(); + func(dst, src1, src2, src3); + gen_store_fpr_F(dc, a->rd, dst); + return advance_pc(dc); +} + +TRANS(FMADDs, FMAF, do_ffff, a, gen_op_fmadds) +TRANS(FMSUBs, FMAF, do_ffff, a, gen_op_fmsubs) +TRANS(FNMSUBs, FMAF, do_ffff, a, gen_op_fnmsubs) +TRANS(FNMADDs, FMAF, do_ffff, a, gen_op_fnmadds) + +static bool do_dddd(DisasContext *dc, arg_r_r_r_r *a, void (*func)(TCGv_i64, TCGv_i64, TCGv_i64, TCGv_i64)) { - TCGv_i64 dst, src0, src1, src2; + TCGv_i64 dst, src1, src2, src3; =20 if (gen_trap_ifnofpu(dc)) { return true; } =20 dst =3D tcg_temp_new_i64(); - src0 =3D gen_load_fpr_D(dc, a->rd); src1 =3D gen_load_fpr_D(dc, a->rs1); src2 =3D gen_load_fpr_D(dc, a->rs2); - func(dst, src0, src1, src2); + src3 =3D gen_load_fpr_D(dc, a->rs3); + func(dst, src1, src2, src3); gen_store_fpr_D(dc, a->rd, dst); return advance_pc(dc); } =20 TRANS(PDIST, VIS1, do_dddd, a, gen_helper_pdist) +TRANS(FMADDd, FMAF, do_dddd, a, gen_op_fmaddd) +TRANS(FMSUBd, FMAF, do_dddd, a, gen_op_fmsubd) +TRANS(FNMSUBd, FMAF, do_dddd, a, gen_op_fnmsubd) +TRANS(FNMADDd, FMAF, do_dddd, a, gen_op_fnmaddd) =20 static bool do_env_qqq(DisasContext *dc, arg_r_r_r *a, void (*func)(TCGv_i128, TCGv_env, TCGv_i128, TCGv_i= 128)) diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc index f573014532..8f3b97d9bf 100644 --- a/fpu/softfloat-specialize.c.inc +++ b/fpu/softfloat-specialize.c.inc @@ -447,6 +447,17 @@ static int pickNaN(FloatClass a_cls, FloatClass b_cls, } else { return 1; } +#elif defined(TARGET_SPARC) + /* Prefer SNaN over QNaN, order B then A. */ + if (is_snan(b_cls)) { + return 1; + } else if (is_snan(a_cls)) { + return 0; + } else if (is_qnan(b_cls)) { + return 1; + } else { + return 0; + } #elif defined(TARGET_XTENSA) /* * Xtensa has two NaN propagation modes. @@ -624,6 +635,26 @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass = b_cls, FloatClass c_cls, float_raise(float_flag_invalid | float_flag_invalid_imz, status); } return 3; /* default NaN */ +#elif defined(TARGET_SPARC) + /* For (inf,0,nan) return c. */ + if (infzero) { + float_raise(float_flag_invalid | float_flag_invalid_imz, status); + return 2; + } + /* Prefer SNaN over QNaN, order C, B, A. */ + if (is_snan(c_cls)) { + return 2; + } else if (is_snan(b_cls)) { + return 1; + } else if (is_snan(a_cls)) { + return 0; + } else if (is_qnan(c_cls)) { + return 2; + } else if (is_qnan(b_cls)) { + return 1; + } else { + return 0; + } #elif defined(TARGET_XTENSA) /* * For Xtensa, the (inf,zero,nan) case sets InvalidOp and returns --=20 2.34.1 From nobody Mon Nov 25 08:36:39 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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[174.21.72.5]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-1f46ad93c2esm28165935ad.263.2024.05.26.12.43.02 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 26 May 2024 12:43:03 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1716752583; x=1717357383; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=gi/s2+2cD+V3SrsXlMXx3XfT3mv0KBqmrRsXrf+YVAk=; b=w4qoWTPfrWV3vuA+XhXDxXV8LMlMbfkPUd/lTpEVs5UOBfmPpHYAoSeqnxIm5Yu00j JyFzjpfnllauSh+joVth0Gbi0VXp5oQZLhQBezC7Mh1Rd+DDRBEA1DySeC9vQe5Gs+ZG QEyJb8rs8C78zHTpxR+wC7IrH8z8aqWDrXLh+xWgB8AxgfmS4iVIhZ6m6kZV6mDc8bTa bkEnJVlo98JtmZRXxjLPeEUUsxHEFYR6ppShiNXEKNVeEVTCW5RHDcmpL1ghnPnNqSG5 8wGfQOCmW9pgbinPf2KGIOjgZpKlPsoSQMh6oPc5RVLv956Wi50LGxrZpPzWgY9MM6d2 xrlg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1716752583; x=1717357383; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=gi/s2+2cD+V3SrsXlMXx3XfT3mv0KBqmrRsXrf+YVAk=; b=HT8ukhCqgxXfXThDswgRlyVDMYJByo9mp0qTHlXqALtt7WMxiMJJ+Oyr5BY415zD42 dDNqG2VTYQeUdyEpT5s0Gw+s9ZS9vJ6eqojlkgExJCagOyFX8pjlPddnWm9I3BCje5sZ 3QotPErQNhuLS7PPsRdlSOfns4dryoACRTnpfe0nHprTj5JwwKlvAZhcMi/ZtLvUmmdX x9BhzeDZ1yKcvc/RoA6rf2JMu0i2YshiH8XdN6iSFDCYETBsPwD69GKy8NFVAo0Y1VRW Fby8Fq3fYpIKTmrqwY12UEVcnpRS1Jb9g3IEK6ZUg+GWZ8r/aUltdV6owP8v6t3LHlK4 fX4g== X-Gm-Message-State: AOJu0YxBhcRy3xVn7X9RCBA5Os6t3LOdCSPCKdDbP0lO597Kjd+Uc9Pm 6kAXdClvL36VBxYh2a9cbUsT32w8QQuyOBRquDKIhl6YKT+/4nOdoFCbH0nKvxEcE4S9vrGlFkx k X-Google-Smtp-Source: AGHT+IE3x9Xvg6nlJO11JIY2GMwB4YXsNx4D5GxtgmoHP8W+u2+RfTVFnCsoVGZO3KdJ/QMbSvW9fg== X-Received: by 2002:a17:902:c94c:b0:1f4:92bb:6604 with SMTP id d9443c01a7336-1f492bb660cmr14211025ad.20.1716752583388; Sun, 26 May 2024 12:43:03 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: mark.cave-ayland@ilande.co.uk, =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH v2 10/37] target/sparc: Add feature bits for VIS 3 Date: Sun, 26 May 2024 12:42:27 -0700 Message-Id: <20240526194254.459395-11-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240526194254.459395-1-richard.henderson@linaro.org> References: <20240526194254.459395-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::629; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x629.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1716752872737100001 The manual separates VIS 3 and VIS 3B, even though they are both present in all extant cpus. For clarity, let the translator match the manual but otherwise leave them on the same feature bit. Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Richard Henderson Tested-by: Mark Cave-Ayland --- target/sparc/cpu-feature.h.inc | 1 + target/sparc/translate.c | 4 ++++ 2 files changed, 5 insertions(+) diff --git a/target/sparc/cpu-feature.h.inc b/target/sparc/cpu-feature.h.inc index a30b9255b2..3913fb4a54 100644 --- a/target/sparc/cpu-feature.h.inc +++ b/target/sparc/cpu-feature.h.inc @@ -13,3 +13,4 @@ FEATURE(CACHE_CTRL) FEATURE(POWERDOWN) FEATURE(CASA) FEATURE(FMAF) +FEATURE(VIS3) diff --git a/target/sparc/translate.c b/target/sparc/translate.c index 378da991eb..9e5fe905ad 100644 --- a/target/sparc/translate.c +++ b/target/sparc/translate.c @@ -2188,6 +2188,8 @@ static int extract_qfpreg(DisasContext *dc, int x) # define avail_HYPV(C) ((C)->def->features & CPU_FEATURE_HYPV) # define avail_VIS1(C) ((C)->def->features & CPU_FEATURE_VIS1) # define avail_VIS2(C) ((C)->def->features & CPU_FEATURE_VIS2) +# define avail_VIS3(C) ((C)->def->features & CPU_FEATURE_VIS3) +# define avail_VIS3B(C) avail_VIS3(C) #else # define avail_32(C) true # define avail_ASR17(C) ((C)->def->features & CPU_FEATURE_ASR17) @@ -2201,6 +2203,8 @@ static int extract_qfpreg(DisasContext *dc, int x) # define avail_HYPV(C) false # define avail_VIS1(C) false # define avail_VIS2(C) false +# define avail_VIS3(C) false +# define avail_VIS3B(C) false #endif =20 /* Default case for non jump instructions. */ --=20 2.34.1 From nobody Mon Nov 25 08:36:39 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1716752960; cv=none; d=zohomail.com; s=zohoarc; b=gPvMtIBoLNAzvFmzKKR/8wfUGnC9PxFuCQYkHDakA2mLFyvfjziQTEoJOZzeXjKTq/w/VEgGqasXWtp+b+DSjyPD7t0todmAEer2J0lIW+iJKbfK6WUyLPrN06f86/U1jMzHA7H0SejH6DXrqo1zUCSaWCh/Z3jUGpFm1nuSEFo= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1716752960; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=5gRl+kJ9r/OgYFfd3fRn/evO0IwNIU7la++WeHVzGO8=; b=CaB9NFd4aR4LghIKgo33/92tTuGs1hLOfxBKJvDojFFbxu5jrNbyLJ6yRGvKnv4BNgjOVrIHYWzhT2/o50BaWFfL2Pnk+bGuBtR99uIEKLRsI7L024hlU6Nct+NCT3BEYr1sP6K5kXiB20RuWvLKFiLosDao5pzATV4UyWjcrnI= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1716752960244796.6286751557104; Sun, 26 May 2024 12:49:20 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1sBJlu-0008Eu-5B; Sun, 26 May 2024 15:43:10 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1sBJls-0008E1-Ax for qemu-devel@nongnu.org; Sun, 26 May 2024 15:43:08 -0400 Received: from mail-pl1-x631.google.com ([2607:f8b0:4864:20::631]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1sBJlp-0007ec-Me for qemu-devel@nongnu.org; Sun, 26 May 2024 15:43:08 -0400 Received: by mail-pl1-x631.google.com with SMTP id d9443c01a7336-1f48bd643a0so3226935ad.3 for ; Sun, 26 May 2024 12:43:05 -0700 (PDT) Received: from stoup.. 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} =20 +static void gen_op_addxc(TCGv dst, TCGv src1, TCGv src2) +{ + tcg_gen_add_tl(dst, src1, src2); + tcg_gen_add_tl(dst, dst, cpu_cc_C); +} + +static void gen_op_addxccc(TCGv dst, TCGv src1, TCGv src2) +{ + gen_op_addcc_int(dst, src1, src2, cpu_cc_C); +} + static void gen_op_subcc_int(TCGv dst, TCGv src1, TCGv src2, TCGv cin) { TCGv z =3D tcg_constant_tl(0); @@ -3692,6 +3703,9 @@ TRANS(ARRAY8, VIS1, do_rrr, a, gen_helper_array8) TRANS(ARRAY16, VIS1, do_rrr, a, gen_op_array16) TRANS(ARRAY32, VIS1, do_rrr, a, gen_op_array32) =20 +TRANS(ADDXC, VIS3, do_rrr, a, gen_op_addxc) +TRANS(ADDXCcc, VIS3, do_rrr, a, gen_op_addxccc) + static void gen_op_alignaddr(TCGv dst, TCGv s1, TCGv s2) { #ifdef TARGET_SPARC64 --=20 2.34.1 From nobody Mon Nov 25 08:36:39 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::635; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x635.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1716752690103100003 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daud=C3=A9 Tested-by: Mark Cave-Ayland --- target/sparc/helper.h | 3 +++ target/sparc/insns.decode | 4 ++++ target/sparc/translate.c | 13 +++++++++++++ target/sparc/vis_helper.c | 38 ++++++++++++++++++++++++++++++++++++++ 4 files changed, 58 insertions(+) diff --git a/target/sparc/helper.h b/target/sparc/helper.h index f4d3311ac4..84435b0932 100644 --- a/target/sparc/helper.h +++ b/target/sparc/helper.h @@ -107,6 +107,9 @@ DEF_HELPER_FLAGS_2(fpack16, TCG_CALL_NO_RWG_SE, i32, i6= 4, i64) DEF_HELPER_FLAGS_3(fpack32, TCG_CALL_NO_RWG_SE, i64, i64, i64, i64) DEF_HELPER_FLAGS_2(fpackfix, TCG_CALL_NO_RWG_SE, i32, i64, i64) DEF_HELPER_FLAGS_3(bshuffle, TCG_CALL_NO_RWG_SE, i64, i64, i64, i64) +DEF_HELPER_FLAGS_2(cmask8, TCG_CALL_NO_RWG_SE, i64, i64, i64) +DEF_HELPER_FLAGS_2(cmask16, TCG_CALL_NO_RWG_SE, i64, i64, i64) +DEF_HELPER_FLAGS_2(cmask32, TCG_CALL_NO_RWG_SE, i64, i64, i64) #define VIS_CMPHELPER(name) \ DEF_HELPER_FLAGS_2(f##name##16, TCG_CALL_NO_RWG_SE, \ i64, i64, i64) \ diff --git a/target/sparc/insns.decode b/target/sparc/insns.decode index 5d1c55aa78..8be808d065 100644 --- a/target/sparc/insns.decode +++ b/target/sparc/insns.decode @@ -384,6 +384,10 @@ FCMPEq 10 000 cc:2 110101 ..... 0 0101 0111 ....= . \ =20 BMASK 10 ..... 110110 ..... 0 0001 1001 ..... @r_r_r =20 + CMASK8 10 00000 110110 00000 0 0001 1011 rs2:5 + CMASK16 10 00000 110110 00000 0 0001 1101 rs2:5 + CMASK32 10 00000 110110 00000 0 0001 1111 rs2:5 + FPCMPLE16 10 ..... 110110 ..... 0 0010 0000 ..... @r_d_d FPCMPNE16 10 ..... 110110 ..... 0 0010 0010 ..... @r_d_d FPCMPGT16 10 ..... 110110 ..... 0 0010 1000 ..... @r_d_d diff --git a/target/sparc/translate.c b/target/sparc/translate.c index 40e245abdd..66c6fb6e41 100644 --- a/target/sparc/translate.c +++ b/target/sparc/translate.c @@ -61,6 +61,9 @@ # define gen_helper_write_softint(E, S) qemu_build_not_reached() # define gen_helper_wrpil(E, S) qemu_build_not_reached() # define gen_helper_wrpstate(E, S) qemu_build_not_reached() +# define gen_helper_cmask8 ({ qemu_build_not_reached(); NULL= ; }) +# define gen_helper_cmask16 ({ qemu_build_not_reached(); NULL= ; }) +# define gen_helper_cmask32 ({ qemu_build_not_reached(); NULL= ; }) # define gen_helper_fcmpeq16 ({ qemu_build_not_reached(); NULL= ; }) # define gen_helper_fcmpeq32 ({ qemu_build_not_reached(); NULL= ; }) # define gen_helper_fcmpgt16 ({ qemu_build_not_reached(); NULL= ; }) @@ -3748,6 +3751,16 @@ static void gen_op_bmask(TCGv dst, TCGv s1, TCGv s2) =20 TRANS(BMASK, VIS2, do_rrr, a, gen_op_bmask) =20 +static bool do_cmask(DisasContext *dc, int rs2, void (*func)(TCGv, TCGv, T= CGv)) +{ + func(cpu_gsr, cpu_gsr, gen_load_gpr(dc, rs2)); + return true; +} + +TRANS(CMASK8, VIS3, do_cmask, a->rs2, gen_helper_cmask8) +TRANS(CMASK16, VIS3, do_cmask, a->rs2, gen_helper_cmask16) +TRANS(CMASK32, VIS3, do_cmask, a->rs2, gen_helper_cmask32) + static bool do_shift_r(DisasContext *dc, arg_shiftr *a, bool l, bool u) { TCGv dst, src1, src2; diff --git a/target/sparc/vis_helper.c b/target/sparc/vis_helper.c index 41312deda4..20baa4ff71 100644 --- a/target/sparc/vis_helper.c +++ b/target/sparc/vis_helper.c @@ -351,3 +351,41 @@ uint64_t helper_bshuffle(uint64_t gsr, uint64_t src1, = uint64_t src2) =20 return r.ll; } + +uint64_t helper_cmask8(uint64_t gsr, uint64_t src) +{ + uint32_t mask =3D 0; + + mask |=3D (src & 0x01 ? 0x00000007 : 0x0000000f); + mask |=3D (src & 0x02 ? 0x00000060 : 0x000000e0); + mask |=3D (src & 0x04 ? 0x00000500 : 0x00000d00); + mask |=3D (src & 0x08 ? 0x00004000 : 0x0000c000); + mask |=3D (src & 0x10 ? 0x00030000 : 0x000b0000); + mask |=3D (src & 0x20 ? 0x00200000 : 0x00a00000); + mask |=3D (src & 0x40 ? 0x01000000 : 0x09000000); + mask |=3D (src & 0x80 ? 0x00000000 : 0x80000000); + + return deposit64(gsr, 32, 32, mask); +} + +uint64_t helper_cmask16(uint64_t gsr, uint64_t src) +{ + uint32_t mask =3D 0; + + mask |=3D (src & 0x1 ? 0x00000067 : 0x000000ef); + mask |=3D (src & 0x2 ? 0x00004500 : 0x0000cd00); + mask |=3D (src & 0x4 ? 0x00230000 : 0x00ab0000); + mask |=3D (src & 0x8 ? 0x01000000 : 0x89000000); + + return deposit64(gsr, 32, 32, mask); +} + +uint64_t helper_cmask32(uint64_t gsr, uint64_t src) +{ + uint32_t mask =3D 0; + + mask |=3D (src & 0x1 ? 0x00004567 : 0x0000cdef); + mask |=3D (src & 0x2 ? 0x01230000 : 0x89ab0000); + + return deposit64(gsr, 32, 32, mask); +} --=20 2.34.1 From nobody Mon Nov 25 08:36:39 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1716752697; cv=none; d=zohomail.com; s=zohoarc; b=QFM8WVSvvzgR80MA9fmypq8gE1X1X/FkGPUvR+1vvSD3FXQRdc1eYx7KU8cevcv6PXgqD5qOM7Xv41Msi865F0r6U5Lk7FICGxTv558FOdRMEffkch47JWGK6hf5GN+CDYY+GgZWhoA6G7my+A1QTbkdP676+/3Y4Zd/u6rhOcQ= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1716752697; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::536; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x536.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1716752698092100001 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daud=C3=A9 Tested-by: Mark Cave-Ayland --- target/sparc/helper.h | 1 + target/sparc/insns.decode | 1 + target/sparc/translate.c | 32 ++++++++++++++++++++++++++++++++ target/sparc/vis_helper.c | 23 +++++++++++++++++++++++ 4 files changed, 57 insertions(+) diff --git a/target/sparc/helper.h b/target/sparc/helper.h index 84435b0932..e59307efc2 100644 --- a/target/sparc/helper.h +++ b/target/sparc/helper.h @@ -110,6 +110,7 @@ DEF_HELPER_FLAGS_3(bshuffle, TCG_CALL_NO_RWG_SE, i64, i= 64, i64, i64) DEF_HELPER_FLAGS_2(cmask8, TCG_CALL_NO_RWG_SE, i64, i64, i64) DEF_HELPER_FLAGS_2(cmask16, TCG_CALL_NO_RWG_SE, i64, i64, i64) DEF_HELPER_FLAGS_2(cmask32, TCG_CALL_NO_RWG_SE, i64, i64, i64) +DEF_HELPER_FLAGS_2(fchksm16, TCG_CALL_NO_RWG_SE, i64, i64, i64) #define VIS_CMPHELPER(name) \ DEF_HELPER_FLAGS_2(f##name##16, TCG_CALL_NO_RWG_SE, \ i64, i64, i64) \ diff --git a/target/sparc/insns.decode b/target/sparc/insns.decode index 8be808d065..18d068d2af 100644 --- a/target/sparc/insns.decode +++ b/target/sparc/insns.decode @@ -410,6 +410,7 @@ FCMPEq 10 000 cc:2 110101 ..... 0 0101 0111 .....= \ PDIST 10 ..... 110110 ..... 0 0011 1110 ..... \ &r_r_r_r rd=3D%dfp_rd rs1=3D%dfp_rd rs2=3D%dfp_rs1 rs3=3D%= dfp_rs2 =20 + FCHKSM16 10 ..... 110110 ..... 0 0100 0100 ..... @d_d_d FALIGNDATAg 10 ..... 110110 ..... 0 0100 1000 ..... @d_d_d FPMERGE 10 ..... 110110 ..... 0 0100 1011 ..... @d_r_r BSHUFFLE 10 ..... 110110 ..... 0 0100 1100 ..... @d_d_d diff --git a/target/sparc/translate.c b/target/sparc/translate.c index 66c6fb6e41..48ee1abd68 100644 --- a/target/sparc/translate.c +++ b/target/sparc/translate.c @@ -788,6 +788,37 @@ static void gen_op_fmuld8sux16(TCGv_i64 dst, TCGv_i32 = src1, TCGv_i32 src2) tcg_gen_concat_i32_i64(dst, t0, t1); } =20 +#ifdef TARGET_SPARC64 +static void gen_vec_fchksm16(unsigned vece, TCGv_vec dst, + TCGv_vec src1, TCGv_vec src2) +{ + TCGv_vec a =3D tcg_temp_new_vec_matching(dst); + TCGv_vec c =3D tcg_temp_new_vec_matching(dst); + + tcg_gen_add_vec(vece, a, src1, src2); + tcg_gen_cmp_vec(TCG_COND_LTU, vece, c, a, src1); + /* Vector cmp produces -1 for true, so subtract to add carry. */ + tcg_gen_sub_vec(vece, dst, a, c); +} + +static void gen_op_fchksm16(unsigned vece, uint32_t dofs, uint32_t aofs, + uint32_t bofs, uint32_t oprsz, uint32_t maxsz) +{ + static const TCGOpcode vecop_list[] =3D { + INDEX_op_cmp_vec, INDEX_op_add_vec, INDEX_op_sub_vec, + }; + static const GVecGen3 op =3D { + .fni8 =3D gen_helper_fchksm16, + .fniv =3D gen_vec_fchksm16, + .opt_opc =3D vecop_list, + .vece =3D MO_16, + }; + tcg_gen_gvec_3(dofs, aofs, bofs, oprsz, maxsz, &op); +} +#else +#define gen_op_fchksm16 ({ qemu_build_not_reached(); NULL; }) +#endif + static void finishing_insn(DisasContext *dc) { /* @@ -4757,6 +4788,7 @@ TRANS(FPADD16, VIS1, do_gvec_ddd, a, MO_16, tcg_gen_g= vec_add) TRANS(FPADD32, VIS1, do_gvec_ddd, a, MO_32, tcg_gen_gvec_add) TRANS(FPSUB16, VIS1, do_gvec_ddd, a, MO_16, tcg_gen_gvec_sub) TRANS(FPSUB32, VIS1, do_gvec_ddd, a, MO_32, tcg_gen_gvec_sub) +TRANS(FCHKSM16, VIS3, do_gvec_ddd, a, MO_16, gen_op_fchksm16) =20 static bool do_ddd(DisasContext *dc, arg_r_r_r *a, void (*func)(TCGv_i64, TCGv_i64, TCGv_i64)) diff --git a/target/sparc/vis_helper.c b/target/sparc/vis_helper.c index 20baa4ff71..fa607375d2 100644 --- a/target/sparc/vis_helper.c +++ b/target/sparc/vis_helper.c @@ -389,3 +389,26 @@ uint64_t helper_cmask32(uint64_t gsr, uint64_t src) =20 return deposit64(gsr, 32, 32, mask); } + +static inline uint16_t do_fchksm16(uint16_t src1, uint16_t src2) +{ + uint16_t a =3D src1 + src2; + uint16_t c =3D a < src1; + return a + c; +} + +uint64_t helper_fchksm16(uint64_t src1, uint64_t src2) +{ + VIS64 r, s1, s2; + + s1.ll =3D src1; + s2.ll =3D src2; + r.ll =3D 0; + + r.VIS_W64(0) =3D do_fchksm16(s1.VIS_W64(0), s2.VIS_W64(0)); + r.VIS_W64(1) =3D do_fchksm16(s1.VIS_W64(1), s2.VIS_W64(1)); + r.VIS_W64(2) =3D do_fchksm16(s1.VIS_W64(2), s2.VIS_W64(2)); + r.VIS_W64(3) =3D do_fchksm16(s1.VIS_W64(3), s2.VIS_W64(3)); + + return r.ll; +} --=20 2.34.1 From nobody Mon Nov 25 08:36:39 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1716752865; cv=none; d=zohomail.com; s=zohoarc; b=VsyBPWgdh1RbeUS2rV++Nt9F/2rv0geI796oMwnxyHZfB4MJK4UKZPfBzaRSmITUmEQtYIyg6wJaElJVqaT+bjcE7EH1yJosbS6skUVJ0VmbGZp1G0o/eLPUKtREtA4FqSjPcQ7AD3PQm+X7RBSPoR8Sk+ZvTKgWxqaFBxhjIv8= ARC-Message-Signature: i=1; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::636; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x636.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1716752866735100010 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson Tested-by: Mark Cave-Ayland --- target/sparc/helper.h | 5 +++ target/sparc/insns.decode | 11 ++++++ target/sparc/fop_helper.c | 68 +++++++++++++++++++++++++++++++++++ target/sparc/translate.c | 76 +++++++++++++++++++++++++++++++++++++++ 4 files changed, 160 insertions(+) diff --git a/target/sparc/helper.h b/target/sparc/helper.h index e59307efc2..15f0907a1b 100644 --- a/target/sparc/helper.h +++ b/target/sparc/helper.h @@ -57,6 +57,8 @@ DEF_HELPER_FLAGS_3(fsubd, TCG_CALL_NO_WG, f64, env, f64, = f64) DEF_HELPER_FLAGS_3(fmuld, TCG_CALL_NO_WG, f64, env, f64, f64) DEF_HELPER_FLAGS_3(fdivd, TCG_CALL_NO_WG, f64, env, f64, f64) DEF_HELPER_FLAGS_5(fmaddd, TCG_CALL_NO_WG, f64, env, f64, f64, f64, i32) +DEF_HELPER_FLAGS_3(fnaddd, TCG_CALL_NO_WG, f64, env, f64, f64) +DEF_HELPER_FLAGS_3(fnmuld, TCG_CALL_NO_WG, f64, env, f64, f64) =20 DEF_HELPER_FLAGS_3(faddq, TCG_CALL_NO_WG, i128, env, i128, i128) DEF_HELPER_FLAGS_3(fsubq, TCG_CALL_NO_WG, i128, env, i128, i128) @@ -68,8 +70,11 @@ DEF_HELPER_FLAGS_3(fsubs, TCG_CALL_NO_WG, f32, env, f32,= f32) DEF_HELPER_FLAGS_3(fmuls, TCG_CALL_NO_WG, f32, env, f32, f32) DEF_HELPER_FLAGS_3(fdivs, TCG_CALL_NO_WG, f32, env, f32, f32) DEF_HELPER_FLAGS_5(fmadds, TCG_CALL_NO_WG, f32, env, f32, f32, f32, i32) +DEF_HELPER_FLAGS_3(fnadds, TCG_CALL_NO_WG, f32, env, f32, f32) +DEF_HELPER_FLAGS_3(fnmuls, TCG_CALL_NO_WG, f32, env, f32, f32) =20 DEF_HELPER_FLAGS_3(fsmuld, TCG_CALL_NO_WG, f64, env, f32, f32) +DEF_HELPER_FLAGS_3(fnsmuld, TCG_CALL_NO_WG, f64, env, f32, f32) DEF_HELPER_FLAGS_3(fdmulq, TCG_CALL_NO_WG, i128, env, f64, f64) =20 DEF_HELPER_FLAGS_2(fitod, TCG_CALL_NO_WG, f64, env, s32) diff --git a/target/sparc/insns.decode b/target/sparc/insns.decode index 18d068d2af..6ec3838865 100644 --- a/target/sparc/insns.decode +++ b/target/sparc/insns.decode @@ -307,8 +307,19 @@ FMULq 10 ..... 110100 ..... 0 0100 1011 ..... = @q_q_q FDIVs 10 ..... 110100 ..... 0 0100 1101 ..... @r_r_r FDIVd 10 ..... 110100 ..... 0 0100 1110 ..... @d_d_d FDIVq 10 ..... 110100 ..... 0 0100 1111 ..... @q_q_q +FNADDs 10 ..... 110100 ..... 0 0101 0001 ..... @r_r_r +FNADDd 10 ..... 110100 ..... 0 0101 0010 ..... @d_d_d +FNMULs 10 ..... 110100 ..... 0 0101 1001 ..... @r_r_r +FNMULd 10 ..... 110100 ..... 0 0101 1010 ..... @d_d_d +FHADDs 10 ..... 110100 ..... 0 0110 0001 ..... @r_r_r +FHADDd 10 ..... 110100 ..... 0 0110 0010 ..... @d_d_d +FHSUBs 10 ..... 110100 ..... 0 0110 0101 ..... @r_r_r +FHSUBd 10 ..... 110100 ..... 0 0110 0110 ..... @d_d_d FsMULd 10 ..... 110100 ..... 0 0110 1001 ..... @d_r_r FdMULq 10 ..... 110100 ..... 0 0110 1110 ..... @q_d_d +FNHADDs 10 ..... 110100 ..... 0 0111 0001 ..... @r_r_r +FNHADDd 10 ..... 110100 ..... 0 0111 0010 ..... @d_d_d +FNsMULd 10 ..... 110100 ..... 0 0111 1001 ..... @d_r_r FsTOx 10 ..... 110100 00000 0 1000 0001 ..... @r_r2 FdTOx 10 ..... 110100 00000 0 1000 0010 ..... @r_d2 FqTOx 10 ..... 110100 00000 0 1000 0011 ..... @r_q2 diff --git a/target/sparc/fop_helper.c b/target/sparc/fop_helper.c index 1de44d79c1..08b5f96f95 100644 --- a/target/sparc/fop_helper.c +++ b/target/sparc/fop_helper.c @@ -359,6 +359,74 @@ float64 helper_fmaddd(CPUSPARCState *env, float64 s1, return ret; } =20 +float32 helper_fnadds(CPUSPARCState *env, float32 src1, float32 src2) +{ + float32 ret =3D float32_add(src1, src2, &env->fp_status); + + /* + * NaN inputs or result do not get a sign change. + * Nor, apparently, does zero: on hardware, -(x + -x) yields +0. + */ + if (!float32_is_any_nan(ret) && !float32_is_zero(ret)) { + ret =3D float32_chs(ret); + } + check_ieee_exceptions(env, GETPC()); + return ret; +} + +float32 helper_fnmuls(CPUSPARCState *env, float32 src1, float32 src2) +{ + float32 ret =3D float32_mul(src1, src2, &env->fp_status); + + /* NaN inputs or result do not get a sign change. */ + if (!float32_is_any_nan(ret)) { + ret =3D float32_chs(ret); + } + check_ieee_exceptions(env, GETPC()); + return ret; +} + +float64 helper_fnaddd(CPUSPARCState *env, float64 src1, float64 src2) +{ + float64 ret =3D float64_add(src1, src2, &env->fp_status); + + /* + * NaN inputs or result do not get a sign change. + * Nor, apparently, does zero: on hardware, -(x + -x) yields +0. + */ + if (!float64_is_any_nan(ret) && !float64_is_zero(ret)) { + ret =3D float64_chs(ret); + } + check_ieee_exceptions(env, GETPC()); + return ret; +} + +float64 helper_fnmuld(CPUSPARCState *env, float64 src1, float64 src2) +{ + float64 ret =3D float64_mul(src1, src2, &env->fp_status); + + /* NaN inputs or result do not get a sign change. */ + if (!float64_is_any_nan(ret)) { + ret =3D float64_chs(ret); + } + check_ieee_exceptions(env, GETPC()); + return ret; +} + +float64 helper_fnsmuld(CPUSPARCState *env, float32 src1, float32 src2) +{ + float64 ret =3D float64_mul(float32_to_float64(src1, &env->fp_status), + float32_to_float64(src2, &env->fp_status), + &env->fp_status); + + /* NaN inputs or result do not get a sign change. */ + if (!float64_is_any_nan(ret)) { + ret =3D float64_chs(ret); + } + check_ieee_exceptions(env, GETPC()); + return ret; +} + static uint32_t finish_fcmp(CPUSPARCState *env, FloatRelation r, uintptr_t= ra) { check_ieee_exceptions(env, ra); diff --git a/target/sparc/translate.c b/target/sparc/translate.c index 48ee1abd68..4515886590 100644 --- a/target/sparc/translate.c +++ b/target/sparc/translate.c @@ -1234,6 +1234,51 @@ static void gen_op_fnmaddd(TCGv_i64 d, TCGv_i64 s1, = TCGv_i64 s2, TCGv_i64 s3) gen_helper_fmaddd(d, tcg_env, s1, s2, s3, tcg_constant_i32(op)); } =20 +/* Use muladd to compute (1 * src1) + src2 / 2 with one rounding. */ +static void gen_op_fhadds(TCGv_i32 d, TCGv_i32 s1, TCGv_i32 s2) +{ + TCGv_i32 one =3D tcg_constant_i32(float32_one); + int op =3D float_muladd_halve_result; + gen_helper_fmadds(d, tcg_env, one, s1, s2, tcg_constant_i32(op)); +} + +static void gen_op_fhaddd(TCGv_i64 d, TCGv_i64 s1, TCGv_i64 s2) +{ + TCGv_i64 one =3D tcg_constant_i64(float64_one); + int op =3D float_muladd_halve_result; + gen_helper_fmaddd(d, tcg_env, one, s1, s2, tcg_constant_i32(op)); +} + +/* Use muladd to compute (1 * src1) - src2 / 2 with one rounding. */ +static void gen_op_fhsubs(TCGv_i32 d, TCGv_i32 s1, TCGv_i32 s2) +{ + TCGv_i32 one =3D tcg_constant_i32(float32_one); + int op =3D float_muladd_negate_c | float_muladd_halve_result; + gen_helper_fmadds(d, tcg_env, one, s1, s2, tcg_constant_i32(op)); +} + +static void gen_op_fhsubd(TCGv_i64 d, TCGv_i64 s1, TCGv_i64 s2) +{ + TCGv_i64 one =3D tcg_constant_i64(float64_one); + int op =3D float_muladd_negate_c | float_muladd_halve_result; + gen_helper_fmaddd(d, tcg_env, one, s1, s2, tcg_constant_i32(op)); +} + +/* Use muladd to compute -((1 * src1) + src2 / 2) with one rounding. */ +static void gen_op_fnhadds(TCGv_i32 d, TCGv_i32 s1, TCGv_i32 s2) +{ + TCGv_i32 one =3D tcg_constant_i32(float32_one); + int op =3D float_muladd_negate_result | float_muladd_halve_result; + gen_helper_fmadds(d, tcg_env, one, s1, s2, tcg_constant_i32(op)); +} + +static void gen_op_fnhaddd(TCGv_i64 d, TCGv_i64 s1, TCGv_i64 s2) +{ + TCGv_i64 one =3D tcg_constant_i64(float64_one); + int op =3D float_muladd_negate_result | float_muladd_halve_result; + gen_helper_fmaddd(d, tcg_env, one, s1, s2, tcg_constant_i32(op)); +} + static void gen_op_fpexception_im(DisasContext *dc, int ftt) { /* @@ -4710,6 +4755,10 @@ TRANS(FXNORs, VIS1, do_fff, a, tcg_gen_eqv_i32) TRANS(FORNOTs, VIS1, do_fff, a, tcg_gen_orc_i32) TRANS(FORs, VIS1, do_fff, a, tcg_gen_or_i32) =20 +TRANS(FHADDs, VIS3, do_fff, a, gen_op_fhadds) +TRANS(FHSUBs, VIS3, do_fff, a, gen_op_fhsubs) +TRANS(FNHADDs, VIS3, do_fff, a, gen_op_fnhadds) + static bool do_env_fff(DisasContext *dc, arg_r_r_r *a, void (*func)(TCGv_i32, TCGv_env, TCGv_i32, TCGv_i32= )) { @@ -4730,6 +4779,8 @@ TRANS(FADDs, ALL, do_env_fff, a, gen_helper_fadds) TRANS(FSUBs, ALL, do_env_fff, a, gen_helper_fsubs) TRANS(FMULs, ALL, do_env_fff, a, gen_helper_fmuls) TRANS(FDIVs, ALL, do_env_fff, a, gen_helper_fdivs) +TRANS(FNADDs, VIS3, do_env_fff, a, gen_helper_fnadds) +TRANS(FNMULs, VIS3, do_env_fff, a, gen_helper_fnmuls) =20 static bool do_dff(DisasContext *dc, arg_r_r_r *a, void (*func)(TCGv_i64, TCGv_i32, TCGv_i32)) @@ -4823,6 +4874,10 @@ TRANS(FPACK32, VIS1, do_ddd, a, gen_op_fpack32) TRANS(FALIGNDATAg, VIS1, do_ddd, a, gen_op_faligndata) TRANS(BSHUFFLE, VIS2, do_ddd, a, gen_op_bshuffle) =20 +TRANS(FHADDd, VIS3, do_ddd, a, gen_op_fhaddd) +TRANS(FHSUBd, VIS3, do_ddd, a, gen_op_fhsubd) +TRANS(FNHADDd, VIS3, do_ddd, a, gen_op_fnhaddd) + static bool do_rdd(DisasContext *dc, arg_r_r_r *a, void (*func)(TCGv, TCGv_i64, TCGv_i64)) { @@ -4872,6 +4927,8 @@ TRANS(FADDd, ALL, do_env_ddd, a, gen_helper_faddd) TRANS(FSUBd, ALL, do_env_ddd, a, gen_helper_fsubd) TRANS(FMULd, ALL, do_env_ddd, a, gen_helper_fmuld) TRANS(FDIVd, ALL, do_env_ddd, a, gen_helper_fdivd) +TRANS(FNADDd, VIS3, do_env_ddd, a, gen_helper_fnaddd) +TRANS(FNMULd, VIS3, do_env_ddd, a, gen_helper_fnmuld) =20 static bool trans_FsMULd(DisasContext *dc, arg_r_r_r *a) { @@ -4893,6 +4950,25 @@ static bool trans_FsMULd(DisasContext *dc, arg_r_r_r= *a) return advance_pc(dc); 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::633; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x633.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1716752603784100003 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson Tested-by: Mark Cave-Ayland --- target/sparc/helper.h | 2 ++ target/sparc/insns.decode | 4 ++++ target/sparc/fop_helper.c | 46 +++++++++++++++++++++++++++++++++++++++ target/sparc/translate.c | 34 +++++++++++++++++++++++++++++ 4 files changed, 86 insertions(+) diff --git a/target/sparc/helper.h b/target/sparc/helper.h index 15f0907a1b..ab79954bb5 100644 --- a/target/sparc/helper.h +++ b/target/sparc/helper.h @@ -50,6 +50,8 @@ DEF_HELPER_FLAGS_3(fcmpd, TCG_CALL_NO_WG, i32, env, f64, = f64) DEF_HELPER_FLAGS_3(fcmped, TCG_CALL_NO_WG, i32, env, f64, f64) DEF_HELPER_FLAGS_3(fcmpq, TCG_CALL_NO_WG, i32, env, i128, i128) DEF_HELPER_FLAGS_3(fcmpeq, TCG_CALL_NO_WG, i32, env, i128, i128) +DEF_HELPER_FLAGS_2(flcmps, TCG_CALL_NO_RWG_SE, i32, f32, f32) +DEF_HELPER_FLAGS_2(flcmpd, TCG_CALL_NO_RWG_SE, i32, f64, f64) DEF_HELPER_2(raise_exception, noreturn, env, int) =20 DEF_HELPER_FLAGS_3(faddd, TCG_CALL_NO_WG, f64, env, f64, f64) diff --git a/target/sparc/insns.decode b/target/sparc/insns.decode index 6ec3838865..de29996304 100644 --- a/target/sparc/insns.decode +++ b/target/sparc/insns.decode @@ -470,6 +470,10 @@ FCMPEq 10 000 cc:2 110101 ..... 0 0101 0111 ....= . \ FZEROs 10 rd:5 110110 00000 0 0110 0001 00000 FONEd 10 ..... 110110 00000 0 0111 1110 00000 rd=3D%dfp_rd FONEs 10 rd:5 110110 00000 0 0111 1111 00000 + + FLCMPs 10 000 cc:2 110110 rs1:5 1 0101 0001 rs2:5 + FLCMPd 10 000 cc:2 110110 ..... 1 0101 0010 ..... \ + rs1=3D%dfp_rs1 rs2=3D%dfp_rs2 ] NCP 10 ----- 110110 ----- --------- ----- # v8 CPop1 } diff --git a/target/sparc/fop_helper.c b/target/sparc/fop_helper.c index 08b5f96f95..1b524c6d3c 100644 --- a/target/sparc/fop_helper.c +++ b/target/sparc/fop_helper.c @@ -490,6 +490,52 @@ uint32_t helper_fcmpeq(CPUSPARCState *env, Int128 src1= , Int128 src2) return finish_fcmp(env, r, GETPC()); } =20 +uint32_t helper_flcmps(float32 src1, float32 src2) +{ + /* + * FLCMP never raises an exception nor modifies any FSR fields. + * Perform the comparison with a dummy fp environment. + */ + float_status discard =3D { }; + FloatRelation r =3D float32_compare_quiet(src1, src2, &discard); + + switch (r) { + case float_relation_equal: + if (src2 =3D=3D float32_zero && src1 !=3D float32_zero) { + return 1; /* -0.0 < +0.0 */ + } + return 0; + case float_relation_less: + return 1; + case float_relation_greater: + return 0; + case float_relation_unordered: + return float32_is_any_nan(src2) ? 3 : 2; + } + g_assert_not_reached(); +} + +uint32_t helper_flcmpd(float64 src1, float64 src2) +{ + float_status discard =3D { }; + FloatRelation r =3D float64_compare_quiet(src1, src2, &discard); + + switch (r) { + case float_relation_equal: + if (src2 =3D=3D float64_zero && src1 !=3D float64_zero) { + return 1; /* -0.0 < +0.0 */ + } + return 0; + case float_relation_less: + return 1; + case float_relation_greater: + return 0; + case float_relation_unordered: + return float64_is_any_nan(src2) ? 3 : 2; + } + g_assert_not_reached(); +} + target_ulong cpu_get_fsr(CPUSPARCState *env) { target_ulong fsr =3D env->fsr | env->fsr_cexc_ftt; diff --git a/target/sparc/translate.c b/target/sparc/translate.c index 4515886590..f53ecf7c41 100644 --- a/target/sparc/translate.c +++ b/target/sparc/translate.c @@ -5203,6 +5203,40 @@ static bool do_fcmpq(DisasContext *dc, arg_FCMPq *a,= bool e) TRANS(FCMPq, ALL, do_fcmpq, a, false) TRANS(FCMPEq, ALL, do_fcmpq, a, true) =20 +static bool trans_FLCMPs(DisasContext *dc, arg_FLCMPs *a) +{ + TCGv_i32 src1, src2; + + if (!avail_VIS3(dc)) { + return false; + } + if (gen_trap_ifnofpu(dc)) { + return true; + } + + src1 =3D gen_load_fpr_F(dc, a->rs1); + src2 =3D gen_load_fpr_F(dc, a->rs2); + gen_helper_flcmps(cpu_fcc[a->cc], src1, src2); + return advance_pc(dc); +} + +static bool trans_FLCMPd(DisasContext *dc, arg_FLCMPd *a) +{ + TCGv_i64 src1, src2; + + if (!avail_VIS3(dc)) { + return false; + } + if (gen_trap_ifnofpu(dc)) { + return true; + } + + src1 =3D gen_load_fpr_D(dc, a->rs1); + src2 =3D gen_load_fpr_D(dc, a->rs2); + gen_helper_flcmpd(cpu_fcc[a->cc], src1, src2); + return advance_pc(dc); +} + static void sparc_tr_init_disas_context(DisasContextBase *dcbase, CPUState= *cs) { DisasContext *dc =3D container_of(dcbase, DisasContext, base); --=20 2.34.1 From nobody Mon Nov 25 08:36:39 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1716752675; cv=none; d=zohomail.com; s=zohoarc; b=LkgEA38LQKli8EY0BkUuoFY9eAhQalH0jwMu0u1PssOI/+0WDeUOfHeW55gXUPz7GCF/0+qSDi4c+xxepBm7Cn4vBhBnaHnuTQ4S/j094MkrjWyJMAJZ5ZT/h8QfGD8tLOLSI70xp3wnGjI2DdEJrP9HE2SAs2OlhfF7upWO96g= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::636; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x636.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1716752676006100003 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daud=C3=A9 Tested-by: Mark Cave-Ayland --- target/sparc/helper.h | 1 + target/sparc/insns.decode | 1 + target/sparc/translate.c | 30 ++++++++++++++++++++++++++++++ target/sparc/vis_helper.c | 21 +++++++++++++++++++++ 4 files changed, 53 insertions(+) diff --git a/target/sparc/helper.h b/target/sparc/helper.h index ab79954bb5..f1b84dc9b3 100644 --- a/target/sparc/helper.h +++ b/target/sparc/helper.h @@ -118,6 +118,7 @@ DEF_HELPER_FLAGS_2(cmask8, TCG_CALL_NO_RWG_SE, i64, i64= , i64) DEF_HELPER_FLAGS_2(cmask16, TCG_CALL_NO_RWG_SE, i64, i64, i64) DEF_HELPER_FLAGS_2(cmask32, TCG_CALL_NO_RWG_SE, i64, i64, i64) DEF_HELPER_FLAGS_2(fchksm16, TCG_CALL_NO_RWG_SE, i64, i64, i64) +DEF_HELPER_FLAGS_2(fmean16, TCG_CALL_NO_RWG_SE, i64, i64, i64) #define VIS_CMPHELPER(name) \ DEF_HELPER_FLAGS_2(f##name##16, TCG_CALL_NO_RWG_SE, \ i64, i64, i64) \ diff --git a/target/sparc/insns.decode b/target/sparc/insns.decode index de29996304..febd1a4a13 100644 --- a/target/sparc/insns.decode +++ b/target/sparc/insns.decode @@ -421,6 +421,7 @@ FCMPEq 10 000 cc:2 110101 ..... 0 0101 0111 .....= \ PDIST 10 ..... 110110 ..... 0 0011 1110 ..... \ &r_r_r_r rd=3D%dfp_rd rs1=3D%dfp_rd rs2=3D%dfp_rs1 rs3=3D%= dfp_rs2 =20 + FMEAN16 10 ..... 110110 ..... 0 0100 0000 ..... @d_d_d FCHKSM16 10 ..... 110110 ..... 0 0100 0100 ..... @d_d_d FALIGNDATAg 10 ..... 110110 ..... 0 0100 1000 ..... @d_d_d FPMERGE 10 ..... 110110 ..... 0 0100 1011 ..... @d_r_r diff --git a/target/sparc/translate.c b/target/sparc/translate.c index f53ecf7c41..cf5f1ea4d0 100644 --- a/target/sparc/translate.c +++ b/target/sparc/translate.c @@ -815,8 +815,37 @@ static void gen_op_fchksm16(unsigned vece, uint32_t do= fs, uint32_t aofs, }; tcg_gen_gvec_3(dofs, aofs, bofs, oprsz, maxsz, &op); } + +static void gen_vec_fmean16(unsigned vece, TCGv_vec dst, + TCGv_vec src1, TCGv_vec src2) +{ + TCGv_vec t =3D tcg_temp_new_vec_matching(dst); + + tcg_gen_or_vec(vece, t, src1, src2); + tcg_gen_and_vec(vece, t, t, tcg_constant_vec_matching(dst, vece, 1)); + tcg_gen_sari_vec(vece, src1, src1, 1); + tcg_gen_sari_vec(vece, src2, src2, 1); + tcg_gen_add_vec(vece, dst, src1, src2); + tcg_gen_add_vec(vece, dst, dst, t); +} + +static void gen_op_fmean16(unsigned vece, uint32_t dofs, uint32_t aofs, + uint32_t bofs, uint32_t oprsz, uint32_t maxsz) +{ + static const TCGOpcode vecop_list[] =3D { + INDEX_op_add_vec, INDEX_op_sari_vec, + }; + static const GVecGen3 op =3D { + .fni8 =3D gen_helper_fmean16, + .fniv =3D gen_vec_fmean16, + .opt_opc =3D vecop_list, + .vece =3D MO_16, + }; + tcg_gen_gvec_3(dofs, aofs, bofs, oprsz, maxsz, &op); +} #else #define gen_op_fchksm16 ({ qemu_build_not_reached(); NULL; }) +#define gen_op_fmean16 ({ qemu_build_not_reached(); NULL; }) #endif =20 static void finishing_insn(DisasContext *dc) @@ -4840,6 +4869,7 @@ TRANS(FPADD32, VIS1, do_gvec_ddd, a, MO_32, tcg_gen_g= vec_add) TRANS(FPSUB16, VIS1, do_gvec_ddd, a, MO_16, tcg_gen_gvec_sub) TRANS(FPSUB32, VIS1, do_gvec_ddd, a, MO_32, tcg_gen_gvec_sub) TRANS(FCHKSM16, VIS3, do_gvec_ddd, a, MO_16, gen_op_fchksm16) +TRANS(FMEAN16, VIS3, do_gvec_ddd, a, MO_16, gen_op_fmean16) =20 static bool do_ddd(DisasContext *dc, arg_r_r_r *a, void (*func)(TCGv_i64, TCGv_i64, TCGv_i64)) diff --git a/target/sparc/vis_helper.c b/target/sparc/vis_helper.c index fa607375d2..6ef36755c3 100644 --- a/target/sparc/vis_helper.c +++ b/target/sparc/vis_helper.c @@ -412,3 +412,24 @@ uint64_t helper_fchksm16(uint64_t src1, uint64_t src2) =20 return r.ll; } + +static inline int16_t do_fmean16(int16_t src1, int16_t src2) +{ + return (src1 + src2 + 1) / 2; +} + +uint64_t helper_fmean16(uint64_t src1, uint64_t src2) +{ + VIS64 r, s1, s2; + + s1.ll =3D src1; + s2.ll =3D src2; + r.ll =3D 0; + + r.VIS_SW64(0) =3D do_fmean16(s1.VIS_SW64(0), s2.VIS_SW64(0)); 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::52b; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x52b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1716752649955100003 Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Richard Henderson Tested-by: Mark Cave-Ayland --- target/sparc/insns.decode | 2 ++ target/sparc/translate.c | 3 +++ 2 files changed, 5 insertions(+) diff --git a/target/sparc/insns.decode b/target/sparc/insns.decode index febd1a4a13..70ca41a69a 100644 --- a/target/sparc/insns.decode +++ b/target/sparc/insns.decode @@ -441,10 +441,12 @@ FCMPEq 10 000 cc:2 110101 ..... 0 0101 0111 ...= .. \ FPADD16s 10 ..... 110110 ..... 0 0101 0001 ..... @r_r_r FPADD32 10 ..... 110110 ..... 0 0101 0010 ..... @d_d_d FPADD32s 10 ..... 110110 ..... 0 0101 0011 ..... @r_r_r + FPADD64 10 ..... 110110 ..... 0 0100 0010 ..... @d_d_d FPSUB16 10 ..... 110110 ..... 0 0101 0100 ..... @d_d_d FPSUB16s 10 ..... 110110 ..... 0 0101 0101 ..... @r_r_r FPSUB32 10 ..... 110110 ..... 0 0101 0110 ..... @d_d_d FPSUB32s 10 ..... 110110 ..... 0 0101 0111 ..... @r_r_r + FPSUB64 10 ..... 110110 ..... 0 0100 0110 ..... @d_d_d =20 FNORd 10 ..... 110110 ..... 0 0110 0010 ..... @d_d_d FNORs 10 ..... 110110 ..... 0 0110 0011 ..... @r_r_r diff --git a/target/sparc/translate.c b/target/sparc/translate.c index cf5f1ea4d0..52b9590b4b 100644 --- a/target/sparc/translate.c +++ b/target/sparc/translate.c @@ -4908,6 +4908,9 @@ TRANS(FHADDd, VIS3, do_ddd, a, gen_op_fhaddd) TRANS(FHSUBd, VIS3, do_ddd, a, gen_op_fhsubd) TRANS(FNHADDd, VIS3, do_ddd, a, gen_op_fnhaddd) =20 +TRANS(FPADD64, VIS3B, do_ddd, a, tcg_gen_add_i64) +TRANS(FPSUB64, VIS3B, do_ddd, a, tcg_gen_sub_i64) + static bool do_rdd(DisasContext *dc, arg_r_r_r *a, void (*func)(TCGv, TCGv_i64, TCGv_i64)) { --=20 2.34.1 From nobody Mon Nov 25 08:36:39 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::630; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x630.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1716752667984100007 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daud=C3=A9 Tested-by: Mark Cave-Ayland --- target/sparc/insns.decode | 9 +++++ target/sparc/translate.c | 82 +++++++++++++++++++++++++++++++++++++++ 2 files changed, 91 insertions(+) diff --git a/target/sparc/insns.decode b/target/sparc/insns.decode index 70ca41a69a..b6553362eb 100644 --- a/target/sparc/insns.decode +++ b/target/sparc/insns.decode @@ -448,6 +448,15 @@ FCMPEq 10 000 cc:2 110101 ..... 0 0101 0111 ....= . \ FPSUB32s 10 ..... 110110 ..... 0 0101 0111 ..... @r_r_r FPSUB64 10 ..... 110110 ..... 0 0100 0110 ..... @d_d_d =20 + FPADDS16 10 ..... 110110 ..... 0 0101 1000 ..... @d_d_d + FPADDS16s 10 ..... 110110 ..... 0 0101 1001 ..... @r_r_r + FPADDS32 10 ..... 110110 ..... 0 0101 1010 ..... @d_d_d + FPADDS32s 10 ..... 110110 ..... 0 0101 1011 ..... @r_r_r + FPSUBS16 10 ..... 110110 ..... 0 0101 1100 ..... @d_d_d + FPSUBS16s 10 ..... 110110 ..... 0 0101 1101 ..... @r_r_r + FPSUBS32 10 ..... 110110 ..... 0 0101 1110 ..... @d_d_d + FPSUBS32s 10 ..... 110110 ..... 0 0101 1111 ..... @r_r_r + FNORd 10 ..... 110110 ..... 0 0110 0010 ..... @d_d_d FNORs 10 ..... 110110 ..... 0 0110 0011 ..... @r_r_r FANDNOTd 10 ..... 110110 ..... 0 0110 0100 ..... @d_d_d # FAND= NOT2d diff --git a/target/sparc/translate.c b/target/sparc/translate.c index 52b9590b4b..b9e932496e 100644 --- a/target/sparc/translate.c +++ b/target/sparc/translate.c @@ -698,6 +698,78 @@ static void gen_op_fpack32(TCGv_i64 dst, TCGv_i64 src1= , TCGv_i64 src2) #endif } =20 +static void gen_op_fpadds16s(TCGv_i32 d, TCGv_i32 src1, TCGv_i32 src2) +{ + TCGv_i32 t[2]; + + for (int i =3D 0; i < 2; i++) { + TCGv_i32 u =3D tcg_temp_new_i32(); + TCGv_i32 v =3D tcg_temp_new_i32(); + + tcg_gen_sextract_i32(u, src1, i * 16, 16); + tcg_gen_sextract_i32(v, src2, i * 16, 16); + tcg_gen_add_i32(u, u, v); + tcg_gen_smax_i32(u, u, tcg_constant_i32(INT16_MIN)); + tcg_gen_smin_i32(u, u, tcg_constant_i32(INT16_MAX)); + t[i] =3D u; + } + tcg_gen_deposit_i32(d, t[0], t[1], 16, 16); +} + +static void gen_op_fpsubs16s(TCGv_i32 d, TCGv_i32 src1, TCGv_i32 src2) +{ + TCGv_i32 t[2]; + + for (int i =3D 0; i < 2; i++) { + TCGv_i32 u =3D tcg_temp_new_i32(); + TCGv_i32 v =3D tcg_temp_new_i32(); + + tcg_gen_sextract_i32(u, src1, i * 16, 16); + tcg_gen_sextract_i32(v, src2, i * 16, 16); + tcg_gen_sub_i32(u, u, v); + tcg_gen_smax_i32(u, u, tcg_constant_i32(INT16_MIN)); + tcg_gen_smin_i32(u, u, tcg_constant_i32(INT16_MAX)); + t[i] =3D u; + } + tcg_gen_deposit_i32(d, t[0], t[1], 16, 16); +} + +static void gen_op_fpadds32s(TCGv_i32 d, TCGv_i32 src1, TCGv_i32 src2) +{ + TCGv_i32 r =3D tcg_temp_new_i32(); + TCGv_i32 t =3D tcg_temp_new_i32(); + TCGv_i32 v =3D tcg_temp_new_i32(); + TCGv_i32 z =3D tcg_constant_i32(0); + + tcg_gen_add_i32(r, src1, src2); + tcg_gen_xor_i32(t, src1, src2); + tcg_gen_xor_i32(v, r, src2); + tcg_gen_andc_i32(v, v, t); + + tcg_gen_setcond_i32(TCG_COND_GE, t, r, z); + tcg_gen_addi_i32(t, t, INT32_MAX); + + tcg_gen_movcond_i32(TCG_COND_LT, d, v, z, t, r); +} + +static void gen_op_fpsubs32s(TCGv_i32 d, TCGv_i32 src1, TCGv_i32 src2) +{ + TCGv_i32 r =3D tcg_temp_new_i32(); + TCGv_i32 t =3D tcg_temp_new_i32(); + TCGv_i32 v =3D tcg_temp_new_i32(); + TCGv_i32 z =3D tcg_constant_i32(0); + + tcg_gen_sub_i32(r, src1, src2); + tcg_gen_xor_i32(t, src1, src2); + tcg_gen_xor_i32(v, r, src1); + tcg_gen_and_i32(v, v, t); + + tcg_gen_setcond_i32(TCG_COND_GE, t, r, z); + tcg_gen_addi_i32(t, t, INT32_MAX); + + tcg_gen_movcond_i32(TCG_COND_LT, d, v, z, t, r); +} + static void gen_op_faligndata(TCGv_i64 dst, TCGv_i64 s1, TCGv_i64 s2) { #ifdef TARGET_SPARC64 @@ -4788,6 +4860,11 @@ TRANS(FHADDs, VIS3, do_fff, a, gen_op_fhadds) TRANS(FHSUBs, VIS3, do_fff, a, gen_op_fhsubs) TRANS(FNHADDs, VIS3, do_fff, a, gen_op_fnhadds) =20 +TRANS(FPADDS16s, VIS3, do_fff, a, gen_op_fpadds16s) +TRANS(FPSUBS16s, VIS3, do_fff, a, gen_op_fpsubs16s) +TRANS(FPADDS32s, VIS3, do_fff, a, gen_op_fpadds32s) +TRANS(FPSUBS32s, VIS3, do_fff, a, gen_op_fpsubs32s) + static bool do_env_fff(DisasContext *dc, arg_r_r_r *a, void (*func)(TCGv_i32, TCGv_env, TCGv_i32, TCGv_i32= )) { @@ -4871,6 +4948,11 @@ TRANS(FPSUB32, VIS1, do_gvec_ddd, a, MO_32, tcg_gen_= gvec_sub) TRANS(FCHKSM16, VIS3, do_gvec_ddd, a, MO_16, gen_op_fchksm16) TRANS(FMEAN16, VIS3, do_gvec_ddd, a, MO_16, gen_op_fmean16) =20 +TRANS(FPADDS16, VIS3, do_gvec_ddd, a, MO_16, tcg_gen_gvec_ssadd) +TRANS(FPADDS32, VIS3, do_gvec_ddd, a, MO_32, tcg_gen_gvec_ssadd) +TRANS(FPSUBS16, VIS3, do_gvec_ddd, a, MO_16, tcg_gen_gvec_sssub) +TRANS(FPSUBS32, VIS3, do_gvec_ddd, a, MO_32, tcg_gen_gvec_sssub) + static bool do_ddd(DisasContext *dc, arg_r_r_r *a, void (*func)(TCGv_i64, TCGv_i64, TCGv_i64)) { --=20 2.34.1 From nobody Mon Nov 25 08:36:39 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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[174.21.72.5]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-1f46ad93c2esm28165935ad.263.2024.05.26.12.43.10 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 26 May 2024 12:43:10 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1716752591; x=1717357391; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=s3TrWiWfbhfRDglMbr7omJW7rWrBNKn4wgYmHvr3JBc=; b=xUYTa2CIidydHlhW2FszT6MikE0n8KiffJNH6YrXlfVxTdRwOYrF3l7Zo6A4pGQnt7 VbXspHqd4Zs+g4w24PKxmFo5onQrAClitU5XkLmsxuaJD4rOoJkdt81CG1AouEK5eKpW 8j4lG+uDATLHVzo5y+o0hhMtYaLgf2l9HKsyGP0gfLmBGHD0AFHBVK9VLHQN+Echcvbf HtqTfn8Hi8/nCxma3+bOK41+wONbExZE0kDDVTI18sjFP+yeNy2WP57RLpxE5sdVqr0H iwMCuWaec0pddDM8kyZwrVv8Jytn3EwHrichUMSBzPHPwgfXsk7BEolhYjT2ODxgYNSl cBfQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1716752591; x=1717357391; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::62b; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1716752832583100005 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daud=C3=A9 Tested-by: Mark Cave-Ayland --- target/sparc/helper.h | 4 ++++ target/sparc/insns.decode | 5 +++++ target/sparc/translate.c | 9 +++++++++ target/sparc/vis_helper.c | 40 +++++++++++++++++++++++++++++++++++++++ 4 files changed, 58 insertions(+) diff --git a/target/sparc/helper.h b/target/sparc/helper.h index f1b84dc9b3..ed295c01e0 100644 --- a/target/sparc/helper.h +++ b/target/sparc/helper.h @@ -128,6 +128,10 @@ VIS_CMPHELPER(cmpgt) VIS_CMPHELPER(cmpeq) VIS_CMPHELPER(cmple) VIS_CMPHELPER(cmpne) +DEF_HELPER_FLAGS_2(fcmpeq8, TCG_CALL_NO_RWG_SE, i64, i64, i64) +DEF_HELPER_FLAGS_2(fcmpne8, TCG_CALL_NO_RWG_SE, i64, i64, i64) +DEF_HELPER_FLAGS_2(fcmpule8, TCG_CALL_NO_RWG_SE, i64, i64, i64) +DEF_HELPER_FLAGS_2(fcmpugt8, TCG_CALL_NO_RWG_SE, i64, i64, i64) #endif #undef VIS_HELPER #undef VIS_CMPHELPER diff --git a/target/sparc/insns.decode b/target/sparc/insns.decode index b6553362eb..295fc36128 100644 --- a/target/sparc/insns.decode +++ b/target/sparc/insns.decode @@ -408,6 +408,11 @@ FCMPEq 10 000 cc:2 110101 ..... 0 0101 0111 ....= . \ FPCMPGT32 10 ..... 110110 ..... 0 0010 1100 ..... @r_d_d FPCMPEQ32 10 ..... 110110 ..... 0 0010 1110 ..... @r_d_d =20 + FPCMPULE8 10 ..... 110110 ..... 1 0010 0000 ..... @r_d_d + FPCMPUGT8 10 ..... 110110 ..... 1 0010 1000 ..... @r_d_d + FPCMPNE8 10 ..... 110110 ..... 1 0010 0010 ..... @r_d_d + FPCMPEQ8 10 ..... 110110 ..... 1 0010 1010 ..... @r_d_d + FMUL8x16 10 ..... 110110 ..... 0 0011 0001 ..... @d_r_d FMUL8x16AU 10 ..... 110110 ..... 0 0011 0011 ..... @d_r_r FMUL8x16AL 10 ..... 110110 ..... 0 0011 0101 ..... @d_r_r diff --git a/target/sparc/translate.c b/target/sparc/translate.c index b9e932496e..7a20e79b7e 100644 --- a/target/sparc/translate.c +++ b/target/sparc/translate.c @@ -64,14 +64,18 @@ # define gen_helper_cmask8 ({ qemu_build_not_reached(); NULL= ; }) # define gen_helper_cmask16 ({ qemu_build_not_reached(); NULL= ; }) # define gen_helper_cmask32 ({ qemu_build_not_reached(); NULL= ; }) +# define gen_helper_fcmpeq8 ({ qemu_build_not_reached(); NULL= ; }) # define gen_helper_fcmpeq16 ({ qemu_build_not_reached(); NULL= ; }) # define gen_helper_fcmpeq32 ({ qemu_build_not_reached(); NULL= ; }) # define gen_helper_fcmpgt16 ({ qemu_build_not_reached(); NULL= ; }) # define gen_helper_fcmpgt32 ({ qemu_build_not_reached(); NULL= ; }) # define gen_helper_fcmple16 ({ qemu_build_not_reached(); NULL= ; }) # define gen_helper_fcmple32 ({ qemu_build_not_reached(); NULL= ; }) +# define gen_helper_fcmpne8 ({ qemu_build_not_reached(); NULL= ; }) # define gen_helper_fcmpne16 ({ qemu_build_not_reached(); NULL= ; }) # define gen_helper_fcmpne32 ({ qemu_build_not_reached(); NULL= ; }) +# define gen_helper_fcmpule8 ({ qemu_build_not_reached(); NULL= ; }) +# define gen_helper_fcmpugt8 ({ qemu_build_not_reached(); NULL= ; }) # define gen_helper_fdtox ({ qemu_build_not_reached(); NULL= ; }) # define gen_helper_fexpand ({ qemu_build_not_reached(); NULL= ; }) # define gen_helper_fmul8sux16 ({ qemu_build_not_reached(); NULL= ; }) @@ -5021,6 +5025,11 @@ TRANS(FPCMPNE32, VIS1, do_rdd, a, gen_helper_fcmpne3= 2) TRANS(FPCMPGT32, VIS1, do_rdd, a, gen_helper_fcmpgt32) TRANS(FPCMPEQ32, VIS1, do_rdd, a, gen_helper_fcmpeq32) =20 +TRANS(FPCMPEQ8, VIS3B, do_rdd, a, gen_helper_fcmpeq8) +TRANS(FPCMPNE8, VIS3B, do_rdd, a, gen_helper_fcmpne8) +TRANS(FPCMPULE8, VIS3B, do_rdd, a, gen_helper_fcmpule8) +TRANS(FPCMPUGT8, VIS3B, do_rdd, a, gen_helper_fcmpugt8) + static bool do_env_ddd(DisasContext *dc, arg_r_r_r *a, void (*func)(TCGv_i64, TCGv_env, TCGv_i64, TCGv_i64= )) { diff --git a/target/sparc/vis_helper.c b/target/sparc/vis_helper.c index 6ef36755c3..5a5da17132 100644 --- a/target/sparc/vis_helper.c +++ b/target/sparc/vis_helper.c @@ -238,6 +238,46 @@ VIS_CMPHELPER(helper_fcmpeq, FCMPEQ) VIS_CMPHELPER(helper_fcmple, FCMPLE) VIS_CMPHELPER(helper_fcmpne, FCMPNE) =20 +uint64_t helper_fcmpeq8(uint64_t src1, uint64_t src2) +{ + uint64_t a =3D src1 ^ src2; + uint64_t m =3D 0x7f7f7f7f7f7f7f7fULL; + uint64_t c =3D ~(((a & m) + m) | a | m); + + /* a.......b.......c.......d.......e.......f.......g.......h....... */ + c |=3D c << 7; + /* ab......bc......cd......de......ef......fg......gh......h....... */ + c |=3D c << 14; + /* abcd....bcde....cdef....defg....efgh....fgh.....gh......h....... */ + c |=3D c << 28; + /* abcdefghbcdefgh.cdefgh..defgh...efgh....fgh.....gh......h....... */ + return c >> 56; +} + +uint64_t helper_fcmpne8(uint64_t src1, uint64_t src2) +{ + return helper_fcmpeq8(src1, src2) ^ 0xff; +} + +uint64_t helper_fcmpule8(uint64_t src1, uint64_t src2) +{ + VIS64 s1, s2; + uint64_t r =3D 0; + + s1.ll =3D src1; + s2.ll =3D src2; + + for (int i =3D 0; i < 8; ++i) { + r |=3D (s1.VIS_B64(i) <=3D s2.VIS_B64(i)) << i; + } + return r; +} + +uint64_t helper_fcmpugt8(uint64_t src1, uint64_t src2) +{ + return helper_fcmpule8(src1, src2) ^ 0xff; +} + uint64_t helper_pdist(uint64_t sum, uint64_t src1, uint64_t src2) { int i; --=20 2.34.1 From nobody Mon Nov 25 08:36:39 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::632; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x632.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1716752666170100001 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daud=C3=A9 Tested-by: Mark Cave-Ayland --- target/sparc/helper.h | 2 ++ target/sparc/insns.decode | 9 +++++++++ target/sparc/translate.c | 11 +++++++++++ target/sparc/vis_helper.c | 36 ++++++++++++++++++++++++++++++++++++ 4 files changed, 58 insertions(+) diff --git a/target/sparc/helper.h b/target/sparc/helper.h index ed295c01e0..219f0e04c7 100644 --- a/target/sparc/helper.h +++ b/target/sparc/helper.h @@ -119,6 +119,8 @@ DEF_HELPER_FLAGS_2(cmask16, TCG_CALL_NO_RWG_SE, i64, i6= 4, i64) DEF_HELPER_FLAGS_2(cmask32, TCG_CALL_NO_RWG_SE, i64, i64, i64) DEF_HELPER_FLAGS_2(fchksm16, TCG_CALL_NO_RWG_SE, i64, i64, i64) DEF_HELPER_FLAGS_2(fmean16, TCG_CALL_NO_RWG_SE, i64, i64, i64) +DEF_HELPER_FLAGS_2(fslas16, TCG_CALL_NO_RWG_SE, i64, i64, i64) +DEF_HELPER_FLAGS_2(fslas32, TCG_CALL_NO_RWG_SE, i64, i64, i64) #define VIS_CMPHELPER(name) \ DEF_HELPER_FLAGS_2(f##name##16, TCG_CALL_NO_RWG_SE, \ i64, i64, i64) \ diff --git a/target/sparc/insns.decode b/target/sparc/insns.decode index 295fc36128..a5eefebfbc 100644 --- a/target/sparc/insns.decode +++ b/target/sparc/insns.decode @@ -408,6 +408,15 @@ FCMPEq 10 000 cc:2 110101 ..... 0 0101 0111 ....= . \ FPCMPGT32 10 ..... 110110 ..... 0 0010 1100 ..... @r_d_d FPCMPEQ32 10 ..... 110110 ..... 0 0010 1110 ..... @r_d_d =20 + FSLL16 10 ..... 110110 ..... 0 0010 0001 ..... @d_d_d + FSRL16 10 ..... 110110 ..... 0 0010 0011 ..... @d_d_d + FSLAS16 10 ..... 110110 ..... 0 0010 1001 ..... @d_d_d + FSRA16 10 ..... 110110 ..... 0 0010 1011 ..... @d_d_d + FSLL32 10 ..... 110110 ..... 0 0010 0101 ..... @d_d_d + FSRL32 10 ..... 110110 ..... 0 0010 0111 ..... @d_d_d + FSLAS32 10 ..... 110110 ..... 0 0010 1101 ..... @d_d_d + FSRA32 10 ..... 110110 ..... 0 0010 1111 ..... @d_d_d + FPCMPULE8 10 ..... 110110 ..... 1 0010 0000 ..... @r_d_d FPCMPUGT8 10 ..... 110110 ..... 1 0010 1000 ..... @r_d_d FPCMPNE8 10 ..... 110110 ..... 1 0010 0010 ..... @r_d_d diff --git a/target/sparc/translate.c b/target/sparc/translate.c index 7a20e79b7e..ade9df3960 100644 --- a/target/sparc/translate.c +++ b/target/sparc/translate.c @@ -83,6 +83,8 @@ # define gen_helper_fmul8x16 ({ qemu_build_not_reached(); NULL= ; }) # define gen_helper_fpmerge ({ qemu_build_not_reached(); NULL= ; }) # define gen_helper_fqtox ({ qemu_build_not_reached(); NULL= ; }) +# define gen_helper_fslas16 ({ qemu_build_not_reached(); NULL= ; }) +# define gen_helper_fslas32 ({ qemu_build_not_reached(); NULL= ; }) # define gen_helper_fstox ({ qemu_build_not_reached(); NULL= ; }) # define gen_helper_fxtod ({ qemu_build_not_reached(); NULL= ; }) # define gen_helper_fxtoq ({ qemu_build_not_reached(); NULL= ; }) @@ -4957,6 +4959,13 @@ TRANS(FPADDS32, VIS3, do_gvec_ddd, a, MO_32, tcg_gen= _gvec_ssadd) TRANS(FPSUBS16, VIS3, do_gvec_ddd, a, MO_16, tcg_gen_gvec_sssub) TRANS(FPSUBS32, VIS3, do_gvec_ddd, a, MO_32, tcg_gen_gvec_sssub) =20 +TRANS(FSLL16, VIS3, do_gvec_ddd, a, MO_16, tcg_gen_gvec_shlv) +TRANS(FSLL32, VIS3, do_gvec_ddd, a, MO_32, tcg_gen_gvec_shlv) +TRANS(FSRL16, VIS3, do_gvec_ddd, a, MO_16, tcg_gen_gvec_shrv) +TRANS(FSRL32, VIS3, do_gvec_ddd, a, MO_32, tcg_gen_gvec_shrv) +TRANS(FSRA16, VIS3, do_gvec_ddd, a, MO_16, tcg_gen_gvec_sarv) +TRANS(FSRA32, VIS3, do_gvec_ddd, a, MO_32, tcg_gen_gvec_sarv) + static bool do_ddd(DisasContext *dc, arg_r_r_r *a, void (*func)(TCGv_i64, TCGv_i64, TCGv_i64)) { @@ -4996,6 +5005,8 @@ TRANS(FNHADDd, VIS3, do_ddd, a, gen_op_fnhaddd) =20 TRANS(FPADD64, VIS3B, do_ddd, a, tcg_gen_add_i64) TRANS(FPSUB64, VIS3B, do_ddd, a, tcg_gen_sub_i64) +TRANS(FSLAS16, VIS3, do_ddd, a, gen_helper_fslas16) +TRANS(FSLAS32, VIS3, do_ddd, a, gen_helper_fslas32) =20 static bool do_rdd(DisasContext *dc, arg_r_r_r *a, void (*func)(TCGv, TCGv_i64, TCGv_i64)) diff --git a/target/sparc/vis_helper.c b/target/sparc/vis_helper.c index 5a5da17132..c21522c533 100644 --- a/target/sparc/vis_helper.c +++ b/target/sparc/vis_helper.c @@ -473,3 +473,39 @@ uint64_t helper_fmean16(uint64_t src1, uint64_t src2) =20 return r.ll; } + +uint64_t helper_fslas16(uint64_t src1, uint64_t src2) +{ + VIS64 r, s1, s2; + + s1.ll =3D src1; + s2.ll =3D src2; + r.ll =3D 0; + + for (int i =3D 0; i < 4; ++i) { + int t =3D s1.VIS_SW64(i) << (s2.VIS_W64(i) % 16); + t =3D MIN(t, INT16_MAX); + t =3D MAX(t, INT16_MIN); + r.VIS_SW64(i) =3D t; + } + + return r.ll; +} + +uint64_t helper_fslas32(uint64_t src1, uint64_t src2) +{ + VIS64 r, s1, s2; + + s1.ll =3D src1; + s2.ll =3D src2; + r.ll =3D 0; + + for (int i =3D 0; i < 2; ++i) { + int64_t t =3D (int64_t)(int32_t)s1.VIS_L64(i) << (s2.VIS_L64(i) % = 32); + t =3D MIN(t, INT32_MAX); + t =3D MAX(t, INT32_MIN); + r.VIS_L64(i) =3D t; + } + + return r.ll; +} --=20 2.34.1 From nobody Mon Nov 25 08:36:39 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::633; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x633.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1716752971120100003 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daud=C3=A9 Tested-by: Mark Cave-Ayland --- target/sparc/helper.h | 1 + target/sparc/insns.decode | 1 + target/sparc/fop_helper.c | 6 ++++++ target/sparc/translate.c | 11 +++++++++-- 4 files changed, 17 insertions(+), 2 deletions(-) diff --git a/target/sparc/helper.h b/target/sparc/helper.h index 219f0e04c7..4ae97866af 100644 --- a/target/sparc/helper.h +++ b/target/sparc/helper.h @@ -40,6 +40,7 @@ DEF_HELPER_FLAGS_4(ld_asi, TCG_CALL_NO_WG, i64, env, tl, = int, i32) DEF_HELPER_FLAGS_5(st_asi, TCG_CALL_NO_WG, void, env, tl, i64, int, i32) #endif DEF_HELPER_FLAGS_1(get_fsr, TCG_CALL_NO_WG_SE, tl, env) +DEF_HELPER_FLAGS_2(set_fsr_nofcc, TCG_CALL_NO_RWG, void, env, i32) DEF_HELPER_FLAGS_2(set_fsr_nofcc_noftt, TCG_CALL_NO_RWG, void, env, i32) DEF_HELPER_FLAGS_2(fsqrts, TCG_CALL_NO_WG, f32, env, f32) DEF_HELPER_FLAGS_2(fsqrtd, TCG_CALL_NO_WG, f64, env, f64) diff --git a/target/sparc/insns.decode b/target/sparc/insns.decode index a5eefebfbc..fec055910e 100644 --- a/target/sparc/insns.decode +++ b/target/sparc/insns.decode @@ -589,6 +589,7 @@ STX 11 ..... 011110 ..... . ............. = @r_r_i_asi # STXA LDF 11 ..... 100000 ..... . ............. @r_r_ri_na LDFSR 11 00000 100001 ..... . ............. @n_r_ri LDXFSR 11 00001 100001 ..... . ............. @n_r_ri +LDXEFSR 11 00011 100001 ..... . ............. @n_r_ri LDQF 11 ..... 100010 ..... . ............. @q_r_ri_na LDDF 11 ..... 100011 ..... . ............. @d_r_ri_na =20 diff --git a/target/sparc/fop_helper.c b/target/sparc/fop_helper.c index 1b524c6d3c..0b30665b51 100644 --- a/target/sparc/fop_helper.c +++ b/target/sparc/fop_helper.c @@ -602,3 +602,9 @@ void helper_set_fsr_nofcc_noftt(CPUSPARCState *env, uin= t32_t fsr) env->fsr_cexc_ftt |=3D fsr & FSR_CEXC_MASK; set_fsr_nonsplit(env, fsr); } + +void helper_set_fsr_nofcc(CPUSPARCState *env, uint32_t fsr) +{ + env->fsr_cexc_ftt =3D fsr & (FSR_CEXC_MASK | FSR_FTT_MASK); + set_fsr_nonsplit(env, fsr); +} diff --git a/target/sparc/translate.c b/target/sparc/translate.c index ade9df3960..e3059f32bb 100644 --- a/target/sparc/translate.c +++ b/target/sparc/translate.c @@ -4458,7 +4458,7 @@ static bool trans_LDFSR(DisasContext *dc, arg_r_r_ri = *a) return advance_pc(dc); } =20 -static bool trans_LDXFSR(DisasContext *dc, arg_r_r_ri *a) +static bool do_ldxfsr(DisasContext *dc, arg_r_r_ri *a, bool entire) { #ifdef TARGET_SPARC64 TCGv addr =3D gen_ldst_addr(dc, a->rs1, a->imm, a->rs2_or_imm); @@ -4483,13 +4483,20 @@ static bool trans_LDXFSR(DisasContext *dc, arg_r_r_= ri *a) tcg_gen_extract_i32(cpu_fcc[2], hi, FSR_FCC2_SHIFT - 32, 2); tcg_gen_extract_i32(cpu_fcc[3], hi, FSR_FCC3_SHIFT - 32, 2); =20 - gen_helper_set_fsr_nofcc_noftt(tcg_env, lo); + if (entire) { + gen_helper_set_fsr_nofcc(tcg_env, lo); + } else { + gen_helper_set_fsr_nofcc_noftt(tcg_env, lo); + } return advance_pc(dc); #else return false; #endif } =20 +TRANS(LDXFSR, 64, do_ldxfsr, a, false) +TRANS(LDXEFSR, VIS3B, do_ldxfsr, a, true) + static bool do_stfsr(DisasContext *dc, arg_r_r_ri *a, MemOp mop) { TCGv addr =3D gen_ldst_addr(dc, a->rs1, a->imm, a->rs2_or_imm); --=20 2.34.1 From nobody Mon Nov 25 08:36:39 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1716752633; cv=none; d=zohomail.com; s=zohoarc; b=C5DLB6tqIBlkwC4D8H9heQzEDQ/JWIhXwM8Bgt/FzGRRgw7fK/DOqZ6lrYscD8/xkFq6qzYKLYBLCuD0oV5jKhyppHT6MIb+oZAlhROZZjRn6JEgF6cynPiDkx497i5uzRJuHks+UacK9LALV242o1QvlXA2kLp015lEyrVRifw= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1716752633; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; 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} =20 +static void gen_op_lzcnt(TCGv dst, TCGv src) +{ + tcg_gen_clzi_tl(dst, src, TARGET_LONG_BITS); +} + #ifndef TARGET_SPARC64 static void gen_helper_array8(TCGv dst, TCGv src1, TCGv src2) { @@ -3873,6 +3878,19 @@ TRANS(EDGE16LN, VIS2, gen_edge, a, 16, 0, 1) TRANS(EDGE32N, VIS2, gen_edge, a, 32, 0, 0) TRANS(EDGE32LN, VIS2, gen_edge, a, 32, 0, 1) =20 +static bool do_rr(DisasContext *dc, arg_r_r *a, + void (*func)(TCGv, TCGv)) +{ + TCGv dst =3D gen_dest_gpr(dc, a->rd); + TCGv src =3D gen_load_gpr(dc, a->rs); + + func(dst, src); + gen_store_gpr(dc, a->rd, dst); + return advance_pc(dc); +} + +TRANS(LZCNT, VIS3, do_rr, a, gen_op_lzcnt) + static bool do_rrr(DisasContext *dc, arg_r_r_r *a, void (*func)(TCGv, TCGv, TCGv)) { --=20 2.34.1 From nobody Mon Nov 25 08:36:39 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::634; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x634.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1716752961122100008 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daud=C3=A9 Tested-by: Mark Cave-Ayland --- target/sparc/insns.decode | 6 ++++++ target/sparc/translate.c | 36 ++++++++++++++++++++++++++++++++++++ 2 files changed, 42 insertions(+) diff --git a/target/sparc/insns.decode b/target/sparc/insns.decode index 4766964893..e0e9248982 100644 --- a/target/sparc/insns.decode +++ b/target/sparc/insns.decode @@ -498,6 +498,12 @@ FCMPEq 10 000 cc:2 110101 ..... 0 0101 0111 ....= . \ FONEd 10 ..... 110110 00000 0 0111 1110 00000 rd=3D%dfp_rd FONEs 10 rd:5 110110 00000 0 0111 1111 00000 =20 + MOVsTOuw 10 ..... 110110 00000 1 0001 0001 ..... @r_r2 + MOVsTOsw 10 ..... 110110 00000 1 0001 0011 ..... @r_r2 + MOVwTOs 10 ..... 110110 00000 1 0001 1001 ..... @r_r2 + MOVdTOx 10 ..... 110110 00000 1 0001 0000 ..... @r_d2 + MOVxTOd 10 ..... 110110 00000 1 0001 1000 ..... @d_r2 + FLCMPs 10 000 cc:2 110110 rs1:5 1 0101 0001 rs2:5 FLCMPd 10 000 cc:2 110110 ..... 1 0101 0010 ..... \ rs1=3D%dfp_rs1 rs2=3D%dfp_rs2 diff --git a/target/sparc/translate.c b/target/sparc/translate.c index 705fcb028a..d8707326ff 100644 --- a/target/sparc/translate.c +++ b/target/sparc/translate.c @@ -5397,6 +5397,42 @@ static bool trans_FLCMPd(DisasContext *dc, arg_FLCMP= d *a) return advance_pc(dc); } =20 +static bool do_movf2r(DisasContext *dc, arg_r_r *a, + int (*offset)(unsigned int), + void (*load)(TCGv, TCGv_ptr, tcg_target_long)) +{ + TCGv dst; + + if (gen_trap_ifnofpu(dc)) { + return true; + } + dst =3D gen_dest_gpr(dc, a->rd); + load(dst, tcg_env, offset(a->rs)); + gen_store_gpr(dc, a->rd, dst); + return advance_pc(dc); +} + +TRANS(MOVsTOsw, VIS3B, do_movf2r, a, gen_offset_fpr_F, tcg_gen_ld32s_tl) +TRANS(MOVsTOuw, VIS3B, do_movf2r, a, gen_offset_fpr_F, tcg_gen_ld32u_tl) +TRANS(MOVdTOx, VIS3B, do_movf2r, a, gen_offset_fpr_D, tcg_gen_ld_tl) + +static bool do_movr2f(DisasContext *dc, arg_r_r *a, + int (*offset)(unsigned int), + void (*store)(TCGv, TCGv_ptr, tcg_target_long)) +{ + TCGv src; + + if (gen_trap_ifnofpu(dc)) { + return true; + } + src =3D gen_load_gpr(dc, a->rs); + store(src, tcg_env, offset(a->rd)); + return advance_pc(dc); +} + +TRANS(MOVwTOs, VIS3B, do_movr2f, a, gen_offset_fpr_F, tcg_gen_st32_tl) +TRANS(MOVxTOd, VIS3B, do_movr2f, a, gen_offset_fpr_D, tcg_gen_st_tl) + static void sparc_tr_init_disas_context(DisasContextBase *dcbase, CPUState= *cs) { DisasContext *dc =3D container_of(dcbase, DisasContext, base); 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[174.21.72.5]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-1f46ad93c2esm28165935ad.263.2024.05.26.12.43.13 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 26 May 2024 12:43:14 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1716752594; x=1717357394; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=ugmNTqEcbc+4V4tkmecPzyQ/Hi7IU9jDHpaQmAFPBps=; b=gPG6HcUiZzeY2VItFIJeJR9bzwbvgD8lExH1Tq3OiehkdZz3CY8TWy+rKRekKC1af4 iFFAZmPSxPemi1sG3CtPW5URxnflKpZ2ivlSeNDuF7xETBlg7tybqz0p5yisjHLrvwjQ ZNEBBFFlihHd3n6vmYfw8cbrkAtbdquhLpDk43XuHh1i65AHt/i0gyt1NyAzKE7EbJEW WWZormBS8aLHZFyusEnCvGdto7pf9q6yESEW+5ku9NaZOQwZAQfjEUigM2kA91uAnrjg TUcMIi6nF4aP4lZxDTOWRCMaMzeEHjpSs4fOg7n2ZQ8Up3pO6s7iK/EIzfZQqYTEzuoc v9Ew== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1716752594; x=1717357394; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::62b; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1716752866726100008 Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Richard Henderson Tested-by: Mark Cave-Ayland --- target/sparc/insns.decode | 1 + target/sparc/translate.c | 11 +++++++++++ 2 files changed, 12 insertions(+) diff --git a/target/sparc/insns.decode b/target/sparc/insns.decode index e0e9248982..09c8adca37 100644 --- a/target/sparc/insns.decode +++ b/target/sparc/insns.decode @@ -435,6 +435,7 @@ FCMPEq 10 000 cc:2 110101 ..... 0 0101 0111 .....= \ FPACKFIX 10 ..... 110110 00000 0 0011 1101 ..... @r_d2 PDIST 10 ..... 110110 ..... 0 0011 1110 ..... \ &r_r_r_r rd=3D%dfp_rd rs1=3D%dfp_rd rs2=3D%dfp_rs1 rs3=3D%= dfp_rs2 + PDISTN 10 ..... 110110 ..... 0 0011 1111 ..... @r_d_d =20 FMEAN16 10 ..... 110110 ..... 0 0100 0000 ..... @d_d_d FCHKSM16 10 ..... 110110 ..... 0 0100 0100 ..... @d_d_d diff --git a/target/sparc/translate.c b/target/sparc/translate.c index d8707326ff..313adcd95b 100644 --- a/target/sparc/translate.c +++ b/target/sparc/translate.c @@ -817,6 +817,15 @@ static void gen_op_bshuffle(TCGv_i64 dst, TCGv_i64 src= 1, TCGv_i64 src2) #endif } =20 +static void gen_op_pdistn(TCGv dst, TCGv_i64 src1, TCGv_i64 src2) +{ +#ifdef TARGET_SPARC64 + gen_helper_pdist(dst, tcg_constant_i64(0), src1, src2); +#else + g_assert_not_reached(); +#endif +} + static void gen_op_fmul8x16al(TCGv_i64 dst, TCGv_i32 src1, TCGv_i32 src2) { tcg_gen_ext16s_i32(src2, src2); @@ -5066,6 +5075,8 @@ TRANS(FPCMPNE8, VIS3B, do_rdd, a, gen_helper_fcmpne8) TRANS(FPCMPULE8, VIS3B, do_rdd, a, gen_helper_fcmpule8) TRANS(FPCMPUGT8, VIS3B, do_rdd, a, gen_helper_fcmpugt8) =20 +TRANS(PDISTN, VIS3, do_rdd, a, gen_op_pdistn) + static bool do_env_ddd(DisasContext *dc, arg_r_r_r *a, void (*func)(TCGv_i64, TCGv_env, TCGv_i64, TCGv_i64= )) { --=20 2.34.1 From nobody Mon Nov 25 08:36:39 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1716752866; cv=none; d=zohomail.com; s=zohoarc; b=Y2hr7siOzTk4sFqtadfJwoGUpNBGhZDrx5uIVRLNYlTTQWFyclIWCDXmtbDWnCYLp2zN07e54H9OMH+PMF8UYwCAn9M9T6cwQAI2/X/rzutvY75zRZptlfugnBuw7MhiWH4bVs9vlZl16Xxgd/h8cqdzIKHrcmeyZoh5O0Uvf0A= ARC-Message-Signature: i=1; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::62c; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1716752866747100011 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daud=C3=A9 Tested-by: Mark Cave-Ayland --- target/sparc/insns.decode | 1 + target/sparc/translate.c | 8 ++++++++ 2 files changed, 9 insertions(+) diff --git a/target/sparc/insns.decode b/target/sparc/insns.decode index 09c8adca37..508175eccd 100644 --- a/target/sparc/insns.decode +++ b/target/sparc/insns.decode @@ -389,6 +389,7 @@ FCMPEq 10 000 cc:2 110101 ..... 0 0101 0111 .....= \ =20 ADDXC 10 ..... 110110 ..... 0 0001 0001 ..... @r_r_r ADDXCcc 10 ..... 110110 ..... 0 0001 0011 ..... @r_r_r + UMULXHI 10 ..... 110110 ..... 0 0001 0110 ..... @r_r_r LZCNT 10 ..... 110110 00000 0 0001 0111 ..... @r_r2 =20 ALIGNADDR 10 ..... 110110 ..... 0 0001 1000 ..... @r_r_r diff --git a/target/sparc/translate.c b/target/sparc/translate.c index 313adcd95b..7bf1e7687e 100644 --- a/target/sparc/translate.c +++ b/target/sparc/translate.c @@ -581,6 +581,12 @@ static void gen_op_smul(TCGv dst, TCGv src1, TCGv src2) gen_op_multiply(dst, src1, src2, 1); } =20 +static void gen_op_umulxhi(TCGv dst, TCGv src1, TCGv src2) +{ + TCGv discard =3D tcg_temp_new(); + tcg_gen_mulu2_tl(discard, dst, src1, src2); +} + static void gen_op_sdiv(TCGv dst, TCGv src1, TCGv src2) { #ifdef TARGET_SPARC64 @@ -3919,6 +3925,8 @@ TRANS(ARRAY32, VIS1, do_rrr, a, gen_op_array32) TRANS(ADDXC, VIS3, do_rrr, a, gen_op_addxc) TRANS(ADDXCcc, VIS3, do_rrr, a, gen_op_addxccc) =20 +TRANS(UMULXHI, VIS3, do_rrr, a, gen_op_umulxhi) + static void gen_op_alignaddr(TCGv dst, TCGv s1, TCGv s2) { #ifdef TARGET_SPARC64 --=20 2.34.1 From nobody Mon Nov 25 08:36:39 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1716752832; cv=none; d=zohomail.com; s=zohoarc; b=VJs+mYwPFfR8kXM4iJS9iVWp1IdoAtyCbk5BKb60Q3PfwGXQmpshG85KotMZwlx5tuCo/gXhorWP4vszv7uM2HwW3rvwY0b2OArCF8i94dIOnm4sM4UEFmjUeVXZL4JIRVNdaoiVjr3jdv58SGwD4QFyvQijqGFKDKNamR2MTEU= ARC-Message-Signature: i=1; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::633; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x633.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1716752834596100011 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daud=C3=A9 Tested-by: Mark Cave-Ayland --- target/sparc/helper.h | 2 ++ target/sparc/insns.decode | 2 ++ target/sparc/translate.c | 4 ++++ target/sparc/vis_helper.c | 11 +++++++++++ 4 files changed, 19 insertions(+) diff --git a/target/sparc/helper.h b/target/sparc/helper.h index 4ae97866af..fe0d8bc593 100644 --- a/target/sparc/helper.h +++ b/target/sparc/helper.h @@ -135,6 +135,8 @@ DEF_HELPER_FLAGS_2(fcmpeq8, TCG_CALL_NO_RWG_SE, i64, i6= 4, i64) DEF_HELPER_FLAGS_2(fcmpne8, TCG_CALL_NO_RWG_SE, i64, i64, i64) DEF_HELPER_FLAGS_2(fcmpule8, TCG_CALL_NO_RWG_SE, i64, i64, i64) DEF_HELPER_FLAGS_2(fcmpugt8, TCG_CALL_NO_RWG_SE, i64, i64, i64) +DEF_HELPER_FLAGS_2(xmulx, TCG_CALL_NO_RWG_SE, i64, i64, i64) +DEF_HELPER_FLAGS_2(xmulxhi, TCG_CALL_NO_RWG_SE, i64, i64, i64) #endif #undef VIS_HELPER #undef VIS_CMPHELPER diff --git a/target/sparc/insns.decode b/target/sparc/insns.decode index 508175eccd..1d54de5367 100644 --- a/target/sparc/insns.decode +++ b/target/sparc/insns.decode @@ -391,6 +391,8 @@ FCMPEq 10 000 cc:2 110101 ..... 0 0101 0111 .....= \ ADDXCcc 10 ..... 110110 ..... 0 0001 0011 ..... @r_r_r UMULXHI 10 ..... 110110 ..... 0 0001 0110 ..... @r_r_r LZCNT 10 ..... 110110 00000 0 0001 0111 ..... @r_r2 + XMULX 10 ..... 110110 ..... 1 0001 0101 ..... @r_r_r + XMULXHI 10 ..... 110110 ..... 1 0001 0110 ..... @r_r_r =20 ALIGNADDR 10 ..... 110110 ..... 0 0001 1000 ..... @r_r_r ALIGNADDRL 10 ..... 110110 ..... 0 0001 1010 ..... @r_r_r diff --git a/target/sparc/translate.c b/target/sparc/translate.c index 7bf1e7687e..11c933af75 100644 --- a/target/sparc/translate.c +++ b/target/sparc/translate.c @@ -90,6 +90,8 @@ # define gen_helper_fxtoq ({ qemu_build_not_reached(); NULL= ; }) # define gen_helper_fxtos ({ qemu_build_not_reached(); NULL= ; }) # define gen_helper_pdist ({ qemu_build_not_reached(); NULL= ; }) +# define gen_helper_xmulx ({ qemu_build_not_reached(); NULL= ; }) +# define gen_helper_xmulxhi ({ qemu_build_not_reached(); NULL= ; }) # define MAXTL_MASK 0 #endif =20 @@ -5084,6 +5086,8 @@ TRANS(FPCMPULE8, VIS3B, do_rdd, a, gen_helper_fcmpule= 8) TRANS(FPCMPUGT8, VIS3B, do_rdd, a, gen_helper_fcmpugt8) =20 TRANS(PDISTN, VIS3, do_rdd, a, gen_op_pdistn) +TRANS(XMULX, VIS3, do_rrr, a, gen_helper_xmulx) +TRANS(XMULXHI, VIS3, do_rrr, a, gen_helper_xmulxhi) =20 static bool do_env_ddd(DisasContext *dc, arg_r_r_r *a, void (*func)(TCGv_i64, TCGv_env, TCGv_i64, TCGv_i64= )) diff --git a/target/sparc/vis_helper.c b/target/sparc/vis_helper.c index c21522c533..c927a054b8 100644 --- a/target/sparc/vis_helper.c +++ b/target/sparc/vis_helper.c @@ -20,6 +20,7 @@ #include "qemu/osdep.h" #include "cpu.h" #include "exec/helper-proto.h" +#include "crypto/clmul.h" =20 target_ulong helper_array8(target_ulong rs1, target_ulong rs2) { @@ -509,3 +510,13 @@ uint64_t helper_fslas32(uint64_t src1, uint64_t src2) =20 return r.ll; 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[174.21.72.5]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-1f46ad93c2esm28165935ad.263.2024.05.26.12.43.16 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 26 May 2024 12:43:16 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1716752597; x=1717357397; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=uEc4KP3uZvO6wOyhGM6ZesqZxEK0BedjSL132wzrDtA=; b=faDNAr/JUlaqxWf1o/wW0T8u8WV63oQ2fFcObkkNMnnYqKpR/y0IKKwG1Tis0debMP 79uxu6cZNmh4VinBPTvUNbQDpg3LSBAVawRLcCS3TBkqooCsG6qwhmuEAHJF2ROAgRtx 5DvTOfuAL18gJFZemo4Fv+BU1IzcvRMlbFDTh3GUGwmdqk4cgqJYoIplPt+EqspFTKSc W7PNYKMod2LkCVEVNppCmfhImqa5rKTxIp3YtpcCgSwff1luB9SNMB6e3xKkmA7fRy2D ikiGWoe8AuXDtbgUrI18M3RG3bEj9TPRjmLy1s5nu/EUjrSoGRzTdPKoNq1kqSTvXL7X p1rA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1716752597; x=1717357397; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=uEc4KP3uZvO6wOyhGM6ZesqZxEK0BedjSL132wzrDtA=; b=RzmFCiey1w+MQw6O8jJ8YQG4gFKSJXyc3eKFdBWBJ4ekfdXdtS7xMh0XXOpsa7UwPe PLk1xffBMEPAaWK/OHFuW6ZTqSeRrKkYliHtRUnU0d2w5wO0J6J1sz2GIImMT5N5VMhw RDs94p3mGBA3O+q1+oFfI/+rUoPEtXoFIJbEd1IGL1waQ+u9sX1QJNcpqJrugqq9H3Ru jD5gjosaTPVo45Cf2seeZhnzqF/S0A2wvweELGDhkK4vS13FRX9DCFjkOPFEURu3GAFp nWd9MC37doe7abkicPIl8uTzbq2fh2qee2nRq1K4875AzTfwcbyCvw3H/Iq8YKGB4zKE vgYw== X-Gm-Message-State: AOJu0YxiB8biRoUOhDWXmDNg81xzcCdgtbWL9KRwpl7fwe3c5+hezPBw 39NmlXdwG6yH+Y9QdlwAVnL0FI11yboIO6CDPhnxgI5prG63pE8reQBfx0kfvzYb4WfbTNc0b1j 4 X-Google-Smtp-Source: AGHT+IHKlaFVk+g52xNULxBSjuTL9grownHGDrkvFfsj92kqsZMFw/4RWfagM5TsMLnzoVxae4mcNw== X-Received: by 2002:a17:903:22d2:b0:1f4:64d9:5cfd with SMTP id d9443c01a7336-1f464d96071mr60181705ad.42.1716752596796; Sun, 26 May 2024 12:43:16 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: mark.cave-ayland@ilande.co.uk Subject: [PATCH v2 27/37] target/sparc: Enable VIS3 feature bit Date: Sun, 26 May 2024 12:42:44 -0700 Message-Id: <20240526194254.459395-28-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240526194254.459395-1-richard.henderson@linaro.org> References: <20240526194254.459395-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::536; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x536.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1716752669966100011 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daud=C3=A9 Tested-by: Mark Cave-Ayland --- linux-user/elfload.c | 1 + target/sparc/cpu.c | 3 +++ 2 files changed, 4 insertions(+) diff --git a/linux-user/elfload.c b/linux-user/elfload.c index 6a1457346a..cb79580431 100644 --- a/linux-user/elfload.c +++ b/linux-user/elfload.c @@ -1004,6 +1004,7 @@ static uint32_t get_elf_hwcap(void) r |=3D features & CPU_FEATURE_VIS1 ? HWCAP_SPARC_VIS : 0; r |=3D features & CPU_FEATURE_VIS2 ? HWCAP_SPARC_VIS2 : 0; r |=3D features & CPU_FEATURE_FMAF ? HWCAP_SPARC_FMAF : 0; + r |=3D features & CPU_FEATURE_VIS3 ? HWCAP_SPARC_VIS3 : 0; #endif =20 return r; diff --git a/target/sparc/cpu.c b/target/sparc/cpu.c index ed9238a69d..8ea977b49f 100644 --- a/target/sparc/cpu.c +++ b/target/sparc/cpu.c @@ -550,6 +550,7 @@ static const char * const feature_name[] =3D { [CPU_FEATURE_BIT_VIS1] =3D "vis1", [CPU_FEATURE_BIT_VIS2] =3D "vis2", [CPU_FEATURE_BIT_FMAF] =3D "fmaf", + [CPU_FEATURE_BIT_VIS3] =3D "vis3", #else [CPU_FEATURE_BIT_MUL] =3D "mul", [CPU_FEATURE_BIT_DIV] =3D "div", @@ -880,6 +881,8 @@ static Property sparc_cpu_properties[] =3D { CPU_FEATURE_BIT_VIS2, false), DEFINE_PROP_BIT("fmaf", SPARCCPU, env.def.features, CPU_FEATURE_BIT_FMAF, false), + DEFINE_PROP_BIT("vis3", SPARCCPU, env.def.features, + CPU_FEATURE_BIT_VIS3, false), #else DEFINE_PROP_BIT("mul", SPARCCPU, env.def.features, CPU_FEATURE_BIT_MUL, false), --=20 2.34.1 From nobody Mon Nov 25 08:36:39 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1716752725; cv=none; d=zohomail.com; s=zohoarc; b=RDyjTzzR2PIEWeK81aYchNnLWbQJM+9Ef4GG8Bgm6PYhmfmDk/I6d4i/POYig0C5GkWWbGHvOtoy6KXaysfL6kPQBwbLXwRtPpSmPKB7inmgt+1GF8h5jZDC6L7eb0X05lqDbHNbiJRFlU4OzpKjrZtavLCQ7GgaYFc+kg9P13k= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1716752725; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=D27xq2Y43YVNQtkiZr5NocypDcRhStz8cpDNJ2SQ+Oc=; b=ZjivAkwU0SDRKmEdcW+tdFf3cR+QPSSMBBPExjuQ3QAoJilgKVxN20xWXzV74cir8A5XP5VeX6XqEHN6kUCt+toqtTlHdEMGikvf4wxXmKc4datFvFU8tIBhzIZrbWUPGsI9WpwC/bXVz3SPR8vOWcva/jq5Mn8cEk+WEJGSM9A= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1716752725306817.1030801148713; Sun, 26 May 2024 12:45:25 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1sBJmA-0000F7-N5; Sun, 26 May 2024 15:43:26 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1sBJm4-00006o-Oy for qemu-devel@nongnu.org; Sun, 26 May 2024 15:43:20 -0400 Received: from mail-pl1-x635.google.com ([2607:f8b0:4864:20::635]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1sBJm2-0007kY-Tn for qemu-devel@nongnu.org; Sun, 26 May 2024 15:43:20 -0400 Received: by mail-pl1-x635.google.com with SMTP id d9443c01a7336-1f44b594deeso17711675ad.2 for ; Sun, 26 May 2024 12:43:18 -0700 (PDT) Received: from stoup.. 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[174.21.72.5]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-1f46ad93c2esm28165935ad.263.2024.05.26.12.43.17 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 26 May 2024 12:43:17 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1716752598; x=1717357398; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=D27xq2Y43YVNQtkiZr5NocypDcRhStz8cpDNJ2SQ+Oc=; b=Ho16WR+mssBYpJRGLckudX2yKk6wK4IduPgYV0Xx6WLXNDeDCNau219vRYi9UQfs3f 2sDLFFwtkjGTd3RlV1hK78xmUv0jcPugu9bcWkmJk79AxVRXNTp6xFVdYzsBppcuTvdM 8JkqgRTcmzzKAxH0Q1ILhyou6KbsviGK7mwf8klr3o42I088ufPAb0SQrICyJwqxuUFj ZU1Ien4Mpkswq8fLznwXsQW4EIGUmwRHmZ03fm+sLMLiDHx7jOnDZMjHpSJCHrQyqhap e7C3Vl4EBxwEDzoBRNEMLAqY9EBw+/M40tOOiFwJdb44u49Nc2asQf9dIcQ3Nj5Sxwxb iEuQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1716752598; x=1717357398; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=D27xq2Y43YVNQtkiZr5NocypDcRhStz8cpDNJ2SQ+Oc=; b=sAGAG5jSeJZFcTvdnNGgG5YvZhYKVoxp0bArFC+21kv97zP4cT5fYnTNLhZlWzUnm+ fqFzeUWXgEExGwdoa++eZ+GRLCn/NrCfRmDosgmwwq0kxatPk/2Fh+k7Pgo/hEm/jRah +bRNuDX4e0EZ+nX4rK7gR8IwDsxVLy0WRLBgG+LSwA0zlGld0xHBqkDQmHbtfmLyquYg in2yduTxh/j1KimZPagyyQEyq9z2/10BXiDzy/28yqZXaDEfECW39XJTiCVbyc2e28xR nWgaXMvyzXqRW7UJEFWgpPdC1fnUe1EgBWhylPMXatfp/fTgG7+TRceCoi/UnuYvrGPB J8Iw== X-Gm-Message-State: AOJu0Yw3KyoiWv7W4EG5riRmBrSR5qXaEjdov6Ya72z8GYQW/Kl1WrYl YW7Ql1t47eIm/Y+3M15nSD+BK6pv/f3NdAhHwILbfuPjzLl5pBSVELKbwVB2dLnrmFCZAdfLVfW D X-Google-Smtp-Source: AGHT+IF6IMDr2R6tgHsyvz3NEJ+hMjos7+JS9TdiaStUl9ZlnU0sVu27EWBdjnbem9qWoXnurPsfQg== X-Received: by 2002:a17:902:c94c:b0:1f4:92bb:6604 with SMTP id d9443c01a7336-1f492bb660cmr14213605ad.20.1716752597631; Sun, 26 May 2024 12:43:17 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: mark.cave-ayland@ilande.co.uk, =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH v2 28/37] target/sparc: Implement IMA extension Date: Sun, 26 May 2024 12:42:45 -0700 Message-Id: <20240526194254.459395-29-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240526194254.459395-1-richard.henderson@linaro.org> References: <20240526194254.459395-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::635; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x635.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1716752726195100003 Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Richard Henderson Tested-by: Mark Cave-Ayland --- target/sparc/cpu-feature.h.inc | 1 + target/sparc/insns.decode | 3 +++ linux-user/elfload.c | 1 + target/sparc/cpu.c | 3 +++ target/sparc/translate.c | 24 ++++++++++++++++++++++++ 5 files changed, 32 insertions(+) diff --git a/target/sparc/cpu-feature.h.inc b/target/sparc/cpu-feature.h.inc index 3913fb4a54..e2e6de9144 100644 --- a/target/sparc/cpu-feature.h.inc +++ b/target/sparc/cpu-feature.h.inc @@ -14,3 +14,4 @@ FEATURE(POWERDOWN) FEATURE(CASA) FEATURE(FMAF) FEATURE(VIS3) +FEATURE(IMA) diff --git a/target/sparc/insns.decode b/target/sparc/insns.decode index 1d54de5367..5d85e124ed 100644 --- a/target/sparc/insns.decode +++ b/target/sparc/insns.decode @@ -525,6 +525,9 @@ FCMPEq 10 000 cc:2 110101 ..... 0 0101 0111 .....= \ FNMSUBd 10 ..... 110111 ..... ..... 1010 ..... @d_d_d_d FNMADDs 10 ..... 110111 ..... ..... 1101 ..... @r_r_r_r FNMADDd 10 ..... 110111 ..... ..... 1110 ..... @d_d_d_d + + FPMADDX 10 ..... 110111 ..... ..... 0000 ..... @d_d_d_d + FPMADDXHI 10 ..... 110111 ..... ..... 0100 ..... @d_d_d_d ] NCP 10 ----- 110111 ----- --------- ----- # v8 CPop2 } diff --git a/linux-user/elfload.c b/linux-user/elfload.c index cb79580431..0d4dc1f6d1 100644 --- a/linux-user/elfload.c +++ b/linux-user/elfload.c @@ -1005,6 +1005,7 @@ static uint32_t get_elf_hwcap(void) r |=3D features & CPU_FEATURE_VIS2 ? HWCAP_SPARC_VIS2 : 0; r |=3D features & CPU_FEATURE_FMAF ? HWCAP_SPARC_FMAF : 0; r |=3D features & CPU_FEATURE_VIS3 ? HWCAP_SPARC_VIS3 : 0; + r |=3D features & CPU_FEATURE_IMA ? HWCAP_SPARC_IMA : 0; #endif =20 return r; diff --git a/target/sparc/cpu.c b/target/sparc/cpu.c index 8ea977b49f..88da5254e8 100644 --- a/target/sparc/cpu.c +++ b/target/sparc/cpu.c @@ -551,6 +551,7 @@ static const char * const feature_name[] =3D { [CPU_FEATURE_BIT_VIS2] =3D "vis2", [CPU_FEATURE_BIT_FMAF] =3D "fmaf", [CPU_FEATURE_BIT_VIS3] =3D "vis3", + [CPU_FEATURE_BIT_IMA] =3D "ima", #else [CPU_FEATURE_BIT_MUL] =3D "mul", [CPU_FEATURE_BIT_DIV] =3D "div", @@ -883,6 +884,8 @@ static Property sparc_cpu_properties[] =3D { CPU_FEATURE_BIT_FMAF, false), DEFINE_PROP_BIT("vis3", SPARCCPU, env.def.features, CPU_FEATURE_BIT_VIS3, false), + DEFINE_PROP_BIT("ima", SPARCCPU, env.def.features, + CPU_FEATURE_BIT_IMA, false), #else DEFINE_PROP_BIT("mul", SPARCCPU, env.def.features, CPU_FEATURE_BIT_MUL, false), diff --git a/target/sparc/translate.c b/target/sparc/translate.c index 11c933af75..d47e1defc1 100644 --- a/target/sparc/translate.c +++ b/target/sparc/translate.c @@ -589,6 +589,26 @@ static void gen_op_umulxhi(TCGv dst, TCGv src1, TCGv s= rc2) tcg_gen_mulu2_tl(discard, dst, src1, src2); } =20 +static void gen_op_fpmaddx(TCGv_i64 dst, TCGv_i64 src1, + TCGv_i64 src2, TCGv_i64 src3) +{ + TCGv_i64 t =3D tcg_temp_new_i64(); + + tcg_gen_mul_i64(t, src1, src2); + tcg_gen_add_i64(dst, src3, t); +} + +static void gen_op_fpmaddxhi(TCGv_i64 dst, TCGv_i64 src1, + TCGv_i64 src2, TCGv_i64 src3) +{ + TCGv_i64 l =3D tcg_temp_new_i64(); + TCGv_i64 h =3D tcg_temp_new_i64(); + TCGv_i64 z =3D tcg_constant_i64(0); + + tcg_gen_mulu2_i64(l, h, src1, src2); + tcg_gen_add2_i64(l, dst, l, h, src3, z); +} + static void gen_op_sdiv(TCGv dst, TCGv src1, TCGv src2) { #ifdef TARGET_SPARC64 @@ -2405,6 +2425,7 @@ static int extract_qfpreg(DisasContext *dc, int x) # define avail_FMAF(C) ((C)->def->features & CPU_FEATURE_FMAF) # define avail_GL(C) ((C)->def->features & CPU_FEATURE_GL) # define avail_HYPV(C) ((C)->def->features & CPU_FEATURE_HYPV) +# define avail_IMA(C) ((C)->def->features & CPU_FEATURE_IMA) # define avail_VIS1(C) ((C)->def->features & CPU_FEATURE_VIS1) # define avail_VIS2(C) ((C)->def->features & CPU_FEATURE_VIS2) # define avail_VIS3(C) ((C)->def->features & CPU_FEATURE_VIS3) @@ -2420,6 +2441,7 @@ static int extract_qfpreg(DisasContext *dc, int x) # define avail_FMAF(C) false # define avail_GL(C) false # define avail_HYPV(C) false +# define avail_IMA(C) false # define avail_VIS1(C) false # define avail_VIS2(C) false # define avail_VIS3(C) false @@ -5198,6 +5220,8 @@ TRANS(FMADDd, FMAF, do_dddd, a, gen_op_fmaddd) TRANS(FMSUBd, FMAF, do_dddd, a, gen_op_fmsubd) TRANS(FNMSUBd, FMAF, do_dddd, a, gen_op_fnmsubd) TRANS(FNMADDd, FMAF, do_dddd, a, gen_op_fnmaddd) +TRANS(FPMADDX, IMA, do_dddd, a, gen_op_fpmaddx) +TRANS(FPMADDXHI, IMA, do_dddd, a, gen_op_fpmaddxhi) =20 static bool do_env_qqq(DisasContext *dc, arg_r_r_r *a, void (*func)(TCGv_i128, TCGv_env, TCGv_i128, TCGv_i= 128)) --=20 2.34.1 From nobody Mon Nov 25 08:36:39 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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[174.21.72.5]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-1f46ad93c2esm28165935ad.263.2024.05.26.12.43.17 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 26 May 2024 12:43:17 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1716752598; x=1717357398; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=+2jVhYHBRn12F1/nF34lAzP9rRGex3+gOE8jz3RmZzU=; b=Whc4Bn6kkZBEU2E6k2IECguXOmzTILRQDdKm8LbV/zZoQVp39OsJ0rtLXaigv9uKyb B1lXEVjA4KVfYCbIqn94QNHGGvw6iAxLCnFR40n3cnQoI3oGcN9w3fbrgx5W91OD1g4C JiCxfn8SAywcRD4FGHvGAFba3THifO6GQK3TmKFjXCTpad3Q/PQx+hCAnMUPVB0ny1Lg eupxm5Ze4y3PhWIkRrhqeFqCvmUX6Xwod0KjFI457HuucSBDkeEF0o6lsrJb+0zo1cv3 qtkvJPKTpdoA8SKx4oU/vNynf7olSaDFLPf1IseB0nwNi97VVYB6Vsm1IvDdROKyepGp VwCQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1716752598; x=1717357398; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::62e; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1716752635897100005 Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Richard Henderson Tested-by: Mark Cave-Ayland --- target/sparc/cpu-feature.h.inc | 1 + target/sparc/translate.c | 2 ++ 2 files changed, 3 insertions(+) diff --git a/target/sparc/cpu-feature.h.inc b/target/sparc/cpu-feature.h.inc index e2e6de9144..be81005237 100644 --- a/target/sparc/cpu-feature.h.inc +++ b/target/sparc/cpu-feature.h.inc @@ -15,3 +15,4 @@ FEATURE(CASA) FEATURE(FMAF) FEATURE(VIS3) FEATURE(IMA) +FEATURE(VIS4) diff --git a/target/sparc/translate.c b/target/sparc/translate.c index d47e1defc1..88e6da4f8b 100644 --- a/target/sparc/translate.c +++ b/target/sparc/translate.c @@ -2430,6 +2430,7 @@ static int extract_qfpreg(DisasContext *dc, int x) # define avail_VIS2(C) ((C)->def->features & CPU_FEATURE_VIS2) # define avail_VIS3(C) ((C)->def->features & CPU_FEATURE_VIS3) # define avail_VIS3B(C) avail_VIS3(C) +# define avail_VIS4(C) ((C)->def->features & CPU_FEATURE_VIS4) #else # define avail_32(C) true # define avail_ASR17(C) ((C)->def->features & CPU_FEATURE_ASR17) @@ -2446,6 +2447,7 @@ static int extract_qfpreg(DisasContext *dc, int x) # define avail_VIS2(C) false # define avail_VIS3(C) false # define avail_VIS3B(C) false +# define avail_VIS4(C) false #endif =20 /* Default case for non jump instructions. */ --=20 2.34.1 From nobody Mon Nov 25 08:36:39 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::633; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x633.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1716752870709100023 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daud=C3=A9 Tested-by: Mark Cave-Ayland --- target/sparc/insns.decode | 1 + target/sparc/translate.c | 33 ++++++++++++++++++++++++++++++--- 2 files changed, 31 insertions(+), 3 deletions(-) diff --git a/target/sparc/insns.decode b/target/sparc/insns.decode index 5d85e124ed..0913fe7a86 100644 --- a/target/sparc/insns.decode +++ b/target/sparc/insns.decode @@ -446,6 +446,7 @@ FCMPEq 10 000 cc:2 110101 ..... 0 0101 0111 .....= \ FPMERGE 10 ..... 110110 ..... 0 0100 1011 ..... @d_r_r BSHUFFLE 10 ..... 110110 ..... 0 0100 1100 ..... @d_d_d FEXPAND 10 ..... 110110 00000 0 0100 1101 ..... @d_r2 + FALIGNDATAi 10 ..... 110110 ..... 0 0100 1001 ..... @d_r_d =20 FSRCd 10 ..... 110110 ..... 0 0111 0100 00000 @d_d1 # FSRC1d FSRCs 10 ..... 110110 ..... 0 0111 0101 00000 @r_r1 # FSRC1s diff --git a/target/sparc/translate.c b/target/sparc/translate.c index 88e6da4f8b..5b6a12c81e 100644 --- a/target/sparc/translate.c +++ b/target/sparc/translate.c @@ -809,7 +809,8 @@ static void gen_op_fpsubs32s(TCGv_i32 d, TCGv_i32 src1,= TCGv_i32 src2) tcg_gen_movcond_i32(TCG_COND_LT, d, v, z, t, r); } =20 -static void gen_op_faligndata(TCGv_i64 dst, TCGv_i64 s1, TCGv_i64 s2) +static void gen_op_faligndata_i(TCGv_i64 dst, TCGv_i64 s1, + TCGv_i64 s2, TCGv gsr) { #ifdef TARGET_SPARC64 TCGv t1, t2, shift; @@ -818,7 +819,7 @@ static void gen_op_faligndata(TCGv_i64 dst, TCGv_i64 s1= , TCGv_i64 s2) t2 =3D tcg_temp_new(); shift =3D tcg_temp_new(); =20 - tcg_gen_andi_tl(shift, cpu_gsr, 7); + tcg_gen_andi_tl(shift, gsr, 7); tcg_gen_shli_tl(shift, shift, 3); tcg_gen_shl_tl(t1, s1, shift); =20 @@ -836,6 +837,11 @@ static void gen_op_faligndata(TCGv_i64 dst, TCGv_i64 s= 1, TCGv_i64 s2) #endif } =20 +static void gen_op_faligndata_g(TCGv_i64 dst, TCGv_i64 s1, TCGv_i64 s2) +{ + gen_op_faligndata_i(dst, s1, s2, cpu_gsr); +} + static void gen_op_bshuffle(TCGv_i64 dst, TCGv_i64 src1, TCGv_i64 src2) { #ifdef TARGET_SPARC64 @@ -5064,7 +5070,7 @@ TRANS(FORNOTd, VIS1, do_ddd, a, tcg_gen_orc_i64) TRANS(FORd, VIS1, do_ddd, a, tcg_gen_or_i64) =20 TRANS(FPACK32, VIS1, do_ddd, a, gen_op_fpack32) -TRANS(FALIGNDATAg, VIS1, do_ddd, a, gen_op_faligndata) +TRANS(FALIGNDATAg, VIS1, do_ddd, a, gen_op_faligndata_g) TRANS(BSHUFFLE, VIS2, do_ddd, a, gen_op_bshuffle) =20 TRANS(FHADDd, VIS3, do_ddd, a, gen_op_fhaddd) @@ -5225,6 +5231,27 @@ TRANS(FNMADDd, FMAF, do_dddd, a, gen_op_fnmaddd) TRANS(FPMADDX, IMA, do_dddd, a, gen_op_fpmaddx) TRANS(FPMADDXHI, IMA, do_dddd, a, gen_op_fpmaddxhi) =20 +static bool trans_FALIGNDATAi(DisasContext *dc, arg_r_r_r *a) +{ + TCGv_i64 dst, src1, src2; + TCGv src3; + + if (!avail_VIS4(dc)) { + return false; + } + if (gen_trap_ifnofpu(dc)) { + return true; + } + + dst =3D tcg_temp_new_i64(); + src1 =3D gen_load_fpr_D(dc, a->rd); + src2 =3D gen_load_fpr_D(dc, a->rs2); + src3 =3D gen_load_gpr(dc, a->rs1); + gen_op_faligndata_i(dst, src1, src2, src3); + gen_store_fpr_D(dc, a->rd, dst); + return advance_pc(dc); +} + static bool do_env_qqq(DisasContext *dc, arg_r_r_r *a, void (*func)(TCGv_i128, TCGv_env, TCGv_i128, TCGv_i= 128)) { --=20 2.34.1 From nobody Mon Nov 25 08:36:39 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1716752671; cv=none; d=zohomail.com; s=zohoarc; b=ACXdcW4se8jFyy6IihIBJIMp/hu4OOACJwpRP+03ebT0RJRG0wMdneFbxsSUU9yTgrwlAIvjwRLmXjZlZF84/kHjsTEP+HbRrWmI/Ckz5+RIBVKiQYt2ixYvY4c+uE1sjcw9E+1ZoAhwAMcZOu3HcNjZQHOFwUm5FlXn1FAX6NA= ARC-Message-Signature: i=1; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::52c; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x52c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1716752671995100015 Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Richard Henderson Tested-by: Mark Cave-Ayland --- target/sparc/insns.decode | 9 +++++++++ target/sparc/translate.c | 11 +++++++++++ 2 files changed, 20 insertions(+) diff --git a/target/sparc/insns.decode b/target/sparc/insns.decode index 0913fe7a86..80579642d1 100644 --- a/target/sparc/insns.decode +++ b/target/sparc/insns.decode @@ -509,6 +509,15 @@ FCMPEq 10 000 cc:2 110101 ..... 0 0101 0111 ....= . \ MOVdTOx 10 ..... 110110 00000 1 0001 0000 ..... @r_d2 MOVxTOd 10 ..... 110110 00000 1 0001 1000 ..... @d_r2 =20 + FPADD8 10 ..... 110110 ..... 1 0010 0100 ..... @d_d_d + FPADDS8 10 ..... 110110 ..... 1 0010 0110 ..... @d_d_d + FPADDUS8 10 ..... 110110 ..... 1 0010 0111 ..... @d_d_d + FPADDUS16 10 ..... 110110 ..... 1 0010 0011 ..... @d_d_d + FPSUB8 10 ..... 110110 ..... 1 0101 0100 ..... @d_d_d + FPSUBS8 10 ..... 110110 ..... 1 0101 0110 ..... @d_d_d + FPSUBUS8 10 ..... 110110 ..... 1 0101 0111 ..... @d_d_d + FPSUBUS16 10 ..... 110110 ..... 1 0101 0011 ..... @d_d_d + FLCMPs 10 000 cc:2 110110 rs1:5 1 0101 0001 rs2:5 FLCMPd 10 000 cc:2 110110 ..... 1 0101 0010 ..... \ rs1=3D%dfp_rs1 rs2=3D%dfp_rs2 diff --git a/target/sparc/translate.c b/target/sparc/translate.c index 5b6a12c81e..0f7f0260c4 100644 --- a/target/sparc/translate.c +++ b/target/sparc/translate.c @@ -5021,17 +5021,28 @@ static bool do_gvec_ddd(DisasContext *dc, arg_r_r_r= *a, MemOp vece, return advance_pc(dc); } =20 +TRANS(FPADD8, VIS4, do_gvec_ddd, a, MO_8, tcg_gen_gvec_add) TRANS(FPADD16, VIS1, do_gvec_ddd, a, MO_16, tcg_gen_gvec_add) TRANS(FPADD32, VIS1, do_gvec_ddd, a, MO_32, tcg_gen_gvec_add) + +TRANS(FPSUB8, VIS4, do_gvec_ddd, a, MO_8, tcg_gen_gvec_sub) TRANS(FPSUB16, VIS1, do_gvec_ddd, a, MO_16, tcg_gen_gvec_sub) TRANS(FPSUB32, VIS1, do_gvec_ddd, a, MO_32, tcg_gen_gvec_sub) + TRANS(FCHKSM16, VIS3, do_gvec_ddd, a, MO_16, gen_op_fchksm16) TRANS(FMEAN16, VIS3, do_gvec_ddd, a, MO_16, gen_op_fmean16) =20 +TRANS(FPADDS8, VIS4, do_gvec_ddd, a, MO_8, tcg_gen_gvec_ssadd) TRANS(FPADDS16, VIS3, do_gvec_ddd, a, MO_16, tcg_gen_gvec_ssadd) TRANS(FPADDS32, VIS3, do_gvec_ddd, a, MO_32, tcg_gen_gvec_ssadd) +TRANS(FPADDUS8, VIS4, do_gvec_ddd, a, MO_8, tcg_gen_gvec_usadd) +TRANS(FPADDUS16, VIS4, do_gvec_ddd, a, MO_16, tcg_gen_gvec_usadd) + +TRANS(FPSUBS8, VIS4, do_gvec_ddd, a, MO_8, tcg_gen_gvec_sssub) TRANS(FPSUBS16, VIS3, do_gvec_ddd, a, MO_16, tcg_gen_gvec_sssub) TRANS(FPSUBS32, VIS3, do_gvec_ddd, a, MO_32, tcg_gen_gvec_sssub) +TRANS(FPSUBUS8, VIS4, do_gvec_ddd, a, MO_8, tcg_gen_gvec_ussub) +TRANS(FPSUBUS16, VIS4, do_gvec_ddd, a, MO_16, tcg_gen_gvec_ussub) =20 TRANS(FSLL16, VIS3, do_gvec_ddd, a, MO_16, tcg_gen_gvec_shlv) TRANS(FSLL32, VIS3, do_gvec_ddd, a, MO_32, tcg_gen_gvec_shlv) --=20 2.34.1 From nobody Mon Nov 25 08:36:39 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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[174.21.72.5]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-1f46ad93c2esm28165935ad.263.2024.05.26.12.43.19 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 26 May 2024 12:43:20 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1716752600; x=1717357400; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=JS2sXItrx1lQjyr/YyxaEv+gYLkHZMhSUN20mnS6HsM=; b=TkijZ/gpevzlTaRaWcFlLkXj096vGh7YGKKojRLviull7Pw0iKW4vnG5Pw9maN33PT H/hv9qXBFDjSTD4BXUCZlK3rg9q54ZJufTdOm0SnMBOM0Fyhn6YJy5vPkIlCs4QDA5e1 6AbPx944PlGiGFqCMue//Pv4kwIZXJM2g+m+IKwqoTW5b0gwa2eop/j7IuuImpGXln7f +SyulvxWwxQefXsLQxoFgNu3k6B/tnFj6UZrVK3HvEpxtuDzMd7RMylVVzNsw494zg7D e0TYHK2MPtBZMRcsFJJFel0X6zRPOZ77eBhOldrKvJHiKo+HFExee0S0ESP/DUzgF1gP Dr+Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1716752600; x=1717357400; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=JS2sXItrx1lQjyr/YyxaEv+gYLkHZMhSUN20mnS6HsM=; b=PPvUhxFfeyNQfAwB9pL0oZl6J10Sfk9PxK1pXnDQCBSLa4thMQqizbM7f7BhPTVNqg Ri7I8tulhdNxEi3j+hUOgEuAeJ7pADEAA8FJaBcdjs+KVdL7PQ9YQDDcJ3jEdJLJ5bTB G+FOpNh8J/lHcMF11T698GJrhmZhi+LVv4W7R1NIg9ArXgUCecxX40X9CGZnre9yry3/ jrYqg5ufSOf0BNMzf/q9pGZwUF/+KdDW6PadmzbYDzGYI14E/5pSiH7bgiCHjfWJfLnK 75NeD9Iuq/Szr9bLiGcLgcBD1xLUmKZnGWe0sq/E7C64PHtJZLtNYrSKoy4pmMyld2vg q1tg== X-Gm-Message-State: AOJu0YxkXX6pgBMqrBrRyD6rjh7wlksFgFwbn2JUPhN7tHLylzqIeLd9 uMLVJmXX03Tc381ZUb7wnf0s3+2ClMTRCUNkcLMwQz6gUgv7GBCQWklLbys0J5C6YNgn2rNbe3H P X-Google-Smtp-Source: AGHT+IFgKxTXj1JiORd0n72dTdfd4bjRQLXmrX7cHURUy+5ekMZeDQPsldrbU+1quHC37smRTEYPUQ== X-Received: by 2002:a17:902:ec85:b0:1f2:fcc3:5b5 with SMTP id d9443c01a7336-1f44870df72mr85720225ad.20.1716752600381; Sun, 26 May 2024 12:43:20 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: mark.cave-ayland@ilande.co.uk Subject: [PATCH v2 32/37] target/sparc: Implement VIS4 comparisons Date: Sun, 26 May 2024 12:42:49 -0700 Message-Id: <20240526194254.459395-33-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240526194254.459395-1-richard.henderson@linaro.org> References: <20240526194254.459395-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::636; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x636.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1716752734230100020 Content-Type: text/plain; charset="utf-8" VIS4 completes the set, adding missing signed 8-bit ops and missing unsigned 16 and 32-bit ops. Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daud=C3=A9 Tested-by: Mark Cave-Ayland --- target/sparc/helper.h | 12 +-- target/sparc/insns.decode | 6 ++ target/sparc/translate.c | 12 +++ target/sparc/vis_helper.c | 170 +++++++++++++++++++++++++++++--------- 4 files changed, 153 insertions(+), 47 deletions(-) diff --git a/target/sparc/helper.h b/target/sparc/helper.h index fe0d8bc593..134e519a37 100644 --- a/target/sparc/helper.h +++ b/target/sparc/helper.h @@ -122,19 +122,19 @@ DEF_HELPER_FLAGS_2(fchksm16, TCG_CALL_NO_RWG_SE, i64,= i64, i64) DEF_HELPER_FLAGS_2(fmean16, TCG_CALL_NO_RWG_SE, i64, i64, i64) DEF_HELPER_FLAGS_2(fslas16, TCG_CALL_NO_RWG_SE, i64, i64, i64) DEF_HELPER_FLAGS_2(fslas32, TCG_CALL_NO_RWG_SE, i64, i64, i64) -#define VIS_CMPHELPER(name) \ +#define VIS_CMPHELPER(name) \ + DEF_HELPER_FLAGS_2(f##name##8, TCG_CALL_NO_RWG_SE, \ + i64, i64, i64) \ DEF_HELPER_FLAGS_2(f##name##16, TCG_CALL_NO_RWG_SE, \ - i64, i64, i64) \ + i64, i64, i64) \ DEF_HELPER_FLAGS_2(f##name##32, TCG_CALL_NO_RWG_SE, \ i64, i64, i64) VIS_CMPHELPER(cmpgt) VIS_CMPHELPER(cmpeq) VIS_CMPHELPER(cmple) VIS_CMPHELPER(cmpne) -DEF_HELPER_FLAGS_2(fcmpeq8, TCG_CALL_NO_RWG_SE, i64, i64, i64) -DEF_HELPER_FLAGS_2(fcmpne8, TCG_CALL_NO_RWG_SE, i64, i64, i64) -DEF_HELPER_FLAGS_2(fcmpule8, TCG_CALL_NO_RWG_SE, i64, i64, i64) -DEF_HELPER_FLAGS_2(fcmpugt8, TCG_CALL_NO_RWG_SE, i64, i64, i64) +VIS_CMPHELPER(cmpugt) +VIS_CMPHELPER(cmpule) DEF_HELPER_FLAGS_2(xmulx, TCG_CALL_NO_RWG_SE, i64, i64, i64) DEF_HELPER_FLAGS_2(xmulxhi, TCG_CALL_NO_RWG_SE, i64, i64, i64) #endif diff --git a/target/sparc/insns.decode b/target/sparc/insns.decode index 80579642d1..be591171ad 100644 --- a/target/sparc/insns.decode +++ b/target/sparc/insns.decode @@ -425,6 +425,12 @@ FCMPEq 10 000 cc:2 110101 ..... 0 0101 0111 ....= . \ FPCMPUGT8 10 ..... 110110 ..... 1 0010 1000 ..... @r_d_d FPCMPNE8 10 ..... 110110 ..... 1 0010 0010 ..... @r_d_d FPCMPEQ8 10 ..... 110110 ..... 1 0010 1010 ..... @r_d_d + FPCMPLE8 10 ..... 110110 ..... 0 0011 0100 ..... @r_d_d + FPCMPGT8 10 ..... 110110 ..... 0 0011 1100 ..... @r_d_d + FPCMPULE16 10 ..... 110110 ..... 1 0010 1110 ..... @r_d_d + FPCMPUGT16 10 ..... 110110 ..... 1 0010 1011 ..... @r_d_d + FPCMPULE32 10 ..... 110110 ..... 1 0010 1111 ..... @r_d_d + FPCMPUGT32 10 ..... 110110 ..... 1 0010 1100 ..... @r_d_d =20 FMUL8x16 10 ..... 110110 ..... 0 0011 0001 ..... @d_r_d FMUL8x16AU 10 ..... 110110 ..... 0 0011 0011 ..... @d_r_r diff --git a/target/sparc/translate.c b/target/sparc/translate.c index 0f7f0260c4..a952a990cc 100644 --- a/target/sparc/translate.c +++ b/target/sparc/translate.c @@ -67,15 +67,21 @@ # define gen_helper_fcmpeq8 ({ qemu_build_not_reached(); NULL= ; }) # define gen_helper_fcmpeq16 ({ qemu_build_not_reached(); NULL= ; }) # define gen_helper_fcmpeq32 ({ qemu_build_not_reached(); NULL= ; }) +# define gen_helper_fcmpgt8 ({ qemu_build_not_reached(); NULL= ; }) # define gen_helper_fcmpgt16 ({ qemu_build_not_reached(); NULL= ; }) # define gen_helper_fcmpgt32 ({ qemu_build_not_reached(); NULL= ; }) +# define gen_helper_fcmple8 ({ qemu_build_not_reached(); NULL= ; }) # define gen_helper_fcmple16 ({ qemu_build_not_reached(); NULL= ; }) # define gen_helper_fcmple32 ({ qemu_build_not_reached(); NULL= ; }) # define gen_helper_fcmpne8 ({ qemu_build_not_reached(); NULL= ; }) # define gen_helper_fcmpne16 ({ qemu_build_not_reached(); NULL= ; }) # define gen_helper_fcmpne32 ({ qemu_build_not_reached(); NULL= ; }) # define gen_helper_fcmpule8 ({ qemu_build_not_reached(); NULL= ; }) +# define gen_helper_fcmpule16 ({ qemu_build_not_reached(); NULL= ; }) +# define gen_helper_fcmpule32 ({ qemu_build_not_reached(); NULL= ; }) # define gen_helper_fcmpugt8 ({ qemu_build_not_reached(); NULL= ; }) +# define gen_helper_fcmpugt16 ({ qemu_build_not_reached(); NULL= ; }) +# define gen_helper_fcmpugt32 ({ qemu_build_not_reached(); NULL= ; }) # define gen_helper_fdtox ({ qemu_build_not_reached(); NULL= ; }) # define gen_helper_fexpand ({ qemu_build_not_reached(); NULL= ; }) # define gen_helper_fmul8sux16 ({ qemu_build_not_reached(); NULL= ; }) @@ -5115,16 +5121,22 @@ TRANS(FPCMPLE16, VIS1, do_rdd, a, gen_helper_fcmple= 16) TRANS(FPCMPNE16, VIS1, do_rdd, a, gen_helper_fcmpne16) TRANS(FPCMPGT16, VIS1, do_rdd, a, gen_helper_fcmpgt16) TRANS(FPCMPEQ16, VIS1, do_rdd, a, gen_helper_fcmpeq16) +TRANS(FPCMPULE16, VIS4, do_rdd, a, gen_helper_fcmpule16) +TRANS(FPCMPUGT16, VIS4, do_rdd, a, gen_helper_fcmpugt16) =20 TRANS(FPCMPLE32, VIS1, do_rdd, a, gen_helper_fcmple32) TRANS(FPCMPNE32, VIS1, do_rdd, a, gen_helper_fcmpne32) TRANS(FPCMPGT32, VIS1, do_rdd, a, gen_helper_fcmpgt32) TRANS(FPCMPEQ32, VIS1, do_rdd, a, gen_helper_fcmpeq32) +TRANS(FPCMPULE32, VIS4, do_rdd, a, gen_helper_fcmpule32) +TRANS(FPCMPUGT32, VIS4, do_rdd, a, gen_helper_fcmpugt32) =20 TRANS(FPCMPEQ8, VIS3B, do_rdd, a, gen_helper_fcmpeq8) TRANS(FPCMPNE8, VIS3B, do_rdd, a, gen_helper_fcmpne8) TRANS(FPCMPULE8, VIS3B, do_rdd, a, gen_helper_fcmpule8) TRANS(FPCMPUGT8, VIS3B, do_rdd, a, gen_helper_fcmpugt8) +TRANS(FPCMPLE8, VIS4, do_rdd, a, gen_helper_fcmple8) +TRANS(FPCMPGT8, VIS4, do_rdd, a, gen_helper_fcmpgt8) =20 TRANS(PDISTN, VIS3, do_rdd, a, gen_op_pdistn) TRANS(XMULX, VIS3, do_rrr, a, gen_helper_xmulx) diff --git a/target/sparc/vis_helper.c b/target/sparc/vis_helper.c index c927a054b8..371f5445a1 100644 --- a/target/sparc/vis_helper.c +++ b/target/sparc/vis_helper.c @@ -66,6 +66,7 @@ target_ulong helper_array8(target_ulong rs1, target_ulong= rs2) #define VIS_W64(n) w[3 - (n)] #define VIS_SW64(n) sw[3 - (n)] #define VIS_L64(n) l[1 - (n)] +#define VIS_SL64(n) sl[1 - (n)] #define VIS_B32(n) b[3 - (n)] #define VIS_W32(n) w[1 - (n)] #else @@ -74,6 +75,7 @@ target_ulong helper_array8(target_ulong rs1, target_ulong= rs2) #define VIS_W64(n) w[n] #define VIS_SW64(n) sw[n] #define VIS_L64(n) l[n] +#define VIS_SL64(n) sl[n] #define VIS_B32(n) b[n] #define VIS_W32(n) w[n] #endif @@ -84,6 +86,7 @@ typedef union { uint16_t w[4]; int16_t sw[4]; uint32_t l[2]; + int32_t sl[2]; uint64_t ll; float64 d; } VIS64; @@ -198,47 +201,6 @@ uint64_t helper_fexpand(uint32_t src2) return d.ll; } =20 -#define VIS_CMPHELPER(name, F) \ - uint64_t name##16(uint64_t src1, uint64_t src2) \ - { \ - VIS64 s, d; \ - \ - s.ll =3D src1; \ - d.ll =3D src2; \ - \ - d.VIS_W64(0) =3D F(s.VIS_W64(0), d.VIS_W64(0)) ? 1 : 0; \ - d.VIS_W64(0) |=3D F(s.VIS_W64(1), d.VIS_W64(1)) ? 2 : 0; \ - d.VIS_W64(0) |=3D F(s.VIS_W64(2), d.VIS_W64(2)) ? 4 : 0; \ - d.VIS_W64(0) |=3D F(s.VIS_W64(3), d.VIS_W64(3)) ? 8 : 0; \ - d.VIS_W64(1) =3D d.VIS_W64(2) =3D d.VIS_W64(3) =3D 0; \ - \ - return d.ll; \ - } \ - \ - uint64_t name##32(uint64_t src1, uint64_t src2) \ - { \ - VIS64 s, d; \ - \ - s.ll =3D src1; \ - d.ll =3D src2; \ - \ - d.VIS_L64(0) =3D F(s.VIS_L64(0), d.VIS_L64(0)) ? 1 : 0; \ - d.VIS_L64(0) |=3D F(s.VIS_L64(1), d.VIS_L64(1)) ? 2 : 0; \ - d.VIS_L64(1) =3D 0; \ - \ - return d.ll; \ - } - -#define FCMPGT(a, b) ((a) > (b)) -#define FCMPEQ(a, b) ((a) =3D=3D (b)) -#define FCMPLE(a, b) ((a) <=3D (b)) -#define FCMPNE(a, b) ((a) !=3D (b)) - -VIS_CMPHELPER(helper_fcmpgt, FCMPGT) -VIS_CMPHELPER(helper_fcmpeq, FCMPEQ) -VIS_CMPHELPER(helper_fcmple, FCMPLE) -VIS_CMPHELPER(helper_fcmpne, FCMPNE) - uint64_t helper_fcmpeq8(uint64_t src1, uint64_t src2) { uint64_t a =3D src1 ^ src2; @@ -260,6 +222,25 @@ uint64_t helper_fcmpne8(uint64_t src1, uint64_t src2) return helper_fcmpeq8(src1, src2) ^ 0xff; } =20 +uint64_t helper_fcmple8(uint64_t src1, uint64_t src2) +{ + VIS64 s1, s2; + uint64_t r =3D 0; + + s1.ll =3D src1; + s2.ll =3D src2; + + for (int i =3D 0; i < 8; ++i) { + r |=3D (s1.VIS_SB64(i) <=3D s2.VIS_SB64(i)) << i; + } + return r; +} + +uint64_t helper_fcmpgt8(uint64_t src1, uint64_t src2) +{ + return helper_fcmple8(src1, src2) ^ 0xff; +} + uint64_t helper_fcmpule8(uint64_t src1, uint64_t src2) { VIS64 s1, s2; @@ -279,6 +260,113 @@ uint64_t helper_fcmpugt8(uint64_t src1, uint64_t src2) return helper_fcmpule8(src1, src2) ^ 0xff; } =20 +uint64_t helper_fcmpeq16(uint64_t src1, uint64_t src2) +{ + uint64_t a =3D src1 ^ src2; + uint64_t m =3D 0x7fff7fff7fff7fffULL; + uint64_t c =3D ~(((a & m) + m) | a | m); + + /* a...............b...............c...............d............... */ + c |=3D c << 15; + /* ab..............bc..............cd..............d............... */ + c |=3D c << 30; + /* abcd............bcd.............cd..............d............... */ + return c >> 60; +} + +uint64_t helper_fcmpne16(uint64_t src1, uint64_t src2) +{ + return helper_fcmpeq16(src1, src2) ^ 0xf; +} + +uint64_t helper_fcmple16(uint64_t src1, uint64_t src2) +{ + VIS64 s1, s2; + uint64_t r =3D 0; + + s1.ll =3D src1; + s2.ll =3D src2; + + for (int i =3D 0; i < 4; ++i) { + r |=3D (s1.VIS_SW64(i) <=3D s2.VIS_SW64(i)) << i; + } + return r; +} + +uint64_t helper_fcmpgt16(uint64_t src1, uint64_t src2) +{ + return helper_fcmple16(src1, src2) ^ 0xf; +} + +uint64_t helper_fcmpule16(uint64_t src1, uint64_t src2) +{ + VIS64 s1, s2; + uint64_t r =3D 0; + + s1.ll =3D src1; + s2.ll =3D src2; + + for (int i =3D 0; i < 4; ++i) { + r |=3D (s1.VIS_W64(i) <=3D s2.VIS_W64(i)) << i; + } + return r; +} + +uint64_t helper_fcmpugt16(uint64_t src1, uint64_t src2) +{ + return helper_fcmpule16(src1, src2) ^ 0xf; +} + +uint64_t helper_fcmpeq32(uint64_t src1, uint64_t src2) +{ + uint64_t a =3D src1 ^ src2; + return ((uint32_t)a =3D=3D 0) | (a >> 32 ? 0 : 2); +} + +uint64_t helper_fcmpne32(uint64_t src1, uint64_t src2) +{ + uint64_t a =3D src1 ^ src2; + return ((uint32_t)a !=3D 0) | (a >> 32 ? 2 : 0); +} + +uint64_t helper_fcmple32(uint64_t src1, uint64_t src2) +{ + VIS64 s1, s2; + uint64_t r =3D 0; + + s1.ll =3D src1; + s2.ll =3D src2; + + for (int i =3D 0; i < 2; ++i) { + r |=3D (s1.VIS_SL64(i) <=3D s2.VIS_SL64(i)) << i; + } + return r; +} + +uint64_t helper_fcmpgt32(uint64_t src1, uint64_t src2) +{ + return helper_fcmple32(src1, src2) ^ 3; +} + +uint64_t helper_fcmpule32(uint64_t src1, uint64_t src2) +{ + VIS64 s1, s2; + uint64_t r =3D 0; + + s1.ll =3D src1; + s2.ll =3D src2; + + for (int i =3D 0; i < 2; ++i) { + r |=3D (s1.VIS_L64(i) <=3D s2.VIS_L64(i)) << i; + } + return r; +} + +uint64_t helper_fcmpugt32(uint64_t src1, uint64_t src2) +{ + return helper_fcmpule32(src1, src2) ^ 3; +} + uint64_t helper_pdist(uint64_t sum, uint64_t src1, uint64_t src2) { int i; --=20 2.34.1 From nobody Mon Nov 25 08:36:39 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::62b; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1716752866726100007 Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Richard Henderson Tested-by: Mark Cave-Ayland --- target/sparc/insns.decode | 14 ++++++++++++++ target/sparc/translate.c | 14 ++++++++++++++ 2 files changed, 28 insertions(+) diff --git a/target/sparc/insns.decode b/target/sparc/insns.decode index be591171ad..2ebee5a1ca 100644 --- a/target/sparc/insns.decode +++ b/target/sparc/insns.decode @@ -524,6 +524,20 @@ FCMPEq 10 000 cc:2 110101 ..... 0 0101 0111 ....= . \ FPSUBUS8 10 ..... 110110 ..... 1 0101 0111 ..... @d_d_d FPSUBUS16 10 ..... 110110 ..... 1 0101 0011 ..... @d_d_d =20 + FPMIN8 10 ..... 110110 ..... 1 0001 1010 ..... @d_d_d + FPMIN16 10 ..... 110110 ..... 1 0001 1011 ..... @d_d_d + FPMIN32 10 ..... 110110 ..... 1 0001 1100 ..... @d_d_d + FPMINU8 10 ..... 110110 ..... 1 0101 1010 ..... @d_d_d + FPMINU16 10 ..... 110110 ..... 1 0101 1011 ..... @d_d_d + FPMINU32 10 ..... 110110 ..... 1 0101 1100 ..... @d_d_d + + FPMAX8 10 ..... 110110 ..... 1 0001 1101 ..... @d_d_d + FPMAX16 10 ..... 110110 ..... 1 0001 1110 ..... @d_d_d + FPMAX32 10 ..... 110110 ..... 1 0001 1111 ..... @d_d_d + FPMAXU8 10 ..... 110110 ..... 1 0101 1101 ..... @d_d_d + FPMAXU16 10 ..... 110110 ..... 1 0101 1110 ..... @d_d_d + FPMAXU32 10 ..... 110110 ..... 1 0101 1111 ..... @d_d_d + FLCMPs 10 000 cc:2 110110 rs1:5 1 0101 0001 rs2:5 FLCMPd 10 000 cc:2 110110 ..... 1 0101 0010 ..... \ rs1=3D%dfp_rs1 rs2=3D%dfp_rs2 diff --git a/target/sparc/translate.c b/target/sparc/translate.c index a952a990cc..242f483fd2 100644 --- a/target/sparc/translate.c +++ b/target/sparc/translate.c @@ -5057,6 +5057,20 @@ TRANS(FSRL32, VIS3, do_gvec_ddd, a, MO_32, tcg_gen_g= vec_shrv) TRANS(FSRA16, VIS3, do_gvec_ddd, a, MO_16, tcg_gen_gvec_sarv) TRANS(FSRA32, VIS3, do_gvec_ddd, a, MO_32, tcg_gen_gvec_sarv) =20 +TRANS(FPMIN8, VIS4, do_gvec_ddd, a, MO_8, tcg_gen_gvec_smin) +TRANS(FPMIN16, VIS4, do_gvec_ddd, a, MO_16, tcg_gen_gvec_smin) +TRANS(FPMIN32, VIS4, do_gvec_ddd, a, MO_32, tcg_gen_gvec_smin) +TRANS(FPMINU8, VIS4, do_gvec_ddd, a, MO_8, tcg_gen_gvec_umin) +TRANS(FPMINU16, VIS4, do_gvec_ddd, a, MO_16, tcg_gen_gvec_umin) +TRANS(FPMINU32, VIS4, do_gvec_ddd, a, MO_32, tcg_gen_gvec_umin) + +TRANS(FPMAX8, VIS4, do_gvec_ddd, a, MO_8, tcg_gen_gvec_smax) +TRANS(FPMAX16, VIS4, do_gvec_ddd, a, MO_16, tcg_gen_gvec_smax) +TRANS(FPMAX32, VIS4, do_gvec_ddd, a, MO_32, tcg_gen_gvec_smax) +TRANS(FPMAXU8, VIS4, do_gvec_ddd, a, MO_8, tcg_gen_gvec_umax) +TRANS(FPMAXU16, VIS4, do_gvec_ddd, a, MO_16, tcg_gen_gvec_umax) +TRANS(FPMAXU32, VIS4, do_gvec_ddd, a, MO_32, tcg_gen_gvec_umax) + static bool do_ddd(DisasContext *dc, arg_r_r_r *a, void (*func)(TCGv_i64, TCGv_i64, TCGv_i64)) { --=20 2.34.1 From nobody Mon Nov 25 08:36:39 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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[174.21.72.5]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-1f46ad93c2esm28165935ad.263.2024.05.26.12.43.21 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 26 May 2024 12:43:21 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1716752602; x=1717357402; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=hcyoZD3anU/IH/PLJOi2XftX4jEwUCrYWawOxmyODIk=; b=Yuah1sJvshy/L9SmbwmFTB35sLyqSAYAE7TAl8sxoxzxzDPGtwGqbYdev2B/ErXavX Ks0EqVrWXHx7JyMsk6h4bk3KQzBsafPqJFRee1KQnUYLkSPhvyY8RCmFnCuib+lMQw0F 6l9HZsnfmGrLMIKNMlWoVBgGtyep2qXq+Suou1nve4ZuYRY6U3mIr//7/58jE2ULjHx+ cQ3ntjfiDuPQRHQ21Vk/9o1iQ/fFt9DvX8EoBgHIBg5wXqYSIRiv6A2PRO2cfv+II7BN 4y+kgo+GsMOsPwENd9S4PW5y7D/wckuxIT64S8kh1+Sou3W1pGDSk9Yjvd+dNXGp1Z2e mpfQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1716752602; x=1717357402; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::634; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x634.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1716752700117100007 Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Richard Henderson Tested-by: Mark Cave-Ayland --- target/sparc/insns.decode | 2 ++ target/sparc/translate.c | 14 ++++++++++++++ 2 files changed, 16 insertions(+) diff --git a/target/sparc/insns.decode b/target/sparc/insns.decode index 2ebee5a1ca..a7720560f8 100644 --- a/target/sparc/insns.decode +++ b/target/sparc/insns.decode @@ -447,6 +447,8 @@ FCMPEq 10 000 cc:2 110101 ..... 0 0101 0111 .....= \ PDISTN 10 ..... 110110 ..... 0 0011 1111 ..... @r_d_d =20 FMEAN16 10 ..... 110110 ..... 0 0100 0000 ..... @d_d_d + SUBXC 10 ..... 110110 ..... 0 0100 0001 ..... @r_r_r + SUBXCcc 10 ..... 110110 ..... 0 0100 0011 ..... @r_r_r FCHKSM16 10 ..... 110110 ..... 0 0100 0100 ..... @d_d_d FALIGNDATAg 10 ..... 110110 ..... 0 0100 1000 ..... @d_d_d FPMERGE 10 ..... 110110 ..... 0 0100 1011 ..... @d_r_r diff --git a/target/sparc/translate.c b/target/sparc/translate.c index 242f483fd2..e3e92bcf83 100644 --- a/target/sparc/translate.c +++ b/target/sparc/translate.c @@ -515,6 +515,17 @@ static void gen_op_subccc(TCGv dst, TCGv src1, TCGv sr= c2) gen_op_subcc_int(dst, src1, src2, gen_carry32()); } =20 +static void gen_op_subxc(TCGv dst, TCGv src1, TCGv src2) +{ + tcg_gen_sub_tl(dst, src1, src2); + tcg_gen_sub_tl(dst, dst, cpu_cc_C); +} + +static void gen_op_subxccc(TCGv dst, TCGv src1, TCGv src2) +{ + gen_op_subcc_int(dst, src1, src2, cpu_cc_C); +} + static void gen_op_mulscc(TCGv dst, TCGv src1, TCGv src2) { TCGv zero =3D tcg_constant_tl(0); @@ -3963,6 +3974,9 @@ TRANS(ARRAY32, VIS1, do_rrr, a, gen_op_array32) TRANS(ADDXC, VIS3, do_rrr, a, gen_op_addxc) TRANS(ADDXCcc, VIS3, do_rrr, a, gen_op_addxccc) =20 +TRANS(SUBXC, VIS4, do_rrr, a, gen_op_subxc) +TRANS(SUBXCcc, VIS4, do_rrr, a, gen_op_subxccc) + TRANS(UMULXHI, VIS3, do_rrr, a, gen_op_umulxhi) =20 static void gen_op_alignaddr(TCGv dst, TCGv s1, TCGv s2) --=20 2.34.1 From nobody Mon Nov 25 08:36:39 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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[174.21.72.5]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-1f46ad93c2esm28165935ad.263.2024.05.26.12.43.22 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 26 May 2024 12:43:22 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1716752603; x=1717357403; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=ADgeOSedbVT4WLVTe/jbh46tCWtzpdfEWbBUSGOZW6w=; b=Hcd7RTn8+u0qBkXVlBs+cvyUwlug9Acb4wD7dcWVk4NldZDHAqaF/gYAplX+ed7XbP /pU5Y0SvsdRq64BIuTRFLChXPaTQmoTv+3sxH73Xvw6KmkgjnhT69dfLEd+/b9m5TZC+ AcKsKWZdSNcLnVmLSlQeB9wUYVXU2/Mkw3iHT/Icdsw+Q5Fleoiwc8/5e/fGO+EZKSH+ gXqhA7b24ASNgvAo7bGYKkwWM3kQV0i5bgofaqtnx4Ws0va7jUq/ZgpXJDElgb6JLft5 LHt4qTQKfpEfiPtk3lfR0G9ee+jYmbxEJxGa7VHhWu477wvSPI0QCoevl58WgEq5fLld bMBg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1716752603; x=1717357403; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=ADgeOSedbVT4WLVTe/jbh46tCWtzpdfEWbBUSGOZW6w=; b=D51zGNsqhm48HBdEX2yYpdMr7y7TUR3R58zaJ9hLJcKK68oVW1E0nffQvVHFU34Dyx zm2GDBo0V/2DNM1CHbz7gLtr8TH3cblecC05iNS0DA6gTRXzG2yL9dSjWeH3nBEwsWsA b/xQPyBDfD/my4SHfTIzdS4f0HZ3dWRrxvX6FOSoD3Bsk7NUjmZcGkd8t/2WSek2uukR BcvLaDvMPjcATRwrf7UHFTfSFrSWs7YxCfgq7vXApp9K9bcpR2gTCTZpZjNt8N0QqCrl P4VwDczQYzwjbKzvGvg8h5wA73k0iQSi2ePof/Ls/hZVgGBgmwHy0gLw2603q3F68jLs o/3w== X-Gm-Message-State: AOJu0Yw3c0h7WlOt2G0pNY3+mTFWX+dKYq+hNYkodaUpaKQgoWtnNHWg +HIixr2QrhAbOv9innOwuitI/y7opJ3qB3C/Wb6mACCYRxG3MrOnnRg57q6YWomlCtxjb2exFnH F X-Google-Smtp-Source: AGHT+IEQA8ob2pI4W58UiHbnukcCbISmhf/nc9KOImNWjNsZBWzHqX57Y/AFnUIlvWe5Urvt4qvxNQ== X-Received: by 2002:a17:902:e849:b0:1f2:ff65:d2e0 with SMTP id d9443c01a7336-1f449026bdamr99291885ad.42.1716752602963; Sun, 26 May 2024 12:43:22 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: mark.cave-ayland@ilande.co.uk Subject: [PATCH v2 35/37] target/sparc: Implement MWAIT Date: Sun, 26 May 2024 12:42:52 -0700 Message-Id: <20240526194254.459395-36-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240526194254.459395-1-richard.henderson@linaro.org> References: <20240526194254.459395-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::536; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x536.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1716752659981100003 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daud=C3=A9 Tested-by: Mark Cave-Ayland --- target/sparc/insns.decode | 1 + target/sparc/translate.c | 11 +++++++++++ 2 files changed, 12 insertions(+) diff --git a/target/sparc/insns.decode b/target/sparc/insns.decode index a7720560f8..fbcb4f7aef 100644 --- a/target/sparc/insns.decode +++ b/target/sparc/insns.decode @@ -124,6 +124,7 @@ CALL 01 i:s30 WRTICK_CMPR 10 10111 110000 ..... . ............. @n_r_ri WRSTICK 10 11000 110000 ..... . ............. @n_r_ri WRSTICK_CMPR 10 11001 110000 ..... . ............. @n_r_ri + WRMWAIT 10 11100 110000 ..... . ............. @n_r_ri ] # Before v8, rs1=3D=3D0 was WRY, and the rest executed as nop. [ diff --git a/target/sparc/translate.c b/target/sparc/translate.c index e3e92bcf83..dba0eaa30c 100644 --- a/target/sparc/translate.c +++ b/target/sparc/translate.c @@ -3344,6 +3344,17 @@ static void do_wrpowerdown(DisasContext *dc, TCGv sr= c) =20 TRANS(WRPOWERDOWN, POWERDOWN, do_wr_special, a, supervisor(dc), do_wrpower= down) =20 +static void do_wrmwait(DisasContext *dc, TCGv src) +{ + /* + * TODO: This is a stub version of mwait, which merely recognizes + * interrupts immediately and does not wait. + */ + dc->base.is_jmp =3D DISAS_EXIT; +} + +TRANS(WRMWAIT, VIS4, do_wr_special, a, true, do_wrmwait) + static void do_wrpsr(DisasContext *dc, TCGv src) { gen_helper_wrpsr(tcg_env, src); --=20 2.34.1 From nobody Mon Nov 25 08:36:39 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1716752831; cv=none; d=zohomail.com; s=zohoarc; b=OBKnII24MqI6FOl5F4NwmUS4MU2fdvqfdTVpLQIEbfv9OAZ4u9iENkVw7LNmywI4WeUYEa5ISemafE9uAj6Ji/6DWFGXaoEczFdNzRH+xMeMKqR0R3bswMsYUmGdeP6G+lHNfwy2pqQB/Y8vwG6ay9zzoX8UOgAGYVEDdbVkECU= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1716752831; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=rlbm4xMC/Lmwfgzv6+7V2/W9TFNWbl6hJzNLN1fFO5Y=; b=NicjVoZJKWkmN3Vt3HFvee04C51WceJNKkzU1sUHIs1DooxkJQgA6jMuNt5Q5YNcEoaZ2aeXZwUaykwuP/Y0fytoRyfRH3O7I+1IDDB+EPfLI9u1oUrxxUzG27DngAI4tnWdjH6tIjp6zdi60vnRejgq9XE45Yhs91rsvcf70f8= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1716752831258281.85217948475804; Sun, 26 May 2024 12:47:11 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1sBJmR-0000xS-25; Sun, 26 May 2024 15:43:43 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1sBJmD-0000R6-8o for qemu-devel@nongnu.org; Sun, 26 May 2024 15:43:29 -0400 Received: from mail-pl1-x630.google.com ([2607:f8b0:4864:20::630]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1sBJm9-0007mA-9d for qemu-devel@nongnu.org; Sun, 26 May 2024 15:43:28 -0400 Received: by mail-pl1-x630.google.com with SMTP id d9443c01a7336-1f44b5d0c50so16505195ad.2 for ; Sun, 26 May 2024 12:43:24 -0700 (PDT) Received: from stoup.. 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[174.21.72.5]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-1f46ad93c2esm28165935ad.263.2024.05.26.12.43.23 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 26 May 2024 12:43:23 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1716752604; x=1717357404; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=rlbm4xMC/Lmwfgzv6+7V2/W9TFNWbl6hJzNLN1fFO5Y=; b=fB+hvliVWD5pAjZZr3QYts0avWzEnScVKw6Rc82jWBmU9RUSdRe7qsCj5lZx3vX30n NgylDTtQVhMYy5TzlHggYJcAusVFNk0f/Fh0pAdWW+evxidHwQGgiMvWaCOSYajNTT3A nHO8Rg7pk8QyAwMfaLAGLHFMYZsoa5egB+6/M5/OhMdGZs3MJO0CDU4+lZdxw9AxL9U3 kYpPz+B7x5l50z6z/SA3W/X4kIxhylyRsVOwEfJk9YJ1QJR3wcJ/SXB1g0VLYmb3EySS Pe606/tT0LwfReGJyxnha9Dk8QlV93IC4gc7eDcH32hoJuqvwhYLd5cCI8iLBio9TK3x phuQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1716752604; x=1717357404; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=rlbm4xMC/Lmwfgzv6+7V2/W9TFNWbl6hJzNLN1fFO5Y=; b=IuC7YgKpkDEMwSAE3S4dqer5l0nVoGaWDE51GGkcRxLBz0R2PGmeslcxenEYrqr51t OWy0CG1df9kU0/hElu+lkn/GGHvAxvp0/Fy/Jf+Mioij1BFYmebBHmI68y0Rcb6W6Lk/ ceLuW8+n37xY682ScgsfjJo/1cv6dhpxUECiIbOR9AtxqVWyclii+w6b0oNmM4p6j4EM MSk9ief9LkrG80RgNvSDEPS+XI0rQcZzuyyWNGzxHANs5lZtrtTsZIYmvO8BYKVfXVJK gb4/GmSQavKoogNxiIREkgPV7HYU1WjmZ57xw2VRtRFH3RKTVTQNfKV2LlY/yW0uN/Pe tp1Q== X-Gm-Message-State: AOJu0Yzcn2P9/QxFNiR5dx11tPhihwiB8H2mUeYUoOUgJNStaahVQPkU Id7Niw9fOuoDzmJvI/MnbQp46HN8U4Ya6ABVjWIVnJj7UyVkWORy0YV5NXl3pHvmvCcEreHr3gm Q X-Google-Smtp-Source: AGHT+IGNHuyKyemrSsOohuov4tHqTScq3e/CRY58vcBRQYgGGula9KTMtcJogZsPY4QMgpZ9i5ztVA== X-Received: by 2002:a17:903:4114:b0:1eb:7172:673b with SMTP id d9443c01a7336-1f4486f1d23mr55513045ad.16.1716752603887; Sun, 26 May 2024 12:43:23 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: mark.cave-ayland@ilande.co.uk, =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH v2 36/37] target/sparc: Implement monitor ASIs Date: Sun, 26 May 2024 12:42:53 -0700 Message-Id: <20240526194254.459395-37-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240526194254.459395-1-richard.henderson@linaro.org> References: <20240526194254.459395-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::630; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x630.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1716752832601100006 Ignore the "monitor" portion and treat them the same as their base ASIs. Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Richard Henderson Tested-by: Mark Cave-Ayland --- target/sparc/asi.h | 4 ++++ target/sparc/ldst_helper.c | 4 ++++ target/sparc/translate.c | 8 ++++++++ 3 files changed, 16 insertions(+) diff --git a/target/sparc/asi.h b/target/sparc/asi.h index a66829674b..14ffaa3842 100644 --- a/target/sparc/asi.h +++ b/target/sparc/asi.h @@ -144,6 +144,8 @@ * ASIs, "(4V)" designates SUN4V specific ASIs. "(NG4)" designates SPARC-= T4 * and later ASIs. */ +#define ASI_MON_AIUP 0x12 /* (VIS4) Primary, user, monitor */ +#define ASI_MON_AIUS 0x13 /* (VIS4) Secondary, user, monitor */ #define ASI_REAL 0x14 /* Real address, cacheable */ #define ASI_PHYS_USE_EC 0x14 /* PADDR, E-cacheable */ #define ASI_REAL_IO 0x15 /* Real address, non-cacheable */ @@ -257,6 +259,8 @@ #define ASI_UDBL_CONTROL_R 0x7f /* External UDB control regs rd low*/ #define ASI_INTR_R 0x7f /* IRQ vector dispatch read */ #define ASI_INTR_DATAN_R 0x7f /* (III) In irq vector data reg N */ +#define ASI_MON_P 0x84 /* (VIS4) Primary, monitor */ +#define ASI_MON_S 0x85 /* (VIS4) Secondary, monitor */ #define ASI_PIC 0xb0 /* (NG4) PIC registers */ #define ASI_PST8_P 0xc0 /* Primary, 8 8-bit, partial */ #define ASI_PST8_S 0xc1 /* Secondary, 8 8-bit, partial */ diff --git a/target/sparc/ldst_helper.c b/target/sparc/ldst_helper.c index 7bdf99e0c0..2d48e98bf4 100644 --- a/target/sparc/ldst_helper.c +++ b/target/sparc/ldst_helper.c @@ -1395,6 +1395,10 @@ uint64_t helper_ld_asi(CPUSPARCState *env, target_ul= ong addr, case ASI_TWINX_PL: /* Primary, twinx, LE */ case ASI_TWINX_S: /* Secondary, twinx */ case ASI_TWINX_SL: /* Secondary, twinx, LE */ + case ASI_MON_P: + case ASI_MON_S: + case ASI_MON_AIUP: + case ASI_MON_AIUS: /* These are always handled inline. */ g_assert_not_reached(); =20 diff --git a/target/sparc/translate.c b/target/sparc/translate.c index dba0eaa30c..d2478a0246 100644 --- a/target/sparc/translate.c +++ b/target/sparc/translate.c @@ -1607,6 +1607,7 @@ static DisasASI resolve_asi(DisasContext *dc, int asi= , MemOp memop) case ASI_BLK_AIUP_L_4V: case ASI_BLK_AIUP: case ASI_BLK_AIUPL: + case ASI_MON_AIUP: mem_idx =3D MMU_USER_IDX; break; case ASI_AIUS: /* As if user secondary */ @@ -1617,6 +1618,7 @@ static DisasASI resolve_asi(DisasContext *dc, int asi= , MemOp memop) case ASI_BLK_AIUS_L_4V: case ASI_BLK_AIUS: case ASI_BLK_AIUSL: + case ASI_MON_AIUS: mem_idx =3D MMU_USER_SECONDARY_IDX; break; case ASI_S: /* Secondary */ @@ -1630,6 +1632,7 @@ static DisasASI resolve_asi(DisasContext *dc, int asi= , MemOp memop) case ASI_FL8_SL: case ASI_FL16_S: case ASI_FL16_SL: + case ASI_MON_S: if (mem_idx =3D=3D MMU_USER_IDX) { mem_idx =3D MMU_USER_SECONDARY_IDX; } else if (mem_idx =3D=3D MMU_KERNEL_IDX) { @@ -1647,6 +1650,7 @@ static DisasASI resolve_asi(DisasContext *dc, int asi= , MemOp memop) case ASI_FL8_PL: case ASI_FL16_P: case ASI_FL16_PL: + case ASI_MON_P: break; } switch (asi) { @@ -1664,6 +1668,10 @@ static DisasASI resolve_asi(DisasContext *dc, int as= i, MemOp memop) case ASI_SL: case ASI_P: case ASI_PL: + case ASI_MON_P: + case ASI_MON_S: + case ASI_MON_AIUP: + case ASI_MON_AIUS: type =3D GET_ASI_DIRECT; break; case ASI_TWINX_REAL: --=20 2.34.1 From nobody Mon Nov 25 08:36:39 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1716752635; cv=none; d=zohomail.com; s=zohoarc; b=d1ffLiHmMrtJtoulD8m7ZT41EgTVucgK9qA559f3OW+b+ffk+EH7zWJKQziCskaCTFApyX00UBAaa0+79jQWKrdOt66rcX+mP/4vHhjlrNLw/x1dPUy1Fl19dGgwCrNnxYcOirDbTEIp4cGz60qAZ7ZPG2duEA/zIpLyuFKG1oQ= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1716752635; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; 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[174.21.72.5]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-1f46ad93c2esm28165935ad.263.2024.05.26.12.43.24 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 26 May 2024 12:43:24 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1716752605; x=1717357405; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=2xkTnIJzxFSsgLxwFEGJgc9RCPD2wi0PV4sGMffGtxM=; b=O98WC+38BpZpX+/HWyUgf7DHEDIzcTW6/R24wqlAE9yrOxNvbceNmH459jBh3a/ERE GUGonLc5wCwo8oz/A5AaWLx9nHWR3XmiD7J4pKvxABRMrMVjbl34Dito+lwtR6QxEQrA YAFSoSFGCEU00rTAIjF+84rDW3Ofj/He/FhuXhSvA7ozBjxoPqXd9GbO2/qRO1IigQ9d t+SN+N609Lh6XBHsiyFN46MWQOz2c6Ign10fX/4F5a2+Rw468/rKnq45GZUFW0jSekIG Js+G6Tjw7faWvWhdRkGaC5UfRaFezGi+YVv8w75lfguN/8CwqZ7u6gr9CnbttZl68l6F w7lA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1716752605; x=1717357405; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=2xkTnIJzxFSsgLxwFEGJgc9RCPD2wi0PV4sGMffGtxM=; b=sB4KmWuMpZ2ccnho/9HXRfoZKcoB8jRR3Sw69bbPz5uB1114ND5MljlSJi94vuJ+z8 ZwaROh41Sa30j2CCOI9FDTQ/U7FuOGvOg6MoJvUN8GKBc8Inr7MJQNRxsQbcMbhAFReT BlSKWhF/sq5nz0QSql3h6TdS/BcLScHBASWpVsWQO8v+d4jvL8+71ptOuzUqwzutGGhp 6y0ATjZifj8FO6BQirzWb2LZcL0XZkS3e6aUGK7/q9lSEYtZ4ZfOAr0CzZCK5xKlKbh6 TSAUUcU3JFygwKn6kFivBRPhcYz9XKp62w2p0OZo2t5Yx8eO3BiSN5v0X7p7ODh2E4is 9PtA== X-Gm-Message-State: AOJu0Yw16p+2m27PQWTyxWjMj/aRHTIT76v1Awcag8xLem61PW6SWcBk oVhYPoVP/c284jUlRFt+FmR4y6FfjgeigCc15aCtI+xsnE8PqEiefSRilR6qNzRgqTd75yWfMyO q X-Google-Smtp-Source: AGHT+IGoGAFNbMYjr5ZS0AH7vYGoE2K6yt6BnQMFWTgoR97D+6JwHPnjeUjVBfc2v7Xv09WUhVlztA== X-Received: by 2002:a17:902:ea03:b0:1f3:81c:c17 with SMTP id d9443c01a7336-1f4481f22cfmr109993785ad.23.1716752604691; Sun, 26 May 2024 12:43:24 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: mark.cave-ayland@ilande.co.uk, =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH v2 37/37] target/sparc: Enable VIS4 feature bit Date: Sun, 26 May 2024 12:42:54 -0700 Message-Id: <20240526194254.459395-38-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240526194254.459395-1-richard.henderson@linaro.org> References: <20240526194254.459395-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::62d; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1716752636168100009 Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Richard Henderson Tested-by: Mark Cave-Ayland --- target/sparc/cpu.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/target/sparc/cpu.c b/target/sparc/cpu.c index 88da5254e8..9bacfb68cb 100644 --- a/target/sparc/cpu.c +++ b/target/sparc/cpu.c @@ -552,6 +552,7 @@ static const char * const feature_name[] =3D { [CPU_FEATURE_BIT_FMAF] =3D "fmaf", [CPU_FEATURE_BIT_VIS3] =3D "vis3", [CPU_FEATURE_BIT_IMA] =3D "ima", + [CPU_FEATURE_BIT_VIS4] =3D "vis4", #else [CPU_FEATURE_BIT_MUL] =3D "mul", [CPU_FEATURE_BIT_DIV] =3D "div", @@ -886,6 +887,8 @@ static Property sparc_cpu_properties[] =3D { CPU_FEATURE_BIT_VIS3, false), DEFINE_PROP_BIT("ima", SPARCCPU, env.def.features, CPU_FEATURE_BIT_IMA, false), + DEFINE_PROP_BIT("vis4", SPARCCPU, env.def.features, + CPU_FEATURE_BIT_VIS4, false), #else DEFINE_PROP_BIT("mul", SPARCCPU, env.def.features, CPU_FEATURE_BIT_MUL, false), --=20 2.34.1