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  3. [PATCH 0/5] target/riscv: Support RISC-V privilege 1.13 spec
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[PATCH 2/5] target/riscv: Support the version for ss1p13

Fea.Wang posted 5 patches 6 months, 2 weeks ago
There is a newer version of this series
[PATCH 2/5] target/riscv: Support the version for ss1p13
Posted by Fea.Wang 6 months, 2 weeks ago 
Add RISC-V privilege 1.13 support.

Signed-off-by: Fea.Wang <fea.wang@sifive.com>
Reviewed-by: Frank Chang <frank.chang@sifive.com>
---
 target/riscv/cpu.c         | 6 +++++-
 target/riscv/cpu.h         | 4 +++-
 target/riscv/cpu_cfg.h     | 1 +
 target/riscv/tcg/tcg-cpu.c | 4 ++++
 4 files changed, 13 insertions(+), 2 deletions(-)

diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index b6b48e5620..a6298c3298 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -1773,7 +1773,9 @@ int priv_spec_from_str(const char *priv_spec_str)
 {
     int priv_version = -1;
 
-    if (!g_strcmp0(priv_spec_str, PRIV_VER_1_12_0_STR)) {
+    if (!g_strcmp0(priv_spec_str, PRIV_VER_1_13_0_STR)) {
+        priv_version = PRIV_VERSION_1_13_0;
+    } else if (!g_strcmp0(priv_spec_str, PRIV_VER_1_12_0_STR)) {
         priv_version = PRIV_VERSION_1_12_0;
     } else if (!g_strcmp0(priv_spec_str, PRIV_VER_1_11_0_STR)) {
         priv_version = PRIV_VERSION_1_11_0;
@@ -1793,6 +1795,8 @@ const char *priv_spec_to_str(int priv_version)
         return PRIV_VER_1_11_0_STR;
     case PRIV_VERSION_1_12_0:
         return PRIV_VER_1_12_0_STR;
+    case PRIV_VERSION_1_13_0:
+        return PRIV_VER_1_13_0_STR;
     default:
         return NULL;
     }
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index 7696102697..776939b56b 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -96,12 +96,14 @@ extern RISCVCPUProfile *riscv_profiles[];
 #define PRIV_VER_1_10_0_STR "v1.10.0"
 #define PRIV_VER_1_11_0_STR "v1.11.0"
 #define PRIV_VER_1_12_0_STR "v1.12.0"
+#define PRIV_VER_1_13_0_STR "v1.13.0"
 enum {
     PRIV_VERSION_1_10_0 = 0,
     PRIV_VERSION_1_11_0,
     PRIV_VERSION_1_12_0,
+    PRIV_VERSION_1_13_0,
 
-    PRIV_VERSION_LATEST = PRIV_VERSION_1_12_0,
+    PRIV_VERSION_LATEST = PRIV_VERSION_1_13_0,
 };
 
 #define VEXT_VERSION_1_00_0 0x00010000
diff --git a/target/riscv/cpu_cfg.h b/target/riscv/cpu_cfg.h
index e1e4f32698..fb7eebde52 100644
--- a/target/riscv/cpu_cfg.h
+++ b/target/riscv/cpu_cfg.h
@@ -136,6 +136,7 @@ struct RISCVCPUConfig {
      * TCG always implement/can't be user disabled,
      * based on spec version.
      */
+    bool has_priv_1_13;
     bool has_priv_1_12;
     bool has_priv_1_11;
 
diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c
index faa8de9b83..a9d188a9fd 100644
--- a/target/riscv/tcg/tcg-cpu.c
+++ b/target/riscv/tcg/tcg-cpu.c
@@ -320,6 +320,10 @@ static void riscv_cpu_update_named_features(RISCVCPU *cpu)
         cpu->cfg.has_priv_1_12 = true;
     }
 
+    if (cpu->env.priv_ver >= PRIV_VERSION_1_13_0) {
+        cpu->cfg.has_priv_1_13 = true;
+    }
+
     /* zic64b is 1.12 or later */
     cpu->cfg.ext_zic64b = cpu->cfg.cbom_blocksize == 64 &&
                           cpu->cfg.cbop_blocksize == 64 &&
-- 
2.34.1
Re: [PATCH 2/5] target/riscv: Support the version for ss1p13
Posted by LIU Zhiwei 6 months, 2 weeks ago 
On 2024/5/10 14:58, Fea.Wang wrote:
> Add RISC-V privilege 1.13 support.
>
> Signed-off-by: Fea.Wang <fea.wang@sifive.com>
> Reviewed-by: Frank Chang <frank.chang@sifive.com>

Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>

Zhiwei

> ---
>   target/riscv/cpu.c         | 6 +++++-
>   target/riscv/cpu.h         | 4 +++-
>   target/riscv/cpu_cfg.h     | 1 +
>   target/riscv/tcg/tcg-cpu.c | 4 ++++
>   4 files changed, 13 insertions(+), 2 deletions(-)
>
> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> index b6b48e5620..a6298c3298 100644
> --- a/target/riscv/cpu.c
> +++ b/target/riscv/cpu.c
> @@ -1773,7 +1773,9 @@ int priv_spec_from_str(const char *priv_spec_str)
>   {
>       int priv_version = -1;
>   
> -    if (!g_strcmp0(priv_spec_str, PRIV_VER_1_12_0_STR)) {
> +    if (!g_strcmp0(priv_spec_str, PRIV_VER_1_13_0_STR)) {
> +        priv_version = PRIV_VERSION_1_13_0;
> +    } else if (!g_strcmp0(priv_spec_str, PRIV_VER_1_12_0_STR)) {
>           priv_version = PRIV_VERSION_1_12_0;
>       } else if (!g_strcmp0(priv_spec_str, PRIV_VER_1_11_0_STR)) {
>           priv_version = PRIV_VERSION_1_11_0;
> @@ -1793,6 +1795,8 @@ const char *priv_spec_to_str(int priv_version)
>           return PRIV_VER_1_11_0_STR;
>       case PRIV_VERSION_1_12_0:
>           return PRIV_VER_1_12_0_STR;
> +    case PRIV_VERSION_1_13_0:
> +        return PRIV_VER_1_13_0_STR;
>       default:
>           return NULL;
>       }
> diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
> index 7696102697..776939b56b 100644
> --- a/target/riscv/cpu.h
> +++ b/target/riscv/cpu.h
> @@ -96,12 +96,14 @@ extern RISCVCPUProfile *riscv_profiles[];
>   #define PRIV_VER_1_10_0_STR "v1.10.0"
>   #define PRIV_VER_1_11_0_STR "v1.11.0"
>   #define PRIV_VER_1_12_0_STR "v1.12.0"
> +#define PRIV_VER_1_13_0_STR "v1.13.0"
>   enum {
>       PRIV_VERSION_1_10_0 = 0,
>       PRIV_VERSION_1_11_0,
>       PRIV_VERSION_1_12_0,
> +    PRIV_VERSION_1_13_0,
>   
> -    PRIV_VERSION_LATEST = PRIV_VERSION_1_12_0,
> +    PRIV_VERSION_LATEST = PRIV_VERSION_1_13_0,
>   };
>   
>   #define VEXT_VERSION_1_00_0 0x00010000
> diff --git a/target/riscv/cpu_cfg.h b/target/riscv/cpu_cfg.h
> index e1e4f32698..fb7eebde52 100644
> --- a/target/riscv/cpu_cfg.h
> +++ b/target/riscv/cpu_cfg.h
> @@ -136,6 +136,7 @@ struct RISCVCPUConfig {
>        * TCG always implement/can't be user disabled,
>        * based on spec version.
>        */
> +    bool has_priv_1_13;
>       bool has_priv_1_12;
>       bool has_priv_1_11;
>   
> diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c
> index faa8de9b83..a9d188a9fd 100644
> --- a/target/riscv/tcg/tcg-cpu.c
> +++ b/target/riscv/tcg/tcg-cpu.c
> @@ -320,6 +320,10 @@ static void riscv_cpu_update_named_features(RISCVCPU *cpu)
>           cpu->cfg.has_priv_1_12 = true;
>       }
>   
> +    if (cpu->env.priv_ver >= PRIV_VERSION_1_13_0) {
> +        cpu->cfg.has_priv_1_13 = true;
> +    }
> +
>       /* zic64b is 1.12 or later */
>       cpu->cfg.ext_zic64b = cpu->cfg.cbom_blocksize == 64 &&
>                             cpu->cfg.cbop_blocksize == 64 &&
Re: [PATCH 2/5] target/riscv: Support the version for ss1p13
Posted by liwei 6 months, 2 weeks ago 
On 2024/5/10 14:58, Fea.Wang wrote:
> Add RISC-V privilege 1.13 support.
>
> Signed-off-by: Fea.Wang <fea.wang@sifive.com>
> Reviewed-by: Frank Chang <frank.chang@sifive.com>
> ---
>   target/riscv/cpu.c         | 6 +++++-
>   target/riscv/cpu.h         | 4 +++-
>   target/riscv/cpu_cfg.h     | 1 +
>   target/riscv/tcg/tcg-cpu.c | 4 ++++
>   4 files changed, 13 insertions(+), 2 deletions(-)
Reviewed-by:  Weiwei Li <liwei1518@gmail.com>

Weiwei Li
>
> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> index b6b48e5620..a6298c3298 100644
> --- a/target/riscv/cpu.c
> +++ b/target/riscv/cpu.c
> @@ -1773,7 +1773,9 @@ int priv_spec_from_str(const char *priv_spec_str)
>   {
>       int priv_version = -1;
>   
> -    if (!g_strcmp0(priv_spec_str, PRIV_VER_1_12_0_STR)) {
> +    if (!g_strcmp0(priv_spec_str, PRIV_VER_1_13_0_STR)) {
> +        priv_version = PRIV_VERSION_1_13_0;
> +    } else if (!g_strcmp0(priv_spec_str, PRIV_VER_1_12_0_STR)) {
>           priv_version = PRIV_VERSION_1_12_0;
>       } else if (!g_strcmp0(priv_spec_str, PRIV_VER_1_11_0_STR)) {
>           priv_version = PRIV_VERSION_1_11_0;
> @@ -1793,6 +1795,8 @@ const char *priv_spec_to_str(int priv_version)
>           return PRIV_VER_1_11_0_STR;
>       case PRIV_VERSION_1_12_0:
>           return PRIV_VER_1_12_0_STR;
> +    case PRIV_VERSION_1_13_0:
> +        return PRIV_VER_1_13_0_STR;
>       default:
>           return NULL;
>       }
> diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
> index 7696102697..776939b56b 100644
> --- a/target/riscv/cpu.h
> +++ b/target/riscv/cpu.h
> @@ -96,12 +96,14 @@ extern RISCVCPUProfile *riscv_profiles[];
>   #define PRIV_VER_1_10_0_STR "v1.10.0"
>   #define PRIV_VER_1_11_0_STR "v1.11.0"
>   #define PRIV_VER_1_12_0_STR "v1.12.0"
> +#define PRIV_VER_1_13_0_STR "v1.13.0"
>   enum {
>       PRIV_VERSION_1_10_0 = 0,
>       PRIV_VERSION_1_11_0,
>       PRIV_VERSION_1_12_0,
> +    PRIV_VERSION_1_13_0,
>   
> -    PRIV_VERSION_LATEST = PRIV_VERSION_1_12_0,
> +    PRIV_VERSION_LATEST = PRIV_VERSION_1_13_0,
>   };
>   
>   #define VEXT_VERSION_1_00_0 0x00010000
> diff --git a/target/riscv/cpu_cfg.h b/target/riscv/cpu_cfg.h
> index e1e4f32698..fb7eebde52 100644
> --- a/target/riscv/cpu_cfg.h
> +++ b/target/riscv/cpu_cfg.h
> @@ -136,6 +136,7 @@ struct RISCVCPUConfig {
>        * TCG always implement/can't be user disabled,
>        * based on spec version.
>        */
> +    bool has_priv_1_13;
>       bool has_priv_1_12;
>       bool has_priv_1_11;
>   
> diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c
> index faa8de9b83..a9d188a9fd 100644
> --- a/target/riscv/tcg/tcg-cpu.c
> +++ b/target/riscv/tcg/tcg-cpu.c
> @@ -320,6 +320,10 @@ static void riscv_cpu_update_named_features(RISCVCPU *cpu)
>           cpu->cfg.has_priv_1_12 = true;
>       }
>   
> +    if (cpu->env.priv_ver >= PRIV_VERSION_1_13_0) {
> +        cpu->cfg.has_priv_1_13 = true;
> +    }
> +
>       /* zic64b is 1.12 or later */
>       cpu->cfg.ext_zic64b = cpu->cfg.cbom_blocksize == 64 &&
>                             cpu->cfg.cbop_blocksize == 64 &&

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