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[59.124.168.89]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-1ef0bf31a7asm25579175ad.140.2024.05.09.23.53.33 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 09 May 2024 23:53:35 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; t=1715324015; x=1715928815; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=VAsL4QSkEAe6lAFIQlVDgyR+n6eZ4E85ah8Bz0EmYD0=; b=SVVRpz/GwFF9uMyfbiOV9+yei4et7thMAB9J/RAHg33CGzWKyPovW2Jp4SiviXLUGi E8xizI+cIM/YVT8Zha/TdoRc5XcbBNs1rWoRcdG1k1azArs2/7pqknqlS5DdUO342P0G FPbIAqdIMBEnXDkYhUeSaJjtPXSTtGp0eZug8AejzqnzYwSqAWbffh6RgpgTTwYoFmNj SU79r2NE96Tn5pRKuICL5lIkBUXi53kKdTEChBlYtmyemTrEfoobqztzYRQElbIzGx10 O03N8HItbTXZunExH+rr2JrzC4uJx47btqEvLx2pkaWn593tPemmNqVOLsJAkr+2W/Or cpNA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1715324015; x=1715928815; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=VAsL4QSkEAe6lAFIQlVDgyR+n6eZ4E85ah8Bz0EmYD0=; b=uYcDtX3JYhoctlNfmEwQHARg/rdih3cCNq/NqO6lHB6fjendFI2I5LnBRRfJHtlvVh hHJbnifTbfknZnNRgHZMNrfjcYgQFD6EFwp8ZgVfP1ETr/D5jj4TMKUawsZY4/T2ctZL OoV51X/12FdslAna1afo07BapFXtyPM2FureRueROQH8nFkqRJLdct1FdSHpoyE8Vs/U aJQJ/8rMnjMp11weHH8+lavTV3CTcg/mjze5wnflV6H9gTa7UnkaBhhp3Wn/SDGmP93S Am2bx7DyGcR9nUK2A2Yw2HGDD/XHtZggSewhNI4z/A8GS8M4g4Li3eUOT/0PDouNz78a oSSQ== X-Gm-Message-State: AOJu0Yyr6OENRys73z1AeJ/FW+bsg0N2HWsQuUZTkcBMD7lZoWLo9Jo2 91bwD7TfmpuA15cg1AalG/wfcFVhdbewChE03S6Cxvh8hha3ouW+T+AlieIeOtiCrEcjOz+A5o9 sD8qrGpNIBhTtaS9luauVbfGKg7uFtG2v8+5XyzSJ3ullBzidu/CaoIo3I2YDxtydWWZz1zOGbG 4479Fz6eI3a21KmBGiGEcv3Fd8rAqbUK/yj/MF5A== X-Google-Smtp-Source: AGHT+IFB/h0yf0oUPaFIYpT5TbgQkYZMBTvyBBPDGTbnqSCimmq/zEPgB4SaDGJWomYSgwV2V77NRA== X-Received: by 2002:a05:6a20:96cd:b0:1aa:4289:5921 with SMTP id adf61e73a8af0-1afde1b0187mr1686905637.50.1715324015361; Thu, 09 May 2024 23:53:35 -0700 (PDT) From: "Fea.Wang" To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Cc: "Fea.Wang" , Frank Chang , Palmer Dabbelt , Alistair Francis , Bin Meng , Weiwei Li , Daniel Henrique Barboza , Liu Zhiwei , Andrew Jones , Max Chou Subject: [PATCH 2/5] target/riscv: Support the version for ss1p13 Date: Fri, 10 May 2024 14:58:52 +0800 Message-Id: <20240510065856.2436870-3-fea.wang@sifive.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240510065856.2436870-1-fea.wang@sifive.com> References: <20240510065856.2436870-1-fea.wang@sifive.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::42f; envelope-from=fea.wang@sifive.com; helo=mail-pf1-x42f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-Mailman-Approved-At: Fri, 10 May 2024 09:17:57 -0400 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @sifive.com) X-ZM-MESSAGEID: 1715347150021100003 Content-Type: text/plain; charset="utf-8" Add RISC-V privilege 1.13 support. Signed-off-by: Fea.Wang Reviewed-by: Frank Chang Reviewed-by: LIU Zhiwei Reviewed-by:=C2=A0 Weiwei Li --- target/riscv/cpu.c | 6 +++++- target/riscv/cpu.h | 4 +++- target/riscv/cpu_cfg.h | 1 + target/riscv/tcg/tcg-cpu.c | 4 ++++ 4 files changed, 13 insertions(+), 2 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index b6b48e5620..a6298c3298 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -1773,7 +1773,9 @@ int priv_spec_from_str(const char *priv_spec_str) { int priv_version =3D -1; =20 - if (!g_strcmp0(priv_spec_str, PRIV_VER_1_12_0_STR)) { + if (!g_strcmp0(priv_spec_str, PRIV_VER_1_13_0_STR)) { + priv_version =3D PRIV_VERSION_1_13_0; + } else if (!g_strcmp0(priv_spec_str, PRIV_VER_1_12_0_STR)) { priv_version =3D PRIV_VERSION_1_12_0; } else if (!g_strcmp0(priv_spec_str, PRIV_VER_1_11_0_STR)) { priv_version =3D PRIV_VERSION_1_11_0; @@ -1793,6 +1795,8 @@ const char *priv_spec_to_str(int priv_version) return PRIV_VER_1_11_0_STR; case PRIV_VERSION_1_12_0: return PRIV_VER_1_12_0_STR; + case PRIV_VERSION_1_13_0: + return PRIV_VER_1_13_0_STR; default: return NULL; } diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 7696102697..776939b56b 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -96,12 +96,14 @@ extern RISCVCPUProfile *riscv_profiles[]; #define PRIV_VER_1_10_0_STR "v1.10.0" #define PRIV_VER_1_11_0_STR "v1.11.0" #define PRIV_VER_1_12_0_STR "v1.12.0" +#define PRIV_VER_1_13_0_STR "v1.13.0" enum { PRIV_VERSION_1_10_0 =3D 0, PRIV_VERSION_1_11_0, PRIV_VERSION_1_12_0, + PRIV_VERSION_1_13_0, =20 - PRIV_VERSION_LATEST =3D PRIV_VERSION_1_12_0, + PRIV_VERSION_LATEST =3D PRIV_VERSION_1_13_0, }; =20 #define VEXT_VERSION_1_00_0 0x00010000 diff --git a/target/riscv/cpu_cfg.h b/target/riscv/cpu_cfg.h index e1e4f32698..fb7eebde52 100644 --- a/target/riscv/cpu_cfg.h +++ b/target/riscv/cpu_cfg.h @@ -136,6 +136,7 @@ struct RISCVCPUConfig { * TCG always implement/can't be user disabled, * based on spec version. */ + bool has_priv_1_13; bool has_priv_1_12; bool has_priv_1_11; =20 diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c index faa8de9b83..a9d188a9fd 100644 --- a/target/riscv/tcg/tcg-cpu.c +++ b/target/riscv/tcg/tcg-cpu.c @@ -320,6 +320,10 @@ static void riscv_cpu_update_named_features(RISCVCPU *= cpu) cpu->cfg.has_priv_1_12 =3D true; } =20 + if (cpu->env.priv_ver >=3D PRIV_VERSION_1_13_0) { + cpu->cfg.has_priv_1_13 =3D true; + } + /* zic64b is 1.12 or later */ cpu->cfg.ext_zic64b =3D cpu->cfg.cbom_blocksize =3D=3D 64 && cpu->cfg.cbop_blocksize =3D=3D 64 && --=20 2.34.1