[PULL 0/2] target-arm queue
[PULL v2 00/32] target-arm queue
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Two bug fixes for 9.0...
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For some reason the xilinx can bus patches built in my local config
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but not in the merge-test ones; dropped those.
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-- PMM
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-- PMM
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The following changes since commit ce64e6224affb8b4e4b019f76d2950270b391af5:
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The following changes since commit a68694cd1f3e5448cca814ff39b871f9ebd71ed5:
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Merge tag 'qemu-sparc-20240404' of https://github.com/mcayland/qemu into staging (2024-04-04 15:28:06 +0100)
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Merge remote-tracking branch 'remotes/philmd-gitlab/tags/edk2-next-20200914' into staging (2020-09-14 12:18:58 +0100)
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are available in the Git repository at:
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are available in the Git repository at:
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https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20240408
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https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20200914-1
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for you to fetch changes up to 19b254e86a900dc5ee332e3ac0baf9c521301abf:
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for you to fetch changes up to 4fe986dd4480308ecf07200cfbd3c3d494a0f639:
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target/arm: Use correct SecuritySpace for AArch64 AT ops at EL3 (2024-04-08 15:38:53 +0100)
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tests/acceptance: console boot tests for quanta-gsj (2020-09-14 14:24:59 +0100)
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----------------------------------------------------------------
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----------------------------------------------------------------
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target-arm:
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* hw/misc/a9scu: Do not allow invalid CPU count
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* Use correct SecuritySpace for AArch64 AT ops at EL3
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* hw/misc/a9scu: Minor cleanups
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* Fix CNTPOFF_EL2 trap to missing EL3
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* hw/timer/armv7m_systick: assert that board code set system_clock_scale
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* decodetree: Improve identifier matching
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* target/arm: Clean up neon fp insn size field decode
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* target/arm: Remove KVM support for 32-bit Arm hosts
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* hw/arm/mps2: New board models mps2-an386, mps2-an500
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* Deprecate Unicore32 port
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* Deprecate lm32 port
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* target/arm: Count PMU events when MDCR.SPME is set
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* hw/arm: versal-virt: Correct the tx/rx GEM clocks
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* New Nuvoton iBMC board models npcm750-evb, quanta-gsj
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----------------------------------------------------------------
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----------------------------------------------------------------
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Peter Maydell (1):
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Aaron Lindsay (1):
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target/arm: Use correct SecuritySpace for AArch64 AT ops at EL3
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target/arm: Count PMU events when MDCR.SPME is set
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Pierre-Clément Tosi (1):
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Edgar E. Iglesias (1):
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target/arm: Fix CNTPOFF_EL2 trap to missing EL3
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hw/arm: versal-virt: Correct the tx/rx GEM clocks
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target/arm/helper.c | 10 +++++++---
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Havard Skinnemoen (14):
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1 file changed, 7 insertions(+), 3 deletions(-)
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hw/misc: Add NPCM7xx System Global Control Registers device model
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hw/misc: Add NPCM7xx Clock Controller device model
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hw/timer: Add NPCM7xx Timer device model
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hw/arm: Add NPCM730 and NPCM750 SoC models
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hw/arm: Add two NPCM7xx-based machines
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roms: Add virtual Boot ROM for NPCM7xx SoCs
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hw/arm: Load -bios image as a boot ROM for npcm7xx
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hw/nvram: NPCM7xx OTP device model
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hw/mem: Stubbed out NPCM7xx Memory Controller model
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hw/ssi: NPCM7xx Flash Interface Unit device model
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hw/arm: Wire up BMC boot flash for npcm750-evb and quanta-gsj
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hw/arm/npcm7xx: add board setup stub for CPU and UART clocks
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docs/system: Add Nuvoton machine documentation
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tests/acceptance: console boot tests for quanta-gsj
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Peter Maydell (11):
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hw/timer/armv7m_systick: assert that board code set system_clock_scale
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target/arm: Convert Neon 3-same-fp size field to MO_* in decode
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target/arm: Convert Neon VCVT fp size field to MO_* in decode
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target/arm: Convert VCMLA, VCADD size field to MO_* in decode
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target/arm: Remove KVM support for 32-bit Arm hosts
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target/arm: Remove no-longer-reachable 32-bit KVM code
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hw/arm/mps2: New board model mps2-an386
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hw/arm/mps2: New board model mps2-an500
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docs/system/arm/mps2.rst: Make board list consistent
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Deprecate Unicore32 port
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Deprecate lm32 port
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Philippe Mathieu-Daudé (4):
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hw/misc/a9scu: Do not allow invalid CPU count
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hw/misc/a9scu: Simplify setting MemoryRegionOps::valid fields
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hw/misc/a9scu: Simplify setting MemoryRegionOps::impl fields
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hw/misc/a9scu: Report unimplemented accesses with qemu_log_mask(UNIMP)
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Richard Henderson (1):
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decodetree: Improve identifier matching
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docs/system/arm/mps2.rst | 20 +-
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docs/system/arm/nuvoton.rst | 92 +++++
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docs/system/deprecated.rst | 32 +-
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docs/system/target-arm.rst | 1 +
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configure | 2 +-
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default-configs/arm-softmmu.mak | 1 +
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include/hw/arm/npcm7xx.h | 112 +++++++
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include/hw/mem/npcm7xx_mc.h | 36 ++
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include/hw/misc/npcm7xx_clk.h | 48 +++
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include/hw/misc/npcm7xx_gcr.h | 43 +++
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include/hw/nvram/npcm7xx_otp.h | 79 +++++
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include/hw/ssi/npcm7xx_fiu.h | 73 ++++
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include/hw/timer/npcm7xx_timer.h | 78 +++++
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target/arm/kvm-consts.h | 7 -
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target/arm/kvm_arm.h | 6 -
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target/arm/neon-dp.decode | 18 +-
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target/arm/neon-shared.decode | 18 +-
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tests/decode/succ_ident1.decode | 7 +
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hw/arm/mps2.c | 97 +++++-
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hw/arm/npcm7xx.c | 532 +++++++++++++++++++++++++++++
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hw/arm/npcm7xx_boards.c | 197 +++++++++++
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hw/arm/xlnx-versal-virt.c | 2 +-
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hw/mem/npcm7xx_mc.c | 84 +++++
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hw/misc/a9scu.c | 59 ++--
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hw/misc/npcm7xx_clk.c | 266 +++++++++++++++
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hw/misc/npcm7xx_gcr.c | 269 +++++++++++++++
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hw/nvram/npcm7xx_otp.c | 440 ++++++++++++++++++++++++
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hw/ssi/npcm7xx_fiu.c | 572 +++++++++++++++++++++++++++++++
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hw/timer/armv7m_systick.c | 8 +
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hw/timer/npcm7xx_timer.c | 543 ++++++++++++++++++++++++++++++
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target/arm/cpu.c | 101 +++---
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target/arm/helper.c | 2 +-
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target/arm/kvm.c | 7 -
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target/arm/kvm32.c | 595 ---------------------------------
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.gitmodules | 3 +
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MAINTAINERS | 10 +
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hw/arm/Kconfig | 9 +
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hw/arm/meson.build | 1 +
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hw/mem/meson.build | 1 +
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hw/misc/meson.build | 4 +
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hw/misc/trace-events | 8 +
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hw/nvram/meson.build | 1 +
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hw/ssi/meson.build | 1 +
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hw/ssi/trace-events | 11 +
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hw/timer/meson.build | 1 +
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hw/timer/trace-events | 5 +
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pc-bios/README | 6 +
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pc-bios/meson.build | 1 +
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pc-bios/npcm7xx_bootrom.bin | Bin 0 -> 768 bytes
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roms/Makefile | 7 +
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roms/vbootrom | 1 +
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scripts/decodetree.py | 46 ++-
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target/arm/meson.build | 5 +-
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target/arm/translate-neon.c.inc | 42 ++-
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tests/acceptance/boot_linux_console.py | 83 +++++
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55 files changed, 3910 insertions(+), 783 deletions(-)
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create mode 100644 docs/system/arm/nuvoton.rst
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create mode 100644 include/hw/arm/npcm7xx.h
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create mode 100644 include/hw/mem/npcm7xx_mc.h
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create mode 100644 include/hw/misc/npcm7xx_clk.h
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create mode 100644 include/hw/misc/npcm7xx_gcr.h
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create mode 100644 include/hw/nvram/npcm7xx_otp.h
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create mode 100644 include/hw/ssi/npcm7xx_fiu.h
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create mode 100644 include/hw/timer/npcm7xx_timer.h
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create mode 100644 tests/decode/succ_ident1.decode
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create mode 100644 hw/arm/npcm7xx.c
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create mode 100644 hw/arm/npcm7xx_boards.c
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create mode 100644 hw/mem/npcm7xx_mc.c
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create mode 100644 hw/misc/npcm7xx_clk.c
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create mode 100644 hw/misc/npcm7xx_gcr.c
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create mode 100644 hw/nvram/npcm7xx_otp.c
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create mode 100644 hw/ssi/npcm7xx_fiu.c
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create mode 100644 hw/timer/npcm7xx_timer.c
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delete mode 100644 target/arm/kvm32.c
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create mode 100644 pc-bios/npcm7xx_bootrom.bin
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create mode 160000 roms/vbootrom
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diff view generated by jsdifflib
[PULL 1/2] target/arm: Fix CNTPOFF_EL2 trap to missing EL3
Deleted patch
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From: Pierre-Clément Tosi <ptosi@google.com>
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1
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EL2 accesses to CNTPOFF_EL2 should only ever trap to EL3 if EL3 is
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present, as described by the reference manual (for MRS):
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/* ... */
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elsif PSTATE.EL == EL2 then
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if Halted() && HaveEL(EL3) && /*...*/ then
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UNDEFINED;
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elsif HaveEL(EL3) && SCR_EL3.ECVEn == '0' then
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/* ... */
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else
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X[t, 64] = CNTPOFF_EL2;
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However, the existing implementation of gt_cntpoff_access() always
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returns CP_ACCESS_TRAP_EL3 for EL2 accesses with SCR_EL3.ECVEn unset. In
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pseudo-code terminology, this corresponds to assuming that HaveEL(EL3)
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is always true, which is wrong. As a result, QEMU panics in
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access_check_cp_reg() when started without EL3 and running EL2 code
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accessing the register (e.g. any recent KVM booting a guest).
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Therefore, add the HaveEL(EL3) check to gt_cntpoff_access().
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Fixes: 2808d3b38a52 ("target/arm: Implement FEAT_ECV CNTPOFF_EL2 handling")
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Signed-off-by: Pierre-Clément Tosi <ptosi@google.com>
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Message-id: m3al6amhdkmsiy2f62w72ufth6dzn45xg5cz6xljceyibphnf4@ezmmpwk4tnhl
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Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
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Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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---
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target/arm/helper.c | 3 ++-
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1 file changed, 2 insertions(+), 1 deletion(-)
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diff --git a/target/arm/helper.c b/target/arm/helper.c
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index XXXXXXX..XXXXXXX 100644
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--- a/target/arm/helper.c
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+++ b/target/arm/helper.c
37
@@ -XXX,XX +XXX,XX @@ static CPAccessResult gt_cntpoff_access(CPUARMState *env,
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const ARMCPRegInfo *ri,
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bool isread)
40
{
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- if (arm_current_el(env) == 2 && !(env->cp15.scr_el3 & SCR_ECVEN)) {
42
+ if (arm_current_el(env) == 2 && arm_feature(env, ARM_FEATURE_EL3) &&
43
+ !(env->cp15.scr_el3 & SCR_ECVEN)) {
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return CP_ACCESS_TRAP_EL3;
45
}
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return CP_ACCESS_OK;
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--
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2.34.1
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diff view generated by jsdifflib
[PULL 2/2] target/arm: Use correct SecuritySpace for AArch64 AT ops at EL3
Deleted patch
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When we do an AT address translation operation, the page table walk
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is supposed to be performed in the context of the EL we're doing the
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walk for, so for instance an AT S1E2R walk is done for EL2. In the
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pseudocode an EL is passed to AArch64.AT(), which calls
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SecurityStateAtEL() to find the security state that we should be
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doing the walk with.
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1
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In ats_write64() we get this wrong, instead using the current
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security space always. This is fine for AT operations performed from
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EL1 and EL2, because there the current security state and the
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security state for the lower EL are the same. But for AT operations
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performed from EL3, the current security state is always either
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Secure or Root, whereas we want to use the security state defined by
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SCR_EL3.{NS,NSE} for the walk. This affects not just guests using
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FEAT_RME but also ones where EL3 is Secure state and the EL3 code
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is trying to do an AT for a NonSecure EL2 or EL1.
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Use arm_security_space_below_el3() to get the SecuritySpace to
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pass to do_ats_write() for all AT operations except the
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AT S1E3* operations.
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Cc: qemu-stable@nongnu.org
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Fixes: e1ee56ec2383 ("target/arm: Pass security space rather than flag for AT instructions")
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Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2250
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Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
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Message-id: 20240405180232.3570066-1-peter.maydell@linaro.org
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---
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target/arm/helper.c | 7 +++++--
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1 file changed, 5 insertions(+), 2 deletions(-)
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diff --git a/target/arm/helper.c b/target/arm/helper.c
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index XXXXXXX..XXXXXXX 100644
34
--- a/target/arm/helper.c
35
+++ b/target/arm/helper.c
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@@ -XXX,XX +XXX,XX @@ static void ats_write64(CPUARMState *env, const ARMCPRegInfo *ri,
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ARMMMUIdx mmu_idx;
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uint64_t hcr_el2 = arm_hcr_el2_eff(env);
39
bool regime_e20 = (hcr_el2 & (HCR_E2H | HCR_TGE)) == (HCR_E2H | HCR_TGE);
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+ bool for_el3 = false;
41
+ ARMSecuritySpace ss;
42
43
switch (ri->opc2 & 6) {
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case 0:
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@@ -XXX,XX +XXX,XX @@ static void ats_write64(CPUARMState *env, const ARMCPRegInfo *ri,
46
break;
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case 6: /* AT S1E3R, AT S1E3W */
48
mmu_idx = ARMMMUIdx_E3;
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+ for_el3 = true;
50
break;
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default:
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g_assert_not_reached();
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@@ -XXX,XX +XXX,XX @@ static void ats_write64(CPUARMState *env, const ARMCPRegInfo *ri,
54
g_assert_not_reached();
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}
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57
- env->cp15.par_el[1] = do_ats_write(env, value, access_type,
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- mmu_idx, arm_security_space(env));
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+ ss = for_el3 ? arm_security_space(env) : arm_security_space_below_el3(env);
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+ env->cp15.par_el[1] = do_ats_write(env, value, access_type, mmu_idx, ss);
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#else
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/* Handled by hardware accelerator. */
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g_assert_not_reached();
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--
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2.34.1
diff view generated by jsdifflib

Patchew 2.1-devel-b67e4c2

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