[v1] misc ppc patches

[PATCH 10/13] spapr: set MSR[ME] and MSR[FP] on client entry

Posted by Nicholas Piggin 8 months, 2 weeks ago

The initial MSR state for PAPR specifies MSR[ME] and MSR[FP] are set.

Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
---
 hw/ppc/spapr_cpu_core.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/hw/ppc/spapr_cpu_core.c b/hw/ppc/spapr_cpu_core.c
index 50523ead25..f3b01b0801 100644
--- a/hw/ppc/spapr_cpu_core.c
+++ b/hw/ppc/spapr_cpu_core.c
@@ -42,6 +42,8 @@ static void spapr_reset_vcpu(PowerPCCPU *cpu)
      * as 32bit (MSR_SF=0) in "8.2.1. Initial Register Values".
      */
     env->msr &= ~(1ULL << MSR_SF);
+    env->msr |= (1ULL << MSR_ME) | (1ULL << MSR_FP);
+
     env->spr[SPR_HIOR] = 0;
 
     lpcr = env->spr[SPR_LPCR];
-- 
2.42.0

Re: [PATCH 10/13] spapr: set MSR[ME] and MSR[FP] on client entry

Posted by Harsh Prateek Bora 8 months, 2 weeks ago


On 3/12/24 00:21, Nicholas Piggin wrote:
> The initial MSR state for PAPR specifies MSR[ME] and MSR[FP] are set.
> 
> Signed-off-by: Nicholas Piggin <npiggin@gmail.com>

It would be good to mention PAPR section numbers suggesting the same.
Anyways,

Reviewed-by: Harsh Prateek Bora <harshpb@linux.ibm.com>

> ---
>   hw/ppc/spapr_cpu_core.c | 2 ++
>   1 file changed, 2 insertions(+)
> 
> diff --git a/hw/ppc/spapr_cpu_core.c b/hw/ppc/spapr_cpu_core.c
> index 50523ead25..f3b01b0801 100644
> --- a/hw/ppc/spapr_cpu_core.c
> +++ b/hw/ppc/spapr_cpu_core.c
> @@ -42,6 +42,8 @@ static void spapr_reset_vcpu(PowerPCCPU *cpu)
>        * as 32bit (MSR_SF=0) in "8.2.1. Initial Register Values".
>        */
>       env->msr &= ~(1ULL << MSR_SF);
> +    env->msr |= (1ULL << MSR_ME) | (1ULL << MSR_FP);
> +
>       env->spr[SPR_HIOR] = 0;
>   
>       lpcr = env->spr[SPR_LPCR];

Re: [PATCH 10/13] spapr: set MSR[ME] and MSR[FP] on client entry

Posted by Nicholas Piggin 8 months, 2 weeks ago

On Tue Mar 12, 2024 at 8:03 PM AEST, Harsh Prateek Bora wrote:
>
>
> On 3/12/24 00:21, Nicholas Piggin wrote:
> > The initial MSR state for PAPR specifies MSR[ME] and MSR[FP] are set.
> > 
> > Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
>
> It would be good to mention PAPR section numbers suggesting the same.

I'll see if I can find it and put it in a comment.

Thanks,
Nick

> Anyways,
>
> Reviewed-by: Harsh Prateek Bora <harshpb@linux.ibm.com>
>
> > ---
> >   hw/ppc/spapr_cpu_core.c | 2 ++
> >   1 file changed, 2 insertions(+)
> > 
> > diff --git a/hw/ppc/spapr_cpu_core.c b/hw/ppc/spapr_cpu_core.c
> > index 50523ead25..f3b01b0801 100644
> > --- a/hw/ppc/spapr_cpu_core.c
> > +++ b/hw/ppc/spapr_cpu_core.c
> > @@ -42,6 +42,8 @@ static void spapr_reset_vcpu(PowerPCCPU *cpu)
> >        * as 32bit (MSR_SF=0) in "8.2.1. Initial Register Values".
> >        */
> >       env->msr &= ~(1ULL << MSR_SF);
> > +    env->msr |= (1ULL << MSR_ME) | (1ULL << MSR_FP);
> > +
> >       env->spr[SPR_HIOR] = 0;
> >   
> >       lpcr = env->spr[SPR_LPCR];