[v4] riscv: named features riscv,isa, 'svade' rework

[PATCH v4 0/6] riscv: named features riscv,isa, 'svade' rework

Daniel Henrique Barboza posted 6 patches 8 months, 2 weeks ago

Diff against v1 v2 v3
Download series mbox

Patches applied successfully (tree, apply log)
git fetch https://github.com/patchew-project/qemu tags/patchew/20240215223955.969568-1-dbarboza@ventanamicro.com

Maintainers: Palmer Dabbelt <palmer@dabbelt.com>, Alistair Francis <alistair.francis@wdc.com>, Bin Meng <bin.meng@windriver.com>, Weiwei Li <liwei1518@gmail.com>, Daniel Henrique Barboza <dbarboza@ventanamicro.com>, Liu Zhiwei <zhiwei_liu@linux.alibaba.com>

target/riscv/cpu.c         | 70 +++++++++++++++++++++++++++-----------
target/riscv/cpu_cfg.h     | 12 +++++--
target/riscv/cpu_helper.c  | 19 ++++++++---
target/riscv/csr.c         |  2 +-
target/riscv/tcg/tcg-cpu.c | 34 +++++++++---------
5 files changed, 94 insertions(+), 43 deletions(-)

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[PATCH v4 0/6] riscv: named features riscv,isa, 'svade' rework

Posted by Daniel Henrique Barboza 8 months, 2 weeks ago

Hi,

This new version is rebased with alistair/riscv-to-apply.next and with
more acks added. 

No other changes made.

Changes from v3:
- rebased with alistair/riscv-to-apply.next @ c93c42a273
- v3 link: https://lore.kernel.org/qemu-riscv/20240202152154.773253-1-dbarboza@ventanamicro.com/

Andrew Jones (3):
  target/riscv: Reset henvcfg to zero
  target/riscv: Gate hardware A/D PTE bit updating
  target/riscv: Promote svade to a normal extension

Daniel Henrique Barboza (3):
  target/riscv/tcg: set 'mmu' with 'satp' in cpu_set_profile()
  target/riscv: add riscv,isa to named features
  target/riscv: add remaining named features

 target/riscv/cpu.c         | 70 +++++++++++++++++++++++++++-----------
 target/riscv/cpu_cfg.h     | 12 +++++--
 target/riscv/cpu_helper.c  | 19 ++++++++---
 target/riscv/csr.c         |  2 +-
 target/riscv/tcg/tcg-cpu.c | 34 +++++++++---------
 5 files changed, 94 insertions(+), 43 deletions(-)

-- 
2.43.0

Re: [PATCH v4 0/6] riscv: named features riscv,isa, 'svade' rework

Posted by Alistair Francis 8 months, 2 weeks ago

On Fri, Feb 16, 2024 at 8:41 AM Daniel Henrique Barboza
<dbarboza@ventanamicro.com> wrote:
>
> Hi,
>
> This new version is rebased with alistair/riscv-to-apply.next and with
> more acks added.
>
> No other changes made.
>
> Changes from v3:
> - rebased with alistair/riscv-to-apply.next @ c93c42a273
> - v3 link: https://lore.kernel.org/qemu-riscv/20240202152154.773253-1-dbarboza@ventanamicro.com/
>
> Andrew Jones (3):
>   target/riscv: Reset henvcfg to zero
>   target/riscv: Gate hardware A/D PTE bit updating
>   target/riscv: Promote svade to a normal extension
>
> Daniel Henrique Barboza (3):
>   target/riscv/tcg: set 'mmu' with 'satp' in cpu_set_profile()
>   target/riscv: add riscv,isa to named features
>   target/riscv: add remaining named features

Thanks!

Applied to riscv-to-apply.next

Alistair

>
>  target/riscv/cpu.c         | 70 +++++++++++++++++++++++++++-----------
>  target/riscv/cpu_cfg.h     | 12 +++++--
>  target/riscv/cpu_helper.c  | 19 ++++++++---
>  target/riscv/csr.c         |  2 +-
>  target/riscv/tcg/tcg-cpu.c | 34 +++++++++---------
>  5 files changed, 94 insertions(+), 43 deletions(-)
>
> --
> 2.43.0
>
>