From nobody Fri Nov 1 05:41:17 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1708036875; cv=none; d=zohomail.com; s=zohoarc; b=O2aGzj059QvW/uAUeDWtSrW7KO1k/s7BUSY9X5PsKMl95DuNYalLDYIlre5x45XeCjArE+i2f1m556vOMyxjUB1YBoAxoLW4/okapFIc1XCpnuFLVWYbmgjpc5rhtKOL3S8qbWSW5zNyv/VvP3uDjD+ovietjrvrgA/0uAnt038= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1708036875; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=R2nCob8e/9MrOFcmg40CV49q7uI9/BynfYgCCukIYUA=; b=mYa47aB/ccvIy72UT7w0MllvnGRSr+NwUGCGld3PqU/axxgI+SvR7i3p2bQ4TBwMdFO/czNmtIebUo6vePbem8o0ViYRVHua2THqDH6O/pevDNMBqY+RjMgjpwvooOf76cRQNGU9sUGzhFDgYgT2KDGWQo+X6AmMj5pAaEsfaoc= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1708036875756304.014148046865; Thu, 15 Feb 2024 14:41:15 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1rakPB-0005gp-UG; Thu, 15 Feb 2024 17:40:34 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1rakPB-0005gd-0P for qemu-devel@nongnu.org; Thu, 15 Feb 2024 17:40:33 -0500 Received: from mail-pl1-x633.google.com ([2607:f8b0:4864:20::633]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1rakP9-00065D-A7 for qemu-devel@nongnu.org; Thu, 15 Feb 2024 17:40:32 -0500 Received: by mail-pl1-x633.google.com with SMTP id d9443c01a7336-1d8ef977f1eso12362925ad.0 for ; Thu, 15 Feb 2024 14:40:30 -0800 (PST) Received: from grind.. ([177.94.15.159]) by smtp.gmail.com with ESMTPSA id j2-20020a170902758200b001db40866e25sm1733679pll.308.2024.02.15.14.40.26 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 15 Feb 2024 14:40:28 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1708036829; x=1708641629; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=R2nCob8e/9MrOFcmg40CV49q7uI9/BynfYgCCukIYUA=; b=Kim9+sthSJR06vc3zSoVq98sqmdVg0VVXXsJPeVqoaStr5tuP3Zr2Xdxqq+xgy1EwF LiI5szZEB6aagcLJvfmoW7/dgTWUpg4rWX9d/CtumOd+4AgOde4p6H3NIkjSyIdXhOY9 UBx2DAVD8j7nui+RodocJzBoL4lQHj2B8oVptXxsAm3a05OAb+eqFCYWSZwiVHto1+1A Jlg4g6u/RDTa2nC2+wLBGTRtMCvR1VvMOZhU4e5/xxydC+6DqWZwqSroGZip4aMBxJbZ BrdNZYKDKnj5x8O1ZJP9/rVT6Wuj91i1M4enxEJRmTN0fbCyMGpNGcyuLD4uAAtboCmM pn+g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1708036829; x=1708641629; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=R2nCob8e/9MrOFcmg40CV49q7uI9/BynfYgCCukIYUA=; b=wSgaXbNIPVueLDA3U+ir4sKlwQ3cp+MDO1IbKEmWRnhscHqPo7L7gRj467ZOR+GEpZ JGw73DVX+pvHA0/ovCG23kBeIVeDJtRQ9hWZpcvE44KFSO1nlnZeQ23A6qWQ1hmVkw21 oSHJVstHKVkVDpaEU3Q3ZvoxXjt6MCdVSDJ50cH6QXrTtgEtcPCGg9DokEdmlPskD9sw BIZHh4lkGEBZM37OmpGwse98rb3YgRNamVSLjGhBx4DcHq2LOlDj9bhH18flVHB4wew9 jUiC6dx3oPF8W97RSDls8MaXr5YhXYdrW9UcdIMZr9zsOnwgTg7pbEZ4n+EdM29rv5VW /d9g== X-Gm-Message-State: AOJu0Ywc/bDNJ1UdEi6j6WA3m3kFvexWPQkoafsl9+9MrX6agHjgSD81 Ew1chq6RuwxVjsA1s6BMLgUrlUOt+RCMSeM5QsCLUcEuioPYfuOG3DsG1e4jqvkFZGedKw6zCJk t X-Google-Smtp-Source: AGHT+IEnCYazQ8KlkmqqjJQ3FCbFoiCNy17z4ZTbct4hW7Boeopm8BdXKvTrxdbhWKTClDAhJU4ZHw== X-Received: by 2002:a17:902:7ed0:b0:1d9:a4bb:29f2 with SMTP id p16-20020a1709027ed000b001d9a4bb29f2mr2462100plb.46.1708036829017; Thu, 15 Feb 2024 14:40:29 -0800 (PST) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, bmeng@tinylab.org, liwei1518@gmail.com, zhiwei_liu@linux.alibaba.com, palmer@rivosinc.com, Daniel Henrique Barboza Subject: [PATCH v4 1/6] target/riscv/tcg: set 'mmu' with 'satp' in cpu_set_profile() Date: Thu, 15 Feb 2024 19:39:50 -0300 Message-ID: <20240215223955.969568-2-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240215223955.969568-1-dbarboza@ventanamicro.com> References: <20240215223955.969568-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::633; envelope-from=dbarboza@ventanamicro.com; helo=mail-pl1-x633.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ventanamicro.com) X-ZM-MESSAGEID: 1708036876615100003 Content-Type: text/plain; charset="utf-8" Recent changes in options handling removed the 'mmu' default the bare CPUs had, meaning that we must enable 'mmu' by hand when using the rva22s64 profile CPU. Given that this profile is setting a satp mode, it already implies that we need a 'mmu'. Enable the 'mmu' in this case. Signed-off-by: Daniel Henrique Barboza Reviewed-by: Alistair Francis --- target/riscv/tcg/tcg-cpu.c | 1 + 1 file changed, 1 insertion(+) diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c index dd5228c288..ee4c349972 100644 --- a/target/riscv/tcg/tcg-cpu.c +++ b/target/riscv/tcg/tcg-cpu.c @@ -1075,6 +1075,7 @@ static void cpu_set_profile(Object *obj, Visitor *v, = const char *name, =20 #ifndef CONFIG_USER_ONLY if (profile->satp_mode !=3D RISCV_PROFILE_ATTR_UNUSED) { + object_property_set_bool(obj, "mmu", true, NULL); const char *satp_prop =3D satp_mode_str(profile->satp_mode, riscv_cpu_is_32bit(cpu)); object_property_set_bool(obj, satp_prop, profile->enabled, NULL); --=20 2.43.0 From nobody Fri Nov 1 05:41:17 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1708036891; cv=none; d=zohomail.com; s=zohoarc; b=TBqaK47sLWagwIo9U3a4VS3n+1vypf/TbsjwOxs12EhWFXLK8IX2B5Yaq1pzAUS2WY/PUGXPYFthm06tyBkiUOTzTt+q0sxYuBlDbed5blbOrXxoBUIji0RpPilRw+sR81PYVCgbJO5FNVcCxZU3QUw140S+sOGbBRgT+0XS1KI= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1708036891; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=zLxOAs6WQfZUlgTkvilwCJDAQXlQdmJsupkbv8PC6m0=; b=kwsoQDlbzXCUHX8VDnMENTS240pnHsmY8OFoJpzFx/XtBFVIb2WoeuHefPY6Dr0PcaurfTymgcHnmXW5netIWxO2NWd3lVfeWxH18ATWqjy7RGGmBiFQAHa2Q16uRXk2qKTkN4+itkK3I8i6EWYLKO/d4YqI1YAtsi3aC1ZhZN4= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1708036891554285.63774879135747; Thu, 15 Feb 2024 14:41:31 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1rakPF-0005iH-TS; Thu, 15 Feb 2024 17:40:37 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1rakPE-0005hV-9M for qemu-devel@nongnu.org; Thu, 15 Feb 2024 17:40:36 -0500 Received: from mail-pf1-x429.google.com ([2607:f8b0:4864:20::429]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1rakPC-00068m-C0 for qemu-devel@nongnu.org; Thu, 15 Feb 2024 17:40:36 -0500 Received: by mail-pf1-x429.google.com with SMTP id d2e1a72fcca58-6e1126f57f1so870632b3a.2 for ; Thu, 15 Feb 2024 14:40:34 -0800 (PST) Received: from grind.. ([177.94.15.159]) by smtp.gmail.com with ESMTPSA id j2-20020a170902758200b001db40866e25sm1733679pll.308.2024.02.15.14.40.29 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 15 Feb 2024 14:40:31 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1708036832; x=1708641632; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=zLxOAs6WQfZUlgTkvilwCJDAQXlQdmJsupkbv8PC6m0=; b=dbXefY8+i71QXXOewQtCGNfvPE8WMSIejlxvVQYX2ydTOfEiUeUm0vRRrzyHe8X/Xe AWQjvlWTPiW7VnxiZT47NME7BlAvLirdoQxYu9v5ePfnonWTO0C+/Z85kZRGuHqrZf5O P9n/VkGocO1ySgSVFZCpOU72nqxA2d4F7vE/e4F2rvhMumOZWxR/aWLUroVX/Mdiovbw OwA0DDskUDWN1qig2PaQpjOkIEemydG1wqJC3+uRmDBwcyp2p4Kb9vNLrDLbRRBRrTi/ 8Ys3DLQ3Ib5s/H4VQfrXggZo3eoY7kVf2PHa9tGTscI72kpTjdncKtEe0BenzEBRfeuM QOUg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1708036832; x=1708641632; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=zLxOAs6WQfZUlgTkvilwCJDAQXlQdmJsupkbv8PC6m0=; b=uhgGG6TrAOqAc7F8oAHiL8fWCrNnaE4lY0FjeZ9wVQGSDlhvPXoU+DeCgoStVLXtJq 7euN7E5F/7D5eYjCxIJecykb+PMUlPxO6aidSkjN2FPcBtNDK+HGlwEF4NhYeuYxHUgD CMM/SNt9vY9qUIsOf1SacLPL66ufdDkfnOVDbB6BIoPQ3JOaztQzsgWoL++M6oVJoGso PIEkGMe5NNQeU4PWH0/vhrlluoqJow9h04JuQU6ADOdFnhx3xfJW807+O55EIa5xOBmz dtLeqj6KBrqOqB3fAvm0NCCilHzWOxVbhnwSk3BLUBZq3o9htdjkl909Ba3Y4wmPc7/I qrJA== X-Gm-Message-State: AOJu0YxFShPmhUTIQARQnjZpuOKBMw1tM4mXZGngl8ouusNO7xErQHxY 3kY2gaa2UvXoy8l/GtQtyvOTT9JLxq9KBj+32LCNwfpyFuIJzzSFCXc/l1rQ6dX+12IixH5eB/z O X-Google-Smtp-Source: AGHT+IE7ab5c/gkKDwSMslcc6juE6vWFquZ1klSZzs1JWkHbr5tL0LoK3jD1/KLBFAMqgmeSSc8Reg== X-Received: by 2002:a17:902:e744:b0:1d9:5d56:9f1f with SMTP id p4-20020a170902e74400b001d95d569f1fmr4201739plf.24.1708036832053; Thu, 15 Feb 2024 14:40:32 -0800 (PST) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, bmeng@tinylab.org, liwei1518@gmail.com, zhiwei_liu@linux.alibaba.com, palmer@rivosinc.com, Daniel Henrique Barboza , Andrew Jones Subject: [PATCH v4 2/6] target/riscv: add riscv,isa to named features Date: Thu, 15 Feb 2024 19:39:51 -0300 Message-ID: <20240215223955.969568-3-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240215223955.969568-1-dbarboza@ventanamicro.com> References: <20240215223955.969568-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::429; envelope-from=dbarboza@ventanamicro.com; helo=mail-pf1-x429.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ventanamicro.com) X-ZM-MESSAGEID: 1708036892555100001 Content-Type: text/plain; charset="utf-8" Further discussions after the introduction of rva22 support in QEMU revealed that what we've been calling 'named features' are actually regular extensions, with their respective riscv,isa DTs. This is clarified in [1]. [2] is a bug tracker asking for the profile spec to be less cryptic about it. As far as QEMU goes we understand extensions as something that the user can enable/disable in the command line. This isn't the case for named features, so we'll have to reach a middle ground. We'll keep our existing nomenclature 'named features' to refer to any extension that the user can't control in the command line. We'll also do the following: - 'svade' and 'zic64b' flags are renamed to 'ext_svade' and 'ext_zic64b'. 'ext_svade' and 'ext_zic64b' now have riscv,isa strings and priv_spec versions; - skip name feature check in cpu_bump_multi_ext_priv_ver(). Now that named features have a riscv,isa and an entry in isa_edata_arr[] we don't need to gate the call to cpu_cfg_ext_get_min_version() anymore. [1] https://github.com/riscv/riscv-profiles/issues/121 [2] https://github.com/riscv/riscv-profiles/issues/142 Signed-off-by: Daniel Henrique Barboza Reviewed-by: Andrew Jones Reviewed-by: Alistair Francis --- target/riscv/cpu.c | 17 +++++++++++++---- target/riscv/cpu_cfg.h | 6 ++++-- target/riscv/tcg/tcg-cpu.c | 16 ++++++---------- 3 files changed, 23 insertions(+), 16 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 1b8d001d23..9e66eb61fd 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -98,6 +98,7 @@ bool riscv_cpu_option_set(const char *optname) * instead. */ const RISCVIsaExtData isa_edata_arr[] =3D { + ISA_EXT_DATA_ENTRY(zic64b, PRIV_VERSION_1_12_0, ext_zic64b), ISA_EXT_DATA_ENTRY(zicbom, PRIV_VERSION_1_12_0, ext_zicbom), ISA_EXT_DATA_ENTRY(zicbop, PRIV_VERSION_1_12_0, ext_zicbop), ISA_EXT_DATA_ENTRY(zicboz, PRIV_VERSION_1_12_0, ext_zicboz), @@ -174,6 +175,7 @@ const RISCVIsaExtData isa_edata_arr[] =3D { ISA_EXT_DATA_ENTRY(ssaia, PRIV_VERSION_1_12_0, ext_ssaia), ISA_EXT_DATA_ENTRY(sscofpmf, PRIV_VERSION_1_12_0, ext_sscofpmf), ISA_EXT_DATA_ENTRY(sstc, PRIV_VERSION_1_12_0, ext_sstc), + ISA_EXT_DATA_ENTRY(svade, PRIV_VERSION_1_11_0, ext_svade), ISA_EXT_DATA_ENTRY(svadu, PRIV_VERSION_1_12_0, ext_svadu), ISA_EXT_DATA_ENTRY(svinval, PRIV_VERSION_1_12_0, ext_svinval), ISA_EXT_DATA_ENTRY(svnapot, PRIV_VERSION_1_12_0, ext_svnapot), @@ -1565,9 +1567,16 @@ const RISCVCPUMultiExtConfig riscv_cpu_experimental_= exts[] =3D { DEFINE_PROP_END_OF_LIST(), }; =20 +/* + * 'Named features' is the name we give to extensions that we + * don't want to expose to users. They are either immutable + * (always enabled/disable) or they'll vary depending on + * the resulting CPU state. They have riscv,isa strings + * and priv_ver like regular extensions. + */ const RISCVCPUMultiExtConfig riscv_cpu_named_features[] =3D { - MULTI_EXT_CFG_BOOL("svade", svade, true), - MULTI_EXT_CFG_BOOL("zic64b", zic64b, true), + MULTI_EXT_CFG_BOOL("svade", ext_svade, true), + MULTI_EXT_CFG_BOOL("zic64b", ext_zic64b, true), =20 DEFINE_PROP_END_OF_LIST(), }; @@ -2185,7 +2194,7 @@ static RISCVCPUProfile RVA22U64 =3D { CPU_CFG_OFFSET(ext_zicbop), CPU_CFG_OFFSET(ext_zicboz), =20 /* mandatory named features for this profile */ - CPU_CFG_OFFSET(zic64b), + CPU_CFG_OFFSET(ext_zic64b), =20 RISCV_PROFILE_EXT_LIST_END } @@ -2216,7 +2225,7 @@ static RISCVCPUProfile RVA22S64 =3D { CPU_CFG_OFFSET(ext_svinval), =20 /* rva22s64 named features */ - CPU_CFG_OFFSET(svade), + CPU_CFG_OFFSET(ext_svade), =20 RISCV_PROFILE_EXT_LIST_END } diff --git a/target/riscv/cpu_cfg.h b/target/riscv/cpu_cfg.h index 833bf58217..e68a4ddb92 100644 --- a/target/riscv/cpu_cfg.h +++ b/target/riscv/cpu_cfg.h @@ -119,13 +119,15 @@ struct RISCVCPUConfig { bool ext_smepmp; bool rvv_ta_all_1s; bool rvv_ma_all_1s; - bool svade; - bool zic64b; =20 uint32_t mvendorid; uint64_t marchid; uint64_t mimpid; =20 + /* Named features */ + bool ext_svade; + bool ext_zic64b; + /* Vendor-specific custom extensions */ bool ext_xtheadba; bool ext_xtheadbb; diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c index ee4c349972..2307999387 100644 --- a/target/riscv/tcg/tcg-cpu.c +++ b/target/riscv/tcg/tcg-cpu.c @@ -197,12 +197,12 @@ static bool cpu_cfg_offset_is_named_feat(uint32_t ext= _offset) static void riscv_cpu_enable_named_feat(RISCVCPU *cpu, uint32_t feat_offse= t) { switch (feat_offset) { - case CPU_CFG_OFFSET(zic64b): + case CPU_CFG_OFFSET(ext_zic64b): cpu->cfg.cbom_blocksize =3D 64; cpu->cfg.cbop_blocksize =3D 64; cpu->cfg.cboz_blocksize =3D 64; break; - case CPU_CFG_OFFSET(svade): + case CPU_CFG_OFFSET(ext_svade): cpu->cfg.ext_svadu =3D false; break; default: @@ -219,10 +219,6 @@ static void cpu_bump_multi_ext_priv_ver(CPURISCVState = *env, return; } =20 - if (cpu_cfg_offset_is_named_feat(ext_offset)) { - return; - } - ext_priv_ver =3D cpu_cfg_ext_get_min_version(ext_offset); =20 if (env->priv_ver < ext_priv_ver) { @@ -322,11 +318,11 @@ static void riscv_cpu_disable_priv_spec_isa_exts(RISC= VCPU *cpu) =20 static void riscv_cpu_update_named_features(RISCVCPU *cpu) { - cpu->cfg.zic64b =3D cpu->cfg.cbom_blocksize =3D=3D 64 && - cpu->cfg.cbop_blocksize =3D=3D 64 && - cpu->cfg.cboz_blocksize =3D=3D 64; + cpu->cfg.ext_zic64b =3D cpu->cfg.cbom_blocksize =3D=3D 64 && + cpu->cfg.cbop_blocksize =3D=3D 64 && + cpu->cfg.cboz_blocksize =3D=3D 64; =20 - cpu->cfg.svade =3D !cpu->cfg.ext_svadu; + cpu->cfg.ext_svade =3D !cpu->cfg.ext_svadu; } =20 static void riscv_cpu_validate_g(RISCVCPU *cpu) --=20 2.43.0 From nobody Fri Nov 1 05:41:17 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; 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([177.94.15.159]) by smtp.gmail.com with ESMTPSA id j2-20020a170902758200b001db40866e25sm1733679pll.308.2024.02.15.14.40.32 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 15 Feb 2024 14:40:34 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1708036835; x=1708641635; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=+CsWvOXHpBr1HttAj6uXJd5rnav59pXwvFvHFD69ko4=; b=oN4OeITkuNoXZzF0wCfgv5qGmsS2ewzb92mc2xFjaPebHCtbXBGTOMsHSNUNsIFkLM DfkQca7LGP8zKA57O9zOlf5h8kC6w+VqBJfUKb+uQ7M4bIJNWpCN91AFjjiAXqNhSBXo pK8Qyykz7vl1/17gGVtaY2m4wZZIUUjLJzLJXqmRGB1fzVRG7zpVtZNqz+nWtHSgiWFm B16UmEkza9nQnowkY05Gi4u6stTaoTKx91HOruDmHA+GsM/ewRrIXukr2ir820Mx5VbV +Cyh6F6IJPJ6lSsxTKjTGXLbrwCxRvahZfLHdtNtUd5RMMrhn3aWIYkeN6Qwe/3IlNp6 0nEQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1708036835; x=1708641635; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=+CsWvOXHpBr1HttAj6uXJd5rnav59pXwvFvHFD69ko4=; b=EwWALZKNnWX/yma6/d0aZpQ7A91EmqIvNzHm/raibG4akgc0Ny8fgBrcgV0751/Ye6 se15NggvyP2LqPSKyn11XTXQyivnUiVMixtyjMfToo+8hy8lhNsKyAramwqQAliNrHUB cZCP9l+P+QMiw0cv7ENgFpPkWK41FFtmgnb4zUEupFPGJvfz32mpuWLwNPGXFU8p3uTo b9rej9X2QbDzWg9BYDh+8knGv33iCpiuUTzkStHq8tQn5NZY8ylMZQyD/kMtNAZI/raV W0wXaLSUPcofkb4G4ezgVqtzuvBSabM819sC4Tlrw7aFd7JRoP/9/TwF9sRr/n/YQ8l2 HgoA== X-Gm-Message-State: AOJu0YxFqIG6tNeZhllgDPk6+xdUK3tIS8AntqaOrNReblVhrY8qTyui W2RfKRc/c5McVz3oZEIDcV+HHspL2EnvuYoD3i25LniwMybobXWhTDSfiqKtsOuW3iedhzr6wXV 2 X-Google-Smtp-Source: AGHT+IHez7m/a/eYG0URWGpoKTJYiySOdUc8WJ+eK8KJzwktIFJ7N3anedypP4R11z2PXi9e15bIvw== X-Received: by 2002:a05:6a21:9212:b0:19e:9b8e:8bda with SMTP id tl18-20020a056a21921200b0019e9b8e8bdamr3813873pzb.42.1708036835119; Thu, 15 Feb 2024 14:40:35 -0800 (PST) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, bmeng@tinylab.org, liwei1518@gmail.com, zhiwei_liu@linux.alibaba.com, palmer@rivosinc.com, Daniel Henrique Barboza , Andrew Jones Subject: [PATCH v4 3/6] target/riscv: add remaining named features Date: Thu, 15 Feb 2024 19:39:52 -0300 Message-ID: <20240215223955.969568-4-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240215223955.969568-1-dbarboza@ventanamicro.com> References: <20240215223955.969568-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::432; envelope-from=dbarboza@ventanamicro.com; helo=mail-pf1-x432.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ventanamicro.com) X-ZM-MESSAGEID: 1708036946621100003 Content-Type: text/plain; charset="utf-8" The RVA22U64 and RVA22S64 profiles mandates certain extensions that, until now, we were implying that they were available. We can't do this anymore since named features also has a riscv,isa entry. Let's add them to riscv_cpu_named_features[]. Instead of adding one bool for each named feature that we'll always implement, i.e. can't be turned off, add a 'ext_always_enabled' bool in cpu->cfg. This bool will be set to 'true' in TCG accel init, and all named features will point to it. This also means that KVM won't see these features as always enable, which is our intention. If any accelerator adds support to disable one of these features, we'll have to promote them to regular extensions and allow users to disable it via command line. After this patch, here's the riscv,isa from a buildroot using the 'rva22s64' CPU: # cat /proc/device-tree/cpus/cpu@0/riscv,isa rv64imafdc_zic64b_zicbom_zicbop_zicboz_ziccamoa_ziccif_zicclsm_ziccrse_ zicntr_zicsr_zifencei_zihintpause_zihpm_za64rs_zfhmin_zca_zcd_zba_zbb_ zbs_zkt_ssccptr_sscounterenw_sstvala_sstvecd_svade_svinval_svpbmt# Signed-off-by: Daniel Henrique Barboza Reviewed-by: Alistair Francis Reviewed-by: Andrew Jones --- target/riscv/cpu.c | 42 +++++++++++++++++++++++++++++++------- target/riscv/cpu_cfg.h | 6 ++++++ target/riscv/tcg/tcg-cpu.c | 2 ++ 3 files changed, 43 insertions(+), 7 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 9e66eb61fd..f424751962 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -102,6 +102,10 @@ const RISCVIsaExtData isa_edata_arr[] =3D { ISA_EXT_DATA_ENTRY(zicbom, PRIV_VERSION_1_12_0, ext_zicbom), ISA_EXT_DATA_ENTRY(zicbop, PRIV_VERSION_1_12_0, ext_zicbop), ISA_EXT_DATA_ENTRY(zicboz, PRIV_VERSION_1_12_0, ext_zicboz), + ISA_EXT_DATA_ENTRY(ziccamoa, PRIV_VERSION_1_11_0, ext_always_enabled), + ISA_EXT_DATA_ENTRY(ziccif, PRIV_VERSION_1_11_0, ext_always_enabled), + ISA_EXT_DATA_ENTRY(zicclsm, PRIV_VERSION_1_11_0, ext_always_enabled), + ISA_EXT_DATA_ENTRY(ziccrse, PRIV_VERSION_1_11_0, ext_always_enabled), ISA_EXT_DATA_ENTRY(zicond, PRIV_VERSION_1_12_0, ext_zicond), ISA_EXT_DATA_ENTRY(zicntr, PRIV_VERSION_1_12_0, ext_zicntr), ISA_EXT_DATA_ENTRY(zicsr, PRIV_VERSION_1_10_0, ext_zicsr), @@ -110,6 +114,7 @@ const RISCVIsaExtData isa_edata_arr[] =3D { ISA_EXT_DATA_ENTRY(zihintpause, PRIV_VERSION_1_10_0, ext_zihintpause), ISA_EXT_DATA_ENTRY(zihpm, PRIV_VERSION_1_12_0, ext_zihpm), ISA_EXT_DATA_ENTRY(zmmul, PRIV_VERSION_1_12_0, ext_zmmul), + ISA_EXT_DATA_ENTRY(za64rs, PRIV_VERSION_1_12_0, ext_always_enabled), ISA_EXT_DATA_ENTRY(zaamo, PRIV_VERSION_1_12_0, ext_zaamo), ISA_EXT_DATA_ENTRY(zacas, PRIV_VERSION_1_12_0, ext_zacas), ISA_EXT_DATA_ENTRY(zalrsc, PRIV_VERSION_1_12_0, ext_zalrsc), @@ -173,8 +178,12 @@ const RISCVIsaExtData isa_edata_arr[] =3D { ISA_EXT_DATA_ENTRY(smepmp, PRIV_VERSION_1_12_0, ext_smepmp), ISA_EXT_DATA_ENTRY(smstateen, PRIV_VERSION_1_12_0, ext_smstateen), ISA_EXT_DATA_ENTRY(ssaia, PRIV_VERSION_1_12_0, ext_ssaia), + ISA_EXT_DATA_ENTRY(ssccptr, PRIV_VERSION_1_11_0, ext_always_enabled), ISA_EXT_DATA_ENTRY(sscofpmf, PRIV_VERSION_1_12_0, ext_sscofpmf), + ISA_EXT_DATA_ENTRY(sscounterenw, PRIV_VERSION_1_12_0, ext_always_enabl= ed), ISA_EXT_DATA_ENTRY(sstc, PRIV_VERSION_1_12_0, ext_sstc), + ISA_EXT_DATA_ENTRY(sstvala, PRIV_VERSION_1_12_0, ext_always_enabled), + ISA_EXT_DATA_ENTRY(sstvecd, PRIV_VERSION_1_12_0, ext_always_enabled), ISA_EXT_DATA_ENTRY(svade, PRIV_VERSION_1_11_0, ext_svade), ISA_EXT_DATA_ENTRY(svadu, PRIV_VERSION_1_12_0, ext_svadu), ISA_EXT_DATA_ENTRY(svinval, PRIV_VERSION_1_12_0, ext_svinval), @@ -1567,6 +1576,11 @@ const RISCVCPUMultiExtConfig riscv_cpu_experimental_= exts[] =3D { DEFINE_PROP_END_OF_LIST(), }; =20 +#define ALWAYS_ENABLED_FEATURE(_name) \ + {.name =3D _name, \ + .offset =3D CPU_CFG_OFFSET(ext_always_enabled), \ + .enabled =3D true} + /* * 'Named features' is the name we give to extensions that we * don't want to expose to users. They are either immutable @@ -1578,6 +1592,23 @@ const RISCVCPUMultiExtConfig riscv_cpu_named_feature= s[] =3D { MULTI_EXT_CFG_BOOL("svade", ext_svade, true), MULTI_EXT_CFG_BOOL("zic64b", ext_zic64b, true), =20 + /* + * cache-related extensions that are always enabled + * in TCG since QEMU RISC-V does not have a cache + * model. + */ + ALWAYS_ENABLED_FEATURE("za64rs"), + ALWAYS_ENABLED_FEATURE("ziccif"), + ALWAYS_ENABLED_FEATURE("ziccrse"), + ALWAYS_ENABLED_FEATURE("ziccamoa"), + ALWAYS_ENABLED_FEATURE("zicclsm"), + ALWAYS_ENABLED_FEATURE("ssccptr"), + + /* Other named features that TCG always implements */ + ALWAYS_ENABLED_FEATURE("sstvecd"), + ALWAYS_ENABLED_FEATURE("sstvala"), + ALWAYS_ENABLED_FEATURE("sscounterenw"), + DEFINE_PROP_END_OF_LIST(), }; =20 @@ -2171,13 +2202,10 @@ static const PropertyInfo prop_marchid =3D { }; =20 /* - * RVA22U64 defines some 'named features' or 'synthetic extensions' - * that are cache related: Za64rs, Zic64b, Ziccif, Ziccrse, Ziccamoa - * and Zicclsm. We do not implement caching in QEMU so we'll consider - * all these named features as always enabled. - * - * There's no riscv,isa update for them (nor for zic64b, despite it - * having a cfg offset) at this moment. + * RVA22U64 defines some 'named features' that are cache + * related: Za64rs, Zic64b, Ziccif, Ziccrse, Ziccamoa + * and Zicclsm. They are always implemented in TCG and + * doesn't need to be manually enabled by the profile. */ static RISCVCPUProfile RVA22U64 =3D { .parent =3D NULL, diff --git a/target/riscv/cpu_cfg.h b/target/riscv/cpu_cfg.h index e68a4ddb92..be39870691 100644 --- a/target/riscv/cpu_cfg.h +++ b/target/riscv/cpu_cfg.h @@ -128,6 +128,12 @@ struct RISCVCPUConfig { bool ext_svade; bool ext_zic64b; =20 + /* + * Always 'true' boolean for named features + * TCG always implement/can't be disabled. + */ + bool ext_always_enabled; + /* Vendor-specific custom extensions */ bool ext_xtheadba; bool ext_xtheadbb; diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c index 2307999387..ea763abb31 100644 --- a/target/riscv/tcg/tcg-cpu.c +++ b/target/riscv/tcg/tcg-cpu.c @@ -1315,6 +1315,8 @@ static void riscv_tcg_cpu_instance_init(CPUState *cs) RISCVCPU *cpu =3D RISCV_CPU(cs); Object *obj =3D OBJECT(cpu); =20 + cpu->cfg.ext_always_enabled =3D true; + misa_ext_user_opts =3D g_hash_table_new(NULL, g_direct_equal); multi_ext_user_opts =3D g_hash_table_new(NULL, g_direct_equal); riscv_cpu_add_user_properties(obj); --=20 2.43.0 From nobody Fri Nov 1 05:41:17 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1708036910; cv=none; d=zohomail.com; s=zohoarc; b=T7V9QlnykwoqtqV4rMRt44nM8TrLw0FF9A6gW0hXNqdiMRA6Geze2MsJgHzSSPN2UAUoHHc9HfFNAeMRlI6wMtFJFGmnWvYRfiSoGjCkB2P2Uj4c3P77dD8t5YJNk+DEE1zVCvJjDzRCsiKfzHL+IWoHlcsw6PGYGE4tLoGzSps= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1708036910; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=lTTNcK59UiSXYalt2ktdHl6kS2NT43afEsYVYkGvX6k=; b=HAntcJ0vGXF3AGbcgOtZ8sh14b41YwkWA9vHECem10YNjf+5vlvT7QRC1vysuxOO6c7HxBKJBVxKavK072l0/TKw/tb8SqDTlDgRiKXtsyjqvikT1CaywrJ3CrhxjuwFXZfLCdrSpbXCs85OK9DQUDZMtc7Oy+vWSP+Pvtw4aUg= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1708036910907670.0314830933539; Thu, 15 Feb 2024 14:41:50 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1rakPL-0005kA-41; Thu, 15 Feb 2024 17:40:43 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1rakPJ-0005je-Vg for qemu-devel@nongnu.org; Thu, 15 Feb 2024 17:40:42 -0500 Received: from mail-pl1-x62a.google.com ([2607:f8b0:4864:20::62a]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1rakPI-0006Co-EW for qemu-devel@nongnu.org; Thu, 15 Feb 2024 17:40:41 -0500 Received: by mail-pl1-x62a.google.com with SMTP id d9443c01a7336-1d8ef977f1eso12363775ad.0 for ; Thu, 15 Feb 2024 14:40:40 -0800 (PST) Received: from grind.. ([177.94.15.159]) by smtp.gmail.com with ESMTPSA id j2-20020a170902758200b001db40866e25sm1733679pll.308.2024.02.15.14.40.35 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 15 Feb 2024 14:40:37 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1708036838; x=1708641638; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=lTTNcK59UiSXYalt2ktdHl6kS2NT43afEsYVYkGvX6k=; b=Rk29nn/hg2m2WiO+S1DOschvUmvIXi3Y/oPtfUozkXpzlzF6pK/8kzo++RbsqUi4iR SN8d5VMvCYB4RRXJZrzgfvUi05X/hKAyIyc+1HKoW7259h9C7tpXjwGwks9Oic/QQEuP wQY8rLKR0ZeMabKL8vQPmxS2nDUhLHUP0hmncRG6rnD1+atpYgXL0nvH3NZqCtQJr0hD tUkOeRAsO0OS2Dp8isNwC5luaCIzsSt4ClWlyR6qOHTwxnMHrJifxAWuxXpG/7zJwF8m 4KptHUINlTEuKWUJrLDFZH9kpoc8/Wwx6V2cKvBStQZjUs2O4XWh8rcbi28DOQgUZKoW vIrw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1708036838; x=1708641638; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=lTTNcK59UiSXYalt2ktdHl6kS2NT43afEsYVYkGvX6k=; b=CcA2aKImqpdL1YiNNT92iOmnSEQGgM7mcrpzl/p+Efuc2hJweyWo4LP9jEKKwjChFI JiscMhetYRNpTmBPmiCjRESnOl3i7kd8/Vb6qPe59PSq1LucscBC7U9mvImgSYOBuJXU 6HkX2YrZ5ND5Xd1zboc1v7/dM4NoeKoVoWUh1bnxFc9RcXIzioqJHNQmXPK8So+g20Ox aUuXCpnTqrAv1SXzLKwpegxy8IV0/7+UBk2Q/ckruOWRslcGRRbv7mtLcbjrrFms7YMX T52MQTapkKHzZf3nZQ2ApPERitmZq1KPTMrIYlk6dkODLHQ6p37c5bPTv4RzdI+SxV9O l+cg== X-Gm-Message-State: AOJu0YzSUiNcDNYRJRHDvBmfY1+uBtL2GpA7XPUH9YvlhLmBEgzcKl2J hr2F4xOH3jr/W3QlUCu/CldFD8TE3MOBNJ9HYufJ1adAXvpI04qOrAD7mmql+fZParY/qwzcOrG + X-Google-Smtp-Source: AGHT+IFXEYRKewXhM2hkRWrQtboAGIpmiggQRYIqQJWX1FL7856E0gtqEBWF4t+maF1E9Tn2jdDRLg== X-Received: by 2002:a17:902:650e:b0:1d9:7046:fbcd with SMTP id b14-20020a170902650e00b001d97046fbcdmr2734641plk.3.1708036838141; Thu, 15 Feb 2024 14:40:38 -0800 (PST) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, bmeng@tinylab.org, liwei1518@gmail.com, zhiwei_liu@linux.alibaba.com, palmer@rivosinc.com, Andrew Jones , Daniel Henrique Barboza Subject: [PATCH v4 4/6] target/riscv: Reset henvcfg to zero Date: Thu, 15 Feb 2024 19:39:53 -0300 Message-ID: <20240215223955.969568-5-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240215223955.969568-1-dbarboza@ventanamicro.com> References: <20240215223955.969568-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::62a; envelope-from=dbarboza@ventanamicro.com; helo=mail-pl1-x62a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ventanamicro.com) X-ZM-MESSAGEID: 1708036912474100003 Content-Type: text/plain; charset="utf-8" From: Andrew Jones The hypervisor should decide what it wants to enable. Zero all configuration enable bits on reset. Also, commit ed67d63798f2 ("target/riscv: Update CSR bits name for svadu extension") missed one reference to 'hade'. Change it now. Fixes: 0af3f115e68e ("target/riscv: Add *envcfg.HADE related check in addre= ss translation") Fixes: ed67d63798f2 ("target/riscv: Update CSR bits name for svadu extensio= n") Reviewed-by: Daniel Henrique Barboza Signed-off-by: Andrew Jones Reviewed-by: Alistair Francis --- target/riscv/cpu.c | 3 +-- target/riscv/csr.c | 2 +- 2 files changed, 2 insertions(+), 3 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index f424751962..e5eef3a4de 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -961,8 +961,7 @@ static void riscv_cpu_reset_hold(Object *obj) =20 env->menvcfg =3D (cpu->cfg.ext_svpbmt ? MENVCFG_PBMTE : 0) | (cpu->cfg.ext_svadu ? MENVCFG_ADUE : 0); - env->henvcfg =3D (cpu->cfg.ext_svpbmt ? HENVCFG_PBMTE : 0) | - (cpu->cfg.ext_svadu ? HENVCFG_ADUE : 0); + env->henvcfg =3D 0; =20 /* Initialized default priorities of local interrupts. */ for (i =3D 0; i < ARRAY_SIZE(env->miprio); i++) { diff --git a/target/riscv/csr.c b/target/riscv/csr.c index d4e8ac13b9..cc9cef3d85 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -2133,7 +2133,7 @@ static RISCVException read_henvcfg(CPURISCVState *env= , int csrno, /* * henvcfg.pbmte is read_only 0 when menvcfg.pbmte =3D 0 * henvcfg.stce is read_only 0 when menvcfg.stce =3D 0 - * henvcfg.hade is read_only 0 when menvcfg.hade =3D 0 + * henvcfg.adue is read_only 0 when menvcfg.adue =3D 0 */ *val =3D env->henvcfg & (~(HENVCFG_PBMTE | HENVCFG_STCE | HENVCFG_ADUE= ) | env->menvcfg); --=20 2.43.0 From nobody Fri Nov 1 05:41:17 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1708036951; cv=none; d=zohomail.com; s=zohoarc; b=UMnTwKIzI+hubSy8235AdCb+a+4enfOybFNEG5K6E+DrbGBD6mkXBHwwZ2V8IP11+80jDbyxPlgd6TK76LbGLrHFJAD6505xyc/hl+29c9653YdxJZhW4eEMWTaFCTlIMlr9xq5WJ0pnNbqYWarohB5AySZzK2jC/YXCZBlnjY4= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1708036951; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=G0c/7JvgnDh+15xoKUqd6xGLTzj/38aC5iwcl74lVSY=; b=EDSU3yqaWmoSYMZip+GlfVw7HUs1ODJ6ORKa+EImEzXCRL1QeQXjs/gILKCWXv7/8EORZbVn2z+5FHmEml466Cc0KAbzfbC7hPLp02OMP0icrwFTSjV0X7i4oonbUy7cPkVAn8k/ukKsQXa819nbDPMTqeH3CLgf1qq/qUPIXVM= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 17080369516471018.0891060786287; Thu, 15 Feb 2024 14:42:31 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1rakPR-0005m8-Rq; Thu, 15 Feb 2024 17:40:49 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1rakPP-0005kr-Gg for qemu-devel@nongnu.org; Thu, 15 Feb 2024 17:40:47 -0500 Received: from mail-pl1-x62b.google.com ([2607:f8b0:4864:20::62b]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1rakPL-0006DQ-3B for qemu-devel@nongnu.org; Thu, 15 Feb 2024 17:40:44 -0500 Received: by mail-pl1-x62b.google.com with SMTP id d9443c01a7336-1d918008b99so11622415ad.3 for ; Thu, 15 Feb 2024 14:40:42 -0800 (PST) Received: from grind.. ([177.94.15.159]) by smtp.gmail.com with ESMTPSA id j2-20020a170902758200b001db40866e25sm1733679pll.308.2024.02.15.14.40.38 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 15 Feb 2024 14:40:40 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1708036841; x=1708641641; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=G0c/7JvgnDh+15xoKUqd6xGLTzj/38aC5iwcl74lVSY=; b=WpMjCDOrcLIda4bGJv0PgQKeiaBiI3szqrleOIusYMCc1RXgOSrsOWmjYd+it2wPdX HeHmJ+Vtu1c7UpvZux04Ux373/KQkl+WjSCfyxvwSjFmSQmxAJ0C3jzZv/l9MjVLDmYF IUU7dcltxvAOGmur72oBzYf2ZFDfTqnarGU2P+Y2wvjswdCA4K1KcazhJU9hsue3x48y Vx64NkRSiUJjYRkIwuTGVqfx3gybCs20tCSlC11CbHzlwRpSAfuzGoaRMDEWoS8rdows bM6ZuwLVV4FihxInYFI35X2Zi6OupRauu9GYGPy/ZqBx9bAf9m3P81yslH5UtMtmgL40 6aog== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1708036841; x=1708641641; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=G0c/7JvgnDh+15xoKUqd6xGLTzj/38aC5iwcl74lVSY=; b=IWN7fuMmdy+4mpExKu/XvLmlcQD5Crb5gmHkHSELpb7HiWo2INavKVQAnBY16/3SuU KIrC3q5Xj9wEtmegMorXmKbOHhUqZd5baa8VSd6OFdR2Z1nvbMDYqwSfxmv96j2ZkgzP 4DNhONHze5/1AheKi4ghxu2+gL6rXH/R2aOcez2Jjn8j9cEcHN7+1TlIRCo0jiTQhHHQ cpxMKUYSp2cCgi510YMkrPBU0cKl0LN+5qyAEmdhwxRo6aNThYhbdNuIE0d7wM+tNEtX HxBgz3Bzjt9bDHXYx+2L/kL1sCohoNeA6aZVM+pk0C2OS0DUg/reuFpTudP2S4G5D8Ov w39Q== X-Gm-Message-State: AOJu0Yxq+k9BVgwlGZRRXz/twV7UYP8owLxGeG7MzCzqDOK9F7GUqzRW gKkmiuQaDIQrEz/PCoOzzDUqHrfXXewjJ5uUibWWbE92aafF565ajUtvR7YDmkF5ZND3EdAzNAR e X-Google-Smtp-Source: AGHT+IEgdOK7sxcd7a82zb18BWAXaQ3yBgh1EMV4FKhvng+9MMBPFPqrfO4rgo+gYnHl+ks3z5zWFg== X-Received: by 2002:a17:902:650e:b0:1d9:7046:fbcd with SMTP id b14-20020a170902650e00b001d97046fbcdmr2734717plk.3.1708036841161; Thu, 15 Feb 2024 14:40:41 -0800 (PST) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, bmeng@tinylab.org, liwei1518@gmail.com, zhiwei_liu@linux.alibaba.com, palmer@rivosinc.com, Andrew Jones , Daniel Henrique Barboza Subject: [PATCH v4 5/6] target/riscv: Gate hardware A/D PTE bit updating Date: Thu, 15 Feb 2024 19:39:54 -0300 Message-ID: <20240215223955.969568-6-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240215223955.969568-1-dbarboza@ventanamicro.com> References: <20240215223955.969568-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::62b; envelope-from=dbarboza@ventanamicro.com; helo=mail-pl1-x62b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ventanamicro.com) X-ZM-MESSAGEID: 1708036952860100001 Content-Type: text/plain; charset="utf-8" From: Andrew Jones Gate hardware A/D PTE bit updating on {m,h}envcfg.ADUE and only enable menvcfg.ADUE on reset if svade has not been selected. Now that we also consider svade, we have four possible configurations: 1) !svade && !svadu use hardware updating and there's no way to disable it (the default, which maintains past behavior. Maintaining the default, even with !svadu is a change that fixes [1]) 2) !svade && svadu use hardware updating, but also provide {m,h}envcfg.ADUE, allowing software to switch to exception mode (being able to switch is a change which fixes [1]) 3) svade && !svadu use exception mode and there's no way to switch to hardware updating (this behavior change fixes [2]) 4) svade && svadu use exception mode, but also provide {m,h}envcfg.ADUE, allowing software to switch to hardware updating (this behavior change fixes [2]) Fixes: 0af3f115e68e ("target/riscv: Add *envcfg.HADE related check in addre= ss translation") [1] Fixes: 48531f5adb2a ("target/riscv: implement svade") [2] Reviewed-by: Daniel Henrique Barboza Signed-off-by: Andrew Jones Reviewed-by: Alistair Francis --- target/riscv/cpu.c | 3 ++- target/riscv/cpu_helper.c | 19 +++++++++++++++---- target/riscv/tcg/tcg-cpu.c | 15 +++++---------- 3 files changed, 22 insertions(+), 15 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index e5eef3a4de..7598daa162 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -960,7 +960,8 @@ static void riscv_cpu_reset_hold(Object *obj) env->two_stage_lookup =3D false; =20 env->menvcfg =3D (cpu->cfg.ext_svpbmt ? MENVCFG_PBMTE : 0) | - (cpu->cfg.ext_svadu ? MENVCFG_ADUE : 0); + (!cpu->cfg.ext_svade && cpu->cfg.ext_svadu ? + MENVCFG_ADUE : 0); env->henvcfg =3D 0; =20 /* Initialized default priorities of local interrupts. */ diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index d462d95ee1..c994a72634 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -907,7 +907,9 @@ static int get_physical_address(CPURISCVState *env, hwa= ddr *physical, } =20 bool pbmte =3D env->menvcfg & MENVCFG_PBMTE; - bool adue =3D env->menvcfg & MENVCFG_ADUE; + bool svade =3D riscv_cpu_cfg(env)->ext_svade; + bool svadu =3D riscv_cpu_cfg(env)->ext_svadu; + bool adue =3D svadu ? env->menvcfg & MENVCFG_ADUE : !svade; =20 if (first_stage && two_stage && env->virt_enabled) { pbmte =3D pbmte && (env->henvcfg & HENVCFG_PBMTE); @@ -1082,9 +1084,18 @@ restart: return TRANSLATE_FAIL; } =20 - /* If necessary, set accessed and dirty bits. */ - target_ulong updated_pte =3D pte | PTE_A | - (access_type =3D=3D MMU_DATA_STORE ? PTE_D : 0); + target_ulong updated_pte =3D pte; + + /* + * If ADUE is enabled, set accessed and dirty bits. + * Otherwise raise an exception if necessary. + */ + if (adue) { + updated_pte |=3D PTE_A | (access_type =3D=3D MMU_DATA_STORE ? PTE_= D : 0); + } else if (!(pte & PTE_A) || + (access_type =3D=3D MMU_DATA_STORE && !(pte & PTE_D))) { + return TRANSLATE_FAIL; + } =20 /* Page table updates need to be atomic with MTTCG enabled */ if (updated_pte !=3D pte && !is_debug) { diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c index ea763abb31..ccfb7b2dd3 100644 --- a/target/riscv/tcg/tcg-cpu.c +++ b/target/riscv/tcg/tcg-cpu.c @@ -196,17 +196,14 @@ static bool cpu_cfg_offset_is_named_feat(uint32_t ext= _offset) =20 static void riscv_cpu_enable_named_feat(RISCVCPU *cpu, uint32_t feat_offse= t) { - switch (feat_offset) { - case CPU_CFG_OFFSET(ext_zic64b): + /* + * All other named features are already enabled + * in riscv_tcg_cpu_instance_init(). + */ + if (feat_offset =3D=3D CPU_CFG_OFFSET(ext_zic64b)) { cpu->cfg.cbom_blocksize =3D 64; cpu->cfg.cbop_blocksize =3D 64; cpu->cfg.cboz_blocksize =3D 64; - break; - case CPU_CFG_OFFSET(ext_svade): - cpu->cfg.ext_svadu =3D false; - break; - default: - g_assert_not_reached(); } } =20 @@ -321,8 +318,6 @@ static void riscv_cpu_update_named_features(RISCVCPU *c= pu) cpu->cfg.ext_zic64b =3D cpu->cfg.cbom_blocksize =3D=3D 64 && cpu->cfg.cbop_blocksize =3D=3D 64 && cpu->cfg.cboz_blocksize =3D=3D 64; - - cpu->cfg.ext_svade =3D !cpu->cfg.ext_svadu; } =20 static void riscv_cpu_validate_g(RISCVCPU *cpu) --=20 2.43.0 From nobody Fri Nov 1 05:41:17 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1708036935; cv=none; d=zohomail.com; s=zohoarc; b=QZbcYoxUxEzqHCb+1MO/WxSv2g8LQFzfkqh283FUUigC6VEhqWgSQdoc9Xa16eEUR1VOQYHk1UlovegV2bs4L6H5vTWPTJJ4ygX5m+5GMg99sXNvZP6F+2FzbQ7FIXeL8KcZxxj6n7CGvkaEEwQ2VXsDQ8q9xoFqrv+QdZrKxK4= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1708036935; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=37fZ+kvSrgmRxrOauqN5Kq+ehbdNsQUKhRww2rKUEUs=; b=PzZ4fAM5KALIMcf6ITmCG1iBxfwmmIJLLodTv8Uh8XwSasWgViAoOc5CV05xfEWHbNeXHuOStYGXLdGlVsiMYKR25OC2AmTH26GK0AAIpe7I4s/z64iZXQaLLrVaXF8oPY0x57s1QB4sOpBY7vvhbPbGZXhaVIyNmSkpHKaxg+g= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1708036935142134.66033756401941; Thu, 15 Feb 2024 14:42:15 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1rakPU-0005mb-2P; Thu, 15 Feb 2024 17:40:52 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1rakPR-0005lr-K6 for qemu-devel@nongnu.org; Thu, 15 Feb 2024 17:40:49 -0500 Received: from mail-il1-x12e.google.com ([2607:f8b0:4864:20::12e]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1rakPP-0006Dz-N8 for qemu-devel@nongnu.org; Thu, 15 Feb 2024 17:40:49 -0500 Received: by mail-il1-x12e.google.com with SMTP id e9e14a558f8ab-364efe11f6aso7218525ab.1 for ; Thu, 15 Feb 2024 14:40:46 -0800 (PST) Received: from grind.. ([177.94.15.159]) by smtp.gmail.com with ESMTPSA id j2-20020a170902758200b001db40866e25sm1733679pll.308.2024.02.15.14.40.41 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 15 Feb 2024 14:40:44 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1708036845; x=1708641645; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=37fZ+kvSrgmRxrOauqN5Kq+ehbdNsQUKhRww2rKUEUs=; b=n+IdDF6Z39Fgup4nNU9ww+62L3PL8j4AGF3Mge6rSLTvB9Oq5gw4caQvJSSTBImDkA Y4Bbaot0kT/ZNJSyquwqqT3Avh+yQlt6fILU7mwnJNzXHpDM5zQGJqkJv5OSBbRmz5yD ZBJk7eqcn4MdMdJHJxU2uykNMYk5xEzg9nukSRSYdbCDvWX3neiGvVghOXoshSsJH5GR zsShQ4lzXa0OEskgbQRaeEFdVyROEMwYAa+mnc1WDCFb9DDPDv0ZuBrDe0r7Qoa1P1zP hxgtOhRFNXrCYMh0a0PhnhVf86ohpowNC6Wxb+tPK8FtKHH56taYRcyh4wZWtODkLCnZ MQIg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1708036845; x=1708641645; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=37fZ+kvSrgmRxrOauqN5Kq+ehbdNsQUKhRww2rKUEUs=; b=hI265HjcgEYjE1KLRMpkxyJeRCg/PkentjjyTsFFRIIUJQtYUnRKbCWIKfcB3v2Jzg H6l6MxDIZFpgildGP93bJXYdBrm0NpPQgeWv7YWXWqVQBFlUHlijLAWrRvo+9pJ9FfrG abIWdARFIfu8MbOxVwLxzkyF3egSYT6UabB4IdYzOhucz30+wLorXv5FpjMTWdzUBg3u +SbHB0pvmBGCUupa8JGM2qIpTK/PS2FmEs04v32RxLxnEKyXU4XFu6edyDqAsG68z7sw 1wjSJuAZbg+dnZPC9ekNsKZXBy/2pITksElzBzd10CCZmKU5t8VFUhKy0OUr1qk7hzzV /7Yw== X-Gm-Message-State: AOJu0YyItpU69cX027lg7O/y/mKqWG/HRKY1llmCn34Ir9D0dWdueYJq FJlhfrzwL47LQG36aCH/DfOTcw9tIvSNSomb6OiqdZr5QXcdd4UmCM7GKO7SQwx8TeBuOUW/wg3 I X-Google-Smtp-Source: AGHT+IGD65iL4k1paZbPg2f7bi3JnC/azY7+Pr4To4vjojjsf39wf4dEYMizyQ8nOfwEfbD6c0W0WQ== X-Received: by 2002:a92:c901:0:b0:363:dfc7:acc2 with SMTP id t1-20020a92c901000000b00363dfc7acc2mr3585472ilp.12.1708036845103; Thu, 15 Feb 2024 14:40:45 -0800 (PST) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, bmeng@tinylab.org, liwei1518@gmail.com, zhiwei_liu@linux.alibaba.com, palmer@rivosinc.com, Andrew Jones , Daniel Henrique Barboza Subject: [PATCH v4 6/6] target/riscv: Promote svade to a normal extension Date: Thu, 15 Feb 2024 19:39:55 -0300 Message-ID: <20240215223955.969568-7-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240215223955.969568-1-dbarboza@ventanamicro.com> References: <20240215223955.969568-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::12e; envelope-from=dbarboza@ventanamicro.com; helo=mail-il1-x12e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ventanamicro.com) X-ZM-MESSAGEID: 1708036936580100003 Content-Type: text/plain; charset="utf-8" From: Andrew Jones Named features are extensions which don't make sense for users to control and are therefore not exposed on the command line. However, svade is an extension which makes sense for users to control, so treat it like a "normal" extension. The default is false, even for the max cpu type, since QEMU has always implemented hardware A/D PTE bit updating, so users must opt into svade (or get it from a CPU type which enables it by default). Reviewed-by: Daniel Henrique Barboza Signed-off-by: Andrew Jones Reviewed-by: Alistair Francis --- target/riscv/cpu.c | 9 ++------- target/riscv/tcg/tcg-cpu.c | 6 ++++++ 2 files changed, 8 insertions(+), 7 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 7598daa162..fd0c7efdda 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -1474,6 +1474,7 @@ const RISCVCPUMultiExtConfig riscv_cpu_extensions[] = =3D { =20 MULTI_EXT_CFG_BOOL("smepmp", ext_smepmp, false), MULTI_EXT_CFG_BOOL("smstateen", ext_smstateen, false), + MULTI_EXT_CFG_BOOL("svade", ext_svade, false), MULTI_EXT_CFG_BOOL("svadu", ext_svadu, true), MULTI_EXT_CFG_BOOL("svinval", ext_svinval, false), MULTI_EXT_CFG_BOOL("svnapot", ext_svnapot, false), @@ -1589,7 +1590,6 @@ const RISCVCPUMultiExtConfig riscv_cpu_experimental_e= xts[] =3D { * and priv_ver like regular extensions. */ const RISCVCPUMultiExtConfig riscv_cpu_named_features[] =3D { - MULTI_EXT_CFG_BOOL("svade", ext_svade, true), MULTI_EXT_CFG_BOOL("zic64b", ext_zic64b, true), =20 /* @@ -2237,8 +2237,6 @@ static RISCVCPUProfile RVA22U64 =3D { * Other named features that we already implement: Sstvecd, Sstvala, * Sscounterenw * - * Named features that we need to enable: svade - * * The remaining features/extensions comes from RVA22U64. */ static RISCVCPUProfile RVA22S64 =3D { @@ -2250,10 +2248,7 @@ static RISCVCPUProfile RVA22S64 =3D { .ext_offsets =3D { /* rva22s64 exts */ CPU_CFG_OFFSET(ext_zifencei), CPU_CFG_OFFSET(ext_svpbmt), - CPU_CFG_OFFSET(ext_svinval), - - /* rva22s64 named features */ - CPU_CFG_OFFSET(ext_svade), + CPU_CFG_OFFSET(ext_svinval), CPU_CFG_OFFSET(ext_svade), =20 RISCV_PROFILE_EXT_LIST_END } diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c index ccfb7b2dd3..ab6db817db 100644 --- a/target/riscv/tcg/tcg-cpu.c +++ b/target/riscv/tcg/tcg-cpu.c @@ -1282,6 +1282,12 @@ static void riscv_init_max_cpu_extensions(Object *ob= j) isa_ext_update_enabled(cpu, prop->offset, true); } =20 + /* + * Some extensions can't be added without backward compatibilty concer= ns. + * Disable those, the user can still opt in to them on the command lin= e. + */ + cpu->cfg.ext_svade =3D false; + /* set vector version */ env->vext_ver =3D VEXT_VERSION_1_00_0; =20 --=20 2.43.0