From: Akihiko Odaki <akihiko.odaki@daynix.com>
misa_mxl_max is now a class member and initialized only once for each
class. This also moves the initialization of gdb_core_xml_file which
will be referenced before realization in the future.
Signed-off-by: Akihiko Odaki <akihiko.odaki@daynix.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20240203-riscv-v11-3-a23f4848a628@daynix.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/cpu.c | 21 +++++++++++++++++++++
target/riscv/tcg/tcg-cpu.c | 23 -----------------------
2 files changed, 21 insertions(+), 23 deletions(-)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 0e6762badd..be3ec5a25d 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -1349,6 +1349,26 @@ static const MISAExtInfo misa_ext_info_arr[] = {
MISA_EXT_INFO(RVB, "x-b", "Bit manipulation (Zba_Zbb_Zbs)")
};
+static void riscv_cpu_validate_misa_mxl(RISCVCPUClass *mcc)
+{
+ CPUClass *cc = CPU_CLASS(mcc);
+
+ /* Validate that MISA_MXL is set properly. */
+ switch (mcc->misa_mxl_max) {
+#ifdef TARGET_RISCV64
+ case MXL_RV64:
+ case MXL_RV128:
+ cc->gdb_core_xml_file = "riscv-64bit-cpu.xml";
+ break;
+#endif
+ case MXL_RV32:
+ cc->gdb_core_xml_file = "riscv-32bit-cpu.xml";
+ break;
+ default:
+ g_assert_not_reached();
+ }
+}
+
static int riscv_validate_misa_info_idx(uint32_t bit)
{
int idx;
@@ -2309,6 +2329,7 @@ static void riscv_cpu_class_init(ObjectClass *c, void *data)
RISCVCPUClass *mcc = RISCV_CPU_CLASS(c);
mcc->misa_mxl_max = (uint32_t)(uintptr_t)data;
+ riscv_cpu_validate_misa_mxl(mcc);
}
static void riscv_isa_string_ext(RISCVCPU *cpu, char **isa_str,
diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c
index d7639d8670..dd5228c288 100644
--- a/target/riscv/tcg/tcg-cpu.c
+++ b/target/riscv/tcg/tcg-cpu.c
@@ -268,27 +268,6 @@ static void riscv_cpu_validate_misa_priv(CPURISCVState *env, Error **errp)
}
}
-static void riscv_cpu_validate_misa_mxl(RISCVCPU *cpu)
-{
- RISCVCPUClass *mcc = RISCV_CPU_GET_CLASS(cpu);
- CPUClass *cc = CPU_CLASS(mcc);
-
- /* Validate that MISA_MXL is set properly. */
- switch (mcc->misa_mxl_max) {
-#ifdef TARGET_RISCV64
- case MXL_RV64:
- case MXL_RV128:
- cc->gdb_core_xml_file = "riscv-64bit-cpu.xml";
- break;
-#endif
- case MXL_RV32:
- cc->gdb_core_xml_file = "riscv-32bit-cpu.xml";
- break;
- default:
- g_assert_not_reached();
- }
-}
-
static void riscv_cpu_validate_v(CPURISCVState *env, RISCVCPUConfig *cfg,
Error **errp)
{
@@ -911,8 +890,6 @@ static bool riscv_tcg_cpu_realize(CPUState *cs, Error **errp)
return false;
}
- riscv_cpu_validate_misa_mxl(cpu);
-
#ifndef CONFIG_USER_ONLY
CPURISCVState *env = &cpu->env;
Error *local_err = NULL;
--
2.43.0