[PULL 00/61] riscv-to-apply queue

Alistair Francis posted 61 patches 2 weeks, 1 day ago
Failed in applying to current master (apply log)
Maintainers: Paolo Bonzini <pbonzini@redhat.com>, Palmer Dabbelt <palmer@dabbelt.com>, Alistair Francis <alistair.francis@wdc.com>, Bin Meng <bin.meng@windriver.com>, Weiwei Li <liwei1518@gmail.com>, Daniel Henrique Barboza <dbarboza@ventanamicro.com>, Liu Zhiwei <zhiwei_liu@linux.alibaba.com>, Sunil V L <sunilvl@ventanamicro.com>, "Michael S. Tsirkin" <mst@redhat.com>, Igor Mammedov <imammedo@redhat.com>, Ani Sinha <anisinha@redhat.com>, Christoph Muellner <christoph.muellner@vrull.eu>
There is a newer version of this series
include/hw/firmware/smbios.h               |    1 +
target/riscv/cpu-qom.h                     |    3 +
target/riscv/cpu.h                         |   30 +-
target/riscv/cpu_bits.h                    |   15 +-
target/riscv/cpu_cfg.h                     |    8 +-
target/riscv/kvm/kvm_riscv.h               |    1 +
hw/riscv/boot.c                            |    3 +-
hw/riscv/numa.c                            |    4 +-
hw/riscv/sifive_u.c                        |    7 +-
hw/riscv/spike.c                           |    6 +-
hw/riscv/virt-acpi-build.c                 |    2 +-
hw/riscv/virt.c                            |  153 ++--
hw/smbios/smbios.c                         |   20 +-
target/riscv/cpu.c                         | 1106 +++++++++++++++++++++-------
target/riscv/cpu_helper.c                  |   11 +-
target/riscv/csr.c                         |  157 ++--
target/riscv/debug.c                       |    2 +
target/riscv/gdbstub.c                     |   18 +-
target/riscv/kvm/kvm-cpu.c                 |  250 +++++--
target/riscv/machine.c                     |    7 +-
target/riscv/tcg/tcg-cpu.c                 |  143 ++--
target/riscv/translate.c                   |    3 +-
target/riscv/vector_helper.c               |   43 +-
target/riscv/insn_trans/trans_rva.c.inc    |   45 +-
target/riscv/insn_trans/trans_rvbf16.c.inc |   12 +-
target/riscv/insn_trans/trans_rvv.c.inc    |  152 ++--
target/riscv/insn_trans/trans_rvvk.c.inc   |   16 +-
target/riscv/insn_trans/trans_xthead.c.inc |   10 -
hw/riscv/Kconfig                           |    1 +
qemu-options.hx                            |    6 +-
30 files changed, 1522 insertions(+), 713 deletions(-)
[PULL 00/61] riscv-to-apply queue
Posted by Alistair Francis 2 weeks, 1 day ago
The following changes since commit 03e4bc0bc02779fdf6f8e8d83197f05e70881abf:

  Merge tag 'pull-tcg-20240205-2' of https://gitlab.com/rth7680/qemu into staging (2024-02-08 16:08:42 +0000)

are available in the Git repository at:

  https://github.com/alistair23/qemu.git tags/pull-riscv-to-apply-20240209

for you to fetch changes up to deb0ff0c777d20602ecc5b6f74f18cb7ecc0b91f:

  target/riscv: add rv32i, rv32e and rv64e CPUs (2024-02-09 20:49:41 +1000)

----------------------------------------------------------------
RISC-V PR for 9.0

* Check for 'A' extension on all atomic instructions
* Add support for 'B' extension
* Internally deprecate riscv_cpu_options
* Implement optional CSR mcontext of debug Sdtrig extension
* Internally add cpu->cfg.vlenb and  remove cpu->cfg.vlen
* Support vlenb and vregs[] in KVM
* RISC-V gdbstub and TCG plugin improvements
* Remove vxrm and vxsat from FCSR
* Use RISCVException as return type for all csr ops
* Use g_autofree more and fix a memory leak
* Add support for Zaamo and Zalrsc
* Support new isa extension detection devicetree properties
* SMBIOS support for RISC-V virt machine
* Enable xtheadsync under user mode
* Add rv32i,rv32e and rv64e CPUs

----------------------------------------------------------------
Akihiko Odaki (3):
      target/riscv: Remove misa_mxl validation
      target/riscv: Move misa_mxl_max to class
      target/riscv: Validate misa_mxl_max only once

Alvin Chang (1):
      target/riscv: Implement optional CSR mcontext of debug Sdtrig extension

Conor Dooley (2):
      target/riscv: use misa_mxl_max to populate isa string rather than TARGET_LONG_BITS
      target/riscv: support new isa extension detection devicetree properties

Daniel Henrique Barboza (42):
      target/riscv/cpu_cfg.h: remove unused fields
      target/riscv: make riscv_cpu_is_vendor() public
      target/riscv: move 'pmu-mask' and 'pmu-num' to riscv_cpu_properties[]
      target/riscv: move 'mmu' to riscv_cpu_properties[]
      target/riscv: move 'pmp' to riscv_cpu_properties[]
      target/riscv: rework 'priv_spec'
      target/riscv: rework 'vext_spec'
      target/riscv: move 'vlen' to riscv_cpu_properties[]
      target/riscv: move 'elen' to riscv_cpu_properties[]
      target/riscv: create finalize_features() for KVM
      target/riscv: move 'cbom_blocksize' to riscv_cpu_properties[]
      target/riscv: move 'cbop_blocksize' to riscv_cpu_properties[]
      target/riscv: move 'cboz_blocksize' to riscv_cpu_properties[]
      target/riscv: remove riscv_cpu_options[]
      target/riscv/cpu.c: move 'mvendorid' to riscv_cpu_properties[]
      target/riscv/cpu.c: move 'mimpid' to riscv_cpu_properties[]
      target/riscv/cpu.c: move 'marchid' to riscv_cpu_properties[]
      target/riscv: add 'vlenb' field in cpu->cfg
      target/riscv/csr.c: use 'vlenb' instead of 'vlen'
      target/riscv/gdbstub.c: use 'vlenb' instead of shifting 'vlen'
      target/riscv/insn_trans/trans_rvbf16.c.inc: use cpu->cfg.vlenb
      target/riscv/insn_trans/trans_rvv.c.inc: use 'vlenb'
      target/riscv/insn_trans/trans_rvvk.c.inc: use 'vlenb'
      target/riscv/vector_helper.c: use 'vlenb'
      target/riscv/vector_helper.c: use vlenb in HELPER(vsetvl)
      target/riscv/insn_trans/trans_rvv.c.inc: use 'vlenb' in MAXSZ()
      target/riscv/cpu.h: use 'vlenb' in vext_get_vlmax()
      target/riscv: change vext_get_vlmax() arguments
      trans_rvv.c.inc: use vext_get_vlmax() in trans_vrgather_v*()
      target/riscv/cpu.c: remove cpu->cfg.vlen
      target/riscv/kvm: change kvm_reg_id to uint64_t
      target/riscv/kvm: initialize 'vlenb' via get-reg-list
      target/riscv/kvm: get/set vector vregs[]
      hw/riscv/virt-acpi-build.c: fix leak in build_rhct()
      hw/riscv/numa.c: use g_autofree in socket_fdt_write_distance_matrix()
      hw/riscv/virt.c: use g_autofree in create_fdt_socket_cpus()
      hw/riscv/virt.c: use g_autofree in create_fdt_sockets()
      hw/riscv/virt.c: use g_autofree in create_fdt_virtio()
      hw/riscv/virt.c: use g_autofree in virt_machine_init()
      hw/riscv/virt.c: use g_autofree in create_fdt_*
      target/riscv/cpu.c: add riscv_bare_cpu_init()
      target/riscv: add rv32i, rv32e and rv64e CPUs

Heinrich Schuchardt (4):
      smbios: add processor-family option
      smbios: function to set default processor family
      target/riscv: SMBIOS support for RISC-V virt machine
      qemu-options: enable -smbios option on RISC-V

LIU Zhiwei (3):
      target/riscv: FCSR doesn't contain vxrm and vxsat
      target/riscv: Use RISCVException as return type for all csr ops
      target/riscv: Enable xtheadsync under user mode

Rob Bradford (6):
      target/riscv: Check for 'A' extension on all atomic instructions
      target/riscv: Add infrastructure for 'B' MISA extension
      target/riscv: Add step to validate 'B' extension
      target/riscv: Add Zaamo and Zalrsc extension infrastructure
      target/riscv: Check 'A' and split extensions for atomic instructions
      target/riscv: Expose Zaamo and Zalrsc extensions

 include/hw/firmware/smbios.h               |    1 +
 target/riscv/cpu-qom.h                     |    3 +
 target/riscv/cpu.h                         |   30 +-
 target/riscv/cpu_bits.h                    |   15 +-
 target/riscv/cpu_cfg.h                     |    8 +-
 target/riscv/kvm/kvm_riscv.h               |    1 +
 hw/riscv/boot.c                            |    3 +-
 hw/riscv/numa.c                            |    4 +-
 hw/riscv/sifive_u.c                        |    7 +-
 hw/riscv/spike.c                           |    6 +-
 hw/riscv/virt-acpi-build.c                 |    2 +-
 hw/riscv/virt.c                            |  153 ++--
 hw/smbios/smbios.c                         |   20 +-
 target/riscv/cpu.c                         | 1106 +++++++++++++++++++++-------
 target/riscv/cpu_helper.c                  |   11 +-
 target/riscv/csr.c                         |  157 ++--
 target/riscv/debug.c                       |    2 +
 target/riscv/gdbstub.c                     |   18 +-
 target/riscv/kvm/kvm-cpu.c                 |  250 +++++--
 target/riscv/machine.c                     |    7 +-
 target/riscv/tcg/tcg-cpu.c                 |  143 ++--
 target/riscv/translate.c                   |    3 +-
 target/riscv/vector_helper.c               |   43 +-
 target/riscv/insn_trans/trans_rva.c.inc    |   45 +-
 target/riscv/insn_trans/trans_rvbf16.c.inc |   12 +-
 target/riscv/insn_trans/trans_rvv.c.inc    |  152 ++--
 target/riscv/insn_trans/trans_rvvk.c.inc   |   16 +-
 target/riscv/insn_trans/trans_xthead.c.inc |   10 -
 hw/riscv/Kconfig                           |    1 +
 qemu-options.hx                            |    6 +-
 30 files changed, 1522 insertions(+), 713 deletions(-)
Re: [PULL 00/61] riscv-to-apply queue
Posted by Peter Maydell 1 week, 5 days ago
On Fri, 9 Feb 2024 at 10:59, Alistair Francis <alistair23@gmail.com> wrote:
>
> The following changes since commit 03e4bc0bc02779fdf6f8e8d83197f05e70881abf:
>
>   Merge tag 'pull-tcg-20240205-2' of https://gitlab.com/rth7680/qemu into staging (2024-02-08 16:08:42 +0000)
>
> are available in the Git repository at:
>
>   https://github.com/alistair23/qemu.git tags/pull-riscv-to-apply-20240209
>
> for you to fetch changes up to deb0ff0c777d20602ecc5b6f74f18cb7ecc0b91f:
>
>   target/riscv: add rv32i, rv32e and rv64e CPUs (2024-02-09 20:49:41 +1000)
>
> ----------------------------------------------------------------
> RISC-V PR for 9.0
>
> * Check for 'A' extension on all atomic instructions
> * Add support for 'B' extension
> * Internally deprecate riscv_cpu_options
> * Implement optional CSR mcontext of debug Sdtrig extension
> * Internally add cpu->cfg.vlenb and  remove cpu->cfg.vlen
> * Support vlenb and vregs[] in KVM
> * RISC-V gdbstub and TCG plugin improvements
> * Remove vxrm and vxsat from FCSR
> * Use RISCVException as return type for all csr ops
> * Use g_autofree more and fix a memory leak
> * Add support for Zaamo and Zalrsc
> * Support new isa extension detection devicetree properties
> * SMBIOS support for RISC-V virt machine
> * Enable xtheadsync under user mode
> * Add rv32i,rv32e and rv64e CPUs
>


Applied, thanks.

Please update the changelog at https://wiki.qemu.org/ChangeLog/9.0
for any user-visible changes.

-- PMM