On Thu, Jan 4, 2024 at 3:48 AM Daniel Henrique Barboza
<dbarboza@ventanamicro.com> wrote:
>
> Turning 'vlen' into a class property will allow its default value to be
> overwritten by cpu_init() later on, solving the issue we have now where
> CPU specific settings are getting overwritten by the default.
>
> Common validation bits are moved from riscv_cpu_validate_v() to
> prop_vlen_set() to be shared with KVM.
>
> And, as done with every option we migrated to riscv_cpu_properties[],
> vendor CPUs can't have their 'vlen' value changed.
>
> Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
> ---
> target/riscv/cpu.c | 45 +++++++++++++++++++++++++++++++++++++-
> target/riscv/tcg/tcg-cpu.c | 5 -----
> 2 files changed, 44 insertions(+), 6 deletions(-)
>
> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> index c39da44f51..557874a017 100644
> --- a/target/riscv/cpu.c
> +++ b/target/riscv/cpu.c
> @@ -29,6 +29,7 @@
> #include "qapi/visitor.h"
> #include "qemu/error-report.h"
> #include "hw/qdev-properties.h"
> +#include "hw/core/qdev-prop-internal.h"
> #include "migration/vmstate.h"
> #include "fpu/softfloat-helpers.h"
> #include "sysemu/kvm.h"
> @@ -1267,6 +1268,7 @@ static void riscv_cpu_init(Object *obj)
>
> /* Default values for non-bool cpu properties */
> cpu->cfg.pmu_mask = MAKE_64BIT_MASK(3, 16);
> + cpu->cfg.vlen = 128;
> cpu->env.vext_ver = VEXT_VERSION_1_00_0;
> }
>
> @@ -1733,8 +1735,47 @@ static const PropertyInfo prop_vext_spec = {
> .set = prop_vext_spec_set,
> };
>
> +static void prop_vlen_set(Object *obj, Visitor *v, const char *name,
> + void *opaque, Error **errp)
> +{
> + RISCVCPU *cpu = RISCV_CPU(obj);
> + uint16_t value;
> +
> + if (!visit_type_uint16(v, name, &value, errp)) {
> + return;
> + }
> +
> + if (!is_power_of_2(value)) {
> + error_setg(errp, "Vector extension VLEN must be power of 2");
> + return;
> + }
> +
> + if (value != cpu->cfg.vlen && riscv_cpu_is_vendor(obj)) {
> + cpu_set_prop_err(cpu, name, errp);
> + error_append_hint(errp, "Current '%s' val: %u\n",
> + name, cpu->cfg.vlen);
> + return;
> + }
> +
> + cpu_option_add_user_setting(name, value);
> + cpu->cfg.vlen = value;
> +}
> +
> +static void prop_vlen_get(Object *obj, Visitor *v, const char *name,
> + void *opaque, Error **errp)
> +{
> + uint16_t value = RISCV_CPU(obj)->cfg.vlen;
> +
> + visit_type_uint16(v, name, &value, errp);
> +}
> +
> +static const PropertyInfo prop_vlen = {
> + .name = "vlen",
> + .get = prop_vlen_get,
> + .set = prop_vlen_set,
> +};
> +
> Property riscv_cpu_options[] = {
> - DEFINE_PROP_UINT16("vlen", RISCVCPU, cfg.vlen, 128),
> DEFINE_PROP_UINT16("elen", RISCVCPU, cfg.elen, 64),
>
> DEFINE_PROP_UINT16("cbom_blocksize", RISCVCPU, cfg.cbom_blocksize, 64),
> @@ -1755,6 +1796,8 @@ static Property riscv_cpu_properties[] = {
> {.name = "priv_spec", .info = &prop_priv_spec},
> {.name = "vext_spec", .info = &prop_vext_spec},
>
> + {.name = "vlen", .info = &prop_vlen},
> +
> #ifndef CONFIG_USER_ONLY
> DEFINE_PROP_UINT64("resetvec", RISCVCPU, env.resetvec, DEFAULT_RSTVEC),
> #endif
> diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c
> index 6501c29d8e..8ec858e096 100644
> --- a/target/riscv/tcg/tcg-cpu.c
> +++ b/target/riscv/tcg/tcg-cpu.c
> @@ -178,11 +178,6 @@ static void riscv_cpu_validate_misa_mxl(RISCVCPU *cpu, Error **errp)
> static void riscv_cpu_validate_v(CPURISCVState *env, RISCVCPUConfig *cfg,
> Error **errp)
> {
> - if (!is_power_of_2(cfg->vlen)) {
> - error_setg(errp, "Vector extension VLEN must be power of 2");
> - return;
> - }
> -
> if (cfg->vlen > RV_VLEN_MAX || cfg->vlen < 128) {
> error_setg(errp,
> "Vector extension implementation only supports VLEN "
> --
> 2.43.0
>
>