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([189.79.21.107]) by smtp.gmail.com with ESMTPSA id v3-20020aa78503000000b006d7f1ae421csm24042050pfn.145.2024.01.03.09.40.47 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 03 Jan 2024 09:40:49 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1704303650; x=1704908450; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=Lf45moVsB1V70aKXjn6Z7X3nShbqPvle7BNNm9DCtHg=; b=o7uRFLJuwmA6xPussQvKXvl5DoCJ8zqZkh3E5hcYVdzFYv2NMR6ktR/8orucvlj2yU Curs8ouC/Gdi/2BVED5vrX7AioFSCEJgCmZwGR7YKGygs8qCBWKswihILTZQ5E4sBiIL V+DCSst6dUQbl7V4Qo2alNTJ15Xbt9RQCWH7Vh/r7FYfw/60pwHRZ0+tVypB33pGhtNW 5uH9N96KIbVXx6wEFbP39JhMDiJul7BFoPGoeeRCFehmvv7SN8Ph9GyrhsyLUKm6F7zP AX6VJpLk/XSJWQcJauSjBoDnaLEEW5Zj7cGNveHidmVN21ijaRDZHg1YdgeegzXgxGw5 f25Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1704303650; x=1704908450; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=Lf45moVsB1V70aKXjn6Z7X3nShbqPvle7BNNm9DCtHg=; b=o0j7DhH8E0Dg7+1QD0AMFo740vzfXLhy6Iw3u6+/ZdhK2iSFoSIG7U0P73Crfysgrd Hhavhs+LlShJ+ru4SvM6OdzXOrXq2xyTigfwDyhfkAxxhwIcN5sYGOyXZMzEHQaX6W1C isqNRd4O7nrZuf+TE/J/R7OLO5VgNNUymnH0hUAS+dLZChUBxpHByMFDdwV1ThIf0G25 DXFfSPEvCQFSQvNFLxqY5Rqpe6y1Gm7T3M1EGE5EX/mBa3Vfxl4iwhhp+F/52zPgMN4p lDuszlxwajpbP333hRveE4oHEmnzK9eSIRYAy+68C9nDSdVGAgGsOBjHm5OVxl/rHw/f F00Q== X-Gm-Message-State: AOJu0Yz89OXR2nTABBFtqQhuf6PpviCgYrTA2ScuwVn3xIo1V9mzNffj qhHcX9K/nIKKjIiQuyZkOllBuCFsblnisCAUUeV0PKdJsjI6BA== X-Google-Smtp-Source: AGHT+IFCMVDzevNCf3ERFrj0IupnV83wOk+utnq2Tr9ry5eB+7TTwLTkwdsUZ9kyFt8RabE1QaLYJg== X-Received: by 2002:a05:6a00:26e3:b0:6d9:9edd:60a0 with SMTP id p35-20020a056a0026e300b006d99edd60a0mr6252093pfw.46.1704303649915; Wed, 03 Jan 2024 09:40:49 -0800 (PST) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, bmeng@tinylab.org, liwei1518@gmail.com, zhiwei_liu@linux.alibaba.com, palmer@rivosinc.com, ajones@ventanamicro.com, vladimir.isaev@syntacore.com, Daniel Henrique Barboza Subject: [PATCH v3 08/16] target/riscv: move 'vlen' to riscv_cpu_properties[] Date: Wed, 3 Jan 2024 14:40:05 -0300 Message-ID: <20240103174013.147279-9-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240103174013.147279-1-dbarboza@ventanamicro.com> References: <20240103174013.147279-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::42b; envelope-from=dbarboza@ventanamicro.com; helo=mail-pf1-x42b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ventanamicro.com) X-ZM-MESSAGEID: 1704303813779100001 Content-Type: text/plain; charset="utf-8" Turning 'vlen' into a class property will allow its default value to be overwritten by cpu_init() later on, solving the issue we have now where CPU specific settings are getting overwritten by the default. Common validation bits are moved from riscv_cpu_validate_v() to prop_vlen_set() to be shared with KVM. And, as done with every option we migrated to riscv_cpu_properties[], vendor CPUs can't have their 'vlen' value changed. Signed-off-by: Daniel Henrique Barboza Reviewed-by: Alistair Francis --- target/riscv/cpu.c | 45 +++++++++++++++++++++++++++++++++++++- target/riscv/tcg/tcg-cpu.c | 5 ----- 2 files changed, 44 insertions(+), 6 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index c39da44f51..557874a017 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -29,6 +29,7 @@ #include "qapi/visitor.h" #include "qemu/error-report.h" #include "hw/qdev-properties.h" +#include "hw/core/qdev-prop-internal.h" #include "migration/vmstate.h" #include "fpu/softfloat-helpers.h" #include "sysemu/kvm.h" @@ -1267,6 +1268,7 @@ static void riscv_cpu_init(Object *obj) =20 /* Default values for non-bool cpu properties */ cpu->cfg.pmu_mask =3D MAKE_64BIT_MASK(3, 16); + cpu->cfg.vlen =3D 128; cpu->env.vext_ver =3D VEXT_VERSION_1_00_0; } =20 @@ -1733,8 +1735,47 @@ static const PropertyInfo prop_vext_spec =3D { .set =3D prop_vext_spec_set, }; =20 +static void prop_vlen_set(Object *obj, Visitor *v, const char *name, + void *opaque, Error **errp) +{ + RISCVCPU *cpu =3D RISCV_CPU(obj); + uint16_t value; + + if (!visit_type_uint16(v, name, &value, errp)) { + return; + } + + if (!is_power_of_2(value)) { + error_setg(errp, "Vector extension VLEN must be power of 2"); + return; + } + + if (value !=3D cpu->cfg.vlen && riscv_cpu_is_vendor(obj)) { + cpu_set_prop_err(cpu, name, errp); + error_append_hint(errp, "Current '%s' val: %u\n", + name, cpu->cfg.vlen); + return; + } + + cpu_option_add_user_setting(name, value); + cpu->cfg.vlen =3D value; +} + +static void prop_vlen_get(Object *obj, Visitor *v, const char *name, + void *opaque, Error **errp) +{ + uint16_t value =3D RISCV_CPU(obj)->cfg.vlen; + + visit_type_uint16(v, name, &value, errp); +} + +static const PropertyInfo prop_vlen =3D { + .name =3D "vlen", + .get =3D prop_vlen_get, + .set =3D prop_vlen_set, +}; + Property riscv_cpu_options[] =3D { - DEFINE_PROP_UINT16("vlen", RISCVCPU, cfg.vlen, 128), DEFINE_PROP_UINT16("elen", RISCVCPU, cfg.elen, 64), =20 DEFINE_PROP_UINT16("cbom_blocksize", RISCVCPU, cfg.cbom_blocksize, 64), @@ -1755,6 +1796,8 @@ static Property riscv_cpu_properties[] =3D { {.name =3D "priv_spec", .info =3D &prop_priv_spec}, {.name =3D "vext_spec", .info =3D &prop_vext_spec}, =20 + {.name =3D "vlen", .info =3D &prop_vlen}, + #ifndef CONFIG_USER_ONLY DEFINE_PROP_UINT64("resetvec", RISCVCPU, env.resetvec, DEFAULT_RSTVEC), #endif diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c index 6501c29d8e..8ec858e096 100644 --- a/target/riscv/tcg/tcg-cpu.c +++ b/target/riscv/tcg/tcg-cpu.c @@ -178,11 +178,6 @@ static void riscv_cpu_validate_misa_mxl(RISCVCPU *cpu,= Error **errp) static void riscv_cpu_validate_v(CPURISCVState *env, RISCVCPUConfig *cfg, Error **errp) { - if (!is_power_of_2(cfg->vlen)) { - error_setg(errp, "Vector extension VLEN must be power of 2"); - return; - } - if (cfg->vlen > RV_VLEN_MAX || cfg->vlen < 128) { error_setg(errp, "Vector extension implementation only supports VLEN " --=20 2.43.0