[PATCH for-9.0 v11 00/18] rv64i and rva22u64 CPUs, RVA22U64 profile support

Daniel Henrique Barboza posted 18 patches 1 year ago
Patches applied successfully (tree, apply log)
git fetch https://github.com/patchew-project/qemu tags/patchew/20231123185122.1100436-1-dbarboza@ventanamicro.com
Maintainers: Palmer Dabbelt <palmer@dabbelt.com>, Alistair Francis <alistair.francis@wdc.com>, Bin Meng <bin.meng@windriver.com>, Weiwei Li <liwei1518@gmail.com>, Daniel Henrique Barboza <dbarboza@ventanamicro.com>, Liu Zhiwei <zhiwei_liu@linux.alibaba.com>
hw/riscv/virt.c               |   5 +
target/riscv/cpu-qom.h        |   4 +
target/riscv/cpu.c            | 134 ++++++++++++-
target/riscv/cpu.h            |  13 ++
target/riscv/cpu_cfg.h        |   3 +
target/riscv/kvm/kvm-cpu.c    |   7 +-
target/riscv/riscv-qmp-cmds.c |  44 +++-
target/riscv/tcg/tcg-cpu.c    | 367 ++++++++++++++++++++++++++++++----
8 files changed, 524 insertions(+), 53 deletions(-)
[PATCH for-9.0 v11 00/18] rv64i and rva22u64 CPUs, RVA22U64 profile support
Posted by Daniel Henrique Barboza 1 year ago
Hi,

In this new version we added a new function, riscv_cpu_enable_named_feat(),
to allow profiles to enable named features.

This doesn't have much of an impact for this current work - the only
named feature we're using here is zic64b and the default block size
values already satisfies it.

The reason we're doing this change now is due to the incoming RVA22S64
support. A new named featured called 'svade' will be added for it, and
'svade' is NOT enabled by default in QEMU. Profiles will need to enable
named features to support RVA22S64, so might as well implement this
capability right from the start.

Series based on master.

Patches missing acks: patch 10

Changes from v10:
- patch 10:
  - add riscv_cpu_enable_named_feat()
  - enable named features during cpu_set_profile()
- v10 link: https://lore.kernel.org/qemu-riscv/20231103134629.561732-1-dbarboza@ventanamicro.com/


Daniel Henrique Barboza (18):
  target/riscv: create TYPE_RISCV_VENDOR_CPU
  target/riscv/tcg: do not use "!generic" CPU checks
  target/riscv/tcg: update priv_ver on user_set extensions
  target/riscv: add rv64i CPU
  target/riscv: add zicbop extension flag
  target/riscv/tcg: add 'zic64b' support
  riscv-qmp-cmds.c: expose named features in cpu_model_expansion
  target/riscv: add rva22u64 profile definition
  target/riscv/kvm: add 'rva22u64' flag as unavailable
  target/riscv/tcg: add user flag for profile support
  target/riscv/tcg: add MISA user options hash
  target/riscv/tcg: add riscv_cpu_write_misa_bit()
  target/riscv/tcg: handle profile MISA bits
  target/riscv/tcg: add hash table insert helpers
  target/riscv/tcg: honor user choice for G MISA bits
  target/riscv/tcg: validate profiles during finalize
  riscv-qmp-cmds.c: add profile flags in cpu-model-expansion
  target/riscv: add 'rva22u64' CPU

 hw/riscv/virt.c               |   5 +
 target/riscv/cpu-qom.h        |   4 +
 target/riscv/cpu.c            | 134 ++++++++++++-
 target/riscv/cpu.h            |  13 ++
 target/riscv/cpu_cfg.h        |   3 +
 target/riscv/kvm/kvm-cpu.c    |   7 +-
 target/riscv/riscv-qmp-cmds.c |  44 +++-
 target/riscv/tcg/tcg-cpu.c    | 367 ++++++++++++++++++++++++++++++----
 8 files changed, 524 insertions(+), 53 deletions(-)

-- 
2.41.0