From nobody Wed Nov 27 04:55:50 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1700765642; cv=none; d=zohomail.com; s=zohoarc; b=m+WoMptnihncLkbUL+jaf6TCy6UpOtzCq4ADaAY/odbQze1vjQp7snCtBtj64ygEZSckQASiLkB5HKhd+gKIgv/yN+iLvKmwCt3PzH7ABXECIZLtSGVnfa0kxU7dpRB7VefCy03CxLrewMpiwoZxslI8DEN/Jte72+i+A7WyR/s= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1700765642; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=g27N76GsCjcJjpEII+LykYnwIqcFv/pUM+HDkvpl0o4=; b=FuySecPZUPd6+lvvq/kM8Hu6Vx429YEbA/n/l/z5pMGESNbthNdOv+p5dge+DxljY9EExxmfyXoIWZLfSCpbXiIXyWGXpQl+iNuoQg8y38K42yb18oGvyR4CSKnoWYRrvUpZWUNzcmrMo8P8g08Md4EJ//+v9KLOgZrGJ+MpEuc= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1700765642882398.7845062403144; Thu, 23 Nov 2023 10:54:02 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1r6Ens-0007yP-MG; Thu, 23 Nov 2023 13:51:59 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1r6EnY-0007rW-9R for qemu-devel@nongnu.org; Thu, 23 Nov 2023 13:51:36 -0500 Received: from mail-pl1-x630.google.com ([2607:f8b0:4864:20::630]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1r6EnW-0008Fh-Jl for qemu-devel@nongnu.org; Thu, 23 Nov 2023 13:51:36 -0500 Received: by mail-pl1-x630.google.com with SMTP id d9443c01a7336-1ce656b9780so8317785ad.2 for ; Thu, 23 Nov 2023 10:51:34 -0800 (PST) Received: from grind.. ([2804:7f0:bdcd:fb00:6501:2693:db52:c621]) by smtp.gmail.com with ESMTPSA id u4-20020a17090282c400b001bb1f0605b2sm1662638plz.214.2023.11.23.10.51.28 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 23 Nov 2023 10:51:31 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1700765491; x=1701370291; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=g27N76GsCjcJjpEII+LykYnwIqcFv/pUM+HDkvpl0o4=; b=NmuuQXi4bvvQZarTM6mJVh1WPBsUv56779S7ma7RhUbqT1HOQeGD12PEI0+HyQIP8K ZfVYPZDdbB3wHvnfItE4D46T1EkS7Tr+TvNUBkuf2jzv7LB1WUBTaPL7KCGFq1hhuMP3 xHplDJiVUx5sw/Neu4+RUf77XZ+6Jne9Ad6D7PyAOfRXnyLBNPckvP4qmd2vetNRCzu9 Sl6JVi9POYVrcv9aSKHVJcl1S2NguM2lYk4QGtVgYQ4BzwBATGVqRNwkih0Cf7YVOCzS QbZFIj2nPHivbNXBgFk4nRzs4WViMDpz5dimHOd40Z1mekyd486yyoX6vFIFHW5K7FVP L9YQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1700765491; x=1701370291; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=g27N76GsCjcJjpEII+LykYnwIqcFv/pUM+HDkvpl0o4=; b=HSyKAu2Lpfs7UtxwcpaX6NTgZSbGVorcWeU+J+VOiPhmj11tWbY5SxZwE/LRftZDiw ZvBJnd5lrmcJ32jgtrWfJ18qdOnONXhpEJUXEAU+LLaZum5s3WKW9F9cuiHMwafH8sP+ X4TDKLD5728QIvw78rn37YxPRC9yt3Qmv6BpXJldrDDH76HdXz+Fg1l/2X/gWvx1ajxc nrZL/AtWLxLeat6cUyS2vRtasWVbSLno5PbiwYSaIKRcG+dMSpoUpvH5mFa6hQ2fuUEi vNkPvFohW3Ch5HGYcmrZKury+iI0SIE/5oZiK3OCc8twH2Wld9W0/TpNffOPhk6pdecF H+6A== X-Gm-Message-State: AOJu0YynVpOfVjlwuliGZG/SJQ+QszqOVelK+fP6q8wLmEpgYmenLUMl IIjmEdJ4EW9rIl+RTsSyxmp/y9WzYpv7cTvqiHg= X-Google-Smtp-Source: AGHT+IEn6hBidhlqvFYJfiXuElEOlm0ZqGjvNTIowvABVIEvK9N4B/j4ME5THOQdOW0N4Yv4tWR0fw== X-Received: by 2002:a17:903:24c:b0:1ce:5b93:1596 with SMTP id j12-20020a170903024c00b001ce5b931596mr415717plh.5.1700765491496; Thu, 23 Nov 2023 10:51:31 -0800 (PST) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, bmeng@tinylab.org, liwei1518@gmail.com, zhiwei_liu@linux.alibaba.com, palmer@rivosinc.com, ajones@ventanamicro.com, Daniel Henrique Barboza Subject: [PATCH for-9.0 v11 01/18] target/riscv: create TYPE_RISCV_VENDOR_CPU Date: Thu, 23 Nov 2023 15:51:05 -0300 Message-ID: <20231123185122.1100436-2-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20231123185122.1100436-1-dbarboza@ventanamicro.com> References: <20231123185122.1100436-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::630; envelope-from=dbarboza@ventanamicro.com; helo=mail-pl1-x630.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ventanamicro.com) X-ZM-MESSAGEID: 1700765643790100013 Content-Type: text/plain; charset="utf-8" We want to add a new CPU type for bare CPUs that will inherit specific traits of the 2 existing types: - it will allow for extensions to be enabled/disabled, like generic CPUs; - it will NOT inherit defaults, like vendor CPUs. We can make this conditions met by adding an explicit type for the existing vendor CPUs and change the existing logic to not imply that "not generic" means vendor CPUs. Let's add the "vendor" CPU type first. Signed-off-by: Daniel Henrique Barboza Reviewed-by: Andrew Jones Reviewed-by: Alistair Francis --- target/riscv/cpu-qom.h | 1 + target/riscv/cpu.c | 30 +++++++++++++++++++++--------- 2 files changed, 22 insertions(+), 9 deletions(-) diff --git a/target/riscv/cpu-qom.h b/target/riscv/cpu-qom.h index 91b3361dec..ca7dd509e3 100644 --- a/target/riscv/cpu-qom.h +++ b/target/riscv/cpu-qom.h @@ -23,6 +23,7 @@ =20 #define TYPE_RISCV_CPU "riscv-cpu" #define TYPE_RISCV_DYNAMIC_CPU "riscv-dynamic-cpu" +#define TYPE_RISCV_VENDOR_CPU "riscv-vendor-cpu" =20 #define RISCV_CPU_TYPE_SUFFIX "-" TYPE_RISCV_CPU #define RISCV_CPU_TYPE_NAME(name) (name RISCV_CPU_TYPE_SUFFIX) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 83c7c0cf07..220113408e 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -1778,6 +1778,13 @@ void riscv_cpu_list(void) .instance_init =3D initfn \ } =20 +#define DEFINE_VENDOR_CPU(type_name, initfn) \ + { \ + .name =3D type_name, \ + .parent =3D TYPE_RISCV_VENDOR_CPU, \ + .instance_init =3D initfn \ + } + static const TypeInfo riscv_cpu_type_infos[] =3D { { .name =3D TYPE_RISCV_CPU, @@ -1795,21 +1802,26 @@ static const TypeInfo riscv_cpu_type_infos[] =3D { .parent =3D TYPE_RISCV_CPU, .abstract =3D true, }, + { + .name =3D TYPE_RISCV_VENDOR_CPU, + .parent =3D TYPE_RISCV_CPU, + .abstract =3D true, + }, DEFINE_DYNAMIC_CPU(TYPE_RISCV_CPU_ANY, riscv_any_cpu_init), DEFINE_DYNAMIC_CPU(TYPE_RISCV_CPU_MAX, riscv_max_cpu_init), #if defined(TARGET_RISCV32) DEFINE_DYNAMIC_CPU(TYPE_RISCV_CPU_BASE32, rv32_base_cpu_init), - DEFINE_CPU(TYPE_RISCV_CPU_IBEX, rv32_ibex_cpu_init), - DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E31, rv32_sifive_e_cpu_init), - DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E34, rv32_imafcu_nommu_cpu_init= ), - DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_U34, rv32_sifive_u_cpu_init), + DEFINE_VENDOR_CPU(TYPE_RISCV_CPU_IBEX, rv32_ibex_cpu_init), + DEFINE_VENDOR_CPU(TYPE_RISCV_CPU_SIFIVE_E31, rv32_sifive_e_cpu_init), + DEFINE_VENDOR_CPU(TYPE_RISCV_CPU_SIFIVE_E34, rv32_imafcu_nommu_cpu_in= it), + DEFINE_VENDOR_CPU(TYPE_RISCV_CPU_SIFIVE_U34, rv32_sifive_u_cpu_init), #elif defined(TARGET_RISCV64) DEFINE_DYNAMIC_CPU(TYPE_RISCV_CPU_BASE64, rv64_base_cpu_init), - DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E51, rv64_sifive_e_cpu_init), - DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_U54, rv64_sifive_u_cpu_init), - DEFINE_CPU(TYPE_RISCV_CPU_SHAKTI_C, rv64_sifive_u_cpu_init), - DEFINE_CPU(TYPE_RISCV_CPU_THEAD_C906, rv64_thead_c906_cpu_init), - DEFINE_CPU(TYPE_RISCV_CPU_VEYRON_V1, rv64_veyron_v1_cpu_init), + DEFINE_VENDOR_CPU(TYPE_RISCV_CPU_SIFIVE_E51, rv64_sifive_e_cpu_init), + DEFINE_VENDOR_CPU(TYPE_RISCV_CPU_SIFIVE_U54, rv64_sifive_u_cpu_init), + DEFINE_VENDOR_CPU(TYPE_RISCV_CPU_SHAKTI_C, rv64_sifive_u_cpu_init), + DEFINE_VENDOR_CPU(TYPE_RISCV_CPU_THEAD_C906, rv64_thead_c906_cpu_init= ), + DEFINE_VENDOR_CPU(TYPE_RISCV_CPU_VEYRON_V1, rv64_veyron_v1_cpu_init), DEFINE_DYNAMIC_CPU(TYPE_RISCV_CPU_BASE128, rv128_base_cpu_init), #endif }; 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([2804:7f0:bdcd:fb00:6501:2693:db52:c621]) by smtp.gmail.com with ESMTPSA id u4-20020a17090282c400b001bb1f0605b2sm1662638plz.214.2023.11.23.10.51.31 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 23 Nov 2023 10:51:34 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1700765494; x=1701370294; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=P8Z8wJmbxe8GqrZMSuETlZ1jRJvjF/0/Y4v1dc9cYe0=; b=kodfxSs34RmTKfA3Ir3WRcz1uUTytmhJz6rTRLV4DuaW+1EsXUMH3lBpqKyhcXaowJ 25mEMrqY2xEOdLj+OGXkBNyZFdsQt4rV6lW2oDt3oQUE1GdTHtYMZdHMx77K6EjMK5Vo ggfXfiKKGjWo4ff8dnPtvbtutgtAvfUb5uKB3ogohgd/RQE5EgBQSpWeUtr0VSslWSF8 +m4ZQ/MuZHj9tnuSvW7JQ66uoGjtdPol8M4f+JQpq1dzlryuJW2Sj+YA0SFj/m5bfBIa O7/4lE71Vegbk0CN/9VTchjwmS/VXUVCZrvEpRLkLRjnl7BH73uC5CH7xnFX7yaUqzQw NCBg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1700765494; x=1701370294; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=P8Z8wJmbxe8GqrZMSuETlZ1jRJvjF/0/Y4v1dc9cYe0=; b=EGHQeRgM8/v0k1+AVPf85fp7EwlStl+ZL0j6Vdp8/H8IzPU4JF0knwXGTR0ivqgng0 NaGYWRx5pvKeZhsOQA/+xpTtWmdDHaikTuIxVIfZ13UFyFmr8TEHHJavLMD/oBUkkkh4 PVCXchwbYv1xulD6VLmWC7ggtP3ZuqVUuQkclfjAaAI71HbG2QO8SP+igE1+z5lZyMpU BHzfBe6NhHvkYDNypLyTYsY0v+m9r8HFCAdW3/kkXAlQnWjq/aat57PApZ4zrFUyJ8KW oJdhDmQ8FYqJrWm/yyzo+VJXmrN4+lSEDmJH81Ucn2GVSm80FF/V7PEnSRY5gZ7V3ntb MKOw== X-Gm-Message-State: AOJu0Yy+ylwCDsjhf2KYC0zsyqkihPg0Vg5fEVuCWmD1s4HeWNmam717 /mKYH7LQ/OFk1zDfOHViQmlWE8ViZVo5KNsTQr8= X-Google-Smtp-Source: AGHT+IGhDFs4teqWjRdzFVgWEm+N+xXKGuzznT2/tWeMoZ5LHMrHhDk5/3Zm19QlTT+SQG2FFN8RVA== X-Received: by 2002:a05:6a20:e30b:b0:187:152d:c1e2 with SMTP id nb11-20020a056a20e30b00b00187152dc1e2mr489882pzb.46.1700765494589; Thu, 23 Nov 2023 10:51:34 -0800 (PST) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, bmeng@tinylab.org, liwei1518@gmail.com, zhiwei_liu@linux.alibaba.com, palmer@rivosinc.com, ajones@ventanamicro.com, Daniel Henrique Barboza Subject: [PATCH for-9.0 v11 02/18] target/riscv/tcg: do not use "!generic" CPU checks Date: Thu, 23 Nov 2023 15:51:06 -0300 Message-ID: <20231123185122.1100436-3-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20231123185122.1100436-1-dbarboza@ventanamicro.com> References: <20231123185122.1100436-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::42b; envelope-from=dbarboza@ventanamicro.com; helo=mail-pf1-x42b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ventanamicro.com) X-ZM-MESSAGEID: 1700765625659100003 Content-Type: text/plain; charset="utf-8" Our current logic in get/setters of MISA and multi-letter extensions works because we have only 2 CPU types, generic and vendor, and by using "!generic" we're implying that we're talking about vendor CPUs. When adding a third CPU type this logic will break so let's handle it beforehand. In set_misa_ext_cfg() and set_multi_ext_cfg(), check for "vendor" cpu inste= ad of "not generic". The "generic CPU" checks remaining are from riscv_cpu_add_misa_properties() and cpu_add_multi_ext_prop() before applying default values for the extensions. This leaves us with: - vendor CPUs will not allow extension enablement, all other CPUs will; - generic CPUs will inherit default values for extensions, all others won't. And now we can add a new, third CPU type, that will allow extensions to be enabled and will not inherit defaults, without changing the existing logic. Signed-off-by: Daniel Henrique Barboza Reviewed-by: Andrew Jones Reviewed-by: Alistair Francis --- target/riscv/tcg/tcg-cpu.c | 13 +++++++++---- 1 file changed, 9 insertions(+), 4 deletions(-) diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c index 8a35683a34..7670120673 100644 --- a/target/riscv/tcg/tcg-cpu.c +++ b/target/riscv/tcg/tcg-cpu.c @@ -663,6 +663,11 @@ static bool riscv_cpu_is_generic(Object *cpu_obj) return object_dynamic_cast(cpu_obj, TYPE_RISCV_DYNAMIC_CPU) !=3D NULL; } =20 +static bool riscv_cpu_is_vendor(Object *cpu_obj) +{ + return object_dynamic_cast(cpu_obj, TYPE_RISCV_VENDOR_CPU) !=3D NULL; +} + /* * We'll get here via the following path: * @@ -731,7 +736,7 @@ static void cpu_set_misa_ext_cfg(Object *obj, Visitor *= v, const char *name, target_ulong misa_bit =3D misa_ext_cfg->misa_bit; RISCVCPU *cpu =3D RISCV_CPU(obj); CPURISCVState *env =3D &cpu->env; - bool generic_cpu =3D riscv_cpu_is_generic(obj); + bool vendor_cpu =3D riscv_cpu_is_vendor(obj); bool prev_val, value; =20 if (!visit_type_bool(v, name, &value, errp)) { @@ -745,7 +750,7 @@ static void cpu_set_misa_ext_cfg(Object *obj, Visitor *= v, const char *name, } =20 if (value) { - if (!generic_cpu) { + if (vendor_cpu) { g_autofree char *cpuname =3D riscv_cpu_get_name(cpu); error_setg(errp, "'%s' CPU does not allow enabling extensions", cpuname); @@ -850,7 +855,7 @@ static void cpu_set_multi_ext_cfg(Object *obj, Visitor = *v, const char *name, { const RISCVCPUMultiExtConfig *multi_ext_cfg =3D opaque; RISCVCPU *cpu =3D RISCV_CPU(obj); - bool generic_cpu =3D riscv_cpu_is_generic(obj); + bool vendor_cpu =3D riscv_cpu_is_vendor(obj); bool prev_val, value; =20 if (!visit_type_bool(v, name, &value, errp)) { @@ -874,7 +879,7 @@ static void cpu_set_multi_ext_cfg(Object *obj, Visitor = *v, const char *name, return; } =20 - if (value && !generic_cpu) { + if (value && vendor_cpu) { g_autofree char *cpuname =3D riscv_cpu_get_name(cpu); error_setg(errp, "'%s' CPU does not allow enabling extensions", cpuname); --=20 2.41.0 From nobody Wed Nov 27 04:55:50 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1700765599; cv=none; d=zohomail.com; s=zohoarc; b=DJGQAcA7aBEzF9Ulik8Bs5sE6EkZCvKkuJCPiSk6brdwiF7kF8yHc5Ksuz2Ct01bzBCbH8zYZgLChnD6buLuehRX4kIj2RfgunGy+B3NvJ/k76qFUEKcRhOciz+fKpmrLEQ0K3QG8UcmrL5xSmLoz9KmtOrPA2MLMccm4MPmxOg= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1700765599; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=ruiTI99kRyklGs/0AQ4FQ49sw2zrr1cnj0+s1Urj/nw=; b=K28NuxYSdiZz2H2eWBgsNRBnthjvCOUweEV5YSeIc81dGmoVaQE+Q73jHr3A+2J2CYRVmJ+hojZRLTj8J+O2eYfDPNZgb/V1bOgctGxpVHPsOqufziWDlRRq5rBO6DaFdlvoCPnQMqZ2dfGCfkOx8nsCpddVymIZjMriovDaNdg= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1700765599680743.0597992144912; Thu, 23 Nov 2023 10:53:19 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1r6Eo5-0008Bn-Lg; Thu, 23 Nov 2023 13:52:09 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1r6Enl-0007y8-S9 for qemu-devel@nongnu.org; Thu, 23 Nov 2023 13:51:53 -0500 Received: from mail-pl1-x634.google.com ([2607:f8b0:4864:20::634]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1r6End-0008H0-1D for qemu-devel@nongnu.org; Thu, 23 Nov 2023 13:51:46 -0500 Received: by mail-pl1-x634.google.com with SMTP id d9443c01a7336-1cf8b35a6dbso7210845ad.0 for ; Thu, 23 Nov 2023 10:51:39 -0800 (PST) Received: from grind.. ([2804:7f0:bdcd:fb00:6501:2693:db52:c621]) by smtp.gmail.com with ESMTPSA id u4-20020a17090282c400b001bb1f0605b2sm1662638plz.214.2023.11.23.10.51.34 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 23 Nov 2023 10:51:37 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1700765498; x=1701370298; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=ruiTI99kRyklGs/0AQ4FQ49sw2zrr1cnj0+s1Urj/nw=; b=ZnCnPPDWniQCF3qe0/lBSMoX+DybA06xe9XFPrj/8QiuJHdk1/o2rIufO5CCPg+QZn gZXKLc4Zh5jJP4s2OMT9fKLESnb6J97wJSAlk8d3TkBnfUycH8JTWK+MxaECSOC9a9iF Im3qEXVimxdM6mcbC6hsHT24Vs9RgOzmlS8dr3jxu5SuYJm9av7lkgPiwM1CpLHLJEq2 KHok5Ttxr/kYoglQWrvqt4j3AFu8I2ywwIBIYbgykZjiottWqcjCTm7+rn+IGtHaFEpu M2tTwSkB3UeDkGDptH1roInq01cVWIUaJudlVyMwjn9rpekReGRQaDyc7kTSJWzaCT3E AZvg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1700765498; x=1701370298; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=ruiTI99kRyklGs/0AQ4FQ49sw2zrr1cnj0+s1Urj/nw=; b=gZZjOKDIJrO0U1SzvOHj2erKY+99B9KTHa9NmqK7LbmiG9+orVc6fVOw8u2DgokpGD oBAV2KOfk+fxWhj1MITI8ZeHHqVZetK6QPcE3d9Xp8Mt9e+WQG2fn8zNzq0M3dj/p6FC jd1Tcr4NIADODSCzFZYf5gcdPROs1TQlBY5oyfGzs+NKrBFv72QoMAl44DehjFsI4tIa KhBBzvJEMCqTKgpAkBHl7+GJIwYV8pl/C7fDRXd1KIPG/lwGPItDNZg5PJFwa/DgNKa5 Rnpw3GWxbhQbAZptgGrgrXJfl8NVruXfAawTAc9pL9hipq9XwbzUP3gZGemZc/PSwxrM o6TA== X-Gm-Message-State: AOJu0Yz387mlq2EqF5VODnezhhkKmlJ002L4g/+KR9FN38Tkx8qaG8Q/ r47zy0bBbAxh7FC8ruzl0IxxJVJDd2BGuWqzvOU= X-Google-Smtp-Source: AGHT+IEO/RYmqV7Jy5PTjl/kwBCwT/n733LSv/IDChWWpxJUOFAZ+qvPWztrUVeYzXbORB6SNA1DCQ== X-Received: by 2002:a17:902:c407:b0:1cf:8ebd:4eae with SMTP id k7-20020a170902c40700b001cf8ebd4eaemr323177plk.69.1700765497767; Thu, 23 Nov 2023 10:51:37 -0800 (PST) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, bmeng@tinylab.org, liwei1518@gmail.com, zhiwei_liu@linux.alibaba.com, palmer@rivosinc.com, ajones@ventanamicro.com, Daniel Henrique Barboza Subject: [PATCH for-9.0 v11 03/18] target/riscv/tcg: update priv_ver on user_set extensions Date: Thu, 23 Nov 2023 15:51:07 -0300 Message-ID: <20231123185122.1100436-4-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20231123185122.1100436-1-dbarboza@ventanamicro.com> References: <20231123185122.1100436-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::634; envelope-from=dbarboza@ventanamicro.com; helo=mail-pl1-x634.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ventanamicro.com) X-ZM-MESSAGEID: 1700765601584100006 Content-Type: text/plain; charset="utf-8" We'll add a new bare CPU type that won't have any default priv_ver. This means that the CPU will default to priv_ver =3D 0, i.e. 1.10.0. At the same we'll allow these CPUs to enable extensions at will, but then, if the extension has a priv_ver newer than 1.10, we'll end up disabling it. Users will then need to manually set priv_ver to something other than 1.10 to enable the extensions they want, which is not ideal. Change the setter() of extensions to allow user enabled extensions to bump the priv_ver of the CPU. This will make it convenient for users to enable extensions for CPUs that doesn't set a default priv_ver. This change does not affect any existing CPU: vendor CPUs does not allow extensions to be enabled, and generic CPUs are already set to priv_ver LATEST. Signed-off-by: Daniel Henrique Barboza Reviewed-by: Andrew Jones --- target/riscv/tcg/tcg-cpu.c | 32 ++++++++++++++++++++++++++++++++ 1 file changed, 32 insertions(+) diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c index 7670120673..d279314624 100644 --- a/target/riscv/tcg/tcg-cpu.c +++ b/target/riscv/tcg/tcg-cpu.c @@ -114,6 +114,26 @@ static int cpu_cfg_ext_get_min_version(uint32_t ext_of= fset) g_assert_not_reached(); } =20 +static void cpu_validate_multi_ext_priv_ver(CPURISCVState *env, + uint32_t ext_offset) +{ + int ext_priv_ver; + + if (env->priv_ver =3D=3D PRIV_VERSION_LATEST) { + return; + } + + ext_priv_ver =3D cpu_cfg_ext_get_min_version(ext_offset); + + if (env->priv_ver < ext_priv_ver) { + /* + * Note: the 'priv_spec' command line option, if present, + * will take precedence over this priv_ver bump. + */ + env->priv_ver =3D ext_priv_ver; + } +} + static void cpu_cfg_ext_auto_update(RISCVCPU *cpu, uint32_t ext_offset, bool value) { @@ -757,6 +777,14 @@ static void cpu_set_misa_ext_cfg(Object *obj, Visitor = *v, const char *name, return; } =20 + if (misa_bit =3D=3D RVH && env->priv_ver < PRIV_VERSION_1_12_0) { + /* + * Note: the 'priv_spec' command line option, if present, + * will take precedence over this priv_ver bump. + */ + env->priv_ver =3D PRIV_VERSION_1_12_0; + } + env->misa_ext |=3D misa_bit; env->misa_ext_mask |=3D misa_bit; } else { @@ -886,6 +914,10 @@ static void cpu_set_multi_ext_cfg(Object *obj, Visitor= *v, const char *name, return; } =20 + if (value) { + cpu_validate_multi_ext_priv_ver(&cpu->env, multi_ext_cfg->offset); + } + isa_ext_update_enabled(cpu, multi_ext_cfg->offset, value); } =20 --=20 2.41.0 From nobody Wed Nov 27 04:55:50 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1700765580; cv=none; d=zohomail.com; s=zohoarc; b=SWk81yBhnxZ5nA11bUFhSaziiPt7sboOwwienWBg415/UXIxIigfD1+Sh4QHRnzgNGUgTk8sfe96fUSjlWiwIzVKbW3Mvk6ijgSK0wiMsUoXrzIPwMKQV2JfxujEu+V/J7Ite9CG/ijrKK1iKeIKLsb8HT2sZoYfjPu4gkmO7R0= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1700765580; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=oNzK71ptVkzN8LH9oIEjdELKVkAXXjFWm0PQTwTkQA4=; b=l4H6vT2u4Yg+zavcxQC6dGVY7eFxGm1oTUBwUi0YNjM8VuFWrj75Tu8F61c//DDt//nbwx4YjDTZtaN/3SogZDvfA+entaPdthmGERl+5w8oP2iUx+mEaI5BDU3X8VB5T1erwSju9zVLKYWqqzevuNDOG20j3fgeKf8P4u9B87Y= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1700765580759868.2302930104629; Thu, 23 Nov 2023 10:53:00 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1r6Eo9-0008HN-HS; Thu, 23 Nov 2023 13:52:13 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1r6Enn-0007yG-PR for qemu-devel@nongnu.org; Thu, 23 Nov 2023 13:51:53 -0500 Received: from mail-pj1-x102d.google.com ([2607:f8b0:4864:20::102d]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1r6Enh-0008HW-79 for qemu-devel@nongnu.org; Thu, 23 Nov 2023 13:51:50 -0500 Received: by mail-pj1-x102d.google.com with SMTP id 98e67ed59e1d1-2855b3d9a9bso832554a91.2 for ; Thu, 23 Nov 2023 10:51:42 -0800 (PST) Received: from grind.. ([2804:7f0:bdcd:fb00:6501:2693:db52:c621]) by smtp.gmail.com with ESMTPSA id u4-20020a17090282c400b001bb1f0605b2sm1662638plz.214.2023.11.23.10.51.38 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 23 Nov 2023 10:51:40 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1700765501; x=1701370301; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=oNzK71ptVkzN8LH9oIEjdELKVkAXXjFWm0PQTwTkQA4=; b=AGGPtwcRuf5Wxs8kt5lYoLwO271cX7x1Iq+tTSg+vE9haOYAPN0zk/MHADc7uJlPsJ ix1neXHdzW7T5npVlDvMxKdKykFpp6UZSC+0UhaNKImk9BxMyRcvIOvgB7tUXWlCG40N 1LNwXFf+0+pMMS0pRvUSvIEJflLS1F9otqnMEUnje8F4ZzB2k2zscB58FZ3C6lUntKpX 51um8dXKpvIxZyny3krLmlFw6KPT4c54lsLcZsgCq02Lohrfqbk/t6ssQFyq+2I/CIyr Ioi6FajyzJ00zZ7/EWdDn1XcJ8mfoOKUbgNAMleBfGLVYngDHOJc5j4fTs38fMYsDGwb xImQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1700765501; x=1701370301; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=oNzK71ptVkzN8LH9oIEjdELKVkAXXjFWm0PQTwTkQA4=; b=iZoS1TikhFO5SCtuzlKBeFqwuZPduBsE6ZBs+GEcLj87tt84CYTfxpdOlC6c1XmbFe NYyVT7HZifp6n4fJFZMWuA4JPCHdGwqsJ/f+56NDDILCfF0wt0frbFxVCUXJao64PASm tBvHCAmTU/B2f3soXsa6BiG6WzTiL3GB7lBtY2wqgnD+4jhZJMOOSH+phNk4j7DWukxk 4j8qNWZ1qyBKAkhW8wIUF2Ru6KH/mkFgOb/mw105iADXCDKXl6ygMswoSdPVg4z4dkT+ BXBvMdrBQK+9GKU4++z0fnsLqDn69gCxxQrNGF9mtPSq37xjIGeseS1TFENTRJMnhkvo Xn7Q== X-Gm-Message-State: AOJu0YzAxwSwNAzUQGeEqGs1yyTPKxUeYpV+g12Ogqslv2TTWFu3gZhj Ia6uDyK0umYIgXyfdR5P1rhQsmG5Hvj/k01brdc= X-Google-Smtp-Source: AGHT+IEqj3i0DQVPPbh/6vlfhlmRPojSpwPCLvU9y0eUZQQ8mILooKYAB44Uiv9rIn5LvrSz/BUsLQ== X-Received: by 2002:a17:90b:3804:b0:280:fcba:bedd with SMTP id mq4-20020a17090b380400b00280fcbabeddmr291331pjb.48.1700765501027; Thu, 23 Nov 2023 10:51:41 -0800 (PST) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, bmeng@tinylab.org, liwei1518@gmail.com, zhiwei_liu@linux.alibaba.com, palmer@rivosinc.com, ajones@ventanamicro.com, Daniel Henrique Barboza Subject: [PATCH for-9.0 v11 04/18] target/riscv: add rv64i CPU Date: Thu, 23 Nov 2023 15:51:08 -0300 Message-ID: <20231123185122.1100436-5-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20231123185122.1100436-1-dbarboza@ventanamicro.com> References: <20231123185122.1100436-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::102d; envelope-from=dbarboza@ventanamicro.com; helo=mail-pj1-x102d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ventanamicro.com) X-ZM-MESSAGEID: 1700765581973100001 Content-Type: text/plain; charset="utf-8" We don't have any form of a 'bare bones' CPU. rv64, our default CPUs, comes with a lot of defaults. This is fine for most regular uses but it's not suitable when more control of what is actually loaded in the CPU is required. A bare-bones CPU would be annoying to deal with if not by profile support, a way to load a multitude of extensions with a single flag. Profile support is going to be implemented shortly, so let's add a CPU for it. The new 'rv64i' CPU will have only RVI loaded. It is inspired in the profile specification that dictates, for RVA22U64 [1]: "RVA22U64 Mandatory Base RV64I is the mandatory base ISA for RVA22U64" And so it seems that RV64I is the mandatory base ISA for all profiles listed in [1], making it an ideal CPU to use with profile support. rv64i is a CPU of type TYPE_RISCV_BARE_CPU. It has a mix of features from pre-existent CPUs: - it allows extensions to be enabled, like generic CPUs; - it will not inherit extension defaults, like vendor CPUs. This is the minimum extension set to boot OpenSBI and buildroot using rv64i: ./build/qemu-system-riscv64 -nographic -M virt \ -cpu rv64i,sv39=3Dtrue,g=3Dtrue,c=3Dtrue,s=3Dtrue,u=3Dtrue Our minimal riscv,isa in this case will be: # cat /proc/device-tree/cpus/cpu@0/riscv,isa rv64imafdc_zicntr_zicsr_zifencei_zihpm_zca_zcd# [1] https://github.com/riscv/riscv-profiles/blob/main/profiles.adoc Signed-off-by: Daniel Henrique Barboza Reviewed-by: Andrew Jones --- target/riscv/cpu-qom.h | 2 ++ target/riscv/cpu.c | 46 ++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 48 insertions(+) diff --git a/target/riscv/cpu-qom.h b/target/riscv/cpu-qom.h index ca7dd509e3..4d1aa54311 100644 --- a/target/riscv/cpu-qom.h +++ b/target/riscv/cpu-qom.h @@ -24,6 +24,7 @@ #define TYPE_RISCV_CPU "riscv-cpu" #define TYPE_RISCV_DYNAMIC_CPU "riscv-dynamic-cpu" #define TYPE_RISCV_VENDOR_CPU "riscv-vendor-cpu" +#define TYPE_RISCV_BARE_CPU "riscv-bare-cpu" =20 #define RISCV_CPU_TYPE_SUFFIX "-" TYPE_RISCV_CPU #define RISCV_CPU_TYPE_NAME(name) (name RISCV_CPU_TYPE_SUFFIX) @@ -33,6 +34,7 @@ #define TYPE_RISCV_CPU_BASE32 RISCV_CPU_TYPE_NAME("rv32") #define TYPE_RISCV_CPU_BASE64 RISCV_CPU_TYPE_NAME("rv64") #define TYPE_RISCV_CPU_BASE128 RISCV_CPU_TYPE_NAME("x-rv128") +#define TYPE_RISCV_CPU_RV64I RISCV_CPU_TYPE_NAME("rv64i") #define TYPE_RISCV_CPU_IBEX RISCV_CPU_TYPE_NAME("lowrisc-ibex") #define TYPE_RISCV_CPU_SHAKTI_C RISCV_CPU_TYPE_NAME("shakti-c") #define TYPE_RISCV_CPU_SIFIVE_E31 RISCV_CPU_TYPE_NAME("sifive-e31") diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 220113408e..a52bf1e33c 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -370,6 +370,17 @@ static void set_satp_mode_max_supported(RISCVCPU *cpu, /* Set the satp mode to the max supported */ static void set_satp_mode_default_map(RISCVCPU *cpu) { + /* + * Bare CPUs do not default to the max available. + * Users must set a valid satp_mode in the command + * line. + */ + if (object_dynamic_cast(OBJECT(cpu), TYPE_RISCV_BARE_CPU) !=3D NULL) { + warn_report("No satp mode set. Defaulting to 'bare'"); + cpu->cfg.satp_mode.map =3D (1 << VM_1_10_MBARE); + return; + } + cpu->cfg.satp_mode.map =3D cpu->cfg.satp_mode.supported; } #endif @@ -552,6 +563,28 @@ static void rv128_base_cpu_init(Object *obj) set_satp_mode_max_supported(RISCV_CPU(obj), VM_1_10_SV57); #endif } + +static void rv64i_bare_cpu_init(Object *obj) +{ + CPURISCVState *env =3D &RISCV_CPU(obj)->env; + riscv_cpu_set_misa(env, MXL_RV64, RVI); + + /* Remove the defaults from the parent class */ + RISCV_CPU(obj)->cfg.ext_zicntr =3D false; + RISCV_CPU(obj)->cfg.ext_zihpm =3D false; + + /* Set to QEMU's first supported priv version */ + env->priv_ver =3D PRIV_VERSION_1_10_0; + + /* + * Support all available satp_mode settings. The default + * value will be set to MBARE if the user doesn't set + * satp_mode manually (see set_satp_mode_default()). + */ +#ifndef CONFIG_USER_ONLY + set_satp_mode_max_supported(RISCV_CPU(obj), VM_1_10_SV64); +#endif +} #else static void rv32_base_cpu_init(Object *obj) { @@ -1785,6 +1818,13 @@ void riscv_cpu_list(void) .instance_init =3D initfn \ } =20 +#define DEFINE_BARE_CPU(type_name, initfn) \ + { \ + .name =3D type_name, \ + .parent =3D TYPE_RISCV_BARE_CPU, \ + .instance_init =3D initfn \ + } + static const TypeInfo riscv_cpu_type_infos[] =3D { { .name =3D TYPE_RISCV_CPU, @@ -1807,6 +1847,11 @@ static const TypeInfo riscv_cpu_type_infos[] =3D { .parent =3D TYPE_RISCV_CPU, .abstract =3D true, }, + { + .name =3D TYPE_RISCV_BARE_CPU, + .parent =3D TYPE_RISCV_CPU, + .abstract =3D true, + }, DEFINE_DYNAMIC_CPU(TYPE_RISCV_CPU_ANY, riscv_any_cpu_init), DEFINE_DYNAMIC_CPU(TYPE_RISCV_CPU_MAX, riscv_max_cpu_init), #if defined(TARGET_RISCV32) @@ -1823,6 +1868,7 @@ static const TypeInfo riscv_cpu_type_infos[] =3D { DEFINE_VENDOR_CPU(TYPE_RISCV_CPU_THEAD_C906, rv64_thead_c906_cpu_init= ), DEFINE_VENDOR_CPU(TYPE_RISCV_CPU_VEYRON_V1, rv64_veyron_v1_cpu_init), DEFINE_DYNAMIC_CPU(TYPE_RISCV_CPU_BASE128, rv128_base_cpu_init), + DEFINE_BARE_CPU(TYPE_RISCV_CPU_RV64I, rv64i_bare_cpu_init), #endif }; =20 --=20 2.41.0 From nobody Wed Nov 27 04:55:50 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1700765666; cv=none; d=zohomail.com; s=zohoarc; b=Nxl9cXYT3v8eHwwlNh2k3T3a7G/BaKxtsNkeU2TLxfu8/+/21WX34Zo7AueJvOHFZZbbbMUj5YYeR3EOOkiau6QC9A4F+I0j+yyr/6foFbTEfh5L9otkfk1uEDJvQPJKzdZVb7V1WQSVlQHHwJGVnN0deFLr21V4dw5MdIzM1kM= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1700765666; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=JDRclKp36HGTBfuGMgAcoAlDAO8icCS2R/NFUb3VCsA=; b=Keo8qt82QB7UJqZ6jJdgtXgoIbC5Ph6sI7951SQR6ZSYXxwpu3ndGhomgEh5MSkzjS4UoJC6oscZqg0rU8VCuIHunXoC5nWFIHN5B0QUAUYHSnULAFP+TA82UG/9YGPy4WF6um+49Oiy5M5wKWubE5+N3ifSv4A4GgaKb6lxOiU= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1700765665919592.8506819378636; Thu, 23 Nov 2023 10:54:25 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1r6EoE-0008Sa-Mu; Thu, 23 Nov 2023 13:52:18 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1r6Enu-0007zX-DO for qemu-devel@nongnu.org; Thu, 23 Nov 2023 13:51:59 -0500 Received: from mail-pl1-x62b.google.com ([2607:f8b0:4864:20::62b]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1r6Enl-0008I1-KL for qemu-devel@nongnu.org; Thu, 23 Nov 2023 13:51:53 -0500 Received: by mail-pl1-x62b.google.com with SMTP id d9443c01a7336-1cc9b626a96so8748235ad.2 for ; Thu, 23 Nov 2023 10:51:45 -0800 (PST) Received: from grind.. ([2804:7f0:bdcd:fb00:6501:2693:db52:c621]) by smtp.gmail.com with ESMTPSA id u4-20020a17090282c400b001bb1f0605b2sm1662638plz.214.2023.11.23.10.51.41 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 23 Nov 2023 10:51:43 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1700765504; x=1701370304; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=JDRclKp36HGTBfuGMgAcoAlDAO8icCS2R/NFUb3VCsA=; b=iaz7HrtpbC4pSfUKemiLn1r//U/OSWmcHxJylhFKsWy5ZwCZ6P/EiRPM6OhFP6KaCX FSYpxXh5Mwv0oqDk/Z7Juskj47sAbTvbw40QiVk9257k/SlLkqyAdArTVwKZOa17lDac tkKmw5OyI3GrTPVu2vTjmMjDQi5dfSNIFX10bjFixNhFPWTenrQjr1jjeSfNiu3sSFJ0 RXTzW4zth5arxVIAVc26W5CzU7LIqBhmwyyz4iVOmxDInNqnwBmEKMEp0uF6jb/pv8UB Y3oN9e7tJzJnles0wXejMjR6OBm5g8sL/g0ZCv5jqkn8a1KptXFCKcRufDe4AhQcmj5e 9kEw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1700765504; x=1701370304; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=JDRclKp36HGTBfuGMgAcoAlDAO8icCS2R/NFUb3VCsA=; b=dXc7pl+tGGrRHSpzHbhkro/1mnxu9z6V+r5zpLKLu/2Zfq5O+bZrWILW0zjy641RsO tYgc0xF6Zi+DVZPAht5CMV0FJV6wX/4BfQ3KO7k+Bt4z+jvfSlNbrEgU0VlqMMBh2aCH rCr9OSGvalL1zAymPsxed9LWOiiHOgkKAL4lZ0R6I2hrmsVF0woLquLfwq0gfiMz99HH rYWCskyDB32TmD8ZFJrj09bplVHTUyfnNz9dD7AwKMyOSMQ1ngJZTr/np9NzpP19Di53 LyGDK896tV8pFFMj/YB9payEB+Vb123LAnHJU/fasir2llcToUqd2L2AgeLfnC6RmUgA zsDQ== X-Gm-Message-State: AOJu0YwM7beDD9Jd3FZ2MFTsKDiJ8MrMqchrG1wIy6zBGI0ky9doTwmw ogpDtYabyjH3/Fk4GxEGjUxVDUuSApff2njulis= X-Google-Smtp-Source: AGHT+IGa4ACqGZVvJX2sCtJKGiiZwChQfFjumyimEIMRtW8QrvPGbXE6uw7Rew+1JKOB03fieHllLw== X-Received: by 2002:a17:902:c146:b0:1cc:449b:41e3 with SMTP id 6-20020a170902c14600b001cc449b41e3mr304954plj.59.1700765504060; Thu, 23 Nov 2023 10:51:44 -0800 (PST) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, bmeng@tinylab.org, liwei1518@gmail.com, zhiwei_liu@linux.alibaba.com, palmer@rivosinc.com, ajones@ventanamicro.com, Daniel Henrique Barboza Subject: [PATCH for-9.0 v11 05/18] target/riscv: add zicbop extension flag Date: Thu, 23 Nov 2023 15:51:09 -0300 Message-ID: <20231123185122.1100436-6-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20231123185122.1100436-1-dbarboza@ventanamicro.com> References: <20231123185122.1100436-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::62b; envelope-from=dbarboza@ventanamicro.com; helo=mail-pl1-x62b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ventanamicro.com) X-ZM-MESSAGEID: 1700765667925100013 Content-Type: text/plain; charset="utf-8" QEMU already implements zicbom (Cache Block Management Operations) and zicboz (Cache Block Zero Operations). Commit 59cb29d6a5 ("target/riscv: add Zicbop cbo.prefetch{i, r, m} placeholder") added placeholders for what would be the instructions for zicbop (Cache Block Prefetch Operations), which are now no-ops. The RVA22U64 profile mandates zicbop, which means that applications that run with this profile might expect zicbop to be present in the riscv,isa DT and might behave badly if it's absent. Adding zicbop as an extension will make our future RVA22U64 implementation more in line with what userspace expects and, if/when cache block prefetch operations became relevant to QEMU, we already have the extension flag to turn then on/off as needed. Signed-off-by: Daniel Henrique Barboza Reviewed-by: Andrew Jones --- hw/riscv/virt.c | 5 +++++ target/riscv/cpu.c | 3 +++ target/riscv/cpu_cfg.h | 2 ++ 3 files changed, 10 insertions(+) diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c index d2eac24156..da650865e5 100644 --- a/hw/riscv/virt.c +++ b/hw/riscv/virt.c @@ -273,6 +273,11 @@ static void create_fdt_socket_cpus(RISCVVirtState *s, = int socket, cpu_ptr->cfg.cboz_blocksize); } =20 + if (cpu_ptr->cfg.ext_zicbop) { + qemu_fdt_setprop_cell(ms->fdt, cpu_name, "riscv,cbop-block-siz= e", + cpu_ptr->cfg.cbop_blocksize); + } + qemu_fdt_setprop_string(ms->fdt, cpu_name, "compatible", "riscv"); qemu_fdt_setprop_string(ms->fdt, cpu_name, "status", "okay"); qemu_fdt_setprop_cell(ms->fdt, cpu_name, "reg", diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index a52bf1e33c..40c64581ec 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -78,6 +78,7 @@ const uint32_t misa_bits[] =3D {RVI, RVE, RVM, RVA, RVF, = RVD, RVV, */ const RISCVIsaExtData isa_edata_arr[] =3D { ISA_EXT_DATA_ENTRY(zicbom, PRIV_VERSION_1_12_0, ext_zicbom), + ISA_EXT_DATA_ENTRY(zicbop, PRIV_VERSION_1_12_0, ext_zicbop), ISA_EXT_DATA_ENTRY(zicboz, PRIV_VERSION_1_12_0, ext_zicboz), ISA_EXT_DATA_ENTRY(zicond, PRIV_VERSION_1_12_0, ext_zicond), ISA_EXT_DATA_ENTRY(zicntr, PRIV_VERSION_1_12_0, ext_zicntr), @@ -1376,6 +1377,7 @@ const RISCVCPUMultiExtConfig riscv_cpu_extensions[] = =3D { MULTI_EXT_CFG_BOOL("zhinxmin", ext_zhinxmin, false), =20 MULTI_EXT_CFG_BOOL("zicbom", ext_zicbom, true), + MULTI_EXT_CFG_BOOL("zicbop", ext_zicbop, true), MULTI_EXT_CFG_BOOL("zicboz", ext_zicboz, true), =20 MULTI_EXT_CFG_BOOL("zmmul", ext_zmmul, false), @@ -1510,6 +1512,7 @@ Property riscv_cpu_options[] =3D { DEFINE_PROP_UINT16("elen", RISCVCPU, cfg.elen, 64), =20 DEFINE_PROP_UINT16("cbom_blocksize", RISCVCPU, cfg.cbom_blocksize, 64), + DEFINE_PROP_UINT16("cbop_blocksize", RISCVCPU, cfg.cbop_blocksize, 64), DEFINE_PROP_UINT16("cboz_blocksize", RISCVCPU, cfg.cboz_blocksize, 64), =20 DEFINE_PROP_END_OF_LIST(), diff --git a/target/riscv/cpu_cfg.h b/target/riscv/cpu_cfg.h index f4605fb190..bd2ff87cc8 100644 --- a/target/riscv/cpu_cfg.h +++ b/target/riscv/cpu_cfg.h @@ -65,6 +65,7 @@ struct RISCVCPUConfig { bool ext_zicntr; bool ext_zicsr; bool ext_zicbom; + bool ext_zicbop; bool ext_zicboz; bool ext_zicond; bool ext_zihintntl; @@ -142,6 +143,7 @@ struct RISCVCPUConfig { uint16_t vlen; uint16_t elen; uint16_t cbom_blocksize; + uint16_t cbop_blocksize; uint16_t cboz_blocksize; bool mmu; bool pmp; --=20 2.41.0 From nobody Wed Nov 27 04:55:50 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1700765641; cv=none; d=zohomail.com; s=zohoarc; b=lAW8x0RlPdKkhFecyVfQdc8eGoDyBpKTRIam2S20uywzB3AilumCNJVOkVuDy6ThQJrBhyxUF+zJEKt97SZlCzJSU+dxQPGUNC0+93P1dIIwlSjuNkt2nzacFaP0AH3Sov38eocph/Mb9JQhkOwOfGXz/DYruIEL0Jm66adRjPg= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1700765641; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=i3asFkCX44dbueHLeyC5ZhzKDVitot3MIedZa9BHV1o=; b=Km7J4gK0IebFgyONSFi8JFzhJkJF6qTX1a/rlnO0V78ZhbKL4+LF928pWwny2ZfOM23ZtNDC1UxzOw6PpFC3hDlg4XrItVhCujTXZf7x0EJbiFnM7spQS7GAx+/kMMbU7wttvIBpgzu0fVYc3yjajuZMCV3DM1YfmB3uFS0EEBc= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1700765641202181.92168473362176; Thu, 23 Nov 2023 10:54:01 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1r6Enz-00085P-JY; Thu, 23 Nov 2023 13:52:03 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1r6Env-0007zc-1k for qemu-devel@nongnu.org; Thu, 23 Nov 2023 13:51:59 -0500 Received: from mail-pl1-x631.google.com ([2607:f8b0:4864:20::631]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1r6Enl-0008IV-LK for qemu-devel@nongnu.org; Thu, 23 Nov 2023 13:51:53 -0500 Received: by mail-pl1-x631.google.com with SMTP id d9443c01a7336-1cf897c8de1so7821615ad.0 for ; Thu, 23 Nov 2023 10:51:49 -0800 (PST) Received: from grind.. ([2804:7f0:bdcd:fb00:6501:2693:db52:c621]) by smtp.gmail.com with ESMTPSA id u4-20020a17090282c400b001bb1f0605b2sm1662638plz.214.2023.11.23.10.51.44 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 23 Nov 2023 10:51:46 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1700765507; x=1701370307; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=i3asFkCX44dbueHLeyC5ZhzKDVitot3MIedZa9BHV1o=; b=HF01N+cJsvaYdDOmDSeeVGF18xfxjIXzUxhyVKOdUS7l7HwjEggcW916RdrhK0k3+c Q9CG8NMxzGN7viKzFoa8pZJMPvmRn54Nnd7XyAWn09hrXJb1KuSTxrsapmjrUg6kLHJR h+5CpEci6yCtCVEsQLcVRMP+caJMdiiItxCDInU8jJoU/+frQn4gaO0AcpoWwXLNRN+L 11ZVCZ1MZ+R24dvh1TpyY3rud+2UqXmWtvj8/YCSj3z2dDO4I7NhjK833cYpA66j61PY av9h+Pz2M8QHiGLF/pE9zozEmfzhDOf84sY+1t/XFMW9V8TqmP1aFVYJ6nbbFxvfAda1 LsPQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1700765507; x=1701370307; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=i3asFkCX44dbueHLeyC5ZhzKDVitot3MIedZa9BHV1o=; b=rrTX04zp+BLj2iKnwPeiDOwE9qslV3Upc3sdOyHz/URJMfwUmrObMO80NNsa6lK/9l Q9UjkFvSH6VLfBQSidSvKXUL5Uns9KfYJRjhI8bshhKx9WYx0v2X1Z9y/BVyDT7AoX+s QQrXMl0hMZ4l/Xz5XPqIFncIEKwPvbA8jx7tn0KMe6ovjKXJvQwtbilflFAXMwVRWSCJ 9AuXvE46LBGL3t/QfRHL4F4PI1l7kSlSd9B/yIFBdhulNglgT277CclT/MMJPK6GSdFh 3sDRs04JFme1SgvPWz7UStUtMb62KrL47g4ggOF77WXBdMObW3RSQ5HSr4SQcheW/+2z eD3A== X-Gm-Message-State: AOJu0YyYcHpJ9kBpthXR7PU0VH76QFlMI9ZcZXYLPOI/lErpRCVDKXOB Bfwb9Rue4pNHPBOHaOr51/aw22gPbtgF8TVaWkg= X-Google-Smtp-Source: AGHT+IGQKNaqcaiZMQfmtwuuOcm5/CsE8UoufuM4r0YqiTH3teG2ccmXxWhCQErzugSEdayymjVudQ== X-Received: by 2002:a17:903:244e:b0:1ce:1892:2fa6 with SMTP id l14-20020a170903244e00b001ce18922fa6mr456527pls.0.1700765507359; Thu, 23 Nov 2023 10:51:47 -0800 (PST) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, bmeng@tinylab.org, liwei1518@gmail.com, zhiwei_liu@linux.alibaba.com, palmer@rivosinc.com, ajones@ventanamicro.com, Daniel Henrique Barboza Subject: [PATCH for-9.0 v11 06/18] target/riscv/tcg: add 'zic64b' support Date: Thu, 23 Nov 2023 15:51:10 -0300 Message-ID: <20231123185122.1100436-7-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20231123185122.1100436-1-dbarboza@ventanamicro.com> References: <20231123185122.1100436-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::631; envelope-from=dbarboza@ventanamicro.com; helo=mail-pl1-x631.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ventanamicro.com) X-ZM-MESSAGEID: 1700765641808100006 Content-Type: text/plain; charset="utf-8" zic64b is defined in the RVA22U64 profile [1] as a named feature for "Cache blocks must be 64 bytes in size, naturally aligned in the address space". It's a fantasy name for 64 bytes cache blocks. The RVA22U64 profile mandates this feature, meaning that applications using this profile expects 64 bytes cache blocks. To make the upcoming RVA22U64 implementation complete, we'll zic64b as a 'named feature', not a regular extension. This means that: - it won't be exposed to users; - it won't be written in riscv,isa. This will be extended to other named extensions in the future, so we're creating some common boilerplate for them as well. zic64b is default to 'true' since we're already using 64 bytes blocks. If any cache block size (cbo{m,p,z}_blocksize) is changed to something different than 64, zic64b is set to 'false'. Our profile implementation will then be able to check the current state of zic64b and take the appropriate action (e.g. throw a warning). [1] https://github.com/riscv/riscv-profiles/releases/download/v1.0/profiles= .pdf Signed-off-by: Daniel Henrique Barboza Reviewed-by: Andrew Jones --- target/riscv/cpu.c | 6 ++++++ target/riscv/cpu.h | 1 + target/riscv/cpu_cfg.h | 1 + target/riscv/tcg/tcg-cpu.c | 31 +++++++++++++++++++++++++++++++ 4 files changed, 39 insertions(+) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 40c64581ec..8841052290 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -1444,6 +1444,12 @@ const RISCVCPUMultiExtConfig riscv_cpu_experimental_= exts[] =3D { DEFINE_PROP_END_OF_LIST(), }; =20 +const RISCVCPUMultiExtConfig riscv_cpu_named_features[] =3D { + MULTI_EXT_CFG_BOOL("zic64b", zic64b, true), + + DEFINE_PROP_END_OF_LIST(), +}; + /* Deprecated entries marked for future removal */ const RISCVCPUMultiExtConfig riscv_cpu_deprecated_exts[] =3D { MULTI_EXT_CFG_BOOL("Zifencei", ext_zifencei, true), diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index d74b361be6..5fb4ca2324 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -767,6 +767,7 @@ typedef struct RISCVCPUMultiExtConfig { extern const RISCVCPUMultiExtConfig riscv_cpu_extensions[]; extern const RISCVCPUMultiExtConfig riscv_cpu_vendor_exts[]; extern const RISCVCPUMultiExtConfig riscv_cpu_experimental_exts[]; +extern const RISCVCPUMultiExtConfig riscv_cpu_named_features[]; extern const RISCVCPUMultiExtConfig riscv_cpu_deprecated_exts[]; extern Property riscv_cpu_options[]; =20 diff --git a/target/riscv/cpu_cfg.h b/target/riscv/cpu_cfg.h index bd2ff87cc8..90f18eb601 100644 --- a/target/riscv/cpu_cfg.h +++ b/target/riscv/cpu_cfg.h @@ -116,6 +116,7 @@ struct RISCVCPUConfig { bool ext_smepmp; bool rvv_ta_all_1s; bool rvv_ma_all_1s; + bool zic64b; =20 uint32_t mvendorid; uint64_t marchid; diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c index d279314624..68577da8a8 100644 --- a/target/riscv/tcg/tcg-cpu.c +++ b/target/riscv/tcg/tcg-cpu.c @@ -114,6 +114,19 @@ static int cpu_cfg_ext_get_min_version(uint32_t ext_of= fset) g_assert_not_reached(); } =20 +static bool cpu_cfg_offset_is_named_feat(uint32_t ext_offset) +{ + const RISCVCPUMultiExtConfig *feat; + + for (feat =3D riscv_cpu_named_features; feat->name !=3D NULL; feat++) { + if (feat->offset =3D=3D ext_offset) { + return true; + } + } + + return false; +} + static void cpu_validate_multi_ext_priv_ver(CPURISCVState *env, uint32_t ext_offset) { @@ -123,6 +136,10 @@ static void cpu_validate_multi_ext_priv_ver(CPURISCVSt= ate *env, return; } =20 + if (cpu_cfg_offset_is_named_feat(ext_offset)) { + return; + } + ext_priv_ver =3D cpu_cfg_ext_get_min_version(ext_offset); =20 if (env->priv_ver < ext_priv_ver) { @@ -293,6 +310,18 @@ static void riscv_cpu_disable_priv_spec_isa_exts(RISCV= CPU *cpu) } } =20 +static void riscv_cpu_validate_zic64b(RISCVCPU *cpu) +{ + cpu->cfg.zic64b =3D cpu->cfg.cbom_blocksize =3D=3D 64 && + cpu->cfg.cbop_blocksize =3D=3D 64 && + cpu->cfg.cboz_blocksize =3D=3D 64; +} + +static void riscv_cpu_validate_named_features(RISCVCPU *cpu) +{ + riscv_cpu_validate_zic64b(cpu); +} + /* * Check consistency between chosen extensions while setting * cpu->cfg accordingly. @@ -657,6 +686,8 @@ void riscv_tcg_cpu_finalize_features(RISCVCPU *cpu, Err= or **errp) return; } =20 + riscv_cpu_validate_named_features(cpu); + if (cpu->cfg.ext_smepmp && !cpu->cfg.pmp) { /* * Enhanced PMP should only be available --=20 2.41.0 From nobody Wed Nov 27 04:55:50 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1700765667; cv=none; d=zohomail.com; s=zohoarc; b=I+a+ZBN9jdSfSKR6SjqBB09SThwRp28ldSGj4QQfh9baGiSGqg1Ia21BzpXfcVx9BbI8L9lZgDRKWGS2vbm3niSsWshP8BkK9qgXXQlRezyZOULDdBvk32zdMAhBLeSDRIcONn09aAOUpvXp7K7yOvJfuv28qMIvzR+WEGGZqcs= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1700765667; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; 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([2804:7f0:bdcd:fb00:6501:2693:db52:c621]) by smtp.gmail.com with ESMTPSA id u4-20020a17090282c400b001bb1f0605b2sm1662638plz.214.2023.11.23.10.51.47 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 23 Nov 2023 10:51:49 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1700765510; x=1701370310; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=W9vkQpTeB3ayrchqiqPL77Nx2STXCsE/ldIKYWZcyJE=; b=gg1A1MyVEsYo0D0ylRy/dp4NVFrEY9jGsY8y/0lTCnKIX/9o+y1EMdnvdAzNaQ/jXS hrWHq5OeghjdVX61glRT7boplksDjy2LLzkqnPIMYL6FN7w4IUhkS1d9vYj03eIqrD59 gv/ysXjpqoTO+zPzohm+bFC4mJQMM3FmHG4AS/2tNH6rp3LvjxM8Pxrn52Z71B6moP0u qYTj4Lg54nY3cocujqxvcae016fPA6KnSmA1sfJkk2ck9vqhT8lWqGJYVIXNjBK5ZZAX zL5mAa4mhuZdoJ2rd2QOmPk/RFaA2SPJ+7PDwCjc28HGvwqaqIc9mD4J2JkJSqqnT0KR kyvg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1700765510; x=1701370310; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=W9vkQpTeB3ayrchqiqPL77Nx2STXCsE/ldIKYWZcyJE=; b=dYslabcQZgCs4ie2PATmF9WDW2ew1fOcBq6/uGQe2J4TOgvKbifVQNdttMqx1kDZtV 3CXKYsybxLK/rf4fAEJ1Rth0AVU+k9aFYPSQOMHi8UUY4QakpSomkz2xbRQkb0t3evgx to6TQdGLogO9uI48BlpaxLPzXCXNVqwYcDK7EmbaR7XfSNX/vA3mXu4qiLDtHMUj94JE 3VJaHkrEE0P/7FypkP1Dl8NPBLDrffXsQ5H+2+677k+Q6YmeARLoS/ZnnKz1fDKq/iH4 wJir83HF51ulVmfLyvnrN4VW8DB0t7/iVuDBpc0nOOQjx9HJxJi2axJWKEbfkY4c6+QQ zj4w== X-Gm-Message-State: AOJu0YwwVfzhBaVZAQRQKqsKcY4z6dYlIfpksHnvMZ6QKiqwNy8/+0Yi 2m6fmC7Dfn2OqorqQjS/YV3ktEs88ByZ2nePK8g= X-Google-Smtp-Source: AGHT+IEiRRefrBm3YIesBGeWx/coaZSozIBmzmcrdl+447E0eFxmNSnOe56B/FI10odx+ghHp9pbvw== X-Received: by 2002:a17:902:eac5:b0:1cf:642a:914a with SMTP id p5-20020a170902eac500b001cf642a914amr400125pld.15.1700765510326; Thu, 23 Nov 2023 10:51:50 -0800 (PST) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, bmeng@tinylab.org, liwei1518@gmail.com, zhiwei_liu@linux.alibaba.com, palmer@rivosinc.com, ajones@ventanamicro.com, Daniel Henrique Barboza Subject: [PATCH for-9.0 v11 07/18] riscv-qmp-cmds.c: expose named features in cpu_model_expansion Date: Thu, 23 Nov 2023 15:51:11 -0300 Message-ID: <20231123185122.1100436-8-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20231123185122.1100436-1-dbarboza@ventanamicro.com> References: <20231123185122.1100436-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::632; envelope-from=dbarboza@ventanamicro.com; helo=mail-pl1-x632.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ventanamicro.com) X-ZM-MESSAGEID: 1700765669921100019 Content-Type: text/plain; charset="utf-8" Named features (zic64b the sole example at this moment) aren't expose to users, thus we need another way to expose them. Go through each named feature, get its boolean value, do the needed conversions (bool to qbool, qbool to QObject) and add it to output dict. Another adjustment is needed: named features are evaluated during finalize(), so riscv_cpu_finalize_features() needs to be mandatory regardless of whether we have an input dict or not. Otherwise zic64b will always return 'false', which is incorrect: the default values of cache blocksizes ([cbom/cbop/cboz]_blocksize) are set to 64, satisfying the conditions for zic64b. Here's an API usage example after this patch: $ ./build/qemu-system-riscv64 -S -M virt -display none -qmp tcp:localhost:1234,server,wait=3Doff $ ./scripts/qmp/qmp-shell localhost:1234 Welcome to the QMP low-level shell! Connected to QEMU 8.1.50 (QEMU) query-cpu-model-expansion type=3Dfull model=3D{"name":"rv64"} {"return": {"model": {"name": "rv64", "props": {... "zic64b": true, ...}}}} zic64b is set to 'true', as expected, since all cache sizes are 64 bytes by default. If we change one of the cache blocksizes, zic64b is returned as 'false': (QEMU) query-cpu-model-expansion type=3Dfull model=3D{"name":"rv64","props"= :{"cbom_blocksize":128}} {"return": {"model": {"name": "rv64", "props": {... "zic64b": false, ...}}}} Signed-off-by: Daniel Henrique Barboza Reviewed-by: Andrew Jones --- target/riscv/riscv-qmp-cmds.c | 30 +++++++++++++++++++++++++----- 1 file changed, 25 insertions(+), 5 deletions(-) diff --git a/target/riscv/riscv-qmp-cmds.c b/target/riscv/riscv-qmp-cmds.c index 2f2dbae7c8..5ada279776 100644 --- a/target/riscv/riscv-qmp-cmds.c +++ b/target/riscv/riscv-qmp-cmds.c @@ -26,6 +26,7 @@ =20 #include "qapi/error.h" #include "qapi/qapi-commands-machine-target.h" +#include "qapi/qmp/qbool.h" #include "qapi/qmp/qdict.h" #include "qapi/qmp/qerror.h" #include "qapi/qobject-input-visitor.h" @@ -99,6 +100,22 @@ static void riscv_obj_add_multiext_props(Object *obj, Q= Dict *qdict_out, } } =20 +static void riscv_obj_add_named_feats_qdict(Object *obj, QDict *qdict_out) +{ + const RISCVCPUMultiExtConfig *named_cfg; + RISCVCPU *cpu =3D RISCV_CPU(obj); + QObject *value; + bool flag_val; + + for (int i =3D 0; riscv_cpu_named_features[i].name !=3D NULL; i++) { + named_cfg =3D &riscv_cpu_named_features[i]; + flag_val =3D isa_ext_is_enabled(cpu, named_cfg->offset); + value =3D QOBJECT(qbool_from_bool(flag_val)); + + qdict_put_obj(qdict_out, named_cfg->name, value); + } +} + static void riscv_cpuobj_validate_qdict_in(Object *obj, QObject *props, const QDict *qdict_in, Error **errp) @@ -129,11 +146,6 @@ static void riscv_cpuobj_validate_qdict_in(Object *obj= , QObject *props, goto err; } =20 - riscv_cpu_finalize_features(RISCV_CPU(obj), &local_err); - if (local_err) { - goto err; - } - visit_end_struct(visitor, NULL); =20 err: @@ -191,6 +203,13 @@ CpuModelExpansionInfo *qmp_query_cpu_model_expansion(C= puModelExpansionType type, } } =20 + riscv_cpu_finalize_features(RISCV_CPU(obj), &local_err); + if (local_err) { + error_propagate(errp, local_err); + object_unref(obj); + return NULL; + } + expansion_info =3D g_new0(CpuModelExpansionInfo, 1); expansion_info->model =3D g_malloc0(sizeof(*expansion_info->model)); expansion_info->model->name =3D g_strdup(model->name); @@ -200,6 +219,7 @@ CpuModelExpansionInfo *qmp_query_cpu_model_expansion(Cp= uModelExpansionType type, riscv_obj_add_multiext_props(obj, qdict_out, riscv_cpu_extensions); riscv_obj_add_multiext_props(obj, qdict_out, riscv_cpu_experimental_ex= ts); riscv_obj_add_multiext_props(obj, qdict_out, riscv_cpu_vendor_exts); + riscv_obj_add_named_feats_qdict(obj, qdict_out); =20 /* Add our CPU boolean options too */ riscv_obj_add_qdict_prop(obj, qdict_out, "mmu"); --=20 2.41.0 From nobody Wed Nov 27 04:55:50 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1700765606; cv=none; d=zohomail.com; s=zohoarc; b=E+g65NUicxg/dUujuKwcLEBSARoBo3wlNSBSa5sbFom43o7Co8KREQM2BM1kUAuOyDPMYMR4Z47c1NPDuCnmQ3nbkPpFrKr8pMp6EMkzzvhAFO23no4J27qLrupVb3A+UtSH3jzRzxqlfr+6xtFYobkI8QOlvll+jv9hyVmjuI8= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1700765606; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=pbNxLYOyAxv1Zp/nW5Ak7yeVc804Q40HQaCIKzw/tb8=; b=h6ngKUbk3b4151KzLMwt62+iKZhrkH0Uk/e5CxFH6aJt0PCwqokawxmFVHAVSJwjNCvOi+UxcZ1GSGZ9ChN20JrReMUHToc43mkKqIrWfCru7MeF07NMkE1wdyCF9NpY3p96I/ho53aTwbc0noNS+5NtjFHLhviAMQFarSpSFVE= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1700765605901732.596800869178; Thu, 23 Nov 2023 10:53:25 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1r6EoC-0008Nc-TE; Thu, 23 Nov 2023 13:52:16 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1r6Eo0-00086t-2D for qemu-devel@nongnu.org; Thu, 23 Nov 2023 13:52:07 -0500 Received: from mail-pl1-x62f.google.com ([2607:f8b0:4864:20::62f]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1r6Enw-0008K3-Kz for qemu-devel@nongnu.org; Thu, 23 Nov 2023 13:52:03 -0500 Received: by mail-pl1-x62f.google.com with SMTP id d9443c01a7336-1cc2575dfc7so8869605ad.1 for ; Thu, 23 Nov 2023 10:51:55 -0800 (PST) Received: from grind.. ([2804:7f0:bdcd:fb00:6501:2693:db52:c621]) by smtp.gmail.com with ESMTPSA id u4-20020a17090282c400b001bb1f0605b2sm1662638plz.214.2023.11.23.10.51.50 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 23 Nov 2023 10:51:53 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1700765513; x=1701370313; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=pbNxLYOyAxv1Zp/nW5Ak7yeVc804Q40HQaCIKzw/tb8=; b=nu7TJgkL4inl7j5JNLbjdafBt5NuvSbdik4fkGEcPAdVoZ7KloGCyoJCbkB+n0t8f5 AJRMCL0UL6/16ZKwJYdiDkkGJnpitB+VzDgCfbOg2ytmwgLbN4/QCZlKMuoMdFiQ66PC ZkpH2R9vsj5DuQdW7ThesLZYigwD+IouWsn9jq7F4U6HMxcC9vqkvyc8vGyw9/Jot91p nsku9Opj/NmPIg1+Z35kgKchm1I+VWwvptrnKzBQRw57/mVDAm1n5Kc0Xiut+t0MvvDu 94h46Qhsbk9iTrLV2xTn3bjr4e+cv1TZLqWeJeSJmDDlcPjBPzxLFvIV/4CwDvDqnmbS f7Aw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1700765513; x=1701370313; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=pbNxLYOyAxv1Zp/nW5Ak7yeVc804Q40HQaCIKzw/tb8=; b=BtoL4X7lSbk3rIkojdWVvb6VzUhwgqBEC1jjKWVqMcubDy9Gm87tYb8RKIx9a8SUCr 4+mxlOrSu5JYEFlfyVNddaeti52r8uRXG/35uF7SNJ3UHGg5mExygPaZCLTX4LKTfgyL /GY9KwjGZu4Okgjp/TRgYwS7hUsGyrIUxrGN9lBlEFCzHNL9KRr+oVZq/EueVrpWMh2n +fiWZe3BMr4dXtxnh6xjYd2x0VRcQx6smaHUogKAVyFx35sUGJGblAdLIsXlvE3mdaEe pv/vP3NgUCwjdxPiAE21/joLR+ZOH5tZzsthpRdYtxP+tt/5y+T5CeeC3219CzO7I/kK BjNA== X-Gm-Message-State: AOJu0YyjQkHA4fWw8kuszJj1HkBjIdxDqouISAtRy4UkIwZ9zUX+zkRr 7DVAVlR29sFtr4Hsf0dAHgUFE1FkE6ldX0niLiU= X-Google-Smtp-Source: AGHT+IHQWScj0z/CmcouKdVLsd19iq67aYSWNvj0WPPSEguAP64/gcFhYYhKdKF6tUG+i8IdMPGB/w== X-Received: by 2002:a17:903:246:b0:1c5:d063:b70e with SMTP id j6-20020a170903024600b001c5d063b70emr283164plh.53.1700765513416; Thu, 23 Nov 2023 10:51:53 -0800 (PST) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, bmeng@tinylab.org, liwei1518@gmail.com, zhiwei_liu@linux.alibaba.com, palmer@rivosinc.com, ajones@ventanamicro.com, Daniel Henrique Barboza Subject: [PATCH for-9.0 v11 08/18] target/riscv: add rva22u64 profile definition Date: Thu, 23 Nov 2023 15:51:12 -0300 Message-ID: <20231123185122.1100436-9-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20231123185122.1100436-1-dbarboza@ventanamicro.com> References: <20231123185122.1100436-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::62f; envelope-from=dbarboza@ventanamicro.com; helo=mail-pl1-x62f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ventanamicro.com) X-ZM-MESSAGEID: 1700765607612100003 Content-Type: text/plain; charset="utf-8" The rva22U64 profile, described in: https://github.com/riscv/riscv-profiles/blob/main/profiles.adoc#rva22-profi= les Contains a set of CPU extensions aimed for 64-bit userspace applications. Enabling this set to be enabled via a single user flag makes it convenient to enable a predictable set of features for the CPU, giving users more predicability when running/testing their workloads. QEMU implements all possible extensions of this profile. All the so called 'synthetic extensions' described in the profile that are cache related are ignored/assumed enabled (Za64rs, Zic64b, Ziccif, Ziccrse, Ziccamoa, Zicclsm) since we do not implement a cache model. An abstraction called RISCVCPUProfile is created to store the profile. 'ext_offsets' contains mandatory extensions that QEMU supports. Same thing with the 'misa_ext' mask. Optional extensions must be enabled manually in the command line if desired. The design here is to use the common target/riscv/cpu.c file to store the profile declaration and export it to the accelerator files. Each accelerator is then responsible to expose it (or not) to users and how to enable the extensions. Next patches will implement the profile for TCG and KVM. Signed-off-by: Daniel Henrique Barboza Acked-by: Alistair Francis Reviewed-by: Andrew Jones --- target/riscv/cpu.c | 32 ++++++++++++++++++++++++++++++++ target/riscv/cpu.h | 12 ++++++++++++ 2 files changed, 44 insertions(+) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 8841052290..f2be40ae21 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -1524,6 +1524,38 @@ Property riscv_cpu_options[] =3D { DEFINE_PROP_END_OF_LIST(), }; =20 +/* + * RVA22U64 defines some 'named features' or 'synthetic extensions' + * that are cache related: Za64rs, Zic64b, Ziccif, Ziccrse, Ziccamoa + * and Zicclsm. We do not implement caching in QEMU so we'll consider + * all these named features as always enabled. + * + * There's no riscv,isa update for them (nor for zic64b, despite it + * having a cfg offset) at this moment. + */ +static RISCVCPUProfile RVA22U64 =3D { + .name =3D "rva22u64", + .misa_ext =3D RVI | RVM | RVA | RVF | RVD | RVC | RVU, + .ext_offsets =3D { + CPU_CFG_OFFSET(ext_zicsr), CPU_CFG_OFFSET(ext_zihintpause), + CPU_CFG_OFFSET(ext_zba), CPU_CFG_OFFSET(ext_zbb), + CPU_CFG_OFFSET(ext_zbs), CPU_CFG_OFFSET(ext_zfhmin), + CPU_CFG_OFFSET(ext_zkt), CPU_CFG_OFFSET(ext_zicntr), + CPU_CFG_OFFSET(ext_zihpm), CPU_CFG_OFFSET(ext_zicbom), + CPU_CFG_OFFSET(ext_zicbop), CPU_CFG_OFFSET(ext_zicboz), + + /* mandatory named features for this profile */ + CPU_CFG_OFFSET(zic64b), + + RISCV_PROFILE_EXT_LIST_END + } +}; + +RISCVCPUProfile *riscv_profiles[] =3D { + &RVA22U64, + NULL, +}; + static Property riscv_cpu_properties[] =3D { DEFINE_PROP_BOOL("debug", RISCVCPU, cfg.debug, true), =20 diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 5fb4ca2324..5ff629650d 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -76,6 +76,18 @@ const char *riscv_get_misa_ext_description(uint32_t bit); =20 #define CPU_CFG_OFFSET(_prop) offsetof(struct RISCVCPUConfig, _prop) =20 +typedef struct riscv_cpu_profile { + const char *name; + uint32_t misa_ext; + bool enabled; + bool user_set; + const int32_t ext_offsets[]; +} RISCVCPUProfile; + +#define RISCV_PROFILE_EXT_LIST_END -1 + +extern RISCVCPUProfile *riscv_profiles[]; + /* Privileged specification version */ enum { PRIV_VERSION_1_10_0 =3D 0, --=20 2.41.0 From nobody Wed Nov 27 04:55:50 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1700765671; cv=none; d=zohomail.com; s=zohoarc; b=CMqFZWVlP3qA/URBpDIxtnLXLk2GAArd2lDvxiQ06D8ye49dzrNWj/QbxqabYJNNVuKN5x9sgxMEK02CqriWHU9qs73/vmsxio8K7FnaZBggZ6PdzHbG3YWiI6MizASD16U/tkwT15jVRS7U1qgPsflyWlUrq7xHxU83ZMjlsdo= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1700765671; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=idOjzqB/2N8r45g3xvXzJsWeC0Y1TlRo66OPhQFDTfY=; b=ZCmtfS9jr0fTCiqN/x/BNgD44Zb5ZHEQByHDILz6FtdqXunzCGg2ebJ571UMKSeO86eU5cMJ/mIV1GI5z9uX3P1TRYR2ORolIQJwB/RkefYJx3U7xlfNquPiJ/7V+JjSeNVOa+/9oLm+1lmK3oDc6tLZBDlFLiDFtBwTDyKKbv8= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1700765671769432.13182345392784; Thu, 23 Nov 2023 10:54:31 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1r6EoD-0008QO-LC; Thu, 23 Nov 2023 13:52:17 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1r6Eo3-0008A7-SM for qemu-devel@nongnu.org; Thu, 23 Nov 2023 13:52:07 -0500 Received: from mail-pf1-x435.google.com ([2607:f8b0:4864:20::435]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1r6Enx-0008NT-Rz for qemu-devel@nongnu.org; Thu, 23 Nov 2023 13:52:06 -0500 Received: by mail-pf1-x435.google.com with SMTP id d2e1a72fcca58-6cbbfdf72ecso1144134b3a.2 for ; Thu, 23 Nov 2023 10:51:57 -0800 (PST) Received: from grind.. ([2804:7f0:bdcd:fb00:6501:2693:db52:c621]) by smtp.gmail.com with ESMTPSA id u4-20020a17090282c400b001bb1f0605b2sm1662638plz.214.2023.11.23.10.51.53 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 23 Nov 2023 10:51:56 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1700765516; x=1701370316; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=idOjzqB/2N8r45g3xvXzJsWeC0Y1TlRo66OPhQFDTfY=; b=Ml8uC9zsXEYWnbmBPv9NKIcoDt3Jdy4n2NbXtN41qiT7TIC7gAToFaMLmOKTRyjmyV RXyJ6bk8f4yvzRZMSjSeJeXQjOtzHChzIE9q6flb+WnwbMNnj+LnBY8HQmZZ5rfkrBWb 2TrnuMb/gT+/8ppFx/Pp6zjMSjo4xIWAisa7T1zM4g4pPLnWb9Iopvnb5Sn6c/ZAgGd7 0gQWFQfqtSKHOUvdbDTvuVeRD1xnvORVwuZ2C65d8E0EtjKNeuOLgQhsttctMAMR9X3e viwbd5pFFqB9rFGF0PPwUoQyzudl2y+dT4fO+4Hg2APYICoqYYpZdM5WObSwYbCLsvjB AswQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1700765516; x=1701370316; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=idOjzqB/2N8r45g3xvXzJsWeC0Y1TlRo66OPhQFDTfY=; b=bLw3shY04ilvF6jGBSG9KyDdiAnGYrZkFrF/33xkLWV9VybCekJNkLQm7FfigxvZCW cFdEU+NUH5Y+Zi/S5BioTKLzFgRHUvHGb+DRrn1HKLgSLC3/v2O8Tm+dWUacSFh5gsuc x0+VNhUJWeRUu5yceYkX9zhB7RcszvDbc5tWAG7whzpYaiAGfDdXNgKFqfnfJL8KOxPz Fwb45KJT+gTrmzFMNf9tmEIZ+52NmaKgE3CGdBg58XKChapdw2Xr0A69GaBCBLOxsPQP Tkh1i7Sfpou3/60ZcE3urS1LDSNTK2A9wkYvwCGumulIyBxhAus1UQT7tQ3WrMq2Lyf/ x0Cg== X-Gm-Message-State: AOJu0YwFJCnzPlqZJsBcj3yhg4o9QURL+W92hFkUs5w+5d0rQ55DP/5f gfaxWaJ+cJ2fOO5fKHsMzalGjndvtNTUc7DjStA= X-Google-Smtp-Source: AGHT+IGnWoYoxI6sUCvbAtpJGwcK9XudH7Mr0e7yLJuw9XB38vvwGxUNQ73VdGBh21GijSBWOLv3Sg== X-Received: by 2002:a05:6a20:7493:b0:189:bde9:71aa with SMTP id p19-20020a056a20749300b00189bde971aamr506764pzd.48.1700765516584; Thu, 23 Nov 2023 10:51:56 -0800 (PST) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, bmeng@tinylab.org, liwei1518@gmail.com, zhiwei_liu@linux.alibaba.com, palmer@rivosinc.com, ajones@ventanamicro.com, Daniel Henrique Barboza Subject: [PATCH for-9.0 v11 09/18] target/riscv/kvm: add 'rva22u64' flag as unavailable Date: Thu, 23 Nov 2023 15:51:13 -0300 Message-ID: <20231123185122.1100436-10-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20231123185122.1100436-1-dbarboza@ventanamicro.com> References: <20231123185122.1100436-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::435; envelope-from=dbarboza@ventanamicro.com; helo=mail-pf1-x435.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ventanamicro.com) X-ZM-MESSAGEID: 1700765673922100003 Content-Type: text/plain; charset="utf-8" KVM does not have the means to support enabling the rva22u64 profile. The main reasons are: - we're missing support for some mandatory rva22u64 extensions in the KVM module; - we can't make promises about enabling a profile since it all depends on host support in the end. We'll revisit this decision in the future if needed. For now mark the 'rva22u64' profile as unavailable when running a KVM CPU: $ qemu-system-riscv64 -machine virt,accel=3Dkvm -cpu rv64,rva22u64=3Dtrue qemu-system-riscv64: can't apply global rv64-riscv-cpu.rva22u64=3Dtrue: 'rva22u64' is not available with KVM Signed-off-by: Daniel Henrique Barboza Reviewed-by: Alistair Francis Reviewed-by: LIU Zhiwei Reviewed-by: Andrew Jones --- target/riscv/kvm/kvm-cpu.c | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/target/riscv/kvm/kvm-cpu.c b/target/riscv/kvm/kvm-cpu.c index 78fa1fa162..9c6ff774b5 100644 --- a/target/riscv/kvm/kvm-cpu.c +++ b/target/riscv/kvm/kvm-cpu.c @@ -398,7 +398,7 @@ static void cpu_set_cfg_unavailable(Object *obj, Visito= r *v, } =20 if (value) { - error_setg(errp, "extension %s is not available with KVM", + error_setg(errp, "'%s' is not available with KVM", propname); } } @@ -479,6 +479,11 @@ static void kvm_riscv_add_cpu_user_properties(Object *= cpu_obj) riscv_cpu_add_kvm_unavail_prop_array(cpu_obj, riscv_cpu_extensions); riscv_cpu_add_kvm_unavail_prop_array(cpu_obj, riscv_cpu_vendor_exts); riscv_cpu_add_kvm_unavail_prop_array(cpu_obj, riscv_cpu_experimental_e= xts); + + /* We don't have the needed KVM support for profiles */ + for (i =3D 0; riscv_profiles[i] !=3D NULL; i++) { + riscv_cpu_add_kvm_unavail_prop(cpu_obj, riscv_profiles[i]->name); + } } =20 static int kvm_riscv_get_regs_core(CPUState *cs) --=20 2.41.0 From nobody Wed Nov 27 04:55:50 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1700765661; cv=none; d=zohomail.com; s=zohoarc; b=NrGjOwHRnID5CFRHpq8FWBf/LKR6eVmi9fIof9wDOVgAdf5PxGc07Ah4E7A8x8FDeDV/aYyHFE1AUdiIr0XmsmRKQ77kmuCNYPc1Zm/uQxzNFKw1qteU2f8unS2cnl/8iBECZZ8Y+MoF5CBl7TvbrMCnFhFJXb97VB59RmSCihg= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1700765661; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=BuGkw4C4KvihosZg4VPOPXopJcGYzRSOe7LfiEFCY9E=; b=fBwRW5oP5ebI7biWcyVCNYDdnBijojtQ/bZ1FNVgyuUtctY4hKIJo+gymBKI5DoJ2BVjLubc44Y1gtV6y+B0c1TDz0pHYTZ8SCHtD5BvNwmqXuvkWcWrmQumkeOkRksadE2spQpkdqevQtU1yOXvqmN932GjuM9gNqefP1cNwAw= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1700765661530919.10285211897; Thu, 23 Nov 2023 10:54:21 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1r6EoD-0008Qi-Rj; Thu, 23 Nov 2023 13:52:17 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1r6Eo2-00087h-0D for qemu-devel@nongnu.org; Thu, 23 Nov 2023 13:52:07 -0500 Received: from mail-pl1-x62e.google.com ([2607:f8b0:4864:20::62e]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1r6Enx-00006U-TQ for qemu-devel@nongnu.org; Thu, 23 Nov 2023 13:52:05 -0500 Received: by mail-pl1-x62e.google.com with SMTP id d9443c01a7336-1ce5e65ba37so8421935ad.1 for ; Thu, 23 Nov 2023 10:52:00 -0800 (PST) Received: from grind.. ([2804:7f0:bdcd:fb00:6501:2693:db52:c621]) by smtp.gmail.com with ESMTPSA id u4-20020a17090282c400b001bb1f0605b2sm1662638plz.214.2023.11.23.10.51.56 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 23 Nov 2023 10:51:59 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1700765520; x=1701370320; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=BuGkw4C4KvihosZg4VPOPXopJcGYzRSOe7LfiEFCY9E=; b=JrO45cgrmHZxOJPg57WCuKmK4QtKKU+15tJjhMxP6dn+MrlZ5pJbeiLd8xe9Esn7vU cnmIr7MeLgU/EsQgWjKYYHa7KXde4mkzL9jfrRJLdwxAlVm3ePbgSFT0XIEHRoxtbsSQ 6lxlU3Dg2tUyXb4PhEcxN92Cq4ZUsicRAY8yGlUJGc9Nsf2S8azhzcV5MzyYre/ZTEPX jxhF/rEDqFLbkCvWH+M/GkqEMFVY+CYFYmu9Eaw0whLCZN5RUVuCQUypjuHngk1UhWbK P5v1nG7ZGDN7Psd2eypXwl0VF1eiGc1JOu37G/Ijx07uJDeI5bYPwshTCsDIPHdiYdLC QJyA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1700765520; x=1701370320; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=BuGkw4C4KvihosZg4VPOPXopJcGYzRSOe7LfiEFCY9E=; b=m+NieCbA4SE2np69SpCxr31dCB+VQhW4zkn2qtZbCwbO4uM8lMNM5+OUtxWzu/p643 wBQlX4QGZWDYQbEOEDTYch2TJZJzTEcMH9Z7jOYBrgW7cnDX1KUoTQ1PFQy/oY71su7y W2grS1zBmwNiMKKevy2Wx6bZKJupsuLlj79/WCOaDJ3T4ZSt7xndDuJ12uC3Aa6cUw8y /P3U7ErLSltABQbJwfALtmm2CZYodM1HeJKp99soaiFidU9/rUGkDEv82KWybczqpFqT 1k7pNLkIH0GxMlk0nMQH8t3Vs0LrvLMOf1XbnVjv2Z9Iy3pzPLbmwsKCGK9Ko2HXRLT7 Oq+A== X-Gm-Message-State: AOJu0Yz/0w3eIRREFbOHHcKAmJhkGiWMqBF9uLLw2Yj/3qm/13+8EOzX bEjFyDk2vy7VdG633Lz/Kv+VNSQBRLadjwW+zt8= X-Google-Smtp-Source: AGHT+IHRdxkhpG9nrgsyTjDt1f4MhIafMOoobIp/zcziBd2FBR7l/eCYehkd+c0MicSVh2pzizEmfQ== X-Received: by 2002:a17:902:e542:b0:1ce:5f0d:e573 with SMTP id n2-20020a170902e54200b001ce5f0de573mr173316plf.0.1700765519667; Thu, 23 Nov 2023 10:51:59 -0800 (PST) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, bmeng@tinylab.org, liwei1518@gmail.com, zhiwei_liu@linux.alibaba.com, palmer@rivosinc.com, ajones@ventanamicro.com, Daniel Henrique Barboza Subject: [PATCH for-9.0 v11 10/18] target/riscv/tcg: add user flag for profile support Date: Thu, 23 Nov 2023 15:51:14 -0300 Message-ID: <20231123185122.1100436-11-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20231123185122.1100436-1-dbarboza@ventanamicro.com> References: <20231123185122.1100436-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::62e; envelope-from=dbarboza@ventanamicro.com; helo=mail-pl1-x62e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ventanamicro.com) X-ZM-MESSAGEID: 1700765661998100005 Content-Type: text/plain; charset="utf-8" The TCG emulation implements all the extensions described in the RVA22U64 profile, both mandatory and optional. The mandatory extensions will be enabled via the profile flag. We'll leave the optional extensions to be enabled by hand. Given that this is the first profile we're implementing in TCG we'll need some ground work first: - all profiles declared in riscv_profiles[] will be exposed to users. TCG is the main accelerator we're considering when adding profile support in QEMU, so for now it's safe to assume that all profiles in riscv_profiles[] will be relevant to TCG; - we'll not support user profile settings for vendor CPUs. The flags will still be exposed but users won't be able to change them; - profile support, albeit available for all non-vendor CPUs, will be based on top of the new 'rv64i' CPU. Setting a profile to 'true' means enable all mandatory extensions of this profile, setting it to 'false' will disable all mandatory profile extensions of the CPU, which will obliterate preset defaults. This is not a problem for a bare CPU like rv64i but it can allow for silly scenarios when using other CPUs. E.g. an user can do "-cpu rv64,rva22u64=3Dfalse" and have a bunch of default rv64 extensions disabled. The recommended way of using profiles is the rv64i CPU, but users are free to experiment. For now we'll handle multi-letter extensions only. MISA extensions need additional steps that we'll take care later. At this point we can boot a Linux buildroot using rva22u64 using the following options: -cpu rv64i,rva22u64=3Dtrue,sv39=3Dtrue,g=3Dtrue,c=3Dtrue,s=3Dtrue Note that being an usermode/application profile we still need to explicitly set 's=3Dtrue' to enable Supervisor mode to boot Linux. Signed-off-by: Daniel Henrique Barboza Reviewed-by: Andrew Jones --- target/riscv/tcg/tcg-cpu.c | 80 ++++++++++++++++++++++++++++++++++++++ 1 file changed, 80 insertions(+) diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c index 68577da8a8..f26dc7748d 100644 --- a/target/riscv/tcg/tcg-cpu.c +++ b/target/riscv/tcg/tcg-cpu.c @@ -127,6 +127,19 @@ static bool cpu_cfg_offset_is_named_feat(uint32_t ext_= offset) return false; } =20 +static void riscv_cpu_enable_named_feat(RISCVCPU *cpu, uint32_t feat_offse= t) +{ + switch (feat_offset) { + case CPU_CFG_OFFSET(zic64b): + cpu->cfg.cbom_blocksize =3D 64; + cpu->cfg.cbop_blocksize =3D 64; + cpu->cfg.cboz_blocksize =3D 64; + break; + default: + g_assert_not_reached(); + } +} + static void cpu_validate_multi_ext_priv_ver(CPURISCVState *env, uint32_t ext_offset) { @@ -890,6 +903,71 @@ static void riscv_cpu_add_misa_properties(Object *cpu_= obj) } } =20 +static void cpu_set_profile(Object *obj, Visitor *v, const char *name, + void *opaque, Error **errp) +{ + RISCVCPUProfile *profile =3D opaque; + RISCVCPU *cpu =3D RISCV_CPU(obj); + bool value; + int i, ext_offset; + + if (riscv_cpu_is_vendor(obj)) { + error_setg(errp, "Profile %s is not available for vendor CPUs", + profile->name); + return; + } + + if (cpu->env.misa_mxl !=3D MXL_RV64) { + error_setg(errp, "Profile %s only available for 64 bit CPUs", + profile->name); + return; + } + + if (!visit_type_bool(v, name, &value, errp)) { + return; + } + + profile->user_set =3D true; + profile->enabled =3D value; + + for (i =3D 0; profile->ext_offsets[i] !=3D RISCV_PROFILE_EXT_LIST_END;= i++) { + ext_offset =3D profile->ext_offsets[i]; + + if (profile->enabled) { + if (cpu_cfg_offset_is_named_feat(ext_offset)) { + riscv_cpu_enable_named_feat(cpu, ext_offset); + } + + cpu_validate_multi_ext_priv_ver(&cpu->env, ext_offset); + } + + g_hash_table_insert(multi_ext_user_opts, + GUINT_TO_POINTER(ext_offset), + (gpointer)profile->enabled); + isa_ext_update_enabled(cpu, ext_offset, profile->enabled); + } +} + +static void cpu_get_profile(Object *obj, Visitor *v, const char *name, + void *opaque, Error **errp) +{ + RISCVCPUProfile *profile =3D opaque; + bool value =3D profile->enabled; + + visit_type_bool(v, name, &value, errp); +} + +static void riscv_cpu_add_profiles(Object *cpu_obj) +{ + for (int i =3D 0; riscv_profiles[i] !=3D NULL; i++) { + const RISCVCPUProfile *profile =3D riscv_profiles[i]; + + object_property_add(cpu_obj, profile->name, "bool", + cpu_get_profile, cpu_set_profile, + NULL, (void *)profile); + } +} + static bool cpu_ext_is_deprecated(const char *ext_name) { return isupper(ext_name[0]); @@ -1017,6 +1095,8 @@ static void riscv_cpu_add_user_properties(Object *obj) =20 riscv_cpu_add_multiext_prop_array(obj, riscv_cpu_deprecated_exts); =20 + riscv_cpu_add_profiles(obj); + for (Property *prop =3D riscv_cpu_options; prop && prop->name; prop++)= { qdev_property_add_static(DEVICE(obj), prop); } --=20 2.41.0 From nobody Wed Nov 27 04:55:50 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; 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([2804:7f0:bdcd:fb00:6501:2693:db52:c621]) by smtp.gmail.com with ESMTPSA id u4-20020a17090282c400b001bb1f0605b2sm1662638plz.214.2023.11.23.10.52.00 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 23 Nov 2023 10:52:02 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1700765522; x=1701370322; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=wLvppxrHlugfax1BmTiiJZtjsEJqto80RCKzfZuCGnM=; b=WzYXsqcq6BSu67Uc047VXtWPzLDIxG0RArvYfZgk2vFmLe68SDhJolycc2UPBgXKPa SDdRwb0PmhJV1fus3nRIe8soUf8xfyPIJPrgbegInEEdI6bMp1f2gCd/LMYSe08lCOcK C62X2WRM0yVtqHv/soeS7HGDuFoIm4rSaOlvsRbFTGhkHC9EK9gOWWB1FbYAkoSj4b5w pOWsMrpToZ75geVo+0oGnKJ/aWcKH0sTfuBX+cqgSWrhUue2sjRRGUE9QacKLRhdWG4I uI26L/ZKw7pZC/Eb2SoycUNKCsZjQ5u3YsMTUK8f/Hp9Lf4/Dxox+XQ4EBdYZ50jCkLE WbOA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1700765522; x=1701370322; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=wLvppxrHlugfax1BmTiiJZtjsEJqto80RCKzfZuCGnM=; b=jm7uVxIxtzDVrpN6ayE7d/eJvnCLki3ND/fYCXo5ULFyz2wqPlMJHVju7jXOgidq4T QnEcY9hQdd/iPByYS/j6eIahKm0bBmxHmFCQk3DlaY5utVHDf7lyU4ZqP3zoBJoQjRKo S5IQXEXwukXqPstzJKD3LiedqylcUvd3h9XcswA9PCbOt9CGCemU8Z8c/fEF34X87+u2 kC7XfGvoWmV4kW0I5EuVc+bkD6Hm1YlnfXPtAsCWywq5wUl/urV+Va0CtczbQ7hTTnKx uaTKZVMELfjjTDFKxaQo15ywpGMxSkQJi4EgDKJgscJ3wA4GbI+i4LIh5k/YcPWBf0/z FxZg== X-Gm-Message-State: AOJu0YyHTSsJDYBmnkgor4AIVO9oHkiYihE4NjRetXxKHa0xgB/6OmX/ 7a3LveMZxKaETN1t4ZXUluafpEwssaP3gvqU6Zc= X-Google-Smtp-Source: AGHT+IE1vAT+MMmIW0LA0ucxG3+349nBFTkh2RjmJGM0wry4g0p4N1RQULVUfbR86UXQ+O/EEI6lNw== X-Received: by 2002:a17:902:c78b:b0:1cf:8c7a:ed20 with SMTP id w11-20020a170902c78b00b001cf8c7aed20mr323269pla.27.1700765522703; Thu, 23 Nov 2023 10:52:02 -0800 (PST) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, bmeng@tinylab.org, liwei1518@gmail.com, zhiwei_liu@linux.alibaba.com, palmer@rivosinc.com, ajones@ventanamicro.com, Daniel Henrique Barboza Subject: [PATCH for-9.0 v11 11/18] target/riscv/tcg: add MISA user options hash Date: Thu, 23 Nov 2023 15:51:15 -0300 Message-ID: <20231123185122.1100436-12-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20231123185122.1100436-1-dbarboza@ventanamicro.com> References: <20231123185122.1100436-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::62f; envelope-from=dbarboza@ventanamicro.com; helo=mail-pl1-x62f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ventanamicro.com) X-ZM-MESSAGEID: 1700765641790100005 Content-Type: text/plain; charset="utf-8" We already track user choice for multi-letter extensions because we needed to honor user choice when enabling/disabling extensions during realize(). We refrained from adding the same mechanism for MISA extensions since we didn't need it. Profile support requires tne need to check for user choice for MISA extensions, so let's add the corresponding hash now. It works like the existing multi-letter hash (multi_ext_user_opts) but tracking MISA bits options in the cpu_set_misa_ext_cfg() callback. Note that we can't re-use the same hash from multi-letter extensions because that hash uses cpu->cfg offsets as keys, while for MISA extensions we're using MISA bits as keys. After adding the user hash in cpu_set_misa_ext_cfg(), setting default values with object_property_set_bool() in add_misa_properties() will end up marking the user choice hash with them. Set the default value manually to avoid it. Signed-off-by: Daniel Henrique Barboza Reviewed-by: Alistair Francis Reviewed-by: LIU Zhiwei Reviewed-by: Andrew Jones --- target/riscv/tcg/tcg-cpu.c | 15 ++++++++++++++- 1 file changed, 14 insertions(+), 1 deletion(-) diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c index f26dc7748d..930aa7465b 100644 --- a/target/riscv/tcg/tcg-cpu.c +++ b/target/riscv/tcg/tcg-cpu.c @@ -34,6 +34,7 @@ =20 /* Hash that stores user set extensions */ static GHashTable *multi_ext_user_opts; +static GHashTable *misa_ext_user_opts; =20 static bool cpu_cfg_ext_is_user_set(uint32_t ext_offset) { @@ -807,6 +808,10 @@ static void cpu_set_misa_ext_cfg(Object *obj, Visitor = *v, const char *name, return; } =20 + g_hash_table_insert(misa_ext_user_opts, + GUINT_TO_POINTER(misa_bit), + (gpointer)value); + prev_val =3D env->misa_ext & misa_bit; =20 if (value =3D=3D prev_val) { @@ -878,6 +883,7 @@ static const RISCVCPUMisaExtConfig misa_ext_cfgs[] =3D { */ static void riscv_cpu_add_misa_properties(Object *cpu_obj) { + CPURISCVState *env =3D &RISCV_CPU(cpu_obj)->env; bool use_def_vals =3D riscv_cpu_is_generic(cpu_obj); int i; =20 @@ -898,7 +904,13 @@ static void riscv_cpu_add_misa_properties(Object *cpu_= obj) NULL, (void *)misa_cfg); object_property_set_description(cpu_obj, name, desc); if (use_def_vals) { - object_property_set_bool(cpu_obj, name, misa_cfg->enabled, NUL= L); + if (misa_cfg->enabled) { + env->misa_ext |=3D bit; + env->misa_ext_mask |=3D bit; + } else { + env->misa_ext &=3D ~bit; + env->misa_ext_mask &=3D ~bit; + } } } } @@ -1147,6 +1159,7 @@ static void tcg_cpu_instance_init(CPUState *cs) RISCVCPU *cpu =3D RISCV_CPU(cs); Object *obj =3D OBJECT(cpu); =20 + misa_ext_user_opts =3D g_hash_table_new(NULL, g_direct_equal); multi_ext_user_opts =3D g_hash_table_new(NULL, g_direct_equal); riscv_cpu_add_user_properties(obj); =20 --=20 2.41.0 From nobody Wed Nov 27 04:55:50 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1700765658; cv=none; d=zohomail.com; s=zohoarc; b=ZXGDV2tUjNCmy1cj5d32DjctSIIhROSv9+bSD2RykSZ0sMgEFfSdJ193cb4BceGOjvqBtx2GfxNnDUq9c4+yuRT32NPWhZ+ijSZFPBXyf9KZOInTpzGv0xrPqSmww/dCjkqNVe0eGdFhdO580aNsA7rBoQkMXdm440P5D21gbUU= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1700765658; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=IcFmOWMQtTKzILzU8WHNKi0gSvrauioMiSu2DiYuiQY=; b=RYLUvggRmWAJ6MfI57cHaChU1JYNHoZn7B4DwME0cXsK3e/T13KJ9nFGWmHImQaV9y/xF5xF/8CKu9md/blyY/JTrBaz8968DWu4UQnHxD5EY7btBBLI2C4GCEmwQcpr4VJOL219xZvcYarzIIahxwxjnrO2WluuLVaoz5EKxL8= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1700765658134512.3764542706336; Thu, 23 Nov 2023 10:54:18 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1r6EoE-0008SM-K2; Thu, 23 Nov 2023 13:52:18 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1r6EoB-0008Hy-IG for qemu-devel@nongnu.org; Thu, 23 Nov 2023 13:52:15 -0500 Received: from mail-pg1-x536.google.com ([2607:f8b0:4864:20::536]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1r6Eo5-0000Bs-Ad for qemu-devel@nongnu.org; Thu, 23 Nov 2023 13:52:13 -0500 Received: by mail-pg1-x536.google.com with SMTP id 41be03b00d2f7-5bd33a450fdso819133a12.0 for ; Thu, 23 Nov 2023 10:52:07 -0800 (PST) Received: from grind.. ([2804:7f0:bdcd:fb00:6501:2693:db52:c621]) by smtp.gmail.com with ESMTPSA id u4-20020a17090282c400b001bb1f0605b2sm1662638plz.214.2023.11.23.10.52.03 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 23 Nov 2023 10:52:05 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1700765526; x=1701370326; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=IcFmOWMQtTKzILzU8WHNKi0gSvrauioMiSu2DiYuiQY=; b=X0c3heZ/G7Lbk8ZLQhdDqFVEexwzggNOBOwPBQaC927XfWA+HUVj6QNlqIu0SaStvt 8FrXNA3KuOxHRdgqxJTKAGMxmARuySNfDqul9nhyHzyNM5Yl2puJ+1FZYuzi+b4nJyVm 48K14riX3TthDSY6mv8naGo1GFrBKnXpUGsZuJRJR53WPkZ1t0Qc5y/0H4eRGzArtMVg Z1aw+vToFcBSi01FnO1guhR9Yygm8ctcy6VlZ2qGCpZf8HoAIfyJsbegDegmOpmg8X4v ZJsci7cdRayMoge20ovNXuoUO++v0MkPRUxsUu9eJdaxbeQnVemFLdnDT8xvMtTTRVcq lQtA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1700765526; x=1701370326; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=IcFmOWMQtTKzILzU8WHNKi0gSvrauioMiSu2DiYuiQY=; b=esSjMfVB8WsHMK/c/VvIUJiBH3ZxNppAhEUJNbkjBAZ2/s441NB1E/EYm05OqwJwlu A0SH5lSXRP4835BPYM4YQhgrlD32GikHtE1F1xmPmcdLLRLdHtZHc2wVEidBZiWaa0Ej XcIDPXzANk3dEBirBZt11HAA8+6v/4BL+PmkXUHdMk8q8RbvRgtC7QOcqtbko7dwc6J+ opCPPKpLN+CTt5n26vFaN3Ua6Gfnld3GU56m3bfLTu8XBzxd1bshn1RGI8VLlo1Z5kO1 NYHzd36CJ3Jvb383dYrY1vHNbuwjFNzmFIjXPnCmu3mMn/Nb8sBdZkvYtM6xVhbbHK33 WXFA== X-Gm-Message-State: AOJu0YxRTmlNqtKelgIzfskr+nQRC8G0DsMKsWaQADeWqSxJC9YLSM3H X5PROfwtdlkTnT6OGmgMgMa+dWzzFLuzbhC4/E0= X-Google-Smtp-Source: AGHT+IHbDturBk3f43LS/DUN1fGaMxgnhK+sgjlP5ylK9Ijw4NKzgRbPV2ulITWBwXYAWzs2+xszIQ== X-Received: by 2002:a05:6a21:9997:b0:18b:cc7e:de3 with SMTP id ve23-20020a056a21999700b0018bcc7e0de3mr546157pzb.41.1700765525867; Thu, 23 Nov 2023 10:52:05 -0800 (PST) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, bmeng@tinylab.org, liwei1518@gmail.com, zhiwei_liu@linux.alibaba.com, palmer@rivosinc.com, ajones@ventanamicro.com, Daniel Henrique Barboza Subject: [PATCH for-9.0 v11 12/18] target/riscv/tcg: add riscv_cpu_write_misa_bit() Date: Thu, 23 Nov 2023 15:51:16 -0300 Message-ID: <20231123185122.1100436-13-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20231123185122.1100436-1-dbarboza@ventanamicro.com> References: <20231123185122.1100436-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::536; envelope-from=dbarboza@ventanamicro.com; helo=mail-pg1-x536.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ventanamicro.com) X-ZM-MESSAGEID: 1700765660024100003 Content-Type: text/plain; charset="utf-8" We have two instances of the setting/clearing a MISA bit from env->misa_ext and env->misa_ext_mask pattern. And the next patch will end up adding one more. Create a helper to avoid code repetition. Signed-off-by: Daniel Henrique Barboza Reviewed-by: Alistair Francis Reviewed-by: LIU Zhiwei Reviewed-by: Andrew Jones --- target/riscv/tcg/tcg-cpu.c | 32 ++++++++++++++++++-------------- 1 file changed, 18 insertions(+), 14 deletions(-) diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c index 930aa7465b..5f770243d0 100644 --- a/target/riscv/tcg/tcg-cpu.c +++ b/target/riscv/tcg/tcg-cpu.c @@ -42,6 +42,20 @@ static bool cpu_cfg_ext_is_user_set(uint32_t ext_offset) GUINT_TO_POINTER(ext_offset)); } =20 +static void riscv_cpu_write_misa_bit(RISCVCPU *cpu, uint32_t bit, + bool enabled) +{ + CPURISCVState *env =3D &cpu->env; + + if (enabled) { + env->misa_ext |=3D bit; + env->misa_ext_mask |=3D bit; + } else { + env->misa_ext &=3D ~bit; + env->misa_ext_mask &=3D ~bit; + } +} + static void riscv_cpu_synchronize_from_tb(CPUState *cs, const TranslationBlock *tb) { @@ -833,13 +847,9 @@ static void cpu_set_misa_ext_cfg(Object *obj, Visitor = *v, const char *name, */ env->priv_ver =3D PRIV_VERSION_1_12_0; } - - env->misa_ext |=3D misa_bit; - env->misa_ext_mask |=3D misa_bit; - } else { - env->misa_ext &=3D ~misa_bit; - env->misa_ext_mask &=3D ~misa_bit; } + + riscv_cpu_write_misa_bit(cpu, misa_bit, value); } =20 static void cpu_get_misa_ext_cfg(Object *obj, Visitor *v, const char *name, @@ -883,7 +893,6 @@ static const RISCVCPUMisaExtConfig misa_ext_cfgs[] =3D { */ static void riscv_cpu_add_misa_properties(Object *cpu_obj) { - CPURISCVState *env =3D &RISCV_CPU(cpu_obj)->env; bool use_def_vals =3D riscv_cpu_is_generic(cpu_obj); int i; =20 @@ -904,13 +913,8 @@ static void riscv_cpu_add_misa_properties(Object *cpu_= obj) NULL, (void *)misa_cfg); object_property_set_description(cpu_obj, name, desc); if (use_def_vals) { - if (misa_cfg->enabled) { - env->misa_ext |=3D bit; - env->misa_ext_mask |=3D bit; - } else { - env->misa_ext &=3D ~bit; - env->misa_ext_mask &=3D ~bit; - } + riscv_cpu_write_misa_bit(RISCV_CPU(cpu_obj), bit, + misa_cfg->enabled); } } } --=20 2.41.0 From nobody Wed Nov 27 04:55:50 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1700765585; cv=none; d=zohomail.com; s=zohoarc; b=LIc9YPLst6Ty3pWRRpHS7RV3Vzst44qs/cy1HnuvKdjhfWOLdwlOFepLw+UxksAhKgRNCXVKTcXVebAsiu/6/Na61A5vjr4xzh9EneDYZkH4LMyjaoNrLnqQowV+GOwDLp6jIoDJyjjPYWziP6Fvl2LmaMNFh0YgmVFQ1nJjEaA= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1700765585; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=Vgcpyo/lx9NHmm9iAX7ut4jSlldFzzfkoTFAHmC7vNw=; b=WpZ/exjYvkRJdUqjXjFFzKt123DTMQPgtTHi3LPMqyrFE+IBv4CtYcGh193mMaqzBuVR+WYdcAYt+mIMQEsn5KsWe1I57M1biW1d8ADoYLZN+34gpiKto8x+ABEPD78PVaayh3bUJIEz0hrZS155T+TeyFkY9HqwCgADp0LNsDY= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1700765585360790.5937380346047; Thu, 23 Nov 2023 10:53:05 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1r6EoG-0000Cb-Lz; Thu, 23 Nov 2023 13:52:20 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1r6EoB-0008Hz-Ie for qemu-devel@nongnu.org; Thu, 23 Nov 2023 13:52:15 -0500 Received: from mail-pl1-x631.google.com ([2607:f8b0:4864:20::631]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1r6Eo8-0000Cg-Es for qemu-devel@nongnu.org; Thu, 23 Nov 2023 13:52:14 -0500 Received: by mail-pl1-x631.google.com with SMTP id d9443c01a7336-1cf80a7be0aso9452905ad.1 for ; Thu, 23 Nov 2023 10:52:10 -0800 (PST) Received: from grind.. ([2804:7f0:bdcd:fb00:6501:2693:db52:c621]) by smtp.gmail.com with ESMTPSA id u4-20020a17090282c400b001bb1f0605b2sm1662638plz.214.2023.11.23.10.52.06 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 23 Nov 2023 10:52:08 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1700765529; x=1701370329; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=Vgcpyo/lx9NHmm9iAX7ut4jSlldFzzfkoTFAHmC7vNw=; b=Swws0dvSPqCnf+uzNYP66BGsRFjgIaH3UCCh7ry+mdGdHa/Azo78i2j29p8IojYA9S itIahegj+fTRo6yt5l9QiOb/UBUo6YvSmcuM4pBw9FXSkEYqOTehH9jU2cFuaidAWuHr R8MmJls9XikW2rRW91PfUL7FvwyvT3Un+Ev9F8nAz+leoHP+oAH8GinS652RIstZZRdv s5MehFFEQ7C9aGJVfVLpBOfDH1oSpWf3DivDA2EsZI3LaOMqrUaJ7myuSfv5Llg/amzY keBfKE/1ijISDFOBBGTb9Ry7YQ1bEl2VCcXUE1QwKzL/1vpsunh7Agg3Ijx8a/+mez0z H6pg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1700765529; x=1701370329; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=Vgcpyo/lx9NHmm9iAX7ut4jSlldFzzfkoTFAHmC7vNw=; b=k8rA1xzvz++KQJ98gyh5JWQJbPbok5g3Q5WJe4HEXV9zTy7iWTJD0UH+IU9MlLTMgB DHZiAfgN8PgD5jZaFUEEWyRszzcz6DhgTvIkhFlvZK2sSwXqbQS5DL/jefw/tH0mGdVH ADACDM9rovvddZ6LoJo1tOPxc8fHQu8XQJnY9LN0T3YefeYfk5nd/adkuioq2R5ZcOid ao4MOg1Z3nX9xrRA8CMWhUAsmzhBYN0qtPB9/j/qi38bgmTuM9rhPn/O1VSmtn0BA8Q5 ef9yOSmsc8tJqYjwcJe6Ox0o3ZZ+ycRJ+3uVSihySIYYi804KTBSql+7sh56p8SKZ5Rm PbNA== X-Gm-Message-State: AOJu0Yy+YUuknmrlgrPqqNfkvKvDDL5et7M3//96CAp53oeZbdRrAcNa fchvApz3SEzM7ND9JrLBI0ucQrg+BspapNUwzhM= X-Google-Smtp-Source: AGHT+IEFi6oDiKTF4SIEfRx5QoK93CU/xujfRE37LR6TuXOvf1rDTjeIV5oXGEydvCup7JRvfUWATw== X-Received: by 2002:a17:902:ee52:b0:1ce:5853:1ff2 with SMTP id 18-20020a170902ee5200b001ce58531ff2mr401943plo.11.1700765529028; Thu, 23 Nov 2023 10:52:09 -0800 (PST) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, bmeng@tinylab.org, liwei1518@gmail.com, zhiwei_liu@linux.alibaba.com, palmer@rivosinc.com, ajones@ventanamicro.com, Daniel Henrique Barboza Subject: [PATCH for-9.0 v11 13/18] target/riscv/tcg: handle profile MISA bits Date: Thu, 23 Nov 2023 15:51:17 -0300 Message-ID: <20231123185122.1100436-14-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20231123185122.1100436-1-dbarboza@ventanamicro.com> References: <20231123185122.1100436-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::631; envelope-from=dbarboza@ventanamicro.com; helo=mail-pl1-x631.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ventanamicro.com) X-ZM-MESSAGEID: 1700765587535100003 Content-Type: text/plain; charset="utf-8" The profile support is handling multi-letter extensions only. Let's add support for MISA bits as well. We'll go through every known MISA bit. If the profile doesn't declare the bit as mandatory, ignore it. Otherwise, set the bit in env->misa_ext and env->misa_ext_mask. Now that we're setting profile MISA bits, one can use the rv64i CPU to boot Linux using the following options: -cpu rv64i,rva22u64=3Dtrue,rv39=3Dtrue,s=3Dtrue,zifencei=3Dtrue In the near future, when rva22s64 (where, 's', 'zifencei' and sv39 are mandatory), is implemented, rv64i will be able to boot Linux loading rva22s64 and no additional flags. Signed-off-by: Daniel Henrique Barboza Reviewed-by: LIU Zhiwei Reviewed-by: Andrew Jones Reviewed-by: Alistair Francis --- target/riscv/tcg/tcg-cpu.c | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c index 5f770243d0..092742c2b7 100644 --- a/target/riscv/tcg/tcg-cpu.c +++ b/target/riscv/tcg/tcg-cpu.c @@ -946,6 +946,27 @@ static void cpu_set_profile(Object *obj, Visitor *v, c= onst char *name, profile->user_set =3D true; profile->enabled =3D value; =20 + for (i =3D 0; misa_bits[i] !=3D 0; i++) { + uint32_t bit =3D misa_bits[i]; + + if (!(profile->misa_ext & bit)) { + continue; + } + + if (bit =3D=3D RVI && !profile->enabled) { + /* + * Disabling profiles will not disable the base + * ISA RV64I. + */ + continue; + } + + g_hash_table_insert(misa_ext_user_opts, + GUINT_TO_POINTER(bit), + (gpointer)value); + riscv_cpu_write_misa_bit(cpu, bit, profile->enabled); + } + for (i =3D 0; profile->ext_offsets[i] !=3D RISCV_PROFILE_EXT_LIST_END;= i++) { ext_offset =3D profile->ext_offsets[i]; =20 --=20 2.41.0 From nobody Wed Nov 27 04:55:50 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1700765642; cv=none; d=zohomail.com; s=zohoarc; b=FDDYJ0zh5XVKMPhMAyZRYflCOEX6RlhSlwP0I9O3xwNrAD1SRqK+f03Ag8l2c1bz305LTHOXOCSt2qCYxika/ke/uNYPLSysaOKVhnHbbXdqybVt5p/Wp/aNSlAM9oenWCapFgqVc8dLdM1Q2355qxmg6q4dobUmGTln3ML4Knw= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1700765642; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=bA9SrnLTVc37f7jGZJNj8vJFWvRNsa04ovjAxVnaKYE=; b=SlM0RWsG931awy4HrU69s3oGq8WlRDwslUPpxy8w/u1gGIMcAgDZ7Grs0ZWHswK1UnFmUd78N9fMj/EM6B5LcOKRGYXur6/D7CwwGwCafU9PNyg/rLmY1RdJi3tQ4zGdXv5m28kIu44E7vBKDnikW5/xBZHTOKhd/tvjEj40+FQ= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1700765642924300.7446546727109; Thu, 23 Nov 2023 10:54:02 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1r6EoG-0000Cz-Oa; Thu, 23 Nov 2023 13:52:20 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1r6EoD-0008OJ-0D for qemu-devel@nongnu.org; Thu, 23 Nov 2023 13:52:17 -0500 Received: from mail-pf1-x430.google.com ([2607:f8b0:4864:20::430]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1r6EoB-0000DJ-0d for qemu-devel@nongnu.org; Thu, 23 Nov 2023 13:52:16 -0500 Received: by mail-pf1-x430.google.com with SMTP id d2e1a72fcca58-6cbc8199a2aso957792b3a.1 for ; Thu, 23 Nov 2023 10:52:14 -0800 (PST) Received: from grind.. ([2804:7f0:bdcd:fb00:6501:2693:db52:c621]) by smtp.gmail.com with ESMTPSA id u4-20020a17090282c400b001bb1f0605b2sm1662638plz.214.2023.11.23.10.52.09 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 23 Nov 2023 10:52:11 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1700765532; x=1701370332; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=bA9SrnLTVc37f7jGZJNj8vJFWvRNsa04ovjAxVnaKYE=; b=BDSpf9YfsaBurnx1pZOzsaLuBREIiIiROyiPhPfHlS0AHNGHvmG+khZvUMSJFN+Ni5 tnsMHjyDPUJilhemNVxB1WxluD9EjU+NhD3rANNe2JQFARpJUEI+dNH4hyRXzE5fDM9N tb4Svwz6Lnr6nmZ3nwpfRdlrJfmaoBdYgOurGYbG4/hgV3EHjFV65vIEMqBpC5HoeVFC 5nQY9+gkYRHz2gfokCGHsIWSKG92tmXpYx4l1fQFI6xBJFI+c15Aeo/uFqYL1JbUVE7G YzZK168yy79YU3dGh1PvWASkXC5E/wJ/mGGjEwhi/8wF1TyBzOY1pYNIbiNTP8pvUfGW VRig== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1700765532; x=1701370332; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=bA9SrnLTVc37f7jGZJNj8vJFWvRNsa04ovjAxVnaKYE=; b=CjE91KMWh8DDWy90I2b1oDcVF3nD96f3hWyP4mtr+XW5hVreLy9YwkjG5arSJw6G0t BrEdLQEogrczWTxKr8hZGFK6rDsXHu6P4UmuyZEgs3wmsukiW9grAcrxPCuzTVWxsbh6 2bgJaeo4DyYQ4vuXbrJmybDqk6xAU5XgLlAAMod6rhQD2+nB7mOqc841QW0PoApcM3cF PBoHuYW9bDEjMhvKniIzU2nAJvo68dOCEAZYSKZThspv4yB4AY7ZJZlcPxkljBePyPfJ 7Kqk8yEcaOGu0JO+/6lYKKoR6jvoJAMMCQXXX9ENeD44Sp3N/kztPXRA1xIxDd4K7V+p 8lUQ== X-Gm-Message-State: AOJu0YxAccws6yqYidrhWuP0AR51Z0y7LTiZKNDjDGTtqEuj/VVCVlul H9QmxGlV7xLgrYE+54ik1eJ6MpAxxuqlr5mTBg0= X-Google-Smtp-Source: AGHT+IETaMvUzgCJt+fNUrO0E/B+pZp1AoK1muFpU+gsh9Y4CB7vvRKSXRXr29N1kj6Xq90ZR09+0w== X-Received: by 2002:a05:6a20:549a:b0:187:2e65:9cc9 with SMTP id i26-20020a056a20549a00b001872e659cc9mr317939pzk.56.1700765532122; Thu, 23 Nov 2023 10:52:12 -0800 (PST) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, bmeng@tinylab.org, liwei1518@gmail.com, zhiwei_liu@linux.alibaba.com, palmer@rivosinc.com, ajones@ventanamicro.com, Daniel Henrique Barboza Subject: [PATCH for-9.0 v11 14/18] target/riscv/tcg: add hash table insert helpers Date: Thu, 23 Nov 2023 15:51:18 -0300 Message-ID: <20231123185122.1100436-15-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20231123185122.1100436-1-dbarboza@ventanamicro.com> References: <20231123185122.1100436-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::430; envelope-from=dbarboza@ventanamicro.com; helo=mail-pf1-x430.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ventanamicro.com) X-ZM-MESSAGEID: 1700765643828100014 Content-Type: text/plain; charset="utf-8" Previous patches added several g_hash_table_insert() patterns. Add two helpers, one for each user hash, to make the code cleaner. Signed-off-by: Daniel Henrique Barboza Reviewed-by: Andrew Jones --- target/riscv/tcg/tcg-cpu.c | 28 ++++++++++++++++------------ 1 file changed, 16 insertions(+), 12 deletions(-) diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c index 092742c2b7..c248944f24 100644 --- a/target/riscv/tcg/tcg-cpu.c +++ b/target/riscv/tcg/tcg-cpu.c @@ -42,6 +42,18 @@ static bool cpu_cfg_ext_is_user_set(uint32_t ext_offset) GUINT_TO_POINTER(ext_offset)); } =20 +static void cpu_cfg_ext_add_user_opt(uint32_t ext_offset, bool value) +{ + g_hash_table_insert(multi_ext_user_opts, GUINT_TO_POINTER(ext_offset), + (gpointer)value); +} + +static void cpu_misa_ext_add_user_opt(uint32_t bit, bool value) +{ + g_hash_table_insert(misa_ext_user_opts, GUINT_TO_POINTER(bit), + (gpointer)value); +} + static void riscv_cpu_write_misa_bit(RISCVCPU *cpu, uint32_t bit, bool enabled) { @@ -822,9 +834,7 @@ static void cpu_set_misa_ext_cfg(Object *obj, Visitor *= v, const char *name, return; } =20 - g_hash_table_insert(misa_ext_user_opts, - GUINT_TO_POINTER(misa_bit), - (gpointer)value); + cpu_misa_ext_add_user_opt(misa_bit, value); =20 prev_val =3D env->misa_ext & misa_bit; =20 @@ -961,9 +971,7 @@ static void cpu_set_profile(Object *obj, Visitor *v, co= nst char *name, continue; } =20 - g_hash_table_insert(misa_ext_user_opts, - GUINT_TO_POINTER(bit), - (gpointer)value); + cpu_misa_ext_add_user_opt(bit, profile->enabled); riscv_cpu_write_misa_bit(cpu, bit, profile->enabled); } =20 @@ -978,9 +986,7 @@ static void cpu_set_profile(Object *obj, Visitor *v, co= nst char *name, cpu_validate_multi_ext_priv_ver(&cpu->env, ext_offset); } =20 - g_hash_table_insert(multi_ext_user_opts, - GUINT_TO_POINTER(ext_offset), - (gpointer)profile->enabled); + cpu_cfg_ext_add_user_opt(ext_offset, profile->enabled); isa_ext_update_enabled(cpu, ext_offset, profile->enabled); } } @@ -1043,9 +1049,7 @@ static void cpu_set_multi_ext_cfg(Object *obj, Visito= r *v, const char *name, multi_ext_cfg->name, lower); } =20 - g_hash_table_insert(multi_ext_user_opts, - GUINT_TO_POINTER(multi_ext_cfg->offset), - (gpointer)value); + cpu_cfg_ext_add_user_opt(multi_ext_cfg->offset, value); =20 prev_val =3D isa_ext_is_enabled(cpu, multi_ext_cfg->offset); =20 --=20 2.41.0 From nobody Wed Nov 27 04:55:50 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1700765664; cv=none; d=zohomail.com; s=zohoarc; b=P/D4W6lr56x0Q5uStuCOJDRxsg4eIxaRiS58XOFvmO2SeWlR2a+eIBq0VyI3zHENS8k1WiIkulQIdfaFsVxJ7YQM/v/HGjZeKDWDwgpuMiM4VE0026SBZC/sm7Kr1bHQNBizYuyGB7hCoKWj263ZOiQAuIxBxqeV/R9vmFITSkg= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1700765664; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=qNfNwjRWKfiYddNL4I/SEvJ+eIw5xJir3c7Q2fn8A6I=; b=ho61mg5TxV99QdFbj7E+Bw3UMFZafJ6l6JnMsL/oEZ3R8CIShuh6M/mc2hvrS7uY0qWUZgONQk0WSZqL1mTYjamrxd/lPd9Gp+LhmkpKwnjTRRdUFGmOr91AXmVDQTQVCi2SOsTNLpduVCpX0jypFJ/evCe2wQiN7qJu36jSGyc= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 170076566424471.50588499454796; Thu, 23 Nov 2023 10:54:24 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1r6EoH-0000KG-U3; Thu, 23 Nov 2023 13:52:21 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1r6EoF-00005h-Ev for qemu-devel@nongnu.org; Thu, 23 Nov 2023 13:52:19 -0500 Received: from mail-pl1-x629.google.com ([2607:f8b0:4864:20::629]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1r6EoD-0000Dt-JO for qemu-devel@nongnu.org; Thu, 23 Nov 2023 13:52:19 -0500 Received: by mail-pl1-x629.google.com with SMTP id d9443c01a7336-1cf50cc2f85so9143905ad.1 for ; Thu, 23 Nov 2023 10:52:17 -0800 (PST) Received: from grind.. ([2804:7f0:bdcd:fb00:6501:2693:db52:c621]) by smtp.gmail.com with ESMTPSA id u4-20020a17090282c400b001bb1f0605b2sm1662638plz.214.2023.11.23.10.52.12 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 23 Nov 2023 10:52:14 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1700765535; x=1701370335; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=qNfNwjRWKfiYddNL4I/SEvJ+eIw5xJir3c7Q2fn8A6I=; b=aTitXhPj5uE6X6ftuc71czfhdFQvRSGL+5UQ6fjNzEFFKZmWgHOSNTJncp7iPAeo2v j1dLZe5sRIitRzR5pYPeCYz7QUiy9IlwcvqQXxvHrrJfSF/ng7CNFT/x685vUhbjiEB3 BsZoUf/FqR9T7l0mpbq6Jt3SzFNoxts+i1cURQQXBkIwSMfiAkBXYzH2uY3VRyAKlwvp TfSPAHNMQc851zqpKQ8m8CkWqp1kQLyCKpUgyWMpTUGrtmPkua9zSvkLAKna/ng0SZSP UQJ7au7UsTuprHmxOpyr2XLpBYjGDoBgPGH28XgOLUAioqt+yLCn9tjNwGWX1RRapsN5 hOHQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1700765535; x=1701370335; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=qNfNwjRWKfiYddNL4I/SEvJ+eIw5xJir3c7Q2fn8A6I=; b=p9aDZtO7Fjq6I5QHwga7Tk7FMix89wgDU7PTdHX/GtLTC+DsgzXWUPdzRNoOvN4+oL PzSti8EoClAn84MxkA43+oX2iXvlxSz/W8wvoCAJwWlMQoDjkLdV5c+Gd5pWLl1cinMr LjQC8SBupNGCITuge2qoQleHH1cUjPvWljUFTA7f+G4OD76CRR44MPIXCMdc75+CwhnW lv2BSJseeq9lRS0Wzp8R/YojrURKeyHx6CURm6ARy3vln4tkW+ARQalwTBUzPOJQoC+l 2BHiGSLxhQcirxyG7UlRq7u3G1Jhrr/LZVAWeVA6N7YsYDrdJQH63lRg+8KJWu9p3IvJ EzUQ== X-Gm-Message-State: AOJu0YyWVsXC+EXRq7+vHgonwEdE8sr09G4gSh7SXIqdLHEVWlj/OJLF W26bkGQoIR2FQZqzHHlMu6sRmvS6BUvaZwTQb8s= X-Google-Smtp-Source: AGHT+IFc+dmeu0PocUDpJsiRvar9vuTzbjWnu+ae292O6cT2KmxuTtZxkZi6sr03e6BLeNOFiX148Q== X-Received: by 2002:a17:902:db02:b0:1cf:7911:4619 with SMTP id m2-20020a170902db0200b001cf79114619mr386310plx.49.1700765535294; Thu, 23 Nov 2023 10:52:15 -0800 (PST) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, bmeng@tinylab.org, liwei1518@gmail.com, zhiwei_liu@linux.alibaba.com, palmer@rivosinc.com, ajones@ventanamicro.com, Daniel Henrique Barboza Subject: [PATCH for-9.0 v11 15/18] target/riscv/tcg: honor user choice for G MISA bits Date: Thu, 23 Nov 2023 15:51:19 -0300 Message-ID: <20231123185122.1100436-16-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20231123185122.1100436-1-dbarboza@ventanamicro.com> References: <20231123185122.1100436-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::629; envelope-from=dbarboza@ventanamicro.com; helo=mail-pl1-x629.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ventanamicro.com) X-ZM-MESSAGEID: 1700765665959100009 Content-Type: text/plain; charset="utf-8" RVG behaves like a profile: a single flag enables a set of bits. Right now we're considering user choice when handling RVG and zicsr/zifencei and ignoring user choice on MISA bits. We'll add user warnings for profiles when the user disables its mandatory extensions in the next patch. We'll do the same thing with RVG now to keep consistency between RVG and profile handling. First and foremost, create a new RVG only helper to avoid clogging riscv_cpu_validate_set_extensions(). We do not want to annoy users with RVG warnings like we did in the past (see 9b9741c38f), thus we'll only warn if RVG was user set and the user disabled a RVG extension in the command line. For every RVG MISA bit (IMAFD), zicsr and zifencei, the logic then becomes: - if enabled, do nothing; - if disabled and not user set, enable it; - if disabled and user set, throw a warning that it's a RVG mandatory extension. This same logic will be used for profiles in the next patch. Note that this is a behavior change, where we would error out if the user disabled either zicsr or zifencei. As long as users are explicitly disabling things in the command line we'll let them have a go at it, at least in this step. We'll error out later in the validation if needed. Other notable changes from the previous RVG code: - use riscv_cpu_write_misa_bit() instead of manually updating both env->misa_ext and env->misa_ext_mask; - set zicsr and zifencei directly. We're already checking if they were user set and priv version will never fail for these extensions, making cpu_cfg_ext_auto_update() redundant. Signed-off-by: Daniel Henrique Barboza Reviewed-by: Andrew Jones Reviewed-by: Alistair Francis --- target/riscv/tcg/tcg-cpu.c | 73 +++++++++++++++++++++++++------------- 1 file changed, 48 insertions(+), 25 deletions(-) diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c index c248944f24..b3bba7887e 100644 --- a/target/riscv/tcg/tcg-cpu.c +++ b/target/riscv/tcg/tcg-cpu.c @@ -42,6 +42,12 @@ static bool cpu_cfg_ext_is_user_set(uint32_t ext_offset) GUINT_TO_POINTER(ext_offset)); } =20 +static bool cpu_misa_ext_is_user_set(uint32_t misa_bit) +{ + return g_hash_table_contains(misa_ext_user_opts, + GUINT_TO_POINTER(misa_bit)); +} + static void cpu_cfg_ext_add_user_opt(uint32_t ext_offset, bool value) { g_hash_table_insert(multi_ext_user_opts, GUINT_TO_POINTER(ext_offset), @@ -362,6 +368,46 @@ static void riscv_cpu_validate_named_features(RISCVCPU= *cpu) riscv_cpu_validate_zic64b(cpu); } =20 +static void riscv_cpu_validate_g(RISCVCPU *cpu) +{ + const char *warn_msg =3D "RVG mandates disabled extension %s"; + uint32_t g_misa_bits[] =3D {RVI, RVM, RVA, RVF, RVD}; + bool send_warn =3D cpu_misa_ext_is_user_set(RVG); + + for (int i =3D 0; i < ARRAY_SIZE(g_misa_bits); i++) { + uint32_t bit =3D g_misa_bits[i]; + + if (riscv_has_ext(&cpu->env, bit)) { + continue; + } + + if (!cpu_misa_ext_is_user_set(bit)) { + riscv_cpu_write_misa_bit(cpu, bit, true); + continue; + } + + if (send_warn) { + warn_report(warn_msg, riscv_get_misa_ext_name(bit)); + } + } + + if (!cpu->cfg.ext_zicsr) { + if (!cpu_cfg_ext_is_user_set(CPU_CFG_OFFSET(ext_zicsr))) { + cpu->cfg.ext_zicsr =3D true; + } else if (send_warn) { + warn_report(warn_msg, "zicsr"); + } + } + + if (!cpu->cfg.ext_zifencei) { + if (!cpu_cfg_ext_is_user_set(CPU_CFG_OFFSET(ext_zifencei))) { + cpu->cfg.ext_zifencei =3D true; + } else if (send_warn) { + warn_report(warn_msg, "zifencei"); + } + } +} + /* * Check consistency between chosen extensions while setting * cpu->cfg accordingly. @@ -371,31 +417,8 @@ void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, = Error **errp) CPURISCVState *env =3D &cpu->env; Error *local_err =3D NULL; =20 - /* Do some ISA extension error checking */ - if (riscv_has_ext(env, RVG) && - !(riscv_has_ext(env, RVI) && riscv_has_ext(env, RVM) && - riscv_has_ext(env, RVA) && riscv_has_ext(env, RVF) && - riscv_has_ext(env, RVD) && - cpu->cfg.ext_zicsr && cpu->cfg.ext_zifencei)) { - - if (cpu_cfg_ext_is_user_set(CPU_CFG_OFFSET(ext_zicsr)) && - !cpu->cfg.ext_zicsr) { - error_setg(errp, "RVG requires Zicsr but user set Zicsr to fal= se"); - return; - } - - if (cpu_cfg_ext_is_user_set(CPU_CFG_OFFSET(ext_zifencei)) && - !cpu->cfg.ext_zifencei) { - error_setg(errp, "RVG requires Zifencei but user set " - "Zifencei to false"); - return; - } - - cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zicsr), true); - cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zifencei), true); - - env->misa_ext |=3D RVI | RVM | RVA | RVF | RVD; - env->misa_ext_mask |=3D RVI | RVM | RVA | RVF | RVD; + if (riscv_has_ext(env, RVG)) { + riscv_cpu_validate_g(cpu); } =20 if (riscv_has_ext(env, RVI) && riscv_has_ext(env, RVE)) { --=20 2.41.0 From nobody Wed Nov 27 04:55:50 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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([2804:7f0:bdcd:fb00:6501:2693:db52:c621]) by smtp.gmail.com with ESMTPSA id u4-20020a17090282c400b001bb1f0605b2sm1662638plz.214.2023.11.23.10.52.15 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 23 Nov 2023 10:52:17 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1700765538; x=1701370338; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=9L//mA22tIuhmtNLXxG7ubOHdo04CcrNlgyms3DZLTw=; b=Kojnt0CgCfNPMuXK+vS6tEDJDOGQz7VqP1TKHMyJBzOJT1vaXKqTA0RCe7uCXsc3Yb dMYkjGTb4r85070kkQMqwBtGBbu7dooddF7btPrpzASMdmlekUi1RyrOCNRegN2eJAzH GOUn8E44V4bhE1ySe+evINO+PtFgjA0BDaKiiUggfzS0B13u5p5vrOOte0T1TfttrWsq CCMoy3IJzfwsZjYFeZzV804a2aSZyXwXPdqaJt3wRLYHo2GkjkfjdTHzKA4EenXFKZ1c 1B02TCIdbFagFaTrDTcVto0oTxLHTT3vFcDFy8/t9aku7Z0fcDNCBssgf3ZpjqsUsf57 nJRA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1700765538; x=1701370338; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=9L//mA22tIuhmtNLXxG7ubOHdo04CcrNlgyms3DZLTw=; b=cgCj6+MJDdXLPTppMVYHea+fFzFU1Q873ojvwu/KenoyevXwGqPCtfTO8e8cmPAzuK 8nwNeyIrc9pYbgwCuhjJYr5FwKXPAKFGfs776f5HDXrDLqrg9aoNnnaqrnSWVEuqjOZU WRBAfmx4hFa39iUfjvqmAy7+V9ZO38YN7AKrvUehkohTCCbsx/PJ6Myz0KMkFYBvjJNx bxv9XQfAvBwqvBA508maM/CXJOgYXJQdqACEQjeriIalJHW3sUW0VhB92/amQ6iFjRtd 53XucuJRtAA8bLQ2ACLjXj3qXTupgGUPPKE8NcZfcZ34TS0iAgdzJ3/0VS25qUDjJIeo erWQ== X-Gm-Message-State: AOJu0YyET1rJMtC8RnMnKHd4q88PYthIwEx3x1q5sxzfURjS+qZKFicr RB0YTCO4/NfNaF4bIPnJhU4nYNv6ewezJrI1xX4= X-Google-Smtp-Source: AGHT+IHoQ9JmgbeXSsbtC5/9Qfn5xoWcFjc6Fa18UX9leZEif9AXOTWN/WvCfCYePXqkdc9PXmj0+g== X-Received: by 2002:a05:6a20:d388:b0:187:fe09:272a with SMTP id iq8-20020a056a20d38800b00187fe09272amr622527pzb.49.1700765538263; Thu, 23 Nov 2023 10:52:18 -0800 (PST) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, bmeng@tinylab.org, liwei1518@gmail.com, zhiwei_liu@linux.alibaba.com, palmer@rivosinc.com, ajones@ventanamicro.com, Daniel Henrique Barboza Subject: [PATCH for-9.0 v11 16/18] target/riscv/tcg: validate profiles during finalize Date: Thu, 23 Nov 2023 15:51:20 -0300 Message-ID: <20231123185122.1100436-17-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20231123185122.1100436-1-dbarboza@ventanamicro.com> References: <20231123185122.1100436-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::531; envelope-from=dbarboza@ventanamicro.com; helo=mail-pg1-x531.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ventanamicro.com) X-ZM-MESSAGEID: 1700765601562100005 Content-Type: text/plain; charset="utf-8" Enabling a profile and then disabling some of its mandatory extensions is a valid use. It can be useful for debugging and testing. But the common expected use of enabling a profile is to enable all its mandatory extensions. Add an user warning when mandatory extensions from an enabled profile are disabled in the command line. We're also going to disable the profile flag in this case since the profile must include all the mandatory extensions. This flag can be exposed by QMP to indicate the actual profile state after the CPU is realized. After this patch, this will throw warnings: -cpu rv64,rva22u64=3Dtrue,zihintpause=3Dfalse,zicbom=3Dfalse,zicboz=3Dfalse qemu-system-riscv64: warning: Profile rva22u64 mandates disabled extension = zihintpause qemu-system-riscv64: warning: Profile rva22u64 mandates disabled extension = zicbom qemu-system-riscv64: warning: Profile rva22u64 mandates disabled extension = zicboz Note that the following will NOT throw warnings because the profile is being enabled last, hence all its mandatory extensions will be enabled: -cpu rv64,zihintpause=3Dfalse,zicbom=3Dfalse,zicboz=3Dfalse,rva22u64=3Dtrue Signed-off-by: Daniel Henrique Barboza Reviewed-by: Andrew Jones --- target/riscv/tcg/tcg-cpu.c | 69 ++++++++++++++++++++++++++++++++++++++ 1 file changed, 69 insertions(+) diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c index b3bba7887e..6c1e54f540 100644 --- a/target/riscv/tcg/tcg-cpu.c +++ b/target/riscv/tcg/tcg-cpu.c @@ -147,6 +147,26 @@ static int cpu_cfg_ext_get_min_version(uint32_t ext_of= fset) g_assert_not_reached(); } =20 +static const char *cpu_cfg_ext_get_name(uint32_t ext_offset) +{ + const RISCVCPUMultiExtConfig *feat; + const RISCVIsaExtData *edata; + + for (edata =3D isa_edata_arr; edata->name !=3D NULL; edata++) { + if (edata->ext_enable_offset =3D=3D ext_offset) { + return edata->name; + } + } + + for (feat =3D riscv_cpu_named_features; feat->name !=3D NULL; feat++) { + if (feat->offset =3D=3D ext_offset) { + return feat->name; + } + } + + g_assert_not_reached(); +} + static bool cpu_cfg_offset_is_named_feat(uint32_t ext_offset) { const RISCVCPUMultiExtConfig *feat; @@ -732,6 +752,54 @@ void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, = Error **errp) riscv_cpu_disable_priv_spec_isa_exts(cpu); } =20 +static void riscv_cpu_validate_profile(RISCVCPU *cpu, + RISCVCPUProfile *profile) +{ + const char *warn_msg =3D "Profile %s mandates disabled extension %s"; + bool send_warn =3D profile->user_set && profile->enabled; + bool profile_impl =3D true; + int i; + + for (i =3D 0; misa_bits[i] !=3D 0; i++) { + uint32_t bit =3D misa_bits[i]; + + if (!(profile->misa_ext & bit)) { + continue; + } + + if (!riscv_has_ext(&cpu->env, bit)) { + profile_impl =3D false; + + if (send_warn) { + warn_report(warn_msg, profile->name, + riscv_get_misa_ext_name(bit)); + } + } + } + + for (i =3D 0; profile->ext_offsets[i] !=3D RISCV_PROFILE_EXT_LIST_END;= i++) { + int ext_offset =3D profile->ext_offsets[i]; + + if (!isa_ext_is_enabled(cpu, ext_offset)) { + profile_impl =3D false; + + if (send_warn) { + warn_report(warn_msg, profile->name, + cpu_cfg_ext_get_name(ext_offset)); + } + } + } + + profile->enabled =3D profile_impl; +} + +static void riscv_cpu_validate_profiles(RISCVCPU *cpu) +{ + for (int i =3D 0; riscv_profiles[i] !=3D NULL; i++) { + riscv_cpu_validate_profile(cpu, riscv_profiles[i]); + } +} + void riscv_tcg_cpu_finalize_features(RISCVCPU *cpu, Error **errp) { CPURISCVState *env =3D &cpu->env; @@ -750,6 +818,7 @@ void riscv_tcg_cpu_finalize_features(RISCVCPU *cpu, Err= or **errp) } =20 riscv_cpu_validate_named_features(cpu); + riscv_cpu_validate_profiles(cpu); =20 if (cpu->cfg.ext_smepmp && !cpu->cfg.pmp) { /* --=20 2.41.0 From nobody Wed Nov 27 04:55:50 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1700765653; cv=none; d=zohomail.com; s=zohoarc; b=Z3GJoeu2ZYakxIt4nK0Uyv58ISiwLNb+5qUdCggGcAHMc49ZkzQDLaazN5VDEKGuiTk8QN+rPsXLHh105ymyvZ7BdlUPYT7Sz2FexlGJj7Mn5jRijIe56267tMfj0w0BSZfpEmcuUbHAyBEDnXAQu+Kvo5BQDdBTWxoVrGueTjA= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1700765653; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=54Kf0rAoudsnnoVt4nlQX6I3ltS6TlxVzrnjj9HiVnE=; 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([2804:7f0:bdcd:fb00:6501:2693:db52:c621]) by smtp.gmail.com with ESMTPSA id u4-20020a17090282c400b001bb1f0605b2sm1662638plz.214.2023.11.23.10.52.18 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 23 Nov 2023 10:52:20 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1700765541; x=1701370341; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=54Kf0rAoudsnnoVt4nlQX6I3ltS6TlxVzrnjj9HiVnE=; b=clvhSzBp3LmYz606VTCvE73t7jGL7w46WsSvXAGyGonxuRgY7x4LEZ3qICuP+BbZeQ rC5ERuDD+H+xtHtKSgov4xPVGpiPbn1nN6Ax/tZlYKnP96PZhNuDV1wywbvJQeBfiSej 1dFHqvRktfoQUA4IjhZw9RbJzkPSOBnAR/iCV7Zn/NV3sd8Jz7WKjkTTAVVQ1//dDjpi YnImzgAtFcM2gmEV/X2v3wEM6EGdppq5QBNVyFQLjQ+//sSW6YHY9Kc/UmN2bJBOTHid qG3zExSMLzWZtwRpLA8oS73JxhUQlBr2ZRZCzWe6wIZ/DUu1EVfXzdztB4v4NDwp6oHF H7Rw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1700765541; x=1701370341; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=54Kf0rAoudsnnoVt4nlQX6I3ltS6TlxVzrnjj9HiVnE=; b=h9ZgLQUGFjJFa4hgoz1QOKIKCNaJhPbfdPx/I4UhNBcFnHeTiaPP0QDeOPRdKsNUcQ L3ZlTfFYhV26+QIHVHs/L6vxbgVUMVbhGSLVJazqO/nUUJddxAkHsMbH8VwyM1riFVzn K4544Mqp5gfWj8db/9B8m11Ly1wS/RJHFv7eqDAWgiNJO9miQK7ejXey2c+w+Ajy/OvJ IGWggkNkih5kzB6ccFHk7ChTJuM8FkPSLqV89LPhuHNFFVvLqTOtQIp3u56dl6vPSlvz jurwc3RnZTQB+wmoA7C8bypLyiTC9MCwv4mMBxPDSJ+DB+y5pWvb2IrzCUFuXycV/4Ui zYVA== X-Gm-Message-State: AOJu0Yyf66Wy9IdNMcZ/YrFE9MYfOvKpjygZleQqtuPpYTeCcFxSwy4a 8WdXXEmXSfFDDOc9rxQGZmK72VotpYkehvi0Jzk= X-Google-Smtp-Source: AGHT+IEKuuzMXbhg9U+DhK3svfaQaayUIV4fPUGI/OUHnmCPUdARvUGiOGyQFLuQqOmlMMruLZbgbw== X-Received: by 2002:a17:902:e5c6:b0:1cf:8df8:3d08 with SMTP id u6-20020a170902e5c600b001cf8df83d08mr348873plf.27.1700765541241; Thu, 23 Nov 2023 10:52:21 -0800 (PST) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, bmeng@tinylab.org, liwei1518@gmail.com, zhiwei_liu@linux.alibaba.com, palmer@rivosinc.com, ajones@ventanamicro.com, Daniel Henrique Barboza Subject: [PATCH for-9.0 v11 17/18] riscv-qmp-cmds.c: add profile flags in cpu-model-expansion Date: Thu, 23 Nov 2023 15:51:21 -0300 Message-ID: <20231123185122.1100436-18-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20231123185122.1100436-1-dbarboza@ventanamicro.com> References: <20231123185122.1100436-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::62d; envelope-from=dbarboza@ventanamicro.com; helo=mail-pl1-x62d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ventanamicro.com) X-ZM-MESSAGEID: 1700765653887100001 Content-Type: text/plain; charset="utf-8" Expose all profile flags for all CPUs when executing query-cpu-model-expansion. This will allow callers to quickly determine if a certain profile is implemented by a given CPU. This includes vendor CPUs - the fact that they don't have profile user flags doesn't mean that they don't implement the profile. After this change it's possible to quickly determine if our stock CPUs implement the existing rva22u64 profile. Here's a few examples: $ ./build/qemu-system-riscv64 -S -M virt -display none -qmp tcp:localhost:1234,server,wait=3Doff $ ./scripts/qmp/qmp-shell localhost:1234 Welcome to the QMP low-level shell! Connected to QEMU 8.1.50 - As expected, the 'max' CPU implements the rva22u64 profile. (QEMU) query-cpu-model-expansion type=3Dfull model=3D{"name":"max"} {"return": {"model": {"name": "rv64", "props": {... "rva22u64": true, ...}}}} - rv64 is missing "zba", "zbb", "zbs", "zkt" and "zfhmin": query-cpu-model-expansion type=3Dfull model=3D{"name":"rv64"} {"return": {"model": {"name": "rv64", "props": {... "rva22u64": false, ...}}}} query-cpu-model-expansion type=3Dfull model=3D{"name":"rv64", "props":{"zba":true,"zbb":true,"zbs":true,"zkt":true,"zfhmin":true}} {"return": {"model": {"name": "rv64", "props": {... "rva22u64": true, ...}}}} We have no vendor CPUs that supports rva22u64 (veyron-v1 is the closest - it is missing just 'zkt'). In short, aside from the 'max' CPU, we have no CPUs that supports rva22u64 by default. Signed-off-by: Daniel Henrique Barboza Reviewed-by: Andrew Jones --- target/riscv/riscv-qmp-cmds.c | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/target/riscv/riscv-qmp-cmds.c b/target/riscv/riscv-qmp-cmds.c index 5ada279776..205aaabeb9 100644 --- a/target/riscv/riscv-qmp-cmds.c +++ b/target/riscv/riscv-qmp-cmds.c @@ -116,6 +116,19 @@ static void riscv_obj_add_named_feats_qdict(Object *ob= j, QDict *qdict_out) } } =20 +static void riscv_obj_add_profiles_qdict(Object *obj, QDict *qdict_out) +{ + RISCVCPUProfile *profile; + QObject *value; + + for (int i =3D 0; riscv_profiles[i] !=3D NULL; i++) { + profile =3D riscv_profiles[i]; + value =3D QOBJECT(qbool_from_bool(profile->enabled)); + + qdict_put_obj(qdict_out, profile->name, value); + } +} + static void riscv_cpuobj_validate_qdict_in(Object *obj, QObject *props, const QDict *qdict_in, Error **errp) @@ -220,6 +233,7 @@ CpuModelExpansionInfo *qmp_query_cpu_model_expansion(Cp= uModelExpansionType type, riscv_obj_add_multiext_props(obj, qdict_out, riscv_cpu_experimental_ex= ts); riscv_obj_add_multiext_props(obj, qdict_out, riscv_cpu_vendor_exts); riscv_obj_add_named_feats_qdict(obj, qdict_out); + riscv_obj_add_profiles_qdict(obj, qdict_out); =20 /* Add our CPU boolean options too */ riscv_obj_add_qdict_prop(obj, qdict_out, "mmu"); --=20 2.41.0 From nobody Wed Nov 27 04:55:50 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1700765612; cv=none; d=zohomail.com; s=zohoarc; b=HefG+tf54V1HHaT1R/5JHYO4iSv2E73DIzZFh7YJk/EmnoXly3a7tEt9CtTNITlemXCYJxg9cOS4ko2x2zyDHYeruimpyJ2t8l4LA2Cb3/r3bUdHgGiAsi0tdEEiFcxdnNmopN7NQHzNqcH+yPbHhwWulFoMQAFN29HfjjpC31Q= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1700765612; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=nIxFD40eOKN1PL7rHkZiTo9EZaqwS4IrnfEmvy9eNNo=; b=Q3eEakhkLXg85UHT+sIKSftxi+Y9vzFt7sTK5PpeuyJ7qSFRLVbaVPhfp96tbvj46U7ExvZSiNYxNHGzO3n3dKmZs++2MQODgUCjga1+/MEJ9pVWxeZriNWTKZA23BD4BCmbTudHGI6OiLU/Hc/hDl3dIWXycXrT+PXLTZj2puU= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1700765612741819.1933986629381; Thu, 23 Nov 2023 10:53:32 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1r6EoP-0000jS-DM; Thu, 23 Nov 2023 13:52:29 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1r6EoO-0000ib-8Q for qemu-devel@nongnu.org; Thu, 23 Nov 2023 13:52:28 -0500 Received: from mail-pl1-x636.google.com ([2607:f8b0:4864:20::636]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1r6EoM-0000HH-Ha for qemu-devel@nongnu.org; Thu, 23 Nov 2023 13:52:28 -0500 Received: by mail-pl1-x636.google.com with SMTP id d9443c01a7336-1cf61eed213so9526435ad.2 for ; Thu, 23 Nov 2023 10:52:26 -0800 (PST) Received: from grind.. ([2804:7f0:bdcd:fb00:6501:2693:db52:c621]) by smtp.gmail.com with ESMTPSA id u4-20020a17090282c400b001bb1f0605b2sm1662638plz.214.2023.11.23.10.52.21 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 23 Nov 2023 10:52:23 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1700765544; x=1701370344; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=nIxFD40eOKN1PL7rHkZiTo9EZaqwS4IrnfEmvy9eNNo=; b=CBufSK6b7xKpOtfqwzY2as76qk6ZJuxlaNNqr/sMwzjb2CutycyCILoMKMZYNjJlwi vmOGH0z0GUjPGj/mgft6ue53DfbU4L7JdcshcT5RMqxjkrBPodm4VnIjgFrEPDlZYCpU Oi3CIXYyxF5uY5eoOYMkmM6vDFaCQ2nNJUsqUJdgwEEIiOrH1iBdFOOyZdzUD13EiNS2 /Q3AnECi/0hyl2Ui/rxMlP/CgX6VE73ATjdbwehYVeMDn0PtMXjZ32deE+FeVefBN8gr GBWPKrub5MswsSJiY8RH+pDIPN/4zm9lP2OrH0Bakdkepbq0hQjsO4JmWvJMfEWymjZD W9Og== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1700765544; x=1701370344; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=nIxFD40eOKN1PL7rHkZiTo9EZaqwS4IrnfEmvy9eNNo=; b=lUuTY6rWqbEg+7gP1q/t5cz7u30vge78IlYI1JZVlWQLi9AfIldCyGyVXIc0eLOYJ5 gRtXykhVem4vqWvI1H1ABSxdcSXc410kJdYKTy6wNgeseCZBzgKb35MTfyObKzuao+nF IibkUB8lr41ksP7C1BfwWI1fgsqA9Xh+hTVg2pdlbM218WzJQftwwms9UTLhJ5Vm7BUs BjyzUN9A3MLVSwkvt3AtF327iIgPA4zclhRpqINtMTb5PEXBTnuQiqKD8X+TZOvjr7yX CnZLIbN8KiFC7usbcNf+N9H5Tnr2Zz5TVKEc23mu/y9DhKsP7x2bz6e3gDSUAq2fhjzL 3fLA== X-Gm-Message-State: AOJu0YwvoWMygofDM4TDn1DqaN4QkYqkigi7WDnoWW1RlwNBB+xeGHeE 4YfuP2Jk6k9J8i8AwRf5uz6dat40uioQXrW33c4= X-Google-Smtp-Source: AGHT+IEfxiCO+2H3NuqbXwl7NGNGPC6eLlXrcp8idnvqykavA9HPP+t3OrWdaBW8ZWiDJ5ohAc9u4g== X-Received: by 2002:a17:902:cec7:b0:1cf:8e9e:8812 with SMTP id d7-20020a170902cec700b001cf8e9e8812mr429223plg.21.1700765544331; Thu, 23 Nov 2023 10:52:24 -0800 (PST) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, bmeng@tinylab.org, liwei1518@gmail.com, zhiwei_liu@linux.alibaba.com, palmer@rivosinc.com, ajones@ventanamicro.com, Daniel Henrique Barboza Subject: [PATCH for-9.0 v11 18/18] target/riscv: add 'rva22u64' CPU Date: Thu, 23 Nov 2023 15:51:22 -0300 Message-ID: <20231123185122.1100436-19-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20231123185122.1100436-1-dbarboza@ventanamicro.com> References: <20231123185122.1100436-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::636; envelope-from=dbarboza@ventanamicro.com; helo=mail-pl1-x636.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ventanamicro.com) X-ZM-MESSAGEID: 1700765613613100001 Content-Type: text/plain; charset="utf-8" This CPU was suggested by Alistair [1] and others during the profile design discussions. It consists of the bare 'rv64i' CPU with rva22u64 enabled by default, like an alias of '-cpu rv64i,rva22u64=3Dtrue'. Users now have an even easier way of consuming this user-mode profile by doing '-cpu rva22u64'. Extensions can be enabled/disabled at will on top of it. We can boot Linux with this "user-mode" CPU by doing: -cpu rva22u64,sv39=3Dtrue,s=3Dtrue,zifencei=3Dtrue [1] https://lore.kernel.org/qemu-riscv/CAKmqyKP7xzZ9Sx=3D-Lbx2Ob0qCfB7Z+JO9= 44FQ2TQ+49mqo0q_Q@mail.gmail.com/ Signed-off-by: Daniel Henrique Barboza Reviewed-by: Andrew Jones --- target/riscv/cpu-qom.h | 1 + target/riscv/cpu.c | 17 +++++++++++++++++ target/riscv/tcg/tcg-cpu.c | 9 +++++++++ 3 files changed, 27 insertions(+) diff --git a/target/riscv/cpu-qom.h b/target/riscv/cpu-qom.h index 4d1aa54311..12fe78fc52 100644 --- a/target/riscv/cpu-qom.h +++ b/target/riscv/cpu-qom.h @@ -35,6 +35,7 @@ #define TYPE_RISCV_CPU_BASE64 RISCV_CPU_TYPE_NAME("rv64") #define TYPE_RISCV_CPU_BASE128 RISCV_CPU_TYPE_NAME("x-rv128") #define TYPE_RISCV_CPU_RV64I RISCV_CPU_TYPE_NAME("rv64i") +#define TYPE_RISCV_CPU_RVA22U64 RISCV_CPU_TYPE_NAME("rva22u64") #define TYPE_RISCV_CPU_IBEX RISCV_CPU_TYPE_NAME("lowrisc-ibex") #define TYPE_RISCV_CPU_SHAKTI_C RISCV_CPU_TYPE_NAME("shakti-c") #define TYPE_RISCV_CPU_SIFIVE_E31 RISCV_CPU_TYPE_NAME("sifive-e31") diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index f2be40ae21..3a230608cb 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -1576,6 +1576,15 @@ static Property riscv_cpu_properties[] =3D { DEFINE_PROP_END_OF_LIST(), }; =20 +#if defined(TARGET_RISCV64) +static void rva22u64_profile_cpu_init(Object *obj) +{ + rv64i_bare_cpu_init(obj); + + RVA22U64.enabled =3D true; +} +#endif + static const gchar *riscv_gdb_arch_name(CPUState *cs) { RISCVCPU *cpu =3D RISCV_CPU(cs); @@ -1866,6 +1875,13 @@ void riscv_cpu_list(void) .instance_init =3D initfn \ } =20 +#define DEFINE_PROFILE_CPU(type_name, initfn) \ + { \ + .name =3D type_name, \ + .parent =3D TYPE_RISCV_BARE_CPU, \ + .instance_init =3D initfn \ + } + static const TypeInfo riscv_cpu_type_infos[] =3D { { .name =3D TYPE_RISCV_CPU, @@ -1910,6 +1926,7 @@ static const TypeInfo riscv_cpu_type_infos[] =3D { DEFINE_VENDOR_CPU(TYPE_RISCV_CPU_VEYRON_V1, rv64_veyron_v1_cpu_init), DEFINE_DYNAMIC_CPU(TYPE_RISCV_CPU_BASE128, rv128_base_cpu_init), DEFINE_BARE_CPU(TYPE_RISCV_CPU_RV64I, rv64i_bare_cpu_init), + DEFINE_PROFILE_CPU(TYPE_RISCV_CPU_RVA22U64, rva22u64_profile_cpu_init), #endif }; =20 diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c index 6c1e54f540..8fa8d61142 100644 --- a/target/riscv/tcg/tcg-cpu.c +++ b/target/riscv/tcg/tcg-cpu.c @@ -1100,6 +1100,15 @@ static void riscv_cpu_add_profiles(Object *cpu_obj) object_property_add(cpu_obj, profile->name, "bool", cpu_get_profile, cpu_set_profile, NULL, (void *)profile); + + /* + * CPUs might enable a profile right from the start. + * Enable its mandatory extensions right away in this + * case. + */ + if (profile->enabled) { + object_property_set_bool(cpu_obj, profile->name, true, NULL); + } } } =20 --=20 2.41.0