Hi,

This series adds canonical/bare bones RISC-V CPUs in QEMU. The idea is
to allow users to create a CPU from scratch without having to deal/disable
existing defaults. 

A bare-bones CPU will avoid scenarios like the one described here:

https://lore.kernel.org/qemu-riscv/258be47f-97be-4308-bed5-dc34ef7ff954@Spark/

Where one has to disable a bunch of defaults from the rv32 CPU to be
able to use the desired configuration. After this series, the case from
the link above:

-cpu rv32,g=false,f=false,v=false,d=false,e=false,h=false,(... desired
setup)

Will be expressed as:

-cpu rv32i,(... desired setup)

Note that the idea isn't new. The rv64i CPU was already presented in the
rva22u64 profile series [1]. That series didn't make it for 8.2, so I'm
picking patches 1-4 (already reviewed and acked) and re-posting for this
work. In case this series is accepted first I'll rebase and re-send the
profile series.

I'm also adding RVE CPUs, rv32e and rv64e. The reason is that we can't
enable I and E at the same time, and all default CPUs has I by default,
so we would need to do something like 'r32i,i=false,e=true' to have a
base RVE 32 bit CPU.

[1] https://lore.kernel.org/qemu-riscv/20231103134629.561732-1-dbarboza@ventanamicro.com/

Daniel Henrique Barboza (6):
  target/riscv: create TYPE_RISCV_VENDOR_CPU
  target/riscv/tcg: do not use "!generic" CPU checks
  target/riscv/tcg: update priv_ver on user_set extensions
  target/riscv: add rv64i CPU
  target/riscv: add rv32i CPU
  target/riscv: add rv32e/rv64e CPUs

 target/riscv/cpu-qom.h     |   6 ++
 target/riscv/cpu.c         | 145 ++++++++++++++++++++++++++++++++++---
 target/riscv/tcg/tcg-cpu.c |  45 +++++++++++-
 3 files changed, 183 insertions(+), 13 deletions(-)

-- 
2.41.0