From nobody Wed Nov 27 07:40:46 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1699911608; cv=none; d=zohomail.com; s=zohoarc; b=JG5X5YsNyv6GCzQsiaJSXmacs0pz+8ku5q2nHyosUTxJmWSjs+WWZ+Z7IJ7k8ZnX0Eudp1JUvPDJxMuchCtY12S6GPzuR13PRM5SWwrLWtnCBxdyX5DzabtC2z65pYgjQfCLo08qXaNA3sdxMKiv3jm8YAZl02eumDCR7KLepx8= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1699911608; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=g27N76GsCjcJjpEII+LykYnwIqcFv/pUM+HDkvpl0o4=; b=J7xc9HUY+BHG+r/6FVNyF0vJjvjkdubhz+fh1UEOH52ysqfFPMYg6weHeNOF7pGqf0ZACtGWTnLnJlVQtn+KrH0xmkHWvtZdnpa+WY0LQL+0cpHzjeTqiQr4FZx7mqdOWsJUlAjpFaOplFzGl0te7b0fOqDKHomiQadvgsYcd7A= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1699911608214332.38284936252137; Mon, 13 Nov 2023 13:40:08 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1r2eeS-00066H-BL; Mon, 13 Nov 2023 16:39:24 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1r2eeQ-000659-8n for qemu-devel@nongnu.org; Mon, 13 Nov 2023 16:39:22 -0500 Received: from mail-pl1-x62c.google.com ([2607:f8b0:4864:20::62c]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1r2eeO-0001Sq-JE for qemu-devel@nongnu.org; Mon, 13 Nov 2023 16:39:22 -0500 Received: by mail-pl1-x62c.google.com with SMTP id d9443c01a7336-1ce28faa92dso11590455ad.2 for ; Mon, 13 Nov 2023 13:39:20 -0800 (PST) Received: from grind.. ([152.250.131.148]) by smtp.gmail.com with ESMTPSA id a6-20020a170902900600b001c736746d33sm4455423plp.217.2023.11.13.13.39.16 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 13 Nov 2023 13:39:18 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1699911559; x=1700516359; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=g27N76GsCjcJjpEII+LykYnwIqcFv/pUM+HDkvpl0o4=; b=ixeY9WKxrx0jRYmDfPXKAf2qELJFwRKPaPdhjclQTNWlXbiFOxikrkMS5SpCWr2xQs oJ4TIsXRMKB7RIyrjImBriCDBFPjfGebF8Mqr02PoR/1Ax7kOlzpcxTeCkNP/bUcnjQX bF8d1DcFICypkw81AFFuydNZE/9v3h/QdjLidxLFtkJGDl0XQKZLq1KXpg2Lp2OL8Kf/ Hne1sjMM1iM3iyv2Sb6w+x+DT7pvFp5ykKDNnCmM2xzkBD683DCzZTEDRNN1WuTqLPOu oboLMWvZRPQF3slYZLPq2gCr6bmFlY9OO9x7bEV0gC/OITNk3nz0HCkCkzqtgx5ztlaw mhSA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1699911559; x=1700516359; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=g27N76GsCjcJjpEII+LykYnwIqcFv/pUM+HDkvpl0o4=; b=v4hHScm2QflwIS3tzbJfwkJqgVG/f8NDqrnYuoE6/zNvzvrVwt89nAKNHvd5ckJmOX 6haa9LuAefhKPa8odfJk9Ricc6jhta2MyZboCTLmdKA/h0UeZ1GLzO2w2sn3JN4Fi3za 9xgiTf/KQB9bADiMwpSkhnqv2JZSX3irU+D+OfaBF0lvU2Bd7s1xeg5prkANiOl0l/EZ saXNli5lHK+er67NkUihRQ1kO/7KI/6alG7qVD2uVZTvz1vtacz85Esz+uLPWA3Rp3XW xbuxSYfRxOr+cy+J8wTEtpBAuim11jlK6XBdLE3JvHh/h6taU/6xoEEsLliRHJhkGxYz pSdQ== X-Gm-Message-State: AOJu0Yx6FRXDFrzU30LVP9WkTTx1m8q8GyHBBlEN8VFM+iXwRFa6l3e6 J1Djjy4sxqfL5q8LrqFKbMJPrq1Fr31lw2I72jM= X-Google-Smtp-Source: AGHT+IH/WzXaOEhniUkigQkBS3d7fJEPkHvF86t/e4arqFbFG7J+8T2he5m8ddqiQkJqfXYanz9WdA== X-Received: by 2002:a17:903:25d5:b0:1cc:50ea:d5c5 with SMTP id jc21-20020a17090325d500b001cc50ead5c5mr514103plb.24.1699911558990; Mon, 13 Nov 2023 13:39:18 -0800 (PST) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, bmeng@tinylab.org, liwei1518@gmail.com, zhiwei_liu@linux.alibaba.com, palmer@rivosinc.com, Daniel Henrique Barboza , Andrew Jones Subject: [PATCH for-9.0 1/6] target/riscv: create TYPE_RISCV_VENDOR_CPU Date: Mon, 13 Nov 2023 18:38:59 -0300 Message-ID: <20231113213904.185320-2-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20231113213904.185320-1-dbarboza@ventanamicro.com> References: <20231113213904.185320-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::62c; envelope-from=dbarboza@ventanamicro.com; helo=mail-pl1-x62c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ventanamicro.com) X-ZM-MESSAGEID: 1699911609199100001 Content-Type: text/plain; charset="utf-8" We want to add a new CPU type for bare CPUs that will inherit specific traits of the 2 existing types: - it will allow for extensions to be enabled/disabled, like generic CPUs; - it will NOT inherit defaults, like vendor CPUs. We can make this conditions met by adding an explicit type for the existing vendor CPUs and change the existing logic to not imply that "not generic" means vendor CPUs. Let's add the "vendor" CPU type first. Signed-off-by: Daniel Henrique Barboza Reviewed-by: Andrew Jones Reviewed-by: Alistair Francis --- target/riscv/cpu-qom.h | 1 + target/riscv/cpu.c | 30 +++++++++++++++++++++--------- 2 files changed, 22 insertions(+), 9 deletions(-) diff --git a/target/riscv/cpu-qom.h b/target/riscv/cpu-qom.h index 91b3361dec..ca7dd509e3 100644 --- a/target/riscv/cpu-qom.h +++ b/target/riscv/cpu-qom.h @@ -23,6 +23,7 @@ =20 #define TYPE_RISCV_CPU "riscv-cpu" #define TYPE_RISCV_DYNAMIC_CPU "riscv-dynamic-cpu" +#define TYPE_RISCV_VENDOR_CPU "riscv-vendor-cpu" =20 #define RISCV_CPU_TYPE_SUFFIX "-" TYPE_RISCV_CPU #define RISCV_CPU_TYPE_NAME(name) (name RISCV_CPU_TYPE_SUFFIX) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 83c7c0cf07..220113408e 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -1778,6 +1778,13 @@ void riscv_cpu_list(void) .instance_init =3D initfn \ } =20 +#define DEFINE_VENDOR_CPU(type_name, initfn) \ + { \ + .name =3D type_name, \ + .parent =3D TYPE_RISCV_VENDOR_CPU, \ + .instance_init =3D initfn \ + } + static const TypeInfo riscv_cpu_type_infos[] =3D { { .name =3D TYPE_RISCV_CPU, @@ -1795,21 +1802,26 @@ static const TypeInfo riscv_cpu_type_infos[] =3D { .parent =3D TYPE_RISCV_CPU, .abstract =3D true, }, + { + .name =3D TYPE_RISCV_VENDOR_CPU, + .parent =3D TYPE_RISCV_CPU, + .abstract =3D true, + }, DEFINE_DYNAMIC_CPU(TYPE_RISCV_CPU_ANY, riscv_any_cpu_init), DEFINE_DYNAMIC_CPU(TYPE_RISCV_CPU_MAX, riscv_max_cpu_init), #if defined(TARGET_RISCV32) DEFINE_DYNAMIC_CPU(TYPE_RISCV_CPU_BASE32, rv32_base_cpu_init), - DEFINE_CPU(TYPE_RISCV_CPU_IBEX, rv32_ibex_cpu_init), - DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E31, rv32_sifive_e_cpu_init), - DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E34, rv32_imafcu_nommu_cpu_init= ), - DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_U34, rv32_sifive_u_cpu_init), + DEFINE_VENDOR_CPU(TYPE_RISCV_CPU_IBEX, rv32_ibex_cpu_init), + DEFINE_VENDOR_CPU(TYPE_RISCV_CPU_SIFIVE_E31, rv32_sifive_e_cpu_init), + DEFINE_VENDOR_CPU(TYPE_RISCV_CPU_SIFIVE_E34, rv32_imafcu_nommu_cpu_in= it), + DEFINE_VENDOR_CPU(TYPE_RISCV_CPU_SIFIVE_U34, rv32_sifive_u_cpu_init), #elif defined(TARGET_RISCV64) DEFINE_DYNAMIC_CPU(TYPE_RISCV_CPU_BASE64, rv64_base_cpu_init), - DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E51, rv64_sifive_e_cpu_init), - DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_U54, rv64_sifive_u_cpu_init), - DEFINE_CPU(TYPE_RISCV_CPU_SHAKTI_C, rv64_sifive_u_cpu_init), - DEFINE_CPU(TYPE_RISCV_CPU_THEAD_C906, rv64_thead_c906_cpu_init), - DEFINE_CPU(TYPE_RISCV_CPU_VEYRON_V1, rv64_veyron_v1_cpu_init), + DEFINE_VENDOR_CPU(TYPE_RISCV_CPU_SIFIVE_E51, rv64_sifive_e_cpu_init), + DEFINE_VENDOR_CPU(TYPE_RISCV_CPU_SIFIVE_U54, rv64_sifive_u_cpu_init), + DEFINE_VENDOR_CPU(TYPE_RISCV_CPU_SHAKTI_C, rv64_sifive_u_cpu_init), + DEFINE_VENDOR_CPU(TYPE_RISCV_CPU_THEAD_C906, rv64_thead_c906_cpu_init= ), + DEFINE_VENDOR_CPU(TYPE_RISCV_CPU_VEYRON_V1, rv64_veyron_v1_cpu_init), DEFINE_DYNAMIC_CPU(TYPE_RISCV_CPU_BASE128, rv128_base_cpu_init), #endif }; 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([152.250.131.148]) by smtp.gmail.com with ESMTPSA id a6-20020a170902900600b001c736746d33sm4455423plp.217.2023.11.13.13.39.19 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 13 Nov 2023 13:39:21 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1699911562; x=1700516362; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=jmMujTAnDCnLNQCIKB7A1R2XebVoD2eMHYsCnu9fyhk=; b=O02OGq8InUtk1FbDVI1FCuiIhoDCO+IM0SWZ2vAjkBfstSYR05O8EDcJgMubSU2R29 Of40NHhI9Ev2S8eWcT16kEal8aA9H4rZ4/PT/I++oAPpd08BtCG/ik6gvGpm033xkJVk 60LN+ggXV+yNkj7L+LUPmiTUDuy83pCvBaUZk1CgcQi/bxSDuzjqXfeQTeg1gNSEQzki u9ZvZP1P2RFajh9K+ieGjWh6VnGrk4DOulFswchO+9VTdL1R3MWbcf8d4lLlASk7fHAk 7O84cNGAgXK//oXKnvdUvyXToG4NrL/bhjaJnDPAJKchbuntPlBps1FV3K/+hQMvPTmU tcRg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1699911562; x=1700516362; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=jmMujTAnDCnLNQCIKB7A1R2XebVoD2eMHYsCnu9fyhk=; b=giZY76XvecD4hJQx7RCxjJOIMz4EmBM7v+cFivq7aYlJIhrJuxD+pXr2/yCZIW+ZO3 nvEndsTRnI4RXX/g88Rjux17lxm76hs1Pqm1fxL3Zait/WDTSY5Vsp5yA8B0z2L8eOb1 zK50mRIKustJ5y1N4ye1O/8wHyL4lZTVs065Q7qFfGnv/4AnmolE74xia2mlDXIth3Sq aRZG+CruRuS6d9KBBaF8XKdR+9qhAEp4SVCKLHySvSIFyu3+CyglClqrhe7CEOIgLNUD 09n0hs3QlLKrokaw26BYMB+6REKAf3LIy3J+gp574FjUnDUctWicS/bFqFsxLqiIQgTf nkvA== X-Gm-Message-State: AOJu0YzwetPOB1DSWNau7+rw7cTwV1rrga8+huYltABkcbnqxjDfXEm7 cbGumBoB+4QTv+2swN7lj3DQBKw52qcD4axjG20= X-Google-Smtp-Source: AGHT+IFtumLXoXJHE5GgejqeRFnAxZ34EQZzDRBdIuMBq+5FIfAHHtsEfIaCBgZ9t/Od0Z1n5CA+0A== X-Received: by 2002:a17:902:a403:b0:1c9:aac5:df30 with SMTP id p3-20020a170902a40300b001c9aac5df30mr419352plq.66.1699911561886; Mon, 13 Nov 2023 13:39:21 -0800 (PST) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, bmeng@tinylab.org, liwei1518@gmail.com, zhiwei_liu@linux.alibaba.com, palmer@rivosinc.com, Daniel Henrique Barboza , Andrew Jones Subject: [PATCH for-9.0 2/6] target/riscv/tcg: do not use "!generic" CPU checks Date: Mon, 13 Nov 2023 18:39:00 -0300 Message-ID: <20231113213904.185320-3-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20231113213904.185320-1-dbarboza@ventanamicro.com> References: <20231113213904.185320-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::62a; envelope-from=dbarboza@ventanamicro.com; helo=mail-pl1-x62a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ventanamicro.com) X-ZM-MESSAGEID: 1699911678934100001 Content-Type: text/plain; charset="utf-8" Our current logic in get/setters of MISA and multi-letter extensions works because we have only 2 CPU types, generic and vendor, and by using "!generic" we're implying that we're talking about vendor CPUs. When adding a third CPU type this logic will break so let's handle it beforehand. In set_misa_ext_cfg() and set_multi_ext_cfg(), check for "vendor" cpu inste= ad of "not generic". The "generic CPU" checks remaining are from riscv_cpu_add_misa_properties() and cpu_add_multi_ext_prop() before applying default values for the extensions. This leaves us with: - vendor CPUs will not allow extension enablement, all other CPUs will; - generic CPUs will inherit default values for extensions, all others won't. And now we can add a new, third CPU type, that will allow extensions to be enabled and will not inherit defaults, without changing the existing logic. Signed-off-by: Daniel Henrique Barboza Reviewed-by: Andrew Jones Reviewed-by: Alistair Francis --- target/riscv/tcg/tcg-cpu.c | 13 +++++++++---- 1 file changed, 9 insertions(+), 4 deletions(-) diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c index 08adad304d..304211169e 100644 --- a/target/riscv/tcg/tcg-cpu.c +++ b/target/riscv/tcg/tcg-cpu.c @@ -654,6 +654,11 @@ static bool riscv_cpu_is_generic(Object *cpu_obj) return object_dynamic_cast(cpu_obj, TYPE_RISCV_DYNAMIC_CPU) !=3D NULL; } =20 +static bool riscv_cpu_is_vendor(Object *cpu_obj) +{ + return object_dynamic_cast(cpu_obj, TYPE_RISCV_VENDOR_CPU) !=3D NULL; +} + /* * We'll get here via the following path: * @@ -722,7 +727,7 @@ static void cpu_set_misa_ext_cfg(Object *obj, Visitor *= v, const char *name, target_ulong misa_bit =3D misa_ext_cfg->misa_bit; RISCVCPU *cpu =3D RISCV_CPU(obj); CPURISCVState *env =3D &cpu->env; - bool generic_cpu =3D riscv_cpu_is_generic(obj); + bool vendor_cpu =3D riscv_cpu_is_vendor(obj); bool prev_val, value; =20 if (!visit_type_bool(v, name, &value, errp)) { @@ -736,7 +741,7 @@ static void cpu_set_misa_ext_cfg(Object *obj, Visitor *= v, const char *name, } =20 if (value) { - if (!generic_cpu) { + if (vendor_cpu) { g_autofree char *cpuname =3D riscv_cpu_get_name(cpu); error_setg(errp, "'%s' CPU does not allow enabling extensions", cpuname); @@ -841,7 +846,7 @@ static void cpu_set_multi_ext_cfg(Object *obj, Visitor = *v, const char *name, { const RISCVCPUMultiExtConfig *multi_ext_cfg =3D opaque; RISCVCPU *cpu =3D RISCV_CPU(obj); - bool generic_cpu =3D riscv_cpu_is_generic(obj); + bool vendor_cpu =3D riscv_cpu_is_vendor(obj); bool prev_val, value; =20 if (!visit_type_bool(v, name, &value, errp)) { @@ -865,7 +870,7 @@ static void cpu_set_multi_ext_cfg(Object *obj, Visitor = *v, const char *name, return; } =20 - if (value && !generic_cpu) { + if (value && vendor_cpu) { g_autofree char *cpuname =3D riscv_cpu_get_name(cpu); error_setg(errp, "'%s' CPU does not allow enabling extensions", cpuname); --=20 2.41.0 From nobody Wed Nov 27 07:40:46 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1699911673; cv=none; d=zohomail.com; s=zohoarc; b=ZKqFumOcAxLkY+ycSN6U2W1dVpq6nhsZ1/ta5GbM7p2sx4PUIofiKV8w6XKdX0lw9rbPvQ3DDpJpgJNR8sQQ7LnNfM1OJyyq97FO37SxLjufxHDAmgljyAxxNMeCq9LpGajsN3b4gI/liKlk7+Z+3sYxAYJpK7JCgA+2swnGLDU= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1699911673; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=0cYVqzO8TRpxKmALsybQRSCPXQl71TGGunhIS2IHSCc=; b=PFHJTXmvU4DCQPK70rGgAfCByXTlFbK9rDPhO9O6BE5L3hC67d+Mio+TX+GxB3+yf2CpRGN5kS3hSV9ZEaU/kKymJKnQeOWGtmHPF7Vz8QxJvnBC2yKV7iQ7I57hGhEGI57KMnl/2D6f+Nb0MY5joaE/GyDYTgbQjIaWO2LbERs= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1699911673619101.67568948893916; Mon, 13 Nov 2023 13:41:13 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1r2eeZ-00067u-2Y; Mon, 13 Nov 2023 16:39:31 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1r2eeX-00067m-Vo for qemu-devel@nongnu.org; Mon, 13 Nov 2023 16:39:30 -0500 Received: from mail-pf1-x431.google.com ([2607:f8b0:4864:20::431]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1r2eeW-0001U8-BJ for qemu-devel@nongnu.org; Mon, 13 Nov 2023 16:39:29 -0500 Received: by mail-pf1-x431.google.com with SMTP id d2e1a72fcca58-6c32a20d5dbso4330477b3a.1 for ; Mon, 13 Nov 2023 13:39:27 -0800 (PST) Received: from grind.. ([152.250.131.148]) by smtp.gmail.com with ESMTPSA id a6-20020a170902900600b001c736746d33sm4455423plp.217.2023.11.13.13.39.22 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 13 Nov 2023 13:39:24 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1699911565; x=1700516365; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=0cYVqzO8TRpxKmALsybQRSCPXQl71TGGunhIS2IHSCc=; b=X45pBnHA6nFygopiOOeSbPn5vRI0bA7SpRKGCpAqVpY4oDvUWBcuKWXZKag7eIn8gc vnuC2CwYG6o5NVnS8nSH9gPx8BfxGezN9Yl2z+jW5P5siCb0U2MaDGSlnQdlYmqyjrSM 8zjSV0FRdT99ALwdIQ/taZA2OdnTsWRv0kK+rnjcH9jUqn/PpdcKYZsSq9psE/bo0DhZ PEqZrcxCd+DMLcLuHsdx2ZbdUAoaW70B1+HZIVDQY8tT5OtsM5Zn/PUGbfCTW8qHtLsf e6kTwlfXh5bb1XfG5OWSjcL2cbaj272uDzHHRmsQsC12lfyEQG9cwo4AMeYq2e+PfuNn Ucwg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1699911565; x=1700516365; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=0cYVqzO8TRpxKmALsybQRSCPXQl71TGGunhIS2IHSCc=; b=ekaQ2Ss+08F0T/oWTR65S/7PWG717I950LtvfwcltJeiFIsNWv5JaIQ7i9gKpsVioF Y+a1sjLMtCokTez/AnAQhUNIhyQIet9nN0xH3QFpWTQ2FHSbDiQaDY2UVht7CRbRF8L0 XUMb0agwx9uvyOwoMm6N2vNDVBrK9mkbxBs7BuFNMTh+Nkgd7Kf/ce0fC3ACWrzd7mHV JSlyLCvpsfWp/NDq12hO+T6+E7eshjySV996XTk6gzeurEbf3X9Ammo3FbNUnyoqXX1V 6q1IRWF00X6WPuQnYRQ3qPKqTVmacpW15PPKkXMNoJd/1+YNzxl1uIT0kclsd1hLlf/e g5Yg== X-Gm-Message-State: AOJu0YzM4GV3VGl7hCIhR5CcGRX9i3BRVCpHxdd+eNsTFGx0x2DlLPZ6 2Il/FCpqKPQ2/pwiWp03Z5uoitcEKxnWyzaIloc= X-Google-Smtp-Source: AGHT+IFEB5VUjapDjOSfyRlzTO8hykZtlUHg8/fUep3SZnlVzXLOBs3mMz7Fwmp0/x7QwlhrBUsM0Q== X-Received: by 2002:a05:6a20:cea6:b0:185:a59a:d37d with SMTP id if38-20020a056a20cea600b00185a59ad37dmr5288314pzb.30.1699911564899; Mon, 13 Nov 2023 13:39:24 -0800 (PST) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, bmeng@tinylab.org, liwei1518@gmail.com, zhiwei_liu@linux.alibaba.com, palmer@rivosinc.com, Daniel Henrique Barboza , Andrew Jones Subject: [PATCH for-9.0 3/6] target/riscv/tcg: update priv_ver on user_set extensions Date: Mon, 13 Nov 2023 18:39:01 -0300 Message-ID: <20231113213904.185320-4-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20231113213904.185320-1-dbarboza@ventanamicro.com> References: <20231113213904.185320-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::431; envelope-from=dbarboza@ventanamicro.com; helo=mail-pf1-x431.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ventanamicro.com) X-ZM-MESSAGEID: 1699911675052100001 Content-Type: text/plain; charset="utf-8" We'll add a new bare CPU type that won't have any default priv_ver. This means that the CPU will default to priv_ver =3D 0, i.e. 1.10.0. At the same we'll allow these CPUs to enable extensions at will, but then, if the extension has a priv_ver newer than 1.10, we'll end up disabling it. Users will then need to manually set priv_ver to something other than 1.10 to enable the extensions they want, which is not ideal. Change the setter() of extensions to allow user enabled extensions to bump the priv_ver of the CPU. This will make it convenient for users to enable extensions for CPUs that doesn't set a default priv_ver. This change does not affect any existing CPU: vendor CPUs does not allow extensions to be enabled, and generic CPUs are already set to priv_ver LATEST. Signed-off-by: Daniel Henrique Barboza Reviewed-by: Andrew Jones --- target/riscv/tcg/tcg-cpu.c | 32 ++++++++++++++++++++++++++++++++ 1 file changed, 32 insertions(+) diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c index 304211169e..c63b2adb5b 100644 --- a/target/riscv/tcg/tcg-cpu.c +++ b/target/riscv/tcg/tcg-cpu.c @@ -114,6 +114,26 @@ static int cpu_cfg_ext_get_min_version(uint32_t ext_of= fset) g_assert_not_reached(); } =20 +static void cpu_validate_multi_ext_priv_ver(CPURISCVState *env, + uint32_t ext_offset) +{ + int ext_priv_ver; + + if (env->priv_ver =3D=3D PRIV_VERSION_LATEST) { + return; + } + + ext_priv_ver =3D cpu_cfg_ext_get_min_version(ext_offset); + + if (env->priv_ver < ext_priv_ver) { + /* + * Note: the 'priv_spec' command line option, if present, + * will take precedence over this priv_ver bump. + */ + env->priv_ver =3D ext_priv_ver; + } +} + static void cpu_cfg_ext_auto_update(RISCVCPU *cpu, uint32_t ext_offset, bool value) { @@ -748,6 +768,14 @@ static void cpu_set_misa_ext_cfg(Object *obj, Visitor = *v, const char *name, return; } =20 + if (misa_bit =3D=3D RVH && env->priv_ver < PRIV_VERSION_1_12_0) { + /* + * Note: the 'priv_spec' command line option, if present, + * will take precedence over this priv_ver bump. + */ + env->priv_ver =3D PRIV_VERSION_1_12_0; + } + env->misa_ext |=3D misa_bit; env->misa_ext_mask |=3D misa_bit; } else { @@ -877,6 +905,10 @@ static void cpu_set_multi_ext_cfg(Object *obj, Visitor= *v, const char *name, return; } =20 + if (value) { + cpu_validate_multi_ext_priv_ver(&cpu->env, multi_ext_cfg->offset); + } + isa_ext_update_enabled(cpu, multi_ext_cfg->offset, value); } =20 --=20 2.41.0 From nobody Wed Nov 27 07:40:46 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1699911645; cv=none; d=zohomail.com; s=zohoarc; b=L3LvkJXOwPhK+LPRINITqYkFCMCZ7IxSbsRRO+PO1xDGQyQiU1hqMPltpL9mVkHBVqIsZqE6NuUD4IzhVk0ODWviIG9ApkzRmpBYBS4Ik0kwz1tjVU2bEn6R/CzxdffsShjwoPRJe7RLnntVwNAvR2UJ1OrbFYfjKMU5wT+91v0= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1699911645; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=oNzK71ptVkzN8LH9oIEjdELKVkAXXjFWm0PQTwTkQA4=; b=kRKjs2eDACILE7GZny8wzdx7cvbIXoIMskcBiLk/+ga4zMjGp2ZYR+M2tqTL35PRtJygIpz2WlY+Ekhze6hMNWR9KZLQn+Wdgh8AttGrtPLf0eZu+Bz7h9K2Z87V8SU5ss2NOempfiy5yS49CRzgqixujg+X1pKSXVmLs2ZkQ6I= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1699911645262848.5770446710255; Mon, 13 Nov 2023 13:40:45 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1r2eeg-0006AW-Km; Mon, 13 Nov 2023 16:39:38 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1r2eef-00069o-0P for qemu-devel@nongnu.org; Mon, 13 Nov 2023 16:39:37 -0500 Received: from mail-pl1-x630.google.com ([2607:f8b0:4864:20::630]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1r2eeY-0001Um-IW for qemu-devel@nongnu.org; Mon, 13 Nov 2023 16:39:36 -0500 Received: by mail-pl1-x630.google.com with SMTP id d9443c01a7336-1cc5fa0e4d5so44688825ad.0 for ; Mon, 13 Nov 2023 13:39:29 -0800 (PST) Received: from grind.. ([152.250.131.148]) by smtp.gmail.com with ESMTPSA id a6-20020a170902900600b001c736746d33sm4455423plp.217.2023.11.13.13.39.25 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 13 Nov 2023 13:39:27 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1699911568; x=1700516368; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=oNzK71ptVkzN8LH9oIEjdELKVkAXXjFWm0PQTwTkQA4=; b=jUJusm4Tby9b33KcqRymj9w0Gr0JID1P02oKwcub0EitBctFZMgRNIPtWoNgyBPNLO kBzeems6cqS0rEM2VDLCpoHk7L65sKX0mGs2jtLi0IwP+tJp4OeiObG+tjAQ9WkMpDYJ YCpB1n0f+GqDjs1dURf7tuRZDsOcgemDmaxDDGoBjIdyKbjoDZcDfy73J1VU74lioJzn fJg+D7ZWzCVGITwIhoih6UcKuniu0acSkG8cF0voug7KVtJ4iH2jGusYOCByeor0SCCY LIyNsa/irZiMKx2aCzL9ENVcTJ4IjpA+/dMnbckZNsNrrObsNCUBWtd10tC3GMy9wffF Lebg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1699911568; x=1700516368; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=oNzK71ptVkzN8LH9oIEjdELKVkAXXjFWm0PQTwTkQA4=; b=mOVYyRmVNU+bGixP8QaBYhqYOYsY5+5Sl6ma5giwiCD/XVYe9LBrebQMh2g/5Yp7S2 aTCAvu38hVIFvOxoq2lfrNiMEAfwKNl3VRsZnFoUeObyLVMaAfTAMkmvBuO7QH6Zhv2C iPwWE4Nn+3HGjrHwLlX7/50QGzYRZMA/rvjq4cfYvuYXCcGoyymlWpJoK1Yvd4xv+vI6 TsDOPobxudjfTKoZdBTQFe26zY/qMbKQhYp1FZrn/WU/ODz9JLecsgb/VvhwA7KBvCBk IRPMbqILr1qgEZ3WiKBi86qYkZLPaJJTGh2oE8GpD44qSF/mZdaIcdLHxeEMNOqwma2G FNww== X-Gm-Message-State: AOJu0Ywal1tGkSm43bgzAWoIKtBudcv+xqXh4UJIb5oWDutKuCNkBrLM MJxEZszq1k9V+54EzacxyoEbLdvbCUT25Kg/qWk= X-Google-Smtp-Source: AGHT+IHGqk3yZ/s1QxFgnjg4f0PD1dQRv+5LD1cZX+/n9Y7mFeMd8otIMe2DnJoihBPtCNaFhUz8Qw== X-Received: by 2002:a17:903:32c4:b0:1cc:3b86:cfc5 with SMTP id i4-20020a17090332c400b001cc3b86cfc5mr570822plr.4.1699911567813; Mon, 13 Nov 2023 13:39:27 -0800 (PST) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, bmeng@tinylab.org, liwei1518@gmail.com, zhiwei_liu@linux.alibaba.com, palmer@rivosinc.com, Daniel Henrique Barboza , Andrew Jones Subject: [PATCH for-9.0 4/6] target/riscv: add rv64i CPU Date: Mon, 13 Nov 2023 18:39:02 -0300 Message-ID: <20231113213904.185320-5-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20231113213904.185320-1-dbarboza@ventanamicro.com> References: <20231113213904.185320-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::630; envelope-from=dbarboza@ventanamicro.com; helo=mail-pl1-x630.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ventanamicro.com) X-ZM-MESSAGEID: 1699911646750100003 Content-Type: text/plain; charset="utf-8" We don't have any form of a 'bare bones' CPU. rv64, our default CPUs, comes with a lot of defaults. This is fine for most regular uses but it's not suitable when more control of what is actually loaded in the CPU is required. A bare-bones CPU would be annoying to deal with if not by profile support, a way to load a multitude of extensions with a single flag. Profile support is going to be implemented shortly, so let's add a CPU for it. The new 'rv64i' CPU will have only RVI loaded. It is inspired in the profile specification that dictates, for RVA22U64 [1]: "RVA22U64 Mandatory Base RV64I is the mandatory base ISA for RVA22U64" And so it seems that RV64I is the mandatory base ISA for all profiles listed in [1], making it an ideal CPU to use with profile support. rv64i is a CPU of type TYPE_RISCV_BARE_CPU. It has a mix of features from pre-existent CPUs: - it allows extensions to be enabled, like generic CPUs; - it will not inherit extension defaults, like vendor CPUs. This is the minimum extension set to boot OpenSBI and buildroot using rv64i: ./build/qemu-system-riscv64 -nographic -M virt \ -cpu rv64i,sv39=3Dtrue,g=3Dtrue,c=3Dtrue,s=3Dtrue,u=3Dtrue Our minimal riscv,isa in this case will be: # cat /proc/device-tree/cpus/cpu@0/riscv,isa rv64imafdc_zicntr_zicsr_zifencei_zihpm_zca_zcd# [1] https://github.com/riscv/riscv-profiles/blob/main/profiles.adoc Signed-off-by: Daniel Henrique Barboza Reviewed-by: Andrew Jones --- target/riscv/cpu-qom.h | 2 ++ target/riscv/cpu.c | 46 ++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 48 insertions(+) diff --git a/target/riscv/cpu-qom.h b/target/riscv/cpu-qom.h index ca7dd509e3..4d1aa54311 100644 --- a/target/riscv/cpu-qom.h +++ b/target/riscv/cpu-qom.h @@ -24,6 +24,7 @@ #define TYPE_RISCV_CPU "riscv-cpu" #define TYPE_RISCV_DYNAMIC_CPU "riscv-dynamic-cpu" #define TYPE_RISCV_VENDOR_CPU "riscv-vendor-cpu" +#define TYPE_RISCV_BARE_CPU "riscv-bare-cpu" =20 #define RISCV_CPU_TYPE_SUFFIX "-" TYPE_RISCV_CPU #define RISCV_CPU_TYPE_NAME(name) (name RISCV_CPU_TYPE_SUFFIX) @@ -33,6 +34,7 @@ #define TYPE_RISCV_CPU_BASE32 RISCV_CPU_TYPE_NAME("rv32") #define TYPE_RISCV_CPU_BASE64 RISCV_CPU_TYPE_NAME("rv64") #define TYPE_RISCV_CPU_BASE128 RISCV_CPU_TYPE_NAME("x-rv128") +#define TYPE_RISCV_CPU_RV64I RISCV_CPU_TYPE_NAME("rv64i") #define TYPE_RISCV_CPU_IBEX RISCV_CPU_TYPE_NAME("lowrisc-ibex") #define TYPE_RISCV_CPU_SHAKTI_C RISCV_CPU_TYPE_NAME("shakti-c") #define TYPE_RISCV_CPU_SIFIVE_E31 RISCV_CPU_TYPE_NAME("sifive-e31") diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 220113408e..a52bf1e33c 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -370,6 +370,17 @@ static void set_satp_mode_max_supported(RISCVCPU *cpu, /* Set the satp mode to the max supported */ static void set_satp_mode_default_map(RISCVCPU *cpu) { + /* + * Bare CPUs do not default to the max available. + * Users must set a valid satp_mode in the command + * line. + */ + if (object_dynamic_cast(OBJECT(cpu), TYPE_RISCV_BARE_CPU) !=3D NULL) { + warn_report("No satp mode set. Defaulting to 'bare'"); + cpu->cfg.satp_mode.map =3D (1 << VM_1_10_MBARE); + return; + } + cpu->cfg.satp_mode.map =3D cpu->cfg.satp_mode.supported; } #endif @@ -552,6 +563,28 @@ static void rv128_base_cpu_init(Object *obj) set_satp_mode_max_supported(RISCV_CPU(obj), VM_1_10_SV57); #endif } + +static void rv64i_bare_cpu_init(Object *obj) +{ + CPURISCVState *env =3D &RISCV_CPU(obj)->env; + riscv_cpu_set_misa(env, MXL_RV64, RVI); + + /* Remove the defaults from the parent class */ + RISCV_CPU(obj)->cfg.ext_zicntr =3D false; + RISCV_CPU(obj)->cfg.ext_zihpm =3D false; + + /* Set to QEMU's first supported priv version */ + env->priv_ver =3D PRIV_VERSION_1_10_0; + + /* + * Support all available satp_mode settings. The default + * value will be set to MBARE if the user doesn't set + * satp_mode manually (see set_satp_mode_default()). + */ +#ifndef CONFIG_USER_ONLY + set_satp_mode_max_supported(RISCV_CPU(obj), VM_1_10_SV64); +#endif +} #else static void rv32_base_cpu_init(Object *obj) { @@ -1785,6 +1818,13 @@ void riscv_cpu_list(void) .instance_init =3D initfn \ } =20 +#define DEFINE_BARE_CPU(type_name, initfn) \ + { \ + .name =3D type_name, \ + .parent =3D TYPE_RISCV_BARE_CPU, \ + .instance_init =3D initfn \ + } + static const TypeInfo riscv_cpu_type_infos[] =3D { { .name =3D TYPE_RISCV_CPU, @@ -1807,6 +1847,11 @@ static const TypeInfo riscv_cpu_type_infos[] =3D { .parent =3D TYPE_RISCV_CPU, .abstract =3D true, }, + { + .name =3D TYPE_RISCV_BARE_CPU, + .parent =3D TYPE_RISCV_CPU, + .abstract =3D true, + }, DEFINE_DYNAMIC_CPU(TYPE_RISCV_CPU_ANY, riscv_any_cpu_init), DEFINE_DYNAMIC_CPU(TYPE_RISCV_CPU_MAX, riscv_max_cpu_init), #if defined(TARGET_RISCV32) @@ -1823,6 +1868,7 @@ static const TypeInfo riscv_cpu_type_infos[] =3D { DEFINE_VENDOR_CPU(TYPE_RISCV_CPU_THEAD_C906, rv64_thead_c906_cpu_init= ), DEFINE_VENDOR_CPU(TYPE_RISCV_CPU_VEYRON_V1, rv64_veyron_v1_cpu_init), DEFINE_DYNAMIC_CPU(TYPE_RISCV_CPU_BASE128, rv128_base_cpu_init), + DEFINE_BARE_CPU(TYPE_RISCV_CPU_RV64I, rv64i_bare_cpu_init), #endif }; =20 --=20 2.41.0 From nobody Wed Nov 27 07:40:46 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1699911638; cv=none; d=zohomail.com; s=zohoarc; b=iqPuXj5Z6IviQC2IxcJFo3Rb7jzm71xcWRiCb/IzA2D9zRgajEbqJCOEOWlq6JXuGSHo11ATBgAr3VRUDA6O+U+P0JZXg1G4AlS3GebEyWDbN2ZMKGAU31+lZ2Z/YUN1K7RwDnSOx9BjpTKkav7N958Fq+bn90iLZ/GX0eHKSMQ= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1699911638; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=BUh/6KkW4XcW8kKVIfjTyve/D2pqne6pt1Gsp4Re3wQ=; b=j1OWAkF1lNRfOi6ehLQeD5y2ko4izU6YcVdX5gwCpj+OftETsPr9gJdtTKHaz1B60GN40s3n+wgVNKmkh+8qzPAYcJs2/DDkDF0diASwFeRGwj8of6yf/7Tii1AqUKfRCaGTYrkRkFzX0hQDIttDoFEv/4h1XPYTGxV49XVoJWk= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1699911638548231.1411133297985; Mon, 13 Nov 2023 13:40:38 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1r2eed-000696-76; Mon, 13 Nov 2023 16:39:35 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1r2eec-00068x-Fp for qemu-devel@nongnu.org; Mon, 13 Nov 2023 16:39:34 -0500 Received: from mail-pl1-x62f.google.com ([2607:f8b0:4864:20::62f]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1r2eea-0001VG-Rr for qemu-devel@nongnu.org; Mon, 13 Nov 2023 16:39:34 -0500 Received: by mail-pl1-x62f.google.com with SMTP id d9443c01a7336-1cc4f777ab9so36812355ad.0 for ; Mon, 13 Nov 2023 13:39:32 -0800 (PST) Received: from grind.. ([152.250.131.148]) by smtp.gmail.com with ESMTPSA id a6-20020a170902900600b001c736746d33sm4455423plp.217.2023.11.13.13.39.28 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 13 Nov 2023 13:39:30 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1699911570; x=1700516370; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=BUh/6KkW4XcW8kKVIfjTyve/D2pqne6pt1Gsp4Re3wQ=; b=R9hX4BooM9sAf+CjIGIDaxXEL+Qv49y5g0w9vz7mMso1C2A7chk0pVpCBVr30vdr6h jJQw436YaH5EFUPt4ENsgjmTd3/lFX6BbjSUvbetl9ywxucgMz0ehQrTQJickBqhloTd ycXZgXb3iijUGyLixSTU6Te+P0raCzperU3On+gFh2sHdLsm8H613JR85nW5syuwDblp uMgMS99/k64XX11K+1TLZfYyjO8Ou2zukwBsGV9qtN1n0E95JC9TeId8jw1I73QoHsLV vOS2XIYRlDNDp90D6QMQzlaSMQ3WTlaxPQ7VoivXJDCvBG3CX9rtaGLEqNY4Tru0ZBtF poqg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1699911570; x=1700516370; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=BUh/6KkW4XcW8kKVIfjTyve/D2pqne6pt1Gsp4Re3wQ=; b=FJzE808sJRo/D7h4mFSZgn7QWVYL3rQYtgyf20Z7eUBZzzIHtmsBhcS38As35lBr2W jXbXCKs4vLk9az+KYV7TTxVhSiZgfbEhttYoVXfimmf6lQDbigV4D26R43XqKtfp0b1h bcFRxW5//nNqX04YaUvC5E6/Ov358cZAC68XnYbrzZvE0ecOuxwUWnCuZfDzPaPZy1V/ lX7rvoyv159nEWSn/KHgcIs2cc7I4N67FCuZZI9oGsiHMRSRrV+Ru9ZEfj4G3GovVKgD Ib5HZRgcQpvvQfOfm5GeP5++wUD67eA40XTwYMh29NFxPCHlCavHNetIYaJXT2ferTm+ fufg== X-Gm-Message-State: AOJu0YwJ5PcnJtlaPfxfjXZWaqJFPfSBbhHiQzTU0eYGjalRESLbh+7T QuKHBG7wlpbJ5jQNZhjmHeVt6cw9bu1a8mjh7Cg= X-Google-Smtp-Source: AGHT+IHUSu7MpgylO/d+b9HuQStXxv4++OOMX1Jpi6gmMuwW+RIUQlSx12lu6CWx67c2oJfy5/PpFQ== X-Received: by 2002:a17:902:ab4f:b0:1ca:7909:6ee6 with SMTP id ij15-20020a170902ab4f00b001ca79096ee6mr440336plb.61.1699911570545; Mon, 13 Nov 2023 13:39:30 -0800 (PST) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, bmeng@tinylab.org, liwei1518@gmail.com, zhiwei_liu@linux.alibaba.com, palmer@rivosinc.com, Daniel Henrique Barboza Subject: [PATCH for-9.0 5/6] target/riscv: add rv32i CPU Date: Mon, 13 Nov 2023 18:39:03 -0300 Message-ID: <20231113213904.185320-6-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20231113213904.185320-1-dbarboza@ventanamicro.com> References: <20231113213904.185320-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::62f; envelope-from=dbarboza@ventanamicro.com; helo=mail-pl1-x62f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ventanamicro.com) X-ZM-MESSAGEID: 1699911640681100003 Content-Type: text/plain; charset="utf-8" Add a bare bones 32 bit CPU, like we already did with rv64i, to ease the pain of users trying to build a CPU from scratch and having to disable the defaults we have with the regular rv32 CPU. See: https://lore.kernel.org/qemu-riscv/258be47f-97be-4308-bed5-dc34ef7ff954@Spa= rk/ For a use case where the existence of rv32i would make things simpler. Signed-off-by: Daniel Henrique Barboza --- target/riscv/cpu-qom.h | 1 + target/riscv/cpu.c | 23 +++++++++++++++++++++++ 2 files changed, 24 insertions(+) diff --git a/target/riscv/cpu-qom.h b/target/riscv/cpu-qom.h index 4d1aa54311..f345c17e69 100644 --- a/target/riscv/cpu-qom.h +++ b/target/riscv/cpu-qom.h @@ -34,6 +34,7 @@ #define TYPE_RISCV_CPU_BASE32 RISCV_CPU_TYPE_NAME("rv32") #define TYPE_RISCV_CPU_BASE64 RISCV_CPU_TYPE_NAME("rv64") #define TYPE_RISCV_CPU_BASE128 RISCV_CPU_TYPE_NAME("x-rv128") +#define TYPE_RISCV_CPU_RV32I RISCV_CPU_TYPE_NAME("rv32i") #define TYPE_RISCV_CPU_RV64I RISCV_CPU_TYPE_NAME("rv64i") #define TYPE_RISCV_CPU_IBEX RISCV_CPU_TYPE_NAME("lowrisc-ibex") #define TYPE_RISCV_CPU_SHAKTI_C RISCV_CPU_TYPE_NAME("shakti-c") diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index a52bf1e33c..55cf114b61 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -666,6 +666,28 @@ static void rv32_imafcu_nommu_cpu_init(Object *obj) cpu->cfg.ext_zicsr =3D true; cpu->cfg.pmp =3D true; } + +static void rv32i_bare_cpu_init(Object *obj) +{ + CPURISCVState *env =3D &RISCV_CPU(obj)->env; + riscv_cpu_set_misa(env, MXL_RV32, RVI); + + /* Remove the defaults from the parent class */ + RISCV_CPU(obj)->cfg.ext_zicntr =3D false; + RISCV_CPU(obj)->cfg.ext_zihpm =3D false; + + /* Set to QEMU's first supported priv version */ + env->priv_ver =3D PRIV_VERSION_1_10_0; + + /* + * Support all available satp_mode settings. The default + * value will be set to MBARE if the user doesn't set + * satp_mode manually (see set_satp_mode_default()). + */ +#ifndef CONFIG_USER_ONLY + set_satp_mode_max_supported(RISCV_CPU(obj), VM_1_10_SV32); +#endif +} #endif =20 static ObjectClass *riscv_cpu_class_by_name(const char *cpu_model) @@ -1860,6 +1882,7 @@ static const TypeInfo riscv_cpu_type_infos[] =3D { DEFINE_VENDOR_CPU(TYPE_RISCV_CPU_SIFIVE_E31, rv32_sifive_e_cpu_init), DEFINE_VENDOR_CPU(TYPE_RISCV_CPU_SIFIVE_E34, rv32_imafcu_nommu_cpu_in= it), DEFINE_VENDOR_CPU(TYPE_RISCV_CPU_SIFIVE_U34, rv32_sifive_u_cpu_init), + DEFINE_BARE_CPU(TYPE_RISCV_CPU_RV32I, rv32i_bare_cpu_init), #elif defined(TARGET_RISCV64) DEFINE_DYNAMIC_CPU(TYPE_RISCV_CPU_BASE64, rv64_base_cpu_init), DEFINE_VENDOR_CPU(TYPE_RISCV_CPU_SIFIVE_E51, rv64_sifive_e_cpu_init), --=20 2.41.0 From nobody Wed Nov 27 07:40:46 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1699911614; cv=none; d=zohomail.com; s=zohoarc; b=FJjpbgAEHNvHoQLJOPk9sZo+Kab3Ixs4vl0nFjN4u3T7TgEGbDzYyR1J1/sY6+7LB8xTGeM2AR+YOEI5Z6zFbzW2c/LUg9NzQqkIcKmtX0Q5nWTgGHplCaSVutiQCMufblGzVeUH0A+bUlfmR61caUp32on2lpUXY74x8sBoXLM= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1699911614; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=qCqMpypxYhR2XXGBnvs8P3AJK9PzGYu4JOrjRZN4juc=; b=EUx55REH/Uz1YBoM4J3iCfd8fux8cgVvh1UXAKaTSA9hGqGIn0TSexwMEANRG7YQL3AdCytjGQw7d5cjNLzarXl3bZkkvXeUj91ashQVxB9TWXbCWI2NXT1Yo8vBbybxDQvLMBDR1D8eXeWS15KcasqLGt2n1aAou52oTjghETc= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1699911614809724.3568415797978; Mon, 13 Nov 2023 13:40:14 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1r2eef-0006AO-Qq; Mon, 13 Nov 2023 16:39:37 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1r2eef-00069p-2o for qemu-devel@nongnu.org; Mon, 13 Nov 2023 16:39:37 -0500 Received: from mail-pl1-x636.google.com ([2607:f8b0:4864:20::636]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1r2eed-0001Vd-61 for qemu-devel@nongnu.org; Mon, 13 Nov 2023 16:39:36 -0500 Received: by mail-pl1-x636.google.com with SMTP id d9443c01a7336-1cc0d0a0355so36686965ad.3 for ; Mon, 13 Nov 2023 13:39:34 -0800 (PST) Received: from grind.. ([152.250.131.148]) by smtp.gmail.com with ESMTPSA id a6-20020a170902900600b001c736746d33sm4455423plp.217.2023.11.13.13.39.30 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 13 Nov 2023 13:39:32 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1699911573; x=1700516373; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=qCqMpypxYhR2XXGBnvs8P3AJK9PzGYu4JOrjRZN4juc=; b=fBfKMuNq8Ygs1B/WyhGOlKdtIkXW78A55rSUmtdZStyOTjDId7Obp8rWGw793gX7On 1lNJRh3V+Wgr5YnU+b+O6KZYKFphWWrSSKGEm5geX7k/NLrSexAQMQria0DnUScsIrSo K7jNwepddeo5CcgZTbVTSRkPZJxiT5FC97lEQk96FY9gFD4t75Dja3z2bJhYIwAD9ATu lT33/7J3JusAZKcJlWv77odlw7nRgb2L2mn3ZacDzo3EUEu4bFJCvo8kEHMmnDLBfxaz WQqDahrLlbjHO8Iq+sMHL3TKab0y/juoaXC4/aEbN/6FO+SDE5ga0Lk3Epqm5mM0uMkZ 1leQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1699911573; x=1700516373; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=qCqMpypxYhR2XXGBnvs8P3AJK9PzGYu4JOrjRZN4juc=; b=uTyxkqILwK+cVnf0bVmFYTHJJc2aR6TYw1D93l6i/1mu1gV5lvb7jm0eo4ZbjHs5+8 I5ldxk5bwbegzfcnmdWYTT/E9cpxZ302I5WdWP07+kGkRABQzhPYbWOv++YR5frEGSFp ISsldylaZ6fZl6xYUTs82iK8NK7tpX6qQqPNVskQUezVOnqoQenwQqpuvmh3Ssz5EiHc TWpcXja3M2bRcM6Vfx0xx0vAQLrDzSqx86KtZlglIrqIB3EEwpnN6fnb3NFwcwmT+oRJ qFjdErmaLKemHydabTUZj77u9EkM1BcS367XmCRe/NSJr6vOCd9z7rgI8qRm6+3k7adi BEfw== X-Gm-Message-State: AOJu0YygLP71Kx45hmzdxDBHjWAMqVw8cHBt1c01D2+QkMifSsbmQTp0 gNkOfaTah7ub4dePAeo4u0eQSUjX7y8ulQL6lig= X-Google-Smtp-Source: AGHT+IF0+LzM7AX6PcgIaK3amHGT48pREfAOCC4/uo37bCL4/jYadOX0xdYrkS5n5ZQBDBDMV5+iVg== X-Received: by 2002:a17:902:db07:b0:1cc:5dd4:7ce5 with SMTP id m7-20020a170902db0700b001cc5dd47ce5mr648135plx.19.1699911573238; Mon, 13 Nov 2023 13:39:33 -0800 (PST) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, bmeng@tinylab.org, liwei1518@gmail.com, zhiwei_liu@linux.alibaba.com, palmer@rivosinc.com, Daniel Henrique Barboza Subject: [PATCH for-9.0 6/6] target/riscv: add rv32e/rv64e CPUs Date: Mon, 13 Nov 2023 18:39:04 -0300 Message-ID: <20231113213904.185320-7-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20231113213904.185320-1-dbarboza@ventanamicro.com> References: <20231113213904.185320-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::636; envelope-from=dbarboza@ventanamicro.com; helo=mail-pl1-x636.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ventanamicro.com) X-ZM-MESSAGEID: 1699911616773100005 Content-Type: text/plain; charset="utf-8" In our internals we'll never allow RVI and RVE to be enabled at the same time, and we require either RVI or RVE to be enabled to proceed with machine boot. And all CPUs we have enables RVI by default. This means that if one wants to create an embedded CPU he'll need to disable RVI first then enable RVE, e.g.: -cpu rv64i,i=3Dfalse,e=3Dtrue Let's add two RVE CPUs to ease the burder when working with embedded CPUs in QEMU. Signed-off-by: Daniel Henrique Barboza --- target/riscv/cpu-qom.h | 2 ++ target/riscv/cpu.c | 46 ++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 48 insertions(+) diff --git a/target/riscv/cpu-qom.h b/target/riscv/cpu-qom.h index f345c17e69..34d1034cfc 100644 --- a/target/riscv/cpu-qom.h +++ b/target/riscv/cpu-qom.h @@ -36,6 +36,8 @@ #define TYPE_RISCV_CPU_BASE128 RISCV_CPU_TYPE_NAME("x-rv128") #define TYPE_RISCV_CPU_RV32I RISCV_CPU_TYPE_NAME("rv32i") #define TYPE_RISCV_CPU_RV64I RISCV_CPU_TYPE_NAME("rv64i") +#define TYPE_RISCV_CPU_RV32E RISCV_CPU_TYPE_NAME("rv32e") +#define TYPE_RISCV_CPU_RV64E RISCV_CPU_TYPE_NAME("rv64e") #define TYPE_RISCV_CPU_IBEX RISCV_CPU_TYPE_NAME("lowrisc-ibex") #define TYPE_RISCV_CPU_SHAKTI_C RISCV_CPU_TYPE_NAME("shakti-c") #define TYPE_RISCV_CPU_SIFIVE_E31 RISCV_CPU_TYPE_NAME("sifive-e31") diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 55cf114b61..7d5ff7a0aa 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -585,6 +585,28 @@ static void rv64i_bare_cpu_init(Object *obj) set_satp_mode_max_supported(RISCV_CPU(obj), VM_1_10_SV64); #endif } + +static void rv64e_bare_cpu_init(Object *obj) +{ + CPURISCVState *env =3D &RISCV_CPU(obj)->env; + riscv_cpu_set_misa(env, MXL_RV64, RVE); + + /* Remove the defaults from the parent class */ + RISCV_CPU(obj)->cfg.ext_zicntr =3D false; + RISCV_CPU(obj)->cfg.ext_zihpm =3D false; + + /* Set to QEMU's first supported priv version */ + env->priv_ver =3D PRIV_VERSION_1_10_0; + + /* + * Support all available satp_mode settings. The default + * value will be set to MBARE if the user doesn't set + * satp_mode manually (see set_satp_mode_default()). + */ +#ifndef CONFIG_USER_ONLY + set_satp_mode_max_supported(RISCV_CPU(obj), VM_1_10_SV64); +#endif +} #else static void rv32_base_cpu_init(Object *obj) { @@ -688,6 +710,28 @@ static void rv32i_bare_cpu_init(Object *obj) set_satp_mode_max_supported(RISCV_CPU(obj), VM_1_10_SV32); #endif } + +static void rv32e_bare_cpu_init(Object *obj) +{ + CPURISCVState *env =3D &RISCV_CPU(obj)->env; + riscv_cpu_set_misa(env, MXL_RV32, RVE); + + /* Remove the defaults from the parent class */ + RISCV_CPU(obj)->cfg.ext_zicntr =3D false; + RISCV_CPU(obj)->cfg.ext_zihpm =3D false; + + /* Set to QEMU's first supported priv version */ + env->priv_ver =3D PRIV_VERSION_1_10_0; + + /* + * Support all available satp_mode settings. The default + * value will be set to MBARE if the user doesn't set + * satp_mode manually (see set_satp_mode_default()). + */ +#ifndef CONFIG_USER_ONLY + set_satp_mode_max_supported(RISCV_CPU(obj), VM_1_10_SV32); +#endif +} #endif =20 static ObjectClass *riscv_cpu_class_by_name(const char *cpu_model) @@ -1883,6 +1927,7 @@ static const TypeInfo riscv_cpu_type_infos[] =3D { DEFINE_VENDOR_CPU(TYPE_RISCV_CPU_SIFIVE_E34, rv32_imafcu_nommu_cpu_in= it), DEFINE_VENDOR_CPU(TYPE_RISCV_CPU_SIFIVE_U34, rv32_sifive_u_cpu_init), DEFINE_BARE_CPU(TYPE_RISCV_CPU_RV32I, rv32i_bare_cpu_init), + DEFINE_BARE_CPU(TYPE_RISCV_CPU_RV32E, rv32e_bare_cpu_init), #elif defined(TARGET_RISCV64) DEFINE_DYNAMIC_CPU(TYPE_RISCV_CPU_BASE64, rv64_base_cpu_init), DEFINE_VENDOR_CPU(TYPE_RISCV_CPU_SIFIVE_E51, rv64_sifive_e_cpu_init), @@ -1892,6 +1937,7 @@ static const TypeInfo riscv_cpu_type_infos[] =3D { DEFINE_VENDOR_CPU(TYPE_RISCV_CPU_VEYRON_V1, rv64_veyron_v1_cpu_init), DEFINE_DYNAMIC_CPU(TYPE_RISCV_CPU_BASE128, rv128_base_cpu_init), DEFINE_BARE_CPU(TYPE_RISCV_CPU_RV64I, rv64i_bare_cpu_init), + DEFINE_BARE_CPU(TYPE_RISCV_CPU_RV64E, rv64e_bare_cpu_init), #endif }; =20 --=20 2.41.0