Manipulate the shift count so that the bit to be tested
is always placed at the MSB.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/hppa/insns.decode | 4 ++--
target/hppa/translate.c | 6 ++----
2 files changed, 4 insertions(+), 6 deletions(-)
diff --git a/target/hppa/insns.decode b/target/hppa/insns.decode
index ad454adcbb..b185523021 100644
--- a/target/hppa/insns.decode
+++ b/target/hppa/insns.decode
@@ -290,8 +290,8 @@ fmpysub_d 100110 ..... ..... ..... ..... 1 ..... @mpyadd
# Conditional Branches
####
-bb_sar 110000 00000 r:5 c:1 10 ........... n:1 . disp=%assemble_12
-bb_imm 110001 p:5 r:5 c:1 10 ........... n:1 . disp=%assemble_12
+bb_sar 110000 00000 r:5 c:1 1 d:1 ........... n:1 . disp=%assemble_12
+bb_imm 110001 p:5 r:5 c:1 1 d:1 ........... n:1 . disp=%assemble_12
movb 110010 ..... ..... ... ........... . . @rrb_cf f=0
movbi 110011 ..... ..... ... ........... . . @rib_cf f=0
diff --git a/target/hppa/translate.c b/target/hppa/translate.c
index df5a6dc896..543a694724 100644
--- a/target/hppa/translate.c
+++ b/target/hppa/translate.c
@@ -3151,13 +3151,12 @@ static bool trans_bb_sar(DisasContext *ctx, arg_bb_sar *a)
{
TCGv_reg tmp, tcg_r;
DisasCond cond;
- bool d = false;
nullify_over(ctx);
tmp = tcg_temp_new();
tcg_r = load_gpr(ctx, a->r);
- if (cond_need_ext(ctx, d)) {
+ if (cond_need_ext(ctx, a->d)) {
/* Force shift into [32,63] */
tcg_gen_ori_reg(tmp, cpu_sar, 32);
tcg_gen_shl_reg(tmp, tcg_r, tmp);
@@ -3173,14 +3172,13 @@ static bool trans_bb_imm(DisasContext *ctx, arg_bb_imm *a)
{
TCGv_reg tmp, tcg_r;
DisasCond cond;
- bool d = false;
int p;
nullify_over(ctx);
tmp = tcg_temp_new();
tcg_r = load_gpr(ctx, a->r);
- p = a->p | (cond_need_ext(ctx, d) ? 32 : 0);
+ p = a->p | (cond_need_ext(ctx, a->d) ? 32 : 0);
tcg_gen_shli_reg(tmp, tcg_r, p);
cond = cond_make_0(a->c ? TCG_COND_GE : TCG_COND_LT, tmp);
--
2.34.1