[PATCH v2 0/4] hw/cxl: Line length reduction and related

Jonathan Cameron via posted 4 patches 9 months, 1 week ago
Failed in applying to current master (apply log)
There is a newer version of this series
include/hw/cxl/cxl_component.h |   3 +-
include/hw/cxl/cxl_device.h    |   5 +-
include/hw/cxl/cxl_events.h    |   3 +-
include/hw/cxl/cxl_pci.h       |   6 +-
hw/cxl/cxl-cdat.c              |   3 +-
hw/cxl/cxl-component-utils.c   | 124 ++++++++++++++++++++-------------
hw/cxl/cxl-device-utils.c      |  11 +--
hw/cxl/cxl-events.c            |   9 ++-
hw/cxl/cxl-mailbox-utils.c     |  21 ++++--
hw/mem/cxl_type3.c             |  31 +++++----
hw/mem/cxl_type3_stubs.c       |   5 +-
hw/pci-bridge/cxl_downstream.c |   2 +-
hw/pci-bridge/cxl_root_port.c  |   2 +-
hw/pci-bridge/cxl_upstream.c   |   2 +-
14 files changed, 141 insertions(+), 86 deletions(-)
[PATCH v2 0/4] hw/cxl: Line length reduction and related
Posted by Jonathan Cameron via 9 months, 1 week ago
v2:
 Replace patch 2 with a change to use switch statements and some asserts
 to improve code readability at same time as dealing with the overly
 long lines.

Suggested-by: Michael S. Tsirkin <mst@redhat.com>

Michael observed that the CXL code regularly went above the 80 character
recommendation and in many cases this was not necessary for readability.

This series is focused on tidying this up for the existing code so that
we can maintain the preferred formatting going forwards.

Based on: [PATCH 0/4] hw/cxl: Minor CXL emulation fixes and cleanup
Based on: [PATCH v2 0/3] hw/cxl: Add dummy ACPI QTG DSM
Based-on: [PATCH V2] hw/pci-bridge/cxl-upstream: Add serial number extended capability support


Based on: Message ID: 20230904132806.6094-1-Jonathan.Cameron@huawei.com
Based on: Message ID: 20230904161847.18468-1-Jonathan.Cameron@huawei.com
Based on: Message ID: 20230913133615.29876-1-Jonathan.Cameron@huawei.com

Jonathan Cameron (4):
  hw/cxl: Use a switch to explicitly check size in caps_reg_read()
  hw/cxl: Use switch statements for read and write of cachemem registers
  hw/cxl: CXLDVSECPortExtensions renamed to CXLDVSECPortExt
  hw/cxl: Line length reductions

 include/hw/cxl/cxl_component.h |   3 +-
 include/hw/cxl/cxl_device.h    |   5 +-
 include/hw/cxl/cxl_events.h    |   3 +-
 include/hw/cxl/cxl_pci.h       |   6 +-
 hw/cxl/cxl-cdat.c              |   3 +-
 hw/cxl/cxl-component-utils.c   | 124 ++++++++++++++++++++-------------
 hw/cxl/cxl-device-utils.c      |  11 +--
 hw/cxl/cxl-events.c            |   9 ++-
 hw/cxl/cxl-mailbox-utils.c     |  21 ++++--
 hw/mem/cxl_type3.c             |  31 +++++----
 hw/mem/cxl_type3_stubs.c       |   5 +-
 hw/pci-bridge/cxl_downstream.c |   2 +-
 hw/pci-bridge/cxl_root_port.c  |   2 +-
 hw/pci-bridge/cxl_upstream.c   |   2 +-
 14 files changed, 141 insertions(+), 86 deletions(-)

-- 
2.39.2