[v3] target/riscv: Add Zihintntl extension ISA string to DTS

[RESEND PATCH v3 0/1] target/riscv: Add Zihintntl extension ISA string to DTS

Jason Chien posted 1 patch 9 months ago

Diff against v1 v1 v2 v3
Download series mbox

Failed in applying to current master (apply log)

target/riscv/cpu.c     | 2 ++
target/riscv/cpu_cfg.h | 1 +
2 files changed, 3 insertions(+)

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[RESEND PATCH v3 0/1] target/riscv: Add Zihintntl extension ISA string to DTS

Posted by Jason Chien 9 months ago

In v2, I rebased the patch on
https://github.com/alistair23/qemu/tree/riscv-to-apply.next
However, I forgot to add "Reviewed-by" in v2, so I add them in v3.

Jason Chien (1):
  target/riscv: Add Zihintntl extension ISA string to DTS

 target/riscv/cpu.c     | 2 ++
 target/riscv/cpu_cfg.h | 1 +
 2 files changed, 3 insertions(+)

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2.17.1