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[59.124.168.89]) by smtp.gmail.com with ESMTPSA id g18-20020aa78752000000b00686c40ccaf2sm756523pfo.9.2023.07.26.00.41.06 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 26 Jul 2023 00:41:07 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; t=1690357269; x=1690962069; h=references:in-reply-to:message-id:date:subject:cc:to:from:from:to :cc:subject:date:message-id:reply-to; bh=4MqX/feLzp+2HvebB53AzArXNcPF6tcsM37ccg0JoqU=; b=Og+cY9lJRRvAgZTYeYqEupOmos/kqYL6tBz2loQqA4cAcPoHP2+PXZ+NWpL4Fhbt5L 84iuoLn+fDrF3jDd9bwJSlnBcg5Gatr8E6twxuzycW7Tmi2hDI32GM+F2twIHb8KANCf 1QN75kBR1BmpBVlxen1cA5bxOIHhG36omYI+KckkL9DRVAJAKjt2UketF0Yg4nywbIoA ku4wQ69JIux5qqu9HBUedZPf+oT1jnQXvuSvNUbVcrMQtnDsSpOJQcInaLKyvtPzFDM3 KTlq9qYsdyymu4zBNeZjq5riPh/4rC0jEFzuzxCYjiXuwM5GsBh7fYM5H1g/9Pr2X+Eg BUSQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1690357269; x=1690962069; h=references:in-reply-to:message-id:date:subject:cc:to:from :x-gm-message-state:from:to:cc:subject:date:message-id:reply-to; bh=4MqX/feLzp+2HvebB53AzArXNcPF6tcsM37ccg0JoqU=; b=OgUGAnKB4D6dNl/FRT//BzFuuBuqOtqzyMYcUgW2wl67613xkIX6Xpl1uN8iIuX/HP WRIY5SQoYZ/jd+QlPxVObKA8pSFaBDl0aEXy6/OTCMPfi1+o1As4nRgzO4VL9d7vZvsl VFKRIhBQsg+Mu/xTOrpa98++LZFH8F3Hd6PqXbiYDnEIJAjANhwm7+BF4Y4CKxBSYWDY Hn9odCz/ix3RKy2onBTrZAwwkMyAOfOustVgAfWNWTJ1Tw3sMFtvG53LbmZ5DDWowhPX jK1Aye5nmIn3OaXzBGuGRncDpW/iEWjXfkfy6lKyL80Y/6ZGm0kJOLlVkCa1cl2r9AkH 84TQ== X-Gm-Message-State: ABy/qLZUZRN3BWR2qeFA59cvHWGC1xPXgYzWi9e4t4mpS7SvHaYgkPLX FYONBMSpcxG7GRoKdfEr1k7WfejYFNrnp3SeIPlPQIz0HeD8DvlqteUjdOR+KTcS6KgJWcUmeok +0fuUHPtMBXX6e05QHKZopzJwJV8dBVasco/TiqZGSmeuJIt8zp+ji9RAkOHD+AVDfbTKY9MExZ F0Ng== X-Google-Smtp-Source: APBJJlFr3iO4n7IAvAGj3jEis+BUQU1k7U1SlNXM0i7T0Cqs6ny5QXt48PWEePGl+ngVH02vqTkygg== X-Received: by 2002:a05:6a00:198d:b0:657:f26e:b01a with SMTP id d13-20020a056a00198d00b00657f26eb01amr1256137pfl.26.1690357268336; Wed, 26 Jul 2023 00:41:08 -0700 (PDT) From: Jason Chien To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Cc: Jason Chien , Palmer Dabbelt , Alistair Francis , Bin Meng , Weiwei Li , Daniel Henrique Barboza , Liu Zhiwei Subject: [RESEND PATCH v3 1/1] target/riscv: Add Zihintntl extension ISA string to DTS Date: Wed, 26 Jul 2023 07:40:46 +0000 Message-Id: <20230726074049.19505-2-jason.chien@sifive.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20230726074049.19505-1-jason.chien@sifive.com> References: <20230726074049.19505-1-jason.chien@sifive.com> Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::434; envelope-from=jason.chien@sifive.com; helo=mail-pf1-x434.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @sifive.com) X-ZM-MESSAGEID: 1690357336283100001 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" RVA23 Profiles states: The RVA23 profiles are intended to be used for 64-bit application processors that will run rich OS stacks from standard binary OS distributions and with a substantial number of third-party binary user applications that will be supported over a considerable length of time in the field. The chapter 4 of the unprivileged spec introduces the Zihintntl extension and Zihintntl is a mandatory extension presented in RVA23 Profiles, whose purpose is to enable application and operating system portability across different implementations. Thus the DTS should contain the Zihintntl ISA string in order to pass to software. The unprivileged spec states: Like any HINTs, these instructions may be freely ignored. Hence, although they are described in terms of cache-based memory hierarchies, they do not mandate the provision of caches. These instructions are encoded with non-used opcode, e.g. ADD x0, x0, x2, which QEMU already supports, and QEMU does not emulate cache. Therefore these instructions can be considered as a no-op, and we only need to add a new property for the Zihintntl extension. Reviewed-by: Frank Chang Reviewed-by: Alistair Francis Signed-off-by: Jason Chien --- target/riscv/cpu.c | 2 ++ target/riscv/cpu_cfg.h | 1 + 2 files changed, 3 insertions(+) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 921c19e6cd..a49e934b41 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -87,6 +87,7 @@ static const struct isa_ext_data isa_edata_arr[] =3D { ISA_EXT_DATA_ENTRY(zicond, PRIV_VERSION_1_12_0, ext_zicond), ISA_EXT_DATA_ENTRY(zicsr, PRIV_VERSION_1_10_0, ext_icsr), ISA_EXT_DATA_ENTRY(zifencei, PRIV_VERSION_1_10_0, ext_ifencei), + ISA_EXT_DATA_ENTRY(zihintntl, PRIV_VERSION_1_10_0, ext_zihintntl), ISA_EXT_DATA_ENTRY(zihintpause, PRIV_VERSION_1_10_0, ext_zihintpause), ISA_EXT_DATA_ENTRY(zmmul, PRIV_VERSION_1_12_0, ext_zmmul), ISA_EXT_DATA_ENTRY(zawrs, PRIV_VERSION_1_12_0, ext_zawrs), @@ -1763,6 +1764,7 @@ static Property riscv_cpu_extensions[] =3D { DEFINE_PROP_BOOL("sscofpmf", RISCVCPU, cfg.ext_sscofpmf, false), DEFINE_PROP_BOOL("Zifencei", RISCVCPU, cfg.ext_ifencei, true), DEFINE_PROP_BOOL("Zicsr", RISCVCPU, cfg.ext_icsr, true), + DEFINE_PROP_BOOL("Zihintntl", RISCVCPU, cfg.ext_zihintntl, true), DEFINE_PROP_BOOL("Zihintpause", RISCVCPU, cfg.ext_zihintpause, true), DEFINE_PROP_BOOL("Zawrs", RISCVCPU, cfg.ext_zawrs, true), DEFINE_PROP_BOOL("Zfa", RISCVCPU, cfg.ext_zfa, true), diff --git a/target/riscv/cpu_cfg.h b/target/riscv/cpu_cfg.h index 2bd9510ba3..518686eaa3 100644 --- a/target/riscv/cpu_cfg.h +++ b/target/riscv/cpu_cfg.h @@ -66,6 +66,7 @@ struct RISCVCPUConfig { bool ext_icbom; bool ext_icboz; bool ext_zicond; + bool ext_zihintntl; bool ext_zihintpause; bool ext_smstateen; bool ext_sstc; --=20 2.17.1