[v3] target/riscv: Add Zihintntl extension ISA string to DTS

[PATCH v3 0/1] target/riscv: Add Zihintntl extension ISA string to DTS

Jason Chien posted 1 patch 2 years, 5 months ago

Diff against v1 v1 v2 v3
Download series mbox

Patches applied successfully (tree, apply log)
git fetch https://github.com/patchew-project/qemu tags/patchew/20230711070402.5846-1-jason.chien@sifive.com

Maintainers: Palmer Dabbelt <palmer@dabbelt.com>, Alistair Francis <alistair.francis@wdc.com>, Bin Meng <bin.meng@windriver.com>, Weiwei Li <liweiwei@iscas.ac.cn>, Daniel Henrique Barboza <dbarboza@ventanamicro.com>, Liu Zhiwei <zhiwei_liu@linux.alibaba.com>

There is a newer version of this series

target/riscv/cpu.c     | 2 ++
target/riscv/cpu_cfg.h | 1 +
2 files changed, 3 insertions(+)

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[PATCH v3 0/1] target/riscv: Add Zihintntl extension ISA string to DTS

Posted by Jason Chien 2 years, 5 months ago

In v2, I rebased the patch on
https://github.com/alistair23/qemu/tree/riscv-to-apply.next
However, I forgot to add "Reviewed-by" in v2, so I add them in v3.

Jason Chien (1):
  target/riscv: Add Zihintntl extension ISA string to DTS

 target/riscv/cpu.c     | 2 ++
 target/riscv/cpu_cfg.h | 1 +
 2 files changed, 3 insertions(+)

-- 
2.17.1