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[PATCH] target/mips: enable GINVx support for I6400 and I6500

Marcin Nowakowski posted 1 patch 2 years, 7 months ago
Patches applied successfully (tree, apply log)
git fetch https://github.com/patchew-project/qemu tags/patchew/20230630072806.3093704-1-marcin.nowakowski@fungible.com
Maintainers: "Philippe Mathieu-Daudé" <philmd@linaro.org>, Aurelien Jarno <aurelien@aurel32.net>, Jiaxun Yang <jiaxun.yang@flygoat.com>, Aleksandar Rikalo <aleksandar.rikalo@syrmia.com>
target/mips/cpu-defs.c.inc | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
[PATCH] target/mips: enable GINVx support for I6400 and I6500
Posted by Marcin Nowakowski 2 years, 7 months ago 
GINVI and GINVT operations are supported on MIPS I6400 and I6500 cores,
so indicate that properly in CP0.Config5 register bits [16:15].

Signed-off-by: Marcin Nowakowski <marcin.nowakowski@fungible.com>
---
 target/mips/cpu-defs.c.inc | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/target/mips/cpu-defs.c.inc b/target/mips/cpu-defs.c.inc
index d45f245a67..da122e72d7 100644
--- a/target/mips/cpu-defs.c.inc
+++ b/target/mips/cpu-defs.c.inc
@@ -709,7 +709,7 @@ const mips_def_t mips_defs[] =
         .CP0_Config4 = MIPS_CONFIG4 | (1U << CP0C4_M) | (3 << CP0C4_IE) |
                        (1 << CP0C4_AE) | (0xfc << CP0C4_KScrExist),
         .CP0_Config5 = MIPS_CONFIG5 | (1 << CP0C5_XNP) | (1 << CP0C5_VP) |
-                       (1 << CP0C5_LLB) | (1 << CP0C5_MRP),
+                       (1 << CP0C5_LLB) | (1 << CP0C5_MRP) | (3 << CP0C5_GI),
         .CP0_Config5_rw_bitmask = (1 << CP0C5_MSAEn) | (1 << CP0C5_SBRI) |
                                   (1 << CP0C5_FRE) | (1 << CP0C5_UFE),
         .CP0_LLAddr_rw_bitmask = 0,
@@ -749,7 +749,7 @@ const mips_def_t mips_defs[] =
         .CP0_Config4 = MIPS_CONFIG4 | (1U << CP0C4_M) | (3 << CP0C4_IE) |
                        (1 << CP0C4_AE) | (0xfc << CP0C4_KScrExist),
         .CP0_Config5 = MIPS_CONFIG5 | (1 << CP0C5_XNP) | (1 << CP0C5_VP) |
-                       (1 << CP0C5_LLB) | (1 << CP0C5_MRP),
+                       (1 << CP0C5_LLB) | (1 << CP0C5_MRP) | (3 << CP0C5_GI),
         .CP0_Config5_rw_bitmask = (1 << CP0C5_MSAEn) | (1 << CP0C5_SBRI) |
                                   (1 << CP0C5_FRE) | (1 << CP0C5_UFE),
         .CP0_LLAddr_rw_bitmask = 0,
-- 
2.25.1
Re: [PATCH] target/mips: enable GINVx support for I6400 and I6500
Posted by Philippe Mathieu-Daudé 2 years, 7 months ago 
On 30/6/23 09:28, Marcin Nowakowski wrote:
> GINVI and GINVT operations are supported on MIPS I6400 and I6500 cores,
> so indicate that properly in CP0.Config5 register bits [16:15].
> 
> Signed-off-by: Marcin Nowakowski <marcin.nowakowski@fungible.com>
> ---
>   target/mips/cpu-defs.c.inc | 4 ++--
>   1 file changed, 2 insertions(+), 2 deletions(-)

Thanks, queued to mips-next.
Re: [PATCH] target/mips: enable GINVx support for I6400 and I6500
Posted by Jiaxun Yang 2 years, 7 months ago 

在 2023/6/30 15:28, Marcin Nowakowski 写道:
> GINVI and GINVT operations are supported on MIPS I6400 and I6500 cores,
> so indicate that properly in CP0.Config5 register bits [16:15].
>
> Signed-off-by: Marcin Nowakowski <marcin.nowakowski@fungible.com>

VZ is unimplemented in TCG so perhaps we should leave them as not supported?

Thanks
- Jiaxun

> ---
>   target/mips/cpu-defs.c.inc | 4 ++--
>   1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/target/mips/cpu-defs.c.inc b/target/mips/cpu-defs.c.inc
> index d45f245a67..da122e72d7 100644
> --- a/target/mips/cpu-defs.c.inc
> +++ b/target/mips/cpu-defs.c.inc
> @@ -709,7 +709,7 @@ const mips_def_t mips_defs[] =
>           .CP0_Config4 = MIPS_CONFIG4 | (1U << CP0C4_M) | (3 << CP0C4_IE) |
>                          (1 << CP0C4_AE) | (0xfc << CP0C4_KScrExist),
>           .CP0_Config5 = MIPS_CONFIG5 | (1 << CP0C5_XNP) | (1 << CP0C5_VP) |
> -                       (1 << CP0C5_LLB) | (1 << CP0C5_MRP),
> +                       (1 << CP0C5_LLB) | (1 << CP0C5_MRP) | (3 << CP0C5_GI),
>           .CP0_Config5_rw_bitmask = (1 << CP0C5_MSAEn) | (1 << CP0C5_SBRI) |
>                                     (1 << CP0C5_FRE) | (1 << CP0C5_UFE),
>           .CP0_LLAddr_rw_bitmask = 0,
> @@ -749,7 +749,7 @@ const mips_def_t mips_defs[] =
>           .CP0_Config4 = MIPS_CONFIG4 | (1U << CP0C4_M) | (3 << CP0C4_IE) |
>                          (1 << CP0C4_AE) | (0xfc << CP0C4_KScrExist),
>           .CP0_Config5 = MIPS_CONFIG5 | (1 << CP0C5_XNP) | (1 << CP0C5_VP) |
> -                       (1 << CP0C5_LLB) | (1 << CP0C5_MRP),
> +                       (1 << CP0C5_LLB) | (1 << CP0C5_MRP) | (3 << CP0C5_GI),
>           .CP0_Config5_rw_bitmask = (1 << CP0C5_MSAEn) | (1 << CP0C5_SBRI) |
>                                     (1 << CP0C5_FRE) | (1 << CP0C5_UFE),
>           .CP0_LLAddr_rw_bitmask = 0,
Re: [PATCH] target/mips: enable GINVx support for I6400 and I6500
Posted by Philippe Mathieu-Daudé 2 years, 7 months ago 
On 10/7/23 14:58, Jiaxun Yang wrote:
> 
> 
> 在 2023/6/30 15:28, Marcin Nowakowski 写道:
>> GINVI and GINVT operations are supported on MIPS I6400 and I6500 cores,
>> so indicate that properly in CP0.Config5 register bits [16:15].
>>
>> Signed-off-by: Marcin Nowakowski <marcin.nowakowski@fungible.com>
> 
> VZ is unimplemented in TCG so perhaps we should leave them as not 
> supported?

GINVI and GINVT instr were implemented in commit 99029be1c2
("target/mips: Add implementation of GINVT instruction").
Re: [PATCH] target/mips: enable GINVx support for I6400 and I6500
Posted by Philippe Mathieu-Daudé 2 years, 7 months ago 
On 30/6/23 09:28, Marcin Nowakowski wrote:
> GINVI and GINVT operations are supported on MIPS I6400 and I6500 cores,
> so indicate that properly in CP0.Config5 register bits [16:15].
> 
> Signed-off-by: Marcin Nowakowski <marcin.nowakowski@fungible.com>
> ---
>   target/mips/cpu-defs.c.inc | 4 ++--
>   1 file changed, 2 insertions(+), 2 deletions(-)

Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>

Patchew 2.1-devel-b67e4c2

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