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[78.8.247.128]) by smtp.gmail.com with ESMTPSA id jw19-20020a170903279300b001b7ed16c7ffsm9381416plb.306.2023.06.30.00.28.14 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 30 Jun 2023 00:28:16 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=fungible.com; s=google; t=1688110101; x=1690702101; h=content-transfer-encoding:mime-version:message-id:date:subject:to :from:from:to:cc:subject:date:message-id:reply-to; bh=7NIXm3S2ofFeqF888HBnrL1QNbDutjXr9HIiL252Hzs=; b=RvR4tSBqartgDm1lg2wyg3JTS6rWyxOVOrpBH5gIcznBEsy7A0gP6o3nvna8erZThL /CAZ8h/P5MqlPl1AQyQgVQ3vsa1YEjgtTp6eZ7db1jT+DtIta2SxcOQME3K+wZ4v6oAj 0C7+oRvQcg8w4JgyDJZz8otU773p+42746P1M= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1688110101; x=1690702101; h=content-transfer-encoding:mime-version:message-id:date:subject:to :from:x-gm-message-state:from:to:cc:subject:date:message-id:reply-to; bh=7NIXm3S2ofFeqF888HBnrL1QNbDutjXr9HIiL252Hzs=; b=NC9MRG/z50dv2PvrxUt7n6hJBRdJocTepEjnZTVRpiDFzaTEkTSBXQIHf7abWfgpEL /QGRwz4cNB7ENUbpuJ9KrtgWWILjMHDpGAr61+bzF87l/yFrrY9mMw3LVca68NBpgv/G 1+9ha7im5CvNNWC6cMmCZWuqPGNQ4trPNFIHmt7/hrwySEXt/IhVr4NhkEUGKOhlfXoT /NF3K1xFsQxc1+98Zeq2xL0WgH199yxijr8xTF5P4J/Fft3QjkKeFDZKWX/ebC5oyhxL 0E9AO9rQoOwpA9lPK51IOJw4+XwenGHSDT+v88yz/ULsDwD1cEl/0zoeMZ04pYtrsB8N XZ2g== X-Gm-Message-State: ABy/qLYBH83jU+W8drI979jZJC+OXZ5iB/GNtGCm2SLs3CIBJYIo/VIk fgYGzrX/ANONHshXSxUrTe4JAw== X-Google-Smtp-Source: APBJJlFynGo/KSCYKqPo9LlvlFMzYtuKeAZxu9P66vhSlfXmfWQnHs6sd6P7YFQmciqRmKNX4CLqAg== X-Received: by 2002:a17:903:481:b0:1b8:36a8:faf9 with SMTP id jj1-20020a170903048100b001b836a8faf9mr1143030plb.38.1688110100871; Fri, 30 Jun 2023 00:28:20 -0700 (PDT) From: Marcin Nowakowski To: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Aurelien Jarno , Jiaxun Yang , Aleksandar Rikalo , qemu-devel@nongnu.org (open list:All patches CC here) Subject: [PATCH] target/mips: enable GINVx support for I6400 and I6500 Date: Fri, 30 Jun 2023 09:28:06 +0200 Message-Id: <20230630072806.3093704-1-marcin.nowakowski@fungible.com> X-Mailer: git-send-email 2.25.1 MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::630; envelope-from=marcin.nowakowski@fungible.com; helo=mail-pl1-x630.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @fungible.com) X-ZM-MESSAGEID: 1688110117208100002 Content-Type: text/plain; charset="utf-8" GINVI and GINVT operations are supported on MIPS I6400 and I6500 cores, so indicate that properly in CP0.Config5 register bits [16:15]. Signed-off-by: Marcin Nowakowski Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- target/mips/cpu-defs.c.inc | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/target/mips/cpu-defs.c.inc b/target/mips/cpu-defs.c.inc index d45f245a67..da122e72d7 100644 --- a/target/mips/cpu-defs.c.inc +++ b/target/mips/cpu-defs.c.inc @@ -709,7 +709,7 @@ const mips_def_t mips_defs[] =3D .CP0_Config4 =3D MIPS_CONFIG4 | (1U << CP0C4_M) | (3 << CP0C4_IE) | (1 << CP0C4_AE) | (0xfc << CP0C4_KScrExist), .CP0_Config5 =3D MIPS_CONFIG5 | (1 << CP0C5_XNP) | (1 << CP0C5_VP)= | - (1 << CP0C5_LLB) | (1 << CP0C5_MRP), + (1 << CP0C5_LLB) | (1 << CP0C5_MRP) | (3 << CP0C5_G= I), .CP0_Config5_rw_bitmask =3D (1 << CP0C5_MSAEn) | (1 << CP0C5_SBRI)= | (1 << CP0C5_FRE) | (1 << CP0C5_UFE), .CP0_LLAddr_rw_bitmask =3D 0, @@ -749,7 +749,7 @@ const mips_def_t mips_defs[] =3D .CP0_Config4 =3D MIPS_CONFIG4 | (1U << CP0C4_M) | (3 << CP0C4_IE) | (1 << CP0C4_AE) | (0xfc << CP0C4_KScrExist), .CP0_Config5 =3D MIPS_CONFIG5 | (1 << CP0C5_XNP) | (1 << CP0C5_VP)= | - (1 << CP0C5_LLB) | (1 << CP0C5_MRP), + (1 << CP0C5_LLB) | (1 << CP0C5_MRP) | (3 << CP0C5_G= I), .CP0_Config5_rw_bitmask =3D (1 << CP0C5_MSAEn) | (1 << CP0C5_SBRI)= | (1 << CP0C5_FRE) | (1 << CP0C5_UFE), .CP0_LLAddr_rw_bitmask =3D 0, --=20 2.25.1