This patchseries does more of the conversion of the A64 decoder to
decodetree.  It covers the exception-generation, system, load and
store instructions.

The rebasing of this on top of the atomics work turned out
hairy enough that I thought it was better to send this out
as a v2. There ae also a couple of new patches at the start
that fix minor things before we start moving the code around.

changes v1->v2:
 * patch 2 is new (but already sent separately and reviewed)
 * patches 3 and 4 are new (fixes to recent refactoring)
 * patch 14 (ld/st pair) is structurally the same as the old
   patch 11, but the underlying code changed enough in the
   atomics work that I figured it was worth getting it
   re-reviewed.
 * The very cautious might also want to re-check some of
   the other load/store patches, but the changes there were
   rather less, so I have retained the R-by tags
 * patch 22 (ld/st single struct) decode reworked to follow
   RTH's suggestion

Patches needing review: 3, 4, 14, 22

thanks
-- PMM

Peter Maydell (23):
  target/arm: Fix return value from LDSMIN/LDSMAX 8/16 bit atomics
  target/arm: Return correct result for LDG when ATA=0
  target/arm: Pass memop to gen_mte_check1_mmuidx() in reg_imm9 decode
  target/arm: Consistently use finalize_memop_asimd() for ASIMD
    loads/stores
  target/arm: Convert hint instruction space to decodetree
  target/arm: Convert barrier insns to decodetree
  target/arm: Convert CFINV, XAFLAG and AXFLAG to decodetree
  target/arm: Convert MSR (immediate) to decodetree
  target/arm: Convert MSR (reg), MRS, SYS, SYSL to decodetree
  target/arm: Convert exception generation instructions to decodetree
  target/arm: Convert load/store exclusive and ordered to decodetree
  target/arm: Convert LDXP, STXP, CASP, CAS to decodetree
  target/arm: Convert load reg (literal) group to decodetree
  target/arm: Convert load/store-pair to decodetree
  target/arm: Convert ld/st reg+imm9 insns to decodetree
  target/arm: Convert LDR/STR with 12-bit immediate to decodetree
  target/arm: Convert LDR/STR reg+reg to decodetree
  target/arm: Convert atomic memory ops to decodetree
  target/arm: Convert load (pointer auth) insns to decodetree
  target/arm: Convert LDAPR/STLR (imm) to decodetree
  target/arm: Convert load/store (multiple structures) to decodetree
  target/arm: Convert load/store single structure to decodetree
  target/arm: Convert load/store tags insns to decodetree

 target/arm/tcg/a64.decode      |  403 ++++
 target/arm/tcg/translate-a64.c | 3322 ++++++++++++++------------------
 2 files changed, 1883 insertions(+), 1842 deletions(-)

-- 
2.34.1