From nobody Fri May 10 11:25:59 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1686499468; cv=none; d=zohomail.com; s=zohoarc; b=hNQ6S5AzZCqsMXhu8yUKA5mdLs2UeZHIdyj4rCWMiucwPq+QNkuHnKhP4g4GT6Aga8686vkZdRFGloBBOidK+ZKSRB/7yrn56qQwgw1o3D/LqbjMUhtoHTvK4fNYDF3TPzdrDRKfx9+NTq2I/ayRho7QlStZihN6m0COYZONYlE= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1686499468; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=QYoLjQUBzDtsQLiewQeHZyMx2G0pXSiMumiEHL4MRBM=; b=dJS91IdnFbLQfeYzh+8o8yCuGuBX4DIpYxeNwtWWGUB4SRGRKtXATmfRSpr9scPqScSm97HpnnuuExIoiH15VZ+i/P0p0/isMy8gaekx22gurFhrC6t+L7ICqBH37Uzlt+ACUUa9HMGODTUPuSz8i08Pz3kh0Z5ZGVavw0Wg/+w= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1686499468493390.4650351289945; Sun, 11 Jun 2023 09:04:28 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1q8NVc-0006Sv-7O; Sun, 11 Jun 2023 12:01:40 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1q8NUg-0005pe-CJ for qemu-devel@nongnu.org; Sun, 11 Jun 2023 12:00:49 -0400 Received: from mail-wm1-x32a.google.com ([2a00:1450:4864:20::32a]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1q8NUc-0000R5-6x for qemu-devel@nongnu.org; Sun, 11 Jun 2023 12:00:41 -0400 Received: by mail-wm1-x32a.google.com with SMTP id 5b1f17b1804b1-3f7fcdc7f7fso22690945e9.0 for ; Sun, 11 Jun 2023 09:00:35 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id m9-20020a056000008900b0030ae499da59sm9923022wrx.111.2023.06.11.09.00.34 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 11 Jun 2023 09:00:34 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1686499234; x=1689091234; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=QYoLjQUBzDtsQLiewQeHZyMx2G0pXSiMumiEHL4MRBM=; b=mcCaaGORXLo8u5KAwAVL5dLyFA6eMej5XUaOFzf6IxmKNQOB5DKtc3BgaYWNqz8k1G 02Yb44mXos0nErkqy7h9llSFN2L9nxPLOIeNGdvedR7748a6Tpn+Ie2RjsNqBkNuUxT3 Oa0JVh8SlpFjzVFD0OthX2Ek2ZgPuDqlRZgO/1oyfJGJ/jl0YNmMdhHsngA6Yo3sTRcs QxQDP7u1Ai/fjrXeIrEFLuwodnvFI4voNWMYax/F3CEnaUsAm1010AHoHLEST6i5st2i EqX33OSdOZczgw1hTfkmB0Cm6LsGnB6MDKIGwLVlRDO2ukn9CxLvS0H3oJudPxinbg33 D1JQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1686499234; x=1689091234; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=QYoLjQUBzDtsQLiewQeHZyMx2G0pXSiMumiEHL4MRBM=; b=Cw9i3GubXQR405CZ61Wg3Y/KejbyQMMQnIoPryv/g0TPtDY4C0UUZdq7ZcZNuC5WhM /CEdkoudF+FUAFJO5P8wKLM57gXbvKZ4AmavGKtY/YSoha8HHu1kC/aG6Hb3Y//vjFGf yUi10aftqjpAz23ItrM5aBnCRxoZ0Hl+wI+F2dKZvPXKddjpfX4hsqQbOiT1wtfJRycC 0ldC7LARrXEY+NErcc2sA5L+ByTZ4VXC4XSbuiYzXDrDaffKoLllVhjt34Zs7Igi41HS NIhHFEKUNePgB2DMzwFBvz//ArIXgnnu0jCNV2O8Xwe+v6eSIj7FJHfH93iORbtWY9BV dwQg== X-Gm-Message-State: AC+VfDyJ2rb/lqogQO/ncboCM8M0lJS+ZuivHeZO6XCsW19D8p2RfXFB FR9o0BYRjADpevDE70M+mj9s20Zt86BQQbDzDzI= X-Google-Smtp-Source: ACHHUZ67Mh+fCshACmW+FQTrSfuFDNU6FN1mHAfy0l2rLZSexBJ19Mc4J+VdRAtbiSyaPmtEnYVetg== X-Received: by 2002:a5d:5265:0:b0:30f:b0de:f100 with SMTP id l5-20020a5d5265000000b0030fb0def100mr3240746wrc.23.1686499234418; Sun, 11 Jun 2023 09:00:34 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH v2 01/23] target/arm: Fix return value from LDSMIN/LDSMAX 8/16 bit atomics Date: Sun, 11 Jun 2023 17:00:10 +0100 Message-Id: <20230611160032.274823-2-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230611160032.274823-1-peter.maydell@linaro.org> References: <20230611160032.274823-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32a; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1686499470554100003 Content-Type: text/plain; charset="utf-8" The atomic memory operations are supposed to return the old memory data value in the destination register. This value is not sign-extended, even if the operation is the signed minimum or maximum. (In the pseudocode for the instructions the returned data value is passed to ZeroExtend() to create the value in the register.) We got this wrong because we were doing a 32-to-64 zero extend on the result for 8 and 16 bit data values, rather than the correct amount of zero extension. Fix the bug by using ext8u and ext16u for the MO_8 and MO_16 data sizes rather than ext32u. Cc: qemu-stable@nongnu.org Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Message-id: 20230602155223.2040685-2-peter.maydell@linaro.org --- target/arm/tcg/translate-a64.c | 18 ++++++++++++++++-- 1 file changed, 16 insertions(+), 2 deletions(-) diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c index aa93f37e216..246e3c15145 100644 --- a/target/arm/tcg/translate-a64.c +++ b/target/arm/tcg/translate-a64.c @@ -3545,8 +3545,22 @@ static void disas_ldst_atomic(DisasContext *s, uint3= 2_t insn, */ fn(tcg_rt, clean_addr, tcg_rs, get_mem_index(s), mop); =20 - if ((mop & MO_SIGN) && size !=3D MO_64) { - tcg_gen_ext32u_i64(tcg_rt, tcg_rt); + if (mop & MO_SIGN) { + switch (size) { + case MO_8: + tcg_gen_ext8u_i64(tcg_rt, tcg_rt); + break; + case MO_16: + tcg_gen_ext16u_i64(tcg_rt, tcg_rt); + break; + case MO_32: + tcg_gen_ext32u_i64(tcg_rt, tcg_rt); + break; + case MO_64: + break; + default: + g_assert_not_reached(); + } } } =20 --=20 2.34.1 From nobody Fri May 10 11:25:59 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1686499364; cv=none; d=zohomail.com; s=zohoarc; b=jTc5ti9PjSmj7fTHELh8O8vHMFpEDtbrmw9uhkMbh+d/X/EHg/Uqm3QqsonxlBR47uUnIv8HLrOQ8TEZvPrgZ3y0QfsY/jpHiILVU13i6hwE0fXcWFTvLlcm89ouYSJAYOvYrT5BFlPe8DMynAXIi1+lmWKUVHrTM9CwKiXRViU= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1686499364; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=3mwJOChiCQUlVNSGMLtjTUS0WqEV7jHFVk5J5OdBzPw=; b=TPQJ7PbsfPoC2r9SlDNzZ8gwvV73DF+VEFOxWqNYoS+kdhO+tc6ztH693KPLJD6+M8Bu+eHoVo5+dYWhwxWruedBLjShk0a8aiDoIpPqg+dpgq6am2vQL+6qBAr8PC5ynSDH0M4tbjztKFutzJ5NBzwqTOPT0GdYXdA53jAWDsA= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 168649936411168.14741630090327; Sun, 11 Jun 2023 09:02:44 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1q8NVV-0006IT-EE; Sun, 11 Jun 2023 12:01:33 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1q8NUc-0005os-St for qemu-devel@nongnu.org; Sun, 11 Jun 2023 12:00:49 -0400 Received: from mail-wm1-x333.google.com ([2a00:1450:4864:20::333]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1q8NUa-0000RD-Uy for qemu-devel@nongnu.org; Sun, 11 Jun 2023 12:00:38 -0400 Received: by mail-wm1-x333.google.com with SMTP id 5b1f17b1804b1-3f738f579ceso25478135e9.3 for ; Sun, 11 Jun 2023 09:00:36 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id m9-20020a056000008900b0030ae499da59sm9923022wrx.111.2023.06.11.09.00.34 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 11 Jun 2023 09:00:34 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1686499235; x=1689091235; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=3mwJOChiCQUlVNSGMLtjTUS0WqEV7jHFVk5J5OdBzPw=; b=WD5Cf06BdxEp5lJ9UcEmQwHjtRrPqplWvZXpeOrqx+O1Fws5QWSc9zINhHoFudIYV5 bSuM2wfH7JCskPftP8s2lXh220Hx2vHtbTH6QCGdCHk2V4PvwwXj/PwxTpeCyBzQSIvB mcV6t76GA2oYI7MjBlW0w93iH9B1jkdrSEqkbOLqQOhYVzNPNl2QIR646lRWkVNTKLus LXpLBanNCQJbsEL1UFwWRUyLWPeBtf2IF6BIuLWE+N+1VkVEDqX6gosMrFsYpDpS8ggv F8Hc0tFIOOrE+QJ5+1V3sczmxz3O+I2qZeoiG44vAn0sI5QouGtdIBuz6GvoFvqwTevD wWBQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1686499235; x=1689091235; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=3mwJOChiCQUlVNSGMLtjTUS0WqEV7jHFVk5J5OdBzPw=; b=PBKe7l5/ky99EiFKibXeXYphE0bo8AQop8K2ibeSglAVo3ayoSpxhOfBSLSl8yc6b5 fUOIRqphn4nsIwMVOg6mqJ7zOb5ouiHZFeBHYPmRsPYOVv9nzBHGSQIZpaMTvCoVcDD2 p0LI0YaLEDE90j4dFjrNCBc5NxHjn89nllN/PRh41jTnosmmmz65ib4Gbql6EdHsKLtV /jZi4rn+YVUvQX4CM6rlhcCOGdld3GNVjOwS8DdQe8vzVAINzD9Pi9zonA7UbNHsV1FR wwyeOjmRFCKHzwU4G51jluK7qO6em6wzXk8xyvp/+sb0ERySVCpdy5blVYmTMVLxlgjB LxwA== X-Gm-Message-State: AC+VfDzSaDPXCtqH1HqfAcGnAliwdUy3V1KLMQ0NkubSsIz981d2Gt9H UBiqnJmf/+W8jIznXrUNLwLMtA== X-Google-Smtp-Source: ACHHUZ4Lig6THpliuaDIF7LRRxIRzhBOfZvyup3sSo6pUxP+hPxoVl9+LKFDbFYwAE6hvFA1MTyYxw== X-Received: by 2002:a7b:c047:0:b0:3f8:1b55:ac08 with SMTP id u7-20020a7bc047000000b003f81b55ac08mr300586wmc.28.1686499234938; Sun, 11 Jun 2023 09:00:34 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH v2 02/23] target/arm: Return correct result for LDG when ATA=0 Date: Sun, 11 Jun 2023 17:00:11 +0100 Message-Id: <20230611160032.274823-3-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230611160032.274823-1-peter.maydell@linaro.org> References: <20230611160032.274823-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::333; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x333.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1686499364510100002 Content-Type: text/plain; charset="utf-8" The LDG instruction loads the tag from a memory address (identified by [Xn + offset]), and then merges that tag into the destination register Xt. We implemented this correctly for the case when allocation tags are enabled, but didn't get it right when ATA=3D0: instead of merging the tag bits into Xt, we merged them into the memory address [Xn + offset] and then set Xt to that. Merge the tag bits into the old Xt value, as they should be. Cc: qemu-stable@nongnu.org Fixes: c15294c1e36a7dd9b25 ("target/arm: Implement LDG, STG, ST2G instructi= ons") Reviewed-by: Richard Henderson Signed-off-by: Peter Maydell --- target/arm/tcg/translate-a64.c | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c index 246e3c15145..4ec857bcd8d 100644 --- a/target/arm/tcg/translate-a64.c +++ b/target/arm/tcg/translate-a64.c @@ -4201,9 +4201,13 @@ static void disas_ldst_tag(DisasContext *s, uint32_t= insn) if (s->ata) { gen_helper_ldg(tcg_rt, cpu_env, addr, tcg_rt); } else { + /* + * Tag access disabled: we must check for aborts on the load + * load from [rn+offset], and then insert a 0 tag into rt. + */ clean_addr =3D clean_data_tbi(s, addr); gen_probe_access(s, clean_addr, MMU_DATA_LOAD, MO_8); - gen_address_with_allocation_tag0(tcg_rt, addr); + gen_address_with_allocation_tag0(tcg_rt, tcg_rt); } } else { tcg_rt =3D cpu_reg_sp(s, rt); --=20 2.34.1 From nobody Fri May 10 11:25:59 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1686499505; cv=none; d=zohomail.com; s=zohoarc; b=XTdhGHllOM6Bzp56ViUFqw4ZUQgUBrhbQFHDNaVfH06l0WH+DFhhJrih6qnmQuznBQ3ubon1/O8BXAQrHP7sh3unSMIBxywdCtXjeeow6siWJItCXS1VAkmLAHhEpikHmcYo8/WnEjO/nJprGsI39Mp1iC/YklC8RbzAwX9jYI0= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1686499505; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=+rINJvFsN+oVD80Eh3osK1p8SBHtR21Dx7Bo1Xv1nvY=; b=LCxujiE2sDbUFj2SYdgp1DgRFU32VWIoOqRN6GqYRsvS0VKegbyN7oxEIon2MMf+GiibMFJDLkHba5/jr/TZW9PJSa9PasfuDi33AHi3dpwG40RSaIEAHlS+ZGfHb2P07MMdnU8pZVc9KqesH6HChhMF3GLSj+lNugwE+KGB4UY= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1686499505637950.5226510894205; Sun, 11 Jun 2023 09:05:05 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1q8NVb-0006Po-2e; Sun, 11 Jun 2023 12:01:39 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1q8NUe-0005ox-G2 for qemu-devel@nongnu.org; Sun, 11 Jun 2023 12:00:49 -0400 Received: from mail-wr1-x429.google.com ([2a00:1450:4864:20::429]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1q8NUb-0000RQ-0t for qemu-devel@nongnu.org; Sun, 11 Jun 2023 12:00:39 -0400 Received: by mail-wr1-x429.google.com with SMTP id ffacd0b85a97d-30af159b433so3329081f8f.3 for ; Sun, 11 Jun 2023 09:00:36 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id m9-20020a056000008900b0030ae499da59sm9923022wrx.111.2023.06.11.09.00.35 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 11 Jun 2023 09:00:35 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1686499235; x=1689091235; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=+rINJvFsN+oVD80Eh3osK1p8SBHtR21Dx7Bo1Xv1nvY=; b=YRcr2d3yuZ/IcB8tq+IMkrHwwlyX5WwRQArfK42t58w6cApfDQ0E+HYtMXZ6epNyTw jJgCiH1cBskj4v+DC1+JDPCUERaVRLedoud0HbIot6asLeX/jikNjOzK1+QU2XSTKEmr VQoeZVBz0xgYHFMnl3faflHibRKFJkp/wMW1RNSGfv/cIZhhqwZBdHiaNhHnwod8VyHS 8kvUj8OD96mdMH8HxBCXBzSx0O1gkVlIjva8vit8z4Uupv0UZZ/moZ4KSd5spq2tm5iZ ORmRQUBcoK56+mH0GI5ikyXYbdrGWjKV3pM3/Z4o/LTXR+/vRjDEwiNtkLKn16QOtFnI vDAA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1686499235; x=1689091235; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=+rINJvFsN+oVD80Eh3osK1p8SBHtR21Dx7Bo1Xv1nvY=; b=PfQlHMWxcrVq93+eoRcc+uQf3Q7G9zZDJlUk3QQJzqHcbbrnJeEIqOM67NES1q7qrP qiV1B/sZ+mLfGghptHM5Mh6KctWXho9fU+fQs4nCanrpVu3r7LIaQiFm3Gf9ALeTqndo cjvEpeqS4rIU3t4/5/ol39k3nLMxwyCl3PJkMCWrP3cGH9umFnU1xCFZ0iMc44TsZw// iAuIm/x7d+XAREF/uPqFXCh9XGjIkOP6OYKI4YYI8ENBNuSLbKaxf056fq9WSuH/zQld YtK2vq3F7PdAIbxsBruaqFMtEdL6xtflvmrwj7HAam+7fVmLHSeV6DmcidnX6UytUPfn 6+qw== X-Gm-Message-State: AC+VfDxwKccY6D59TyNWM38akbVVLmhahk18EhRIC6U9bQ50hriYwr16 VKmhUSscWTLlKdVyrdz+e7xT+W+++6qEIREGRSQ= X-Google-Smtp-Source: ACHHUZ66KF9IFzxhY2U4vA01+QjyfeEgK+Q/FFvk8yRnpIox3X4HbZdin9qvL9520/7HGffFRJydxw== X-Received: by 2002:a05:6000:136c:b0:30f:c243:d7e7 with SMTP id q12-20020a056000136c00b0030fc243d7e7mr199984wrz.68.1686499235464; Sun, 11 Jun 2023 09:00:35 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH v2 03/23] target/arm: Pass memop to gen_mte_check1_mmuidx() in reg_imm9 decode Date: Sun, 11 Jun 2023 17:00:12 +0100 Message-Id: <20230611160032.274823-4-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230611160032.274823-1-peter.maydell@linaro.org> References: <20230611160032.274823-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::429; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x429.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1686499505855100001 Content-Type: text/plain; charset="utf-8" In disas_ldst_reg_imm9() we missed one place where a call to a gen_mte_check* function should now be passed the memop we have created rather than just being passed the size. Fix this. Signed-off-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson --- target/arm/tcg/translate-a64.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c index 4ec857bcd8d..d271449431a 100644 --- a/target/arm/tcg/translate-a64.c +++ b/target/arm/tcg/translate-a64.c @@ -3226,7 +3226,7 @@ static void disas_ldst_reg_imm9(DisasContext *s, uint= 32_t insn, =20 clean_addr =3D gen_mte_check1_mmuidx(s, dirty_addr, is_store, writeback || rn !=3D 31, - size, is_unpriv, memidx); + memop, is_unpriv, memidx); =20 if (is_vector) { if (is_store) { --=20 2.34.1 From nobody Fri May 10 11:25:59 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1686499399; cv=none; d=zohomail.com; s=zohoarc; b=FrDoiapoMROPeqHPc1ozm+ZphXIdQPZKvpFdYc2fAnAptBGxtSOiYuZiVxhK4YAea2V5PX61qctPHg2VxvqeQGTEdzGMpOdBEpy2XC1isWTA0SLcsbvrF63f/P7IBOw7zzkd7BF5UziYW7FVftpoxURQ+3fE4Z9c+M7fzHUSBOA= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1686499399; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=bzdwcdEJDH3+9LvIk3s+qDKAfWLrlUNUbth2GVMBPBg=; b=gYlLFW3LjD36dtXTfnHMNdHkLIWjuG9StLTOY46iZANOfpr4n2YoLUx6VFzqQOM0wcO/0LhRTLCIQRYfPoPTDFYyYEY8KAgr1fYS+Wc57oMsz0SMKR6xawAZKroYfNy95RAsecNMMo/PcTrwvGMVdQb5nFgDQ1rpQu6S6SmP+6U= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1686499399068407.9372328978719; Sun, 11 Jun 2023 09:03:19 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1q8NVl-0006hy-Ka; Sun, 11 Jun 2023 12:01:49 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1q8NUg-0005pd-9t for qemu-devel@nongnu.org; Sun, 11 Jun 2023 12:00:49 -0400 Received: from mail-wr1-x435.google.com ([2a00:1450:4864:20::435]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1q8NUc-0000Rc-7G for qemu-devel@nongnu.org; Sun, 11 Jun 2023 12:00:41 -0400 Received: by mail-wr1-x435.google.com with SMTP id ffacd0b85a97d-30fb4b3e62fso538283f8f.2 for ; Sun, 11 Jun 2023 09:00:37 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id m9-20020a056000008900b0030ae499da59sm9923022wrx.111.2023.06.11.09.00.35 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 11 Jun 2023 09:00:35 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1686499236; x=1689091236; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=bzdwcdEJDH3+9LvIk3s+qDKAfWLrlUNUbth2GVMBPBg=; b=TP5j7R5aWCmSlMxWZ53YfX5KXxqW3flVjsON8OnwCjLZpE//x8roiwKhryCBXwIJb/ XMhbXLdbWXjNoNZ89f/8e+azDA9j8sU3KIdjLhktrd5yHEbb3Zrn43BGOCLW4vObR/oS pfw8XUESrbiXw0G11nt/0BgNtAJ6DQAAg+3BhNTHjcs6lxypj+8jhGkL2xykJL0iAkn8 i05Fesl1auCcvCN3PgY68YCOGmmTypivdUbHp9cTiTgzRFR5Xf6IH5okbEmry+QAENiy /de4o+IZP3Od551fSMDL6vnBmpFrzAkVr/Hxx3Dt+uccgFrLpGh4ASyvOFTtM5f0qahP g93w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1686499236; x=1689091236; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=bzdwcdEJDH3+9LvIk3s+qDKAfWLrlUNUbth2GVMBPBg=; b=PYAWVy9MpxvUUDyi0VtDWwFrF4prddDU0n2JdO1tnc4MEJ69rgi8gqB6BRo46/5nK5 mz4hk4OZzxpQfCt1p2dohFgH+yiJZmBZXb0tAetcadT0iIiXgN6zyEUNk9Ydh61+0pqY Tv/5x5MCMe+aW1HHNzOYxwf81KedsHVsgnZ9uRLa/+zglqovZamykJnJ/e3evpTwCP+h tOQQ4WomOl06u583fgabSgtOIR/Dn2jK1dz+dDnuuvbMYIaEpV9iXbFHzRAV8Ek2ilCZ x0d4X4KJ73QMoWd0RP6MayNU5Az68IJQPdNRHJvjJT2KEOjMZLMxQBEPeo4QJeHPTS8p vDZg== X-Gm-Message-State: AC+VfDwxoh2dLzVi/SlyYhU0ksFlCKgU8tHW/AC2hYR1GtlVD/KmYO5W b5CVjxHNrDzFIbFkjS8u8oDYsi5WysLJoLH3SpE= X-Google-Smtp-Source: ACHHUZ6342Ved2HTi7CCgJnt+75jYRRhueycfoFOVdEQ542WvnmVAnlMy7OMg5LM/bJUUHSVGJ95Hg== X-Received: by 2002:a5d:4acb:0:b0:30a:e542:c5c9 with SMTP id y11-20020a5d4acb000000b0030ae542c5c9mr2685698wrs.24.1686499236055; Sun, 11 Jun 2023 09:00:36 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH v2 04/23] target/arm: Consistently use finalize_memop_asimd() for ASIMD loads/stores Date: Sun, 11 Jun 2023 17:00:13 +0100 Message-Id: <20230611160032.274823-5-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230611160032.274823-1-peter.maydell@linaro.org> References: <20230611160032.274823-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::435; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x435.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1686499400665100008 Content-Type: text/plain; charset="utf-8" In the recent refactoring we missed a few places which should be calling finalize_memop_asimd() for ASIMD loads and stores but instead are just calling finalize_memop(); fix these. For the disas_ldst_single_struct() and disas_ldst_multiple_struct() cases, this is not a behaviour change because there the size is never MO_128 and the two finalize functions do the same thing. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target/arm/tcg/translate-a64.c | 10 ++++++---- 1 file changed, 6 insertions(+), 4 deletions(-) diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c index d271449431a..1108f8287b8 100644 --- a/target/arm/tcg/translate-a64.c +++ b/target/arm/tcg/translate-a64.c @@ -3309,6 +3309,7 @@ static void disas_ldst_reg_roffset(DisasContext *s, u= int32_t insn, if (!fp_access_check(s)) { return; } + memop =3D finalize_memop_asimd(s, size); } else { if (size =3D=3D 3 && opc =3D=3D 2) { /* PRFM - prefetch */ @@ -3321,6 +3322,7 @@ static void disas_ldst_reg_roffset(DisasContext *s, u= int32_t insn, is_store =3D (opc =3D=3D 0); is_signed =3D !is_store && extract32(opc, 1, 1); is_extended =3D (size < 3) && extract32(opc, 0, 1); + memop =3D finalize_memop(s, size + is_signed * MO_SIGN); } =20 if (rn =3D=3D 31) { @@ -3333,7 +3335,6 @@ static void disas_ldst_reg_roffset(DisasContext *s, u= int32_t insn, =20 tcg_gen_add_i64(dirty_addr, dirty_addr, tcg_rm); =20 - memop =3D finalize_memop(s, size + is_signed * MO_SIGN); clean_addr =3D gen_mte_check1(s, dirty_addr, is_store, true, memop); =20 if (is_vector) { @@ -3398,6 +3399,7 @@ static void disas_ldst_reg_unsigned_imm(DisasContext = *s, uint32_t insn, if (!fp_access_check(s)) { return; } + memop =3D finalize_memop_asimd(s, size); } else { if (size =3D=3D 3 && opc =3D=3D 2) { /* PRFM - prefetch */ @@ -3410,6 +3412,7 @@ static void disas_ldst_reg_unsigned_imm(DisasContext = *s, uint32_t insn, is_store =3D (opc =3D=3D 0); is_signed =3D !is_store && extract32(opc, 1, 1); is_extended =3D (size < 3) && extract32(opc, 0, 1); + memop =3D finalize_memop(s, size + is_signed * MO_SIGN); } =20 if (rn =3D=3D 31) { @@ -3419,7 +3422,6 @@ static void disas_ldst_reg_unsigned_imm(DisasContext = *s, uint32_t insn, offset =3D imm12 << size; tcg_gen_addi_i64(dirty_addr, dirty_addr, offset); =20 - memop =3D finalize_memop(s, size + is_signed * MO_SIGN); clean_addr =3D gen_mte_check1(s, dirty_addr, is_store, rn !=3D 31, mem= op); =20 if (is_vector) { @@ -3861,7 +3863,7 @@ static void disas_ldst_multiple_struct(DisasContext *= s, uint32_t insn) * promote consecutive little-endian elements below. */ clean_addr =3D gen_mte_checkN(s, tcg_rn, is_store, is_postidx || rn != =3D 31, - total, finalize_memop(s, size)); + total, finalize_memop_asimd(s, size)); =20 /* * Consecutive little-endian elements from a single register @@ -4019,7 +4021,7 @@ static void disas_ldst_single_struct(DisasContext *s,= uint32_t insn) total =3D selem << scale; tcg_rn =3D cpu_reg_sp(s, rn); =20 - mop =3D finalize_memop(s, scale); + mop =3D finalize_memop_asimd(s, scale); =20 clean_addr =3D gen_mte_checkN(s, tcg_rn, !is_load, is_postidx || rn != =3D 31, total, mop); --=20 2.34.1 From nobody Fri May 10 11:25:59 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id m9-20020a056000008900b0030ae499da59sm9923022wrx.111.2023.06.11.09.00.36 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 11 Jun 2023 09:00:36 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1686499236; x=1689091236; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=tdjaSXSdLsKu4MO87YZyRq3fS44rsN7i4e3GLBzxGpI=; b=GrAVhpesV/vOpDjAWBgmbsaQ5nB9zyuAeSUVrjO8t3X9dgp3KaHoCnVpyN6UWwuyHD jt5hB59yssTkT73UOElTRWlB7PIup/lcuighshQvSNT9Gy4YrLWze1fW2SjwDzqjudJf 9WSvLYDvVLjUROz5iFFQnCii/4nroQlG/QPxcpfw5LMJxFr9nRDsGW1b89/DHk4o2gNz HrGezyof+9TRUxA6MOj6G5XGQm4wwpemw1CuvCaQ3nJbVAxstDe+kAEFiSfT8zKQnC7C lKnFJESyCN5J1jdYHCL/bSX9hAKfSyKCTGgEoEHaT5fckYeY/Cn0tnA88q2YTM8DNQZ5 wBlg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1686499236; x=1689091236; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=tdjaSXSdLsKu4MO87YZyRq3fS44rsN7i4e3GLBzxGpI=; b=E4KZmsShagSzkQLYPI20HjjtZk9uVxzhBe8suMsOkTNN9hYs4UQsbBZonUgYLvew7A Z9yi6MIKFTXEzwbiMaCUyq4+pV6FBwVjfnfYde77cU+u8GrwCitSJOKW69bcd8elSjuB 9IpR19zqy1oTBDpO9zWpAXLsd2WepQfavEL/mOW/VYn/yqqVG/i0Oqda6DgKx+GXo0s8 UTqXRyNq3Qmuej9Ccerd5gKuILXwxCltL2p7a8pnYsM65KP3RmI226LZj2QslUQKyQOe jRfcQ/2BhQP+HfE7+FXv2DyUDYfjzgzMb29sis9KRiWkixsV8zU/3/Ai6r61JWwKAHrs oaLw== X-Gm-Message-State: AC+VfDwl129BfqzlxSr3X0Z3yiNWwp8eNvvLKOE7lXYn/l/Jan39iJfn 44Z8AcnUwKR9NRoxfZAkYLV0ug== X-Google-Smtp-Source: ACHHUZ7kRqF8I5kYzxdmnYFFypm5F+tISPZNd+8utzo3V5vyIFNo+wxEQJ6nhmYfDu1M5P97cvWc2Q== X-Received: by 2002:a7b:cc82:0:b0:3f6:f4b:38bd with SMTP id p2-20020a7bcc82000000b003f60f4b38bdmr4487715wma.8.1686499236652; Sun, 11 Jun 2023 09:00:36 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH v2 05/23] target/arm: Convert hint instruction space to decodetree Date: Sun, 11 Jun 2023 17:00:14 +0100 Message-Id: <20230611160032.274823-6-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230611160032.274823-1-peter.maydell@linaro.org> References: <20230611160032.274823-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::335; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x335.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1686499364526100003 Content-Type: text/plain; charset="utf-8" Convert the various instructions in the hint instruction space to decodetree. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Message-id: 20230602155223.2040685-3-peter.maydell@linaro.org --- target/arm/tcg/a64.decode | 31 ++++ target/arm/tcg/translate-a64.c | 277 ++++++++++++++++++--------------- 2 files changed, 185 insertions(+), 123 deletions(-) diff --git a/target/arm/tcg/a64.decode b/target/arm/tcg/a64.decode index 12a310d0a31..1efd436e175 100644 --- a/target/arm/tcg/a64.decode +++ b/target/arm/tcg/a64.decode @@ -150,3 +150,34 @@ ERETA 1101011 0100 11111 00001 m:1 11111 111= 11 &reta # ERETAA, ERETAB # the processor is in halting debug state (which we don't implement). # The pattern is listed here as documentation. # DRPS 1101011 0101 11111 000000 11111 00000 + +# Hint instruction group +{ + [ + YIELD 1101 0101 0000 0011 0010 0000 001 11111 + WFE 1101 0101 0000 0011 0010 0000 010 11111 + WFI 1101 0101 0000 0011 0010 0000 011 11111 + # We implement WFE to never block, so our SEV/SEVL are NOPs + # SEV 1101 0101 0000 0011 0010 0000 100 11111 + # SEVL 1101 0101 0000 0011 0010 0000 101 11111 + # Our DGL is a NOP because we don't merge memory accesses anyway. + # DGL 1101 0101 0000 0011 0010 0000 110 11111 + XPACLRI 1101 0101 0000 0011 0010 0000 111 11111 + PACIA1716 1101 0101 0000 0011 0010 0001 000 11111 + PACIB1716 1101 0101 0000 0011 0010 0001 010 11111 + AUTIA1716 1101 0101 0000 0011 0010 0001 100 11111 + AUTIB1716 1101 0101 0000 0011 0010 0001 110 11111 + ESB 1101 0101 0000 0011 0010 0010 000 11111 + PACIAZ 1101 0101 0000 0011 0010 0011 000 11111 + PACIASP 1101 0101 0000 0011 0010 0011 001 11111 + PACIBZ 1101 0101 0000 0011 0010 0011 010 11111 + PACIBSP 1101 0101 0000 0011 0010 0011 011 11111 + AUTIAZ 1101 0101 0000 0011 0010 0011 100 11111 + AUTIASP 1101 0101 0000 0011 0010 0011 101 11111 + AUTIBZ 1101 0101 0000 0011 0010 0011 110 11111 + AUTIBSP 1101 0101 0000 0011 0010 0011 111 11111 + ] + # The canonical NOP has CRm =3D=3D op2 =3D=3D 0, but all of the space + # that isn't specifically allocated to an instruction must NOP + NOP 1101 0101 0000 0011 0010 ---- --- 11111 +} diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c index 1108f8287b8..eb8addac1b3 100644 --- a/target/arm/tcg/translate-a64.c +++ b/target/arm/tcg/translate-a64.c @@ -1649,133 +1649,167 @@ static bool trans_ERETA(DisasContext *s, arg_reta= *a) return true; } =20 -/* HINT instruction group, including various allocated HINTs */ -static void handle_hint(DisasContext *s, uint32_t insn, - unsigned int op1, unsigned int op2, unsigned int c= rm) +static bool trans_NOP(DisasContext *s, arg_NOP *a) { - unsigned int selector =3D crm << 3 | op2; + return true; +} =20 - if (op1 !=3D 3) { - unallocated_encoding(s); - return; +static bool trans_YIELD(DisasContext *s, arg_YIELD *a) +{ + /* + * When running in MTTCG we don't generate jumps to the yield and + * WFE helpers as it won't affect the scheduling of other vCPUs. + * If we wanted to more completely model WFE/SEV so we don't busy + * spin unnecessarily we would need to do something more involved. + */ + if (!(tb_cflags(s->base.tb) & CF_PARALLEL)) { + s->base.is_jmp =3D DISAS_YIELD; } + return true; +} =20 - switch (selector) { - case 0b00000: /* NOP */ - break; - case 0b00011: /* WFI */ - s->base.is_jmp =3D DISAS_WFI; - break; - case 0b00001: /* YIELD */ - /* When running in MTTCG we don't generate jumps to the yield and - * WFE helpers as it won't affect the scheduling of other vCPUs. - * If we wanted to more completely model WFE/SEV so we don't busy - * spin unnecessarily we would need to do something more involved. +static bool trans_WFI(DisasContext *s, arg_WFI *a) +{ + s->base.is_jmp =3D DISAS_WFI; + return true; +} + +static bool trans_WFE(DisasContext *s, arg_WFI *a) +{ + /* + * When running in MTTCG we don't generate jumps to the yield and + * WFE helpers as it won't affect the scheduling of other vCPUs. + * If we wanted to more completely model WFE/SEV so we don't busy + * spin unnecessarily we would need to do something more involved. + */ + if (!(tb_cflags(s->base.tb) & CF_PARALLEL)) { + s->base.is_jmp =3D DISAS_WFE; + } + return true; +} + +static bool trans_XPACLRI(DisasContext *s, arg_XPACLRI *a) +{ + if (s->pauth_active) { + gen_helper_xpaci(cpu_X[30], cpu_env, cpu_X[30]); + } + return true; +} + +static bool trans_PACIA1716(DisasContext *s, arg_PACIA1716 *a) +{ + if (s->pauth_active) { + gen_helper_pacia(cpu_X[17], cpu_env, cpu_X[17], cpu_X[16]); + } + return true; +} + +static bool trans_PACIB1716(DisasContext *s, arg_PACIB1716 *a) +{ + if (s->pauth_active) { + gen_helper_pacib(cpu_X[17], cpu_env, cpu_X[17], cpu_X[16]); + } + return true; +} + +static bool trans_AUTIA1716(DisasContext *s, arg_AUTIA1716 *a) +{ + if (s->pauth_active) { + gen_helper_autia(cpu_X[17], cpu_env, cpu_X[17], cpu_X[16]); + } + return true; +} + +static bool trans_AUTIB1716(DisasContext *s, arg_AUTIB1716 *a) +{ + if (s->pauth_active) { + gen_helper_autib(cpu_X[17], cpu_env, cpu_X[17], cpu_X[16]); + } + return true; +} + +static bool trans_ESB(DisasContext *s, arg_ESB *a) +{ + /* Without RAS, we must implement this as NOP. */ + if (dc_isar_feature(aa64_ras, s)) { + /* + * QEMU does not have a source of physical SErrors, + * so we are only concerned with virtual SErrors. + * The pseudocode in the ARM for this case is + * if PSTATE.EL IN {EL0, EL1} && EL2Enabled() then + * AArch64.vESBOperation(); + * Most of the condition can be evaluated at translation time. + * Test for EL2 present, and defer test for SEL2 to runtime. */ - if (!(tb_cflags(s->base.tb) & CF_PARALLEL)) { - s->base.is_jmp =3D DISAS_YIELD; + if (s->current_el <=3D 1 && arm_dc_feature(s, ARM_FEATURE_EL2)) { + gen_helper_vesb(cpu_env); } - break; - case 0b00010: /* WFE */ - if (!(tb_cflags(s->base.tb) & CF_PARALLEL)) { - s->base.is_jmp =3D DISAS_WFE; - } - break; - case 0b00100: /* SEV */ - case 0b00101: /* SEVL */ - case 0b00110: /* DGH */ - /* we treat all as NOP at least for now */ - break; - case 0b00111: /* XPACLRI */ - if (s->pauth_active) { - gen_helper_xpaci(cpu_X[30], cpu_env, cpu_X[30]); - } - break; - case 0b01000: /* PACIA1716 */ - if (s->pauth_active) { - gen_helper_pacia(cpu_X[17], cpu_env, cpu_X[17], cpu_X[16]); - } - break; - case 0b01010: /* PACIB1716 */ - if (s->pauth_active) { - gen_helper_pacib(cpu_X[17], cpu_env, cpu_X[17], cpu_X[16]); - } - break; - case 0b01100: /* AUTIA1716 */ - if (s->pauth_active) { - gen_helper_autia(cpu_X[17], cpu_env, cpu_X[17], cpu_X[16]); - } - break; - case 0b01110: /* AUTIB1716 */ - if (s->pauth_active) { - gen_helper_autib(cpu_X[17], cpu_env, cpu_X[17], cpu_X[16]); - } - break; - case 0b10000: /* ESB */ - /* Without RAS, we must implement this as NOP. */ - if (dc_isar_feature(aa64_ras, s)) { - /* - * QEMU does not have a source of physical SErrors, - * so we are only concerned with virtual SErrors. - * The pseudocode in the ARM for this case is - * if PSTATE.EL IN {EL0, EL1} && EL2Enabled() then - * AArch64.vESBOperation(); - * Most of the condition can be evaluated at translation time. - * Test for EL2 present, and defer test for SEL2 to runtime. - */ - if (s->current_el <=3D 1 && arm_dc_feature(s, ARM_FEATURE_EL2)= ) { - gen_helper_vesb(cpu_env); - } - } - break; - case 0b11000: /* PACIAZ */ - if (s->pauth_active) { - gen_helper_pacia(cpu_X[30], cpu_env, cpu_X[30], - tcg_constant_i64(0)); - } - break; - case 0b11001: /* PACIASP */ - if (s->pauth_active) { - gen_helper_pacia(cpu_X[30], cpu_env, cpu_X[30], cpu_X[31]); - } - break; - case 0b11010: /* PACIBZ */ - if (s->pauth_active) { - gen_helper_pacib(cpu_X[30], cpu_env, cpu_X[30], - tcg_constant_i64(0)); - } - break; - case 0b11011: /* PACIBSP */ - if (s->pauth_active) { - gen_helper_pacib(cpu_X[30], cpu_env, cpu_X[30], cpu_X[31]); - } - break; - case 0b11100: /* AUTIAZ */ - if (s->pauth_active) { - gen_helper_autia(cpu_X[30], cpu_env, cpu_X[30], - tcg_constant_i64(0)); - } - break; - case 0b11101: /* AUTIASP */ - if (s->pauth_active) { - gen_helper_autia(cpu_X[30], cpu_env, cpu_X[30], cpu_X[31]); - } - break; - case 0b11110: /* AUTIBZ */ - if (s->pauth_active) { - gen_helper_autib(cpu_X[30], cpu_env, cpu_X[30], - tcg_constant_i64(0)); - } - break; - case 0b11111: /* AUTIBSP */ - if (s->pauth_active) { - gen_helper_autib(cpu_X[30], cpu_env, cpu_X[30], cpu_X[31]); - } - break; - default: - /* default specified as NOP equivalent */ - break; } + return true; +} + +static bool trans_PACIAZ(DisasContext *s, arg_PACIAZ *a) +{ + if (s->pauth_active) { + gen_helper_pacia(cpu_X[30], cpu_env, cpu_X[30], tcg_constant_i64(0= )); + } + return true; +} + +static bool trans_PACIASP(DisasContext *s, arg_PACIASP *a) +{ + if (s->pauth_active) { + gen_helper_pacia(cpu_X[30], cpu_env, cpu_X[30], cpu_X[31]); + } + return true; +} + +static bool trans_PACIBZ(DisasContext *s, arg_PACIBZ *a) +{ + if (s->pauth_active) { + gen_helper_pacib(cpu_X[30], cpu_env, cpu_X[30], tcg_constant_i64(0= )); + } + return true; +} + +static bool trans_PACIBSP(DisasContext *s, arg_PACIBSP *a) +{ + if (s->pauth_active) { + gen_helper_pacib(cpu_X[30], cpu_env, cpu_X[30], cpu_X[31]); + } + return true; +} + +static bool trans_AUTIAZ(DisasContext *s, arg_AUTIAZ *a) +{ + if (s->pauth_active) { + gen_helper_autia(cpu_X[30], cpu_env, cpu_X[30], tcg_constant_i64(0= )); + } + return true; +} + +static bool trans_AUTIASP(DisasContext *s, arg_AUTIASP *a) +{ + if (s->pauth_active) { + gen_helper_autia(cpu_X[30], cpu_env, cpu_X[30], cpu_X[31]); + } + return true; +} + +static bool trans_AUTIBZ(DisasContext *s, arg_AUTIBZ *a) +{ + if (s->pauth_active) { + gen_helper_autib(cpu_X[30], cpu_env, cpu_X[30], tcg_constant_i64(0= )); + } + return true; +} + +static bool trans_AUTIBSP(DisasContext *s, arg_AUTIBSP *a) +{ + if (s->pauth_active) { + gen_helper_autib(cpu_X[30], cpu_env, cpu_X[30], cpu_X[31]); + } + return true; } =20 static void gen_clrex(DisasContext *s, uint32_t insn) @@ -2302,9 +2336,6 @@ static void disas_system(DisasContext *s, uint32_t in= sn) return; } switch (crn) { - case 2: /* HINT (including allocated hints like NOP, YIELD, etc) */ - handle_hint(s, insn, op1, op2, crm); - break; case 3: /* CLREX, DSB, DMB, ISB */ handle_sync(s, insn, op1, op2, crm); break; --=20 2.34.1 From nobody Fri May 10 11:25:59 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1686499416; cv=none; d=zohomail.com; s=zohoarc; b=F5M/pfa4LytmUiqo3t63z8VWj/Vk1fuaEEiBkEGI8BhBU/XsHYIERsiNb58Z9rso0teSRIUfnX5/SLxLntUqcRx6/zEYqJeI+ngo+C6cS4omr3nCTGF+e8x7Sm3tsicpsH3DFfYqVRvRrWeKEzJW87GYF1cgT/wzzdj6iV70du8= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1686499416; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=AvurtF/dISSi4a7QlYCrOBVBZSeEKbEVU2dJJafv7aE=; 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id m9-20020a056000008900b0030ae499da59sm9923022wrx.111.2023.06.11.09.00.36 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 11 Jun 2023 09:00:36 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1686499237; x=1689091237; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=AvurtF/dISSi4a7QlYCrOBVBZSeEKbEVU2dJJafv7aE=; b=AAYNsKbiH3xVj1kO2lpQ0CQX6nZPoLq3b1Sc4hMnsnokSAUnS+E4bd+Gcpmlb7o5jo ur78Hd+apLcoD/ojf5o5KqmR55+hYVQcRFVqH3TpeFc2YzVXP1hgSQK8Urlx7ZYd0yWO n6B2UmD3a4LtcSv/DlO2sg9zoBMqJLL3CmcRrSg+Vvb++S0JVAD6ZnL6pAsRBlNVILiD 5mS9PCxvJO3skZwVKLkRWeBJauRbyb+rJsZ3HdFvIrlrLUeEuLpuDDdk4+0/vLSg7tJR kn/pAnXLKh2MFeXpfA+V6W6yU78Q4McORhfOIMUsElUSV84AcJL6TmiIWVv2txuYAL9Y hjlg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1686499237; x=1689091237; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=AvurtF/dISSi4a7QlYCrOBVBZSeEKbEVU2dJJafv7aE=; b=OUd6PNBEZxoGvWwFXGOUSNCh42FlD6ggq19deQUwk7uA/IvpDmhpHBTVJXbHsl7OMj g0KEqmCvZU5vhSzOu4QLiDKLiPF7ctPDLwiwNdQZf0JLI7aNG77H8WAq88AhcfZUFGS5 gykDQkHgbd2cowBeyxFJ5GCAt3PMoiqhBNOH0uV9xTXlu9YEg6ZP2OiiA6/L3rtc60oX 5EuYSua+0Yh1qkmfxWxXhkYXgAPBdjFxhiTDPoHRW/PGar+Y+prgShCJ4763gvOMW2T3 HDzED9rx8uc8d1XHC5KfevYXKFNm4oHyBBswgvK1CIrBg6yTwy0yxV+A0wCpZF5du3Xx GNgA== X-Gm-Message-State: AC+VfDwcNq7kdkOg4e9p8nMTDTbdOLEv2t3DpsJd3nFd/xXcVHKK0LwJ vu+tspPZxdx2RA6omw1msTXQLg== X-Google-Smtp-Source: ACHHUZ4JsvFLroMpvdGJysH1sjrsmcUIdYxR6Cs80zNY2279dRgnzhk3Ry3pzzjm/i2Sp0CxLKqxZg== X-Received: by 2002:a05:6000:136c:b0:30f:c243:d7e7 with SMTP id q12-20020a056000136c00b0030fc243d7e7mr200062wrz.68.1686499237201; Sun, 11 Jun 2023 09:00:37 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH v2 06/23] target/arm: Convert barrier insns to decodetree Date: Sun, 11 Jun 2023 17:00:15 +0100 Message-Id: <20230611160032.274823-7-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230611160032.274823-1-peter.maydell@linaro.org> References: <20230611160032.274823-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::436; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x436.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1686499418345100001 Content-Type: text/plain; charset="utf-8" Convert the insns in the "Barriers" instruction class to decodetree: CLREX, DSB, DMB, ISB and SB. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Message-id: 20230602155223.2040685-4-peter.maydell@linaro.org Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- target/arm/tcg/a64.decode | 7 +++ target/arm/tcg/translate-a64.c | 92 ++++++++++++++-------------------- 2 files changed, 46 insertions(+), 53 deletions(-) diff --git a/target/arm/tcg/a64.decode b/target/arm/tcg/a64.decode index 1efd436e175..b3608d38dc9 100644 --- a/target/arm/tcg/a64.decode +++ b/target/arm/tcg/a64.decode @@ -181,3 +181,10 @@ ERETA 1101011 0100 11111 00001 m:1 11111 111= 11 &reta # ERETAA, ERETAB # that isn't specifically allocated to an instruction must NOP NOP 1101 0101 0000 0011 0010 ---- --- 11111 } + +# Barriers + +CLREX 1101 0101 0000 0011 0011 ---- 010 11111 +DSB_DMB 1101 0101 0000 0011 0011 domain:2 types:2 10- 11111 +ISB 1101 0101 0000 0011 0011 ---- 110 11111 +SB 1101 0101 0000 0011 0011 0000 111 11111 diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c index eb8addac1b3..088dfd8b1fd 100644 --- a/target/arm/tcg/translate-a64.c +++ b/target/arm/tcg/translate-a64.c @@ -1812,67 +1812,56 @@ static bool trans_AUTIBSP(DisasContext *s, arg_AUTI= BSP *a) return true; } =20 -static void gen_clrex(DisasContext *s, uint32_t insn) +static bool trans_CLREX(DisasContext *s, arg_CLREX *a) { tcg_gen_movi_i64(cpu_exclusive_addr, -1); + return true; } =20 -/* CLREX, DSB, DMB, ISB */ -static void handle_sync(DisasContext *s, uint32_t insn, - unsigned int op1, unsigned int op2, unsigned int c= rm) +static bool trans_DSB_DMB(DisasContext *s, arg_DSB_DMB *a) { + /* We handle DSB and DMB the same way */ TCGBar bar; =20 - if (op1 !=3D 3) { - unallocated_encoding(s); - return; + switch (a->types) { + case 1: /* MBReqTypes_Reads */ + bar =3D TCG_BAR_SC | TCG_MO_LD_LD | TCG_MO_LD_ST; + break; + case 2: /* MBReqTypes_Writes */ + bar =3D TCG_BAR_SC | TCG_MO_ST_ST; + break; + default: /* MBReqTypes_All */ + bar =3D TCG_BAR_SC | TCG_MO_ALL; + break; } + tcg_gen_mb(bar); + return true; +} =20 - switch (op2) { - case 2: /* CLREX */ - gen_clrex(s, insn); - return; - case 4: /* DSB */ - case 5: /* DMB */ - switch (crm & 3) { - case 1: /* MBReqTypes_Reads */ - bar =3D TCG_BAR_SC | TCG_MO_LD_LD | TCG_MO_LD_ST; - break; - case 2: /* MBReqTypes_Writes */ - bar =3D TCG_BAR_SC | TCG_MO_ST_ST; - break; - default: /* MBReqTypes_All */ - bar =3D TCG_BAR_SC | TCG_MO_ALL; - break; - } - tcg_gen_mb(bar); - return; - case 6: /* ISB */ - /* We need to break the TB after this insn to execute - * a self-modified code correctly and also to take - * any pending interrupts immediately. - */ - reset_btype(s); - gen_goto_tb(s, 0, 4); - return; +static bool trans_ISB(DisasContext *s, arg_ISB *a) +{ + /* + * We need to break the TB after this insn to execute + * self-modifying code correctly and also to take + * any pending interrupts immediately. + */ + reset_btype(s); + gen_goto_tb(s, 0, 4); + return true; +} =20 - case 7: /* SB */ - if (crm !=3D 0 || !dc_isar_feature(aa64_sb, s)) { - goto do_unallocated; - } - /* - * TODO: There is no speculation barrier opcode for TCG; - * MB and end the TB instead. - */ - tcg_gen_mb(TCG_MO_ALL | TCG_BAR_SC); - gen_goto_tb(s, 0, 4); - return; - - default: - do_unallocated: - unallocated_encoding(s); - return; +static bool trans_SB(DisasContext *s, arg_SB *a) +{ + if (!dc_isar_feature(aa64_sb, s)) { + return false; } + /* + * TODO: There is no speculation barrier opcode for TCG; + * MB and end the TB instead. + */ + tcg_gen_mb(TCG_MO_ALL | TCG_BAR_SC); + gen_goto_tb(s, 0, 4); + return true; } =20 static void gen_xaflag(void) @@ -2336,9 +2325,6 @@ static void disas_system(DisasContext *s, uint32_t in= sn) return; } switch (crn) { - case 3: /* CLREX, DSB, DMB, ISB */ - handle_sync(s, insn, op1, op2, crm); - break; case 4: /* MSR (immediate) */ handle_msr_i(s, insn, op1, op2, crm); break; --=20 2.34.1 From nobody Fri May 10 11:25:59 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1686499534; cv=none; d=zohomail.com; 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id m9-20020a056000008900b0030ae499da59sm9923022wrx.111.2023.06.11.09.00.37 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 11 Jun 2023 09:00:37 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1686499237; x=1689091237; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=EhniXz311o/2DcPgdcKAEpSrZXehm+PpvIlCx/ZyH40=; b=sSRGz/mcblbfikzBzOQ8d7UvGsbkzHXp7q6oeQ4EigRv2RlU+wf0/KO858BuyjkgXd iRmbrepMj0hzSkbKathdsCRD93S1hw/AT7YSV1TsyNDIzfEP7szVDDFDS1ATjsE6DuSm A3R+ClsSoUx2beMCbkGp3ykaJg6e9W+JDq2vk5awpcvxig4sYaPA4BsQ2LKSLoRcYNs8 u/uIeiOyjnNS+h6tqHIjmYKWOWuqKRysttnLdVv/JwFFctcwxBGz67E93E7/PPy5GPO9 Luw/0nJWRRKQpywl2dm9UJU0yjsjZrTcpwtyQsbiZFBXrCbCSUEZk1ke0nweIhPJcf72 qIbQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1686499237; x=1689091237; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=EhniXz311o/2DcPgdcKAEpSrZXehm+PpvIlCx/ZyH40=; b=PKKPtsq3exZU2VQCnc1rTd90QWp/+wpEVxrXjvuUWAWmDZPi57ju3i6VXR3zO+9reF vSEnBmgC4U4QqHRXL/gdb9pSsXU61qWZPihUCjeqJIa4sGGeIErRBVimfFiadougy6zm pEv7hQVeJbxAomR5DE8khOjlA4XFOZ7U1+FJ0yvBbU5q3I0D5UJVK1MEq8wvVEYg4grb j4f/NETeB3pkkZATv/E9eNJPW8+pQtA8cWYbhSIIAsdXrQSOA2uNBSprFpBcz1CvBicc g0/zMztgcSRY2QXgDukotI1hvxo20WnufeoZRl7msuFL/z+UU9FXciLck6L4NWZLpF+a IYfA== X-Gm-Message-State: AC+VfDz5Mr3QLtQRtqobwiZoAxoBVVODYbClWsV4DigK99CuIzDvSnGE C2OLa4THUHBbyeIMTU5onJU62Ig1sIGx64pn3Ko= X-Google-Smtp-Source: ACHHUZ6H0loE2rg1Wp/bDDFTABmwKGaQPGJ8BblhJepmPi+RaBfbOwacng87w+MQ+i74jkE8+4nung== X-Received: by 2002:a05:600c:365a:b0:3f7:38e1:5e53 with SMTP id y26-20020a05600c365a00b003f738e15e53mr4991909wmq.4.1686499237724; Sun, 11 Jun 2023 09:00:37 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH v2 07/23] target/arm: Convert CFINV, XAFLAG and AXFLAG to decodetree Date: Sun, 11 Jun 2023 17:00:16 +0100 Message-Id: <20230611160032.274823-8-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230611160032.274823-1-peter.maydell@linaro.org> References: <20230611160032.274823-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::331; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x331.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1686499535946100001 Content-Type: text/plain; charset="utf-8" Convert the CFINV, XAFLAG and AXFLAG insns to decodetree. The old decoder handles these in handle_msr_i(), but the architecture defines them as separate instructions from MSR (immediate). Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Message-id: 20230602155223.2040685-5-peter.maydell@linaro.org --- target/arm/tcg/a64.decode | 6 ++++ target/arm/tcg/translate-a64.c | 53 +++++++++++++++++----------------- 2 files changed, 32 insertions(+), 27 deletions(-) diff --git a/target/arm/tcg/a64.decode b/target/arm/tcg/a64.decode index b3608d38dc9..fd23fc3e0ff 100644 --- a/target/arm/tcg/a64.decode +++ b/target/arm/tcg/a64.decode @@ -188,3 +188,9 @@ CLREX 1101 0101 0000 0011 0011 ---- 010 11111 DSB_DMB 1101 0101 0000 0011 0011 domain:2 types:2 10- 11111 ISB 1101 0101 0000 0011 0011 ---- 110 11111 SB 1101 0101 0000 0011 0011 0000 111 11111 + +# PSTATE + +CFINV 1101 0101 0000 0 000 0100 0000 000 11111 +XAFLAG 1101 0101 0000 0 000 0100 0000 001 11111 +AXFLAG 1101 0101 0000 0 000 0100 0000 010 11111 diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c index 088dfd8b1fd..c1b02b96183 100644 --- a/target/arm/tcg/translate-a64.c +++ b/target/arm/tcg/translate-a64.c @@ -1864,9 +1864,24 @@ static bool trans_SB(DisasContext *s, arg_SB *a) return true; } =20 -static void gen_xaflag(void) +static bool trans_CFINV(DisasContext *s, arg_CFINV *a) { - TCGv_i32 z =3D tcg_temp_new_i32(); + if (!dc_isar_feature(aa64_condm_4, s)) { + return false; + } + tcg_gen_xori_i32(cpu_CF, cpu_CF, 1); + return true; +} + +static bool trans_XAFLAG(DisasContext *s, arg_XAFLAG *a) +{ + TCGv_i32 z; + + if (!dc_isar_feature(aa64_condm_5, s)) { + return false; + } + + z =3D tcg_temp_new_i32(); =20 tcg_gen_setcondi_i32(TCG_COND_EQ, z, cpu_ZF, 0); =20 @@ -1890,10 +1905,16 @@ static void gen_xaflag(void) =20 /* C | Z */ tcg_gen_or_i32(cpu_CF, cpu_CF, z); + + return true; } =20 -static void gen_axflag(void) +static bool trans_AXFLAG(DisasContext *s, arg_AXFLAG *a) { + if (!dc_isar_feature(aa64_condm_5, s)) { + return false; + } + tcg_gen_sari_i32(cpu_VF, cpu_VF, 31); /* V ? -1 : 0 */ tcg_gen_andc_i32(cpu_CF, cpu_CF, cpu_VF); /* C & !V */ =20 @@ -1902,6 +1923,8 @@ static void gen_axflag(void) =20 tcg_gen_movi_i32(cpu_NF, 0); tcg_gen_movi_i32(cpu_VF, 0); + + return true; } =20 /* MSR (immediate) - move immediate to processor state field */ @@ -1914,30 +1937,6 @@ static void handle_msr_i(DisasContext *s, uint32_t i= nsn, s->base.is_jmp =3D DISAS_TOO_MANY; =20 switch (op) { - case 0x00: /* CFINV */ - if (crm !=3D 0 || !dc_isar_feature(aa64_condm_4, s)) { - goto do_unallocated; - } - tcg_gen_xori_i32(cpu_CF, cpu_CF, 1); - s->base.is_jmp =3D DISAS_NEXT; - break; - - case 0x01: /* XAFlag */ - if (crm !=3D 0 || !dc_isar_feature(aa64_condm_5, s)) { - goto do_unallocated; - } - gen_xaflag(); - s->base.is_jmp =3D DISAS_NEXT; - break; - - case 0x02: /* AXFlag */ - if (crm !=3D 0 || !dc_isar_feature(aa64_condm_5, s)) { - goto do_unallocated; - } - gen_axflag(); - s->base.is_jmp =3D DISAS_NEXT; - break; - case 0x03: /* UAO */ if (!dc_isar_feature(aa64_uao, s) || s->current_el =3D=3D 0) { goto do_unallocated; --=20 2.34.1 From nobody Fri May 10 11:25:59 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1686499364; cv=none; d=zohomail.com; s=zohoarc; b=Fhv7xm6X+MSq0mZOg0xHTyCybuib4NhuawdE2XMRTGXNQFL3HMaIO8Xq6SXIJjdCKIgbG2IBbQZSHZsbF/mK6WPKjX0v0OjD1UhqulyTB6gaAiOmC35D9lmG6PwL4ERtJqHBHGyRycYp9qtocRv3xfsRBE9bovWXDpKqYp18ess= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1686499364; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=gOvf60YN74xnTNfixpVWMsKoOKc9WSdyaA7UMG2RTxA=; b=E7+fO0joiCoBImn11AzK+VAKJqpQrdC7u9IgQHQrghf/RSafPSGRR5owZ2OeW+QbRn923pXtBrtjfVQp3d2GVdqntuLYmiAx65Ngjo8OZM/cSWjR8XmPU3oQF9cVHrcl/WoRZATqp3ZID+9UkCBhQW0LhyPbs7Ne781kP6b0Xy0= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1686499364838761.4870005691909; Sun, 11 Jun 2023 09:02:44 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1q8NVf-0006X4-CE; Sun, 11 Jun 2023 12:01:43 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1q8NUj-0005r1-AF for qemu-devel@nongnu.org; Sun, 11 Jun 2023 12:00:50 -0400 Received: from mail-wm1-x335.google.com ([2a00:1450:4864:20::335]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1q8NUd-0000SP-NU for qemu-devel@nongnu.org; Sun, 11 Jun 2023 12:00:44 -0400 Received: by mail-wm1-x335.google.com with SMTP id 5b1f17b1804b1-3f78a32266bso35238115e9.3 for ; Sun, 11 Jun 2023 09:00:39 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id m9-20020a056000008900b0030ae499da59sm9923022wrx.111.2023.06.11.09.00.37 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 11 Jun 2023 09:00:37 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1686499238; x=1689091238; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=gOvf60YN74xnTNfixpVWMsKoOKc9WSdyaA7UMG2RTxA=; b=R2B6wF7vBiIYg4qjkFt1rMFvShskcI9/7KNfRLJQTKVjbuNYFxSNcOGXAWkYRbjd2Q qsGO3dRLpTMSQvI6GJlyqbCzwE7ijxTd7d5Pl/yDqg+8K7e5RaeHRDNxdcjItms9max7 ANaatVvX3SoMV+/rfmiN13ITUhZ37zOVKBwhIJg9wpylpDGCUGKT+nzoOEtjYyokEGZg FJsSd+DiKiBVuTkdgMHg2AJNDZZ6q/AW8Ff5z3P5xcKEonECWyVFKisuwPrfrbYaBitL ITYzR587408XFIYwVP63RLA/7QN21gImcJ/xQrFbpjTZMXA1QFTcIEJy3F88o+ZpnNjU daKA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1686499238; x=1689091238; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=gOvf60YN74xnTNfixpVWMsKoOKc9WSdyaA7UMG2RTxA=; b=BL0+9ETc9dv6jnPUpYm+61hAVQxKa4j5nl2SOYn6uEb/89YD7HeBnnLKCmV69V5+xQ dq0fExegCVcZeVXqWvWkVWYK6Sx82YTbVVk/7Nq1ybC2aegSKRBOxlFhCpyoEs/tvCeW TEK7e0oe1CWHHHi4aThGBPEX27D1Apb5Qo0K7bPM2gM3hJJ4Ed0FZT/hVmkYJ5LHnVqn KvuSZwhB4iNbjGsUg1IspzhE9YZD1UKcrT6BVoFVeO7hD2GBuPN57UoE1EZCby3Qzntl ZNuE7Ss0nvocSfq+aKKOGySt0kg/8mrxUeKB4jOXtttUHCtH4PAHm6odztAgrvXGqRhb B2Kw== X-Gm-Message-State: AC+VfDy1Ppudsqzu/wJBVM7UQ79AP7w/+UpskbV0Pd77mwjmq40OIQ3f rdtkw+MyvHFUuabIcfLLsta9fA== X-Google-Smtp-Source: ACHHUZ7PCAuNLav728Mzg4vS3ouCCe8o65cWFsNbHjXOOKISPx261cFkpQmiyzBpgtSGHAf3nJezlw== X-Received: by 2002:adf:f842:0:b0:30d:1df7:f145 with SMTP id d2-20020adff842000000b0030d1df7f145mr3108414wrq.64.1686499238269; Sun, 11 Jun 2023 09:00:38 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH v2 08/23] target/arm: Convert MSR (immediate) to decodetree Date: Sun, 11 Jun 2023 17:00:17 +0100 Message-Id: <20230611160032.274823-9-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230611160032.274823-1-peter.maydell@linaro.org> References: <20230611160032.274823-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::335; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x335.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1686499366140100013 Content-Type: text/plain; charset="utf-8" Convert the MSR (immediate) insn to decodetree. Our implementation has basically no commonality between the different destinations, so we decode the destination register in a64.decode. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Message-id: 20230602155223.2040685-6-peter.maydell@linaro.org --- target/arm/tcg/a64.decode | 13 ++ target/arm/tcg/translate-a64.c | 251 ++++++++++++++++----------------- 2 files changed, 136 insertions(+), 128 deletions(-) diff --git a/target/arm/tcg/a64.decode b/target/arm/tcg/a64.decode index fd23fc3e0ff..4f94a08907b 100644 --- a/target/arm/tcg/a64.decode +++ b/target/arm/tcg/a64.decode @@ -194,3 +194,16 @@ SB 1101 0101 0000 0011 0011 0000 111 11111 CFINV 1101 0101 0000 0 000 0100 0000 000 11111 XAFLAG 1101 0101 0000 0 000 0100 0000 001 11111 AXFLAG 1101 0101 0000 0 000 0100 0000 010 11111 + +# These are architecturally all "MSR (immediate)"; we decode the destinati= on +# register too because there is no commonality in our implementation. +@msr_i .... .... .... . ... .... imm:4 ... ..... +MSR_i_UAO 1101 0101 0000 0 000 0100 .... 011 11111 @msr_i +MSR_i_PAN 1101 0101 0000 0 000 0100 .... 100 11111 @msr_i +MSR_i_SPSEL 1101 0101 0000 0 000 0100 .... 101 11111 @msr_i +MSR_i_SBSS 1101 0101 0000 0 011 0100 .... 001 11111 @msr_i +MSR_i_DIT 1101 0101 0000 0 011 0100 .... 010 11111 @msr_i +MSR_i_TCO 1101 0101 0000 0 011 0100 .... 100 11111 @msr_i +MSR_i_DAIFSET 1101 0101 0000 0 011 0100 .... 110 11111 @msr_i +MSR_i_DAIFCLEAR 1101 0101 0000 0 011 0100 .... 111 11111 @msr_i +MSR_i_SVCR 1101 0101 0000 0 011 0100 0 mask:2 imm:1 011 11111 diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c index c1b02b96183..8c57b48d81f 100644 --- a/target/arm/tcg/translate-a64.c +++ b/target/arm/tcg/translate-a64.c @@ -1927,124 +1927,130 @@ static bool trans_AXFLAG(DisasContext *s, arg_AXF= LAG *a) return true; } =20 -/* MSR (immediate) - move immediate to processor state field */ -static void handle_msr_i(DisasContext *s, uint32_t insn, - unsigned int op1, unsigned int op2, unsigned int = crm) +static bool trans_MSR_i_UAO(DisasContext *s, arg_i *a) { - int op =3D op1 << 3 | op2; - - /* End the TB by default, chaining is ok. */ - s->base.is_jmp =3D DISAS_TOO_MANY; - - switch (op) { - case 0x03: /* UAO */ - if (!dc_isar_feature(aa64_uao, s) || s->current_el =3D=3D 0) { - goto do_unallocated; - } - if (crm & 1) { - set_pstate_bits(PSTATE_UAO); - } else { - clear_pstate_bits(PSTATE_UAO); - } - gen_rebuild_hflags(s); - break; - - case 0x04: /* PAN */ - if (!dc_isar_feature(aa64_pan, s) || s->current_el =3D=3D 0) { - goto do_unallocated; - } - if (crm & 1) { - set_pstate_bits(PSTATE_PAN); - } else { - clear_pstate_bits(PSTATE_PAN); - } - gen_rebuild_hflags(s); - break; - - case 0x05: /* SPSel */ - if (s->current_el =3D=3D 0) { - goto do_unallocated; - } - gen_helper_msr_i_spsel(cpu_env, tcg_constant_i32(crm & PSTATE_SP)); - break; - - case 0x19: /* SSBS */ - if (!dc_isar_feature(aa64_ssbs, s)) { - goto do_unallocated; - } - if (crm & 1) { - set_pstate_bits(PSTATE_SSBS); - } else { - clear_pstate_bits(PSTATE_SSBS); - } - /* Don't need to rebuild hflags since SSBS is a nop */ - break; - - case 0x1a: /* DIT */ - if (!dc_isar_feature(aa64_dit, s)) { - goto do_unallocated; - } - if (crm & 1) { - set_pstate_bits(PSTATE_DIT); - } else { - clear_pstate_bits(PSTATE_DIT); - } - /* There's no need to rebuild hflags because DIT is a nop */ - break; - - case 0x1e: /* DAIFSet */ - gen_helper_msr_i_daifset(cpu_env, tcg_constant_i32(crm)); - break; - - case 0x1f: /* DAIFClear */ - gen_helper_msr_i_daifclear(cpu_env, tcg_constant_i32(crm)); - /* For DAIFClear, exit the cpu loop to re-evaluate pending IRQs. = */ - s->base.is_jmp =3D DISAS_UPDATE_EXIT; - break; - - case 0x1c: /* TCO */ - if (dc_isar_feature(aa64_mte, s)) { - /* Full MTE is enabled -- set the TCO bit as directed. */ - if (crm & 1) { - set_pstate_bits(PSTATE_TCO); - } else { - clear_pstate_bits(PSTATE_TCO); - } - gen_rebuild_hflags(s); - /* Many factors, including TCO, go into MTE_ACTIVE. */ - s->base.is_jmp =3D DISAS_UPDATE_NOCHAIN; - } else if (dc_isar_feature(aa64_mte_insn_reg, s)) { - /* Only "instructions accessible at EL0" -- PSTATE.TCO is WI. = */ - s->base.is_jmp =3D DISAS_NEXT; - } else { - goto do_unallocated; - } - break; - - case 0x1b: /* SVCR* */ - if (!dc_isar_feature(aa64_sme, s) || crm < 2 || crm > 7) { - goto do_unallocated; - } - if (sme_access_check(s)) { - int old =3D s->pstate_sm | (s->pstate_za << 1); - int new =3D (crm & 1) * 3; - int msk =3D (crm >> 1) & 3; - - if ((old ^ new) & msk) { - /* At least one bit changes. */ - gen_helper_set_svcr(cpu_env, tcg_constant_i32(new), - tcg_constant_i32(msk)); - } else { - s->base.is_jmp =3D DISAS_NEXT; - } - } - break; - - default: - do_unallocated: - unallocated_encoding(s); - return; + if (!dc_isar_feature(aa64_uao, s) || s->current_el =3D=3D 0) { + return false; } + if (a->imm & 1) { + set_pstate_bits(PSTATE_UAO); + } else { + clear_pstate_bits(PSTATE_UAO); + } + gen_rebuild_hflags(s); + s->base.is_jmp =3D DISAS_TOO_MANY; + return true; +} + +static bool trans_MSR_i_PAN(DisasContext *s, arg_i *a) +{ + if (!dc_isar_feature(aa64_pan, s) || s->current_el =3D=3D 0) { + return false; + } + if (a->imm & 1) { + set_pstate_bits(PSTATE_PAN); + } else { + clear_pstate_bits(PSTATE_PAN); + } + gen_rebuild_hflags(s); + s->base.is_jmp =3D DISAS_TOO_MANY; + return true; +} + +static bool trans_MSR_i_SPSEL(DisasContext *s, arg_i *a) +{ + if (s->current_el =3D=3D 0) { + return false; + } + gen_helper_msr_i_spsel(cpu_env, tcg_constant_i32(a->imm & PSTATE_SP)); + s->base.is_jmp =3D DISAS_TOO_MANY; + return true; +} + +static bool trans_MSR_i_SBSS(DisasContext *s, arg_i *a) +{ + if (!dc_isar_feature(aa64_ssbs, s)) { + return false; + } + if (a->imm & 1) { + set_pstate_bits(PSTATE_SSBS); + } else { + clear_pstate_bits(PSTATE_SSBS); + } + /* Don't need to rebuild hflags since SSBS is a nop */ + s->base.is_jmp =3D DISAS_TOO_MANY; + return true; +} + +static bool trans_MSR_i_DIT(DisasContext *s, arg_i *a) +{ + if (!dc_isar_feature(aa64_dit, s)) { + return false; + } + if (a->imm & 1) { + set_pstate_bits(PSTATE_DIT); + } else { + clear_pstate_bits(PSTATE_DIT); + } + /* There's no need to rebuild hflags because DIT is a nop */ + s->base.is_jmp =3D DISAS_TOO_MANY; + return true; +} + +static bool trans_MSR_i_TCO(DisasContext *s, arg_i *a) +{ + if (dc_isar_feature(aa64_mte, s)) { + /* Full MTE is enabled -- set the TCO bit as directed. */ + if (a->imm & 1) { + set_pstate_bits(PSTATE_TCO); + } else { + clear_pstate_bits(PSTATE_TCO); + } + gen_rebuild_hflags(s); + /* Many factors, including TCO, go into MTE_ACTIVE. */ + s->base.is_jmp =3D DISAS_UPDATE_NOCHAIN; + return true; + } else if (dc_isar_feature(aa64_mte_insn_reg, s)) { + /* Only "instructions accessible at EL0" -- PSTATE.TCO is WI. */ + return true; + } else { + /* Insn not present */ + return false; + } +} + +static bool trans_MSR_i_DAIFSET(DisasContext *s, arg_i *a) +{ + gen_helper_msr_i_daifset(cpu_env, tcg_constant_i32(a->imm)); + s->base.is_jmp =3D DISAS_TOO_MANY; + return true; +} + +static bool trans_MSR_i_DAIFCLEAR(DisasContext *s, arg_i *a) +{ + gen_helper_msr_i_daifclear(cpu_env, tcg_constant_i32(a->imm)); + /* Exit the cpu loop to re-evaluate pending IRQs. */ + s->base.is_jmp =3D DISAS_UPDATE_EXIT; + return true; +} + +static bool trans_MSR_i_SVCR(DisasContext *s, arg_MSR_i_SVCR *a) +{ + if (!dc_isar_feature(aa64_sme, s) || a->mask =3D=3D 0) { + return false; + } + if (sme_access_check(s)) { + int old =3D s->pstate_sm | (s->pstate_za << 1); + int new =3D a->imm * 3; + + if ((old ^ new) & a->mask) { + /* At least one bit changes. */ + gen_helper_set_svcr(cpu_env, tcg_constant_i32(new), + tcg_constant_i32(a->mask)); + s->base.is_jmp =3D DISAS_TOO_MANY; + } + } + return true; } =20 static void gen_get_nzcv(TCGv_i64 tcg_rt) @@ -2319,18 +2325,7 @@ static void disas_system(DisasContext *s, uint32_t i= nsn) rt =3D extract32(insn, 0, 5); =20 if (op0 =3D=3D 0) { - if (l || rt !=3D 31) { - unallocated_encoding(s); - return; - } - switch (crn) { - case 4: /* MSR (immediate) */ - handle_msr_i(s, insn, op1, op2, crm); - break; - default: - unallocated_encoding(s); - break; - } + unallocated_encoding(s); return; } handle_sys(s, insn, l, op0, op1, op2, crn, crm, rt); --=20 2.34.1 From nobody Fri May 10 11:25:59 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1686499391; cv=none; d=zohomail.com; s=zohoarc; b=FxE4c+/0PNIfGt8wN1YTINPgPkE3MVq6G0arh/GKo5CO0rebd/aaDTDFKa8dswzhngftakuMBsFigXDtpZZvjLjMQFtT/vtb3u3WCH6i/pNKThMEoGWltp7KQVY/kI81WTcSKWUC3EqDCW0qy/asHeMSQbI7xWm9dteSx4TtPJo= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1686499391; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id m9-20020a056000008900b0030ae499da59sm9923022wrx.111.2023.06.11.09.00.38 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 11 Jun 2023 09:00:38 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1686499239; x=1689091239; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=+XbYmxSJE64dVnwOczE4gA9sgyTn0e033FPdiaF2Mxo=; b=fsrDInrJvDMO9Hl0DJ9Y0z4FNacHrknt/Hk3qrga0z4T1G6Zt5wFzvp+qzvFph7MBN lmlhWN0NWP5416MVIT3MNkDrc+QYlkB8kJAWcWPDUUFdMGgEsIniPQNQEA5pHK40cOb+ H2cp0ygzuvqsg2y+ZRmA1KPKJFELSZv2gPGldKcsiQ76I+ATfeCNHe8pzC8TNLctTTA0 /30GguTETpbQ8RvRZKQVz2rts3ffzQ/5FWWtH4qKURkGbcrptIQLfIQWQvlbKV5F2Qup 0oBdxN2iVXCoPmNs8m+BX2z82rM4xuRWGXsL5S/lMABE/WvGtxdBXZPR/ck1b7hfgG8w qsSw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1686499239; x=1689091239; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=+XbYmxSJE64dVnwOczE4gA9sgyTn0e033FPdiaF2Mxo=; b=FDvDPKf33a9d6mKWuZrr6HlV8lrWxhkxrmP/scyLuVma2Ov40l/ZVTkaxAhZzChBY7 Bu2ea4OC2AtSfH00HtLqruS+W5eZgxIkntxeWYCnVukO+7Ql3zMDwD8HOA4I/+0LOudN C+ABMBsq9gC+ZsbZ/iP3r/zv0MC6gKRQ1AgHev3hcPBtudz7xQTOvs5Pc5kWAIOtas06 VtJfdHrtHrW0Zn8SUwZdO2FsU8jJUyxpG5a0SPuOxrTiX9+KLVdJ2NYwre3OVOt4bUbS LtrOp6Tbdwoz9Jkn1BfmekRFSFe1bsSc3hAMLilIU+nFXGeHkXHajQBgW5PPbOyEdD1X cp9w== X-Gm-Message-State: AC+VfDwJtprB2lAHfLNXg/gfbQ2GLfHjmWswv7Mq2nvH7cAuNw70eX0P vTFCcsziVBzwF+dHXgzvE5r94lnWG6LmGO6VTdg= X-Google-Smtp-Source: ACHHUZ44Shf8UF1cup7uF4kGiQmGOxhpndAXC0TuIgeV9niE6sFqXBrG3f4hle/3rQQN4grn5cLGTw== X-Received: by 2002:adf:de8c:0:b0:309:5119:7259 with SMTP id w12-20020adfde8c000000b0030951197259mr3402478wrl.20.1686499238818; Sun, 11 Jun 2023 09:00:38 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH v2 09/23] target/arm: Convert MSR (reg), MRS, SYS, SYSL to decodetree Date: Sun, 11 Jun 2023 17:00:18 +0100 Message-Id: <20230611160032.274823-10-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230611160032.274823-1-peter.maydell@linaro.org> References: <20230611160032.274823-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::436; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x436.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1686499392376100001 Content-Type: text/plain; charset="utf-8" Convert MSR (reg), MRS, SYS, SYSL to decodetree. For QEMU these are all essentially the same instruction (system register access). Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Message-id: 20230602155223.2040685-7-peter.maydell@linaro.org Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- target/arm/tcg/a64.decode | 8 ++++++++ target/arm/tcg/translate-a64.c | 32 +++++--------------------------- 2 files changed, 13 insertions(+), 27 deletions(-) diff --git a/target/arm/tcg/a64.decode b/target/arm/tcg/a64.decode index 4f94a08907b..c49215cca8d 100644 --- a/target/arm/tcg/a64.decode +++ b/target/arm/tcg/a64.decode @@ -207,3 +207,11 @@ MSR_i_TCO 1101 0101 0000 0 011 0100 .... 100 111= 11 @msr_i MSR_i_DAIFSET 1101 0101 0000 0 011 0100 .... 110 11111 @msr_i MSR_i_DAIFCLEAR 1101 0101 0000 0 011 0100 .... 111 11111 @msr_i MSR_i_SVCR 1101 0101 0000 0 011 0100 0 mask:2 imm:1 011 11111 + +# MRS, MSR (register), SYS, SYSL. These are all essentially the +# same instruction as far as QEMU is concerned. +# NB: op0 is bits [20:19], but op0=3D0b00 is other insns, so we have +# to hand-decode it. +SYS 1101 0101 00 l:1 01 op1:3 crn:4 crm:4 op2:3 rt:5 op0=3D1 +SYS 1101 0101 00 l:1 10 op1:3 crn:4 crm:4 op2:3 rt:5 op0=3D2 +SYS 1101 0101 00 l:1 11 op1:3 crn:4 crm:4 op2:3 rt:5 op0=3D3 diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c index 8c57b48d81f..74a389da4a7 100644 --- a/target/arm/tcg/translate-a64.c +++ b/target/arm/tcg/translate-a64.c @@ -2122,7 +2122,7 @@ static void gen_sysreg_undef(DisasContext *s, bool is= read, * These are all essentially the same insn in 'read' and 'write' * versions, with varying op0 fields. */ -static void handle_sys(DisasContext *s, uint32_t insn, bool isread, +static void handle_sys(DisasContext *s, bool isread, unsigned int op0, unsigned int op1, unsigned int op= 2, unsigned int crn, unsigned int crm, unsigned int rt) { @@ -2307,28 +2307,10 @@ static void handle_sys(DisasContext *s, uint32_t in= sn, bool isread, } } =20 -/* System - * 31 22 21 20 19 18 16 15 12 11 8 7 5 4 0 - * +---------------------+---+-----+-----+-------+-------+-----+------+ - * | 1 1 0 1 0 1 0 1 0 0 | L | op0 | op1 | CRn | CRm | op2 | Rt | - * +---------------------+---+-----+-----+-------+-------+-----+------+ - */ -static void disas_system(DisasContext *s, uint32_t insn) +static bool trans_SYS(DisasContext *s, arg_SYS *a) { - unsigned int l, op0, op1, crn, crm, op2, rt; - l =3D extract32(insn, 21, 1); - op0 =3D extract32(insn, 19, 2); - op1 =3D extract32(insn, 16, 3); - crn =3D extract32(insn, 12, 4); - crm =3D extract32(insn, 8, 4); - op2 =3D extract32(insn, 5, 3); - rt =3D extract32(insn, 0, 5); - - if (op0 =3D=3D 0) { - unallocated_encoding(s); - return; - } - handle_sys(s, insn, l, op0, op1, op2, crn, crm, rt); + handle_sys(s, a->l, a->op0, a->op1, a->op2, a->crn, a->crm, a->rt); + return true; } =20 /* Exception generation @@ -2435,11 +2417,7 @@ static void disas_b_exc_sys(DisasContext *s, uint32_= t insn) switch (extract32(insn, 25, 7)) { case 0x6a: /* Exception generation / System */ if (insn & (1 << 24)) { - if (extract32(insn, 22, 2) =3D=3D 0) { - disas_system(s, insn); - } else { - unallocated_encoding(s); - } + unallocated_encoding(s); } else { disas_exc(s, insn); } --=20 2.34.1 From nobody Fri May 10 11:25:59 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1686499510; cv=none; d=zohomail.com; s=zohoarc; b=ZOMU7No68mkgfCwNZ1OR+eFf2LYxhDZL3s/Bw9Hlt80g+xA5Md5RgDAFgUxGle5FvtACEusNHqTgngPbR494JaqxvLof46BusTzp7sY2hphIJCAZGUlc9l7Oj6IWyb9c6zWXDA3AuaAr21Ut3UXXuvIyySTPIJ8ao+G4uV0+0Eg= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1686499510; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=Hv0rchOEEfJPVEoDeEXmaUe1CECfSOxYqHxG0bO7LPk=; b=gXg8bJuMLTkNyvZMx+OstRtwKj+7tV0FHQfQGo0CpFJlnAmIYmSVQQU9KNro6iZIm6BZUms8PJVRzXm3/JM3WTwrfPaB9lv0ekRkEg0gSlm26EkTB9phekiunbcFR6I0O5XBvmXRd6xOEWwXVDqI6R/+glqVrulAvLyQ7U7WPoM= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1686499510089565.0819881818298; Sun, 11 Jun 2023 09:05:10 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1q8NVh-0006b1-IS; Sun, 11 Jun 2023 12:01:45 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1q8NUl-0005rT-9t for qemu-devel@nongnu.org; Sun, 11 Jun 2023 12:00:50 -0400 Received: from mail-wr1-x431.google.com ([2a00:1450:4864:20::431]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1q8NUg-0000Sq-17 for qemu-devel@nongnu.org; Sun, 11 Jun 2023 12:00:46 -0400 Received: by mail-wr1-x431.google.com with SMTP id ffacd0b85a97d-30e3caa6aa7so3446314f8f.1 for ; Sun, 11 Jun 2023 09:00:40 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id m9-20020a056000008900b0030ae499da59sm9923022wrx.111.2023.06.11.09.00.38 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 11 Jun 2023 09:00:39 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1686499239; x=1689091239; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=Hv0rchOEEfJPVEoDeEXmaUe1CECfSOxYqHxG0bO7LPk=; b=S+ijqPSiTZH+6QFKDNA8RgF8SqtkXJcXHWed9aHAqAWaktXrPTq4+cpVH7MbzZekIB 3/dRxe8dHM+NKHkLjXJlduSx9b7fIg/Ae0VtRrzWkl6MYMfLTXo6fN5F0ZPxmq7seZ5a IZysjIDbPLim8XEjwkwnWK1ud28uayY32jtk3nSktlf5N3N97RyqtDyoPof/bJg4zeM2 SKhRldNbCPUDiZKlcdijPrkWKCTDaiMxiD9jl+mBY26nmcFAuT13//mYWg4Wd2R3Iel1 ms6iN+1K5j8d9y/ie66ALvG+sINUW0cZEy1TzYx+66HJ+Td32pyRkScF0yU7ePiilEHO b9ww== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1686499239; x=1689091239; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=Hv0rchOEEfJPVEoDeEXmaUe1CECfSOxYqHxG0bO7LPk=; b=Qz+h3TKlffeo8uPKLcAsWvj7bAsP5T2XROzrsJbxdlUxL3S5hvdoBnf1qKdfAJkjQ7 Zera64/RwizalTSZv9bm56PlnHpDiY5x0s5tdJKBkkP6fes9c8R0OmiNfAAu/wu2yRjl fuSqXls4idNknom0FzDe81ppWhETpsj0XBXMTreuV2eLQ0irMbuQ3iX20NmaUd19FXKN vkIYcWmxAhSYTCvFyQQhLqy0aij1hvbBSTEZrIiE9XRzn/KD14m3GqM8I4KUWhCiQhDp s14ioyX0KzVjGGZ8mKwiGN2o/rxRZi6nIbn3UIAwbU4v8L84bf1loMz2lAx7kKbIl3dB Fb6A== X-Gm-Message-State: AC+VfDyQjnRnl1S6tmJQN5wX/Z4d/VXYA/ic3ZZDeguzYZggokEfyM3X 5m9hPKwcEFoSjRGLv3TR5LLpwQ== X-Google-Smtp-Source: ACHHUZ6FSkhxML4Kjce/5jdPAqiXZdwQbOwj8praYb0knYgOhtNRVOiJHK6ia5MWhFR6wIJrCDD/og== X-Received: by 2002:a5d:6a03:0:b0:309:44ed:ccff with SMTP id m3-20020a5d6a03000000b0030944edccffmr3110523wru.1.1686499239342; Sun, 11 Jun 2023 09:00:39 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH v2 10/23] target/arm: Convert exception generation instructions to decodetree Date: Sun, 11 Jun 2023 17:00:19 +0100 Message-Id: <20230611160032.274823-11-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230611160032.274823-1-peter.maydell@linaro.org> References: <20230611160032.274823-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::431; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x431.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1686499511996100003 Content-Type: text/plain; charset="utf-8" Convert the exception generation instructions SVC, HVC, SMC, BRK and HLT to decodetree. The old decoder decoded the halting-debug insnns DCPS1, DCPS2 and DCPS3 just in order to then make them UNDEF; as with DRPS, we don't bother to decode them, but document the patterns in a64.decode. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Message-id: 20230602155223.2040685-8-peter.maydell@linaro.org --- target/arm/tcg/a64.decode | 15 +++ target/arm/tcg/translate-a64.c | 173 ++++++++++++--------------------- 2 files changed, 79 insertions(+), 109 deletions(-) diff --git a/target/arm/tcg/a64.decode b/target/arm/tcg/a64.decode index c49215cca8d..eeaca08ae83 100644 --- a/target/arm/tcg/a64.decode +++ b/target/arm/tcg/a64.decode @@ -215,3 +215,18 @@ MSR_i_SVCR 1101 0101 0000 0 011 0100 0 mask:2 imm= :1 011 11111 SYS 1101 0101 00 l:1 01 op1:3 crn:4 crm:4 op2:3 rt:5 op0=3D1 SYS 1101 0101 00 l:1 10 op1:3 crn:4 crm:4 op2:3 rt:5 op0=3D2 SYS 1101 0101 00 l:1 11 op1:3 crn:4 crm:4 op2:3 rt:5 op0=3D3 + +# Exception generation + +@i16 .... .... ... imm:16 ... .. &i +SVC 1101 0100 000 ................ 000 01 @i16 +HVC 1101 0100 000 ................ 000 10 @i16 +SMC 1101 0100 000 ................ 000 11 @i16 +BRK 1101 0100 001 ................ 000 00 @i16 +HLT 1101 0100 010 ................ 000 00 @i16 +# These insns always UNDEF unless in halting debug state, which +# we don't implement. So we don't need to decode them. The patterns +# are listed here as documentation. +# DCPS1 1101 0100 101 ................ 000 01 @i16 +# DCPS2 1101 0100 101 ................ 000 10 @i16 +# DCPS3 1101 0100 101 ................ 000 11 @i16 diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c index 74a389da4a7..a2a71b4062f 100644 --- a/target/arm/tcg/translate-a64.c +++ b/target/arm/tcg/translate-a64.c @@ -2313,119 +2313,77 @@ static bool trans_SYS(DisasContext *s, arg_SYS *a) return true; } =20 -/* Exception generation - * - * 31 24 23 21 20 5 4 2 1 0 - * +-----------------+-----+------------------------+-----+----+ - * | 1 1 0 1 0 1 0 0 | opc | imm16 | op2 | LL | - * +-----------------------+------------------------+----------+ - */ -static void disas_exc(DisasContext *s, uint32_t insn) +static bool trans_SVC(DisasContext *s, arg_i *a) { - int opc =3D extract32(insn, 21, 3); - int op2_ll =3D extract32(insn, 0, 5); - int imm16 =3D extract32(insn, 5, 16); - uint32_t syndrome; - - switch (opc) { - case 0: - /* For SVC, HVC and SMC we advance the single-step state - * machine before taking the exception. This is architecturally - * mandated, to ensure that single-stepping a system call - * instruction works properly. - */ - switch (op2_ll) { - case 1: /* SVC= */ - syndrome =3D syn_aa64_svc(imm16); - if (s->fgt_svc) { - gen_exception_insn_el(s, 0, EXCP_UDEF, syndrome, 2); - break; - } - gen_ss_advance(s); - gen_exception_insn(s, 4, EXCP_SWI, syndrome); - break; - case 2: /* HVC= */ - if (s->current_el =3D=3D 0) { - unallocated_encoding(s); - break; - } - /* The pre HVC helper handles cases when HVC gets trapped - * as an undefined insn by runtime configuration. - */ - gen_a64_update_pc(s, 0); - gen_helper_pre_hvc(cpu_env); - gen_ss_advance(s); - gen_exception_insn_el(s, 4, EXCP_HVC, syn_aa64_hvc(imm16), 2); - break; - case 3: /* SMC= */ - if (s->current_el =3D=3D 0) { - unallocated_encoding(s); - break; - } - gen_a64_update_pc(s, 0); - gen_helper_pre_smc(cpu_env, tcg_constant_i32(syn_aa64_smc(imm1= 6))); - gen_ss_advance(s); - gen_exception_insn_el(s, 4, EXCP_SMC, syn_aa64_smc(imm16), 3); - break; - default: - unallocated_encoding(s); - break; - } - break; - case 1: - if (op2_ll !=3D 0) { - unallocated_encoding(s); - break; - } - /* BRK */ - gen_exception_bkpt_insn(s, syn_aa64_bkpt(imm16)); - break; - case 2: - if (op2_ll !=3D 0) { - unallocated_encoding(s); - break; - } - /* HLT. This has two purposes. - * Architecturally, it is an external halting debug instruction. - * Since QEMU doesn't implement external debug, we treat this as - * it is required for halting debug disabled: it will UNDEF. - * Secondly, "HLT 0xf000" is the A64 semihosting syscall instructi= on. - */ - if (semihosting_enabled(s->current_el =3D=3D 0) && imm16 =3D=3D 0x= f000) { - gen_exception_internal_insn(s, EXCP_SEMIHOST); - } else { - unallocated_encoding(s); - } - break; - case 5: - if (op2_ll < 1 || op2_ll > 3) { - unallocated_encoding(s); - break; - } - /* DCPS1, DCPS2, DCPS3 */ - unallocated_encoding(s); - break; - default: - unallocated_encoding(s); - break; + /* + * For SVC, HVC and SMC we advance the single-step state + * machine before taking the exception. This is architecturally + * mandated, to ensure that single-stepping a system call + * instruction works properly. + */ + uint32_t syndrome =3D syn_aa64_svc(a->imm); + if (s->fgt_svc) { + gen_exception_insn_el(s, 0, EXCP_UDEF, syndrome, 2); + return true; } + gen_ss_advance(s); + gen_exception_insn(s, 4, EXCP_SWI, syndrome); + return true; } =20 -/* Branches, exception generating and system instructions */ -static void disas_b_exc_sys(DisasContext *s, uint32_t insn) +static bool trans_HVC(DisasContext *s, arg_i *a) { - switch (extract32(insn, 25, 7)) { - case 0x6a: /* Exception generation / System */ - if (insn & (1 << 24)) { - unallocated_encoding(s); - } else { - disas_exc(s, insn); - } - break; - default: + if (s->current_el =3D=3D 0) { unallocated_encoding(s); - break; + return true; } + /* + * The pre HVC helper handles cases when HVC gets trapped + * as an undefined insn by runtime configuration. + */ + gen_a64_update_pc(s, 0); + gen_helper_pre_hvc(cpu_env); + /* Architecture requires ss advance before we do the actual work */ + gen_ss_advance(s); + gen_exception_insn_el(s, 4, EXCP_HVC, syn_aa64_hvc(a->imm), 2); + return true; +} + +static bool trans_SMC(DisasContext *s, arg_i *a) +{ + if (s->current_el =3D=3D 0) { + unallocated_encoding(s); + return true; + } + gen_a64_update_pc(s, 0); + gen_helper_pre_smc(cpu_env, tcg_constant_i32(syn_aa64_smc(a->imm))); + /* Architecture requires ss advance before we do the actual work */ + gen_ss_advance(s); + gen_exception_insn_el(s, 4, EXCP_SMC, syn_aa64_smc(a->imm), 3); + return true; +} + +static bool trans_BRK(DisasContext *s, arg_i *a) +{ + gen_exception_bkpt_insn(s, syn_aa64_bkpt(a->imm)); + return true; +} + +static bool trans_HLT(DisasContext *s, arg_i *a) +{ + /* + * HLT. This has two purposes. + * Architecturally, it is an external halting debug instruction. + * Since QEMU doesn't implement external debug, we treat this as + * it is required for halting debug disabled: it will UNDEF. + * Secondly, "HLT 0xf000" is the A64 semihosting syscall instruction. + */ + if (semihosting_enabled(s->current_el =3D=3D 0) && a->imm =3D=3D 0xf00= 0) { + gen_exception_internal_insn(s, EXCP_SEMIHOST); + } else { + unallocated_encoding(s); + } + return true; } =20 /* @@ -14188,9 +14146,6 @@ static bool btype_destination_ok(uint32_t insn, boo= l bt, int btype) static void disas_a64_legacy(DisasContext *s, uint32_t insn) { switch (extract32(insn, 25, 4)) { - case 0xa: case 0xb: /* Branch, exception generation and system insns */ - disas_b_exc_sys(s, insn); - break; case 0x4: case 0x6: case 0xc: --=20 2.34.1 From nobody Fri May 10 11:25:59 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1686499396; cv=none; d=zohomail.com; s=zohoarc; b=ZgMmUjCxSQJ9G3qadIx01evJmQgrxIhSMZJkTZl4dIzqiQBvp/8BrKXGo+7nmNFiznxyXvmEdYJ06/gsoY1ma3wHBizQ+Hq3EqVNCR2ePU66bqO0xmVkqFsdkqRI6YJpoU+EzFCpITVa4olaHJpaIC9fzQVN57KRKrXyXZcIxFM= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1686499396; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=SdGx08aoksaLp21YxsKPPHNcMRVUjRR75hXQYQOrgY4=; b=Uta7+Irjd9A3teLJoj+wrwTmwRhuCg13GQ41O3nrskD6IuJy0RENkqZVPfFt/1UhmYG33/PxZESKoAaqjDbqMDWhmyAKNIdNGYv4ld2mLy2h6cwmiqcJ2qyNbN5VVrsiRmhpBWilis+lfD3aAP3Qn118bhnd2LZcN0XD5vMp5ko= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1686499396634340.0256693947217; Sun, 11 Jun 2023 09:03:16 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1q8NVc-0006Tt-T2; Sun, 11 Jun 2023 12:01:40 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1q8NUj-0005r4-Jn for qemu-devel@nongnu.org; Sun, 11 Jun 2023 12:00:50 -0400 Received: from mail-wr1-x42e.google.com ([2a00:1450:4864:20::42e]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1q8NUf-0000T7-IP for qemu-devel@nongnu.org; Sun, 11 Jun 2023 12:00:45 -0400 Received: by mail-wr1-x42e.google.com with SMTP id ffacd0b85a97d-30c55d2b9f3so2247158f8f.2 for ; Sun, 11 Jun 2023 09:00:40 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id m9-20020a056000008900b0030ae499da59sm9923022wrx.111.2023.06.11.09.00.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 11 Jun 2023 09:00:39 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1686499240; x=1689091240; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=SdGx08aoksaLp21YxsKPPHNcMRVUjRR75hXQYQOrgY4=; b=YOour/a+FPdkh8tOB4eNA5N8M21lsK3pynHJQlbYnyyUNF8VukyYld1chuEbl4XgcD o3lV4x+CvIkNXGNf/oX2XobxmXDcQLrkrK7TW/94uoEkUrc57+Jw0y/LzsIrIkUgfO+e BzdL4zEn0FJgav3tsELGatLDBIGlLz+HfMG0LmMc5Gz1tMxR8g0Nyxoidk3x4xDBL+P/ iH+8Jyv3sxet1WPY3UXGsO9tsGLNtxjRQFqwMqZwrW26DotcVbM41V0eXPnBbZkXhIYu rcF5elCprmkF7zDadHW6I4M1pKPumC2i0O+3NzV0G+Ren9LDcnkyTphkz4vYBEgVXd1M U5Xw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1686499240; x=1689091240; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=SdGx08aoksaLp21YxsKPPHNcMRVUjRR75hXQYQOrgY4=; b=Hv9nZL1d4FqRxYn0tUd6f5b1ceVKMVsf+tOKYzrwtGluZ0ehXV/jMtkKFN1zOLrFsA oYcjcI3rTT0XuaicslIFQ08cRwpZQjVHeMUX5lJ/ZriGNuFPBAIi7VLPESrlJaa3kMtb 7EmnEgIOP/Yh6YeR9drXjSPgx8UXh1dzQzJAYoWDE0lA7mQGcVpDRJ3KP3ieS8Ic63dR bm2Csd9IOHOA88UU3DCZHGrlhfH3VkiNth5QzfTpXhoUIx1SHFnqVeUBRez1YMT67QpC N6GjZUp0f4qulJ7+BVZYoUMxpFErNi1/P2xfL+B3D7PdTztZRjoiHcCr++7YLP9nXltn /vFg== X-Gm-Message-State: AC+VfDyecsI9/ayonwUs32ijceRnw4tR5rVyI+z7Z6T+ftnP6F0CKFTk 2zEkkqmk9sYUOHBAFRAtMw0lEQ== X-Google-Smtp-Source: ACHHUZ78A1hrsPWPkWScIJ2j+eJWJwSBxb3D6tfEDclu/rE1gav1IGr4DUC6dFf/bsjgFYr4I92/1A== X-Received: by 2002:adf:e8d0:0:b0:309:31ac:6663 with SMTP id k16-20020adfe8d0000000b0030931ac6663mr2852103wrn.16.1686499239782; Sun, 11 Jun 2023 09:00:39 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH v2 11/23] target/arm: Convert load/store exclusive and ordered to decodetree Date: Sun, 11 Jun 2023 17:00:20 +0100 Message-Id: <20230611160032.274823-12-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230611160032.274823-1-peter.maydell@linaro.org> References: <20230611160032.274823-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42e; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1686499398658100001 Content-Type: text/plain; charset="utf-8" Convert the instructions in the load/store exclusive (STXR, STLXR, LDXR, LDAXR) and load/store ordered (STLR, STLLR, LDAR, LDLAR) to decodetree. Note that for STLR, STLLR, LDAR, LDLAR this fixes an under-decoding in the legacy decoder where we were not checking that the RES1 bits in the Rs and Rt2 fields were set. The new function ldst_iss_sf() is equivalent to the existing disas_ldst_compute_iss_sf(), but it takes the pre-decoded 'ext' field rather than taking an undecoded two-bit opc field and extracting 'ext' from it. Once all the loads and stores have been converted to decodetree disas_ldst_compute_iss_sf() will be unused and can be deleted. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Message-id: 20230602155223.2040685-9-peter.maydell@linaro.org --- target/arm/tcg/a64.decode | 11 +++ target/arm/tcg/translate-a64.c | 154 ++++++++++++++++++++------------- 2 files changed, 103 insertions(+), 62 deletions(-) diff --git a/target/arm/tcg/a64.decode b/target/arm/tcg/a64.decode index eeaca08ae83..c5894fc06d2 100644 --- a/target/arm/tcg/a64.decode +++ b/target/arm/tcg/a64.decode @@ -230,3 +230,14 @@ HLT 1101 0100 010 ................ 000 00 = @i16 # DCPS1 1101 0100 101 ................ 000 01 @i16 # DCPS2 1101 0100 101 ................ 000 10 @i16 # DCPS3 1101 0100 101 ................ 000 11 @i16 + +# Loads and stores + +&stxr rn rt rt2 rs sz lasr +&stlr rn rt sz lasr +@stxr sz:2 ...... ... rs:5 lasr:1 rt2:5 rn:5 rt:5 &stxr +@stlr sz:2 ...... ... ..... lasr:1 ..... rn:5 rt:5 &stlr +STXR .. 001000 000 ..... . ..... ..... ..... @stxr # inc STLXR +LDXR .. 001000 010 ..... . ..... ..... ..... @stxr # inc LDAXR +STLR .. 001000 100 11111 . 11111 ..... ..... @stlr # inc STLLR +LDAR .. 001000 110 11111 . 11111 ..... ..... @stlr # inc LDLAR diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c index a2a71b4062f..1ba2d6a75e4 100644 --- a/target/arm/tcg/translate-a64.c +++ b/target/arm/tcg/translate-a64.c @@ -2652,6 +2652,95 @@ static bool disas_ldst_compute_iss_sf(int size, bool= is_signed, int opc) return regsize =3D=3D 64; } =20 +static bool ldst_iss_sf(int size, bool sign, bool ext) +{ + + if (sign) { + /* + * Signed loads are 64 bit results if we are not going to + * do a zero-extend from 32 to 64 after the load. + * (For a store, sign and ext are always false.) + */ + return !ext; + } else { + /* Unsigned loads/stores work at the specified size */ + return size =3D=3D MO_64; + } +} + +static bool trans_STXR(DisasContext *s, arg_stxr *a) +{ + if (a->rn =3D=3D 31) { + gen_check_sp_alignment(s); + } + if (a->lasr) { + tcg_gen_mb(TCG_MO_ALL | TCG_BAR_STRL); + } + gen_store_exclusive(s, a->rs, a->rt, a->rt2, a->rn, a->sz, false); + return true; +} + +static bool trans_LDXR(DisasContext *s, arg_stxr *a) +{ + if (a->rn =3D=3D 31) { + gen_check_sp_alignment(s); + } + gen_load_exclusive(s, a->rt, a->rt2, a->rn, a->sz, false); + if (a->lasr) { + tcg_gen_mb(TCG_MO_ALL | TCG_BAR_LDAQ); + } + return true; +} + +static bool trans_STLR(DisasContext *s, arg_stlr *a) +{ + TCGv_i64 clean_addr; + MemOp memop; + bool iss_sf =3D ldst_iss_sf(a->sz, false, false); + + /* + * StoreLORelease is the same as Store-Release for QEMU, but + * needs the feature-test. + */ + if (!a->lasr && !dc_isar_feature(aa64_lor, s)) { + return false; + } + /* Generate ISS for non-exclusive accesses including LASR. */ + if (a->rn =3D=3D 31) { + gen_check_sp_alignment(s); + } + tcg_gen_mb(TCG_MO_ALL | TCG_BAR_STRL); + memop =3D check_ordered_align(s, a->rn, 0, true, a->sz); + clean_addr =3D gen_mte_check1(s, cpu_reg_sp(s, a->rn), + true, a->rn !=3D 31, memop); + do_gpr_st(s, cpu_reg(s, a->rt), clean_addr, memop, true, a->rt, + iss_sf, a->lasr); + return true; +} + +static bool trans_LDAR(DisasContext *s, arg_stlr *a) +{ + TCGv_i64 clean_addr; + MemOp memop; + bool iss_sf =3D ldst_iss_sf(a->sz, false, false); + + /* LoadLOAcquire is the same as Load-Acquire for QEMU. */ + if (!a->lasr && !dc_isar_feature(aa64_lor, s)) { + return false; + } + /* Generate ISS for non-exclusive accesses including LASR. */ + if (a->rn =3D=3D 31) { + gen_check_sp_alignment(s); + } + memop =3D check_ordered_align(s, a->rn, 0, false, a->sz); + clean_addr =3D gen_mte_check1(s, cpu_reg_sp(s, a->rn), + false, a->rn !=3D 31, memop); + do_gpr_ld(s, cpu_reg(s, a->rt), clean_addr, memop, false, true, + a->rt, iss_sf, a->lasr); + tcg_gen_mb(TCG_MO_ALL | TCG_BAR_LDAQ); + return true; +} + /* Load/store exclusive * * 31 30 29 24 23 22 21 20 16 15 14 10 9 5 4 0 @@ -2674,70 +2763,8 @@ static void disas_ldst_excl(DisasContext *s, uint32_= t insn) int is_lasr =3D extract32(insn, 15, 1); int o2_L_o1_o0 =3D extract32(insn, 21, 3) * 2 | is_lasr; int size =3D extract32(insn, 30, 2); - TCGv_i64 clean_addr; - MemOp memop; =20 switch (o2_L_o1_o0) { - case 0x0: /* STXR */ - case 0x1: /* STLXR */ - if (rn =3D=3D 31) { - gen_check_sp_alignment(s); - } - if (is_lasr) { - tcg_gen_mb(TCG_MO_ALL | TCG_BAR_STRL); - } - gen_store_exclusive(s, rs, rt, rt2, rn, size, false); - return; - - case 0x4: /* LDXR */ - case 0x5: /* LDAXR */ - if (rn =3D=3D 31) { - gen_check_sp_alignment(s); - } - gen_load_exclusive(s, rt, rt2, rn, size, false); - if (is_lasr) { - tcg_gen_mb(TCG_MO_ALL | TCG_BAR_LDAQ); - } - return; - - case 0x8: /* STLLR */ - if (!dc_isar_feature(aa64_lor, s)) { - break; - } - /* StoreLORelease is the same as Store-Release for QEMU. */ - /* fall through */ - case 0x9: /* STLR */ - /* Generate ISS for non-exclusive accesses including LASR. */ - if (rn =3D=3D 31) { - gen_check_sp_alignment(s); - } - tcg_gen_mb(TCG_MO_ALL | TCG_BAR_STRL); - memop =3D check_ordered_align(s, rn, 0, true, size); - clean_addr =3D gen_mte_check1(s, cpu_reg_sp(s, rn), - true, rn !=3D 31, memop); - do_gpr_st(s, cpu_reg(s, rt), clean_addr, memop, true, rt, - disas_ldst_compute_iss_sf(size, false, 0), is_lasr); - return; - - case 0xc: /* LDLAR */ - if (!dc_isar_feature(aa64_lor, s)) { - break; - } - /* LoadLOAcquire is the same as Load-Acquire for QEMU. */ - /* fall through */ - case 0xd: /* LDAR */ - /* Generate ISS for non-exclusive accesses including LASR. */ - if (rn =3D=3D 31) { - gen_check_sp_alignment(s); - } - memop =3D check_ordered_align(s, rn, 0, false, size); - clean_addr =3D gen_mte_check1(s, cpu_reg_sp(s, rn), - false, rn !=3D 31, memop); - do_gpr_ld(s, cpu_reg(s, rt), clean_addr, memop, false, true, - rt, disas_ldst_compute_iss_sf(size, false, 0), is_lasr); - tcg_gen_mb(TCG_MO_ALL | TCG_BAR_LDAQ); - return; - case 0x2: case 0x3: /* CASP / STXP */ if (size & 2) { /* STXP / STLXP */ if (rn =3D=3D 31) { @@ -2787,6 +2814,9 @@ static void disas_ldst_excl(DisasContext *s, uint32_t= insn) return; } break; + default: + /* Handled in decodetree */ + break; } unallocated_encoding(s); } --=20 2.34.1 From nobody Fri May 10 11:25:59 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1686499557; cv=none; d=zohomail.com; s=zohoarc; b=Oew7j0rkBNVWP51UcHa3X827v1bpJlxZ2ci5Zm2G5z6dYqQzXW9vHQtYvWjI4daPsFRp2xb6Ij7MLKRZK3oXewSNUfQnGrGLh4ouP+r67gzYzpA/4Flg5EW+FCyUjNlSwv9sYHgFBUiUNTHIw9od60iH/rT7G2By0AgpOFOSRVk= ARC-Message-Signature: i=1; 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id m9-20020a056000008900b0030ae499da59sm9923022wrx.111.2023.06.11.09.00.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 11 Jun 2023 09:00:40 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1686499240; x=1689091240; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=6KI6vCKi2hK4kMqI/ACVjSnqVa1PBuwOd1A7QPwu8LI=; b=tkc3WpNKu9t+jbTLQ4dI/E6epyt1V6zRVfi95pLb26KnoL9Hv7ZseTzzFIzIzzbN9f GtV5plRcAbM3FKzo4mMIeN9ctAjedU3vXF7eENT3rI1Ms8vrf+itIb3JCVvH/HlQ80VT 18LACp7PIIneOnds8bZH5ekkcVA56idVTo46mRarqO7bnPQx0BDf66v1mJLGu/IVkr5M MuGL4q1Vro4N2hmJ5O1oudSMKAhIIcQxiAJ2Lp0lwx9mYQRalWVsNdtSIK0Qsy0Ey1Do T2FdpEHeS+Zk0B2pSvCnZ8HNRLp1UNwetrknyBYaM4Y0Lh11xuUL9UYnVme1LS8QoaGh ZBTQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1686499240; x=1689091240; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=6KI6vCKi2hK4kMqI/ACVjSnqVa1PBuwOd1A7QPwu8LI=; b=gDfakUfY4ADzogKJ2RhgZ+ARJsfaUC4JLJTxEzT1DuF/HYvWnQdgr5TAmGi4bD+STz U/JPfuQtQxZV4Yz3vBr9zIDA352649I6H40fjCGyuiDiEofnri1UtUuRrgvXIV+idz9/ uBkRPQRRH9NRca6BTEqctSj/vGgosaQW1dgBEqcE33o2LmCZRDyNZVEtcylPr6VOIp61 9lQjAbnv4V8JVnU3MH7UbBYULBAm7uhoUetOLIh7t+ztjD1z0oBnxPW5B5xEnL/hNSIy WDxvJOJ0KqOLvovDEaW71dSU3Ll/G51ZRfNDTXeGJOg4ftIiuhUyegawSRQ1UcEY8Ddh HRAg== X-Gm-Message-State: AC+VfDy1SC/Aoa9jvhzguIk5ujZoFRnQCKg/zhLN7sz6OlsPOqFQOH7H uNJytu+UwBeqX6W318rzUS9jAivVog3LpIowKoY= X-Google-Smtp-Source: ACHHUZ66newDqLoY928ay/To/oTbrFivPPS4UJb4QlB12jD9IDqKuHKPlCwAeaJwlZuZ0xDRF/s5Xw== X-Received: by 2002:a5d:4952:0:b0:309:3bc3:7d1f with SMTP id r18-20020a5d4952000000b003093bc37d1fmr2681565wrs.70.1686499240359; Sun, 11 Jun 2023 09:00:40 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH v2 12/23] target/arm: Convert LDXP, STXP, CASP, CAS to decodetree Date: Sun, 11 Jun 2023 17:00:21 +0100 Message-Id: <20230611160032.274823-13-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230611160032.274823-1-peter.maydell@linaro.org> References: <20230611160032.274823-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32a; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1686499558949100003 Content-Type: text/plain; charset="utf-8" Convert the load/store exclusive pair (LDXP, STXP, LDAXP, STLXP), compare-and-swap pair (CASP, CASPA, CASPAL, CASPL), and compare-and swap (CAS, CASA, CASAL, CASL) instructions to decodetree. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Message-id: 20230602155223.2040685-10-peter.maydell@linaro.org --- target/arm/tcg/a64.decode | 11 +++ target/arm/tcg/translate-a64.c | 121 ++++++++++++--------------------- 2 files changed, 53 insertions(+), 79 deletions(-) diff --git a/target/arm/tcg/a64.decode b/target/arm/tcg/a64.decode index c5894fc06d2..6b1079b8bdf 100644 --- a/target/arm/tcg/a64.decode +++ b/target/arm/tcg/a64.decode @@ -237,7 +237,18 @@ HLT 1101 0100 010 ................ 000 00 = @i16 &stlr rn rt sz lasr @stxr sz:2 ...... ... rs:5 lasr:1 rt2:5 rn:5 rt:5 &stxr @stlr sz:2 ...... ... ..... lasr:1 ..... rn:5 rt:5 &stlr +%imm1_30_p2 30:1 !function=3Dplus_2 +@stxp .. ...... ... rs:5 lasr:1 rt2:5 rn:5 rt:5 &stxr sz=3D%imm1= _30_p2 STXR .. 001000 000 ..... . ..... ..... ..... @stxr # inc STLXR LDXR .. 001000 010 ..... . ..... ..... ..... @stxr # inc LDAXR STLR .. 001000 100 11111 . 11111 ..... ..... @stlr # inc STLLR LDAR .. 001000 110 11111 . 11111 ..... ..... @stlr # inc LDLAR + +STXP 1 . 001000 001 ..... . ..... ..... ..... @stxp # inc STLXP +LDXP 1 . 001000 011 ..... . ..... ..... ..... @stxp # inc LDAXP + +# CASP, CASPA, CASPAL, CASPL (we don't decode the bits that determine +# acquire/release semantics because QEMU's cmpxchg always has those) +CASP 0 . 001000 0 - 1 rs:5 - 11111 rn:5 rt:5 sz=3D%imm1_30_p2 +# CAS, CASA, CASAL, CASL +CAS sz:2 001000 1 - 1 rs:5 - 11111 rn:5 rt:5 diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c index 1ba2d6a75e4..ff4338ee4df 100644 --- a/target/arm/tcg/translate-a64.c +++ b/target/arm/tcg/translate-a64.c @@ -2741,84 +2741,50 @@ static bool trans_LDAR(DisasContext *s, arg_stlr *a) return true; } =20 -/* Load/store exclusive - * - * 31 30 29 24 23 22 21 20 16 15 14 10 9 5 4 0 - * +-----+-------------+----+---+----+------+----+-------+------+------+ - * | sz | 0 0 1 0 0 0 | o2 | L | o1 | Rs | o0 | Rt2 | Rn | Rt | - * +-----+-------------+----+---+----+------+----+-------+------+------+ - * - * sz: 00 -> 8 bit, 01 -> 16 bit, 10 -> 32 bit, 11 -> 64 bit - * L: 0 -> store, 1 -> load - * o2: 0 -> exclusive, 1 -> not - * o1: 0 -> single register, 1 -> register pair - * o0: 1 -> load-acquire/store-release, 0 -> not - */ -static void disas_ldst_excl(DisasContext *s, uint32_t insn) +static bool trans_STXP(DisasContext *s, arg_stxr *a) { - int rt =3D extract32(insn, 0, 5); - int rn =3D extract32(insn, 5, 5); - int rt2 =3D extract32(insn, 10, 5); - int rs =3D extract32(insn, 16, 5); - int is_lasr =3D extract32(insn, 15, 1); - int o2_L_o1_o0 =3D extract32(insn, 21, 3) * 2 | is_lasr; - int size =3D extract32(insn, 30, 2); - - switch (o2_L_o1_o0) { - case 0x2: case 0x3: /* CASP / STXP */ - if (size & 2) { /* STXP / STLXP */ - if (rn =3D=3D 31) { - gen_check_sp_alignment(s); - } - if (is_lasr) { - tcg_gen_mb(TCG_MO_ALL | TCG_BAR_STRL); - } - gen_store_exclusive(s, rs, rt, rt2, rn, size, true); - return; - } - if (rt2 =3D=3D 31 - && ((rt | rs) & 1) =3D=3D 0 - && dc_isar_feature(aa64_atomics, s)) { - /* CASP / CASPL */ - gen_compare_and_swap_pair(s, rs, rt, rn, size | 2); - return; - } - break; - - case 0x6: case 0x7: /* CASPA / LDXP */ - if (size & 2) { /* LDXP / LDAXP */ - if (rn =3D=3D 31) { - gen_check_sp_alignment(s); - } - gen_load_exclusive(s, rt, rt2, rn, size, true); - if (is_lasr) { - tcg_gen_mb(TCG_MO_ALL | TCG_BAR_LDAQ); - } - return; - } - if (rt2 =3D=3D 31 - && ((rt | rs) & 1) =3D=3D 0 - && dc_isar_feature(aa64_atomics, s)) { - /* CASPA / CASPAL */ - gen_compare_and_swap_pair(s, rs, rt, rn, size | 2); - return; - } - break; - - case 0xa: /* CAS */ - case 0xb: /* CASL */ - case 0xe: /* CASA */ - case 0xf: /* CASAL */ - if (rt2 =3D=3D 31 && dc_isar_feature(aa64_atomics, s)) { - gen_compare_and_swap(s, rs, rt, rn, size); - return; - } - break; - default: - /* Handled in decodetree */ - break; + if (a->rn =3D=3D 31) { + gen_check_sp_alignment(s); } - unallocated_encoding(s); + if (a->lasr) { + tcg_gen_mb(TCG_MO_ALL | TCG_BAR_STRL); + } + gen_store_exclusive(s, a->rs, a->rt, a->rt2, a->rn, a->sz, true); + return true; +} + +static bool trans_LDXP(DisasContext *s, arg_stxr *a) +{ + if (a->rn =3D=3D 31) { + gen_check_sp_alignment(s); + } + gen_load_exclusive(s, a->rt, a->rt2, a->rn, a->sz, true); + if (a->lasr) { + tcg_gen_mb(TCG_MO_ALL | TCG_BAR_LDAQ); + } + return true; +} + +static bool trans_CASP(DisasContext *s, arg_CASP *a) +{ + if (!dc_isar_feature(aa64_atomics, s)) { + return false; + } + if (((a->rt | a->rs) & 1) !=3D 0) { + return false; + } + + gen_compare_and_swap_pair(s, a->rs, a->rt, a->rn, a->sz); + return true; +} + +static bool trans_CAS(DisasContext *s, arg_CAS *a) +{ + if (!dc_isar_feature(aa64_atomics, s)) { + return false; + } + gen_compare_and_swap(s, a->rs, a->rt, a->rn, a->sz); + return true; } =20 /* @@ -4247,9 +4213,6 @@ static void disas_ldst_tag(DisasContext *s, uint32_t = insn) static void disas_ldst(DisasContext *s, uint32_t insn) { switch (extract32(insn, 24, 6)) { - case 0x08: /* Load/store exclusive */ - disas_ldst_excl(s, insn); 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id m9-20020a056000008900b0030ae499da59sm9923022wrx.111.2023.06.11.09.00.40 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 11 Jun 2023 09:00:40 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1686499241; x=1689091241; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=Zon/L+1E7pApwo5q3JdDpEUBgb4onUwkVEYPmbfuPTc=; b=CGcl4O4q1QVCU27e1WrwojCYtLjCGvcxo1eL1svsBWC8+dzEqU3ffqCzvTQPuHId1M fXv9zgyTON6h3+SEJBVk8BS6IcXN/u7QTXGw2I3zIm502zD+0LsdplJuu6DzGyYecMKw /h/lNqhZRtqTDIDFcZoCcmuPnjOFxXItbF3SHqqUc9VDvZD3OGkgjDLFK0BbbhJdsvor hMvKlbhtPTVa5Ny+JPQ5oOjTX4t8g5WrEScMccV6HQemFhwXVA5reyH2IgB3YIPVlB4v V/Fs48wwg/mhwotTqgtzwz+CxG+o/Q5Tl4nk3VWqODSuv47xZDSqnNQ6SPvMOI9aqQF3 xykA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1686499241; x=1689091241; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=Zon/L+1E7pApwo5q3JdDpEUBgb4onUwkVEYPmbfuPTc=; b=E4MBg5Tkk2dywaHgOSs9uMvvJyKCyxK2pFk4/u0Plgkd6HWTe2nQqjL8s+pxNwlGCr HnbAp6zFG3E+qzbrcW20tLPlDU3pxvX8w8+nsTi/Bf64BbGohuzNqgIv/lA26F2fVITF gGup7Kkh40rw5uJNPDKEJzHhLnIrLlPcZbFXRa+QxBtPB1tLg4aaPlqgOzWzRbgrvojb ENKJXX9mDlDWWwFnyC/D5OQZP1zHgqSBsLUOOvgH7raBz2rm+K8E/uaYuen/gH8hbNCy LG3PnUzhAiKOcwpY+mpb18D/aZF5zfsbHhWt0ZHJpM6k6AjD74OsqrUmtgRFzGw50I+e xzhQ== X-Gm-Message-State: AC+VfDzYwrXlGClINyjdRa675piJkHUjqFse2Jj3W66Nk/mmYYYFhWLx T8uJuAlcGFnHD57X0f3wfiBJx2OkZjSbU6Shn6k= X-Google-Smtp-Source: ACHHUZ64yRwLQyn9v7eIJzI5bcTUBD0TRPFGuXBqyJHCyaALWwLWbAZdsFDTYIvBeh6Qt+OdfYcclw== X-Received: by 2002:adf:fac9:0:b0:30a:b4e1:a89b with SMTP id a9-20020adffac9000000b0030ab4e1a89bmr3151898wrs.67.1686499241004; Sun, 11 Jun 2023 09:00:41 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH v2 13/23] target/arm: Convert load reg (literal) group to decodetree Date: Sun, 11 Jun 2023 17:00:22 +0100 Message-Id: <20230611160032.274823-14-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230611160032.274823-1-peter.maydell@linaro.org> References: <20230611160032.274823-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::333; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x333.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1686499490683100001 Content-Type: text/plain; charset="utf-8" Convert the "Load register (literal)" instruction class to decodetree. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Message-id: 20230602155223.2040685-11-peter.maydell@linaro.org --- target/arm/tcg/a64.decode | 13 ++++++ target/arm/tcg/translate-a64.c | 76 ++++++++++------------------------ 2 files changed, 35 insertions(+), 54 deletions(-) diff --git a/target/arm/tcg/a64.decode b/target/arm/tcg/a64.decode index 6b1079b8bdf..c2c6ac0196d 100644 --- a/target/arm/tcg/a64.decode +++ b/target/arm/tcg/a64.decode @@ -252,3 +252,16 @@ LDXP 1 . 001000 011 ..... . ..... ..... ...= .. @stxp # inc LDAXP CASP 0 . 001000 0 - 1 rs:5 - 11111 rn:5 rt:5 sz=3D%imm1_30_p2 # CAS, CASA, CASAL, CASL CAS sz:2 001000 1 - 1 rs:5 - 11111 rn:5 rt:5 + +&ldlit rt imm sz sign +@ldlit .. ... . .. ................... rt:5 &ldlit imm=3D%imm19 + +LD_lit 00 011 0 00 ................... ..... @ldlit sz=3D2 sign= =3D0 +LD_lit 01 011 0 00 ................... ..... @ldlit sz=3D3 sign= =3D0 +LD_lit 10 011 0 00 ................... ..... @ldlit sz=3D2 sign= =3D1 +LD_lit_v 00 011 1 00 ................... ..... @ldlit sz=3D2 sign= =3D0 +LD_lit_v 01 011 1 00 ................... ..... @ldlit sz=3D3 sign= =3D0 +LD_lit_v 10 011 1 00 ................... ..... @ldlit sz=3D4 sign= =3D0 + +# PRFM +NOP 11 011 0 00 ------------------- ----- diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c index ff4338ee4df..d1df41f2e5e 100644 --- a/target/arm/tcg/translate-a64.c +++ b/target/arm/tcg/translate-a64.c @@ -2787,62 +2787,33 @@ static bool trans_CAS(DisasContext *s, arg_CAS *a) return true; } =20 -/* - * Load register (literal) - * - * 31 30 29 27 26 25 24 23 5 4 0 - * +-----+-------+---+-----+-------------------+-------+ - * | opc | 0 1 1 | V | 0 0 | imm19 | Rt | - * +-----+-------+---+-----+-------------------+-------+ - * - * V: 1 -> vector (simd/fp) - * opc (non-vector): 00 -> 32 bit, 01 -> 64 bit, - * 10-> 32 bit signed, 11 -> prefetch - * opc (vector): 00 -> 32 bit, 01 -> 64 bit, 10 -> 128 bit (11 unallocated) - */ -static void disas_ld_lit(DisasContext *s, uint32_t insn) +static bool trans_LD_lit(DisasContext *s, arg_ldlit *a) { - int rt =3D extract32(insn, 0, 5); - int64_t imm =3D sextract32(insn, 5, 19) << 2; - bool is_vector =3D extract32(insn, 26, 1); - int opc =3D extract32(insn, 30, 2); - bool is_signed =3D false; - int size =3D 2; - TCGv_i64 tcg_rt, clean_addr; + bool iss_sf =3D ldst_iss_sf(a->sz, a->sign, false); + TCGv_i64 tcg_rt =3D cpu_reg(s, a->rt); + TCGv_i64 clean_addr =3D tcg_temp_new_i64(); + MemOp memop =3D finalize_memop(s, a->sz + a->sign * MO_SIGN); + + gen_pc_plus_diff(s, clean_addr, a->imm); + do_gpr_ld(s, tcg_rt, clean_addr, memop, + false, true, a->rt, iss_sf, false); + return true; +} + +static bool trans_LD_lit_v(DisasContext *s, arg_ldlit *a) +{ + /* Load register (literal), vector version */ + TCGv_i64 clean_addr; MemOp memop; =20 - if (is_vector) { - if (opc =3D=3D 3) { - unallocated_encoding(s); - return; - } - size =3D 2 + opc; - if (!fp_access_check(s)) { - return; - } - memop =3D finalize_memop_asimd(s, size); - } else { - if (opc =3D=3D 3) { - /* PRFM (literal) : prefetch */ - return; - } - size =3D 2 + extract32(opc, 0, 1); - is_signed =3D extract32(opc, 1, 1); - memop =3D finalize_memop(s, size + is_signed * MO_SIGN); + if (!fp_access_check(s)) { + return true; } - - tcg_rt =3D cpu_reg(s, rt); - + memop =3D finalize_memop_asimd(s, a->sz); clean_addr =3D tcg_temp_new_i64(); - gen_pc_plus_diff(s, clean_addr, imm); - - if (is_vector) { - do_fp_ld(s, rt, clean_addr, memop); - } else { - /* Only unsigned 32bit loads target 32bit registers. */ - bool iss_sf =3D opc !=3D 0; - do_gpr_ld(s, tcg_rt, clean_addr, memop, false, true, rt, iss_sf, f= alse); - } + gen_pc_plus_diff(s, clean_addr, a->imm); + do_fp_ld(s, a->rt, clean_addr, memop); + return true; } =20 /* @@ -4213,9 +4184,6 @@ static void disas_ldst_tag(DisasContext *s, uint32_t = insn) static void disas_ldst(DisasContext *s, uint32_t insn) { switch (extract32(insn, 24, 6)) { - case 0x18: case 0x1c: /* Load register (literal) */ - disas_ld_lit(s, insn); - break; case 0x28: case 0x29: case 0x2c: case 0x2d: /* Load/store pair (all forms) */ disas_ldst_pair(s, insn); --=20 2.34.1 From nobody Fri May 10 11:25:59 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1686499439; cv=none; d=zohomail.com; s=zohoarc; b=ZyYDxpmEzBpf4U0Gsv33RFoJ4U1aNXqGZAKl1IM8ZvN+f6bbgo6n9IYtg2gOA5zgjJFp8fXc/P8gqfPiae0nuiwyAw/DZnpyA5qnS7B4Q9LBy3JahO25X/+Haj2FbrpSwNYgqIbKjT+GLSdLjGaglGR6oJSjkzHDuxd4FJjLFwk= ARC-Message-Signature: i=1; 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id m9-20020a056000008900b0030ae499da59sm9923022wrx.111.2023.06.11.09.00.41 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 11 Jun 2023 09:00:41 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1686499241; x=1689091241; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=QI2O7/o+tJxt//r7OSwmG8FHKQHHruFPQGJIFvn8wxU=; b=BJu5vXEWPO0qZmlRnQ485kpWcRaSFUXgCeuhvN1rTvNeJmYIF7R7Tp7wsJFrIf2Df/ +fxOjYO34zaWkRap9KX7sBQ6lUpDNrmAffxgT5oF4SyGreevXTQ3ZYNRrHm0PzW7B2VW ZYlO0AwXmp4gafufOtxpvbzTg81hslj1RewjQYJyMej3oF2vtc/4hV4qc7BPkcf9piJI GBYPePkDbxozhu0JFhGtZqS2NwW8p9NOe2zfg0vcFiRKkQi/dvPvclEfyarfeF0ECoIL g0Fwohi/fZyo3EVM1DIZ7E0LxfCrllZfJMklcIpPw7o6nQFHJp21M5OKpLkxpmPbDKaB IQrQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1686499241; x=1689091241; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=QI2O7/o+tJxt//r7OSwmG8FHKQHHruFPQGJIFvn8wxU=; b=Mm4rgscP8rtJ7UjTluixDKaYCzSVNhh8+g+FsVRHr45WQpupnAWP7j0flQ5580qXpo VAfZveKxvzIWRnlvqyG0nINr6viM7uHni4jdwgo8XrQFjbO5iGVCzeudKhlD2uTt5TTF ySDFueVWbydtsLVzYHrPJ/jmp3FtFtCtQna08xSeyjg3vjEatw4nBOilWsQm7s6RTRzL QDlhBcJdPeVr7lh7EMDa428XUsHEsOmT6bDB8WX6lPsITcjPFsFHsaZfs+ppb5D0IiR5 Vza2taSqXC53kNp0JY9w8wqo2Ax1v2X4X+G7dL01RFtStlGmVTfQAgYgs1k8PH7nHrji guKg== X-Gm-Message-State: AC+VfDwbDlhAg/L/CYNwR2J2bHIB1MEcRcyMDxHML1B5pnkt/i5KELep AtnBu1IrQlp9O+UdWQPRyU5IAg== X-Google-Smtp-Source: ACHHUZ7Wgb3qRthTS+FhLtRFXPH6noyr+41l5bRbaKKMLf7a+hXqBQlpnvw/Njl77doTHK4fbuCA2w== X-Received: by 2002:a5d:6412:0:b0:30f:bafb:247a with SMTP id z18-20020a5d6412000000b0030fbafb247amr1881638wru.55.1686499241533; Sun, 11 Jun 2023 09:00:41 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH v2 14/23] target/arm: Convert load/store-pair to decodetree Date: Sun, 11 Jun 2023 17:00:23 +0100 Message-Id: <20230611160032.274823-15-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230611160032.274823-1-peter.maydell@linaro.org> References: <20230611160032.274823-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32a; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1686499441081100001 Content-Type: text/plain; charset="utf-8" Convert the load/store register pair insns (LDP, STP, LDNP, STNP, LDPSW, STGP) to decodetree. Signed-off-by: Peter Maydell Message-id: 20230602155223.2040685-12-peter.maydell@linaro.org Reviewed-by: Richard Henderson --- This was reviewed in v1, but the underlying code changed enough in the atomic-ops work that I've dropped the R-by tag. --- target/arm/tcg/a64.decode | 61 +++++ target/arm/tcg/translate-a64.c | 425 ++++++++++++++++----------------- 2 files changed, 271 insertions(+), 215 deletions(-) diff --git a/target/arm/tcg/a64.decode b/target/arm/tcg/a64.decode index c2c6ac0196d..f5787919931 100644 --- a/target/arm/tcg/a64.decode +++ b/target/arm/tcg/a64.decode @@ -265,3 +265,64 @@ LD_lit_v 10 011 1 00 ................... ..... = @ldlit sz=3D4 sign=3D0 =20 # PRFM NOP 11 011 0 00 ------------------- ----- + +&ldstpair rt2 rt rn imm sz sign w p +@ldstpair .. ... . ... . imm:s7 rt2:5 rn:5 rt:5 &ldstpair + +# STNP, LDNP: Signed offset, non-temporal hint. We don't emulate caches +# so we ignore hints about data access patterns, and handle these like +# plain signed offset. +STP 00 101 0 000 0 ....... ..... ..... ..... @ldstpair sz=3D2 = sign=3D0 p=3D0 w=3D0 +LDP 00 101 0 000 1 ....... ..... ..... ..... @ldstpair sz=3D2 = sign=3D0 p=3D0 w=3D0 +STP 10 101 0 000 0 ....... ..... ..... ..... @ldstpair sz=3D3 = sign=3D0 p=3D0 w=3D0 +LDP 10 101 0 000 1 ....... ..... ..... ..... @ldstpair sz=3D3 = sign=3D0 p=3D0 w=3D0 +STP_v 00 101 1 000 0 ....... ..... ..... ..... @ldstpair sz=3D2 = sign=3D0 p=3D0 w=3D0 +LDP_v 00 101 1 000 1 ....... ..... ..... ..... @ldstpair sz=3D2 = sign=3D0 p=3D0 w=3D0 +STP_v 01 101 1 000 0 ....... ..... ..... ..... @ldstpair sz=3D3 = sign=3D0 p=3D0 w=3D0 +LDP_v 01 101 1 000 1 ....... ..... ..... ..... @ldstpair sz=3D3 = sign=3D0 p=3D0 w=3D0 +STP_v 10 101 1 000 0 ....... ..... ..... ..... @ldstpair sz=3D4 = sign=3D0 p=3D0 w=3D0 +LDP_v 10 101 1 000 1 ....... ..... ..... ..... @ldstpair sz=3D4 = sign=3D0 p=3D0 w=3D0 + +# STP and LDP: post-indexed +STP 00 101 0 001 0 ....... ..... ..... ..... @ldstpair sz=3D2 = sign=3D0 p=3D1 w=3D1 +LDP 00 101 0 001 1 ....... ..... ..... ..... @ldstpair sz=3D2 = sign=3D0 p=3D1 w=3D1 +LDP 01 101 0 001 1 ....... ..... ..... ..... @ldstpair sz=3D2 = sign=3D1 p=3D1 w=3D1 +STP 10 101 0 001 0 ....... ..... ..... ..... @ldstpair sz=3D3 = sign=3D0 p=3D1 w=3D1 +LDP 10 101 0 001 1 ....... ..... ..... ..... @ldstpair sz=3D3 = sign=3D0 p=3D1 w=3D1 +STP_v 00 101 1 001 0 ....... ..... ..... ..... @ldstpair sz=3D2 = sign=3D0 p=3D1 w=3D1 +LDP_v 00 101 1 001 1 ....... ..... ..... ..... @ldstpair sz=3D2 = sign=3D0 p=3D1 w=3D1 +STP_v 01 101 1 001 0 ....... ..... ..... ..... @ldstpair sz=3D3 = sign=3D0 p=3D1 w=3D1 +LDP_v 01 101 1 001 1 ....... ..... ..... ..... @ldstpair sz=3D3 = sign=3D0 p=3D1 w=3D1 +STP_v 10 101 1 001 0 ....... ..... ..... ..... @ldstpair sz=3D4 = sign=3D0 p=3D1 w=3D1 +LDP_v 10 101 1 001 1 ....... ..... ..... ..... @ldstpair sz=3D4 = sign=3D0 p=3D1 w=3D1 + +# STP and LDP: offset +STP 00 101 0 010 0 ....... ..... ..... ..... @ldstpair sz=3D2 = sign=3D0 p=3D0 w=3D0 +LDP 00 101 0 010 1 ....... ..... ..... ..... @ldstpair sz=3D2 = sign=3D0 p=3D0 w=3D0 +LDP 01 101 0 010 1 ....... ..... ..... ..... @ldstpair sz=3D2 = sign=3D1 p=3D0 w=3D0 +STP 10 101 0 010 0 ....... ..... ..... ..... @ldstpair sz=3D3 = sign=3D0 p=3D0 w=3D0 +LDP 10 101 0 010 1 ....... ..... ..... ..... @ldstpair sz=3D3 = sign=3D0 p=3D0 w=3D0 +STP_v 00 101 1 010 0 ....... ..... ..... ..... @ldstpair sz=3D2 = sign=3D0 p=3D0 w=3D0 +LDP_v 00 101 1 010 1 ....... ..... ..... ..... @ldstpair sz=3D2 = sign=3D0 p=3D0 w=3D0 +STP_v 01 101 1 010 0 ....... ..... ..... ..... @ldstpair sz=3D3 = sign=3D0 p=3D0 w=3D0 +LDP_v 01 101 1 010 1 ....... ..... ..... ..... @ldstpair sz=3D3 = sign=3D0 p=3D0 w=3D0 +STP_v 10 101 1 010 0 ....... ..... ..... ..... @ldstpair sz=3D4 = sign=3D0 p=3D0 w=3D0 +LDP_v 10 101 1 010 1 ....... ..... ..... ..... @ldstpair sz=3D4 = sign=3D0 p=3D0 w=3D0 + +# STP and LDP: pre-indexed +STP 00 101 0 011 0 ....... ..... ..... ..... @ldstpair sz=3D2 = sign=3D0 p=3D0 w=3D1 +LDP 00 101 0 011 1 ....... ..... ..... ..... @ldstpair sz=3D2 = sign=3D0 p=3D0 w=3D1 +LDP 01 101 0 011 1 ....... ..... ..... ..... @ldstpair sz=3D2 = sign=3D1 p=3D0 w=3D1 +STP 10 101 0 011 0 ....... ..... ..... ..... @ldstpair sz=3D3 = sign=3D0 p=3D0 w=3D1 +LDP 10 101 0 011 1 ....... ..... ..... ..... @ldstpair sz=3D3 = sign=3D0 p=3D0 w=3D1 +STP_v 00 101 1 011 0 ....... ..... ..... ..... @ldstpair sz=3D2 = sign=3D0 p=3D0 w=3D1 +LDP_v 00 101 1 011 1 ....... ..... ..... ..... @ldstpair sz=3D2 = sign=3D0 p=3D0 w=3D1 +STP_v 01 101 1 011 0 ....... ..... ..... ..... @ldstpair sz=3D3 = sign=3D0 p=3D0 w=3D1 +LDP_v 01 101 1 011 1 ....... ..... ..... ..... @ldstpair sz=3D3 = sign=3D0 p=3D0 w=3D1 +STP_v 10 101 1 011 0 ....... ..... ..... ..... @ldstpair sz=3D4 = sign=3D0 p=3D0 w=3D1 +LDP_v 10 101 1 011 1 ....... ..... ..... ..... @ldstpair sz=3D4 = sign=3D0 p=3D0 w=3D1 + +# STGP: store tag and pair +STGP 01 101 0 001 0 ....... ..... ..... ..... @ldstpair sz=3D3 = sign=3D0 p=3D1 w=3D1 +STGP 01 101 0 010 0 ....... ..... ..... ..... @ldstpair sz=3D3 = sign=3D0 p=3D0 w=3D0 +STGP 01 101 0 011 0 ....... ..... ..... ..... @ldstpair sz=3D3 = sign=3D0 p=3D0 w=3D1 diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c index d1df41f2e5e..8b8c9939013 100644 --- a/target/arm/tcg/translate-a64.c +++ b/target/arm/tcg/translate-a64.c @@ -2816,229 +2816,228 @@ static bool trans_LD_lit_v(DisasContext *s, arg_l= dlit *a) return true; } =20 -/* - * LDNP (Load Pair - non-temporal hint) - * LDP (Load Pair - non vector) - * LDPSW (Load Pair Signed Word - non vector) - * STNP (Store Pair - non-temporal hint) - * STP (Store Pair - non vector) - * LDNP (Load Pair of SIMD&FP - non-temporal hint) - * LDP (Load Pair of SIMD&FP) - * STNP (Store Pair of SIMD&FP - non-temporal hint) - * STP (Store Pair of SIMD&FP) - * - * 31 30 29 27 26 25 24 23 22 21 15 14 10 9 5 4 0 - * +-----+-------+---+---+-------+---+-----------------------------+ - * | opc | 1 0 1 | V | 0 | index | L | imm7 | Rt2 | Rn | Rt | - * +-----+-------+---+---+-------+---+-------+-------+------+------+ - * - * opc: LDP/STP/LDNP/STNP 00 -> 32 bit, 10 -> 64 bit - * LDPSW/STGP 01 - * LDP/STP/LDNP/STNP (SIMD) 00 -> 32 bit, 01 -> 64 bit, 10 -> 128 bit - * V: 0 -> GPR, 1 -> Vector - * idx: 00 -> signed offset with non-temporal hint, 01 -> post-index, - * 10 -> signed offset, 11 -> pre-index - * L: 0 -> Store 1 -> Load - * - * Rt, Rt2 =3D GPR or SIMD registers to be stored - * Rn =3D general purpose register containing address - * imm7 =3D signed offset (multiple of 4 or 8 depending on size) - */ -static void disas_ldst_pair(DisasContext *s, uint32_t insn) +static void op_addr_ldstpair_pre(DisasContext *s, arg_ldstpair *a, + TCGv_i64 *clean_addr, TCGv_i64 *dirty_add= r, + uint64_t offset, bool is_store, MemOp mop) { - int rt =3D extract32(insn, 0, 5); - int rn =3D extract32(insn, 5, 5); - int rt2 =3D extract32(insn, 10, 5); - uint64_t offset =3D sextract64(insn, 15, 7); - int index =3D extract32(insn, 23, 2); - bool is_vector =3D extract32(insn, 26, 1); - bool is_load =3D extract32(insn, 22, 1); - int opc =3D extract32(insn, 30, 2); - bool is_signed =3D false; - bool postindex =3D false; - bool wback =3D false; - bool set_tag =3D false; - TCGv_i64 clean_addr, dirty_addr; - MemOp mop; - int size; - - if (opc =3D=3D 3) { - unallocated_encoding(s); - return; - } - - if (is_vector) { - size =3D 2 + opc; - } else if (opc =3D=3D 1 && !is_load) { - /* STGP */ - if (!dc_isar_feature(aa64_mte_insn_reg, s) || index =3D=3D 0) { - unallocated_encoding(s); - return; - } - size =3D 3; - set_tag =3D true; - } else { - size =3D 2 + extract32(opc, 1, 1); - is_signed =3D extract32(opc, 0, 1); - if (!is_load && is_signed) { - unallocated_encoding(s); - return; - } - } - - switch (index) { - case 1: /* post-index */ - postindex =3D true; - wback =3D true; - break; - case 0: - /* signed offset with "non-temporal" hint. Since we don't emulate - * caches we don't care about hints to the cache system about - * data access patterns, and handle this identically to plain - * signed offset. - */ - if (is_signed) { - /* There is no non-temporal-hint version of LDPSW */ - unallocated_encoding(s); - return; - } - postindex =3D false; - break; - case 2: /* signed offset, rn not updated */ - postindex =3D false; - break; - case 3: /* pre-index */ - postindex =3D false; - wback =3D true; - break; - } - - if (is_vector && !fp_access_check(s)) { - return; - } - - offset <<=3D (set_tag ? LOG2_TAG_GRANULE : size); - - if (rn =3D=3D 31) { + if (a->rn =3D=3D 31) { gen_check_sp_alignment(s); } =20 - dirty_addr =3D read_cpu_reg_sp(s, rn, 1); - if (!postindex) { + *dirty_addr =3D read_cpu_reg_sp(s, a->rn, 1); + if (!a->p) { + tcg_gen_addi_i64(*dirty_addr, *dirty_addr, offset); + } + + *clean_addr =3D gen_mte_checkN(s, *dirty_addr, is_store, + (a->w || a->rn !=3D 31), 2 << a->sz, mop); +} + +static void op_addr_ldstpair_post(DisasContext *s, arg_ldstpair *a, + TCGv_i64 dirty_addr, uint64_t offset) +{ + if (a->w) { + if (a->p) { + tcg_gen_addi_i64(dirty_addr, dirty_addr, offset); + } + tcg_gen_mov_i64(cpu_reg_sp(s, a->rn), dirty_addr); + } +} + +static bool trans_STP(DisasContext *s, arg_ldstpair *a) +{ + uint64_t offset =3D a->imm << a->sz; + TCGv_i64 clean_addr, dirty_addr, tcg_rt, tcg_rt2; + MemOp mop =3D finalize_memop(s, a->sz); + + op_addr_ldstpair_pre(s, a, &clean_addr, &dirty_addr, offset, true, mop= ); + tcg_rt =3D cpu_reg(s, a->rt); + tcg_rt2 =3D cpu_reg(s, a->rt2); + /* + * We built mop above for the single logical access -- rebuild it + * now for the paired operation. + * + * With LSE2, non-sign-extending pairs are treated atomically if + * aligned, and if unaligned one of the pair will be completely + * within a 16-byte block and that element will be atomic. + * Otherwise each element is separately atomic. + * In all cases, issue one operation with the correct atomicity. + * + * This treats sign-extending loads like zero-extending loads, + * since that reuses the most code below. + */ + mop =3D a->sz + 1; + if (s->align_mem) { + mop |=3D (a->sz =3D=3D 2 ? MO_ALIGN_4 : MO_ALIGN_8); + } + mop =3D finalize_memop_pair(s, mop); + if (a->sz =3D=3D 2) { + TCGv_i64 tmp =3D tcg_temp_new_i64(); + + if (s->be_data =3D=3D MO_LE) { + tcg_gen_concat32_i64(tmp, tcg_rt, tcg_rt2); + } else { + tcg_gen_concat32_i64(tmp, tcg_rt2, tcg_rt); + } + tcg_gen_qemu_st_i64(tmp, clean_addr, get_mem_index(s), mop); + } else { + TCGv_i128 tmp =3D tcg_temp_new_i128(); + + if (s->be_data =3D=3D MO_LE) { + tcg_gen_concat_i64_i128(tmp, tcg_rt, tcg_rt2); + } else { + tcg_gen_concat_i64_i128(tmp, tcg_rt2, tcg_rt); + } + tcg_gen_qemu_st_i128(tmp, clean_addr, get_mem_index(s), mop); + } + op_addr_ldstpair_post(s, a, dirty_addr, offset); + return true; +} + +static bool trans_LDP(DisasContext *s, arg_ldstpair *a) +{ + uint64_t offset =3D a->imm << a->sz; + TCGv_i64 clean_addr, dirty_addr, tcg_rt, tcg_rt2; + MemOp mop =3D finalize_memop(s, a->sz); + + op_addr_ldstpair_pre(s, a, &clean_addr, &dirty_addr, offset, false, mo= p); + tcg_rt =3D cpu_reg(s, a->rt); + tcg_rt2 =3D cpu_reg(s, a->rt2); + + /* + * We built mop above for the single logical access -- rebuild it + * now for the paired operation. + * + * With LSE2, non-sign-extending pairs are treated atomically if + * aligned, and if unaligned one of the pair will be completely + * within a 16-byte block and that element will be atomic. + * Otherwise each element is separately atomic. + * In all cases, issue one operation with the correct atomicity. + * + * This treats sign-extending loads like zero-extending loads, + * since that reuses the most code below. + */ + mop =3D a->sz + 1; + if (s->align_mem) { + mop |=3D (a->sz =3D=3D 2 ? MO_ALIGN_4 : MO_ALIGN_8); + } + mop =3D finalize_memop_pair(s, mop); + if (a->sz =3D=3D 2) { + int o2 =3D s->be_data =3D=3D MO_LE ? 32 : 0; + int o1 =3D o2 ^ 32; + + tcg_gen_qemu_ld_i64(tcg_rt, clean_addr, get_mem_index(s), mop); + if (a->sign) { + tcg_gen_sextract_i64(tcg_rt2, tcg_rt, o2, 32); + tcg_gen_sextract_i64(tcg_rt, tcg_rt, o1, 32); + } else { + tcg_gen_extract_i64(tcg_rt2, tcg_rt, o2, 32); + tcg_gen_extract_i64(tcg_rt, tcg_rt, o1, 32); + } + } else { + TCGv_i128 tmp =3D tcg_temp_new_i128(); + + tcg_gen_qemu_ld_i128(tmp, clean_addr, get_mem_index(s), mop); + if (s->be_data =3D=3D MO_LE) { + tcg_gen_extr_i128_i64(tcg_rt, tcg_rt2, tmp); + } else { + tcg_gen_extr_i128_i64(tcg_rt2, tcg_rt, tmp); + } + } + op_addr_ldstpair_post(s, a, dirty_addr, offset); + return true; +} + +static bool trans_STP_v(DisasContext *s, arg_ldstpair *a) +{ + uint64_t offset =3D a->imm << a->sz; + TCGv_i64 clean_addr, dirty_addr; + MemOp mop; + + if (!fp_access_check(s)) { + return true; + } + + /* LSE2 does not merge FP pairs; leave these as separate operations. */ + mop =3D finalize_memop_asimd(s, a->sz); + op_addr_ldstpair_pre(s, a, &clean_addr, &dirty_addr, offset, true, mop= ); + do_fp_st(s, a->rt, clean_addr, mop); + tcg_gen_addi_i64(clean_addr, clean_addr, 1 << a->sz); + do_fp_st(s, a->rt2, clean_addr, mop); + op_addr_ldstpair_post(s, a, dirty_addr, offset); + return true; +} + +static bool trans_LDP_v(DisasContext *s, arg_ldstpair *a) +{ + uint64_t offset =3D a->imm << a->sz; + TCGv_i64 clean_addr, dirty_addr; + MemOp mop; + + if (!fp_access_check(s)) { + return true; + } + + /* LSE2 does not merge FP pairs; leave these as separate operations. */ + mop =3D finalize_memop_asimd(s, a->sz); + op_addr_ldstpair_pre(s, a, &clean_addr, &dirty_addr, offset, false, mo= p); + do_fp_ld(s, a->rt, clean_addr, mop); + tcg_gen_addi_i64(clean_addr, clean_addr, 1 << a->sz); + do_fp_ld(s, a->rt2, clean_addr, mop); + op_addr_ldstpair_post(s, a, dirty_addr, offset); + return true; +} + +static bool trans_STGP(DisasContext *s, arg_ldstpair *a) +{ + TCGv_i64 clean_addr, dirty_addr, tcg_rt, tcg_rt2; + uint64_t offset =3D a->imm << LOG2_TAG_GRANULE; + MemOp mop; + TCGv_i128 tmp; + + if (!dc_isar_feature(aa64_mte_insn_reg, s)) { + return false; + } + + if (a->rn =3D=3D 31) { + gen_check_sp_alignment(s); + } + + dirty_addr =3D read_cpu_reg_sp(s, a->rn, 1); + if (!a->p) { tcg_gen_addi_i64(dirty_addr, dirty_addr, offset); } =20 - if (set_tag) { - if (!s->ata) { - /* - * TODO: We could rely on the stores below, at least for - * system mode, if we arrange to add MO_ALIGN_16. - */ - gen_helper_stg_stub(cpu_env, dirty_addr); - } else if (tb_cflags(s->base.tb) & CF_PARALLEL) { - gen_helper_stg_parallel(cpu_env, dirty_addr, dirty_addr); - } else { - gen_helper_stg(cpu_env, dirty_addr, dirty_addr); - } - } - - if (is_vector) { - mop =3D finalize_memop_asimd(s, size); - } else { - mop =3D finalize_memop(s, size); - } - clean_addr =3D gen_mte_checkN(s, dirty_addr, !is_load, - (wback || rn !=3D 31) && !set_tag, - 2 << size, mop); - - if (is_vector) { - /* LSE2 does not merge FP pairs; leave these as separate operation= s. */ - if (is_load) { - do_fp_ld(s, rt, clean_addr, mop); - } else { - do_fp_st(s, rt, clean_addr, mop); - } - tcg_gen_addi_i64(clean_addr, clean_addr, 1 << size); - if (is_load) { - do_fp_ld(s, rt2, clean_addr, mop); - } else { - do_fp_st(s, rt2, clean_addr, mop); - } - } else { - TCGv_i64 tcg_rt =3D cpu_reg(s, rt); - TCGv_i64 tcg_rt2 =3D cpu_reg(s, rt2); - + if (!s->ata) { /* - * We built mop above for the single logical access -- rebuild it - * now for the paired operation. - * - * With LSE2, non-sign-extending pairs are treated atomically if - * aligned, and if unaligned one of the pair will be completely - * within a 16-byte block and that element will be atomic. - * Otherwise each element is separately atomic. - * In all cases, issue one operation with the correct atomicity. - * - * This treats sign-extending loads like zero-extending loads, - * since that reuses the most code below. + * TODO: We could rely on the stores below, at least for + * system mode, if we arrange to add MO_ALIGN_16. */ - mop =3D size + 1; - if (s->align_mem) { - mop |=3D (size =3D=3D 2 ? MO_ALIGN_4 : MO_ALIGN_8); - } - mop =3D finalize_memop_pair(s, mop); - - if (is_load) { - if (size =3D=3D 2) { - int o2 =3D s->be_data =3D=3D MO_LE ? 32 : 0; - int o1 =3D o2 ^ 32; - - tcg_gen_qemu_ld_i64(tcg_rt, clean_addr, get_mem_index(s), = mop); - if (is_signed) { - tcg_gen_sextract_i64(tcg_rt2, tcg_rt, o2, 32); - tcg_gen_sextract_i64(tcg_rt, tcg_rt, o1, 32); - } else { - tcg_gen_extract_i64(tcg_rt2, tcg_rt, o2, 32); - tcg_gen_extract_i64(tcg_rt, tcg_rt, o1, 32); - } - } else { - TCGv_i128 tmp =3D tcg_temp_new_i128(); - - tcg_gen_qemu_ld_i128(tmp, clean_addr, get_mem_index(s), mo= p); - if (s->be_data =3D=3D MO_LE) { - tcg_gen_extr_i128_i64(tcg_rt, tcg_rt2, tmp); - } else { - tcg_gen_extr_i128_i64(tcg_rt2, tcg_rt, tmp); - } - } - } else { - if (size =3D=3D 2) { - TCGv_i64 tmp =3D tcg_temp_new_i64(); - - if (s->be_data =3D=3D MO_LE) { - tcg_gen_concat32_i64(tmp, tcg_rt, tcg_rt2); - } else { - tcg_gen_concat32_i64(tmp, tcg_rt2, tcg_rt); - } - tcg_gen_qemu_st_i64(tmp, clean_addr, get_mem_index(s), mop= ); - } else { - TCGv_i128 tmp =3D tcg_temp_new_i128(); - - if (s->be_data =3D=3D MO_LE) { - tcg_gen_concat_i64_i128(tmp, tcg_rt, tcg_rt2); - } else { - tcg_gen_concat_i64_i128(tmp, tcg_rt2, tcg_rt); - } - tcg_gen_qemu_st_i128(tmp, clean_addr, get_mem_index(s), mo= p); - } - } + gen_helper_stg_stub(cpu_env, dirty_addr); + } else if (tb_cflags(s->base.tb) & CF_PARALLEL) { + gen_helper_stg_parallel(cpu_env, dirty_addr, dirty_addr); + } else { + gen_helper_stg(cpu_env, dirty_addr, dirty_addr); } =20 - if (wback) { - if (postindex) { - tcg_gen_addi_i64(dirty_addr, dirty_addr, offset); - } - tcg_gen_mov_i64(cpu_reg_sp(s, rn), dirty_addr); + mop =3D finalize_memop(s, a->sz); + clean_addr =3D gen_mte_checkN(s, dirty_addr, true, false, 2 << a->sz, = mop); + + tcg_rt =3D cpu_reg(s, a->rt); + tcg_rt2 =3D cpu_reg(s, a->rt2); + + assert(a->sz =3D=3D 3); + + tmp =3D tcg_temp_new_i128(); + if (s->be_data =3D=3D MO_LE) { + tcg_gen_concat_i64_i128(tmp, tcg_rt, tcg_rt2); + } else { + tcg_gen_concat_i64_i128(tmp, tcg_rt2, tcg_rt); } + tcg_gen_qemu_st_i128(tmp, clean_addr, get_mem_index(s), mop); + + op_addr_ldstpair_post(s, a, dirty_addr, offset); + return true; } =20 /* @@ -4184,10 +4183,6 @@ static void disas_ldst_tag(DisasContext *s, uint32_t= insn) static void disas_ldst(DisasContext *s, uint32_t insn) { switch (extract32(insn, 24, 6)) { - case 0x28: case 0x29: - case 0x2c: case 0x2d: /* Load/store pair (all forms) */ - disas_ldst_pair(s, insn); - break; case 0x38: case 0x39: case 0x3c: case 0x3d: /* Load/store register (all forms) */ disas_ldst_reg(s, insn); --=20 2.34.1 From nobody Fri May 10 11:25:59 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1686499384; cv=none; d=zohomail.com; s=zohoarc; b=klz1v6N7Y+6nmCBmrPnJbmRmWXAdH7IPbGkADVY5mwm71jsBkWTuh6kSnVIl8AfLvxVhDQCdsJBcURXn0cjyIKSDeQbwufMLVZWLWUqo6apveeZjIKwqnInQ68fqvydQk+1NbLWtoltbSFUk20DvYy88jSEh92ovs1z+veOPICs= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1686499384; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=OAtg9LQL9ts1JABGS7gXYhJ1xEOgXCbhcvc8lEvcc64=; b=WiRAhulbuKMnnAow09DTcPAPK8Ein7on74h5Tv1xHRNF4eJXfo55l2soxn1TKvKnHEdnzg1/nJtEwDhj9Sxv0Fbc48/1eBuU/vjpl7nIc3sNldPQwVRnRoJnxiickRa0U6XxtXSWKw3mOkN280/Pz4tLzA3xG8ogk3OTaM0pO+s= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1686499384498600.738047666061; Sun, 11 Jun 2023 09:03:04 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1q8NVf-0006Ww-7U; Sun, 11 Jun 2023 12:01:43 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1q8NUp-0005wO-2x for qemu-devel@nongnu.org; Sun, 11 Jun 2023 12:00:53 -0400 Received: from mail-wr1-x42d.google.com ([2a00:1450:4864:20::42d]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1q8NUi-0000UG-Ux for qemu-devel@nongnu.org; Sun, 11 Jun 2023 12:00:50 -0400 Received: by mail-wr1-x42d.google.com with SMTP id ffacd0b85a97d-30fbf253dc7so244549f8f.0 for ; Sun, 11 Jun 2023 09:00:43 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id m9-20020a056000008900b0030ae499da59sm9923022wrx.111.2023.06.11.09.00.41 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 11 Jun 2023 09:00:41 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1686499242; x=1689091242; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=OAtg9LQL9ts1JABGS7gXYhJ1xEOgXCbhcvc8lEvcc64=; b=s2KjYWFTcGNR/c7MECLf8zO6JcAoo0q1MJblbIhGkm6Qn3fw15l9xudJ3tcDIFQ664 qpKDnnjUFfCwNFY0UVJ3xV7QtmHR1QwNckvaRxFVbJIs22jMJxLag9ulR5Y85mdM24VK r9xjhYVY0v8q5X4B3/KPPuHl50NknDQ7vHDj8foCvW3fhy0cQ2+X5deJOMDaM3s25cWf SMoDNYr9r/HXsD51avRlPAgZFrObWCEHRGke5SwwSC7JWaRIOehONjMB5rwFxl9vGhq8 0qQHRtopE1VqEWMXHVAOX3dB2rMuX+cE3Dyo5vzvsvhBBQ7Xmqbhq7D3aqJN4Ofrvw9v 5r6A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1686499242; x=1689091242; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=OAtg9LQL9ts1JABGS7gXYhJ1xEOgXCbhcvc8lEvcc64=; b=DEy7lk3vuMUJ1bX5vNgiShnqD0ZWLDz2QLkEfzvIBo3r/yWhJnStlNDH7yqJfry8us JbjqBieyFt4t7KEau3ybhbBDTOjfakMWhbx3iz6MIupKNetLw0k2ifXVHt2lTE7kxpMW AHkMNvLHD3s1hu7RjmOF86XnvnfgwYo0OCDdH4WH1DjkoHns05WqBKv0TW3Iel6jLwrM i7YjyNIKjZQ31T6d5WqXNMu2EUye3LC5oOjcGX20vIxtHe38/fgr3k9ajf64t9PK30dE BHHtslxBCqlCmAMrZlOrbPGbUSsxA75WkuE+9mmJO2Ul/FgTIkNiNtbCquv7jPYv9PXr SGlg== X-Gm-Message-State: AC+VfDztd3C6y7EWQ1d6VqXoGQNtoFmwWelJaey2znovQIdHzYBnTDSy sSF5qlwPtzBugDWvnV+SZaFwSg== X-Google-Smtp-Source: ACHHUZ579ehGWaGF8a7hTfJCJY2t/21Q11umtOYdtiO6lTzDg/PlT9rhluoQpw0OZeRWhnCvbcHRCg== X-Received: by 2002:a5d:4208:0:b0:30a:e589:68a5 with SMTP id n8-20020a5d4208000000b0030ae58968a5mr3496434wrq.29.1686499242180; Sun, 11 Jun 2023 09:00:42 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH v2 15/23] target/arm: Convert ld/st reg+imm9 insns to decodetree Date: Sun, 11 Jun 2023 17:00:24 +0100 Message-Id: <20230611160032.274823-16-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230611160032.274823-1-peter.maydell@linaro.org> References: <20230611160032.274823-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42d; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1686499384826100001 Content-Type: text/plain; charset="utf-8" Convert the load and store instructions which use a 9-bit immediate offset to decodetree. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Message-id: 20230602155223.2040685-13-peter.maydell@linaro.org --- target/arm/tcg/a64.decode | 69 +++++++++++ target/arm/tcg/translate-a64.c | 206 ++++++++++++++------------------- 2 files changed, 153 insertions(+), 122 deletions(-) diff --git a/target/arm/tcg/a64.decode b/target/arm/tcg/a64.decode index f5787919931..d55c09684a7 100644 --- a/target/arm/tcg/a64.decode +++ b/target/arm/tcg/a64.decode @@ -326,3 +326,72 @@ LDP_v 10 101 1 011 1 ....... ..... ..... ...= .. @ldstpair sz=3D4 sign=3D0 p STGP 01 101 0 001 0 ....... ..... ..... ..... @ldstpair sz=3D3 = sign=3D0 p=3D1 w=3D1 STGP 01 101 0 010 0 ....... ..... ..... ..... @ldstpair sz=3D3 = sign=3D0 p=3D0 w=3D0 STGP 01 101 0 011 0 ....... ..... ..... ..... @ldstpair sz=3D3 = sign=3D0 p=3D0 w=3D1 + +# Load/store register (unscaled immediate) +&ldst_imm rt rn imm sz sign w p unpriv ext +@ldst_imm .. ... . .. .. . imm:s9 .. rn:5 rt:5 &ldst_imm unpriv=3D0 = p=3D0 w=3D0 +@ldst_imm_pre .. ... . .. .. . imm:s9 .. rn:5 rt:5 &ldst_imm unpriv=3D0 = p=3D0 w=3D1 +@ldst_imm_post .. ... . .. .. . imm:s9 .. rn:5 rt:5 &ldst_imm unpriv=3D0 = p=3D1 w=3D1 +@ldst_imm_user .. ... . .. .. . imm:s9 .. rn:5 rt:5 &ldst_imm unpriv=3D1 = p=3D0 w=3D0 + +STR_i sz:2 111 0 00 00 0 ......... 00 ..... ..... @ldst_imm sign= =3D0 ext=3D0 +LDR_i 00 111 0 00 01 0 ......... 00 ..... ..... @ldst_imm sign= =3D0 ext=3D1 sz=3D0 +LDR_i 01 111 0 00 01 0 ......... 00 ..... ..... @ldst_imm sign= =3D0 ext=3D1 sz=3D1 +LDR_i 10 111 0 00 01 0 ......... 00 ..... ..... @ldst_imm sign= =3D0 ext=3D1 sz=3D2 +LDR_i 11 111 0 00 01 0 ......... 00 ..... ..... @ldst_imm sign= =3D0 ext=3D0 sz=3D3 +LDR_i 00 111 0 00 10 0 ......... 00 ..... ..... @ldst_imm sign= =3D1 ext=3D0 sz=3D0 +LDR_i 01 111 0 00 10 0 ......... 00 ..... ..... @ldst_imm sign= =3D1 ext=3D0 sz=3D1 +LDR_i 10 111 0 00 10 0 ......... 00 ..... ..... @ldst_imm sign= =3D1 ext=3D0 sz=3D2 +LDR_i 00 111 0 00 11 0 ......... 00 ..... ..... @ldst_imm sign= =3D1 ext=3D1 sz=3D0 +LDR_i 01 111 0 00 11 0 ......... 00 ..... ..... @ldst_imm sign= =3D1 ext=3D1 sz=3D1 + +STR_i sz:2 111 0 00 00 0 ......... 01 ..... ..... @ldst_imm_post= sign=3D0 ext=3D0 +LDR_i 00 111 0 00 01 0 ......... 01 ..... ..... @ldst_imm_post s= ign=3D0 ext=3D1 sz=3D0 +LDR_i 01 111 0 00 01 0 ......... 01 ..... ..... @ldst_imm_post s= ign=3D0 ext=3D1 sz=3D1 +LDR_i 10 111 0 00 01 0 ......... 01 ..... ..... @ldst_imm_post s= ign=3D0 ext=3D1 sz=3D2 +LDR_i 11 111 0 00 01 0 ......... 01 ..... ..... @ldst_imm_post s= ign=3D0 ext=3D0 sz=3D3 +LDR_i 00 111 0 00 10 0 ......... 01 ..... ..... @ldst_imm_post s= ign=3D1 ext=3D0 sz=3D0 +LDR_i 01 111 0 00 10 0 ......... 01 ..... ..... @ldst_imm_post s= ign=3D1 ext=3D0 sz=3D1 +LDR_i 10 111 0 00 10 0 ......... 01 ..... ..... @ldst_imm_post s= ign=3D1 ext=3D0 sz=3D2 +LDR_i 00 111 0 00 11 0 ......... 01 ..... ..... @ldst_imm_post s= ign=3D1 ext=3D1 sz=3D0 +LDR_i 01 111 0 00 11 0 ......... 01 ..... ..... @ldst_imm_post s= ign=3D1 ext=3D1 sz=3D1 + +STR_i sz:2 111 0 00 00 0 ......... 10 ..... ..... @ldst_imm_user= sign=3D0 ext=3D0 +LDR_i 00 111 0 00 01 0 ......... 10 ..... ..... @ldst_imm_user s= ign=3D0 ext=3D1 sz=3D0 +LDR_i 01 111 0 00 01 0 ......... 10 ..... ..... @ldst_imm_user s= ign=3D0 ext=3D1 sz=3D1 +LDR_i 10 111 0 00 01 0 ......... 10 ..... ..... @ldst_imm_user s= ign=3D0 ext=3D1 sz=3D2 +LDR_i 11 111 0 00 01 0 ......... 10 ..... ..... @ldst_imm_user s= ign=3D0 ext=3D0 sz=3D3 +LDR_i 00 111 0 00 10 0 ......... 10 ..... ..... @ldst_imm_user s= ign=3D1 ext=3D0 sz=3D0 +LDR_i 01 111 0 00 10 0 ......... 10 ..... ..... @ldst_imm_user s= ign=3D1 ext=3D0 sz=3D1 +LDR_i 10 111 0 00 10 0 ......... 10 ..... ..... @ldst_imm_user s= ign=3D1 ext=3D0 sz=3D2 +LDR_i 00 111 0 00 11 0 ......... 10 ..... ..... @ldst_imm_user s= ign=3D1 ext=3D1 sz=3D0 +LDR_i 01 111 0 00 11 0 ......... 10 ..... ..... @ldst_imm_user s= ign=3D1 ext=3D1 sz=3D1 + +STR_i sz:2 111 0 00 00 0 ......... 11 ..... ..... @ldst_imm_pre = sign=3D0 ext=3D0 +LDR_i 00 111 0 00 01 0 ......... 11 ..... ..... @ldst_imm_pre si= gn=3D0 ext=3D1 sz=3D0 +LDR_i 01 111 0 00 01 0 ......... 11 ..... ..... @ldst_imm_pre si= gn=3D0 ext=3D1 sz=3D1 +LDR_i 10 111 0 00 01 0 ......... 11 ..... ..... @ldst_imm_pre si= gn=3D0 ext=3D1 sz=3D2 +LDR_i 11 111 0 00 01 0 ......... 11 ..... ..... @ldst_imm_pre si= gn=3D0 ext=3D0 sz=3D3 +LDR_i 00 111 0 00 10 0 ......... 11 ..... ..... @ldst_imm_pre si= gn=3D1 ext=3D0 sz=3D0 +LDR_i 01 111 0 00 10 0 ......... 11 ..... ..... @ldst_imm_pre si= gn=3D1 ext=3D0 sz=3D1 +LDR_i 10 111 0 00 10 0 ......... 11 ..... ..... @ldst_imm_pre si= gn=3D1 ext=3D0 sz=3D2 +LDR_i 00 111 0 00 11 0 ......... 11 ..... ..... @ldst_imm_pre si= gn=3D1 ext=3D1 sz=3D0 +LDR_i 01 111 0 00 11 0 ......... 11 ..... ..... @ldst_imm_pre si= gn=3D1 ext=3D1 sz=3D1 + +# PRFM : prefetch memory: a no-op for QEMU +NOP 11 111 0 00 10 0 --------- 00 ----- ----- + +STR_v_i sz:2 111 1 00 00 0 ......... 00 ..... ..... @ldst_imm sign= =3D0 ext=3D0 +STR_v_i 00 111 1 00 10 0 ......... 00 ..... ..... @ldst_imm sign= =3D0 ext=3D0 sz=3D4 +LDR_v_i sz:2 111 1 00 01 0 ......... 00 ..... ..... @ldst_imm sign= =3D0 ext=3D0 +LDR_v_i 00 111 1 00 11 0 ......... 00 ..... ..... @ldst_imm sign= =3D0 ext=3D0 sz=3D4 + +STR_v_i sz:2 111 1 00 00 0 ......... 01 ..... ..... @ldst_imm_post= sign=3D0 ext=3D0 +STR_v_i 00 111 1 00 10 0 ......... 01 ..... ..... @ldst_imm_post s= ign=3D0 ext=3D0 sz=3D4 +LDR_v_i sz:2 111 1 00 01 0 ......... 01 ..... ..... @ldst_imm_post= sign=3D0 ext=3D0 +LDR_v_i 00 111 1 00 11 0 ......... 01 ..... ..... @ldst_imm_post s= ign=3D0 ext=3D0 sz=3D4 + +STR_v_i sz:2 111 1 00 00 0 ......... 11 ..... ..... @ldst_imm_pre = sign=3D0 ext=3D0 +STR_v_i 00 111 1 00 10 0 ......... 11 ..... ..... @ldst_imm_pre si= gn=3D0 ext=3D0 sz=3D4 +LDR_v_i sz:2 111 1 00 01 0 ......... 11 ..... ..... @ldst_imm_pre = sign=3D0 ext=3D0 +LDR_v_i 00 111 1 00 11 0 ......... 11 ..... ..... @ldst_imm_pre si= gn=3D0 ext=3D0 sz=3D4 diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c index 8b8c9939013..4cabdadde41 100644 --- a/target/arm/tcg/translate-a64.c +++ b/target/arm/tcg/translate-a64.c @@ -3040,134 +3040,101 @@ static bool trans_STGP(DisasContext *s, arg_ldstp= air *a) return true; } =20 -/* - * Load/store (immediate post-indexed) - * Load/store (immediate pre-indexed) - * Load/store (unscaled immediate) - * - * 31 30 29 27 26 25 24 23 22 21 20 12 11 10 9 5 4 0 - * +----+-------+---+-----+-----+---+--------+-----+------+------+ - * |size| 1 1 1 | V | 0 0 | opc | 0 | imm9 | idx | Rn | Rt | - * +----+-------+---+-----+-----+---+--------+-----+------+------+ - * - * idx =3D 01 -> post-indexed, 11 pre-indexed, 00 unscaled imm. (no writeb= ack) - 10 -> unprivileged - * V =3D 0 -> non-vector - * size: 00 -> 8 bit, 01 -> 16 bit, 10 -> 32 bit, 11 -> 64bit - * opc: 00 -> store, 01 -> loadu, 10 -> loads 64, 11 -> loads 32 - */ -static void disas_ldst_reg_imm9(DisasContext *s, uint32_t insn, - int opc, - int size, - int rt, - bool is_vector) +static void op_addr_ldst_imm_pre(DisasContext *s, arg_ldst_imm *a, + TCGv_i64 *clean_addr, TCGv_i64 *dirty_add= r, + uint64_t offset, bool is_store, MemOp mop) { - int rn =3D extract32(insn, 5, 5); - int imm9 =3D sextract32(insn, 12, 9); - int idx =3D extract32(insn, 10, 2); - bool is_signed =3D false; - bool is_store =3D false; - bool is_extended =3D false; - bool is_unpriv =3D (idx =3D=3D 2); - bool iss_valid; - bool post_index; - bool writeback; int memidx; - MemOp memop; - TCGv_i64 clean_addr, dirty_addr; =20 - if (is_vector) { - size |=3D (opc & 2) << 1; - if (size > 4 || is_unpriv) { - unallocated_encoding(s); - return; - } - is_store =3D ((opc & 1) =3D=3D 0); - if (!fp_access_check(s)) { - return; - } - memop =3D finalize_memop_asimd(s, size); - } else { - if (size =3D=3D 3 && opc =3D=3D 2) { - /* PRFM - prefetch */ - if (idx !=3D 0) { - unallocated_encoding(s); - return; - } - return; - } - if (opc =3D=3D 3 && size > 1) { - unallocated_encoding(s); - return; - } - is_store =3D (opc =3D=3D 0); - is_signed =3D !is_store && extract32(opc, 1, 1); - is_extended =3D (size < 3) && extract32(opc, 0, 1); - memop =3D finalize_memop(s, size + is_signed * MO_SIGN); - } - - switch (idx) { - case 0: - case 2: - post_index =3D false; - writeback =3D false; - break; - case 1: - post_index =3D true; - writeback =3D true; - break; - case 3: - post_index =3D false; - writeback =3D true; - break; - default: - g_assert_not_reached(); - } - - iss_valid =3D !is_vector && !writeback; - - if (rn =3D=3D 31) { + if (a->rn =3D=3D 31) { gen_check_sp_alignment(s); } =20 - dirty_addr =3D read_cpu_reg_sp(s, rn, 1); - if (!post_index) { - tcg_gen_addi_i64(dirty_addr, dirty_addr, imm9); + *dirty_addr =3D read_cpu_reg_sp(s, a->rn, 1); + if (!a->p) { + tcg_gen_addi_i64(*dirty_addr, *dirty_addr, offset); } + memidx =3D a->unpriv ? get_a64_user_mem_index(s) : get_mem_index(s); + *clean_addr =3D gen_mte_check1_mmuidx(s, *dirty_addr, is_store, + a->w || a->rn !=3D 31, + mop, a->unpriv, memidx); +} =20 - memidx =3D is_unpriv ? get_a64_user_mem_index(s) : get_mem_index(s); - - clean_addr =3D gen_mte_check1_mmuidx(s, dirty_addr, is_store, - writeback || rn !=3D 31, - memop, is_unpriv, memidx); - - if (is_vector) { - if (is_store) { - do_fp_st(s, rt, clean_addr, memop); - } else { - do_fp_ld(s, rt, clean_addr, memop); - } - } else { - TCGv_i64 tcg_rt =3D cpu_reg(s, rt); - bool iss_sf =3D disas_ldst_compute_iss_sf(size, is_signed, opc); - - if (is_store) { - do_gpr_st_memidx(s, tcg_rt, clean_addr, memop, memidx, - iss_valid, rt, iss_sf, false); - } else { - do_gpr_ld_memidx(s, tcg_rt, clean_addr, memop, - is_extended, memidx, - iss_valid, rt, iss_sf, false); +static void op_addr_ldst_imm_post(DisasContext *s, arg_ldst_imm *a, + TCGv_i64 dirty_addr, uint64_t offset) +{ + if (a->w) { + if (a->p) { + tcg_gen_addi_i64(dirty_addr, dirty_addr, offset); } + tcg_gen_mov_i64(cpu_reg_sp(s, a->rn), dirty_addr); } +} =20 - if (writeback) { - TCGv_i64 tcg_rn =3D cpu_reg_sp(s, rn); - if (post_index) { - tcg_gen_addi_i64(dirty_addr, dirty_addr, imm9); - } - tcg_gen_mov_i64(tcg_rn, dirty_addr); +static bool trans_STR_i(DisasContext *s, arg_ldst_imm *a) +{ + bool iss_sf, iss_valid =3D !a->w; + TCGv_i64 clean_addr, dirty_addr, tcg_rt; + int memidx =3D a->unpriv ? get_a64_user_mem_index(s) : get_mem_index(s= ); + MemOp mop =3D finalize_memop(s, a->sz + a->sign * MO_SIGN); + + op_addr_ldst_imm_pre(s, a, &clean_addr, &dirty_addr, a->imm, true, mop= ); + + tcg_rt =3D cpu_reg(s, a->rt); + iss_sf =3D ldst_iss_sf(a->sz, a->sign, a->ext); + + do_gpr_st_memidx(s, tcg_rt, clean_addr, mop, memidx, + iss_valid, a->rt, iss_sf, false); + op_addr_ldst_imm_post(s, a, dirty_addr, a->imm); + return true; +} + +static bool trans_LDR_i(DisasContext *s, arg_ldst_imm *a) +{ + bool iss_sf, iss_valid =3D !a->w; + TCGv_i64 clean_addr, dirty_addr, tcg_rt; + int memidx =3D a->unpriv ? get_a64_user_mem_index(s) : get_mem_index(s= ); + MemOp mop =3D finalize_memop(s, a->sz + a->sign * MO_SIGN); + + op_addr_ldst_imm_pre(s, a, &clean_addr, &dirty_addr, a->imm, false, mo= p); + + tcg_rt =3D cpu_reg(s, a->rt); + iss_sf =3D ldst_iss_sf(a->sz, a->sign, a->ext); + + do_gpr_ld_memidx(s, tcg_rt, clean_addr, mop, + a->ext, memidx, iss_valid, a->rt, iss_sf, false); + op_addr_ldst_imm_post(s, a, dirty_addr, a->imm); + return true; +} + +static bool trans_STR_v_i(DisasContext *s, arg_ldst_imm *a) +{ + TCGv_i64 clean_addr, dirty_addr; + MemOp mop; + + if (!fp_access_check(s)) { + return true; } + mop =3D finalize_memop_asimd(s, a->sz); + op_addr_ldst_imm_pre(s, a, &clean_addr, &dirty_addr, a->imm, true, mop= ); + do_fp_st(s, a->rt, clean_addr, mop); + op_addr_ldst_imm_post(s, a, dirty_addr, a->imm); + return true; +} + +static bool trans_LDR_v_i(DisasContext *s, arg_ldst_imm *a) +{ + TCGv_i64 clean_addr, dirty_addr; + MemOp mop; + + if (!fp_access_check(s)) { + return true; + } + mop =3D finalize_memop_asimd(s, a->sz); + op_addr_ldst_imm_pre(s, a, &clean_addr, &dirty_addr, a->imm, false, mo= p); + do_fp_ld(s, a->rt, clean_addr, mop); + op_addr_ldst_imm_post(s, a, dirty_addr, a->imm); + return true; } =20 /* @@ -3640,12 +3607,7 @@ static void disas_ldst_reg(DisasContext *s, uint32_t= insn) switch (extract32(insn, 24, 2)) { case 0: if (extract32(insn, 21, 1) =3D=3D 0) { - /* Load/store register (unscaled immediate) - * Load/store immediate pre/post-indexed - * Load/store register unprivileged - */ - disas_ldst_reg_imm9(s, insn, opc, size, rt, is_vector); - return; + break; } switch (extract32(insn, 10, 2)) { case 0: --=20 2.34.1 From nobody Fri May 10 11:25:59 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1686499409; cv=none; d=zohomail.com; s=zohoarc; b=g5gS3wOZ+Hs/cC5Mj2EBIYJTvfOXAhwA7qSkVlB2N17hQvq55Gfq+wSRFOGVbh4ISnM3/d3x1vIQcbEqeBvpuNQOe0vvGZAer8/LS1AfDsbSLbO8C1BEL148wqheaLCU73jSy1sDlQ8fcc9GZnlQ7I+4HCUT86YUzOh/ndcWcjg= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1686499409; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=oJIgChC16XW2w2F+7O8jEKJMEfu8u6OYMg1OR7BVh28=; b=VTsnB3+Uffyrvfze6RxZ540gTUqbsCUBh/iz8ZIM7aCHXGechR9SPK9CUj07VcJdyfPvmgyo6q/k33T8ut+zyu7k0FIJbuczQssyQnCN5dgP6tmpyoFJmSb9CByBTYt1Pjiq4XLklQFN751cOIkOr/Am5rTLg5nT1FtRFXqLwI0= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1686499409795840.5578861598185; Sun, 11 Jun 2023 09:03:29 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1q8NVm-0006kM-SU; Sun, 11 Jun 2023 12:01:50 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1q8NUo-0005vt-BG for qemu-devel@nongnu.org; Sun, 11 Jun 2023 12:00:52 -0400 Received: from mail-wr1-x432.google.com ([2a00:1450:4864:20::432]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1q8NUi-0000UQ-Vn for qemu-devel@nongnu.org; Sun, 11 Jun 2023 12:00:49 -0400 Received: by mail-wr1-x432.google.com with SMTP id ffacd0b85a97d-30ae95c4e75so3440925f8f.2 for ; Sun, 11 Jun 2023 09:00:43 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id m9-20020a056000008900b0030ae499da59sm9923022wrx.111.2023.06.11.09.00.42 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 11 Jun 2023 09:00:42 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1686499242; x=1689091242; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=oJIgChC16XW2w2F+7O8jEKJMEfu8u6OYMg1OR7BVh28=; b=mbwAZKujyQJePHrSKKzPrhn7BxUcT0TjONhTQzBDWL4RUALWlpsaehYh+TWDTs1Hyv aVhmpsleT21QhWOT3YFJUXsyy4r8g6PjF00p4KTuRyI7wZEQmIOr1zUMdC80BqXRRLGA 77OfIr9I69xWe0m7zYuaWjpGgG+2OeT0WTm2Y/qZc4fCEudcroMH1x4T+STlwGZHQNkG kl6tFU+/6YTeoOzfqEFB1nnHLlqhHqtCzP35G/IdpvWq+6fTBFWP8WtRYKbvL94c2HWQ SsmnrIfHK8c2TW2NNWnZ9UhHjXWIVXQhmm2YevdUQDWRF5STR9oP2+8txBmPbKRlQC/4 BxyQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1686499242; x=1689091242; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=oJIgChC16XW2w2F+7O8jEKJMEfu8u6OYMg1OR7BVh28=; b=TjupjdVlMOje1ytfC3+ZxMt5povn1VnuTz4a8WXnxExWQ8stJQGSfABQcivKVBT9Sf EwHPEKc9NXl2dOUIQMOH9KuEkN2UibQALQqOnMEgAMwpbTrDatDIpKtGrjavQstFND5h EghuTYoa56fmiJTKY/jfwPRnpiY4ds5XMwebAuH88bcm2q0Qs9Tl2vH9xv6QCQ8VZY9S vSkqooLgBPY+HBq8Z79WYoXLM/h9hjEesi+xX7TCDw714wOFS7/4/FH2QIU3FiH3VNfh /nKkYFN1c1PKshs42gJx3gfX4Mp2aMpytzogSVlFiAPsDFn6sVHQj+t9VyG+e+WxRAz0 ZYIQ== X-Gm-Message-State: AC+VfDxnmHNJxqvgCl/IRrykscLa34VBT1wUpUQeZ7xvEwreRwWPTrAh Hfwx57EaHsh8A+jHnEwvzucdFPCrccWGfGGtcNE= X-Google-Smtp-Source: ACHHUZ4j8hAHTmaFcVm1rRt5aXivyCCLK4A1xjsc3LOhVmArdzS9MtbOQv0S1bkqmGl/TMr3GXqU9Q== X-Received: by 2002:adf:f48a:0:b0:30f:c27c:a36d with SMTP id l10-20020adff48a000000b0030fc27ca36dmr121940wro.69.1686499242678; Sun, 11 Jun 2023 09:00:42 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH v2 16/23] target/arm: Convert LDR/STR with 12-bit immediate to decodetree Date: Sun, 11 Jun 2023 17:00:25 +0100 Message-Id: <20230611160032.274823-17-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230611160032.274823-1-peter.maydell@linaro.org> References: <20230611160032.274823-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::432; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x432.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1686499410998100003 Content-Type: text/plain; charset="utf-8" Convert the LDR and STR instructions which use a 12-bit immediate offset to decodetree. We can reuse the existing LDR and STR trans functions for these. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Message-id: 20230602155223.2040685-14-peter.maydell@linaro.org --- target/arm/tcg/a64.decode | 25 ++++++++ target/arm/tcg/translate-a64.c | 104 +++++---------------------------- 2 files changed, 41 insertions(+), 88 deletions(-) diff --git a/target/arm/tcg/a64.decode b/target/arm/tcg/a64.decode index d55c09684a7..d6b31c10838 100644 --- a/target/arm/tcg/a64.decode +++ b/target/arm/tcg/a64.decode @@ -395,3 +395,28 @@ STR_v_i sz:2 111 1 00 00 0 ......... 11 ..... = ..... @ldst_imm_pre sign=3D0 STR_v_i 00 111 1 00 10 0 ......... 11 ..... ..... @ldst_imm_pre si= gn=3D0 ext=3D0 sz=3D4 LDR_v_i sz:2 111 1 00 01 0 ......... 11 ..... ..... @ldst_imm_pre = sign=3D0 ext=3D0 LDR_v_i 00 111 1 00 11 0 ......... 11 ..... ..... @ldst_imm_pre si= gn=3D0 ext=3D0 sz=3D4 + +# Load/store with an unsigned 12 bit immediate, which is scaled by the +# element size. The function gets the sz:imm and returns the scaled immedi= ate. +%uimm_scaled 10:12 sz:3 !function=3Duimm_scaled + +@ldst_uimm .. ... . .. .. ............ rn:5 rt:5 &ldst_imm unpriv=3D0= p=3D0 w=3D0 imm=3D%uimm_scaled + +STR_i sz:2 111 0 01 00 ............ ..... ..... @ldst_uimm sign= =3D0 ext=3D0 +LDR_i 00 111 0 01 01 ............ ..... ..... @ldst_uimm sign=3D= 0 ext=3D1 sz=3D0 +LDR_i 01 111 0 01 01 ............ ..... ..... @ldst_uimm sign=3D= 0 ext=3D1 sz=3D1 +LDR_i 10 111 0 01 01 ............ ..... ..... @ldst_uimm sign=3D= 0 ext=3D1 sz=3D2 +LDR_i 11 111 0 01 01 ............ ..... ..... @ldst_uimm sign=3D= 0 ext=3D0 sz=3D3 +LDR_i 00 111 0 01 10 ............ ..... ..... @ldst_uimm sign=3D= 1 ext=3D0 sz=3D0 +LDR_i 01 111 0 01 10 ............ ..... ..... @ldst_uimm sign=3D= 1 ext=3D0 sz=3D1 +LDR_i 10 111 0 01 10 ............ ..... ..... @ldst_uimm sign=3D= 1 ext=3D0 sz=3D2 +LDR_i 00 111 0 01 11 ............ ..... ..... @ldst_uimm sign=3D= 1 ext=3D1 sz=3D0 +LDR_i 01 111 0 01 11 ............ ..... ..... @ldst_uimm sign=3D= 1 ext=3D1 sz=3D1 + +# PRFM +NOP 11 111 0 01 10 ------------ ----- ----- + +STR_v_i sz:2 111 1 01 00 ............ ..... ..... @ldst_uimm sign= =3D0 ext=3D0 +STR_v_i 00 111 1 01 10 ............ ..... ..... @ldst_uimm sign=3D= 0 ext=3D0 sz=3D4 +LDR_v_i sz:2 111 1 01 01 ............ ..... ..... @ldst_uimm sign= =3D0 ext=3D0 +LDR_v_i 00 111 1 01 11 ............ ..... ..... @ldst_uimm sign=3D= 0 ext=3D0 sz=3D4 diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c index 4cabdadde41..e1936c7c246 100644 --- a/target/arm/tcg/translate-a64.c +++ b/target/arm/tcg/translate-a64.c @@ -46,6 +46,22 @@ enum a64_shift_type { A64_SHIFT_TYPE_ROR =3D 3 }; =20 +/* + * Helpers for extracting complex instruction fields + */ + +/* + * For load/store with an unsigned 12 bit immediate scaled by the element + * size. The input has the immediate field in bits [14:3] and the element + * size in [2:0]. + */ +static int uimm_scaled(DisasContext *s, int x) +{ + unsigned imm =3D x >> 3; + unsigned scale =3D extract32(x, 0, 3); + return imm << scale; +} + /* * Include the generated decoders. */ @@ -3237,91 +3253,6 @@ static void disas_ldst_reg_roffset(DisasContext *s, = uint32_t insn, } } =20 -/* - * Load/store (unsigned immediate) - * - * 31 30 29 27 26 25 24 23 22 21 10 9 5 - * +----+-------+---+-----+-----+------------+-------+------+ - * |size| 1 1 1 | V | 0 1 | opc | imm12 | Rn | Rt | - * +----+-------+---+-----+-----+------------+-------+------+ - * - * For non-vector: - * size: 00-> byte, 01 -> 16 bit, 10 -> 32bit, 11 -> 64bit - * opc: 00 -> store, 01 -> loadu, 10 -> loads 64, 11 -> loads 32 - * For vector: - * size is opc<1>:size<1:0> so 100 -> 128 bit; 110 and 111 unallocated - * opc<0>: 0 -> store, 1 -> load - * Rn: base address register (inc SP) - * Rt: target register - */ -static void disas_ldst_reg_unsigned_imm(DisasContext *s, uint32_t insn, - int opc, - int size, - int rt, - bool is_vector) -{ - int rn =3D extract32(insn, 5, 5); - unsigned int imm12 =3D extract32(insn, 10, 12); - unsigned int offset; - TCGv_i64 clean_addr, dirty_addr; - bool is_store; - bool is_signed =3D false; - bool is_extended =3D false; - MemOp memop; - - if (is_vector) { - size |=3D (opc & 2) << 1; - if (size > 4) { - unallocated_encoding(s); - return; - } - is_store =3D !extract32(opc, 0, 1); - if (!fp_access_check(s)) { - return; - } - memop =3D finalize_memop_asimd(s, size); - } else { - if (size =3D=3D 3 && opc =3D=3D 2) { - /* PRFM - prefetch */ - return; - } - if (opc =3D=3D 3 && size > 1) { - unallocated_encoding(s); - return; - } - is_store =3D (opc =3D=3D 0); - is_signed =3D !is_store && extract32(opc, 1, 1); - is_extended =3D (size < 3) && extract32(opc, 0, 1); - memop =3D finalize_memop(s, size + is_signed * MO_SIGN); - } - - if (rn =3D=3D 31) { - gen_check_sp_alignment(s); - } - dirty_addr =3D read_cpu_reg_sp(s, rn, 1); - offset =3D imm12 << size; - tcg_gen_addi_i64(dirty_addr, dirty_addr, offset); - - clean_addr =3D gen_mte_check1(s, dirty_addr, is_store, rn !=3D 31, mem= op); - - if (is_vector) { - if (is_store) { - do_fp_st(s, rt, clean_addr, memop); - } else { - do_fp_ld(s, rt, clean_addr, memop); - } - } else { - TCGv_i64 tcg_rt =3D cpu_reg(s, rt); - bool iss_sf =3D disas_ldst_compute_iss_sf(size, is_signed, opc); - if (is_store) { - do_gpr_st(s, tcg_rt, clean_addr, memop, true, rt, iss_sf, fals= e); - } else { - do_gpr_ld(s, tcg_rt, clean_addr, memop, - is_extended, true, rt, iss_sf, false); - } - } -} - /* Atomic memory operations * * 31 30 27 26 24 22 21 16 15 12 10 5 0 @@ -3621,9 +3552,6 @@ static void disas_ldst_reg(DisasContext *s, uint32_t = insn) return; } break; - case 1: - disas_ldst_reg_unsigned_imm(s, insn, opc, size, rt, is_vector); - return; } unallocated_encoding(s); } --=20 2.34.1 From nobody Fri May 10 11:25:59 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id m9-20020a056000008900b0030ae499da59sm9923022wrx.111.2023.06.11.09.00.42 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 11 Jun 2023 09:00:42 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1686499243; x=1689091243; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=L/WClOmRe7ZqC6CcCm7m1pNSLACFLdzYSCXTc15BbAs=; b=uUo6tIr9qAAHR0PMVFXpG0ELF2wSp8bSWyIy6xdwV4UGKACECpTcWeuo18NwyboXSh yfcT7oeu9JFmjhvMrB1QAkENGOtXQImsMOMC0hF2NQXwSkAqTGJkEOd/kQkAReeMCa53 XbEspJCdek5KX+wZ4zSSaK7ullBazzwQT/YHcqGhzUfrINbx7jX75R6YKtYXdVIaDjx1 52hvc0inrwcisO0y8x7l3/VQD83NZTvLwuk4RwNa+oETNmaUBYdXDg+NmOWjv5zgsqKW NcPDrWfvNmzRwNzuK40NwHhae+sEnuKI2d6Uie2nOkBhdrt/vP/VzbipeeLv56VSWJYI CAUQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1686499243; x=1689091243; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=L/WClOmRe7ZqC6CcCm7m1pNSLACFLdzYSCXTc15BbAs=; b=NKfH0h4W1lsPyPzSmGY+yr+mltDXt3SOjbzsGajEM3tGlp3YiJOh8zdAEa4zVHZRyV XS6FqKz0ROYQdaD0TwuzL7pteYCA3athUrlDOA8COC00cTiW/2tYCdmS/Bty4ZRGePpC EaQ1G8d3iFXHeNuRfmO8KeYG28h3rImDW3+hP7qABCdXz3Xo9nprXhX25Sp6NJz4YMqg 9yiEKdFuRTyd7ZORP3cm67P2BWDw0wUUG6+TNUiNcrm+rD7c6k605+w8lPGBiX73DEGt oGgosnXKFIXF00KE5u+kIzwRimx57NlX0OhKv/Wi/4TutkFP64OA6B5waJeUJf7cmVmB StTg== X-Gm-Message-State: AC+VfDyzi+E9ngUDKc6IGH+tmJQzTIogc7zJoaxxXbnIqSYVC1QzpEO5 KnBycaHwP/QgiBbG3YcH4WT7wg== X-Google-Smtp-Source: ACHHUZ7/UxvWpxiYPbDsSB5JoWoyEGZKjPTkL4tVGl+m4vsXSkQ1Sch8FawkBLC3qBb2ZNAkxF1TNA== X-Received: by 2002:a5d:50c2:0:b0:309:303b:3dc5 with SMTP id f2-20020a5d50c2000000b00309303b3dc5mr3050531wrt.7.1686499243280; Sun, 11 Jun 2023 09:00:43 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH v2 17/23] target/arm: Convert LDR/STR reg+reg to decodetree Date: Sun, 11 Jun 2023 17:00:26 +0100 Message-Id: <20230611160032.274823-18-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230611160032.274823-1-peter.maydell@linaro.org> References: <20230611160032.274823-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::432; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x432.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1686499399326100005 Content-Type: text/plain; charset="utf-8" Convert the LDR and STR instructions which take a register plus register offset to decodetree. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Message-id: 20230602155223.2040685-15-peter.maydell@linaro.org --- target/arm/tcg/a64.decode | 22 +++++ target/arm/tcg/translate-a64.c | 173 +++++++++++++++------------------ 2 files changed, 103 insertions(+), 92 deletions(-) diff --git a/target/arm/tcg/a64.decode b/target/arm/tcg/a64.decode index d6b31c10838..5c086d6af6d 100644 --- a/target/arm/tcg/a64.decode +++ b/target/arm/tcg/a64.decode @@ -420,3 +420,25 @@ STR_v_i sz:2 111 1 01 00 ............ ..... ..= ... @ldst_uimm sign=3D0 ext=3D STR_v_i 00 111 1 01 10 ............ ..... ..... @ldst_uimm sign=3D= 0 ext=3D0 sz=3D4 LDR_v_i sz:2 111 1 01 01 ............ ..... ..... @ldst_uimm sign= =3D0 ext=3D0 LDR_v_i 00 111 1 01 11 ............ ..... ..... @ldst_uimm sign=3D= 0 ext=3D0 sz=3D4 + +# Load/store with register offset +&ldst rm rn rt sign ext sz opt s +@ldst .. ... . .. .. . rm:5 opt:3 s:1 .. rn:5 rt:5 &ldst +STR sz:2 111 0 00 00 1 ..... ... . 10 ..... ..... @ldst sign= =3D0 ext=3D0 +LDR 00 111 0 00 01 1 ..... ... . 10 ..... ..... @ldst sign=3D0= ext=3D1 sz=3D0 +LDR 01 111 0 00 01 1 ..... ... . 10 ..... ..... @ldst sign=3D0= ext=3D1 sz=3D1 +LDR 10 111 0 00 01 1 ..... ... . 10 ..... ..... @ldst sign=3D0= ext=3D1 sz=3D2 +LDR 11 111 0 00 01 1 ..... ... . 10 ..... ..... @ldst sign=3D0= ext=3D0 sz=3D3 +LDR 00 111 0 00 10 1 ..... ... . 10 ..... ..... @ldst sign=3D1= ext=3D0 sz=3D0 +LDR 01 111 0 00 10 1 ..... ... . 10 ..... ..... @ldst sign=3D1= ext=3D0 sz=3D1 +LDR 10 111 0 00 10 1 ..... ... . 10 ..... ..... @ldst sign=3D1= ext=3D0 sz=3D2 +LDR 00 111 0 00 11 1 ..... ... . 10 ..... ..... @ldst sign=3D1= ext=3D1 sz=3D0 +LDR 01 111 0 00 11 1 ..... ... . 10 ..... ..... @ldst sign=3D1= ext=3D1 sz=3D1 + +# PRFM +NOP 11 111 0 00 10 1 ----- -1- - 10 ----- ----- + +STR_v sz:2 111 1 00 00 1 ..... ... . 10 ..... ..... @ldst sign= =3D0 ext=3D0 +STR_v 00 111 1 00 10 1 ..... ... . 10 ..... ..... @ldst sign=3D0= ext=3D0 sz=3D4 +LDR_v sz:2 111 1 00 01 1 ..... ... . 10 ..... ..... @ldst sign= =3D0 ext=3D0 +LDR_v 00 111 1 00 11 1 ..... ... . 10 ..... ..... @ldst sign=3D0= ext=3D0 sz=3D4 diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c index e1936c7c246..3d161169411 100644 --- a/target/arm/tcg/translate-a64.c +++ b/target/arm/tcg/translate-a64.c @@ -3153,104 +3153,95 @@ static bool trans_LDR_v_i(DisasContext *s, arg_lds= t_imm *a) return true; } =20 -/* - * Load/store (register offset) - * - * 31 30 29 27 26 25 24 23 22 21 20 16 15 13 12 11 10 9 5 4 0 - * +----+-------+---+-----+-----+---+------+-----+--+-----+----+----+ - * |size| 1 1 1 | V | 0 0 | opc | 1 | Rm | opt | S| 1 0 | Rn | Rt | - * +----+-------+---+-----+-----+---+------+-----+--+-----+----+----+ - * - * For non-vector: - * size: 00-> byte, 01 -> 16 bit, 10 -> 32bit, 11 -> 64bit - * opc: 00 -> store, 01 -> loadu, 10 -> loads 64, 11 -> loads 32 - * For vector: - * size is opc<1>:size<1:0> so 100 -> 128 bit; 110 and 111 unallocated - * opc<0>: 0 -> store, 1 -> load - * V: 1 -> vector/simd - * opt: extend encoding (see DecodeRegExtend) - * S: if S=3D1 then scale (essentially index by sizeof(size)) - * Rt: register to transfer into/out of - * Rn: address register or SP for base - * Rm: offset register or ZR for offset - */ -static void disas_ldst_reg_roffset(DisasContext *s, uint32_t insn, - int opc, - int size, - int rt, - bool is_vector) +static void op_addr_ldst_pre(DisasContext *s, arg_ldst *a, + TCGv_i64 *clean_addr, TCGv_i64 *dirty_addr, + bool is_store, MemOp memop) { - int rn =3D extract32(insn, 5, 5); - int shift =3D extract32(insn, 12, 1); - int rm =3D extract32(insn, 16, 5); - int opt =3D extract32(insn, 13, 3); - bool is_signed =3D false; - bool is_store =3D false; - bool is_extended =3D false; - TCGv_i64 tcg_rm, clean_addr, dirty_addr; - MemOp memop; + TCGv_i64 tcg_rm; =20 - if (extract32(opt, 1, 1) =3D=3D 0) { - unallocated_encoding(s); - return; - } - - if (is_vector) { - size |=3D (opc & 2) << 1; - if (size > 4) { - unallocated_encoding(s); - return; - } - is_store =3D !extract32(opc, 0, 1); - if (!fp_access_check(s)) { - return; - } - memop =3D finalize_memop_asimd(s, size); - } else { - if (size =3D=3D 3 && opc =3D=3D 2) { - /* PRFM - prefetch */ - return; - } - if (opc =3D=3D 3 && size > 1) { - unallocated_encoding(s); - return; - } - is_store =3D (opc =3D=3D 0); - is_signed =3D !is_store && extract32(opc, 1, 1); - is_extended =3D (size < 3) && extract32(opc, 0, 1); - memop =3D finalize_memop(s, size + is_signed * MO_SIGN); - } - - if (rn =3D=3D 31) { + if (a->rn =3D=3D 31) { gen_check_sp_alignment(s); } - dirty_addr =3D read_cpu_reg_sp(s, rn, 1); + *dirty_addr =3D read_cpu_reg_sp(s, a->rn, 1); =20 - tcg_rm =3D read_cpu_reg(s, rm, 1); - ext_and_shift_reg(tcg_rm, tcg_rm, opt, shift ? size : 0); + tcg_rm =3D read_cpu_reg(s, a->rm, 1); + ext_and_shift_reg(tcg_rm, tcg_rm, a->opt, a->s ? a->sz : 0); =20 - tcg_gen_add_i64(dirty_addr, dirty_addr, tcg_rm); + tcg_gen_add_i64(*dirty_addr, *dirty_addr, tcg_rm); + *clean_addr =3D gen_mte_check1(s, *dirty_addr, is_store, true, memop); +} =20 - clean_addr =3D gen_mte_check1(s, dirty_addr, is_store, true, memop); +static bool trans_LDR(DisasContext *s, arg_ldst *a) +{ + TCGv_i64 clean_addr, dirty_addr, tcg_rt; + bool iss_sf =3D ldst_iss_sf(a->sz, a->sign, a->ext); + MemOp memop; =20 - if (is_vector) { - if (is_store) { - do_fp_st(s, rt, clean_addr, memop); - } else { - do_fp_ld(s, rt, clean_addr, memop); - } - } else { - TCGv_i64 tcg_rt =3D cpu_reg(s, rt); - bool iss_sf =3D disas_ldst_compute_iss_sf(size, is_signed, opc); - - if (is_store) { - do_gpr_st(s, tcg_rt, clean_addr, memop, - true, rt, iss_sf, false); - } else { - do_gpr_ld(s, tcg_rt, clean_addr, memop, - is_extended, true, rt, iss_sf, false); - } + if (extract32(a->opt, 1, 1) =3D=3D 0) { + return false; } + + memop =3D finalize_memop(s, a->sz + a->sign * MO_SIGN); + op_addr_ldst_pre(s, a, &clean_addr, &dirty_addr, false, memop); + tcg_rt =3D cpu_reg(s, a->rt); + do_gpr_ld(s, tcg_rt, clean_addr, memop, + a->ext, true, a->rt, iss_sf, false); + return true; +} + +static bool trans_STR(DisasContext *s, arg_ldst *a) +{ + TCGv_i64 clean_addr, dirty_addr, tcg_rt; + bool iss_sf =3D ldst_iss_sf(a->sz, a->sign, a->ext); + MemOp memop; + + if (extract32(a->opt, 1, 1) =3D=3D 0) { + return false; + } + + memop =3D finalize_memop(s, a->sz); + op_addr_ldst_pre(s, a, &clean_addr, &dirty_addr, true, memop); + tcg_rt =3D cpu_reg(s, a->rt); + do_gpr_st(s, tcg_rt, clean_addr, memop, true, a->rt, iss_sf, false); + return true; +} + +static bool trans_LDR_v(DisasContext *s, arg_ldst *a) +{ + TCGv_i64 clean_addr, dirty_addr; + MemOp memop; + + if (extract32(a->opt, 1, 1) =3D=3D 0) { + return false; + } + + if (!fp_access_check(s)) { + return true; + } + + memop =3D finalize_memop_asimd(s, a->sz); + op_addr_ldst_pre(s, a, &clean_addr, &dirty_addr, false, memop); + do_fp_ld(s, a->rt, clean_addr, memop); + return true; +} + +static bool trans_STR_v(DisasContext *s, arg_ldst *a) +{ + TCGv_i64 clean_addr, dirty_addr; + MemOp memop; + + if (extract32(a->opt, 1, 1) =3D=3D 0) { + return false; + } + + if (!fp_access_check(s)) { + return true; + } + + memop =3D finalize_memop_asimd(s, a->sz); + op_addr_ldst_pre(s, a, &clean_addr, &dirty_addr, true, memop); + do_fp_st(s, a->rt, clean_addr, memop); + return true; } =20 /* Atomic memory operations @@ -3531,7 +3522,6 @@ static void disas_ldst_ldapr_stlr(DisasContext *s, ui= nt32_t insn) static void disas_ldst_reg(DisasContext *s, uint32_t insn) { int rt =3D extract32(insn, 0, 5); - int opc =3D extract32(insn, 22, 2); bool is_vector =3D extract32(insn, 26, 1); int size =3D extract32(insn, 30, 2); =20 @@ -3545,8 +3535,7 @@ static void disas_ldst_reg(DisasContext *s, uint32_t = insn) disas_ldst_atomic(s, insn, size, rt, is_vector); return; case 2: - disas_ldst_reg_roffset(s, insn, opc, size, rt, is_vector); - return; + break; default: disas_ldst_pac(s, insn, size, rt, is_vector); return; --=20 2.34.1 From nobody Fri May 10 11:25:59 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1686499378; cv=none; d=zohomail.com; s=zohoarc; b=USREXrN++UJBZqsqUtqhK1YlpZscznkTFZc+Xa2exerI3wlTY55i3usTrVoeINpGTImAEhx7butb9Qs1+POnQHnmfM/ay/3VTp58ThQoSrKTPyuwsYZbZ7zQik/ytMGi1ifg5ZiZudUoOZddz7Mf54daYfZgCymSXKfu1uqGvfk= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1686499378; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id m9-20020a056000008900b0030ae499da59sm9923022wrx.111.2023.06.11.09.00.43 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 11 Jun 2023 09:00:43 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1686499244; x=1689091244; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=oLXqPmCYkrVQJjFssdMLngIfPo1Xii5VF1gQjOemTjU=; b=FztI6AKJSqmxnkw6DQTdM5787q4EEfj/2IRls1cxJXF40xY4Q64XQq5n56GYm8rQmf B2QUiPpJYLm3Q2wiHZH33wjPOyhwTuY9IHBlCNfaPeS5ZrlCjMIBrvMWxcOLdSGR8Tvc q/lNygn+VySdGz/V+78E3jBCSpII5ghqxasHM1svvqOO2/0ISyCqLFhbeYecZ9/2WGt2 WKQfgK2c2jEubr1FJAKSleT4oaorSah2AYcv2Uwum3Oir3e93bWqAq+/Ug5Boy5+EI6t HggNsj7yQaThluJdH0N5UH1jEayJWHC5pZQHXOxxLxft4Qn+EBUIyqSdfjW14ZPWRsW/ jK6w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1686499244; x=1689091244; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=oLXqPmCYkrVQJjFssdMLngIfPo1Xii5VF1gQjOemTjU=; b=l7QdzL82vl6ppVmX2J5rutn79n8ZNKLSOp+5zvabPxiOFqtikJSJRwjBv04RD1IeXd yBzoT+997SkF4DcZl3m6KmSUuRVpGd00Bw+Kwj8jupbWHfzekNLO/PvNDrCEjQ9GHatn OFTvL5WaIA2AueL1WSyFR9yTAY4ABNcFEQsR46apI7tGQKOr5lcnaUMYTU4qUnLA+FlJ 9jt3X0c+eGrh/9CihYIbcV3Wux4q1vOXZ8QS3MPxCy5AVUJ9gVie5/eUIlEBTuveZQ+N q81XihYN3x0O83kHTdPGyI2sL7SmTGqFuhta7K/FadbaxmqYcGBQTam2pfB1sJlgKA0g 4bNQ== X-Gm-Message-State: AC+VfDwSxfS1QwMwbyorWuKGWTQB/A/JRrcCTgReW5JzuzRPxEXEdqEA QqEqKTr4XL6ZfpHhYyOIdvnvXA== X-Google-Smtp-Source: ACHHUZ7Aj0/tieaFGlWPf0cvh8zHacxNdQM++DsJwV06/TgQQAICw+m2NsAd9N4L3GHTV68/Shd85w== X-Received: by 2002:adf:f642:0:b0:2f0:2dfe:e903 with SMTP id x2-20020adff642000000b002f02dfee903mr2240852wrp.69.1686499243992; Sun, 11 Jun 2023 09:00:43 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH v2 18/23] target/arm: Convert atomic memory ops to decodetree Date: Sun, 11 Jun 2023 17:00:27 +0100 Message-Id: <20230611160032.274823-19-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230611160032.274823-1-peter.maydell@linaro.org> References: <20230611160032.274823-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::429; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x429.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1686499378631100002 Content-Type: text/plain; charset="utf-8" Convert the insns in the atomic memory operations group to decodetree. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Message-id: 20230602155223.2040685-16-peter.maydell@linaro.org --- target/arm/tcg/a64.decode | 15 ++++ target/arm/tcg/translate-a64.c | 153 ++++++++++++--------------------- 2 files changed, 70 insertions(+), 98 deletions(-) diff --git a/target/arm/tcg/a64.decode b/target/arm/tcg/a64.decode index 5c086d6af6d..799c5ecb77a 100644 --- a/target/arm/tcg/a64.decode +++ b/target/arm/tcg/a64.decode @@ -442,3 +442,18 @@ STR_v sz:2 111 1 00 00 1 ..... ... . 10 ....= . ..... @ldst sign=3D0 ext=3D0 STR_v 00 111 1 00 10 1 ..... ... . 10 ..... ..... @ldst sign=3D0= ext=3D0 sz=3D4 LDR_v sz:2 111 1 00 01 1 ..... ... . 10 ..... ..... @ldst sign= =3D0 ext=3D0 LDR_v 00 111 1 00 11 1 ..... ... . 10 ..... ..... @ldst sign=3D0= ext=3D0 sz=3D4 + +# Atomic memory operations +&atomic rs rn rt a r sz +@atomic sz:2 ... . .. a:1 r:1 . rs:5 . ... .. rn:5 rt:5 &atomic +LDADD .. 111 0 00 . . 1 ..... 0000 00 ..... ..... @atomic +LDCLR .. 111 0 00 . . 1 ..... 0001 00 ..... ..... @atomic +LDEOR .. 111 0 00 . . 1 ..... 0010 00 ..... ..... @atomic +LDSET .. 111 0 00 . . 1 ..... 0011 00 ..... ..... @atomic +LDSMAX .. 111 0 00 . . 1 ..... 0100 00 ..... ..... @atomic +LDSMIN .. 111 0 00 . . 1 ..... 0101 00 ..... ..... @atomic +LDUMAX .. 111 0 00 . . 1 ..... 0110 00 ..... ..... @atomic +LDUMIN .. 111 0 00 . . 1 ..... 0111 00 ..... ..... @atomic +SWP .. 111 0 00 . . 1 ..... 1000 00 ..... ..... @atomic + +LDAPR sz:2 111 0 00 1 0 1 11111 1100 00 rn:5 rt:5 diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c index 3d161169411..ba072e557e1 100644 --- a/target/arm/tcg/translate-a64.c +++ b/target/arm/tcg/translate-a64.c @@ -3244,113 +3244,32 @@ static bool trans_STR_v(DisasContext *s, arg_ldst = *a) return true; } =20 -/* Atomic memory operations - * - * 31 30 27 26 24 22 21 16 15 12 10 5 0 - * +------+-------+---+-----+-----+---+----+----+-----+-----+----+-----+ - * | size | 1 1 1 | V | 0 0 | A R | 1 | Rs | o3 | opc | 0 0 | Rn | Rt | - * +------+-------+---+-----+-----+--------+----+-----+-----+----+-----+ - * - * Rt: the result register - * Rn: base address or SP - * Rs: the source register for the operation - * V: vector flag (always 0 as of v8.3) - * A: acquire flag - * R: release flag - */ -static void disas_ldst_atomic(DisasContext *s, uint32_t insn, - int size, int rt, bool is_vector) + +static bool do_atomic_ld(DisasContext *s, arg_atomic *a, AtomicThreeOpFn *= fn, + int sign, bool invert) { - int rs =3D extract32(insn, 16, 5); - int rn =3D extract32(insn, 5, 5); - int o3_opc =3D extract32(insn, 12, 4); - bool r =3D extract32(insn, 22, 1); - bool a =3D extract32(insn, 23, 1); - TCGv_i64 tcg_rs, tcg_rt, clean_addr; - AtomicThreeOpFn *fn =3D NULL; - MemOp mop =3D size; + MemOp mop =3D a->sz | sign; + TCGv_i64 clean_addr, tcg_rs, tcg_rt; =20 - if (is_vector || !dc_isar_feature(aa64_atomics, s)) { - unallocated_encoding(s); - return; - } - switch (o3_opc) { - case 000: /* LDADD */ - fn =3D tcg_gen_atomic_fetch_add_i64; - break; - case 001: /* LDCLR */ - fn =3D tcg_gen_atomic_fetch_and_i64; - break; - case 002: /* LDEOR */ - fn =3D tcg_gen_atomic_fetch_xor_i64; - break; - case 003: /* LDSET */ - fn =3D tcg_gen_atomic_fetch_or_i64; - break; - case 004: /* LDSMAX */ - fn =3D tcg_gen_atomic_fetch_smax_i64; - mop |=3D MO_SIGN; - break; - case 005: /* LDSMIN */ - fn =3D tcg_gen_atomic_fetch_smin_i64; - mop |=3D MO_SIGN; - break; - case 006: /* LDUMAX */ - fn =3D tcg_gen_atomic_fetch_umax_i64; - break; - case 007: /* LDUMIN */ - fn =3D tcg_gen_atomic_fetch_umin_i64; - break; - case 010: /* SWP */ - fn =3D tcg_gen_atomic_xchg_i64; - break; - case 014: /* LDAPR, LDAPRH, LDAPRB */ - if (!dc_isar_feature(aa64_rcpc_8_3, s) || - rs !=3D 31 || a !=3D 1 || r !=3D 0) { - unallocated_encoding(s); - return; - } - break; - default: - unallocated_encoding(s); - return; - } - - if (rn =3D=3D 31) { + if (a->rn =3D=3D 31) { gen_check_sp_alignment(s); } - - mop =3D check_atomic_align(s, rn, mop); - clean_addr =3D gen_mte_check1(s, cpu_reg_sp(s, rn), false, rn !=3D 31,= mop); - - if (o3_opc =3D=3D 014) { - /* - * LDAPR* are a special case because they are a simple load, not a - * fetch-and-do-something op. - * The architectural consistency requirements here are weaker than - * full load-acquire (we only need "load-acquire processor consist= ent"), - * but we choose to implement them as full LDAQ. - */ - do_gpr_ld(s, cpu_reg(s, rt), clean_addr, mop, false, - true, rt, disas_ldst_compute_iss_sf(size, false, 0), tru= e); - tcg_gen_mb(TCG_MO_ALL | TCG_BAR_LDAQ); - return; - } - - tcg_rs =3D read_cpu_reg(s, rs, true); - tcg_rt =3D cpu_reg(s, rt); - - if (o3_opc =3D=3D 1) { /* LDCLR */ + mop =3D check_atomic_align(s, a->rn, mop); + clean_addr =3D gen_mte_check1(s, cpu_reg_sp(s, a->rn), false, + a->rn !=3D 31, mop); + tcg_rs =3D read_cpu_reg(s, a->rs, true); + tcg_rt =3D cpu_reg(s, a->rt); + if (invert) { tcg_gen_not_i64(tcg_rs, tcg_rs); } - - /* The tcg atomic primitives are all full barriers. Therefore we + /* + * The tcg atomic primitives are all full barriers. Therefore we * can ignore the Acquire and Release bits of this instruction. */ fn(tcg_rt, clean_addr, tcg_rs, get_mem_index(s), mop); =20 if (mop & MO_SIGN) { - switch (size) { + switch (a->sz) { case MO_8: tcg_gen_ext8u_i64(tcg_rt, tcg_rt); break; @@ -3366,6 +3285,46 @@ static void disas_ldst_atomic(DisasContext *s, uint3= 2_t insn, g_assert_not_reached(); } } + return true; +} + +TRANS_FEAT(LDADD, aa64_atomics, do_atomic_ld, a, tcg_gen_atomic_fetch_add_= i64, 0, false) +TRANS_FEAT(LDCLR, aa64_atomics, do_atomic_ld, a, tcg_gen_atomic_fetch_and_= i64, 0, true) +TRANS_FEAT(LDEOR, aa64_atomics, do_atomic_ld, a, tcg_gen_atomic_fetch_xor_= i64, 0, false) +TRANS_FEAT(LDSET, aa64_atomics, do_atomic_ld, a, tcg_gen_atomic_fetch_or_i= 64, 0, false) +TRANS_FEAT(LDSMAX, aa64_atomics, do_atomic_ld, a, tcg_gen_atomic_fetch_sma= x_i64, MO_SIGN, false) +TRANS_FEAT(LDSMIN, aa64_atomics, do_atomic_ld, a, tcg_gen_atomic_fetch_smi= n_i64, MO_SIGN, false) +TRANS_FEAT(LDUMAX, aa64_atomics, do_atomic_ld, a, tcg_gen_atomic_fetch_uma= x_i64, 0, false) +TRANS_FEAT(LDUMIN, aa64_atomics, do_atomic_ld, a, tcg_gen_atomic_fetch_umi= n_i64, 0, false) +TRANS_FEAT(SWP, aa64_atomics, do_atomic_ld, a, tcg_gen_atomic_xchg_i64, 0,= false) + +static bool trans_LDAPR(DisasContext *s, arg_LDAPR *a) +{ + bool iss_sf =3D ldst_iss_sf(a->sz, false, false); + TCGv_i64 clean_addr; + MemOp mop; + + if (!dc_isar_feature(aa64_atomics, s) || + !dc_isar_feature(aa64_rcpc_8_3, s)) { + return false; + } + if (a->rn =3D=3D 31) { + gen_check_sp_alignment(s); + } + mop =3D check_atomic_align(s, a->rn, a->sz); + clean_addr =3D gen_mte_check1(s, cpu_reg_sp(s, a->rn), false, + a->rn !=3D 31, mop); + /* + * LDAPR* are a special case because they are a simple load, not a + * fetch-and-do-something op. + * The architectural consistency requirements here are weaker than + * full load-acquire (we only need "load-acquire processor consistent"= ), + * but we choose to implement them as full LDAQ. + */ + do_gpr_ld(s, cpu_reg(s, a->rt), clean_addr, mop, false, + true, a->rt, iss_sf, true); + tcg_gen_mb(TCG_MO_ALL | TCG_BAR_LDAQ); + return true; } =20 /* @@ -3532,8 +3491,6 @@ static void disas_ldst_reg(DisasContext *s, uint32_t = insn) } switch (extract32(insn, 10, 2)) { case 0: - disas_ldst_atomic(s, insn, size, rt, is_vector); - return; case 2: break; default: --=20 2.34.1 From nobody Fri May 10 11:25:59 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1686499536; cv=none; d=zohomail.com; s=zohoarc; b=Ko9RVmssZdeJTH/V+q342XiQq8g1X1Fi9c5KmHYNlvlCe4T82NKnvzIhTeBkijLJWCySD9RZ1OsN/p/qY+BOK4t8Eu7SqqYpo5xpsoLB9DVO//h7UgBO5+Eeav6nq6GecwnMO+FdEiHSb6Udd7QS+onF/ovGRrkEA2gRHHIDv0s= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1686499536; h=Content-Type:Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=N+pQRQmAdtEEtSrG+QeiKV8rPKg6vCTkrLwwP7CdWfo=; b=e/CxIjHsrMdvqJYh//2LebQdCbOS0QLiCOBtZ79++yVpZAOPSi6dRYunZPdhM2EtMjc0o4Sio6Jztt492ei03tdAWSSuZk1rB6Q860QlHIEJdUSKTatEqN1QvyRxwYFUKT9kDJhBpb6uChdxFMHE8dnWpYGUgcBHeVtE+aWdb+A= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1686499536092518.0067466103544; Sun, 11 Jun 2023 09:05:36 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1q8NVi-0006dY-TW; Sun, 11 Jun 2023 12:01:46 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1q8NUq-0005xZ-Nx for qemu-devel@nongnu.org; Sun, 11 Jun 2023 12:00:54 -0400 Received: from mail-wr1-x434.google.com ([2a00:1450:4864:20::434]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1q8NUk-0000Wf-2t for qemu-devel@nongnu.org; Sun, 11 Jun 2023 12:00:52 -0400 Received: by mail-wr1-x434.google.com with SMTP id ffacd0b85a97d-30af86a966eso2198011f8f.2 for ; Sun, 11 Jun 2023 09:00:45 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id m9-20020a056000008900b0030ae499da59sm9923022wrx.111.2023.06.11.09.00.44 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 11 Jun 2023 09:00:44 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1686499244; x=1689091244; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=N+pQRQmAdtEEtSrG+QeiKV8rPKg6vCTkrLwwP7CdWfo=; b=e8vU85VBADO34kcK0WVnYNNBKAq0zBN52RtHpO84wkigHo++frFCA99lJXzt/eer8C GiFUkKiIcW/0T7oa6k2+tKYTj7jeD7UePgtF8+1+Rxbjk5dKqMCwDLysmQzC3ZePwp4n sBydQT5BlJIjwiqOY+ce/AN081clXtonEU49gahb0NkXyUcjttmA/WbiHf1hJReyJowl uCn2m6DfGQat3uSh2FoyXoiJhup9px/VJS4thF1u6e5vJS5V8NBZaZ7VAWIHBLxMCGDK clMWHl4UF4kInz42Iwno3HM4NszLsggmJ5OSXRSXEr1bEnyG6m7EI2bgu0kSV/NEqLr+ ycwA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1686499244; x=1689091244; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=N+pQRQmAdtEEtSrG+QeiKV8rPKg6vCTkrLwwP7CdWfo=; b=bGebTRzIdwSl/I061tJczK6SO1vXVETSLmLU2XJJeptqbWIbDZ64eTOLko+ENAvzO/ 4mtYY94HDIpQ1qleAN1rUuYPMeg/WTVzVLC64ecLc4EW08fl3QkYxv2isAoiS5L2rkgA W7khht45UJofQ7mACGTt4ZmD7pqQkXkriTMadWzhf2YqJUXymAOS18wnVZhMWsKJeDmP wnubusm/e8bYRl/jtzYUit3uaASx+7K/4ySqqIFFBe36NHrpLkvnfv7yMqQXPetFdb+t Z4USE3RZd3r5adpn1sVIEMAwzJRvD+YjGV9AKEx2TLFAbe11WNIkVbVd3wD8R5l7jnZp Q1QA== X-Gm-Message-State: AC+VfDyiT+D3hZ6BcozQFdUAoQlwDcS3f22jptUNRqDwpARI9SZpsh86 0qChqwBSjneE8OOLEkJbyWEvskW2T3SGeuqkSTE= X-Google-Smtp-Source: ACHHUZ7YHYeSEIGp+KveMzPDRnqjQ+WT9TqPDyWoDfbgECcxK/xMjjSpBJR00oE76sQK3D7DlM6PFg== X-Received: by 2002:a5d:470b:0:b0:2f4:6574:5a93 with SMTP id y11-20020a5d470b000000b002f465745a93mr2528242wrq.4.1686499244679; Sun, 11 Jun 2023 09:00:44 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH v2 19/23] target/arm: Convert load (pointer auth) insns to decodetree Date: Sun, 11 Jun 2023 17:00:28 +0100 Message-Id: <20230611160032.274823-20-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230611160032.274823-1-peter.maydell@linaro.org> References: <20230611160032.274823-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::434; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x434.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1686499537533100006 Convert the instructions in the load/store register (pointer authentication) group ot decodetree: LDRAA, LDRAB. Signed-off-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson Message-id: 20230602155223.2040685-17-peter.maydell@linaro.org --- target/arm/tcg/a64.decode | 7 +++ target/arm/tcg/translate-a64.c | 83 +++++++--------------------------- 2 files changed, 23 insertions(+), 67 deletions(-) diff --git a/target/arm/tcg/a64.decode b/target/arm/tcg/a64.decode index 799c5ecb77a..b80a17111e7 100644 --- a/target/arm/tcg/a64.decode +++ b/target/arm/tcg/a64.decode @@ -457,3 +457,10 @@ LDUMIN .. 111 0 00 . . 1 ..... 0111 00 ..... = ..... @atomic SWP .. 111 0 00 . . 1 ..... 1000 00 ..... ..... @atomic =20 LDAPR sz:2 111 0 00 1 0 1 11111 1100 00 rn:5 rt:5 + +# Load/store register (pointer authentication) + +# LDRA immediate is 10 bits signed and scaled, but the bits aren't all con= tiguous +%ldra_imm 22:s1 12:9 !function=3Dtimes_2 + +LDRA 11 111 0 00 m:1 . 1 ......... w:1 1 rn:5 rt:5 imm=3D%ldra_= imm diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c index ba072e557e1..b4b029d0910 100644 --- a/target/arm/tcg/translate-a64.c +++ b/target/arm/tcg/translate-a64.c @@ -3327,43 +3327,23 @@ static bool trans_LDAPR(DisasContext *s, arg_LDAPR = *a) return true; } =20 -/* - * PAC memory operations - * - * 31 30 27 26 24 22 21 12 11 10 5 0 - * +------+-------+---+-----+-----+---+--------+---+---+----+-----+ - * | size | 1 1 1 | V | 0 0 | M S | 1 | imm9 | W | 1 | Rn | Rt | - * +------+-------+---+-----+-----+---+--------+---+---+----+-----+ - * - * Rt: the result register - * Rn: base address or SP - * V: vector flag (always 0 as of v8.3) - * M: clear for key DA, set for key DB - * W: pre-indexing flag - * S: sign for imm9. - */ -static void disas_ldst_pac(DisasContext *s, uint32_t insn, - int size, int rt, bool is_vector) +static bool trans_LDRA(DisasContext *s, arg_LDRA *a) { - int rn =3D extract32(insn, 5, 5); - bool is_wback =3D extract32(insn, 11, 1); - bool use_key_a =3D !extract32(insn, 23, 1); - int offset; TCGv_i64 clean_addr, dirty_addr, tcg_rt; MemOp memop; =20 - if (size !=3D 3 || is_vector || !dc_isar_feature(aa64_pauth, s)) { - unallocated_encoding(s); - return; + /* Load with pointer authentication */ + if (!dc_isar_feature(aa64_pauth, s)) { + return false; } =20 - if (rn =3D=3D 31) { + if (a->rn =3D=3D 31) { gen_check_sp_alignment(s); } - dirty_addr =3D read_cpu_reg_sp(s, rn, 1); + dirty_addr =3D read_cpu_reg_sp(s, a->rn, 1); =20 if (s->pauth_active) { - if (use_key_a) { + if (!a->m) { gen_helper_autda(dirty_addr, cpu_env, dirty_addr, tcg_constant_i64(0)); } else { @@ -3372,25 +3352,23 @@ static void disas_ldst_pac(DisasContext *s, uint32_= t insn, } } =20 - /* Form the 10-bit signed, scaled offset. */ - offset =3D (extract32(insn, 22, 1) << 9) | extract32(insn, 12, 9); - offset =3D sextract32(offset << size, 0, 10 + size); - tcg_gen_addi_i64(dirty_addr, dirty_addr, offset); + tcg_gen_addi_i64(dirty_addr, dirty_addr, a->imm); =20 - memop =3D finalize_memop(s, size); + memop =3D finalize_memop(s, MO_64); =20 /* Note that "clean" and "dirty" here refer to TBI not PAC. */ clean_addr =3D gen_mte_check1(s, dirty_addr, false, - is_wback || rn !=3D 31, memop); + a->w || a->rn !=3D 31, memop); =20 - tcg_rt =3D cpu_reg(s, rt); + tcg_rt =3D cpu_reg(s, a->rt); do_gpr_ld(s, tcg_rt, clean_addr, memop, - /* extend */ false, /* iss_valid */ !is_wback, - /* iss_srt */ rt, /* iss_sf */ true, /* iss_ar */ false); + /* extend */ false, /* iss_valid */ !a->w, + /* iss_srt */ a->rt, /* iss_sf */ true, /* iss_ar */ false); =20 - if (is_wback) { - tcg_gen_mov_i64(cpu_reg_sp(s, rn), dirty_addr); + if (a->w) { + tcg_gen_mov_i64(cpu_reg_sp(s, a->rn), dirty_addr); } + return true; } =20 /* @@ -3477,31 +3455,6 @@ static void disas_ldst_ldapr_stlr(DisasContext *s, u= int32_t insn) } } =20 -/* Load/store register (all forms) */ -static void disas_ldst_reg(DisasContext *s, uint32_t insn) -{ - int rt =3D extract32(insn, 0, 5); - bool is_vector =3D extract32(insn, 26, 1); - int size =3D extract32(insn, 30, 2); - - switch (extract32(insn, 24, 2)) { - case 0: - if (extract32(insn, 21, 1) =3D=3D 0) { - break; - } - switch (extract32(insn, 10, 2)) { - case 0: - case 2: - break; - default: - disas_ldst_pac(s, insn, size, rt, is_vector); - return; - } - break; - } - unallocated_encoding(s); -} - /* AdvSIMD load/store multiple structures * * 31 30 29 23 22 21 16 15 12 11 10 9 5 4 0 @@ -4019,10 +3972,6 @@ static void disas_ldst_tag(DisasContext *s, uint32_t= insn) static void disas_ldst(DisasContext *s, uint32_t insn) { switch (extract32(insn, 24, 6)) { - case 0x38: case 0x39: - case 0x3c: case 0x3d: /* Load/store register (all forms) */ - disas_ldst_reg(s, insn); - break; case 0x0c: /* AdvSIMD load/store multiple structures */ disas_ldst_multiple_struct(s, insn); break; --=20 2.34.1 From nobody Fri May 10 11:25:59 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1686499590; cv=none; d=zohomail.com; s=zohoarc; b=YiUpEDj9lPvHsF740WZdhjm2fcPgsSGJ1xVDO+KThu16wakbo4j6lzZMfOHIA9/1yXcQ+xFvtSUzPulng9TVBLWGbmt41kkxQXjsNLgyxaUSVRi2qV8W/6sJvGABHdEIJTf+gr00Qp2vchxkJfDetRY/QizBTXc7+IFT017wj60= ARC-Message-Signature: i=1; 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id m9-20020a056000008900b0030ae499da59sm9923022wrx.111.2023.06.11.09.00.44 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 11 Jun 2023 09:00:44 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1686499245; x=1689091245; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=54h5KyRrZywpu1fDQUIOHLpTGvmaF3+L9nkmV/iZDt8=; b=siFfS4UeRkmZilsU8crwbaSQ0PtTACdyuQZNBjPeZkCl2/oeuNOIEPjUJCo/wGpG4n OEYNDhgLUVFZEybG2nfEYIv3sC636kT3ttpt1//LzwtTsZpCBN/ijhgLVZmjQw7lrIAk lt9ajJzD7yZPFlEBL8wJSrqhZXEiTvoHScr1TYhyZKfIjZk2Xw+HZ5UxY+r7cHEJOoBz qodiuoLRlKPPWZLvAj23b6hfKwIHrNwaQfjc+kIn+U+8pFwnDkMyL/bkG//HUD2YPE+7 WE9zh9tYL4Dwbbr6jSs86iAGVeYjMYSSsvzA42xIwWjGJTXvLH3ISFaYMFEoFr5DE3m8 MTAw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1686499245; x=1689091245; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=54h5KyRrZywpu1fDQUIOHLpTGvmaF3+L9nkmV/iZDt8=; b=A76UN+KvMsNn2xbVC7gkAawVfxVhCfiV6O+CeVw4bSMbgncLtzF8v/wDGtL4oePaqg 3z7U2Qp0sRp5PEpFoXWkth5DuONx/CRfOgszOcMktLcweky92DNw5NyF6QDvza4ASKQW wU3hVlBWmNRhr/OLR+VdBGws7f/QaDcj2/be+jG/Y7fuTFz8JkXJsRYGfOB7V0JaYKH/ TxD8UtjB114n/O16sqJOggtnsNJjetKLATGluLQ+/MDYHehtUEhS8BwtT0GMsBc80aFg can2Yt+oUifKD32jW0itMQq/RBgJjO29ePafAS3cyqO6pDqwe5eur0DrGGC0j86BzxY7 ujxA== X-Gm-Message-State: AC+VfDzR6+Z9qJgUz4I1AEChb8ynlrj0pJIvN6KBYfaa5g+4W5erMen6 UavnE8Xx+3qMtBGeVNKbcmKu7yXIiSHvp39N/3A= X-Google-Smtp-Source: ACHHUZ5E2M6xE/U1EtrMoq4EYYGmmjex2M1v7LY/1qfLsw6WPitxQS7S/9To2O1P78748cU+SofNvQ== X-Received: by 2002:a05:6000:147:b0:30a:bf2b:e03b with SMTP id r7-20020a056000014700b0030abf2be03bmr2997799wrx.1.1686499245224; Sun, 11 Jun 2023 09:00:45 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH v2 20/23] target/arm: Convert LDAPR/STLR (imm) to decodetree Date: Sun, 11 Jun 2023 17:00:29 +0100 Message-Id: <20230611160032.274823-21-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230611160032.274823-1-peter.maydell@linaro.org> References: <20230611160032.274823-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32d; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1686499591944100003 Content-Type: text/plain; charset="utf-8" Convert the instructions in the LDAPR/STLR (unscaled immediate) group to decodetree. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Message-id: 20230602155223.2040685-18-peter.maydell@linaro.org --- target/arm/tcg/a64.decode | 10 +++ target/arm/tcg/translate-a64.c | 132 ++++++++++++--------------------- 2 files changed, 56 insertions(+), 86 deletions(-) diff --git a/target/arm/tcg/a64.decode b/target/arm/tcg/a64.decode index b80a17111e7..db4f44c4f40 100644 --- a/target/arm/tcg/a64.decode +++ b/target/arm/tcg/a64.decode @@ -464,3 +464,13 @@ LDAPR sz:2 111 0 00 1 0 1 11111 1100 00 rn:5= rt:5 %ldra_imm 22:s1 12:9 !function=3Dtimes_2 =20 LDRA 11 111 0 00 m:1 . 1 ......... w:1 1 rn:5 rt:5 imm=3D%ldra_= imm + +&ldapr_stlr_i rn rt imm sz sign ext +@ldapr_stlr_i .. ...... .. . imm:9 .. rn:5 rt:5 &ldapr_stlr_i +STLR_i sz:2 011001 00 0 ......... 00 ..... ..... @ldapr_stlr_i si= gn=3D0 ext=3D0 +LDAPR_i sz:2 011001 01 0 ......... 00 ..... ..... @ldapr_stlr_i si= gn=3D0 ext=3D0 +LDAPR_i 00 011001 10 0 ......... 00 ..... ..... @ldapr_stlr_i sign= =3D1 ext=3D0 sz=3D0 +LDAPR_i 01 011001 10 0 ......... 00 ..... ..... @ldapr_stlr_i sign= =3D1 ext=3D0 sz=3D1 +LDAPR_i 10 011001 10 0 ......... 00 ..... ..... @ldapr_stlr_i sign= =3D1 ext=3D0 sz=3D2 +LDAPR_i 00 011001 11 0 ......... 00 ..... ..... @ldapr_stlr_i sign= =3D1 ext=3D1 sz=3D0 +LDAPR_i 01 011001 11 0 ......... 00 ..... ..... @ldapr_stlr_i sign= =3D1 ext=3D1 sz=3D1 diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c index b4b029d0910..54383211006 100644 --- a/target/arm/tcg/translate-a64.c +++ b/target/arm/tcg/translate-a64.c @@ -2652,22 +2652,12 @@ static void gen_compare_and_swap_pair(DisasContext = *s, int rs, int rt, } } =20 -/* Update the Sixty-Four bit (SF) registersize. This logic is derived +/* + * Compute the ISS.SF bit for syndrome information if an exception + * is taken on a load or store. This indicates whether the instruction + * is accessing a 32-bit or 64-bit register. This logic is derived * from the ARMv8 specs for LDR (Shared decode for all encodings). */ -static bool disas_ldst_compute_iss_sf(int size, bool is_signed, int opc) -{ - int opc0 =3D extract32(opc, 0, 1); - int regsize; - - if (is_signed) { - regsize =3D opc0 ? 32 : 64; - } else { - regsize =3D size =3D=3D 3 ? 64 : 32; - } - return regsize =3D=3D 64; -} - static bool ldst_iss_sf(int size, bool sign, bool ext) { =20 @@ -3371,88 +3361,60 @@ static bool trans_LDRA(DisasContext *s, arg_LDRA *a) return true; } =20 -/* - * LDAPR/STLR (unscaled immediate) - * - * 31 30 24 22 21 12 10 5 0 - * +------+-------------+-----+---+--------+-----+----+-----+ - * | size | 0 1 1 0 0 1 | opc | 0 | imm9 | 0 0 | Rn | Rt | - * +------+-------------+-----+---+--------+-----+----+-----+ - * - * Rt: source or destination register - * Rn: base register - * imm9: unscaled immediate offset - * opc: 00: STLUR*, 01/10/11: various LDAPUR* - * size: size of load/store - */ -static void disas_ldst_ldapr_stlr(DisasContext *s, uint32_t insn) +static bool trans_LDAPR_i(DisasContext *s, arg_ldapr_stlr_i *a) { - int rt =3D extract32(insn, 0, 5); - int rn =3D extract32(insn, 5, 5); - int offset =3D sextract32(insn, 12, 9); - int opc =3D extract32(insn, 22, 2); - int size =3D extract32(insn, 30, 2); TCGv_i64 clean_addr, dirty_addr; - bool is_store =3D false; - bool extend =3D false; - bool iss_sf; - MemOp mop =3D size; + MemOp mop =3D a->sz | (a->sign ? MO_SIGN : 0); + bool iss_sf =3D ldst_iss_sf(a->sz, a->sign, a->ext); =20 if (!dc_isar_feature(aa64_rcpc_8_4, s)) { - unallocated_encoding(s); - return; + return false; } =20 - switch (opc) { - case 0: /* STLURB */ - is_store =3D true; - break; - case 1: /* LDAPUR* */ - break; - case 2: /* LDAPURS* 64-bit variant */ - if (size =3D=3D 3) { - unallocated_encoding(s); - return; - } - mop |=3D MO_SIGN; - break; - case 3: /* LDAPURS* 32-bit variant */ - if (size > 1) { - unallocated_encoding(s); - return; - } - mop |=3D MO_SIGN; - extend =3D true; /* zero-extend 32->64 after signed load */ - break; - default: - g_assert_not_reached(); - } - - iss_sf =3D disas_ldst_compute_iss_sf(size, (mop & MO_SIGN) !=3D 0, opc= ); - - if (rn =3D=3D 31) { + if (a->rn =3D=3D 31) { gen_check_sp_alignment(s); } =20 - mop =3D check_ordered_align(s, rn, offset, is_store, mop); - - dirty_addr =3D read_cpu_reg_sp(s, rn, 1); - tcg_gen_addi_i64(dirty_addr, dirty_addr, offset); + mop =3D check_ordered_align(s, a->rn, a->imm, false, mop); + dirty_addr =3D read_cpu_reg_sp(s, a->rn, 1); + tcg_gen_addi_i64(dirty_addr, dirty_addr, a->imm); clean_addr =3D clean_data_tbi(s, dirty_addr); =20 - if (is_store) { - /* Store-Release semantics */ - tcg_gen_mb(TCG_MO_ALL | TCG_BAR_STRL); - do_gpr_st(s, cpu_reg(s, rt), clean_addr, mop, true, rt, iss_sf, tr= ue); - } else { - /* - * Load-AcquirePC semantics; we implement as the slightly more - * restrictive Load-Acquire. - */ - do_gpr_ld(s, cpu_reg(s, rt), clean_addr, mop, - extend, true, rt, iss_sf, true); - tcg_gen_mb(TCG_MO_ALL | TCG_BAR_LDAQ); + /* + * Load-AcquirePC semantics; we implement as the slightly more + * restrictive Load-Acquire. + */ + do_gpr_ld(s, cpu_reg(s, a->rt), clean_addr, mop, a->ext, true, + a->rt, iss_sf, true); + tcg_gen_mb(TCG_MO_ALL | TCG_BAR_LDAQ); + return true; +} + +static bool trans_STLR_i(DisasContext *s, arg_ldapr_stlr_i *a) +{ + TCGv_i64 clean_addr, dirty_addr; + MemOp mop =3D a->sz; + bool iss_sf =3D ldst_iss_sf(a->sz, a->sign, a->ext); + + if (!dc_isar_feature(aa64_rcpc_8_4, s)) { + return false; } + + /* TODO: ARMv8.4-LSE SCTLR.nAA */ + + if (a->rn =3D=3D 31) { + gen_check_sp_alignment(s); + } + + mop =3D check_ordered_align(s, a->rn, a->imm, true, mop); + dirty_addr =3D read_cpu_reg_sp(s, a->rn, 1); + tcg_gen_addi_i64(dirty_addr, dirty_addr, a->imm); + clean_addr =3D clean_data_tbi(s, dirty_addr); + + /* Store-Release semantics */ + tcg_gen_mb(TCG_MO_ALL | TCG_BAR_STRL); + do_gpr_st(s, cpu_reg(s, a->rt), clean_addr, mop, true, a->rt, iss_sf, = true); + return true; } =20 /* AdvSIMD load/store multiple structures @@ -3981,8 +3943,6 @@ static void disas_ldst(DisasContext *s, uint32_t insn) case 0x19: if (extract32(insn, 21, 1) !=3D 0) { disas_ldst_tag(s, insn); - } else if (extract32(insn, 10, 2) =3D=3D 0) { - disas_ldst_ldapr_stlr(s, insn); } else { unallocated_encoding(s); } --=20 2.34.1 From nobody Fri May 10 11:25:59 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id m9-20020a056000008900b0030ae499da59sm9923022wrx.111.2023.06.11.09.00.45 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 11 Jun 2023 09:00:45 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1686499246; x=1689091246; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=2RxZp4L2OOp86GeN9wdwmMgvMFkloHNsLM24GLSIa0U=; b=eoAJnuGRZa9p4qK/jadAodscf5DyoMNOwEAgGqxG8OtUn1mnpBAZ2lxOkTNpURuWou BgkWwGONwLZ74CHChimq4u0rZyDsmS3s9MNXC3J6xXwY0lOiFzeuGocD+vlEx0lpiIVM lFkxho2zLtz7Pq360SI2gNhfdyACwHARsJ4buYAAtwdwk22ZKyAgI7hpwqsx/1bs30xo AyTHKbcNgpCut45b4vB7Q7BhkqWam4hgEJwf+MIPhsRMiGWNJ7+lppobdBiMSFbM9tIt z6r0rmII9lwJ0C/g/G6Z1ACcqS/2c+45iOzDitL390/dZxu2Mi+T2rfTdOQY6ULbd4GQ nA6Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1686499246; x=1689091246; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=2RxZp4L2OOp86GeN9wdwmMgvMFkloHNsLM24GLSIa0U=; b=llq4xJT2iDL21zx73um+PsHAE8o1og+RJyhEUx6IVmcliQepvRIn5VVGz2o+G4LUNa 2a1ariq4H2ixbhGBLE0l0TzeYE9T2UJsIbijWZzt5e05Vk4lBcK+McEn/0X+RVbK/8lG QhMi6J5q6NmLQaxL4aI/vz/IHQbLOQytzRI2Di86N5X7tsbFBjJ56SKOnG2Rp2Bpwj69 yc8CUi57RWi5fWSCdPkV8c+UfjUx3A8MIYdfscLsP7iT+ijaR5DLWGJ5/H4OlKLa559K 4dBRg8MmUM6qV++nCFk7V3ZU5dAiC6faAf0uPQJXcg1osnh2CSDvi3+v/2KTUqPhM4sF catg== X-Gm-Message-State: AC+VfDyHv3X5wT3wkYIvL7Ls6iA2z8az8Yks3UEEsDpFqGpX09rH3xFZ 1VLSozsvh13s5ZPJ7coNcC34eg== X-Google-Smtp-Source: ACHHUZ5XYMicalWOvbqUjT5G2UxM7N+NFGFkolpcjOvkbanFsXQUwiTJ+S5s3brQitZ3FJfQTB5btA== X-Received: by 2002:a5d:6a87:0:b0:2cf:e747:b0d4 with SMTP id s7-20020a5d6a87000000b002cfe747b0d4mr2417583wru.40.1686499245790; Sun, 11 Jun 2023 09:00:45 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH v2 21/23] target/arm: Convert load/store (multiple structures) to decodetree Date: Sun, 11 Jun 2023 17:00:30 +0100 Message-Id: <20230611160032.274823-22-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230611160032.274823-1-peter.maydell@linaro.org> References: <20230611160032.274823-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::436; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x436.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1686499512715100005 Content-Type: text/plain; charset="utf-8" Convert the instructions in the ASIMD load/store multiple structures instruction classes to decodetree. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Message-id: 20230602155223.2040685-19-peter.maydell@linaro.org --- target/arm/tcg/a64.decode | 20 +++ target/arm/tcg/translate-a64.c | 222 ++++++++++++++++----------------- 2 files changed, 131 insertions(+), 111 deletions(-) diff --git a/target/arm/tcg/a64.decode b/target/arm/tcg/a64.decode index db4f44c4f40..69bdfa2e73b 100644 --- a/target/arm/tcg/a64.decode +++ b/target/arm/tcg/a64.decode @@ -474,3 +474,23 @@ LDAPR_i 01 011001 10 0 ......... 00 ..... ....= . @ldapr_stlr_i sign=3D1 ext LDAPR_i 10 011001 10 0 ......... 00 ..... ..... @ldapr_stlr_i sign= =3D1 ext=3D0 sz=3D2 LDAPR_i 00 011001 11 0 ......... 00 ..... ..... @ldapr_stlr_i sign= =3D1 ext=3D1 sz=3D0 LDAPR_i 01 011001 11 0 ......... 00 ..... ..... @ldapr_stlr_i sign= =3D1 ext=3D1 sz=3D1 + +# Load/store multiple structures +# The 4-bit opcode in [15:12] encodes repeat count and structure elements +&ldst_mult rm rn rt sz q p rpt selem +@ldst_mult . q:1 ...... p:1 . . rm:5 .... sz:2 rn:5 rt:5 &ldst_mult +ST_mult 0 . 001100 . 0 0 ..... 0000 .. ..... ..... @ldst_mult rpt= =3D1 selem=3D4 +ST_mult 0 . 001100 . 0 0 ..... 0010 .. ..... ..... @ldst_mult rpt= =3D4 selem=3D1 +ST_mult 0 . 001100 . 0 0 ..... 0100 .. ..... ..... @ldst_mult rpt= =3D1 selem=3D3 +ST_mult 0 . 001100 . 0 0 ..... 0110 .. ..... ..... @ldst_mult rpt= =3D3 selem=3D1 +ST_mult 0 . 001100 . 0 0 ..... 0111 .. ..... ..... @ldst_mult rpt= =3D1 selem=3D1 +ST_mult 0 . 001100 . 0 0 ..... 1000 .. ..... ..... @ldst_mult rpt= =3D1 selem=3D2 +ST_mult 0 . 001100 . 0 0 ..... 1010 .. ..... ..... @ldst_mult rpt= =3D2 selem=3D1 + +LD_mult 0 . 001100 . 1 0 ..... 0000 .. ..... ..... @ldst_mult rpt= =3D1 selem=3D4 +LD_mult 0 . 001100 . 1 0 ..... 0010 .. ..... ..... @ldst_mult rpt= =3D4 selem=3D1 +LD_mult 0 . 001100 . 1 0 ..... 0100 .. ..... ..... @ldst_mult rpt= =3D1 selem=3D3 +LD_mult 0 . 001100 . 1 0 ..... 0110 .. ..... ..... @ldst_mult rpt= =3D3 selem=3D1 +LD_mult 0 . 001100 . 1 0 ..... 0111 .. ..... ..... @ldst_mult rpt= =3D1 selem=3D1 +LD_mult 0 . 001100 . 1 0 ..... 1000 .. ..... ..... @ldst_mult rpt= =3D1 selem=3D2 +LD_mult 0 . 001100 . 1 0 ..... 1010 .. ..... ..... @ldst_mult rpt= =3D2 selem=3D1 diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c index 54383211006..1c8a57f7b52 100644 --- a/target/arm/tcg/translate-a64.c +++ b/target/arm/tcg/translate-a64.c @@ -3417,99 +3417,28 @@ static bool trans_STLR_i(DisasContext *s, arg_ldapr= _stlr_i *a) return true; } =20 -/* AdvSIMD load/store multiple structures - * - * 31 30 29 23 22 21 16 15 12 11 10 9 5 4 0 - * +---+---+---------------+---+-------------+--------+------+------+-----= -+ - * | 0 | Q | 0 0 1 1 0 0 0 | L | 0 0 0 0 0 0 | opcode | size | Rn | Rt = | - * +---+---+---------------+---+-------------+--------+------+------+-----= -+ - * - * AdvSIMD load/store multiple structures (post-indexed) - * - * 31 30 29 23 22 21 20 16 15 12 11 10 9 5 4 0 - * +---+---+---------------+---+---+---------+--------+------+------+-----= -+ - * | 0 | Q | 0 0 1 1 0 0 1 | L | 0 | Rm | opcode | size | Rn | Rt = | - * +---+---+---------------+---+---+---------+--------+------+------+-----= -+ - * - * Rt: first (or only) SIMD&FP register to be transferred - * Rn: base address or SP - * Rm (post-index only): post-index register (when !31) or size dependent = #imm - */ -static void disas_ldst_multiple_struct(DisasContext *s, uint32_t insn) +static bool trans_LD_mult(DisasContext *s, arg_ldst_mult *a) { - int rt =3D extract32(insn, 0, 5); - int rn =3D extract32(insn, 5, 5); - int rm =3D extract32(insn, 16, 5); - int size =3D extract32(insn, 10, 2); - int opcode =3D extract32(insn, 12, 4); - bool is_store =3D !extract32(insn, 22, 1); - bool is_postidx =3D extract32(insn, 23, 1); - bool is_q =3D extract32(insn, 30, 1); TCGv_i64 clean_addr, tcg_rn, tcg_ebytes; MemOp endian, align, mop; =20 int total; /* total bytes */ int elements; /* elements per vector */ - int rpt; /* num iterations */ - int selem; /* structure elements */ int r; + int size =3D a->sz; =20 - if (extract32(insn, 31, 1) || extract32(insn, 21, 1)) { - unallocated_encoding(s); - return; + if (!a->p && a->rm !=3D 0) { + /* For non-postindexed accesses the Rm field must be 0 */ + return false; } - - if (!is_postidx && rm !=3D 0) { - unallocated_encoding(s); - return; + if (size =3D=3D 3 && !a->q && a->selem !=3D 1) { + return false; } - - /* From the shared decode logic */ - switch (opcode) { - case 0x0: - rpt =3D 1; - selem =3D 4; - break; - case 0x2: - rpt =3D 4; - selem =3D 1; - break; - case 0x4: - rpt =3D 1; - selem =3D 3; - break; - case 0x6: - rpt =3D 3; - selem =3D 1; - break; - case 0x7: - rpt =3D 1; - selem =3D 1; - break; - case 0x8: - rpt =3D 1; - selem =3D 2; - break; - case 0xa: - rpt =3D 2; - selem =3D 1; - break; - default: - unallocated_encoding(s); - return; - } - - if (size =3D=3D 3 && !is_q && selem !=3D 1) { - /* reserved */ - unallocated_encoding(s); - return; - } - if (!fp_access_check(s)) { - return; + return true; } =20 - if (rn =3D=3D 31) { + if (a->rn =3D=3D 31) { gen_check_sp_alignment(s); } =20 @@ -3519,22 +3448,22 @@ static void disas_ldst_multiple_struct(DisasContext= *s, uint32_t insn) endian =3D MO_LE; } =20 - total =3D rpt * selem * (is_q ? 16 : 8); - tcg_rn =3D cpu_reg_sp(s, rn); + total =3D a->rpt * a->selem * (a->q ? 16 : 8); + tcg_rn =3D cpu_reg_sp(s, a->rn); =20 /* * Issue the MTE check vs the logical repeat count, before we * promote consecutive little-endian elements below. */ - clean_addr =3D gen_mte_checkN(s, tcg_rn, is_store, is_postidx || rn != =3D 31, - total, finalize_memop_asimd(s, size)); + clean_addr =3D gen_mte_checkN(s, tcg_rn, false, a->p || a->rn !=3D 31,= total, + finalize_memop_asimd(s, size)); =20 /* * Consecutive little-endian elements from a single register * can be promoted to a larger little-endian operation. */ align =3D MO_ALIGN; - if (selem =3D=3D 1 && endian =3D=3D MO_LE) { + if (a->selem =3D=3D 1 && endian =3D=3D MO_LE) { align =3D pow2_align(size); size =3D 3; } @@ -3543,45 +3472,119 @@ static void disas_ldst_multiple_struct(DisasContex= t *s, uint32_t insn) } mop =3D endian | size | align; =20 - elements =3D (is_q ? 16 : 8) >> size; + elements =3D (a->q ? 16 : 8) >> size; tcg_ebytes =3D tcg_constant_i64(1 << size); - for (r =3D 0; r < rpt; r++) { + for (r =3D 0; r < a->rpt; r++) { int e; for (e =3D 0; e < elements; e++) { int xs; - for (xs =3D 0; xs < selem; xs++) { - int tt =3D (rt + r + xs) % 32; - if (is_store) { - do_vec_st(s, tt, e, clean_addr, mop); - } else { - do_vec_ld(s, tt, e, clean_addr, mop); - } + for (xs =3D 0; xs < a->selem; xs++) { + int tt =3D (a->rt + r + xs) % 32; + do_vec_ld(s, tt, e, clean_addr, mop); tcg_gen_add_i64(clean_addr, clean_addr, tcg_ebytes); } } } =20 - if (!is_store) { - /* For non-quad operations, setting a slice of the low - * 64 bits of the register clears the high 64 bits (in - * the ARM ARM pseudocode this is implicit in the fact - * that 'rval' is a 64 bit wide variable). - * For quad operations, we might still need to zero the - * high bits of SVE. - */ - for (r =3D 0; r < rpt * selem; r++) { - int tt =3D (rt + r) % 32; - clear_vec_high(s, is_q, tt); + /* + * For non-quad operations, setting a slice of the low 64 bits of + * the register clears the high 64 bits (in the ARM ARM pseudocode + * this is implicit in the fact that 'rval' is a 64 bit wide + * variable). For quad operations, we might still need to zero + * the high bits of SVE. + */ + for (r =3D 0; r < a->rpt * a->selem; r++) { + int tt =3D (a->rt + r) % 32; + clear_vec_high(s, a->q, tt); + } + + if (a->p) { + if (a->rm =3D=3D 31) { + tcg_gen_addi_i64(tcg_rn, tcg_rn, total); + } else { + tcg_gen_add_i64(tcg_rn, tcg_rn, cpu_reg(s, a->rm)); + } + } + return true; +} + +static bool trans_ST_mult(DisasContext *s, arg_ldst_mult *a) +{ + TCGv_i64 clean_addr, tcg_rn, tcg_ebytes; + MemOp endian, align, mop; + + int total; /* total bytes */ + int elements; /* elements per vector */ + int r; + int size =3D a->sz; + + if (!a->p && a->rm !=3D 0) { + /* For non-postindexed accesses the Rm field must be 0 */ + return false; + } + if (size =3D=3D 3 && !a->q && a->selem !=3D 1) { + return false; + } + if (!fp_access_check(s)) { + return true; + } + + if (a->rn =3D=3D 31) { + gen_check_sp_alignment(s); + } + + /* For our purposes, bytes are always little-endian. */ + endian =3D s->be_data; + if (size =3D=3D 0) { + endian =3D MO_LE; + } + + total =3D a->rpt * a->selem * (a->q ? 16 : 8); + tcg_rn =3D cpu_reg_sp(s, a->rn); + + /* + * Issue the MTE check vs the logical repeat count, before we + * promote consecutive little-endian elements below. + */ + clean_addr =3D gen_mte_checkN(s, tcg_rn, true, a->p || a->rn !=3D 31, = total, + finalize_memop_asimd(s, size)); + + /* + * Consecutive little-endian elements from a single register + * can be promoted to a larger little-endian operation. + */ + align =3D MO_ALIGN; + if (a->selem =3D=3D 1 && endian =3D=3D MO_LE) { + align =3D pow2_align(size); + size =3D 3; + } + if (!s->align_mem) { + align =3D 0; + } + mop =3D endian | size | align; + + elements =3D (a->q ? 16 : 8) >> size; + tcg_ebytes =3D tcg_constant_i64(1 << size); + for (r =3D 0; r < a->rpt; r++) { + int e; + for (e =3D 0; e < elements; e++) { + int xs; + for (xs =3D 0; xs < a->selem; xs++) { + int tt =3D (a->rt + r + xs) % 32; + do_vec_st(s, tt, e, clean_addr, mop); + tcg_gen_add_i64(clean_addr, clean_addr, tcg_ebytes); + } } } =20 - if (is_postidx) { - if (rm =3D=3D 31) { + if (a->p) { + if (a->rm =3D=3D 31) { tcg_gen_addi_i64(tcg_rn, tcg_rn, total); } else { - tcg_gen_add_i64(tcg_rn, tcg_rn, cpu_reg(s, rm)); + tcg_gen_add_i64(tcg_rn, tcg_rn, cpu_reg(s, a->rm)); } } + return true; } =20 /* AdvSIMD load/store single structure @@ -3934,9 +3937,6 @@ static void disas_ldst_tag(DisasContext *s, uint32_t = insn) static void disas_ldst(DisasContext *s, uint32_t insn) { switch (extract32(insn, 24, 6)) { - case 0x0c: /* AdvSIMD load/store multiple structures */ - disas_ldst_multiple_struct(s, insn); - break; case 0x0d: /* AdvSIMD load/store single structure */ disas_ldst_single_struct(s, insn); break; --=20 2.34.1 From nobody Fri May 10 11:25:59 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1686499364; cv=none; d=zohomail.com; s=zohoarc; b=cEp2NRQ9QVmzNlBOsQ0hMgHw1MHv+Ug5cLcJzs7BmEngJuTTFsvREdPnqiir4dj53iPIY7W0YjpumJqFlS7YzWu7qmAjPSG9iWq/IfvDI/o7KGQakj7ucJnJJvzH2o3DqZ5r7T0nMiNK8mnhB0H8EAp2Ty+yGtKruXR/WdqEq40= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1686499364; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=Tjmthin5TQuDssMEMCBUr/UdC5X7+Wb+s2H58zsniSY=; b=bvpYXgYYwQFAE5f/tWUHdAZE09SP+HtZYzR4ajX1QyDetlGIVzwgQa/54r+YpTkyUujwMwc/E+3GhJCVh/r0p1o9ixSRc1vKAj1VKmJbOd0aaU3yMUTURblz5MDVG1KrSsudzR1/KvF8n35RRdVhcTRc/d5qyDRzKdLkKC2O8Nk= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1686499364292985.9616262848184; Sun, 11 Jun 2023 09:02:44 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1q8NVj-0006eY-Kl; Sun, 11 Jun 2023 12:01:47 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1q8NUt-000611-48 for qemu-devel@nongnu.org; Sun, 11 Jun 2023 12:01:00 -0400 Received: from mail-wm1-x32a.google.com ([2a00:1450:4864:20::32a]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1q8NUm-0000XV-El for qemu-devel@nongnu.org; Sun, 11 Jun 2023 12:00:54 -0400 Received: by mail-wm1-x32a.google.com with SMTP id 5b1f17b1804b1-3f7f6341bf9so35039965e9.1 for ; Sun, 11 Jun 2023 09:00:47 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id m9-20020a056000008900b0030ae499da59sm9923022wrx.111.2023.06.11.09.00.45 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 11 Jun 2023 09:00:46 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1686499246; x=1689091246; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=Tjmthin5TQuDssMEMCBUr/UdC5X7+Wb+s2H58zsniSY=; b=Lju/q0TO9G1cE68bmBTRp3Nf1tEI8A/zakHeNQNTRrvYHijd3iYUeeqrH9yjUVsXiR Myq/OQ1MMkVdnFElEbVyBZ3JyIBAUTNNZTVvQin2carC/o3z/4DGrQZ3LxUzO7CqS77g yyLA5IYj5X7E81JuqAPdYlJBUuafGAcTA2bmjZTdOZ4Rg3az/2diw1VaM5VuACxqIKq6 J24POTSNFy7nwL7OciLcSW/DE080pYbEwIf0aig/XKeqJ7QMAhaQLPv003VDRjpmQ4Yp kz2bdYDqf7OKLqS+bPwzICQtwEMyuJ+8+ggwSLJkjmm1eB0G5ARjPJfqJc8XTdCOCXOx +Fcg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1686499246; x=1689091246; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=Tjmthin5TQuDssMEMCBUr/UdC5X7+Wb+s2H58zsniSY=; b=d+szbYstzrDcqcSI0EdIvri27B25voEh6ckf8T0acESztOeISddHAUnhu0kvJlKOOL ZR9gUf9pehB9sgIPhJgKOrU1D+6bNzWjne5HzWv4GpC7qp6Irdwl1YEIQE73ON3PvBSG SiwOcGWRacTDt2aRqNvHhc0fOCtV/EFu1d4+H9CoYJdbtL6Br2uEsXaW9lXFu2yzbEQ5 OM+FbltaLP7mtIDAiCRGTbNOI3tJEqZfst3yGJMX7mPfAF+qB4t6+QnYBCP9YnhDAGxD b6IKlBOajLpZiWG+2YDpwF1WSfyFUfy19uMpBNYIA6X0pY17JuN22Dvtky0BfRkPVdnz 779g== X-Gm-Message-State: AC+VfDxYya0g8X52Ar7EN31ZizvK+VFqv5DpYCA27ft5Eicehvwa9O4H NaSsZu8u6FOwfDmfCpou87HbHVtvL0VqPhnbX3I= X-Google-Smtp-Source: ACHHUZ5e3mwyeyrp6feU+7cHXcnKxUrnfXm8LGRRXp4qV9ESAaY7WbStESCZ44QXipirGe+SpsPasQ== X-Received: by 2002:a5d:6107:0:b0:30a:ec3b:58d8 with SMTP id v7-20020a5d6107000000b0030aec3b58d8mr3326192wrt.3.1686499246427; Sun, 11 Jun 2023 09:00:46 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH v2 22/23] target/arm: Convert load/store single structure to decodetree Date: Sun, 11 Jun 2023 17:00:31 +0100 Message-Id: <20230611160032.274823-23-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230611160032.274823-1-peter.maydell@linaro.org> References: <20230611160032.274823-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32a; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1686499364951100009 Content-Type: text/plain; charset="utf-8" Convert the ASIMD load/store single structure insns to decodetree. Signed-off-by: Peter Maydell Message-id: 20230602155223.2040685-20-peter.maydell@linaro.org --- target/arm/tcg/a64.decode | 34 +++++ target/arm/tcg/translate-a64.c | 219 +++++++++++++++------------------ 2 files changed, 136 insertions(+), 117 deletions(-) diff --git a/target/arm/tcg/a64.decode b/target/arm/tcg/a64.decode index 69bdfa2e73b..4ffdc91865f 100644 --- a/target/arm/tcg/a64.decode +++ b/target/arm/tcg/a64.decode @@ -494,3 +494,37 @@ LD_mult 0 . 001100 . 1 0 ..... 0110 .. ..... .= .... @ldst_mult rpt=3D3 sele LD_mult 0 . 001100 . 1 0 ..... 0111 .. ..... ..... @ldst_mult rpt= =3D1 selem=3D1 LD_mult 0 . 001100 . 1 0 ..... 1000 .. ..... ..... @ldst_mult rpt= =3D1 selem=3D2 LD_mult 0 . 001100 . 1 0 ..... 1010 .. ..... ..... @ldst_mult rpt= =3D2 selem=3D1 + +# Load/store single structure +&ldst_single rm rn rt p selem index scale + +%ldst_single_selem 13:1 21:1 !function=3Dplus_1 + +%ldst_single_index_b 30:1 10:3 +%ldst_single_index_h 30:1 11:2 +%ldst_single_index_s 30:1 12:1 + +@ldst_single_b .. ...... p:1 .. rm:5 ...... rn:5 rt:5 \ + &ldst_single scale=3D0 selem=3D%ldst_single_selem \ + index=3D%ldst_single_index_b +@ldst_single_h .. ...... p:1 .. rm:5 ...... rn:5 rt:5 \ + &ldst_single scale=3D1 selem=3D%ldst_single_selem \ + index=3D%ldst_single_index_h +@ldst_single_s .. ...... p:1 .. rm:5 ...... rn:5 rt:5 \ + &ldst_single scale=3D2 selem=3D%ldst_single_selem \ + index=3D%ldst_single_index_s +@ldst_single_d . index:1 ...... p:1 .. rm:5 ...... rn:5 rt:5 \ + &ldst_single scale=3D3 selem=3D%ldst_single_selem + +ST_single 0 . 001101 . 0 . ..... 00 . ... ..... ..... @ldst_sing= le_b +ST_single 0 . 001101 . 0 . ..... 01 . ..0 ..... ..... @ldst_sing= le_h +ST_single 0 . 001101 . 0 . ..... 10 . .00 ..... ..... @ldst_sing= le_s +ST_single 0 . 001101 . 0 . ..... 10 . 001 ..... ..... @ldst_sing= le_d + +LD_single 0 . 001101 . 1 . ..... 00 . ... ..... ..... @ldst_sing= le_b +LD_single 0 . 001101 . 1 . ..... 01 . ..0 ..... ..... @ldst_sing= le_h +LD_single 0 . 001101 . 1 . ..... 10 . .00 ..... ..... @ldst_sing= le_s +LD_single 0 . 001101 . 1 . ..... 10 . 001 ..... ..... @ldst_sing= le_d + +# Replicating load case +LD_single_repl 0 q:1 001101 p:1 1 . rm:5 11 . 0 scale:2 rn:5 rt:5 selem= =3D%ldst_single_selem diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c index 1c8a57f7b52..6e7fe1f35cf 100644 --- a/target/arm/tcg/translate-a64.c +++ b/target/arm/tcg/translate-a64.c @@ -3587,141 +3587,129 @@ static bool trans_ST_mult(DisasContext *s, arg_ld= st_mult *a) return true; } =20 -/* AdvSIMD load/store single structure - * - * 31 30 29 23 22 21 20 16 15 13 12 11 10 9 5 4 = 0 - * +---+---+---------------+-----+-----------+-----+---+------+------+----= --+ - * | 0 | Q | 0 0 1 1 0 1 0 | L R | 0 0 0 0 0 | opc | S | size | Rn | Rt= | - * +---+---+---------------+-----+-----------+-----+---+------+------+----= --+ - * - * AdvSIMD load/store single structure (post-indexed) - * - * 31 30 29 23 22 21 20 16 15 13 12 11 10 9 5 4 = 0 - * +---+---+---------------+-----+-----------+-----+---+------+------+----= --+ - * | 0 | Q | 0 0 1 1 0 1 1 | L R | Rm | opc | S | size | Rn | Rt= | - * +---+---+---------------+-----+-----------+-----+---+------+------+----= --+ - * - * Rt: first (or only) SIMD&FP register to be transferred - * Rn: base address or SP - * Rm (post-index only): post-index register (when !31) or size dependent = #imm - * index =3D encoded in Q:S:size dependent on size - * - * lane_size =3D encoded in R, opc - * transfer width =3D encoded in opc, S, size - */ -static void disas_ldst_single_struct(DisasContext *s, uint32_t insn) +static bool trans_ST_single(DisasContext *s, arg_ldst_single *a) { - int rt =3D extract32(insn, 0, 5); - int rn =3D extract32(insn, 5, 5); - int rm =3D extract32(insn, 16, 5); - int size =3D extract32(insn, 10, 2); - int S =3D extract32(insn, 12, 1); - int opc =3D extract32(insn, 13, 3); - int R =3D extract32(insn, 21, 1); - int is_load =3D extract32(insn, 22, 1); - int is_postidx =3D extract32(insn, 23, 1); - int is_q =3D extract32(insn, 30, 1); - - int scale =3D extract32(opc, 1, 2); - int selem =3D (extract32(opc, 0, 1) << 1 | R) + 1; - bool replicate =3D false; - int index =3D is_q << 3 | S << 2 | size; - int xs, total; + int xs, total, rt; TCGv_i64 clean_addr, tcg_rn, tcg_ebytes; MemOp mop; =20 - if (extract32(insn, 31, 1)) { - unallocated_encoding(s); - return; + if (!a->p && a->rm !=3D 0) { + return false; } - if (!is_postidx && rm !=3D 0) { - unallocated_encoding(s); - return; - } - - switch (scale) { - case 3: - if (!is_load || S) { - unallocated_encoding(s); - return; - } - scale =3D size; - replicate =3D true; - break; - case 0: - break; - case 1: - if (extract32(size, 0, 1)) { - unallocated_encoding(s); - return; - } - index >>=3D 1; - break; - case 2: - if (extract32(size, 1, 1)) { - unallocated_encoding(s); - return; - } - if (!extract32(size, 0, 1)) { - index >>=3D 2; - } else { - if (S) { - unallocated_encoding(s); - return; - } - index >>=3D 3; - scale =3D 3; - } - break; - default: - g_assert_not_reached(); - } - if (!fp_access_check(s)) { - return; + return true; } =20 - if (rn =3D=3D 31) { + if (a->rn =3D=3D 31) { gen_check_sp_alignment(s); } =20 - total =3D selem << scale; - tcg_rn =3D cpu_reg_sp(s, rn); + total =3D a->selem << a->scale; + tcg_rn =3D cpu_reg_sp(s, a->rn); =20 - mop =3D finalize_memop_asimd(s, scale); - - clean_addr =3D gen_mte_checkN(s, tcg_rn, !is_load, is_postidx || rn != =3D 31, + mop =3D finalize_memop_asimd(s, a->scale); + clean_addr =3D gen_mte_checkN(s, tcg_rn, true, a->p || a->rn !=3D 31, total, mop); =20 - tcg_ebytes =3D tcg_constant_i64(1 << scale); - for (xs =3D 0; xs < selem; xs++) { - if (replicate) { - /* Load and replicate to all elements */ - TCGv_i64 tcg_tmp =3D tcg_temp_new_i64(); - - tcg_gen_qemu_ld_i64(tcg_tmp, clean_addr, get_mem_index(s), mop= ); - tcg_gen_gvec_dup_i64(scale, vec_full_reg_offset(s, rt), - (is_q + 1) * 8, vec_full_reg_size(s), - tcg_tmp); - } else { - /* Load/store one element per register */ - if (is_load) { - do_vec_ld(s, rt, index, clean_addr, mop); - } else { - do_vec_st(s, rt, index, clean_addr, mop); - } - } + tcg_ebytes =3D tcg_constant_i64(1 << a->scale); + for (xs =3D 0, rt =3D a->rt; xs < a->selem; xs++, rt =3D (rt + 1) % 32= ) { + do_vec_st(s, rt, a->index, clean_addr, mop); tcg_gen_add_i64(clean_addr, clean_addr, tcg_ebytes); - rt =3D (rt + 1) % 32; } =20 - if (is_postidx) { - if (rm =3D=3D 31) { + if (a->p) { + if (a->rm =3D=3D 31) { tcg_gen_addi_i64(tcg_rn, tcg_rn, total); } else { - tcg_gen_add_i64(tcg_rn, tcg_rn, cpu_reg(s, rm)); + tcg_gen_add_i64(tcg_rn, tcg_rn, cpu_reg(s, a->rm)); } } + return true; +} + +static bool trans_LD_single(DisasContext *s, arg_ldst_single *a) +{ + int xs, total, rt; + TCGv_i64 clean_addr, tcg_rn, tcg_ebytes; + MemOp mop; + + if (!a->p && a->rm !=3D 0) { + return false; + } + if (!fp_access_check(s)) { + return true; + } + + if (a->rn =3D=3D 31) { + gen_check_sp_alignment(s); + } + + total =3D a->selem << a->scale; + tcg_rn =3D cpu_reg_sp(s, a->rn); + + mop =3D finalize_memop_asimd(s, a->scale); + clean_addr =3D gen_mte_checkN(s, tcg_rn, false, a->p || a->rn !=3D 31, + total, mop); + + tcg_ebytes =3D tcg_constant_i64(1 << a->scale); + for (xs =3D 0, rt =3D a->rt; xs < a->selem; xs++, rt =3D (rt + 1) % 32= ) { + do_vec_ld(s, rt, a->index, clean_addr, mop); + tcg_gen_add_i64(clean_addr, clean_addr, tcg_ebytes); + } + + if (a->p) { + if (a->rm =3D=3D 31) { + tcg_gen_addi_i64(tcg_rn, tcg_rn, total); + } else { + tcg_gen_add_i64(tcg_rn, tcg_rn, cpu_reg(s, a->rm)); + } + } + return true; +} + +static bool trans_LD_single_repl(DisasContext *s, arg_LD_single_repl *a) +{ + int xs, total, rt; + TCGv_i64 clean_addr, tcg_rn, tcg_ebytes; + MemOp mop; + + if (!a->p && a->rm !=3D 0) { + return false; + } + if (!fp_access_check(s)) { + return true; + } + + if (a->rn =3D=3D 31) { + gen_check_sp_alignment(s); + } + + total =3D a->selem << a->scale; + tcg_rn =3D cpu_reg_sp(s, a->rn); + + mop =3D finalize_memop_asimd(s, a->scale); + clean_addr =3D gen_mte_checkN(s, tcg_rn, false, a->p || a->rn !=3D 31, + total, mop); + + tcg_ebytes =3D tcg_constant_i64(1 << a->scale); + for (xs =3D 0, rt =3D a->rt; xs < a->selem; xs++, rt =3D (rt + 1) % 32= ) { + /* Load and replicate to all elements */ + TCGv_i64 tcg_tmp =3D tcg_temp_new_i64(); + + tcg_gen_qemu_ld_i64(tcg_tmp, clean_addr, get_mem_index(s), mop); + tcg_gen_gvec_dup_i64(a->scale, vec_full_reg_offset(s, rt), + (a->q + 1) * 8, vec_full_reg_size(s), tcg_tmp= ); + tcg_gen_add_i64(clean_addr, clean_addr, tcg_ebytes); + } + + if (a->p) { + if (a->rm =3D=3D 31) { + tcg_gen_addi_i64(tcg_rn, tcg_rn, total); + } else { + tcg_gen_add_i64(tcg_rn, tcg_rn, cpu_reg(s, a->rm)); + } + } + return true; } =20 /* @@ -3937,9 +3925,6 @@ static void disas_ldst_tag(DisasContext *s, uint32_t = insn) static void disas_ldst(DisasContext *s, uint32_t insn) { switch (extract32(insn, 24, 6)) { - case 0x0d: /* AdvSIMD load/store single structure */ - disas_ldst_single_struct(s, insn); - break; case 0x19: if (extract32(insn, 21, 1) !=3D 0) { disas_ldst_tag(s, insn); --=20 2.34.1 From nobody Fri May 10 11:25:59 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1686499593; cv=none; d=zohomail.com; s=zohoarc; b=LNygHa8VEShezAw8cLWCVicS0CluVjCw1KadHIhS35SH4dA3Cb80efrClG+vFNgbdw955HPNdc/SSjm6GznKsSpdMvVavKdsjapm44/Sq9pAlPaQovJBvd1mqUpSvcDT8FXGJkmChivgxP/r5eOH9PZurevohbEJ35wRSANDffg= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1686499593; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=N3PW9VYsAGC1K2Fi7FePAHwlou4P1DBl1fvZGT4Ua6o=; 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id m9-20020a056000008900b0030ae499da59sm9923022wrx.111.2023.06.11.09.00.46 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 11 Jun 2023 09:00:46 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1686499247; x=1689091247; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=N3PW9VYsAGC1K2Fi7FePAHwlou4P1DBl1fvZGT4Ua6o=; b=R3EahtEMoyCM0Z+UROplgAYMMPCKNPfbwBnGvJKOfrWp5vOkPJbW8ZK9hJc3ZbUpVI 5+qqx618f7pY/7FbXgfn8CkyjwBbG0Jzdp/GlPrr618ap7R+HqFv2l9d+9tpFfIo46Xy bnfwPL67QDXA/nnDyryiQBW7OhM0OiRnelNdWlsyzgp4g+k230yOKmMb1Sz+rM8H3brs T/TRT/Jc6ud0kmsDgRoaPrzfrKiTh1YGVP1syU9xLaC0r2+siCc21hmE10kHn+To0591 ZoDUT9eeL5GqqdaaDvVkBevbZb+yZn/5K+CW2IXbP/GFL22m+tb+PaBdStjwr96JEAJW wv4g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1686499247; x=1689091247; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=N3PW9VYsAGC1K2Fi7FePAHwlou4P1DBl1fvZGT4Ua6o=; b=h8b+kMgGeijlhj3F8xVGOMhhH/hkTQjHZFOx9aLcWAqAxTDZNMKystY7dhgPgYM/Dc 9Y1h+bVtKSOXLyw+Mm3EIk+TEUFCFodCdVlXDdAkqIV2wqigfaxj2gIV96f1B5IPzN2W oFasdfgjQcVIuNQDF5HG5rf1qqrgUTOKDvAYcWobvVG8Qduocn4RiFE3TYxNQfZVZg7R uzEXZlN924rKMEN3j8Y3XhWus2DLW3LD8wItB/2iSYoZbZrScLLXUkE3e1qe/WNgNOs3 1KAPAuHRHpKmxA6Zea7lro0VlVALGYvpiAe+UOaJe2IP5lVuhv4InOcgosh3WI2dPq7N mjmw== X-Gm-Message-State: AC+VfDx7/lb3ySo5Fvit0kv6JcXRHJd34x6A99Tz1rPClen7/+OwvJTF qhHK0n01MaHPekdRgJBnGteXEmlmInbctrnf5uY= X-Google-Smtp-Source: ACHHUZ5pisSMJqRMcubg0WtV4BPnLOVkSKOttbeHmK/73zLaIg878QB4u481/LEi+CRQ/qaXxe/FjA== X-Received: by 2002:adf:e906:0:b0:30f:be0f:fbf with SMTP id f6-20020adfe906000000b0030fbe0f0fbfmr1109970wrm.22.1686499247015; Sun, 11 Jun 2023 09:00:47 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH v2 23/23] target/arm: Convert load/store tags insns to decodetree Date: Sun, 11 Jun 2023 17:00:32 +0100 Message-Id: <20230611160032.274823-24-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230611160032.274823-1-peter.maydell@linaro.org> References: <20230611160032.274823-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::431; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x431.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1686499594315100007 Content-Type: text/plain; charset="utf-8" Convert the instructions in the load/store memory tags instruction group to decodetree. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Message-id: 20230602155223.2040685-21-peter.maydell@linaro.org --- target/arm/tcg/a64.decode | 25 +++ target/arm/tcg/translate-a64.c | 360 ++++++++++++++++----------------- 2 files changed, 199 insertions(+), 186 deletions(-) diff --git a/target/arm/tcg/a64.decode b/target/arm/tcg/a64.decode index 4ffdc91865f..ef64a3f9cba 100644 --- a/target/arm/tcg/a64.decode +++ b/target/arm/tcg/a64.decode @@ -528,3 +528,28 @@ LD_single 0 . 001101 . 1 . ..... 10 . 001 ...= .. ..... @ldst_single_d =20 # Replicating load case LD_single_repl 0 q:1 001101 p:1 1 . rm:5 11 . 0 scale:2 rn:5 rt:5 selem= =3D%ldst_single_selem + +%tag_offset 12:s9 !function=3Dscale_by_log2_tag_granule +&ldst_tag rn rt imm p w +@ldst_tag ........ .. . ......... .. rn:5 rt:5 &ldst_tag imm=3D%tag_= offset +@ldst_tag_mult ........ .. . 000000000 .. rn:5 rt:5 &ldst_tag imm=3D0 + +STZGM 11011001 00 1 ......... 00 ..... ..... @ldst_tag_mult p=3D= 0 w=3D0 +STG 11011001 00 1 ......... 01 ..... ..... @ldst_tag p=3D1 w= =3D1 +STG 11011001 00 1 ......... 10 ..... ..... @ldst_tag p=3D0 w= =3D0 +STG 11011001 00 1 ......... 11 ..... ..... @ldst_tag p=3D0 w= =3D1 + +LDG 11011001 01 1 ......... 00 ..... ..... @ldst_tag p=3D0 w= =3D0 +STZG 11011001 01 1 ......... 01 ..... ..... @ldst_tag p=3D1 w= =3D1 +STZG 11011001 01 1 ......... 10 ..... ..... @ldst_tag p=3D0 w= =3D0 +STZG 11011001 01 1 ......... 11 ..... ..... @ldst_tag p=3D0 w= =3D1 + +STGM 11011001 10 1 ......... 00 ..... ..... @ldst_tag_mult p=3D= 0 w=3D0 +ST2G 11011001 10 1 ......... 01 ..... ..... @ldst_tag p=3D1 w= =3D1 +ST2G 11011001 10 1 ......... 10 ..... ..... @ldst_tag p=3D0 w= =3D0 +ST2G 11011001 10 1 ......... 11 ..... ..... @ldst_tag p=3D0 w= =3D1 + +LDGM 11011001 11 1 ......... 00 ..... ..... @ldst_tag_mult p=3D= 0 w=3D0 +STZ2G 11011001 11 1 ......... 01 ..... ..... @ldst_tag p=3D1 w= =3D1 +STZ2G 11011001 11 1 ......... 10 ..... ..... @ldst_tag p=3D0 w= =3D0 +STZ2G 11011001 11 1 ......... 11 ..... ..... @ldst_tag p=3D0 w= =3D1 diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c index 6e7fe1f35cf..43963287a8c 100644 --- a/target/arm/tcg/translate-a64.c +++ b/target/arm/tcg/translate-a64.c @@ -62,6 +62,12 @@ static int uimm_scaled(DisasContext *s, int x) return imm << scale; } =20 +/* For load/store memory tags: scale offset by LOG2_TAG_GRANULE */ +static int scale_by_log2_tag_granule(DisasContext *s, int x) +{ + return x << LOG2_TAG_GRANULE; +} + /* * Include the generated decoders. */ @@ -3712,185 +3718,184 @@ static bool trans_LD_single_repl(DisasContext *s,= arg_LD_single_repl *a) return true; } =20 -/* - * Load/Store memory tags - * - * 31 30 29 24 22 21 12 10 5 0 - * +-----+-------------+-----+---+------+-----+------+------+ - * | 1 1 | 0 1 1 0 0 1 | op1 | 1 | imm9 | op2 | Rn | Rt | - * +-----+-------------+-----+---+------+-----+------+------+ - */ -static void disas_ldst_tag(DisasContext *s, uint32_t insn) +static bool trans_STZGM(DisasContext *s, arg_ldst_tag *a) { - int rt =3D extract32(insn, 0, 5); - int rn =3D extract32(insn, 5, 5); - uint64_t offset =3D sextract64(insn, 12, 9) << LOG2_TAG_GRANULE; - int op2 =3D extract32(insn, 10, 2); - int op1 =3D extract32(insn, 22, 2); - bool is_load =3D false, is_pair =3D false, is_zero =3D false, is_mult = =3D false; - int index =3D 0; TCGv_i64 addr, clean_addr, tcg_rt; + int size =3D 4 << s->dcz_blocksize; =20 - /* We checked insn bits [29:24,21] in the caller. */ - if (extract32(insn, 30, 2) !=3D 3) { - goto do_unallocated; + if (!dc_isar_feature(aa64_mte, s)) { + return false; + } + if (s->current_el =3D=3D 0) { + return false; } =20 - /* - * @index is a tri-state variable which has 3 states: - * < 0 : post-index, writeback - * =3D 0 : signed offset - * > 0 : pre-index, writeback - */ - switch (op1) { - case 0: - if (op2 !=3D 0) { - /* STG */ - index =3D op2 - 2; - } else { - /* STZGM */ - if (s->current_el =3D=3D 0 || offset !=3D 0) { - goto do_unallocated; - } - is_mult =3D is_zero =3D true; - } - break; - case 1: - if (op2 !=3D 0) { - /* STZG */ - is_zero =3D true; - index =3D op2 - 2; - } else { - /* LDG */ - is_load =3D true; - } - break; - case 2: - if (op2 !=3D 0) { - /* ST2G */ - is_pair =3D true; - index =3D op2 - 2; - } else { - /* STGM */ - if (s->current_el =3D=3D 0 || offset !=3D 0) { - goto do_unallocated; - } - is_mult =3D true; - } - break; - case 3: - if (op2 !=3D 0) { - /* STZ2G */ - is_pair =3D is_zero =3D true; - index =3D op2 - 2; - } else { - /* LDGM */ - if (s->current_el =3D=3D 0 || offset !=3D 0) { - goto do_unallocated; - } - is_mult =3D is_load =3D true; - } - break; - - default: - do_unallocated: - unallocated_encoding(s); - return; - } - - if (is_mult - ? !dc_isar_feature(aa64_mte, s) - : !dc_isar_feature(aa64_mte_insn_reg, s)) { - goto do_unallocated; - } - - if (rn =3D=3D 31) { + if (a->rn =3D=3D 31) { gen_check_sp_alignment(s); } =20 - addr =3D read_cpu_reg_sp(s, rn, true); - if (index >=3D 0) { + addr =3D read_cpu_reg_sp(s, a->rn, true); + tcg_gen_addi_i64(addr, addr, a->imm); + tcg_rt =3D cpu_reg(s, a->rt); + + if (s->ata) { + gen_helper_stzgm_tags(cpu_env, addr, tcg_rt); + } + /* + * The non-tags portion of STZGM is mostly like DC_ZVA, + * except the alignment happens before the access. + */ + clean_addr =3D clean_data_tbi(s, addr); + tcg_gen_andi_i64(clean_addr, clean_addr, -size); + gen_helper_dc_zva(cpu_env, clean_addr); + return true; +} + +static bool trans_STGM(DisasContext *s, arg_ldst_tag *a) +{ + TCGv_i64 addr, clean_addr, tcg_rt; + + if (!dc_isar_feature(aa64_mte, s)) { + return false; + } + if (s->current_el =3D=3D 0) { + return false; + } + + if (a->rn =3D=3D 31) { + gen_check_sp_alignment(s); + } + + addr =3D read_cpu_reg_sp(s, a->rn, true); + tcg_gen_addi_i64(addr, addr, a->imm); + tcg_rt =3D cpu_reg(s, a->rt); + + if (s->ata) { + gen_helper_stgm(cpu_env, addr, tcg_rt); + } else { + MMUAccessType acc =3D MMU_DATA_STORE; + int size =3D 4 << GMID_EL1_BS; + + clean_addr =3D clean_data_tbi(s, addr); + tcg_gen_andi_i64(clean_addr, clean_addr, -size); + gen_probe_access(s, clean_addr, acc, size); + } + return true; +} + +static bool trans_LDGM(DisasContext *s, arg_ldst_tag *a) +{ + TCGv_i64 addr, clean_addr, tcg_rt; + + if (!dc_isar_feature(aa64_mte, s)) { + return false; + } + if (s->current_el =3D=3D 0) { + return false; + } + + if (a->rn =3D=3D 31) { + gen_check_sp_alignment(s); + } + + addr =3D read_cpu_reg_sp(s, a->rn, true); + tcg_gen_addi_i64(addr, addr, a->imm); + tcg_rt =3D cpu_reg(s, a->rt); + + if (s->ata) { + gen_helper_ldgm(tcg_rt, cpu_env, addr); + } else { + MMUAccessType acc =3D MMU_DATA_LOAD; + int size =3D 4 << GMID_EL1_BS; + + clean_addr =3D clean_data_tbi(s, addr); + tcg_gen_andi_i64(clean_addr, clean_addr, -size); + gen_probe_access(s, clean_addr, acc, size); + /* The result tags are zeros. */ + tcg_gen_movi_i64(tcg_rt, 0); + } + return true; +} + +static bool trans_LDG(DisasContext *s, arg_ldst_tag *a) +{ + TCGv_i64 addr, clean_addr, tcg_rt; + + if (!dc_isar_feature(aa64_mte_insn_reg, s)) { + return false; + } + + if (a->rn =3D=3D 31) { + gen_check_sp_alignment(s); + } + + addr =3D read_cpu_reg_sp(s, a->rn, true); + if (!a->p) { /* pre-index or signed offset */ - tcg_gen_addi_i64(addr, addr, offset); + tcg_gen_addi_i64(addr, addr, a->imm); } =20 - if (is_mult) { - tcg_rt =3D cpu_reg(s, rt); + tcg_gen_andi_i64(addr, addr, -TAG_GRANULE); + tcg_rt =3D cpu_reg(s, a->rt); + if (s->ata) { + gen_helper_ldg(tcg_rt, cpu_env, addr, tcg_rt); + } else { + /* + * Tag access disabled: we must check for aborts on the load + * load from [rn+offset], and then insert a 0 tag into rt. + */ + clean_addr =3D clean_data_tbi(s, addr); + gen_probe_access(s, clean_addr, MMU_DATA_LOAD, MO_8); + gen_address_with_allocation_tag0(tcg_rt, tcg_rt); + } =20 - if (is_zero) { - int size =3D 4 << s->dcz_blocksize; - - if (s->ata) { - gen_helper_stzgm_tags(cpu_env, addr, tcg_rt); - } - /* - * The non-tags portion of STZGM is mostly like DC_ZVA, - * except the alignment happens before the access. - */ - clean_addr =3D clean_data_tbi(s, addr); - tcg_gen_andi_i64(clean_addr, clean_addr, -size); - gen_helper_dc_zva(cpu_env, clean_addr); - } else if (s->ata) { - if (is_load) { - gen_helper_ldgm(tcg_rt, cpu_env, addr); - } else { - gen_helper_stgm(cpu_env, addr, tcg_rt); - } - } else { - MMUAccessType acc =3D is_load ? MMU_DATA_LOAD : MMU_DATA_STORE; - int size =3D 4 << GMID_EL1_BS; - - clean_addr =3D clean_data_tbi(s, addr); - tcg_gen_andi_i64(clean_addr, clean_addr, -size); - gen_probe_access(s, clean_addr, acc, size); - - if (is_load) { - /* The result tags are zeros. */ - tcg_gen_movi_i64(tcg_rt, 0); - } + if (a->w) { + /* pre-index or post-index */ + if (a->p) { + /* post-index */ + tcg_gen_addi_i64(addr, addr, a->imm); } - return; + tcg_gen_mov_i64(cpu_reg_sp(s, a->rn), addr); + } + return true; +} + +static bool do_STG(DisasContext *s, arg_ldst_tag *a, bool is_zero, bool is= _pair) +{ + TCGv_i64 addr, tcg_rt; + + if (a->rn =3D=3D 31) { + gen_check_sp_alignment(s); } =20 - if (is_load) { - tcg_gen_andi_i64(addr, addr, -TAG_GRANULE); - tcg_rt =3D cpu_reg(s, rt); - if (s->ata) { - gen_helper_ldg(tcg_rt, cpu_env, addr, tcg_rt); + addr =3D read_cpu_reg_sp(s, a->rn, true); + if (!a->p) { + /* pre-index or signed offset */ + tcg_gen_addi_i64(addr, addr, a->imm); + } + tcg_rt =3D cpu_reg_sp(s, a->rt); + if (!s->ata) { + /* + * For STG and ST2G, we need to check alignment and probe memory. + * TODO: For STZG and STZ2G, we could rely on the stores below, + * at least for system mode; user-only won't enforce alignment. + */ + if (is_pair) { + gen_helper_st2g_stub(cpu_env, addr); } else { - /* - * Tag access disabled: we must check for aborts on the load - * load from [rn+offset], and then insert a 0 tag into rt. - */ - clean_addr =3D clean_data_tbi(s, addr); - gen_probe_access(s, clean_addr, MMU_DATA_LOAD, MO_8); - gen_address_with_allocation_tag0(tcg_rt, tcg_rt); + gen_helper_stg_stub(cpu_env, addr); + } + } else if (tb_cflags(s->base.tb) & CF_PARALLEL) { + if (is_pair) { + gen_helper_st2g_parallel(cpu_env, addr, tcg_rt); + } else { + gen_helper_stg_parallel(cpu_env, addr, tcg_rt); } } else { - tcg_rt =3D cpu_reg_sp(s, rt); - if (!s->ata) { - /* - * For STG and ST2G, we need to check alignment and probe memo= ry. - * TODO: For STZG and STZ2G, we could rely on the stores below, - * at least for system mode; user-only won't enforce alignment. - */ - if (is_pair) { - gen_helper_st2g_stub(cpu_env, addr); - } else { - gen_helper_stg_stub(cpu_env, addr); - } - } else if (tb_cflags(s->base.tb) & CF_PARALLEL) { - if (is_pair) { - gen_helper_st2g_parallel(cpu_env, addr, tcg_rt); - } else { - gen_helper_stg_parallel(cpu_env, addr, tcg_rt); - } + if (is_pair) { + gen_helper_st2g(cpu_env, addr, tcg_rt); } else { - if (is_pair) { - gen_helper_st2g(cpu_env, addr, tcg_rt); - } else { - gen_helper_stg(cpu_env, addr, tcg_rt); - } + gen_helper_stg(cpu_env, addr, tcg_rt); } } =20 @@ -3911,32 +3916,21 @@ static void disas_ldst_tag(DisasContext *s, uint32_= t insn) } } =20 - if (index !=3D 0) { + if (a->w) { /* pre-index or post-index */ - if (index < 0) { + if (a->p) { /* post-index */ - tcg_gen_addi_i64(addr, addr, offset); + tcg_gen_addi_i64(addr, addr, a->imm); } - tcg_gen_mov_i64(cpu_reg_sp(s, rn), addr); + tcg_gen_mov_i64(cpu_reg_sp(s, a->rn), addr); } + return true; } =20 -/* Loads and stores */ -static void disas_ldst(DisasContext *s, uint32_t insn) -{ - switch (extract32(insn, 24, 6)) { - case 0x19: - if (extract32(insn, 21, 1) !=3D 0) { - disas_ldst_tag(s, insn); - } else { - unallocated_encoding(s); - } - break; - default: - unallocated_encoding(s); - break; - } -} +TRANS_FEAT(STG, aa64_mte_insn_reg, do_STG, a, false, false) +TRANS_FEAT(STZG, aa64_mte_insn_reg, do_STG, a, true, false) +TRANS_FEAT(ST2G, aa64_mte_insn_reg, do_STG, a, false, true) +TRANS_FEAT(STZ2G, aa64_mte_insn_reg, do_STG, a, true, true) =20 typedef void ArithTwoOp(TCGv_i64, TCGv_i64, TCGv_i64); =20 @@ -13832,12 +13826,6 @@ static bool btype_destination_ok(uint32_t insn, bo= ol bt, int btype) static void disas_a64_legacy(DisasContext *s, uint32_t insn) { switch (extract32(insn, 25, 4)) { - case 0x4: - case 0x6: - case 0xc: - case 0xe: /* Loads and stores */ - disas_ldst(s, insn); - break; case 0x5: case 0xd: /* Data processing - register */ disas_data_proc_reg(s, insn); --=20 2.34.1