[PULL 0/1] loongarch-to-apply queue
[PULL 00/31] loongarch-to-apply queue
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The following changes since commit 848a6caa88b9f082c89c9b41afa975761262981d:
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The following changes since commit b0dd9a7d6dd15a6898e9c585b521e6bec79b25aa:
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Merge tag 'migration-20230602-pull-request' of https://gitlab.com/juan.quintela/qemu into staging (2023-06-02 17:33:29 -0700)
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Open 8.2 development tree (2023-08-22 07:14:07 -0700)
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are available in the Git repository at:
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are available in the Git repository at:
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6
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https://gitlab.com/gaosong/qemu.git tags/pull-loongarch-20230605
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https://gitlab.com/gaosong/qemu.git tags/pull-loongarch-20230824
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8
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for you to fetch changes up to 8555ddc671203969b0e6eb651e538d02a9a79b3a:
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for you to fetch changes up to 3f6bec4a9f7c159d32d49f6df5c2c3d587b953b9:
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hw/intc/loongarch_ipi: Bring back all 4 IPI mailboxes (2023-06-05 11:08:55 +0800)
11
hw/loongarch: Fix ACPI processor id off-by-one error (2023-08-24 16:58:16 +0800)
12
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13
----------------------------------------------------------------
13
----------------------------------------------------------------
14
Fixes Coverity CID: 1512452, 1512453
14
pull-loongarch-20230824
15
Fixes: 78464f023b54 ("hw/loongarch/virt: Modify ipi as percpu device")
15
16
* Add la32 & va32 support for loongarch64-softmmu;
17
* Cleanups in preparation of loongarch32 support;
18
* Add some checks before translating instructions;
19
* Split fcc register to fcc0-7 in gdbstub;
20
* Fix ACPI processor id off-by-one error;
21
* Implement get_arch_id callback;
22
* Fix edge triggered irq handling.
16
23
17
----------------------------------------------------------------
24
----------------------------------------------------------------
18
Jiaxun Yang (1):
25
Bibo Mao (2):
19
hw/intc/loongarch_ipi: Bring back all 4 IPI mailboxes
26
target/loongarch: cpu: Implement get_arch_id callback
27
hw/intc/loongarch_pch: fix edge triggered irq handling
20
28
21
hw/intc/loongarch_ipi.c | 6 +++---
29
Jiajie Chen (16):
22
include/hw/intc/loongarch_ipi.h | 4 +++-
30
target/loongarch: Add function to check current arch
23
2 files changed, 6 insertions(+), 4 deletions(-)
31
target/loongarch: Add new object class for loongarch32 cpus
32
target/loongarch: Add GDB support for loongarch32 mode
33
target/loongarch: Support LoongArch32 TLB entry
34
target/loongarch: Support LoongArch32 DMW
35
target/loongarch: Support LoongArch32 VPPN
36
target/loongarch: Add LA64 & VA32 to DisasContext
37
target/loongarch: Extract make_address_x() helper
38
target/loongarch: Extract make_address_i() helper
39
target/loongarch: Extract make_address_pc() helper
40
target/loongarch: Extract set_pc() helper
41
target/loongarch: Truncate high 32 bits of address in VA32 mode
42
target/loongarch: Sign extend results in VA32 mode
43
target/loongarch: Add LoongArch32 cpu la132
44
target/loongarch: Split fcc register to fcc0-7 in gdbstub
45
hw/loongarch: Fix ACPI processor id off-by-one error
46
47
Philippe Mathieu-Daudé (4):
48
target/loongarch: Log I/O write accesses to CSR registers
49
target/loongarch: Remove duplicated disas_set_info assignment
50
target/loongarch: Introduce abstract TYPE_LOONGARCH64_CPU
51
target/loongarch: Extract 64-bit specifics to loongarch64_cpu_class_init
52
53
Song Gao (9):
54
target/loongarch: Fix loongarch_la464_initfn() misses setting LSPW
55
target/loongarch: Add a check parameter to the TRANS macro
56
target/loongarch: Add avail_64 to check la64-only instructions
57
hw/loongarch: Remove restriction of la464 cores in the virt machine
58
target/loongarch: Add avail_FP/FP_SP/FP_DP to check fpu instructions
59
target/loongarch: Add avail_LSPW to check LSPW instructions
60
target/loongarch: Add avail_LAM to check atomic instructions
61
target/loongarch: Add avail_LSX to check LSX instructions
62
target/loongarch: Add avail_IOCSR to check iocsr instructions
63
64
configs/targets/loongarch64-softmmu.mak | 2 +-
65
gdb-xml/loongarch-base32.xml | 45 +
66
gdb-xml/loongarch-fpu.xml | 9 +-
67
hw/intc/loongarch_pch_pic.c | 7 +-
68
hw/loongarch/acpi-build.c | 2 +-
69
hw/loongarch/virt.c | 7 +-
70
target/loongarch/cpu-csr.h | 22 +-
71
target/loongarch/cpu.c | 110 +-
72
target/loongarch/cpu.h | 35 +
73
target/loongarch/gdbstub.c | 50 +-
74
target/loongarch/insn_trans/trans_arith.c.inc | 98 +-
75
target/loongarch/insn_trans/trans_atomic.c.inc | 85 +-
76
target/loongarch/insn_trans/trans_bit.c.inc | 56 +-
77
target/loongarch/insn_trans/trans_branch.c.inc | 27 +-
78
target/loongarch/insn_trans/trans_extra.c.inc | 24 +-
79
target/loongarch/insn_trans/trans_farith.c.inc | 96 +-
80
target/loongarch/insn_trans/trans_fcmp.c.inc | 8 +
81
target/loongarch/insn_trans/trans_fcnv.c.inc | 56 +-
82
target/loongarch/insn_trans/trans_fmemory.c.inc | 62 +-
83
target/loongarch/insn_trans/trans_fmov.c.inc | 52 +-
84
target/loongarch/insn_trans/trans_lsx.c.inc | 1520 +++++++++++---------
85
target/loongarch/insn_trans/trans_memory.c.inc | 118 +-
86
target/loongarch/insn_trans/trans_privileged.c.inc | 24 +-
87
target/loongarch/insn_trans/trans_shift.c.inc | 34 +-
88
target/loongarch/op_helper.c | 4 +-
89
target/loongarch/tlb_helper.c | 66 +-
90
target/loongarch/translate.c | 46 +
91
target/loongarch/translate.h | 19 +-
92
28 files changed, 1591 insertions(+), 1093 deletions(-)
93
create mode 100644 gdb-xml/loongarch-base32.xml
94
95
diff view generated by jsdifflib
New patch
[PULL 01/31] target/loongarch: Log I/O write accesses to CSR registers
1
From: Philippe Mathieu-Daudé <philmd@linaro.org>
1
2
3
Various CSR registers have Read/Write fields. We might
4
want to see guest trying to change such registers.
5
6
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
7
Reviewed-by: Song Gao <gaosong@loongson.cn>
8
Message-Id: <20230821125959.28666-2-philmd@linaro.org>
9
Signed-off-by: Song Gao <gaosong@loongson.cn>
10
---
11
target/loongarch/cpu.c | 2 ++
12
1 file changed, 2 insertions(+)
13
14
diff --git a/target/loongarch/cpu.c b/target/loongarch/cpu.c
15
index XXXXXXX..XXXXXXX 100644
16
--- a/target/loongarch/cpu.c
17
+++ b/target/loongarch/cpu.c
18
@@ -XXX,XX +XXX,XX @@ static void loongarch_cpu_realizefn(DeviceState *dev, Error **errp)
19
static void loongarch_qemu_write(void *opaque, hwaddr addr,
20
uint64_t val, unsigned size)
21
{
22
+ qemu_log_mask(LOG_UNIMP, "[%s]: Unimplemented reg 0x%" HWADDR_PRIx "\n",
23
+ __func__, addr);
24
}
25
26
static uint64_t loongarch_qemu_read(void *opaque, hwaddr addr, unsigned size)
27
--
28
2.39.1
29
30
diff view generated by jsdifflib
New patch
[PULL 02/31] target/loongarch: Remove duplicated disas_set_info assignment
1
From: Philippe Mathieu-Daudé <philmd@linaro.org>
1
2
3
Commit 228021f05e ("target/loongarch: Add core definition") sets
4
disas_set_info to loongarch_cpu_disas_set_info. Probably due to
5
a failed git-rebase, commit ca61e75071 ("target/loongarch: Add gdb
6
support") also sets it to the same value. Remove the duplication.
7
8
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
9
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
10
Reviewed-by: Song Gao <gaosong@loongson.cn>
11
Message-Id: <20230821125959.28666-3-philmd@linaro.org>
12
Signed-off-by: Song Gao <gaosong@loongson.cn>
13
---
14
target/loongarch/cpu.c | 1 -
15
1 file changed, 1 deletion(-)
16
17
diff --git a/target/loongarch/cpu.c b/target/loongarch/cpu.c
18
index XXXXXXX..XXXXXXX 100644
19
--- a/target/loongarch/cpu.c
20
+++ b/target/loongarch/cpu.c
21
@@ -XXX,XX +XXX,XX @@ static void loongarch_cpu_class_init(ObjectClass *c, void *data)
22
cc->disas_set_info = loongarch_cpu_disas_set_info;
23
cc->gdb_read_register = loongarch_cpu_gdb_read_register;
24
cc->gdb_write_register = loongarch_cpu_gdb_write_register;
25
- cc->disas_set_info = loongarch_cpu_disas_set_info;
26
cc->gdb_num_core_regs = 35;
27
cc->gdb_core_xml_file = "loongarch-base64.xml";
28
cc->gdb_stop_before_watchpoint = true;
29
--
30
2.39.1
31
32
diff view generated by jsdifflib
New patch
[PULL 03/31] target/loongarch: Fix loongarch_la464_initfn() misses setting LSPW
1
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
2
Signed-off-by: Song Gao <gaosong@loongson.cn>
3
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
4
Message-ID: <20230817093121.1053890-11-gaosong@loongson.cn>
5
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
6
Message-Id: <20230821125959.28666-4-philmd@linaro.org>
7
---
8
target/loongarch/cpu.c | 1 +
9
1 file changed, 1 insertion(+)
1
10
11
diff --git a/target/loongarch/cpu.c b/target/loongarch/cpu.c
12
index XXXXXXX..XXXXXXX 100644
13
--- a/target/loongarch/cpu.c
14
+++ b/target/loongarch/cpu.c
15
@@ -XXX,XX +XXX,XX @@ static void loongarch_la464_initfn(Object *obj)
16
data = FIELD_DP32(data, CPUCFG2, LSX, 1),
17
data = FIELD_DP32(data, CPUCFG2, LLFTP, 1);
18
data = FIELD_DP32(data, CPUCFG2, LLFTP_VER, 1);
19
+ data = FIELD_DP32(data, CPUCFG2, LSPW, 1);
20
data = FIELD_DP32(data, CPUCFG2, LAM, 1);
21
env->cpucfg[2] = data;
22
23
--
24
2.39.1
25
26
diff view generated by jsdifflib
New patch
[PULL 04/31] target/loongarch: Introduce abstract TYPE_LOONGARCH64_CPU
1
From: Philippe Mathieu-Daudé <philmd@linaro.org>
1
2
3
In preparation of introducing TYPE_LOONGARCH32_CPU, introduce
4
an abstract TYPE_LOONGARCH64_CPU.
5
6
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
7
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
8
Message-Id: <20230821125959.28666-5-philmd@linaro.org>
9
Signed-off-by: Song Gao <gaosong@loongson.cn>
10
---
11
target/loongarch/cpu.c | 12 +++++++++---
12
target/loongarch/cpu.h | 1 +
13
2 files changed, 10 insertions(+), 3 deletions(-)
14
15
diff --git a/target/loongarch/cpu.c b/target/loongarch/cpu.c
16
index XXXXXXX..XXXXXXX 100644
17
--- a/target/loongarch/cpu.c
18
+++ b/target/loongarch/cpu.c
19
@@ -XXX,XX +XXX,XX @@ static void loongarch_cpu_class_init(ObjectClass *c, void *data)
20
#endif
21
}
22
23
-#define DEFINE_LOONGARCH_CPU_TYPE(model, initfn) \
24
+#define DEFINE_LOONGARCH_CPU_TYPE(size, model, initfn) \
25
{ \
26
- .parent = TYPE_LOONGARCH_CPU, \
27
+ .parent = TYPE_LOONGARCH##size##_CPU, \
28
.instance_init = initfn, \
29
.name = LOONGARCH_CPU_TYPE_NAME(model), \
30
}
31
@@ -XXX,XX +XXX,XX @@ static const TypeInfo loongarch_cpu_type_infos[] = {
32
.class_size = sizeof(LoongArchCPUClass),
33
.class_init = loongarch_cpu_class_init,
34
},
35
- DEFINE_LOONGARCH_CPU_TYPE("la464", loongarch_la464_initfn),
36
+ {
37
+ .name = TYPE_LOONGARCH64_CPU,
38
+ .parent = TYPE_LOONGARCH_CPU,
39
+
40
+ .abstract = true,
41
+ },
42
+ DEFINE_LOONGARCH_CPU_TYPE(64, "la464", loongarch_la464_initfn),
43
};
44
45
DEFINE_TYPES(loongarch_cpu_type_infos)
46
diff --git a/target/loongarch/cpu.h b/target/loongarch/cpu.h
47
index XXXXXXX..XXXXXXX 100644
48
--- a/target/loongarch/cpu.h
49
+++ b/target/loongarch/cpu.h
50
@@ -XXX,XX +XXX,XX @@ struct ArchCPU {
51
};
52
53
#define TYPE_LOONGARCH_CPU "loongarch-cpu"
54
+#define TYPE_LOONGARCH64_CPU "loongarch64-cpu"
55
56
OBJECT_DECLARE_CPU_TYPE(LoongArchCPU, LoongArchCPUClass,
57
LOONGARCH_CPU)
58
--
59
2.39.1
60
61
diff view generated by jsdifflib
New patch
[PULL 05/31] target/loongarch: Extract 64-bit specifics to loongarch64_cpu_class_init
1
From: Philippe Mathieu-Daudé <philmd@linaro.org>
1
2
3
Extract loongarch64 specific code from loongarch_cpu_class_init()
4
to a new loongarch64_cpu_class_init().
5
6
In preparation of supporting loongarch32 cores, rename these
7
functions using the '64' suffix.
8
9
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
10
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
11
Message-Id: <20230821125959.28666-6-philmd@linaro.org>
12
Signed-off-by: Song Gao <gaosong@loongson.cn>
13
---
14
target/loongarch/cpu.c | 23 +++++++++++++++--------
15
1 file changed, 15 insertions(+), 8 deletions(-)
16
17
diff --git a/target/loongarch/cpu.c b/target/loongarch/cpu.c
18
index XXXXXXX..XXXXXXX 100644
19
--- a/target/loongarch/cpu.c
20
+++ b/target/loongarch/cpu.c
21
@@ -XXX,XX +XXX,XX @@ static const struct SysemuCPUOps loongarch_sysemu_ops = {
22
};
23
#endif
24
25
-static gchar *loongarch_gdb_arch_name(CPUState *cs)
26
-{
27
- return g_strdup("loongarch64");
28
-}
29
-
30
static void loongarch_cpu_class_init(ObjectClass *c, void *data)
31
{
32
LoongArchCPUClass *lacc = LOONGARCH_CPU_CLASS(c);
33
@@ -XXX,XX +XXX,XX @@ static void loongarch_cpu_class_init(ObjectClass *c, void *data)
34
cc->disas_set_info = loongarch_cpu_disas_set_info;
35
cc->gdb_read_register = loongarch_cpu_gdb_read_register;
36
cc->gdb_write_register = loongarch_cpu_gdb_write_register;
37
- cc->gdb_num_core_regs = 35;
38
- cc->gdb_core_xml_file = "loongarch-base64.xml";
39
cc->gdb_stop_before_watchpoint = true;
40
- cc->gdb_arch_name = loongarch_gdb_arch_name;
41
42
#ifdef CONFIG_TCG
43
cc->tcg_ops = &loongarch_tcg_ops;
44
#endif
45
}
46
47
+static gchar *loongarch64_gdb_arch_name(CPUState *cs)
48
+{
49
+ return g_strdup("loongarch64");
50
+}
51
+
52
+static void loongarch64_cpu_class_init(ObjectClass *c, void *data)
53
+{
54
+ CPUClass *cc = CPU_CLASS(c);
55
+
56
+ cc->gdb_num_core_regs = 35;
57
+ cc->gdb_core_xml_file = "loongarch-base64.xml";
58
+ cc->gdb_arch_name = loongarch64_gdb_arch_name;
59
+}
60
+
61
#define DEFINE_LOONGARCH_CPU_TYPE(size, model, initfn) \
62
{ \
63
.parent = TYPE_LOONGARCH##size##_CPU, \
64
@@ -XXX,XX +XXX,XX @@ static const TypeInfo loongarch_cpu_type_infos[] = {
65
.parent = TYPE_LOONGARCH_CPU,
66
67
.abstract = true,
68
+ .class_init = loongarch64_cpu_class_init,
69
},
70
DEFINE_LOONGARCH_CPU_TYPE(64, "la464", loongarch_la464_initfn),
71
};
72
--
73
2.39.1
74
75
diff view generated by jsdifflib
New patch
[PULL 06/31] target/loongarch: Add function to check current arch
1
From: Jiajie Chen <c@jia.je>
1
2
3
Add is_la64 function to check if the current cpucfg[1].arch equals to
4
2(LA64).
5
6
Signed-off-by: Jiajie Chen <c@jia.je>
7
Co-authored-by: Richard Henderson <richard.henderson@linaro.org>
8
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
9
Signed-off-by: Song Gao <gaosong@loongson.cn>
10
Message-ID: <20230817093121.1053890-2-gaosong@loongson.cn>
11
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
12
Message-Id: <20230821125959.28666-7-philmd@linaro.org>
13
---
14
target/loongarch/cpu.h | 10 ++++++++++
15
1 file changed, 10 insertions(+)
16
17
diff --git a/target/loongarch/cpu.h b/target/loongarch/cpu.h
18
index XXXXXXX..XXXXXXX 100644
19
--- a/target/loongarch/cpu.h
20
+++ b/target/loongarch/cpu.h
21
@@ -XXX,XX +XXX,XX @@ FIELD(CPUCFG1, HP, 24, 1)
22
FIELD(CPUCFG1, IOCSR_BRD, 25, 1)
23
FIELD(CPUCFG1, MSG_INT, 26, 1)
24
25
+/* cpucfg[1].arch */
26
+#define CPUCFG1_ARCH_LA32R 0
27
+#define CPUCFG1_ARCH_LA32 1
28
+#define CPUCFG1_ARCH_LA64 2
29
+
30
/* cpucfg[2] bits */
31
FIELD(CPUCFG2, FP, 0, 1)
32
FIELD(CPUCFG2, FP_SP, 1, 1)
33
@@ -XXX,XX +XXX,XX @@ static inline int cpu_mmu_index(CPULoongArchState *env, bool ifetch)
34
#endif
35
}
36
37
+static inline bool is_la64(CPULoongArchState *env)
38
+{
39
+ return FIELD_EX32(env->cpucfg[1], CPUCFG1, ARCH) == CPUCFG1_ARCH_LA64;
40
+}
41
+
42
/*
43
* LoongArch CPUs hardware flags.
44
*/
45
--
46
2.39.1
47
48
diff view generated by jsdifflib
New patch
[PULL 07/31] target/loongarch: Add new object class for loongarch32 cpus
1
From: Jiajie Chen <c@jia.je>
1
2
3
Add object class stub for future loongarch32 cpus.
4
5
Signed-off-by: Jiajie Chen <c@jia.je>
6
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
7
Signed-off-by: Song Gao <gaosong@loongson.cn>
8
Message-ID: <20230817093121.1053890-3-gaosong@loongson.cn>
9
[Rebased on TYPE_LOONGARCH64_CPU introduction]
10
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
11
Message-Id: <20230821125959.28666-8-philmd@linaro.org>
12
---
13
target/loongarch/cpu.c | 11 +++++++++++
14
target/loongarch/cpu.h | 1 +
15
2 files changed, 12 insertions(+)
16
17
diff --git a/target/loongarch/cpu.c b/target/loongarch/cpu.c
18
index XXXXXXX..XXXXXXX 100644
19
--- a/target/loongarch/cpu.c
20
+++ b/target/loongarch/cpu.c
21
@@ -XXX,XX +XXX,XX @@ static void loongarch_cpu_class_init(ObjectClass *c, void *data)
22
#endif
23
}
24
25
+static void loongarch32_cpu_class_init(ObjectClass *c, void *data)
26
+{
27
+}
28
+
29
static gchar *loongarch64_gdb_arch_name(CPUState *cs)
30
{
31
return g_strdup("loongarch64");
32
@@ -XXX,XX +XXX,XX @@ static const TypeInfo loongarch_cpu_type_infos[] = {
33
.class_size = sizeof(LoongArchCPUClass),
34
.class_init = loongarch_cpu_class_init,
35
},
36
+ {
37
+ .name = TYPE_LOONGARCH32_CPU,
38
+ .parent = TYPE_LOONGARCH_CPU,
39
+
40
+ .abstract = true,
41
+ .class_init = loongarch32_cpu_class_init,
42
+ },
43
{
44
.name = TYPE_LOONGARCH64_CPU,
45
.parent = TYPE_LOONGARCH_CPU,
46
diff --git a/target/loongarch/cpu.h b/target/loongarch/cpu.h
47
index XXXXXXX..XXXXXXX 100644
48
--- a/target/loongarch/cpu.h
49
+++ b/target/loongarch/cpu.h
50
@@ -XXX,XX +XXX,XX @@ struct ArchCPU {
51
};
52
53
#define TYPE_LOONGARCH_CPU "loongarch-cpu"
54
+#define TYPE_LOONGARCH32_CPU "loongarch32-cpu"
55
#define TYPE_LOONGARCH64_CPU "loongarch64-cpu"
56
57
OBJECT_DECLARE_CPU_TYPE(LoongArchCPU, LoongArchCPUClass,
58
--
59
2.39.1
60
61
diff view generated by jsdifflib
New patch
[PULL 08/31] target/loongarch: Add GDB support for loongarch32 mode
1
From: Jiajie Chen <c@jia.je>
1
2
3
GPRs and PC are 32-bit wide in loongarch32 mode.
4
5
Signed-off-by: Jiajie Chen <c@jia.je>
6
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
7
Signed-off-by: Song Gao <gaosong@loongson.cn>
8
Message-ID: <20230817093121.1053890-4-gaosong@loongson.cn>
9
[PMD: Rebased, set gdb_num_core_regs]
10
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
11
Message-Id: <20230821125959.28666-9-philmd@linaro.org>
12
---
13
configs/targets/loongarch64-softmmu.mak | 2 +-
14
gdb-xml/loongarch-base32.xml | 45 +++++++++++++++++++++++++
15
target/loongarch/cpu.c | 10 ++++++
16
target/loongarch/gdbstub.c | 32 ++++++++++++++----
17
4 files changed, 81 insertions(+), 8 deletions(-)
18
create mode 100644 gdb-xml/loongarch-base32.xml
19
20
diff --git a/configs/targets/loongarch64-softmmu.mak b/configs/targets/loongarch64-softmmu.mak
21
index XXXXXXX..XXXXXXX 100644
22
--- a/configs/targets/loongarch64-softmmu.mak
23
+++ b/configs/targets/loongarch64-softmmu.mak
24
@@ -XXX,XX +XXX,XX @@
25
TARGET_ARCH=loongarch64
26
TARGET_BASE_ARCH=loongarch
27
TARGET_SUPPORTS_MTTCG=y
28
-TARGET_XML_FILES= gdb-xml/loongarch-base64.xml gdb-xml/loongarch-fpu.xml
29
+TARGET_XML_FILES= gdb-xml/loongarch-base32.xml gdb-xml/loongarch-base64.xml gdb-xml/loongarch-fpu.xml
30
TARGET_NEED_FDT=y
31
diff --git a/gdb-xml/loongarch-base32.xml b/gdb-xml/loongarch-base32.xml
32
new file mode 100644
33
index XXXXXXX..XXXXXXX
34
--- /dev/null
35
+++ b/gdb-xml/loongarch-base32.xml
36
@@ -XXX,XX +XXX,XX @@
37
+<?xml version="1.0"?>
38
+<!-- Copyright (C) 2022 Free Software Foundation, Inc.
39
+
40
+ Copying and distribution of this file, with or without modification,
41
+ are permitted in any medium without royalty provided the copyright
42
+ notice and this notice are preserved. -->
43
+
44
+<!DOCTYPE feature SYSTEM "gdb-target.dtd">
45
+<feature name="org.gnu.gdb.loongarch.base">
46
+ <reg name="r0" bitsize="32" type="uint32" group="general"/>
47
+ <reg name="r1" bitsize="32" type="code_ptr" group="general"/>
48
+ <reg name="r2" bitsize="32" type="data_ptr" group="general"/>
49
+ <reg name="r3" bitsize="32" type="data_ptr" group="general"/>
50
+ <reg name="r4" bitsize="32" type="uint32" group="general"/>
51
+ <reg name="r5" bitsize="32" type="uint32" group="general"/>
52
+ <reg name="r6" bitsize="32" type="uint32" group="general"/>
53
+ <reg name="r7" bitsize="32" type="uint32" group="general"/>
54
+ <reg name="r8" bitsize="32" type="uint32" group="general"/>
55
+ <reg name="r9" bitsize="32" type="uint32" group="general"/>
56
+ <reg name="r10" bitsize="32" type="uint32" group="general"/>
57
+ <reg name="r11" bitsize="32" type="uint32" group="general"/>
58
+ <reg name="r12" bitsize="32" type="uint32" group="general"/>
59
+ <reg name="r13" bitsize="32" type="uint32" group="general"/>
60
+ <reg name="r14" bitsize="32" type="uint32" group="general"/>
61
+ <reg name="r15" bitsize="32" type="uint32" group="general"/>
62
+ <reg name="r16" bitsize="32" type="uint32" group="general"/>
63
+ <reg name="r17" bitsize="32" type="uint32" group="general"/>
64
+ <reg name="r18" bitsize="32" type="uint32" group="general"/>
65
+ <reg name="r19" bitsize="32" type="uint32" group="general"/>
66
+ <reg name="r20" bitsize="32" type="uint32" group="general"/>
67
+ <reg name="r21" bitsize="32" type="uint32" group="general"/>
68
+ <reg name="r22" bitsize="32" type="data_ptr" group="general"/>
69
+ <reg name="r23" bitsize="32" type="uint32" group="general"/>
70
+ <reg name="r24" bitsize="32" type="uint32" group="general"/>
71
+ <reg name="r25" bitsize="32" type="uint32" group="general"/>
72
+ <reg name="r26" bitsize="32" type="uint32" group="general"/>
73
+ <reg name="r27" bitsize="32" type="uint32" group="general"/>
74
+ <reg name="r28" bitsize="32" type="uint32" group="general"/>
75
+ <reg name="r29" bitsize="32" type="uint32" group="general"/>
76
+ <reg name="r30" bitsize="32" type="uint32" group="general"/>
77
+ <reg name="r31" bitsize="32" type="uint32" group="general"/>
78
+ <reg name="orig_a0" bitsize="32" type="uint32" group="general"/>
79
+ <reg name="pc" bitsize="32" type="code_ptr" group="general"/>
80
+ <reg name="badv" bitsize="32" type="code_ptr" group="general"/>
81
+</feature>
82
diff --git a/target/loongarch/cpu.c b/target/loongarch/cpu.c
83
index XXXXXXX..XXXXXXX 100644
84
--- a/target/loongarch/cpu.c
85
+++ b/target/loongarch/cpu.c
86
@@ -XXX,XX +XXX,XX @@ static void loongarch_cpu_class_init(ObjectClass *c, void *data)
87
#endif
88
}
89
90
+static gchar *loongarch32_gdb_arch_name(CPUState *cs)
91
+{
92
+ return g_strdup("loongarch32");
93
+}
94
+
95
static void loongarch32_cpu_class_init(ObjectClass *c, void *data)
96
{
97
+ CPUClass *cc = CPU_CLASS(c);
98
+
99
+ cc->gdb_num_core_regs = 35;
100
+ cc->gdb_core_xml_file = "loongarch-base32.xml";
101
+ cc->gdb_arch_name = loongarch32_gdb_arch_name;
102
}
103
104
static gchar *loongarch64_gdb_arch_name(CPUState *cs)
105
diff --git a/target/loongarch/gdbstub.c b/target/loongarch/gdbstub.c
106
index XXXXXXX..XXXXXXX 100644
107
--- a/target/loongarch/gdbstub.c
108
+++ b/target/loongarch/gdbstub.c
109
@@ -XXX,XX +XXX,XX @@ int loongarch_cpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n)
110
{
111
LoongArchCPU *cpu = LOONGARCH_CPU(cs);
112
CPULoongArchState *env = &cpu->env;
113
+ uint64_t val;
114
115
if (0 <= n && n < 32) {
116
- return gdb_get_regl(mem_buf, env->gpr[n]);
117
+ val = env->gpr[n];
118
} else if (n == 32) {
119
/* orig_a0 */
120
- return gdb_get_regl(mem_buf, 0);
121
+ val = 0;
122
} else if (n == 33) {
123
- return gdb_get_regl(mem_buf, env->pc);
124
+ val = env->pc;
125
} else if (n == 34) {
126
- return gdb_get_regl(mem_buf, env->CSR_BADV);
127
+ val = env->CSR_BADV;
128
+ }
129
+
130
+ if (0 <= n && n <= 34) {
131
+ if (is_la64(env)) {
132
+ return gdb_get_reg64(mem_buf, val);
133
+ } else {
134
+ return gdb_get_reg32(mem_buf, val);
135
+ }
136
}
137
return 0;
138
}
139
@@ -XXX,XX +XXX,XX @@ int loongarch_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n)
140
{
141
LoongArchCPU *cpu = LOONGARCH_CPU(cs);
142
CPULoongArchState *env = &cpu->env;
143
- target_ulong tmp = ldtul_p(mem_buf);
144
+ target_ulong tmp;
145
+ int read_length;
146
int length = 0;
147
148
+ if (is_la64(env)) {
149
+ tmp = ldq_p(mem_buf);
150
+ read_length = 8;
151
+ } else {
152
+ tmp = ldl_p(mem_buf);
153
+ read_length = 4;
154
+ }
155
+
156
if (0 <= n && n < 32) {
157
env->gpr[n] = tmp;
158
- length = sizeof(target_ulong);
159
+ length = read_length;
160
} else if (n == 33) {
161
env->pc = tmp;
162
- length = sizeof(target_ulong);
163
+ length = read_length;
164
}
165
return length;
166
}
167
--
168
2.39.1
169
170
diff view generated by jsdifflib
New patch
[PULL 09/31] target/loongarch: Support LoongArch32 TLB entry
1
From: Jiajie Chen <c@jia.je>
1
2
3
The TLB entry of LA32 lacks NR, NX and RPLV and they are hardwired to
4
zero in LoongArch32.
5
6
Signed-off-by: Jiajie Chen <c@jia.je>
7
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
8
Signed-off-by: Song Gao <gaosong@loongson.cn>
9
Message-ID: <20230822032724.1353391-2-gaosong@loongson.cn>
10
Message-Id: <20230822071405.35386-2-philmd@linaro.org>
11
---
12
target/loongarch/cpu-csr.h | 9 +++++----
13
target/loongarch/tlb_helper.c | 17 ++++++++++++-----
14
2 files changed, 17 insertions(+), 9 deletions(-)
15
16
diff --git a/target/loongarch/cpu-csr.h b/target/loongarch/cpu-csr.h
17
index XXXXXXX..XXXXXXX 100644
18
--- a/target/loongarch/cpu-csr.h
19
+++ b/target/loongarch/cpu-csr.h
20
@@ -XXX,XX +XXX,XX @@ FIELD(TLBENTRY, D, 1, 1)
21
FIELD(TLBENTRY, PLV, 2, 2)
22
FIELD(TLBENTRY, MAT, 4, 2)
23
FIELD(TLBENTRY, G, 6, 1)
24
-FIELD(TLBENTRY, PPN, 12, 36)
25
-FIELD(TLBENTRY, NR, 61, 1)
26
-FIELD(TLBENTRY, NX, 62, 1)
27
-FIELD(TLBENTRY, RPLV, 63, 1)
28
+FIELD(TLBENTRY_32, PPN, 8, 24)
29
+FIELD(TLBENTRY_64, PPN, 12, 36)
30
+FIELD(TLBENTRY_64, NR, 61, 1)
31
+FIELD(TLBENTRY_64, NX, 62, 1)
32
+FIELD(TLBENTRY_64, RPLV, 63, 1)
33
34
#define LOONGARCH_CSR_ASID 0x18 /* Address space identifier */
35
FIELD(CSR_ASID, ASID, 0, 10)
36
diff --git a/target/loongarch/tlb_helper.c b/target/loongarch/tlb_helper.c
37
index XXXXXXX..XXXXXXX 100644
38
--- a/target/loongarch/tlb_helper.c
39
+++ b/target/loongarch/tlb_helper.c
40
@@ -XXX,XX +XXX,XX @@ static int loongarch_map_tlb_entry(CPULoongArchState *env, hwaddr *physical,
41
tlb_v = FIELD_EX64(tlb_entry, TLBENTRY, V);
42
tlb_d = FIELD_EX64(tlb_entry, TLBENTRY, D);
43
tlb_plv = FIELD_EX64(tlb_entry, TLBENTRY, PLV);
44
- tlb_ppn = FIELD_EX64(tlb_entry, TLBENTRY, PPN);
45
- tlb_nx = FIELD_EX64(tlb_entry, TLBENTRY, NX);
46
- tlb_nr = FIELD_EX64(tlb_entry, TLBENTRY, NR);
47
- tlb_rplv = FIELD_EX64(tlb_entry, TLBENTRY, RPLV);
48
+ if (is_la64(env)) {
49
+ tlb_ppn = FIELD_EX64(tlb_entry, TLBENTRY_64, PPN);
50
+ tlb_nx = FIELD_EX64(tlb_entry, TLBENTRY_64, NX);
51
+ tlb_nr = FIELD_EX64(tlb_entry, TLBENTRY_64, NR);
52
+ tlb_rplv = FIELD_EX64(tlb_entry, TLBENTRY_64, RPLV);
53
+ } else {
54
+ tlb_ppn = FIELD_EX64(tlb_entry, TLBENTRY_32, PPN);
55
+ tlb_nx = 0;
56
+ tlb_nr = 0;
57
+ tlb_rplv = 0;
58
+ }
59
60
/* Check access rights */
61
if (!tlb_v) {
62
@@ -XXX,XX +XXX,XX @@ static int loongarch_map_tlb_entry(CPULoongArchState *env, hwaddr *physical,
63
* tlb_entry contains ppn[47:12] while 16KiB ppn is [47:15]
64
* need adjust.
65
*/
66
- *physical = (tlb_ppn << R_TLBENTRY_PPN_SHIFT) |
67
+ *physical = (tlb_ppn << R_TLBENTRY_64_PPN_SHIFT) |
68
(address & MAKE_64BIT_MASK(0, tlb_ps));
69
*prot = PAGE_READ;
70
if (tlb_d) {
71
--
72
2.39.1
diff view generated by jsdifflib
New patch
[PULL 10/31] target/loongarch: Support LoongArch32 DMW
1
From: Jiajie Chen <c@jia.je>
1
2
3
LA32 uses a different encoding for CSR.DMW and a new direct mapping
4
mechanism.
5
6
Signed-off-by: Jiajie Chen <c@jia.je>
7
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
8
Signed-off-by: Song Gao <gaosong@loongson.cn>
9
Message-ID: <20230822032724.1353391-3-gaosong@loongson.cn>
10
Message-Id: <20230822071405.35386-3-philmd@linaro.org>
11
---
12
target/loongarch/cpu-csr.h | 7 +++----
13
target/loongarch/tlb_helper.c | 26 +++++++++++++++++++++++---
14
2 files changed, 26 insertions(+), 7 deletions(-)
15
16
diff --git a/target/loongarch/cpu-csr.h b/target/loongarch/cpu-csr.h
17
index XXXXXXX..XXXXXXX 100644
18
--- a/target/loongarch/cpu-csr.h
19
+++ b/target/loongarch/cpu-csr.h
20
@@ -XXX,XX +XXX,XX @@ FIELD(CSR_DMW, PLV1, 1, 1)
21
FIELD(CSR_DMW, PLV2, 2, 1)
22
FIELD(CSR_DMW, PLV3, 3, 1)
23
FIELD(CSR_DMW, MAT, 4, 2)
24
-FIELD(CSR_DMW, VSEG, 60, 4)
25
-
26
-#define dmw_va2pa(va) \
27
- (va & MAKE_64BIT_MASK(0, TARGET_VIRT_ADDR_SPACE_BITS))
28
+FIELD(CSR_DMW_32, PSEG, 25, 3)
29
+FIELD(CSR_DMW_32, VSEG, 29, 3)
30
+FIELD(CSR_DMW_64, VSEG, 60, 4)
31
32
/* Debug CSRs */
33
#define LOONGARCH_CSR_DBG 0x500 /* debug config */
34
diff --git a/target/loongarch/tlb_helper.c b/target/loongarch/tlb_helper.c
35
index XXXXXXX..XXXXXXX 100644
36
--- a/target/loongarch/tlb_helper.c
37
+++ b/target/loongarch/tlb_helper.c
38
@@ -XXX,XX +XXX,XX @@ static int loongarch_map_address(CPULoongArchState *env, hwaddr *physical,
39
return TLBRET_NOMATCH;
40
}
41
42
+static hwaddr dmw_va2pa(CPULoongArchState *env, target_ulong va,
43
+ target_ulong dmw)
44
+{
45
+ if (is_la64(env)) {
46
+ return va & TARGET_VIRT_MASK;
47
+ } else {
48
+ uint32_t pseg = FIELD_EX32(dmw, CSR_DMW_32, PSEG);
49
+ return (va & MAKE_64BIT_MASK(0, R_CSR_DMW_32_VSEG_SHIFT)) | \
50
+ (pseg << R_CSR_DMW_32_VSEG_SHIFT);
51
+ }
52
+}
53
+
54
static int get_physical_address(CPULoongArchState *env, hwaddr *physical,
55
int *prot, target_ulong address,
56
MMUAccessType access_type, int mmu_idx)
57
@@ -XXX,XX +XXX,XX @@ static int get_physical_address(CPULoongArchState *env, hwaddr *physical,
58
}
59
60
plv = kernel_mode | (user_mode << R_CSR_DMW_PLV3_SHIFT);
61
- base_v = address >> R_CSR_DMW_VSEG_SHIFT;
62
+ if (is_la64(env)) {
63
+ base_v = address >> R_CSR_DMW_64_VSEG_SHIFT;
64
+ } else {
65
+ base_v = address >> R_CSR_DMW_32_VSEG_SHIFT;
66
+ }
67
/* Check direct map window */
68
for (int i = 0; i < 4; i++) {
69
- base_c = FIELD_EX64(env->CSR_DMW[i], CSR_DMW, VSEG);
70
+ if (is_la64(env)) {
71
+ base_c = FIELD_EX64(env->CSR_DMW[i], CSR_DMW_64, VSEG);
72
+ } else {
73
+ base_c = FIELD_EX64(env->CSR_DMW[i], CSR_DMW_32, VSEG);
74
+ }
75
if ((plv & env->CSR_DMW[i]) && (base_c == base_v)) {
76
- *physical = dmw_va2pa(address);
77
+ *physical = dmw_va2pa(env, address, env->CSR_DMW[i]);
78
*prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
79
return TLBRET_MATCH;
80
}
81
--
82
2.39.1
diff view generated by jsdifflib
New patch
[PULL 11/31] target/loongarch: Support LoongArch32 VPPN
1
From: Jiajie Chen <c@jia.je>
1
2
3
VPPN of TLBEHI/TLBREHI is limited to 19 bits in LA32.
4
5
Signed-off-by: Jiajie Chen <c@jia.je>
6
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
7
Signed-off-by: Song Gao <gaosong@loongson.cn>
8
Message-ID: <20230822032724.1353391-4-gaosong@loongson.cn>
9
Message-Id: <20230822071405.35386-4-philmd@linaro.org>
10
---
11
target/loongarch/cpu-csr.h | 6 ++++--
12
target/loongarch/tlb_helper.c | 23 ++++++++++++++++++-----
13
2 files changed, 22 insertions(+), 7 deletions(-)
14
15
diff --git a/target/loongarch/cpu-csr.h b/target/loongarch/cpu-csr.h
16
index XXXXXXX..XXXXXXX 100644
17
--- a/target/loongarch/cpu-csr.h
18
+++ b/target/loongarch/cpu-csr.h
19
@@ -XXX,XX +XXX,XX @@ FIELD(CSR_TLBIDX, PS, 24, 6)
20
FIELD(CSR_TLBIDX, NE, 31, 1)
21
22
#define LOONGARCH_CSR_TLBEHI 0x11 /* TLB EntryHi */
23
-FIELD(CSR_TLBEHI, VPPN, 13, 35)
24
+FIELD(CSR_TLBEHI_32, VPPN, 13, 19)
25
+FIELD(CSR_TLBEHI_64, VPPN, 13, 35)
26
27
#define LOONGARCH_CSR_TLBELO0 0x12 /* TLB EntryLo0 */
28
#define LOONGARCH_CSR_TLBELO1 0x13 /* TLB EntryLo1 */
29
@@ -XXX,XX +XXX,XX @@ FIELD(CSR_TLBRERA, PC, 2, 62)
30
#define LOONGARCH_CSR_TLBRELO1 0x8d /* TLB refill entrylo1 */
31
#define LOONGARCH_CSR_TLBREHI 0x8e /* TLB refill entryhi */
32
FIELD(CSR_TLBREHI, PS, 0, 6)
33
-FIELD(CSR_TLBREHI, VPPN, 13, 35)
34
+FIELD(CSR_TLBREHI_32, VPPN, 13, 19)
35
+FIELD(CSR_TLBREHI_64, VPPN, 13, 35)
36
#define LOONGARCH_CSR_TLBRPRMD 0x8f /* TLB refill mode info */
37
FIELD(CSR_TLBRPRMD, PPLV, 0, 2)
38
FIELD(CSR_TLBRPRMD, PIE, 2, 1)
39
diff --git a/target/loongarch/tlb_helper.c b/target/loongarch/tlb_helper.c
40
index XXXXXXX..XXXXXXX 100644
41
--- a/target/loongarch/tlb_helper.c
42
+++ b/target/loongarch/tlb_helper.c
43
@@ -XXX,XX +XXX,XX @@ static void raise_mmu_exception(CPULoongArchState *env, target_ulong address,
44
45
if (tlb_error == TLBRET_NOMATCH) {
46
env->CSR_TLBRBADV = address;
47
- env->CSR_TLBREHI = FIELD_DP64(env->CSR_TLBREHI, CSR_TLBREHI, VPPN,
48
- extract64(address, 13, 35));
49
+ if (is_la64(env)) {
50
+ env->CSR_TLBREHI = FIELD_DP64(env->CSR_TLBREHI, CSR_TLBREHI_64,
51
+ VPPN, extract64(address, 13, 35));
52
+ } else {
53
+ env->CSR_TLBREHI = FIELD_DP64(env->CSR_TLBREHI, CSR_TLBREHI_32,
54
+ VPPN, extract64(address, 13, 19));
55
+ }
56
} else {
57
if (!FIELD_EX64(env->CSR_DBG, CSR_DBG, DST)) {
58
env->CSR_BADV = address;
59
@@ -XXX,XX +XXX,XX @@ static void fill_tlb_entry(CPULoongArchState *env, int index)
60
61
if (FIELD_EX64(env->CSR_TLBRERA, CSR_TLBRERA, ISTLBR)) {
62
csr_ps = FIELD_EX64(env->CSR_TLBREHI, CSR_TLBREHI, PS);
63
- csr_vppn = FIELD_EX64(env->CSR_TLBREHI, CSR_TLBREHI, VPPN);
64
+ if (is_la64(env)) {
65
+ csr_vppn = FIELD_EX64(env->CSR_TLBREHI, CSR_TLBREHI_64, VPPN);
66
+ } else {
67
+ csr_vppn = FIELD_EX64(env->CSR_TLBREHI, CSR_TLBREHI_32, VPPN);
68
+ }
69
lo0 = env->CSR_TLBRELO0;
70
lo1 = env->CSR_TLBRELO1;
71
} else {
72
csr_ps = FIELD_EX64(env->CSR_TLBIDX, CSR_TLBIDX, PS);
73
- csr_vppn = FIELD_EX64(env->CSR_TLBEHI, CSR_TLBEHI, VPPN);
74
+ if (is_la64(env)) {
75
+ csr_vppn = FIELD_EX64(env->CSR_TLBEHI, CSR_TLBEHI_64, VPPN);
76
+ } else {
77
+ csr_vppn = FIELD_EX64(env->CSR_TLBEHI, CSR_TLBEHI_32, VPPN);
78
+ }
79
lo0 = env->CSR_TLBELO0;
80
lo1 = env->CSR_TLBELO1;
81
}
82
@@ -XXX,XX +XXX,XX @@ void helper_tlbfill(CPULoongArchState *env)
83
84
if (pagesize == stlb_ps) {
85
/* Only write into STLB bits [47:13] */
86
- address = entryhi & ~MAKE_64BIT_MASK(0, R_CSR_TLBEHI_VPPN_SHIFT);
87
+ address = entryhi & ~MAKE_64BIT_MASK(0, R_CSR_TLBEHI_64_VPPN_SHIFT);
88
89
/* Choose one set ramdomly */
90
set = get_random_tlb(0, 7);
91
--
92
2.39.1
diff view generated by jsdifflib
New patch
[PULL 12/31] target/loongarch: Add LA64 & VA32 to DisasContext
1
From: Jiajie Chen <c@jia.je>
1
2
3
Add LA64 and VA32(32-bit Virtual Address) to DisasContext to allow the
4
translator to reject doubleword instructions in LA32 mode for example.
5
6
Signed-off-by: Jiajie Chen <c@jia.je>
7
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
8
Signed-off-by: Song Gao <gaosong@loongson.cn>
9
Message-ID: <20230822032724.1353391-5-gaosong@loongson.cn>
10
Message-Id: <20230822071405.35386-5-philmd@linaro.org>
11
---
12
target/loongarch/cpu.h | 13 +++++++++++++
13
target/loongarch/translate.c | 3 +++
14
target/loongarch/translate.h | 2 ++
15
3 files changed, 18 insertions(+)
16
17
diff --git a/target/loongarch/cpu.h b/target/loongarch/cpu.h
18
index XXXXXXX..XXXXXXX 100644
19
--- a/target/loongarch/cpu.h
20
+++ b/target/loongarch/cpu.h
21
@@ -XXX,XX +XXX,XX @@ static inline bool is_la64(CPULoongArchState *env)
22
return FIELD_EX32(env->cpucfg[1], CPUCFG1, ARCH) == CPUCFG1_ARCH_LA64;
23
}
24
25
+static inline bool is_va32(CPULoongArchState *env)
26
+{
27
+ /* VA32 if !LA64 or VA32L[1-3] */
28
+ bool va32 = !is_la64(env);
29
+ uint64_t plv = FIELD_EX64(env->CSR_CRMD, CSR_CRMD, PLV);
30
+ if (plv >= 1 && (FIELD_EX64(env->CSR_MISC, CSR_MISC, VA32) & (1 << plv))) {
31
+ va32 = true;
32
+ }
33
+ return va32;
34
+}
35
+
36
/*
37
* LoongArch CPUs hardware flags.
38
*/
39
@@ -XXX,XX +XXX,XX @@ static inline bool is_la64(CPULoongArchState *env)
40
#define HW_FLAGS_CRMD_PG R_CSR_CRMD_PG_MASK /* 0x10 */
41
#define HW_FLAGS_EUEN_FPE 0x04
42
#define HW_FLAGS_EUEN_SXE 0x08
43
+#define HW_FLAGS_VA32 0x20
44
45
static inline void cpu_get_tb_cpu_state(CPULoongArchState *env, vaddr *pc,
46
uint64_t *cs_base, uint32_t *flags)
47
@@ -XXX,XX +XXX,XX @@ static inline void cpu_get_tb_cpu_state(CPULoongArchState *env, vaddr *pc,
48
*flags = env->CSR_CRMD & (R_CSR_CRMD_PLV_MASK | R_CSR_CRMD_PG_MASK);
49
*flags |= FIELD_EX64(env->CSR_EUEN, CSR_EUEN, FPE) * HW_FLAGS_EUEN_FPE;
50
*flags |= FIELD_EX64(env->CSR_EUEN, CSR_EUEN, SXE) * HW_FLAGS_EUEN_SXE;
51
+ *flags |= is_va32(env) * HW_FLAGS_VA32;
52
}
53
54
void loongarch_cpu_list(void);
55
diff --git a/target/loongarch/translate.c b/target/loongarch/translate.c
56
index XXXXXXX..XXXXXXX 100644
57
--- a/target/loongarch/translate.c
58
+++ b/target/loongarch/translate.c
59
@@ -XXX,XX +XXX,XX @@ static void loongarch_tr_init_disas_context(DisasContextBase *dcbase,
60
ctx->vl = LSX_LEN;
61
}
62
63
+ ctx->la64 = is_la64(env);
64
+ ctx->va32 = (ctx->base.tb->flags & HW_FLAGS_VA32) != 0;
65
+
66
ctx->zero = tcg_constant_tl(0);
67
}
68
69
diff --git a/target/loongarch/translate.h b/target/loongarch/translate.h
70
index XXXXXXX..XXXXXXX 100644
71
--- a/target/loongarch/translate.h
72
+++ b/target/loongarch/translate.h
73
@@ -XXX,XX +XXX,XX @@ typedef struct DisasContext {
74
uint16_t plv;
75
int vl; /* Vector length */
76
TCGv zero;
77
+ bool la64; /* LoongArch64 mode */
78
+ bool va32; /* 32-bit virtual address */
79
} DisasContext;
80
81
void generate_exception(DisasContext *ctx, int excp);
82
--
83
2.39.1
diff view generated by jsdifflib
New patch
[PULL 13/31] target/loongarch: Extract make_address_x() helper
1
From: Jiajie Chen <c@jia.je>
1
2
3
Signed-off-by: Jiajie Chen <c@jia.je>
4
Co-authored-by: Richard Henderson <richard.henderson@linaro.org>
5
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
6
Signed-off-by: Song Gao <gaosong@loongson.cn>
7
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
8
Message-ID: <20230822032724.1353391-6-gaosong@loongson.cn>
9
[PMD: Extract helper from bigger patch]
10
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
11
Message-Id: <20230822071405.35386-6-philmd@linaro.org>
12
---
13
.../loongarch/insn_trans/trans_fmemory.c.inc | 18 ++++++------------
14
target/loongarch/insn_trans/trans_lsx.c.inc | 6 ++----
15
target/loongarch/insn_trans/trans_memory.c.inc | 6 ++----
16
target/loongarch/translate.c | 12 ++++++++++++
17
4 files changed, 22 insertions(+), 20 deletions(-)
18
19
diff --git a/target/loongarch/insn_trans/trans_fmemory.c.inc b/target/loongarch/insn_trans/trans_fmemory.c.inc
20
index XXXXXXX..XXXXXXX 100644
21
--- a/target/loongarch/insn_trans/trans_fmemory.c.inc
22
+++ b/target/loongarch/insn_trans/trans_fmemory.c.inc
23
@@ -XXX,XX +XXX,XX @@ static bool gen_floadx(DisasContext *ctx, arg_frr *a, MemOp mop)
24
25
CHECK_FPE;
26
27
- addr = tcg_temp_new();
28
- tcg_gen_add_tl(addr, src1, src2);
29
+ addr = make_address_x(ctx, src1, src2);
30
tcg_gen_qemu_ld_tl(dest, addr, ctx->mem_idx, mop);
31
maybe_nanbox_load(dest, mop);
32
set_fpr(a->fd, dest);
33
@@ -XXX,XX +XXX,XX @@ static bool gen_fstorex(DisasContext *ctx, arg_frr *a, MemOp mop)
34
35
CHECK_FPE;
36
37
- addr = tcg_temp_new();
38
- tcg_gen_add_tl(addr, src1, src2);
39
+ addr = make_address_x(ctx, src1, src2);
40
tcg_gen_qemu_st_tl(src3, addr, ctx->mem_idx, mop);
41
42
return true;
43
@@ -XXX,XX +XXX,XX @@ static bool gen_fload_gt(DisasContext *ctx, arg_frr *a, MemOp mop)
44
45
CHECK_FPE;
46
47
- addr = tcg_temp_new();
48
gen_helper_asrtgt_d(cpu_env, src1, src2);
49
- tcg_gen_add_tl(addr, src1, src2);
50
+ addr = make_address_x(ctx, src1, src2);
51
tcg_gen_qemu_ld_tl(dest, addr, ctx->mem_idx, mop);
52
maybe_nanbox_load(dest, mop);
53
set_fpr(a->fd, dest);
54
@@ -XXX,XX +XXX,XX @@ static bool gen_fstore_gt(DisasContext *ctx, arg_frr *a, MemOp mop)
55
56
CHECK_FPE;
57
58
- addr = tcg_temp_new();
59
gen_helper_asrtgt_d(cpu_env, src1, src2);
60
- tcg_gen_add_tl(addr, src1, src2);
61
+ addr = make_address_x(ctx, src1, src2);
62
tcg_gen_qemu_st_tl(src3, addr, ctx->mem_idx, mop);
63
64
return true;
65
@@ -XXX,XX +XXX,XX @@ static bool gen_fload_le(DisasContext *ctx, arg_frr *a, MemOp mop)
66
67
CHECK_FPE;
68
69
- addr = tcg_temp_new();
70
gen_helper_asrtle_d(cpu_env, src1, src2);
71
- tcg_gen_add_tl(addr, src1, src2);
72
+ addr = make_address_x(ctx, src1, src2);
73
tcg_gen_qemu_ld_tl(dest, addr, ctx->mem_idx, mop);
74
maybe_nanbox_load(dest, mop);
75
set_fpr(a->fd, dest);
76
@@ -XXX,XX +XXX,XX @@ static bool gen_fstore_le(DisasContext *ctx, arg_frr *a, MemOp mop)
77
78
CHECK_FPE;
79
80
- addr = tcg_temp_new();
81
gen_helper_asrtle_d(cpu_env, src1, src2);
82
- tcg_gen_add_tl(addr, src1, src2);
83
+ addr = make_address_x(ctx, src1, src2);
84
tcg_gen_qemu_st_tl(src3, addr, ctx->mem_idx, mop);
85
86
return true;
87
diff --git a/target/loongarch/insn_trans/trans_lsx.c.inc b/target/loongarch/insn_trans/trans_lsx.c.inc
88
index XXXXXXX..XXXXXXX 100644
89
--- a/target/loongarch/insn_trans/trans_lsx.c.inc
90
+++ b/target/loongarch/insn_trans/trans_lsx.c.inc
91
@@ -XXX,XX +XXX,XX @@ static bool trans_vldx(DisasContext *ctx, arg_vrr *a)
92
93
CHECK_SXE;
94
95
- addr = tcg_temp_new();
96
src1 = gpr_src(ctx, a->rj, EXT_NONE);
97
src2 = gpr_src(ctx, a->rk, EXT_NONE);
98
val = tcg_temp_new_i128();
99
rl = tcg_temp_new_i64();
100
rh = tcg_temp_new_i64();
101
102
- tcg_gen_add_tl(addr, src1, src2);
103
+ addr = make_address_x(ctx, src1, src2);
104
tcg_gen_qemu_ld_i128(val, addr, ctx->mem_idx, MO_128 | MO_TE);
105
tcg_gen_extr_i128_i64(rl, rh, val);
106
set_vreg64(rh, a->vd, 1);
107
@@ -XXX,XX +XXX,XX @@ static bool trans_vstx(DisasContext *ctx, arg_vrr *a)
108
109
CHECK_SXE;
110
111
- addr = tcg_temp_new();
112
src1 = gpr_src(ctx, a->rj, EXT_NONE);
113
src2 = gpr_src(ctx, a->rk, EXT_NONE);
114
val = tcg_temp_new_i128();
115
ah = tcg_temp_new_i64();
116
al = tcg_temp_new_i64();
117
118
- tcg_gen_add_tl(addr, src1, src2);
119
+ addr = make_address_x(ctx, src1, src2);
120
get_vreg64(ah, a->vd, 1);
121
get_vreg64(al, a->vd, 0);
122
tcg_gen_concat_i64_i128(val, al, ah);
123
diff --git a/target/loongarch/insn_trans/trans_memory.c.inc b/target/loongarch/insn_trans/trans_memory.c.inc
124
index XXXXXXX..XXXXXXX 100644
125
--- a/target/loongarch/insn_trans/trans_memory.c.inc
126
+++ b/target/loongarch/insn_trans/trans_memory.c.inc
127
@@ -XXX,XX +XXX,XX @@ static bool gen_loadx(DisasContext *ctx, arg_rrr *a, MemOp mop)
128
TCGv dest = gpr_dst(ctx, a->rd, EXT_NONE);
129
TCGv src1 = gpr_src(ctx, a->rj, EXT_NONE);
130
TCGv src2 = gpr_src(ctx, a->rk, EXT_NONE);
131
- TCGv addr = tcg_temp_new();
132
+ TCGv addr = make_address_x(ctx, src1, src2);
133
134
- tcg_gen_add_tl(addr, src1, src2);
135
tcg_gen_qemu_ld_tl(dest, addr, ctx->mem_idx, mop);
136
gen_set_gpr(a->rd, dest, EXT_NONE);
137
138
@@ -XXX,XX +XXX,XX @@ static bool gen_storex(DisasContext *ctx, arg_rrr *a, MemOp mop)
139
TCGv data = gpr_src(ctx, a->rd, EXT_NONE);
140
TCGv src1 = gpr_src(ctx, a->rj, EXT_NONE);
141
TCGv src2 = gpr_src(ctx, a->rk, EXT_NONE);
142
- TCGv addr = tcg_temp_new();
143
+ TCGv addr = make_address_x(ctx, src1, src2);
144
145
- tcg_gen_add_tl(addr, src1, src2);
146
tcg_gen_qemu_st_tl(data, addr, ctx->mem_idx, mop);
147
148
return true;
149
diff --git a/target/loongarch/translate.c b/target/loongarch/translate.c
150
index XXXXXXX..XXXXXXX 100644
151
--- a/target/loongarch/translate.c
152
+++ b/target/loongarch/translate.c
153
@@ -XXX,XX +XXX,XX @@ static void set_fpr(int reg_num, TCGv val)
154
offsetof(CPULoongArchState, fpr[reg_num].vreg.D(0)));
155
}
156
157
+static TCGv make_address_x(DisasContext *ctx, TCGv base, TCGv addend)
158
+{
159
+ TCGv temp = NULL;
160
+
161
+ if (addend) {
162
+ temp = tcg_temp_new();
163
+ tcg_gen_add_tl(temp, base, addend);
164
+ base = temp;
165
+ }
166
+ return base;
167
+}
168
+
169
#include "decode-insns.c.inc"
170
#include "insn_trans/trans_arith.c.inc"
171
#include "insn_trans/trans_shift.c.inc"
172
--
173
2.39.1
174
175
diff view generated by jsdifflib
New patch
[PULL 14/31] target/loongarch: Extract make_address_i() helper
1
1
From: Jiajie Chen <c@jia.je>
2
3
Signed-off-by: Jiajie Chen <c@jia.je>
4
Co-authored-by: Richard Henderson <richard.henderson@linaro.org>
5
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
6
Signed-off-by: Song Gao <gaosong@loongson.cn>
7
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
8
Message-ID: <20230822032724.1353391-6-gaosong@loongson.cn>
9
[PMD: Extract helper from bigger patch]
10
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
11
Message-Id: <20230822071405.35386-7-philmd@linaro.org>
12
---
13
.../loongarch/insn_trans/trans_atomic.c.inc | 5 +--
14
.../loongarch/insn_trans/trans_branch.c.inc | 3 +-
15
.../loongarch/insn_trans/trans_fmemory.c.inc | 12 ++-----
16
target/loongarch/insn_trans/trans_lsx.c.inc | 32 +++++--------------
17
.../loongarch/insn_trans/trans_memory.c.inc | 28 +++++-----------
18
target/loongarch/translate.c | 6 ++++
19
6 files changed, 29 insertions(+), 57 deletions(-)
20
21
diff --git a/target/loongarch/insn_trans/trans_atomic.c.inc b/target/loongarch/insn_trans/trans_atomic.c.inc
22
index XXXXXXX..XXXXXXX 100644
23
--- a/target/loongarch/insn_trans/trans_atomic.c.inc
24
+++ b/target/loongarch/insn_trans/trans_atomic.c.inc
25
@@ -XXX,XX +XXX,XX @@ static bool gen_ll(DisasContext *ctx, arg_rr_i *a, MemOp mop)
26
{
27
TCGv dest = gpr_dst(ctx, a->rd, EXT_NONE);
28
TCGv src1 = gpr_src(ctx, a->rj, EXT_NONE);
29
- TCGv t0 = tcg_temp_new();
30
+ TCGv t0 = make_address_i(ctx, src1, a->imm);
31
32
- tcg_gen_addi_tl(t0, src1, a->imm);
33
tcg_gen_qemu_ld_i64(dest, t0, ctx->mem_idx, mop);
34
tcg_gen_st_tl(t0, cpu_env, offsetof(CPULoongArchState, lladdr));
35
tcg_gen_st_tl(dest, cpu_env, offsetof(CPULoongArchState, llval));
36
@@ -XXX,XX +XXX,XX @@ static bool gen_am(DisasContext *ctx, arg_rrr *a,
37
return false;
38
}
39
40
+ addr = make_address_i(ctx, addr, 0);
41
+
42
func(dest, addr, val, ctx->mem_idx, mop);
43
gen_set_gpr(a->rd, dest, EXT_NONE);
44
45
diff --git a/target/loongarch/insn_trans/trans_branch.c.inc b/target/loongarch/insn_trans/trans_branch.c.inc
46
index XXXXXXX..XXXXXXX 100644
47
--- a/target/loongarch/insn_trans/trans_branch.c.inc
48
+++ b/target/loongarch/insn_trans/trans_branch.c.inc
49
@@ -XXX,XX +XXX,XX @@ static bool trans_jirl(DisasContext *ctx, arg_jirl *a)
50
TCGv dest = gpr_dst(ctx, a->rd, EXT_NONE);
51
TCGv src1 = gpr_src(ctx, a->rj, EXT_NONE);
52
53
- tcg_gen_addi_tl(cpu_pc, src1, a->imm);
54
+ TCGv addr = make_address_i(ctx, src1, a->imm);
55
+ tcg_gen_mov_tl(cpu_pc, addr);
56
tcg_gen_movi_tl(dest, ctx->base.pc_next + 4);
57
gen_set_gpr(a->rd, dest, EXT_NONE);
58
tcg_gen_lookup_and_goto_ptr();
59
diff --git a/target/loongarch/insn_trans/trans_fmemory.c.inc b/target/loongarch/insn_trans/trans_fmemory.c.inc
60
index XXXXXXX..XXXXXXX 100644
61
--- a/target/loongarch/insn_trans/trans_fmemory.c.inc
62
+++ b/target/loongarch/insn_trans/trans_fmemory.c.inc
63
@@ -XXX,XX +XXX,XX @@ static bool gen_fload_i(DisasContext *ctx, arg_fr_i *a, MemOp mop)
64
65
CHECK_FPE;
66
67
- if (a->imm) {
68
- TCGv temp = tcg_temp_new();
69
- tcg_gen_addi_tl(temp, addr, a->imm);
70
- addr = temp;
71
- }
72
+ addr = make_address_i(ctx, addr, a->imm);
73
74
tcg_gen_qemu_ld_tl(dest, addr, ctx->mem_idx, mop);
75
maybe_nanbox_load(dest, mop);
76
@@ -XXX,XX +XXX,XX @@ static bool gen_fstore_i(DisasContext *ctx, arg_fr_i *a, MemOp mop)
77
78
CHECK_FPE;
79
80
- if (a->imm) {
81
- TCGv temp = tcg_temp_new();
82
- tcg_gen_addi_tl(temp, addr, a->imm);
83
- addr = temp;
84
- }
85
+ addr = make_address_i(ctx, addr, a->imm);
86
87
tcg_gen_qemu_st_tl(src, addr, ctx->mem_idx, mop);
88
89
diff --git a/target/loongarch/insn_trans/trans_lsx.c.inc b/target/loongarch/insn_trans/trans_lsx.c.inc
90
index XXXXXXX..XXXXXXX 100644
91
--- a/target/loongarch/insn_trans/trans_lsx.c.inc
92
+++ b/target/loongarch/insn_trans/trans_lsx.c.inc
93
@@ -XXX,XX +XXX,XX @@ TRANS(vextrins_d, gen_vv_i, gen_helper_vextrins_d)
94
95
static bool trans_vld(DisasContext *ctx, arg_vr_i *a)
96
{
97
- TCGv addr, temp;
98
+ TCGv addr;
99
TCGv_i64 rl, rh;
100
TCGv_i128 val;
101
102
@@ -XXX,XX +XXX,XX @@ static bool trans_vld(DisasContext *ctx, arg_vr_i *a)
103
rl = tcg_temp_new_i64();
104
rh = tcg_temp_new_i64();
105
106
- if (a->imm) {
107
- temp = tcg_temp_new();
108
- tcg_gen_addi_tl(temp, addr, a->imm);
109
- addr = temp;
110
- }
111
+ addr = make_address_i(ctx, addr, a->imm);
112
113
tcg_gen_qemu_ld_i128(val, addr, ctx->mem_idx, MO_128 | MO_TE);
114
tcg_gen_extr_i128_i64(rl, rh, val);
115
@@ -XXX,XX +XXX,XX @@ static bool trans_vld(DisasContext *ctx, arg_vr_i *a)
116
117
static bool trans_vst(DisasContext *ctx, arg_vr_i *a)
118
{
119
- TCGv addr, temp;
120
+ TCGv addr;
121
TCGv_i128 val;
122
TCGv_i64 ah, al;
123
124
@@ -XXX,XX +XXX,XX @@ static bool trans_vst(DisasContext *ctx, arg_vr_i *a)
125
ah = tcg_temp_new_i64();
126
al = tcg_temp_new_i64();
127
128
- if (a->imm) {
129
- temp = tcg_temp_new();
130
- tcg_gen_addi_tl(temp, addr, a->imm);
131
- addr = temp;
132
- }
133
+ addr = make_address_i(ctx, addr, a->imm);
134
135
get_vreg64(ah, a->vd, 1);
136
get_vreg64(al, a->vd, 0);
137
@@ -XXX,XX +XXX,XX @@ static bool trans_vstx(DisasContext *ctx, arg_vrr *a)
138
#define VLDREPL(NAME, MO) \
139
static bool trans_## NAME (DisasContext *ctx, arg_vr_i *a) \
140
{ \
141
- TCGv addr, temp; \
142
+ TCGv addr; \
143
TCGv_i64 val; \
144
\
145
CHECK_SXE; \
146
@@ -XXX,XX +XXX,XX @@ static bool trans_## NAME (DisasContext *ctx, arg_vr_i *a) \
147
addr = gpr_src(ctx, a->rj, EXT_NONE); \
148
val = tcg_temp_new_i64(); \
149
\
150
- if (a->imm) { \
151
- temp = tcg_temp_new(); \
152
- tcg_gen_addi_tl(temp, addr, a->imm); \
153
- addr = temp; \
154
- } \
155
+ addr = make_address_i(ctx, addr, a->imm); \
156
\
157
tcg_gen_qemu_ld_i64(val, addr, ctx->mem_idx, MO); \
158
tcg_gen_gvec_dup_i64(MO, vec_full_offset(a->vd), 16, ctx->vl/8, val); \
159
@@ -XXX,XX +XXX,XX @@ VLDREPL(vldrepl_d, MO_64)
160
#define VSTELM(NAME, MO, E) \
161
static bool trans_## NAME (DisasContext *ctx, arg_vr_ii *a) \
162
{ \
163
- TCGv addr, temp; \
164
+ TCGv addr; \
165
TCGv_i64 val; \
166
\
167
CHECK_SXE; \
168
@@ -XXX,XX +XXX,XX @@ static bool trans_## NAME (DisasContext *ctx, arg_vr_ii *a) \
169
addr = gpr_src(ctx, a->rj, EXT_NONE); \
170
val = tcg_temp_new_i64(); \
171
\
172
- if (a->imm) { \
173
- temp = tcg_temp_new(); \
174
- tcg_gen_addi_tl(temp, addr, a->imm); \
175
- addr = temp; \
176
- } \
177
+ addr = make_address_i(ctx, addr, a->imm); \
178
\
179
tcg_gen_ld_i64(val, cpu_env, \
180
offsetof(CPULoongArchState, fpr[a->vd].vreg.E(a->imm2))); \
181
diff --git a/target/loongarch/insn_trans/trans_memory.c.inc b/target/loongarch/insn_trans/trans_memory.c.inc
182
index XXXXXXX..XXXXXXX 100644
183
--- a/target/loongarch/insn_trans/trans_memory.c.inc
184
+++ b/target/loongarch/insn_trans/trans_memory.c.inc
185
@@ -XXX,XX +XXX,XX @@ static bool gen_load(DisasContext *ctx, arg_rr_i *a, MemOp mop)
186
TCGv dest = gpr_dst(ctx, a->rd, EXT_NONE);
187
TCGv addr = gpr_src(ctx, a->rj, EXT_NONE);
188
189
- if (a->imm) {
190
- TCGv temp = tcg_temp_new();
191
- tcg_gen_addi_tl(temp, addr, a->imm);
192
- addr = temp;
193
- }
194
+ addr = make_address_i(ctx, addr, a->imm);
195
196
tcg_gen_qemu_ld_tl(dest, addr, ctx->mem_idx, mop);
197
gen_set_gpr(a->rd, dest, EXT_NONE);
198
@@ -XXX,XX +XXX,XX @@ static bool gen_store(DisasContext *ctx, arg_rr_i *a, MemOp mop)
199
TCGv data = gpr_src(ctx, a->rd, EXT_NONE);
200
TCGv addr = gpr_src(ctx, a->rj, EXT_NONE);
201
202
- if (a->imm) {
203
- TCGv temp = tcg_temp_new();
204
- tcg_gen_addi_tl(temp, addr, a->imm);
205
- addr = temp;
206
- }
207
+ addr = make_address_i(ctx, addr, a->imm);
208
209
tcg_gen_qemu_st_tl(data, addr, ctx->mem_idx, mop);
210
return true;
211
@@ -XXX,XX +XXX,XX @@ static bool gen_load_gt(DisasContext *ctx, arg_rrr *a, MemOp mop)
212
TCGv src2 = gpr_src(ctx, a->rk, EXT_NONE);
213
214
gen_helper_asrtgt_d(cpu_env, src1, src2);
215
+ src1 = make_address_i(ctx, src1, 0);
216
tcg_gen_qemu_ld_tl(dest, src1, ctx->mem_idx, mop);
217
gen_set_gpr(a->rd, dest, EXT_NONE);
218
219
@@ -XXX,XX +XXX,XX @@ static bool gen_load_le(DisasContext *ctx, arg_rrr *a, MemOp mop)
220
TCGv src2 = gpr_src(ctx, a->rk, EXT_NONE);
221
222
gen_helper_asrtle_d(cpu_env, src1, src2);
223
+ src1 = make_address_i(ctx, src1, 0);
224
tcg_gen_qemu_ld_tl(dest, src1, ctx->mem_idx, mop);
225
gen_set_gpr(a->rd, dest, EXT_NONE);
226
227
@@ -XXX,XX +XXX,XX @@ static bool gen_store_gt(DisasContext *ctx, arg_rrr *a, MemOp mop)
228
TCGv src2 = gpr_src(ctx, a->rk, EXT_NONE);
229
230
gen_helper_asrtgt_d(cpu_env, src1, src2);
231
+ src1 = make_address_i(ctx, src1, 0);
232
tcg_gen_qemu_st_tl(data, src1, ctx->mem_idx, mop);
233
234
return true;
235
@@ -XXX,XX +XXX,XX @@ static bool gen_store_le(DisasContext *ctx, arg_rrr *a, MemOp mop)
236
TCGv src2 = gpr_src(ctx, a->rk, EXT_NONE);
237
238
gen_helper_asrtle_d(cpu_env, src1, src2);
239
+ src1 = make_address_i(ctx, src1, 0);
240
tcg_gen_qemu_st_tl(data, src1, ctx->mem_idx, mop);
241
242
return true;
243
@@ -XXX,XX +XXX,XX @@ static bool gen_ldptr(DisasContext *ctx, arg_rr_i *a, MemOp mop)
244
TCGv dest = gpr_dst(ctx, a->rd, EXT_NONE);
245
TCGv addr = gpr_src(ctx, a->rj, EXT_NONE);
246
247
- if (a->imm) {
248
- TCGv temp = tcg_temp_new();
249
- tcg_gen_addi_tl(temp, addr, a->imm);
250
- addr = temp;
251
- }
252
+ addr = make_address_i(ctx, addr, a->imm);
253
254
tcg_gen_qemu_ld_tl(dest, addr, ctx->mem_idx, mop);
255
gen_set_gpr(a->rd, dest, EXT_NONE);
256
@@ -XXX,XX +XXX,XX @@ static bool gen_stptr(DisasContext *ctx, arg_rr_i *a, MemOp mop)
257
TCGv data = gpr_src(ctx, a->rd, EXT_NONE);
258
TCGv addr = gpr_src(ctx, a->rj, EXT_NONE);
259
260
- if (a->imm) {
261
- TCGv temp = tcg_temp_new();
262
- tcg_gen_addi_tl(temp, addr, a->imm);
263
- addr = temp;
264
- }
265
+ addr = make_address_i(ctx, addr, a->imm);
266
267
tcg_gen_qemu_st_tl(data, addr, ctx->mem_idx, mop);
268
return true;
269
diff --git a/target/loongarch/translate.c b/target/loongarch/translate.c
270
index XXXXXXX..XXXXXXX 100644
271
--- a/target/loongarch/translate.c
272
+++ b/target/loongarch/translate.c
273
@@ -XXX,XX +XXX,XX @@ static TCGv make_address_x(DisasContext *ctx, TCGv base, TCGv addend)
274
return base;
275
}
276
277
+static TCGv make_address_i(DisasContext *ctx, TCGv base, target_long ofs)
278
+{
279
+ TCGv addend = ofs ? tcg_constant_tl(ofs) : NULL;
280
+ return make_address_x(ctx, base, addend);
281
+}
282
+
283
#include "decode-insns.c.inc"
284
#include "insn_trans/trans_arith.c.inc"
285
#include "insn_trans/trans_shift.c.inc"
286
--
287
2.39.1
288
289
diff view generated by jsdifflib
New patch
[PULL 15/31] target/loongarch: Extract make_address_pc() helper
1
From: Jiajie Chen <c@jia.je>
1
2
3
Signed-off-by: Jiajie Chen <c@jia.je>
4
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
5
Signed-off-by: Song Gao <gaosong@loongson.cn>
6
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
7
Message-ID: <20230822032724.1353391-7-gaosong@loongson.cn>
8
[PMD: Extract helper from bigger patch]
9
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
10
Message-Id: <20230822071405.35386-8-philmd@linaro.org>
11
---
12
target/loongarch/insn_trans/trans_arith.c.inc | 2 +-
13
target/loongarch/insn_trans/trans_branch.c.inc | 4 ++--
14
target/loongarch/translate.c | 5 +++++
15
3 files changed, 8 insertions(+), 3 deletions(-)
16
17
diff --git a/target/loongarch/insn_trans/trans_arith.c.inc b/target/loongarch/insn_trans/trans_arith.c.inc
18
index XXXXXXX..XXXXXXX 100644
19
--- a/target/loongarch/insn_trans/trans_arith.c.inc
20
+++ b/target/loongarch/insn_trans/trans_arith.c.inc
21
@@ -XXX,XX +XXX,XX @@ static bool gen_pc(DisasContext *ctx, arg_r_i *a,
22
target_ulong (*func)(target_ulong, int))
23
{
24
TCGv dest = gpr_dst(ctx, a->rd, EXT_NONE);
25
- target_ulong addr = func(ctx->base.pc_next, a->imm);
26
+ target_ulong addr = make_address_pc(ctx, func(ctx->base.pc_next, a->imm));
27
28
tcg_gen_movi_tl(dest, addr);
29
gen_set_gpr(a->rd, dest, EXT_NONE);
30
diff --git a/target/loongarch/insn_trans/trans_branch.c.inc b/target/loongarch/insn_trans/trans_branch.c.inc
31
index XXXXXXX..XXXXXXX 100644
32
--- a/target/loongarch/insn_trans/trans_branch.c.inc
33
+++ b/target/loongarch/insn_trans/trans_branch.c.inc
34
@@ -XXX,XX +XXX,XX @@ static bool trans_b(DisasContext *ctx, arg_b *a)
35
36
static bool trans_bl(DisasContext *ctx, arg_bl *a)
37
{
38
- tcg_gen_movi_tl(cpu_gpr[1], ctx->base.pc_next + 4);
39
+ tcg_gen_movi_tl(cpu_gpr[1], make_address_pc(ctx, ctx->base.pc_next + 4));
40
gen_goto_tb(ctx, 0, ctx->base.pc_next + a->offs);
41
ctx->base.is_jmp = DISAS_NORETURN;
42
return true;
43
@@ -XXX,XX +XXX,XX @@ static bool trans_jirl(DisasContext *ctx, arg_jirl *a)
44
45
TCGv addr = make_address_i(ctx, src1, a->imm);
46
tcg_gen_mov_tl(cpu_pc, addr);
47
- tcg_gen_movi_tl(dest, ctx->base.pc_next + 4);
48
+ tcg_gen_movi_tl(dest, make_address_pc(ctx, ctx->base.pc_next + 4));
49
gen_set_gpr(a->rd, dest, EXT_NONE);
50
tcg_gen_lookup_and_goto_ptr();
51
ctx->base.is_jmp = DISAS_NORETURN;
52
diff --git a/target/loongarch/translate.c b/target/loongarch/translate.c
53
index XXXXXXX..XXXXXXX 100644
54
--- a/target/loongarch/translate.c
55
+++ b/target/loongarch/translate.c
56
@@ -XXX,XX +XXX,XX @@ static TCGv make_address_i(DisasContext *ctx, TCGv base, target_long ofs)
57
return make_address_x(ctx, base, addend);
58
}
59
60
+static uint64_t make_address_pc(DisasContext *ctx, uint64_t addr)
61
+{
62
+ return addr;
63
+}
64
+
65
#include "decode-insns.c.inc"
66
#include "insn_trans/trans_arith.c.inc"
67
#include "insn_trans/trans_shift.c.inc"
68
--
69
2.39.1
70
71
diff view generated by jsdifflib
New patch
[PULL 16/31] target/loongarch: Extract set_pc() helper
1
From: Jiajie Chen <c@jia.je>
1
2
3
Signed-off-by: Jiajie Chen <c@jia.je>
4
Co-authored-by: Richard Henderson <richard.henderson@linaro.org>
5
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
6
Signed-off-by: Song Gao <gaosong@loongson.cn>
7
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
8
Message-ID: <20230822032724.1353391-6-gaosong@loongson.cn>
9
[PMD: Extract helper from bigger patch]
10
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
11
Message-Id: <20230822071405.35386-9-philmd@linaro.org>
12
---
13
target/loongarch/cpu.c | 16 ++++++++--------
14
target/loongarch/cpu.h | 5 +++++
15
target/loongarch/gdbstub.c | 2 +-
16
target/loongarch/op_helper.c | 4 ++--
17
4 files changed, 16 insertions(+), 11 deletions(-)
18
19
diff --git a/target/loongarch/cpu.c b/target/loongarch/cpu.c
20
index XXXXXXX..XXXXXXX 100644
21
--- a/target/loongarch/cpu.c
22
+++ b/target/loongarch/cpu.c
23
@@ -XXX,XX +XXX,XX @@ static void loongarch_cpu_set_pc(CPUState *cs, vaddr value)
24
LoongArchCPU *cpu = LOONGARCH_CPU(cs);
25
CPULoongArchState *env = &cpu->env;
26
27
- env->pc = value;
28
+ set_pc(env, value);
29
}
30
31
static vaddr loongarch_cpu_get_pc(CPUState *cs)
32
@@ -XXX,XX +XXX,XX @@ static void loongarch_cpu_do_interrupt(CPUState *cs)
33
set_DERA:
34
env->CSR_DERA = env->pc;
35
env->CSR_DBG = FIELD_DP64(env->CSR_DBG, CSR_DBG, DST, 1);
36
- env->pc = env->CSR_EENTRY + 0x480;
37
+ set_pc(env, env->CSR_EENTRY + 0x480);
38
break;
39
case EXCCODE_INT:
40
if (FIELD_EX64(env->CSR_DBG, CSR_DBG, DST)) {
41
@@ -XXX,XX +XXX,XX @@ static void loongarch_cpu_do_interrupt(CPUState *cs)
42
43
/* Find the highest-priority interrupt. */
44
vector = 31 - clz32(pending);
45
- env->pc = env->CSR_EENTRY + (EXCCODE_EXTERNAL_INT + vector) * vec_size;
46
+ set_pc(env, env->CSR_EENTRY + \
47
+ (EXCCODE_EXTERNAL_INT + vector) * vec_size);
48
qemu_log_mask(CPU_LOG_INT,
49
"%s: PC " TARGET_FMT_lx " ERA " TARGET_FMT_lx
50
" cause %d\n" " A " TARGET_FMT_lx " D "
51
@@ -XXX,XX +XXX,XX @@ static void loongarch_cpu_do_interrupt(CPUState *cs)
52
env->CSR_ECFG, env->CSR_ESTAT);
53
} else {
54
if (tlbfill) {
55
- env->pc = env->CSR_TLBRENTRY;
56
+ set_pc(env, env->CSR_TLBRENTRY);
57
} else {
58
- env->pc = env->CSR_EENTRY;
59
- env->pc += EXCODE_MCODE(cause) * vec_size;
60
+ set_pc(env, env->CSR_EENTRY + EXCODE_MCODE(cause) * vec_size);
61
}
62
qemu_log_mask(CPU_LOG_INT,
63
"%s: PC " TARGET_FMT_lx " ERA " TARGET_FMT_lx
64
@@ -XXX,XX +XXX,XX @@ static void loongarch_cpu_synchronize_from_tb(CPUState *cs,
65
CPULoongArchState *env = &cpu->env;
66
67
tcg_debug_assert(!(cs->tcg_cflags & CF_PCREL));
68
- env->pc = tb->pc;
69
+ set_pc(env, tb->pc);
70
}
71
72
static void loongarch_restore_state_to_opc(CPUState *cs,
73
@@ -XXX,XX +XXX,XX @@ static void loongarch_restore_state_to_opc(CPUState *cs,
74
LoongArchCPU *cpu = LOONGARCH_CPU(cs);
75
CPULoongArchState *env = &cpu->env;
76
77
- env->pc = data[0];
78
+ set_pc(env, data[0]);
79
}
80
#endif /* CONFIG_TCG */
81
82
diff --git a/target/loongarch/cpu.h b/target/loongarch/cpu.h
83
index XXXXXXX..XXXXXXX 100644
84
--- a/target/loongarch/cpu.h
85
+++ b/target/loongarch/cpu.h
86
@@ -XXX,XX +XXX,XX @@ static inline bool is_va32(CPULoongArchState *env)
87
return va32;
88
}
89
90
+static inline void set_pc(CPULoongArchState *env, uint64_t value)
91
+{
92
+ env->pc = value;
93
+}
94
+
95
/*
96
* LoongArch CPUs hardware flags.
97
*/
98
diff --git a/target/loongarch/gdbstub.c b/target/loongarch/gdbstub.c
99
index XXXXXXX..XXXXXXX 100644
100
--- a/target/loongarch/gdbstub.c
101
+++ b/target/loongarch/gdbstub.c
102
@@ -XXX,XX +XXX,XX @@ int loongarch_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n)
103
env->gpr[n] = tmp;
104
length = read_length;
105
} else if (n == 33) {
106
- env->pc = tmp;
107
+ set_pc(env, tmp);
108
length = read_length;
109
}
110
return length;
111
diff --git a/target/loongarch/op_helper.c b/target/loongarch/op_helper.c
112
index XXXXXXX..XXXXXXX 100644
113
--- a/target/loongarch/op_helper.c
114
+++ b/target/loongarch/op_helper.c
115
@@ -XXX,XX +XXX,XX @@ void helper_ertn(CPULoongArchState *env)
116
env->CSR_TLBRERA = FIELD_DP64(env->CSR_TLBRERA, CSR_TLBRERA, ISTLBR, 0);
117
env->CSR_CRMD = FIELD_DP64(env->CSR_CRMD, CSR_CRMD, DA, 0);
118
env->CSR_CRMD = FIELD_DP64(env->CSR_CRMD, CSR_CRMD, PG, 1);
119
- env->pc = env->CSR_TLBRERA;
120
+ set_pc(env, env->CSR_TLBRERA);
121
qemu_log_mask(CPU_LOG_INT, "%s: TLBRERA " TARGET_FMT_lx "\n",
122
__func__, env->CSR_TLBRERA);
123
} else {
124
csr_pplv = FIELD_EX64(env->CSR_PRMD, CSR_PRMD, PPLV);
125
csr_pie = FIELD_EX64(env->CSR_PRMD, CSR_PRMD, PIE);
126
127
- env->pc = env->CSR_ERA;
128
+ set_pc(env, env->CSR_ERA);
129
qemu_log_mask(CPU_LOG_INT, "%s: ERA " TARGET_FMT_lx "\n",
130
__func__, env->CSR_ERA);
131
}
132
--
133
2.39.1
134
135
diff view generated by jsdifflib
New patch
[PULL 17/31] target/loongarch: Truncate high 32 bits of address in VA32 mode
1
From: Jiajie Chen <c@jia.je>
1
2
3
When running in VA32 mode(!LA64 or VA32L[1-3] matching PLV), virtual
4
address is truncated to 32 bits before address mapping.
5
6
Signed-off-by: Jiajie Chen <c@jia.je>
7
Co-authored-by: Richard Henderson <richard.henderson@linaro.org>
8
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
9
Signed-off-by: Song Gao <gaosong@loongson.cn>
10
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
11
Message-ID: <20230822032724.1353391-6-gaosong@loongson.cn>
12
Message-Id: <20230822071405.35386-10-philmd@linaro.org>
13
---
14
target/loongarch/cpu.h | 6 +++++-
15
target/loongarch/translate.c | 16 +++++++++++++++-
16
2 files changed, 20 insertions(+), 2 deletions(-)
17
18
diff --git a/target/loongarch/cpu.h b/target/loongarch/cpu.h
19
index XXXXXXX..XXXXXXX 100644
20
--- a/target/loongarch/cpu.h
21
+++ b/target/loongarch/cpu.h
22
@@ -XXX,XX +XXX,XX @@ static inline bool is_va32(CPULoongArchState *env)
23
24
static inline void set_pc(CPULoongArchState *env, uint64_t value)
25
{
26
- env->pc = value;
27
+ if (is_va32(env)) {
28
+ env->pc = (uint32_t)value;
29
+ } else {
30
+ env->pc = value;
31
+ }
32
}
33
34
/*
35
diff --git a/target/loongarch/translate.c b/target/loongarch/translate.c
36
index XXXXXXX..XXXXXXX 100644
37
--- a/target/loongarch/translate.c
38
+++ b/target/loongarch/translate.c
39
@@ -XXX,XX +XXX,XX @@ void generate_exception(DisasContext *ctx, int excp)
40
41
static inline void gen_goto_tb(DisasContext *ctx, int n, target_ulong dest)
42
{
43
+ if (ctx->va32) {
44
+ dest = (uint32_t) dest;
45
+ }
46
+
47
if (translator_use_goto_tb(&ctx->base, dest)) {
48
tcg_gen_goto_tb(n);
49
tcg_gen_movi_tl(cpu_pc, dest);
50
@@ -XXX,XX +XXX,XX @@ static TCGv make_address_x(DisasContext *ctx, TCGv base, TCGv addend)
51
{
52
TCGv temp = NULL;
53
54
- if (addend) {
55
+ if (addend || ctx->va32) {
56
temp = tcg_temp_new();
57
+ }
58
+ if (addend) {
59
tcg_gen_add_tl(temp, base, addend);
60
base = temp;
61
}
62
+ if (ctx->va32) {
63
+ tcg_gen_ext32u_tl(temp, base);
64
+ base = temp;
65
+ }
66
return base;
67
}
68
69
@@ -XXX,XX +XXX,XX @@ static void loongarch_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs)
70
}
71
72
ctx->base.pc_next += 4;
73
+
74
+ if (ctx->va32) {
75
+ ctx->base.pc_next = (uint32_t)ctx->base.pc_next;
76
+ }
77
}
78
79
static void loongarch_tr_tb_stop(DisasContextBase *dcbase, CPUState *cs)
80
--
81
2.39.1
82
83
diff view generated by jsdifflib
New patch
[PULL 18/31] target/loongarch: Sign extend results in VA32 mode
1
From: Jiajie Chen <c@jia.je>
1
2
3
In VA32 mode, BL, JIRL and PC* instructions should sign-extend the low
4
32 bit result to 64 bits.
5
6
Signed-off-by: Jiajie Chen <c@jia.je>
7
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
8
Signed-off-by: Song Gao <gaosong@loongson.cn>
9
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
10
Message-ID: <20230822032724.1353391-7-gaosong@loongson.cn>
11
Message-Id: <20230822071959.35620-1-philmd@linaro.org>
12
---
13
target/loongarch/translate.c | 3 +++
14
1 file changed, 3 insertions(+)
15
16
diff --git a/target/loongarch/translate.c b/target/loongarch/translate.c
17
index XXXXXXX..XXXXXXX 100644
18
--- a/target/loongarch/translate.c
19
+++ b/target/loongarch/translate.c
20
@@ -XXX,XX +XXX,XX @@ static TCGv make_address_i(DisasContext *ctx, TCGv base, target_long ofs)
21
22
static uint64_t make_address_pc(DisasContext *ctx, uint64_t addr)
23
{
24
+ if (ctx->va32) {
25
+ addr = (int32_t)addr;
26
+ }
27
return addr;
28
}
29
30
--
31
2.39.1
32
33
diff view generated by jsdifflib
New patch
[PULL 19/31] target/loongarch: Add a check parameter to the TRANS macro
1
The default check parmeter is ALL.
1
2
3
Suggested-by: Richard Henderson <richard.henderson@linaro.org>
4
Signed-off-by: Song Gao <gaosong@loongson.cn>
5
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
6
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
7
Message-ID: <20230822032724.1353391-8-gaosong@loongson.cn>
8
Message-Id: <20230822071959.35620-2-philmd@linaro.org>
9
---
10
target/loongarch/insn_trans/trans_arith.c.inc | 84 +-
11
.../loongarch/insn_trans/trans_atomic.c.inc | 80 +-
12
target/loongarch/insn_trans/trans_bit.c.inc | 56 +-
13
.../loongarch/insn_trans/trans_branch.c.inc | 20 +-
14
target/loongarch/insn_trans/trans_extra.c.inc | 16 +-
15
.../loongarch/insn_trans/trans_farith.c.inc | 72 +-
16
target/loongarch/insn_trans/trans_fcnv.c.inc | 56 +-
17
.../loongarch/insn_trans/trans_fmemory.c.inc | 32 +-
18
target/loongarch/insn_trans/trans_fmov.c.inc | 16 +-
19
target/loongarch/insn_trans/trans_lsx.c.inc | 1322 ++++++++---------
20
.../loongarch/insn_trans/trans_memory.c.inc | 84 +-
21
.../insn_trans/trans_privileged.c.inc | 16 +-
22
target/loongarch/insn_trans/trans_shift.c.inc | 30 +-
23
target/loongarch/translate.h | 6 +-
24
14 files changed, 946 insertions(+), 944 deletions(-)
25
26
diff --git a/target/loongarch/insn_trans/trans_arith.c.inc b/target/loongarch/insn_trans/trans_arith.c.inc
27
index XXXXXXX..XXXXXXX 100644
28
--- a/target/loongarch/insn_trans/trans_arith.c.inc
29
+++ b/target/loongarch/insn_trans/trans_arith.c.inc
30
@@ -XXX,XX +XXX,XX @@ static bool trans_addu16i_d(DisasContext *ctx, arg_addu16i_d *a)
31
return true;
32
}
33
34
-TRANS(add_w, gen_rrr, EXT_NONE, EXT_NONE, EXT_SIGN, tcg_gen_add_tl)
35
-TRANS(add_d, gen_rrr, EXT_NONE, EXT_NONE, EXT_NONE, tcg_gen_add_tl)
36
-TRANS(sub_w, gen_rrr, EXT_NONE, EXT_NONE, EXT_SIGN, tcg_gen_sub_tl)
37
-TRANS(sub_d, gen_rrr, EXT_NONE, EXT_NONE, EXT_NONE, tcg_gen_sub_tl)
38
-TRANS(and, gen_rrr, EXT_NONE, EXT_NONE, EXT_NONE, tcg_gen_and_tl)
39
-TRANS(or, gen_rrr, EXT_NONE, EXT_NONE, EXT_NONE, tcg_gen_or_tl)
40
-TRANS(xor, gen_rrr, EXT_NONE, EXT_NONE, EXT_NONE, tcg_gen_xor_tl)
41
-TRANS(nor, gen_rrr, EXT_NONE, EXT_NONE, EXT_NONE, tcg_gen_nor_tl)
42
-TRANS(andn, gen_rrr, EXT_NONE, EXT_NONE, EXT_NONE, tcg_gen_andc_tl)
43
-TRANS(orn, gen_rrr, EXT_NONE, EXT_NONE, EXT_NONE, tcg_gen_orc_tl)
44
-TRANS(slt, gen_rrr, EXT_NONE, EXT_NONE, EXT_NONE, gen_slt)
45
-TRANS(sltu, gen_rrr, EXT_NONE, EXT_NONE, EXT_NONE, gen_sltu)
46
-TRANS(mul_w, gen_rrr, EXT_SIGN, EXT_SIGN, EXT_SIGN, tcg_gen_mul_tl)
47
-TRANS(mul_d, gen_rrr, EXT_NONE, EXT_NONE, EXT_NONE, tcg_gen_mul_tl)
48
-TRANS(mulh_w, gen_rrr, EXT_SIGN, EXT_SIGN, EXT_NONE, gen_mulh_w)
49
-TRANS(mulh_wu, gen_rrr, EXT_ZERO, EXT_ZERO, EXT_NONE, gen_mulh_w)
50
-TRANS(mulh_d, gen_rrr, EXT_NONE, EXT_NONE, EXT_NONE, gen_mulh_d)
51
-TRANS(mulh_du, gen_rrr, EXT_NONE, EXT_NONE, EXT_NONE, gen_mulh_du)
52
-TRANS(mulw_d_w, gen_rrr, EXT_SIGN, EXT_SIGN, EXT_NONE, tcg_gen_mul_tl)
53
-TRANS(mulw_d_wu, gen_rrr, EXT_ZERO, EXT_ZERO, EXT_NONE, tcg_gen_mul_tl)
54
-TRANS(div_w, gen_rrr, EXT_SIGN, EXT_SIGN, EXT_SIGN, gen_div_w)
55
-TRANS(mod_w, gen_rrr, EXT_SIGN, EXT_SIGN, EXT_SIGN, gen_rem_w)
56
-TRANS(div_wu, gen_rrr, EXT_ZERO, EXT_ZERO, EXT_SIGN, gen_div_du)
57
-TRANS(mod_wu, gen_rrr, EXT_ZERO, EXT_ZERO, EXT_SIGN, gen_rem_du)
58
-TRANS(div_d, gen_rrr, EXT_NONE, EXT_NONE, EXT_NONE, gen_div_d)
59
-TRANS(mod_d, gen_rrr, EXT_NONE, EXT_NONE, EXT_NONE, gen_rem_d)
60
-TRANS(div_du, gen_rrr, EXT_NONE, EXT_NONE, EXT_NONE, gen_div_du)
61
-TRANS(mod_du, gen_rrr, EXT_NONE, EXT_NONE, EXT_NONE, gen_rem_du)
62
-TRANS(slti, gen_rri_v, EXT_NONE, EXT_NONE, gen_slt)
63
-TRANS(sltui, gen_rri_v, EXT_NONE, EXT_NONE, gen_sltu)
64
-TRANS(addi_w, gen_rri_c, EXT_NONE, EXT_SIGN, tcg_gen_addi_tl)
65
-TRANS(addi_d, gen_rri_c, EXT_NONE, EXT_NONE, tcg_gen_addi_tl)
66
-TRANS(alsl_w, gen_rrr_sa, EXT_NONE, EXT_SIGN, gen_alsl)
67
-TRANS(alsl_wu, gen_rrr_sa, EXT_NONE, EXT_ZERO, gen_alsl)
68
-TRANS(alsl_d, gen_rrr_sa, EXT_NONE, EXT_NONE, gen_alsl)
69
-TRANS(pcaddi, gen_pc, gen_pcaddi)
70
-TRANS(pcalau12i, gen_pc, gen_pcalau12i)
71
-TRANS(pcaddu12i, gen_pc, gen_pcaddu12i)
72
-TRANS(pcaddu18i, gen_pc, gen_pcaddu18i)
73
-TRANS(andi, gen_rri_c, EXT_NONE, EXT_NONE, tcg_gen_andi_tl)
74
-TRANS(ori, gen_rri_c, EXT_NONE, EXT_NONE, tcg_gen_ori_tl)
75
-TRANS(xori, gen_rri_c, EXT_NONE, EXT_NONE, tcg_gen_xori_tl)
76
+TRANS(add_w, ALL, gen_rrr, EXT_NONE, EXT_NONE, EXT_SIGN, tcg_gen_add_tl)
77
+TRANS(add_d, ALL, gen_rrr, EXT_NONE, EXT_NONE, EXT_NONE, tcg_gen_add_tl)
78
+TRANS(sub_w, ALL, gen_rrr, EXT_NONE, EXT_NONE, EXT_SIGN, tcg_gen_sub_tl)
79
+TRANS(sub_d, ALL, gen_rrr, EXT_NONE, EXT_NONE, EXT_NONE, tcg_gen_sub_tl)
80
+TRANS(and, ALL, gen_rrr, EXT_NONE, EXT_NONE, EXT_NONE, tcg_gen_and_tl)
81
+TRANS(or, ALL, gen_rrr, EXT_NONE, EXT_NONE, EXT_NONE, tcg_gen_or_tl)
82
+TRANS(xor, ALL, gen_rrr, EXT_NONE, EXT_NONE, EXT_NONE, tcg_gen_xor_tl)
83
+TRANS(nor, ALL, gen_rrr, EXT_NONE, EXT_NONE, EXT_NONE, tcg_gen_nor_tl)
84
+TRANS(andn, ALL, gen_rrr, EXT_NONE, EXT_NONE, EXT_NONE, tcg_gen_andc_tl)
85
+TRANS(orn, ALL, gen_rrr, EXT_NONE, EXT_NONE, EXT_NONE, tcg_gen_orc_tl)
86
+TRANS(slt, ALL, gen_rrr, EXT_NONE, EXT_NONE, EXT_NONE, gen_slt)
87
+TRANS(sltu, ALL, gen_rrr, EXT_NONE, EXT_NONE, EXT_NONE, gen_sltu)
88
+TRANS(mul_w, ALL, gen_rrr, EXT_SIGN, EXT_SIGN, EXT_SIGN, tcg_gen_mul_tl)
89
+TRANS(mul_d, ALL, gen_rrr, EXT_NONE, EXT_NONE, EXT_NONE, tcg_gen_mul_tl)
90
+TRANS(mulh_w, ALL, gen_rrr, EXT_SIGN, EXT_SIGN, EXT_NONE, gen_mulh_w)
91
+TRANS(mulh_wu, ALL, gen_rrr, EXT_ZERO, EXT_ZERO, EXT_NONE, gen_mulh_w)
92
+TRANS(mulh_d, ALL, gen_rrr, EXT_NONE, EXT_NONE, EXT_NONE, gen_mulh_d)
93
+TRANS(mulh_du, ALL, gen_rrr, EXT_NONE, EXT_NONE, EXT_NONE, gen_mulh_du)
94
+TRANS(mulw_d_w, ALL, gen_rrr, EXT_SIGN, EXT_SIGN, EXT_NONE, tcg_gen_mul_tl)
95
+TRANS(mulw_d_wu, ALL, gen_rrr, EXT_ZERO, EXT_ZERO, EXT_NONE, tcg_gen_mul_tl)
96
+TRANS(div_w, ALL, gen_rrr, EXT_SIGN, EXT_SIGN, EXT_SIGN, gen_div_w)
97
+TRANS(mod_w, ALL, gen_rrr, EXT_SIGN, EXT_SIGN, EXT_SIGN, gen_rem_w)
98
+TRANS(div_wu, ALL, gen_rrr, EXT_ZERO, EXT_ZERO, EXT_SIGN, gen_div_du)
99
+TRANS(mod_wu, ALL, gen_rrr, EXT_ZERO, EXT_ZERO, EXT_SIGN, gen_rem_du)
100
+TRANS(div_d, ALL, gen_rrr, EXT_NONE, EXT_NONE, EXT_NONE, gen_div_d)
101
+TRANS(mod_d, ALL, gen_rrr, EXT_NONE, EXT_NONE, EXT_NONE, gen_rem_d)
102
+TRANS(div_du, ALL, gen_rrr, EXT_NONE, EXT_NONE, EXT_NONE, gen_div_du)
103
+TRANS(mod_du, ALL, gen_rrr, EXT_NONE, EXT_NONE, EXT_NONE, gen_rem_du)
104
+TRANS(slti, ALL, gen_rri_v, EXT_NONE, EXT_NONE, gen_slt)
105
+TRANS(sltui, ALL, gen_rri_v, EXT_NONE, EXT_NONE, gen_sltu)
106
+TRANS(addi_w, ALL, gen_rri_c, EXT_NONE, EXT_SIGN, tcg_gen_addi_tl)
107
+TRANS(addi_d, ALL, gen_rri_c, EXT_NONE, EXT_NONE, tcg_gen_addi_tl)
108
+TRANS(alsl_w, ALL, gen_rrr_sa, EXT_NONE, EXT_SIGN, gen_alsl)
109
+TRANS(alsl_wu, ALL, gen_rrr_sa, EXT_NONE, EXT_ZERO, gen_alsl)
110
+TRANS(alsl_d, ALL, gen_rrr_sa, EXT_NONE, EXT_NONE, gen_alsl)
111
+TRANS(pcaddi, ALL, gen_pc, gen_pcaddi)
112
+TRANS(pcalau12i, ALL, gen_pc, gen_pcalau12i)
113
+TRANS(pcaddu12i, ALL, gen_pc, gen_pcaddu12i)
114
+TRANS(pcaddu18i, ALL, gen_pc, gen_pcaddu18i)
115
+TRANS(andi, ALL, gen_rri_c, EXT_NONE, EXT_NONE, tcg_gen_andi_tl)
116
+TRANS(ori, ALL, gen_rri_c, EXT_NONE, EXT_NONE, tcg_gen_ori_tl)
117
+TRANS(xori, ALL, gen_rri_c, EXT_NONE, EXT_NONE, tcg_gen_xori_tl)
118
diff --git a/target/loongarch/insn_trans/trans_atomic.c.inc b/target/loongarch/insn_trans/trans_atomic.c.inc
119
index XXXXXXX..XXXXXXX 100644
120
--- a/target/loongarch/insn_trans/trans_atomic.c.inc
121
+++ b/target/loongarch/insn_trans/trans_atomic.c.inc
122
@@ -XXX,XX +XXX,XX @@ static bool gen_am(DisasContext *ctx, arg_rrr *a,
123
return true;
124
}
125
126
-TRANS(ll_w, gen_ll, MO_TESL)
127
-TRANS(sc_w, gen_sc, MO_TESL)
128
-TRANS(ll_d, gen_ll, MO_TEUQ)
129
-TRANS(sc_d, gen_sc, MO_TEUQ)
130
-TRANS(amswap_w, gen_am, tcg_gen_atomic_xchg_tl, MO_TESL)
131
-TRANS(amswap_d, gen_am, tcg_gen_atomic_xchg_tl, MO_TEUQ)
132
-TRANS(amadd_w, gen_am, tcg_gen_atomic_fetch_add_tl, MO_TESL)
133
-TRANS(amadd_d, gen_am, tcg_gen_atomic_fetch_add_tl, MO_TEUQ)
134
-TRANS(amand_w, gen_am, tcg_gen_atomic_fetch_and_tl, MO_TESL)
135
-TRANS(amand_d, gen_am, tcg_gen_atomic_fetch_and_tl, MO_TEUQ)
136
-TRANS(amor_w, gen_am, tcg_gen_atomic_fetch_or_tl, MO_TESL)
137
-TRANS(amor_d, gen_am, tcg_gen_atomic_fetch_or_tl, MO_TEUQ)
138
-TRANS(amxor_w, gen_am, tcg_gen_atomic_fetch_xor_tl, MO_TESL)
139
-TRANS(amxor_d, gen_am, tcg_gen_atomic_fetch_xor_tl, MO_TEUQ)
140
-TRANS(ammax_w, gen_am, tcg_gen_atomic_fetch_smax_tl, MO_TESL)
141
-TRANS(ammax_d, gen_am, tcg_gen_atomic_fetch_smax_tl, MO_TEUQ)
142
-TRANS(ammin_w, gen_am, tcg_gen_atomic_fetch_smin_tl, MO_TESL)
143
-TRANS(ammin_d, gen_am, tcg_gen_atomic_fetch_smin_tl, MO_TEUQ)
144
-TRANS(ammax_wu, gen_am, tcg_gen_atomic_fetch_umax_tl, MO_TESL)
145
-TRANS(ammax_du, gen_am, tcg_gen_atomic_fetch_umax_tl, MO_TEUQ)
146
-TRANS(ammin_wu, gen_am, tcg_gen_atomic_fetch_umin_tl, MO_TESL)
147
-TRANS(ammin_du, gen_am, tcg_gen_atomic_fetch_umin_tl, MO_TEUQ)
148
-TRANS(amswap_db_w, gen_am, tcg_gen_atomic_xchg_tl, MO_TESL)
149
-TRANS(amswap_db_d, gen_am, tcg_gen_atomic_xchg_tl, MO_TEUQ)
150
-TRANS(amadd_db_w, gen_am, tcg_gen_atomic_fetch_add_tl, MO_TESL)
151
-TRANS(amadd_db_d, gen_am, tcg_gen_atomic_fetch_add_tl, MO_TEUQ)
152
-TRANS(amand_db_w, gen_am, tcg_gen_atomic_fetch_and_tl, MO_TESL)
153
-TRANS(amand_db_d, gen_am, tcg_gen_atomic_fetch_and_tl, MO_TEUQ)
154
-TRANS(amor_db_w, gen_am, tcg_gen_atomic_fetch_or_tl, MO_TESL)
155
-TRANS(amor_db_d, gen_am, tcg_gen_atomic_fetch_or_tl, MO_TEUQ)
156
-TRANS(amxor_db_w, gen_am, tcg_gen_atomic_fetch_xor_tl, MO_TESL)
157
-TRANS(amxor_db_d, gen_am, tcg_gen_atomic_fetch_xor_tl, MO_TEUQ)
158
-TRANS(ammax_db_w, gen_am, tcg_gen_atomic_fetch_smax_tl, MO_TESL)
159
-TRANS(ammax_db_d, gen_am, tcg_gen_atomic_fetch_smax_tl, MO_TEUQ)
160
-TRANS(ammin_db_w, gen_am, tcg_gen_atomic_fetch_smin_tl, MO_TESL)
161
-TRANS(ammin_db_d, gen_am, tcg_gen_atomic_fetch_smin_tl, MO_TEUQ)
162
-TRANS(ammax_db_wu, gen_am, tcg_gen_atomic_fetch_umax_tl, MO_TESL)
163
-TRANS(ammax_db_du, gen_am, tcg_gen_atomic_fetch_umax_tl, MO_TEUQ)
164
-TRANS(ammin_db_wu, gen_am, tcg_gen_atomic_fetch_umin_tl, MO_TESL)
165
-TRANS(ammin_db_du, gen_am, tcg_gen_atomic_fetch_umin_tl, MO_TEUQ)
166
+TRANS(ll_w, ALL, gen_ll, MO_TESL)
167
+TRANS(sc_w, ALL, gen_sc, MO_TESL)
168
+TRANS(ll_d, ALL, gen_ll, MO_TEUQ)
169
+TRANS(sc_d, ALL, gen_sc, MO_TEUQ)
170
+TRANS(amswap_w, ALL, gen_am, tcg_gen_atomic_xchg_tl, MO_TESL)
171
+TRANS(amswap_d, ALL, gen_am, tcg_gen_atomic_xchg_tl, MO_TEUQ)
172
+TRANS(amadd_w, ALL, gen_am, tcg_gen_atomic_fetch_add_tl, MO_TESL)
173
+TRANS(amadd_d, ALL, gen_am, tcg_gen_atomic_fetch_add_tl, MO_TEUQ)
174
+TRANS(amand_w, ALL, gen_am, tcg_gen_atomic_fetch_and_tl, MO_TESL)
175
+TRANS(amand_d, ALL, gen_am, tcg_gen_atomic_fetch_and_tl, MO_TEUQ)
176
+TRANS(amor_w, ALL, gen_am, tcg_gen_atomic_fetch_or_tl, MO_TESL)
177
+TRANS(amor_d, ALL, gen_am, tcg_gen_atomic_fetch_or_tl, MO_TEUQ)
178
+TRANS(amxor_w, ALL, gen_am, tcg_gen_atomic_fetch_xor_tl, MO_TESL)
179
+TRANS(amxor_d, ALL, gen_am, tcg_gen_atomic_fetch_xor_tl, MO_TEUQ)
180
+TRANS(ammax_w, ALL, gen_am, tcg_gen_atomic_fetch_smax_tl, MO_TESL)
181
+TRANS(ammax_d, ALL, gen_am, tcg_gen_atomic_fetch_smax_tl, MO_TEUQ)
182
+TRANS(ammin_w, ALL, gen_am, tcg_gen_atomic_fetch_smin_tl, MO_TESL)
183
+TRANS(ammin_d, ALL, gen_am, tcg_gen_atomic_fetch_smin_tl, MO_TEUQ)
184
+TRANS(ammax_wu, ALL, gen_am, tcg_gen_atomic_fetch_umax_tl, MO_TESL)
185
+TRANS(ammax_du, ALL, gen_am, tcg_gen_atomic_fetch_umax_tl, MO_TEUQ)
186
+TRANS(ammin_wu, ALL, gen_am, tcg_gen_atomic_fetch_umin_tl, MO_TESL)
187
+TRANS(ammin_du, ALL, gen_am, tcg_gen_atomic_fetch_umin_tl, MO_TEUQ)
188
+TRANS(amswap_db_w, ALL, gen_am, tcg_gen_atomic_xchg_tl, MO_TESL)
189
+TRANS(amswap_db_d, ALL, gen_am, tcg_gen_atomic_xchg_tl, MO_TEUQ)
190
+TRANS(amadd_db_w, ALL, gen_am, tcg_gen_atomic_fetch_add_tl, MO_TESL)
191
+TRANS(amadd_db_d, ALL, gen_am, tcg_gen_atomic_fetch_add_tl, MO_TEUQ)
192
+TRANS(amand_db_w, ALL, gen_am, tcg_gen_atomic_fetch_and_tl, MO_TESL)
193
+TRANS(amand_db_d, ALL, gen_am, tcg_gen_atomic_fetch_and_tl, MO_TEUQ)
194
+TRANS(amor_db_w, ALL, gen_am, tcg_gen_atomic_fetch_or_tl, MO_TESL)
195
+TRANS(amor_db_d, ALL, gen_am, tcg_gen_atomic_fetch_or_tl, MO_TEUQ)
196
+TRANS(amxor_db_w, ALL, gen_am, tcg_gen_atomic_fetch_xor_tl, MO_TESL)
197
+TRANS(amxor_db_d, ALL, gen_am, tcg_gen_atomic_fetch_xor_tl, MO_TEUQ)
198
+TRANS(ammax_db_w, ALL, gen_am, tcg_gen_atomic_fetch_smax_tl, MO_TESL)
199
+TRANS(ammax_db_d, ALL, gen_am, tcg_gen_atomic_fetch_smax_tl, MO_TEUQ)
200
+TRANS(ammin_db_w, ALL, gen_am, tcg_gen_atomic_fetch_smin_tl, MO_TESL)
201
+TRANS(ammin_db_d, ALL, gen_am, tcg_gen_atomic_fetch_smin_tl, MO_TEUQ)
202
+TRANS(ammax_db_wu, ALL, gen_am, tcg_gen_atomic_fetch_umax_tl, MO_TESL)
203
+TRANS(ammax_db_du, ALL, gen_am, tcg_gen_atomic_fetch_umax_tl, MO_TEUQ)
204
+TRANS(ammin_db_wu, ALL, gen_am, tcg_gen_atomic_fetch_umin_tl, MO_TESL)
205
+TRANS(ammin_db_du, ALL, gen_am, tcg_gen_atomic_fetch_umin_tl, MO_TEUQ)
206
diff --git a/target/loongarch/insn_trans/trans_bit.c.inc b/target/loongarch/insn_trans/trans_bit.c.inc
207
index XXXXXXX..XXXXXXX 100644
208
--- a/target/loongarch/insn_trans/trans_bit.c.inc
209
+++ b/target/loongarch/insn_trans/trans_bit.c.inc
210
@@ -XXX,XX +XXX,XX @@ static void gen_masknez(TCGv dest, TCGv src1, TCGv src2)
211
tcg_gen_movcond_tl(TCG_COND_NE, dest, src2, zero, zero, src1);
212
}
213
214
-TRANS(ext_w_h, gen_rr, EXT_NONE, EXT_NONE, tcg_gen_ext16s_tl)
215
-TRANS(ext_w_b, gen_rr, EXT_NONE, EXT_NONE, tcg_gen_ext8s_tl)
216
-TRANS(clo_w, gen_rr, EXT_NONE, EXT_NONE, gen_clo_w)
217
-TRANS(clz_w, gen_rr, EXT_ZERO, EXT_NONE, gen_clz_w)
218
-TRANS(cto_w, gen_rr, EXT_NONE, EXT_NONE, gen_cto_w)
219
-TRANS(ctz_w, gen_rr, EXT_NONE, EXT_NONE, gen_ctz_w)
220
-TRANS(clo_d, gen_rr, EXT_NONE, EXT_NONE, gen_clo_d)
221
-TRANS(clz_d, gen_rr, EXT_NONE, EXT_NONE, gen_clz_d)
222
-TRANS(cto_d, gen_rr, EXT_NONE, EXT_NONE, gen_cto_d)
223
-TRANS(ctz_d, gen_rr, EXT_NONE, EXT_NONE, gen_ctz_d)
224
-TRANS(revb_2h, gen_rr, EXT_NONE, EXT_SIGN, gen_revb_2h)
225
-TRANS(revb_4h, gen_rr, EXT_NONE, EXT_NONE, gen_revb_4h)
226
-TRANS(revb_2w, gen_rr, EXT_NONE, EXT_NONE, gen_revb_2w)
227
-TRANS(revb_d, gen_rr, EXT_NONE, EXT_NONE, tcg_gen_bswap64_i64)
228
-TRANS(revh_2w, gen_rr, EXT_NONE, EXT_NONE, gen_revh_2w)
229
-TRANS(revh_d, gen_rr, EXT_NONE, EXT_NONE, gen_revh_d)
230
-TRANS(bitrev_4b, gen_rr, EXT_ZERO, EXT_SIGN, gen_helper_bitswap)
231
-TRANS(bitrev_8b, gen_rr, EXT_NONE, EXT_NONE, gen_helper_bitswap)
232
-TRANS(bitrev_w, gen_rr, EXT_NONE, EXT_SIGN, gen_helper_bitrev_w)
233
-TRANS(bitrev_d, gen_rr, EXT_NONE, EXT_NONE, gen_helper_bitrev_d)
234
-TRANS(maskeqz, gen_rrr, EXT_NONE, EXT_NONE, EXT_NONE, gen_maskeqz)
235
-TRANS(masknez, gen_rrr, EXT_NONE, EXT_NONE, EXT_NONE, gen_masknez)
236
-TRANS(bytepick_w, gen_rrr_sa, EXT_NONE, EXT_NONE, gen_bytepick_w)
237
-TRANS(bytepick_d, gen_rrr_sa, EXT_NONE, EXT_NONE, gen_bytepick_d)
238
-TRANS(bstrins_w, gen_bstrins, EXT_SIGN)
239
-TRANS(bstrins_d, gen_bstrins, EXT_NONE)
240
-TRANS(bstrpick_w, gen_bstrpick, EXT_SIGN)
241
-TRANS(bstrpick_d, gen_bstrpick, EXT_NONE)
242
+TRANS(ext_w_h, ALL, gen_rr, EXT_NONE, EXT_NONE, tcg_gen_ext16s_tl)
243
+TRANS(ext_w_b, ALL, gen_rr, EXT_NONE, EXT_NONE, tcg_gen_ext8s_tl)
244
+TRANS(clo_w, ALL, gen_rr, EXT_NONE, EXT_NONE, gen_clo_w)
245
+TRANS(clz_w, ALL, gen_rr, EXT_ZERO, EXT_NONE, gen_clz_w)
246
+TRANS(cto_w, ALL, gen_rr, EXT_NONE, EXT_NONE, gen_cto_w)
247
+TRANS(ctz_w, ALL, gen_rr, EXT_NONE, EXT_NONE, gen_ctz_w)
248
+TRANS(clo_d, ALL, gen_rr, EXT_NONE, EXT_NONE, gen_clo_d)
249
+TRANS(clz_d, ALL, gen_rr, EXT_NONE, EXT_NONE, gen_clz_d)
250
+TRANS(cto_d, ALL, gen_rr, EXT_NONE, EXT_NONE, gen_cto_d)
251
+TRANS(ctz_d, ALL, gen_rr, EXT_NONE, EXT_NONE, gen_ctz_d)
252
+TRANS(revb_2h, ALL, gen_rr, EXT_NONE, EXT_SIGN, gen_revb_2h)
253
+TRANS(revb_4h, ALL, gen_rr, EXT_NONE, EXT_NONE, gen_revb_4h)
254
+TRANS(revb_2w, ALL, gen_rr, EXT_NONE, EXT_NONE, gen_revb_2w)
255
+TRANS(revb_d, ALL, gen_rr, EXT_NONE, EXT_NONE, tcg_gen_bswap64_i64)
256
+TRANS(revh_2w, ALL, gen_rr, EXT_NONE, EXT_NONE, gen_revh_2w)
257
+TRANS(revh_d, ALL, gen_rr, EXT_NONE, EXT_NONE, gen_revh_d)
258
+TRANS(bitrev_4b, ALL, gen_rr, EXT_ZERO, EXT_SIGN, gen_helper_bitswap)
259
+TRANS(bitrev_8b, ALL, gen_rr, EXT_NONE, EXT_NONE, gen_helper_bitswap)
260
+TRANS(bitrev_w, ALL, gen_rr, EXT_NONE, EXT_SIGN, gen_helper_bitrev_w)
261
+TRANS(bitrev_d, ALL, gen_rr, EXT_NONE, EXT_NONE, gen_helper_bitrev_d)
262
+TRANS(maskeqz, ALL, gen_rrr, EXT_NONE, EXT_NONE, EXT_NONE, gen_maskeqz)
263
+TRANS(masknez, ALL, gen_rrr, EXT_NONE, EXT_NONE, EXT_NONE, gen_masknez)
264
+TRANS(bytepick_w, ALL, gen_rrr_sa, EXT_NONE, EXT_NONE, gen_bytepick_w)
265
+TRANS(bytepick_d, ALL, gen_rrr_sa, EXT_NONE, EXT_NONE, gen_bytepick_d)
266
+TRANS(bstrins_w, ALL, gen_bstrins, EXT_SIGN)
267
+TRANS(bstrins_d, ALL, gen_bstrins, EXT_NONE)
268
+TRANS(bstrpick_w, ALL, gen_bstrpick, EXT_SIGN)
269
+TRANS(bstrpick_d, ALL, gen_bstrpick, EXT_NONE)
270
diff --git a/target/loongarch/insn_trans/trans_branch.c.inc b/target/loongarch/insn_trans/trans_branch.c.inc
271
index XXXXXXX..XXXXXXX 100644
272
--- a/target/loongarch/insn_trans/trans_branch.c.inc
273
+++ b/target/loongarch/insn_trans/trans_branch.c.inc
274
@@ -XXX,XX +XXX,XX @@ static bool gen_cz_bc(DisasContext *ctx, arg_c_offs *a, TCGCond cond)
275
return true;
276
}
277
278
-TRANS(beq, gen_rr_bc, TCG_COND_EQ)
279
-TRANS(bne, gen_rr_bc, TCG_COND_NE)
280
-TRANS(blt, gen_rr_bc, TCG_COND_LT)
281
-TRANS(bge, gen_rr_bc, TCG_COND_GE)
282
-TRANS(bltu, gen_rr_bc, TCG_COND_LTU)
283
-TRANS(bgeu, gen_rr_bc, TCG_COND_GEU)
284
-TRANS(beqz, gen_rz_bc, TCG_COND_EQ)
285
-TRANS(bnez, gen_rz_bc, TCG_COND_NE)
286
-TRANS(bceqz, gen_cz_bc, TCG_COND_EQ)
287
-TRANS(bcnez, gen_cz_bc, TCG_COND_NE)
288
+TRANS(beq, ALL, gen_rr_bc, TCG_COND_EQ)
289
+TRANS(bne, ALL, gen_rr_bc, TCG_COND_NE)
290
+TRANS(blt, ALL, gen_rr_bc, TCG_COND_LT)
291
+TRANS(bge, ALL, gen_rr_bc, TCG_COND_GE)
292
+TRANS(bltu, ALL, gen_rr_bc, TCG_COND_LTU)
293
+TRANS(bgeu, ALL, gen_rr_bc, TCG_COND_GEU)
294
+TRANS(beqz, ALL, gen_rz_bc, TCG_COND_EQ)
295
+TRANS(bnez, ALL, gen_rz_bc, TCG_COND_NE)
296
+TRANS(bceqz, ALL, gen_cz_bc, TCG_COND_EQ)
297
+TRANS(bcnez, ALL, gen_cz_bc, TCG_COND_NE)
298
diff --git a/target/loongarch/insn_trans/trans_extra.c.inc b/target/loongarch/insn_trans/trans_extra.c.inc
299
index XXXXXXX..XXXXXXX 100644
300
--- a/target/loongarch/insn_trans/trans_extra.c.inc
301
+++ b/target/loongarch/insn_trans/trans_extra.c.inc
302
@@ -XXX,XX +XXX,XX @@ static bool gen_crc(DisasContext *ctx, arg_rrr *a,
303
return true;
304
}
305
306
-TRANS(crc_w_b_w, gen_crc, gen_helper_crc32, tcg_constant_tl(1))
307
-TRANS(crc_w_h_w, gen_crc, gen_helper_crc32, tcg_constant_tl(2))
308
-TRANS(crc_w_w_w, gen_crc, gen_helper_crc32, tcg_constant_tl(4))
309
-TRANS(crc_w_d_w, gen_crc, gen_helper_crc32, tcg_constant_tl(8))
310
-TRANS(crcc_w_b_w, gen_crc, gen_helper_crc32c, tcg_constant_tl(1))
311
-TRANS(crcc_w_h_w, gen_crc, gen_helper_crc32c, tcg_constant_tl(2))
312
-TRANS(crcc_w_w_w, gen_crc, gen_helper_crc32c, tcg_constant_tl(4))
313
-TRANS(crcc_w_d_w, gen_crc, gen_helper_crc32c, tcg_constant_tl(8))
314
+TRANS(crc_w_b_w, ALL, gen_crc, gen_helper_crc32, tcg_constant_tl(1))
315
+TRANS(crc_w_h_w, ALL, gen_crc, gen_helper_crc32, tcg_constant_tl(2))
316
+TRANS(crc_w_w_w, ALL, gen_crc, gen_helper_crc32, tcg_constant_tl(4))
317
+TRANS(crc_w_d_w, ALL, gen_crc, gen_helper_crc32, tcg_constant_tl(8))
318
+TRANS(crcc_w_b_w, ALL, gen_crc, gen_helper_crc32c, tcg_constant_tl(1))
319
+TRANS(crcc_w_h_w, ALL, gen_crc, gen_helper_crc32c, tcg_constant_tl(2))
320
+TRANS(crcc_w_w_w, ALL, gen_crc, gen_helper_crc32c, tcg_constant_tl(4))
321
+TRANS(crcc_w_d_w, ALL, gen_crc, gen_helper_crc32c, tcg_constant_tl(8))
322
diff --git a/target/loongarch/insn_trans/trans_farith.c.inc b/target/loongarch/insn_trans/trans_farith.c.inc
323
index XXXXXXX..XXXXXXX 100644
324
--- a/target/loongarch/insn_trans/trans_farith.c.inc
325
+++ b/target/loongarch/insn_trans/trans_farith.c.inc
326
@@ -XXX,XX +XXX,XX @@ static bool trans_fneg_d(DisasContext *ctx, arg_fneg_d *a)
327
return true;
328
}
329
330
-TRANS(fadd_s, gen_fff, gen_helper_fadd_s)
331
-TRANS(fadd_d, gen_fff, gen_helper_fadd_d)
332
-TRANS(fsub_s, gen_fff, gen_helper_fsub_s)
333
-TRANS(fsub_d, gen_fff, gen_helper_fsub_d)
334
-TRANS(fmul_s, gen_fff, gen_helper_fmul_s)
335
-TRANS(fmul_d, gen_fff, gen_helper_fmul_d)
336
-TRANS(fdiv_s, gen_fff, gen_helper_fdiv_s)
337
-TRANS(fdiv_d, gen_fff, gen_helper_fdiv_d)
338
-TRANS(fmax_s, gen_fff, gen_helper_fmax_s)
339
-TRANS(fmax_d, gen_fff, gen_helper_fmax_d)
340
-TRANS(fmin_s, gen_fff, gen_helper_fmin_s)
341
-TRANS(fmin_d, gen_fff, gen_helper_fmin_d)
342
-TRANS(fmaxa_s, gen_fff, gen_helper_fmaxa_s)
343
-TRANS(fmaxa_d, gen_fff, gen_helper_fmaxa_d)
344
-TRANS(fmina_s, gen_fff, gen_helper_fmina_s)
345
-TRANS(fmina_d, gen_fff, gen_helper_fmina_d)
346
-TRANS(fscaleb_s, gen_fff, gen_helper_fscaleb_s)
347
-TRANS(fscaleb_d, gen_fff, gen_helper_fscaleb_d)
348
-TRANS(fsqrt_s, gen_ff, gen_helper_fsqrt_s)
349
-TRANS(fsqrt_d, gen_ff, gen_helper_fsqrt_d)
350
-TRANS(frecip_s, gen_ff, gen_helper_frecip_s)
351
-TRANS(frecip_d, gen_ff, gen_helper_frecip_d)
352
-TRANS(frsqrt_s, gen_ff, gen_helper_frsqrt_s)
353
-TRANS(frsqrt_d, gen_ff, gen_helper_frsqrt_d)
354
-TRANS(flogb_s, gen_ff, gen_helper_flogb_s)
355
-TRANS(flogb_d, gen_ff, gen_helper_flogb_d)
356
-TRANS(fclass_s, gen_ff, gen_helper_fclass_s)
357
-TRANS(fclass_d, gen_ff, gen_helper_fclass_d)
358
-TRANS(fmadd_s, gen_muladd, gen_helper_fmuladd_s, 0)
359
-TRANS(fmadd_d, gen_muladd, gen_helper_fmuladd_d, 0)
360
-TRANS(fmsub_s, gen_muladd, gen_helper_fmuladd_s, float_muladd_negate_c)
361
-TRANS(fmsub_d, gen_muladd, gen_helper_fmuladd_d, float_muladd_negate_c)
362
-TRANS(fnmadd_s, gen_muladd, gen_helper_fmuladd_s, float_muladd_negate_result)
363
-TRANS(fnmadd_d, gen_muladd, gen_helper_fmuladd_d, float_muladd_negate_result)
364
-TRANS(fnmsub_s, gen_muladd, gen_helper_fmuladd_s,
365
+TRANS(fadd_s, ALL, gen_fff, gen_helper_fadd_s)
366
+TRANS(fadd_d, ALL, gen_fff, gen_helper_fadd_d)
367
+TRANS(fsub_s, ALL, gen_fff, gen_helper_fsub_s)
368
+TRANS(fsub_d, ALL, gen_fff, gen_helper_fsub_d)
369
+TRANS(fmul_s, ALL, gen_fff, gen_helper_fmul_s)
370
+TRANS(fmul_d, ALL, gen_fff, gen_helper_fmul_d)
371
+TRANS(fdiv_s, ALL, gen_fff, gen_helper_fdiv_s)
372
+TRANS(fdiv_d, ALL, gen_fff, gen_helper_fdiv_d)
373
+TRANS(fmax_s, ALL, gen_fff, gen_helper_fmax_s)
374
+TRANS(fmax_d, ALL, gen_fff, gen_helper_fmax_d)
375
+TRANS(fmin_s, ALL, gen_fff, gen_helper_fmin_s)
376
+TRANS(fmin_d, ALL, gen_fff, gen_helper_fmin_d)
377
+TRANS(fmaxa_s, ALL, gen_fff, gen_helper_fmaxa_s)
378
+TRANS(fmaxa_d, ALL, gen_fff, gen_helper_fmaxa_d)
379
+TRANS(fmina_s, ALL, gen_fff, gen_helper_fmina_s)
380
+TRANS(fmina_d, ALL, gen_fff, gen_helper_fmina_d)
381
+TRANS(fscaleb_s, ALL, gen_fff, gen_helper_fscaleb_s)
382
+TRANS(fscaleb_d, ALL, gen_fff, gen_helper_fscaleb_d)
383
+TRANS(fsqrt_s, ALL, gen_ff, gen_helper_fsqrt_s)
384
+TRANS(fsqrt_d, ALL, gen_ff, gen_helper_fsqrt_d)
385
+TRANS(frecip_s, ALL, gen_ff, gen_helper_frecip_s)
386
+TRANS(frecip_d, ALL, gen_ff, gen_helper_frecip_d)
387
+TRANS(frsqrt_s, ALL, gen_ff, gen_helper_frsqrt_s)
388
+TRANS(frsqrt_d, ALL, gen_ff, gen_helper_frsqrt_d)
389
+TRANS(flogb_s, ALL, gen_ff, gen_helper_flogb_s)
390
+TRANS(flogb_d, ALL, gen_ff, gen_helper_flogb_d)
391
+TRANS(fclass_s, ALL, gen_ff, gen_helper_fclass_s)
392
+TRANS(fclass_d, ALL, gen_ff, gen_helper_fclass_d)
393
+TRANS(fmadd_s, ALL, gen_muladd, gen_helper_fmuladd_s, 0)
394
+TRANS(fmadd_d, ALL, gen_muladd, gen_helper_fmuladd_d, 0)
395
+TRANS(fmsub_s, ALL, gen_muladd, gen_helper_fmuladd_s, float_muladd_negate_c)
396
+TRANS(fmsub_d, ALL, gen_muladd, gen_helper_fmuladd_d, float_muladd_negate_c)
397
+TRANS(fnmadd_s, ALL, gen_muladd, gen_helper_fmuladd_s, float_muladd_negate_result)
398
+TRANS(fnmadd_d, ALL, gen_muladd, gen_helper_fmuladd_d, float_muladd_negate_result)
399
+TRANS(fnmsub_s, ALL, gen_muladd, gen_helper_fmuladd_s,
400
float_muladd_negate_c | float_muladd_negate_result)
401
-TRANS(fnmsub_d, gen_muladd, gen_helper_fmuladd_d,
402
+TRANS(fnmsub_d, ALL, gen_muladd, gen_helper_fmuladd_d,
403
float_muladd_negate_c | float_muladd_negate_result)
404
diff --git a/target/loongarch/insn_trans/trans_fcnv.c.inc b/target/loongarch/insn_trans/trans_fcnv.c.inc
405
index XXXXXXX..XXXXXXX 100644
406
--- a/target/loongarch/insn_trans/trans_fcnv.c.inc
407
+++ b/target/loongarch/insn_trans/trans_fcnv.c.inc
408
@@ -XXX,XX +XXX,XX @@
409
* Copyright (c) 2021 Loongson Technology Corporation Limited
410
*/
411
412
-TRANS(fcvt_s_d, gen_ff, gen_helper_fcvt_s_d)
413
-TRANS(fcvt_d_s, gen_ff, gen_helper_fcvt_d_s)
414
-TRANS(ftintrm_w_s, gen_ff, gen_helper_ftintrm_w_s)
415
-TRANS(ftintrm_w_d, gen_ff, gen_helper_ftintrm_w_d)
416
-TRANS(ftintrm_l_s, gen_ff, gen_helper_ftintrm_l_s)
417
-TRANS(ftintrm_l_d, gen_ff, gen_helper_ftintrm_l_d)
418
-TRANS(ftintrp_w_s, gen_ff, gen_helper_ftintrp_w_s)
419
-TRANS(ftintrp_w_d, gen_ff, gen_helper_ftintrp_w_d)
420
-TRANS(ftintrp_l_s, gen_ff, gen_helper_ftintrp_l_s)
421
-TRANS(ftintrp_l_d, gen_ff, gen_helper_ftintrp_l_d)
422
-TRANS(ftintrz_w_s, gen_ff, gen_helper_ftintrz_w_s)
423
-TRANS(ftintrz_w_d, gen_ff, gen_helper_ftintrz_w_d)
424
-TRANS(ftintrz_l_s, gen_ff, gen_helper_ftintrz_l_s)
425
-TRANS(ftintrz_l_d, gen_ff, gen_helper_ftintrz_l_d)
426
-TRANS(ftintrne_w_s, gen_ff, gen_helper_ftintrne_w_s)
427
-TRANS(ftintrne_w_d, gen_ff, gen_helper_ftintrne_w_d)
428
-TRANS(ftintrne_l_s, gen_ff, gen_helper_ftintrne_l_s)
429
-TRANS(ftintrne_l_d, gen_ff, gen_helper_ftintrne_l_d)
430
-TRANS(ftint_w_s, gen_ff, gen_helper_ftint_w_s)
431
-TRANS(ftint_w_d, gen_ff, gen_helper_ftint_w_d)
432
-TRANS(ftint_l_s, gen_ff, gen_helper_ftint_l_s)
433
-TRANS(ftint_l_d, gen_ff, gen_helper_ftint_l_d)
434
-TRANS(ffint_s_w, gen_ff, gen_helper_ffint_s_w)
435
-TRANS(ffint_s_l, gen_ff, gen_helper_ffint_s_l)
436
-TRANS(ffint_d_w, gen_ff, gen_helper_ffint_d_w)
437
-TRANS(ffint_d_l, gen_ff, gen_helper_ffint_d_l)
438
-TRANS(frint_s, gen_ff, gen_helper_frint_s)
439
-TRANS(frint_d, gen_ff, gen_helper_frint_d)
440
+TRANS(fcvt_s_d, ALL, gen_ff, gen_helper_fcvt_s_d)
441
+TRANS(fcvt_d_s, ALL, gen_ff, gen_helper_fcvt_d_s)
442
+TRANS(ftintrm_w_s, ALL, gen_ff, gen_helper_ftintrm_w_s)
443
+TRANS(ftintrm_w_d, ALL, gen_ff, gen_helper_ftintrm_w_d)
444
+TRANS(ftintrm_l_s, ALL, gen_ff, gen_helper_ftintrm_l_s)
445
+TRANS(ftintrm_l_d, ALL, gen_ff, gen_helper_ftintrm_l_d)
446
+TRANS(ftintrp_w_s, ALL, gen_ff, gen_helper_ftintrp_w_s)
447
+TRANS(ftintrp_w_d, ALL, gen_ff, gen_helper_ftintrp_w_d)
448
+TRANS(ftintrp_l_s, ALL, gen_ff, gen_helper_ftintrp_l_s)
449
+TRANS(ftintrp_l_d, ALL, gen_ff, gen_helper_ftintrp_l_d)
450
+TRANS(ftintrz_w_s, ALL, gen_ff, gen_helper_ftintrz_w_s)
451
+TRANS(ftintrz_w_d, ALL, gen_ff, gen_helper_ftintrz_w_d)
452
+TRANS(ftintrz_l_s, ALL, gen_ff, gen_helper_ftintrz_l_s)
453
+TRANS(ftintrz_l_d, ALL, gen_ff, gen_helper_ftintrz_l_d)
454
+TRANS(ftintrne_w_s, ALL, gen_ff, gen_helper_ftintrne_w_s)
455
+TRANS(ftintrne_w_d, ALL, gen_ff, gen_helper_ftintrne_w_d)
456
+TRANS(ftintrne_l_s, ALL, gen_ff, gen_helper_ftintrne_l_s)
457
+TRANS(ftintrne_l_d, ALL, gen_ff, gen_helper_ftintrne_l_d)
458
+TRANS(ftint_w_s, ALL, gen_ff, gen_helper_ftint_w_s)
459
+TRANS(ftint_w_d, ALL, gen_ff, gen_helper_ftint_w_d)
460
+TRANS(ftint_l_s, ALL, gen_ff, gen_helper_ftint_l_s)
461
+TRANS(ftint_l_d, ALL, gen_ff, gen_helper_ftint_l_d)
462
+TRANS(ffint_s_w, ALL, gen_ff, gen_helper_ffint_s_w)
463
+TRANS(ffint_s_l, ALL, gen_ff, gen_helper_ffint_s_l)
464
+TRANS(ffint_d_w, ALL, gen_ff, gen_helper_ffint_d_w)
465
+TRANS(ffint_d_l, ALL, gen_ff, gen_helper_ffint_d_l)
466
+TRANS(frint_s, ALL, gen_ff, gen_helper_frint_s)
467
+TRANS(frint_d, ALL, gen_ff, gen_helper_frint_d)
468
diff --git a/target/loongarch/insn_trans/trans_fmemory.c.inc b/target/loongarch/insn_trans/trans_fmemory.c.inc
469
index XXXXXXX..XXXXXXX 100644
470
--- a/target/loongarch/insn_trans/trans_fmemory.c.inc
471
+++ b/target/loongarch/insn_trans/trans_fmemory.c.inc
472
@@ -XXX,XX +XXX,XX @@ static bool gen_fstore_le(DisasContext *ctx, arg_frr *a, MemOp mop)
473
return true;
474
}
475
476
-TRANS(fld_s, gen_fload_i, MO_TEUL)
477
-TRANS(fst_s, gen_fstore_i, MO_TEUL)
478
-TRANS(fld_d, gen_fload_i, MO_TEUQ)
479
-TRANS(fst_d, gen_fstore_i, MO_TEUQ)
480
-TRANS(fldx_s, gen_floadx, MO_TEUL)
481
-TRANS(fldx_d, gen_floadx, MO_TEUQ)
482
-TRANS(fstx_s, gen_fstorex, MO_TEUL)
483
-TRANS(fstx_d, gen_fstorex, MO_TEUQ)
484
-TRANS(fldgt_s, gen_fload_gt, MO_TEUL)
485
-TRANS(fldgt_d, gen_fload_gt, MO_TEUQ)
486
-TRANS(fldle_s, gen_fload_le, MO_TEUL)
487
-TRANS(fldle_d, gen_fload_le, MO_TEUQ)
488
-TRANS(fstgt_s, gen_fstore_gt, MO_TEUL)
489
-TRANS(fstgt_d, gen_fstore_gt, MO_TEUQ)
490
-TRANS(fstle_s, gen_fstore_le, MO_TEUL)
491
-TRANS(fstle_d, gen_fstore_le, MO_TEUQ)
492
+TRANS(fld_s, ALL, gen_fload_i, MO_TEUL)
493
+TRANS(fst_s, ALL, gen_fstore_i, MO_TEUL)
494
+TRANS(fld_d, ALL, gen_fload_i, MO_TEUQ)
495
+TRANS(fst_d, ALL, gen_fstore_i, MO_TEUQ)
496
+TRANS(fldx_s, ALL, gen_floadx, MO_TEUL)
497
+TRANS(fldx_d, ALL, gen_floadx, MO_TEUQ)
498
+TRANS(fstx_s, ALL, gen_fstorex, MO_TEUL)
499
+TRANS(fstx_d, ALL, gen_fstorex, MO_TEUQ)
500
+TRANS(fldgt_s, ALL, gen_fload_gt, MO_TEUL)
501
+TRANS(fldgt_d, ALL, gen_fload_gt, MO_TEUQ)
502
+TRANS(fldle_s, ALL, gen_fload_le, MO_TEUL)
503
+TRANS(fldle_d, ALL, gen_fload_le, MO_TEUQ)
504
+TRANS(fstgt_s, ALL, gen_fstore_gt, MO_TEUL)
505
+TRANS(fstgt_d, ALL, gen_fstore_gt, MO_TEUQ)
506
+TRANS(fstle_s, ALL, gen_fstore_le, MO_TEUL)
507
+TRANS(fstle_d, ALL, gen_fstore_le, MO_TEUQ)
508
diff --git a/target/loongarch/insn_trans/trans_fmov.c.inc b/target/loongarch/insn_trans/trans_fmov.c.inc
509
index XXXXXXX..XXXXXXX 100644
510
--- a/target/loongarch/insn_trans/trans_fmov.c.inc
511
+++ b/target/loongarch/insn_trans/trans_fmov.c.inc
512
@@ -XXX,XX +XXX,XX @@ static bool trans_movcf2gr(DisasContext *ctx, arg_movcf2gr *a)
513
return true;
514
}
515
516
-TRANS(fmov_s, gen_f2f, tcg_gen_mov_tl, true)
517
-TRANS(fmov_d, gen_f2f, tcg_gen_mov_tl, false)
518
-TRANS(movgr2fr_w, gen_r2f, gen_movgr2fr_w)
519
-TRANS(movgr2fr_d, gen_r2f, tcg_gen_mov_tl)
520
-TRANS(movgr2frh_w, gen_r2f, gen_movgr2frh_w)
521
-TRANS(movfr2gr_s, gen_f2r, tcg_gen_ext32s_tl)
522
-TRANS(movfr2gr_d, gen_f2r, tcg_gen_mov_tl)
523
-TRANS(movfrh2gr_s, gen_f2r, gen_movfrh2gr_s)
524
+TRANS(fmov_s, ALL, gen_f2f, tcg_gen_mov_tl, true)
525
+TRANS(fmov_d, ALL, gen_f2f, tcg_gen_mov_tl, false)
526
+TRANS(movgr2fr_w, ALL, gen_r2f, gen_movgr2fr_w)
527
+TRANS(movgr2fr_d, ALL, gen_r2f, tcg_gen_mov_tl)
528
+TRANS(movgr2frh_w, ALL, gen_r2f, gen_movgr2frh_w)
529
+TRANS(movfr2gr_s, ALL, gen_f2r, tcg_gen_ext32s_tl)
530
+TRANS(movfr2gr_d, ALL, gen_f2r, tcg_gen_mov_tl)
531
+TRANS(movfrh2gr_s, ALL, gen_f2r, gen_movfrh2gr_s)
532
diff --git a/target/loongarch/insn_trans/trans_lsx.c.inc b/target/loongarch/insn_trans/trans_lsx.c.inc
533
index XXXXXXX..XXXXXXX 100644
534
--- a/target/loongarch/insn_trans/trans_lsx.c.inc
535
+++ b/target/loongarch/insn_trans/trans_lsx.c.inc
536
@@ -XXX,XX +XXX,XX @@ static bool gvec_subi(DisasContext *ctx, arg_vv_i *a, MemOp mop)
537
return true;
538
}
539
540
-TRANS(vadd_b, gvec_vvv, MO_8, tcg_gen_gvec_add)
541
-TRANS(vadd_h, gvec_vvv, MO_16, tcg_gen_gvec_add)
542
-TRANS(vadd_w, gvec_vvv, MO_32, tcg_gen_gvec_add)
543
-TRANS(vadd_d, gvec_vvv, MO_64, tcg_gen_gvec_add)
544
+TRANS(vadd_b, ALL, gvec_vvv, MO_8, tcg_gen_gvec_add)
545
+TRANS(vadd_h, ALL, gvec_vvv, MO_16, tcg_gen_gvec_add)
546
+TRANS(vadd_w, ALL, gvec_vvv, MO_32, tcg_gen_gvec_add)
547
+TRANS(vadd_d, ALL, gvec_vvv, MO_64, tcg_gen_gvec_add)
548
549
#define VADDSUB_Q(NAME) \
550
static bool trans_v## NAME ##_q(DisasContext *ctx, arg_vvv *a) \
551
@@ -XXX,XX +XXX,XX @@ static bool trans_v## NAME ##_q(DisasContext *ctx, arg_vvv *a) \
552
VADDSUB_Q(add)
553
VADDSUB_Q(sub)
554
555
-TRANS(vsub_b, gvec_vvv, MO_8, tcg_gen_gvec_sub)
556
-TRANS(vsub_h, gvec_vvv, MO_16, tcg_gen_gvec_sub)
557
-TRANS(vsub_w, gvec_vvv, MO_32, tcg_gen_gvec_sub)
558
-TRANS(vsub_d, gvec_vvv, MO_64, tcg_gen_gvec_sub)
559
-
560
-TRANS(vaddi_bu, gvec_vv_i, MO_8, tcg_gen_gvec_addi)
561
-TRANS(vaddi_hu, gvec_vv_i, MO_16, tcg_gen_gvec_addi)
562
-TRANS(vaddi_wu, gvec_vv_i, MO_32, tcg_gen_gvec_addi)
563
-TRANS(vaddi_du, gvec_vv_i, MO_64, tcg_gen_gvec_addi)
564
-TRANS(vsubi_bu, gvec_subi, MO_8)
565
-TRANS(vsubi_hu, gvec_subi, MO_16)
566
-TRANS(vsubi_wu, gvec_subi, MO_32)
567
-TRANS(vsubi_du, gvec_subi, MO_64)
568
-
569
-TRANS(vneg_b, gvec_vv, MO_8, tcg_gen_gvec_neg)
570
-TRANS(vneg_h, gvec_vv, MO_16, tcg_gen_gvec_neg)
571
-TRANS(vneg_w, gvec_vv, MO_32, tcg_gen_gvec_neg)
572
-TRANS(vneg_d, gvec_vv, MO_64, tcg_gen_gvec_neg)
573
-
574
-TRANS(vsadd_b, gvec_vvv, MO_8, tcg_gen_gvec_ssadd)
575
-TRANS(vsadd_h, gvec_vvv, MO_16, tcg_gen_gvec_ssadd)
576
-TRANS(vsadd_w, gvec_vvv, MO_32, tcg_gen_gvec_ssadd)
577
-TRANS(vsadd_d, gvec_vvv, MO_64, tcg_gen_gvec_ssadd)
578
-TRANS(vsadd_bu, gvec_vvv, MO_8, tcg_gen_gvec_usadd)
579
-TRANS(vsadd_hu, gvec_vvv, MO_16, tcg_gen_gvec_usadd)
580
-TRANS(vsadd_wu, gvec_vvv, MO_32, tcg_gen_gvec_usadd)
581
-TRANS(vsadd_du, gvec_vvv, MO_64, tcg_gen_gvec_usadd)
582
-TRANS(vssub_b, gvec_vvv, MO_8, tcg_gen_gvec_sssub)
583
-TRANS(vssub_h, gvec_vvv, MO_16, tcg_gen_gvec_sssub)
584
-TRANS(vssub_w, gvec_vvv, MO_32, tcg_gen_gvec_sssub)
585
-TRANS(vssub_d, gvec_vvv, MO_64, tcg_gen_gvec_sssub)
586
-TRANS(vssub_bu, gvec_vvv, MO_8, tcg_gen_gvec_ussub)
587
-TRANS(vssub_hu, gvec_vvv, MO_16, tcg_gen_gvec_ussub)
588
-TRANS(vssub_wu, gvec_vvv, MO_32, tcg_gen_gvec_ussub)
589
-TRANS(vssub_du, gvec_vvv, MO_64, tcg_gen_gvec_ussub)
590
-
591
-TRANS(vhaddw_h_b, gen_vvv, gen_helper_vhaddw_h_b)
592
-TRANS(vhaddw_w_h, gen_vvv, gen_helper_vhaddw_w_h)
593
-TRANS(vhaddw_d_w, gen_vvv, gen_helper_vhaddw_d_w)
594
-TRANS(vhaddw_q_d, gen_vvv, gen_helper_vhaddw_q_d)
595
-TRANS(vhaddw_hu_bu, gen_vvv, gen_helper_vhaddw_hu_bu)
596
-TRANS(vhaddw_wu_hu, gen_vvv, gen_helper_vhaddw_wu_hu)
597
-TRANS(vhaddw_du_wu, gen_vvv, gen_helper_vhaddw_du_wu)
598
-TRANS(vhaddw_qu_du, gen_vvv, gen_helper_vhaddw_qu_du)
599
-TRANS(vhsubw_h_b, gen_vvv, gen_helper_vhsubw_h_b)
600
-TRANS(vhsubw_w_h, gen_vvv, gen_helper_vhsubw_w_h)
601
-TRANS(vhsubw_d_w, gen_vvv, gen_helper_vhsubw_d_w)
602
-TRANS(vhsubw_q_d, gen_vvv, gen_helper_vhsubw_q_d)
603
-TRANS(vhsubw_hu_bu, gen_vvv, gen_helper_vhsubw_hu_bu)
604
-TRANS(vhsubw_wu_hu, gen_vvv, gen_helper_vhsubw_wu_hu)
605
-TRANS(vhsubw_du_wu, gen_vvv, gen_helper_vhsubw_du_wu)
606
-TRANS(vhsubw_qu_du, gen_vvv, gen_helper_vhsubw_qu_du)
607
+TRANS(vsub_b, ALL, gvec_vvv, MO_8, tcg_gen_gvec_sub)
608
+TRANS(vsub_h, ALL, gvec_vvv, MO_16, tcg_gen_gvec_sub)
609
+TRANS(vsub_w, ALL, gvec_vvv, MO_32, tcg_gen_gvec_sub)
610
+TRANS(vsub_d, ALL, gvec_vvv, MO_64, tcg_gen_gvec_sub)
611
+
612
+TRANS(vaddi_bu, ALL, gvec_vv_i, MO_8, tcg_gen_gvec_addi)
613
+TRANS(vaddi_hu, ALL, gvec_vv_i, MO_16, tcg_gen_gvec_addi)
614
+TRANS(vaddi_wu, ALL, gvec_vv_i, MO_32, tcg_gen_gvec_addi)
615
+TRANS(vaddi_du, ALL, gvec_vv_i, MO_64, tcg_gen_gvec_addi)
616
+TRANS(vsubi_bu, ALL, gvec_subi, MO_8)
617
+TRANS(vsubi_hu, ALL, gvec_subi, MO_16)
618
+TRANS(vsubi_wu, ALL, gvec_subi, MO_32)
619
+TRANS(vsubi_du, ALL, gvec_subi, MO_64)
620
+
621
+TRANS(vneg_b, ALL, gvec_vv, MO_8, tcg_gen_gvec_neg)
622
+TRANS(vneg_h, ALL, gvec_vv, MO_16, tcg_gen_gvec_neg)
623
+TRANS(vneg_w, ALL, gvec_vv, MO_32, tcg_gen_gvec_neg)
624
+TRANS(vneg_d, ALL, gvec_vv, MO_64, tcg_gen_gvec_neg)
625
+
626
+TRANS(vsadd_b, ALL, gvec_vvv, MO_8, tcg_gen_gvec_ssadd)
627
+TRANS(vsadd_h, ALL, gvec_vvv, MO_16, tcg_gen_gvec_ssadd)
628
+TRANS(vsadd_w, ALL, gvec_vvv, MO_32, tcg_gen_gvec_ssadd)
629
+TRANS(vsadd_d, ALL, gvec_vvv, MO_64, tcg_gen_gvec_ssadd)
630
+TRANS(vsadd_bu, ALL, gvec_vvv, MO_8, tcg_gen_gvec_usadd)
631
+TRANS(vsadd_hu, ALL, gvec_vvv, MO_16, tcg_gen_gvec_usadd)
632
+TRANS(vsadd_wu, ALL, gvec_vvv, MO_32, tcg_gen_gvec_usadd)
633
+TRANS(vsadd_du, ALL, gvec_vvv, MO_64, tcg_gen_gvec_usadd)
634
+TRANS(vssub_b, ALL, gvec_vvv, MO_8, tcg_gen_gvec_sssub)
635
+TRANS(vssub_h, ALL, gvec_vvv, MO_16, tcg_gen_gvec_sssub)
636
+TRANS(vssub_w, ALL, gvec_vvv, MO_32, tcg_gen_gvec_sssub)
637
+TRANS(vssub_d, ALL, gvec_vvv, MO_64, tcg_gen_gvec_sssub)
638
+TRANS(vssub_bu, ALL, gvec_vvv, MO_8, tcg_gen_gvec_ussub)
639
+TRANS(vssub_hu, ALL, gvec_vvv, MO_16, tcg_gen_gvec_ussub)
640
+TRANS(vssub_wu, ALL, gvec_vvv, MO_32, tcg_gen_gvec_ussub)
641
+TRANS(vssub_du, ALL, gvec_vvv, MO_64, tcg_gen_gvec_ussub)
642
+
643
+TRANS(vhaddw_h_b, ALL, gen_vvv, gen_helper_vhaddw_h_b)
644
+TRANS(vhaddw_w_h, ALL, gen_vvv, gen_helper_vhaddw_w_h)
645
+TRANS(vhaddw_d_w, ALL, gen_vvv, gen_helper_vhaddw_d_w)
646
+TRANS(vhaddw_q_d, ALL, gen_vvv, gen_helper_vhaddw_q_d)
647
+TRANS(vhaddw_hu_bu, ALL, gen_vvv, gen_helper_vhaddw_hu_bu)
648
+TRANS(vhaddw_wu_hu, ALL, gen_vvv, gen_helper_vhaddw_wu_hu)
649
+TRANS(vhaddw_du_wu, ALL, gen_vvv, gen_helper_vhaddw_du_wu)
650
+TRANS(vhaddw_qu_du, ALL, gen_vvv, gen_helper_vhaddw_qu_du)
651
+TRANS(vhsubw_h_b, ALL, gen_vvv, gen_helper_vhsubw_h_b)
652
+TRANS(vhsubw_w_h, ALL, gen_vvv, gen_helper_vhsubw_w_h)
653
+TRANS(vhsubw_d_w, ALL, gen_vvv, gen_helper_vhsubw_d_w)
654
+TRANS(vhsubw_q_d, ALL, gen_vvv, gen_helper_vhsubw_q_d)
655
+TRANS(vhsubw_hu_bu, ALL, gen_vvv, gen_helper_vhsubw_hu_bu)
656
+TRANS(vhsubw_wu_hu, ALL, gen_vvv, gen_helper_vhsubw_wu_hu)
657
+TRANS(vhsubw_du_wu, ALL, gen_vvv, gen_helper_vhsubw_du_wu)
658
+TRANS(vhsubw_qu_du, ALL, gen_vvv, gen_helper_vhsubw_qu_du)
659
660
static void gen_vaddwev_s(unsigned vece, TCGv_vec t, TCGv_vec a, TCGv_vec b)
661
{
662
@@ -XXX,XX +XXX,XX @@ static void do_vaddwev_s(unsigned vece, uint32_t vd_ofs, uint32_t vj_ofs,
663
tcg_gen_gvec_3(vd_ofs, vj_ofs, vk_ofs, oprsz, maxsz, &op[vece]);
664
}
665
666
-TRANS(vaddwev_h_b, gvec_vvv, MO_8, do_vaddwev_s)
667
-TRANS(vaddwev_w_h, gvec_vvv, MO_16, do_vaddwev_s)
668
-TRANS(vaddwev_d_w, gvec_vvv, MO_32, do_vaddwev_s)
669
-TRANS(vaddwev_q_d, gvec_vvv, MO_64, do_vaddwev_s)
670
+TRANS(vaddwev_h_b, ALL, gvec_vvv, MO_8, do_vaddwev_s)
671
+TRANS(vaddwev_w_h, ALL, gvec_vvv, MO_16, do_vaddwev_s)
672
+TRANS(vaddwev_d_w, ALL, gvec_vvv, MO_32, do_vaddwev_s)
673
+TRANS(vaddwev_q_d, ALL, gvec_vvv, MO_64, do_vaddwev_s)
674
675
static void gen_vaddwod_w_h(TCGv_i32 t, TCGv_i32 a, TCGv_i32 b)
676
{
677
@@ -XXX,XX +XXX,XX @@ static void do_vaddwod_s(unsigned vece, uint32_t vd_ofs, uint32_t vj_ofs,
678
tcg_gen_gvec_3(vd_ofs, vj_ofs, vk_ofs, oprsz, maxsz, &op[vece]);
679
}
680
681
-TRANS(vaddwod_h_b, gvec_vvv, MO_8, do_vaddwod_s)
682
-TRANS(vaddwod_w_h, gvec_vvv, MO_16, do_vaddwod_s)
683
-TRANS(vaddwod_d_w, gvec_vvv, MO_32, do_vaddwod_s)
684
-TRANS(vaddwod_q_d, gvec_vvv, MO_64, do_vaddwod_s)
685
+TRANS(vaddwod_h_b, ALL, gvec_vvv, MO_8, do_vaddwod_s)
686
+TRANS(vaddwod_w_h, ALL, gvec_vvv, MO_16, do_vaddwod_s)
687
+TRANS(vaddwod_d_w, ALL, gvec_vvv, MO_32, do_vaddwod_s)
688
+TRANS(vaddwod_q_d, ALL, gvec_vvv, MO_64, do_vaddwod_s)
689
690
static void gen_vsubwev_s(unsigned vece, TCGv_vec t, TCGv_vec a, TCGv_vec b)
691
{
692
@@ -XXX,XX +XXX,XX @@ static void do_vsubwev_s(unsigned vece, uint32_t vd_ofs, uint32_t vj_ofs,
693
tcg_gen_gvec_3(vd_ofs, vj_ofs, vk_ofs, oprsz, maxsz, &op[vece]);
694
}
695
696
-TRANS(vsubwev_h_b, gvec_vvv, MO_8, do_vsubwev_s)
697
-TRANS(vsubwev_w_h, gvec_vvv, MO_16, do_vsubwev_s)
698
-TRANS(vsubwev_d_w, gvec_vvv, MO_32, do_vsubwev_s)
699
-TRANS(vsubwev_q_d, gvec_vvv, MO_64, do_vsubwev_s)
700
+TRANS(vsubwev_h_b, ALL, gvec_vvv, MO_8, do_vsubwev_s)
701
+TRANS(vsubwev_w_h, ALL, gvec_vvv, MO_16, do_vsubwev_s)
702
+TRANS(vsubwev_d_w, ALL, gvec_vvv, MO_32, do_vsubwev_s)
703
+TRANS(vsubwev_q_d, ALL, gvec_vvv, MO_64, do_vsubwev_s)
704
705
static void gen_vsubwod_s(unsigned vece, TCGv_vec t, TCGv_vec a, TCGv_vec b)
706
{
707
@@ -XXX,XX +XXX,XX @@ static void do_vsubwod_s(unsigned vece, uint32_t vd_ofs, uint32_t vj_ofs,
708
tcg_gen_gvec_3(vd_ofs, vj_ofs, vk_ofs, oprsz, maxsz, &op[vece]);
709
}
710
711
-TRANS(vsubwod_h_b, gvec_vvv, MO_8, do_vsubwod_s)
712
-TRANS(vsubwod_w_h, gvec_vvv, MO_16, do_vsubwod_s)
713
-TRANS(vsubwod_d_w, gvec_vvv, MO_32, do_vsubwod_s)
714
-TRANS(vsubwod_q_d, gvec_vvv, MO_64, do_vsubwod_s)
715
+TRANS(vsubwod_h_b, ALL, gvec_vvv, MO_8, do_vsubwod_s)
716
+TRANS(vsubwod_w_h, ALL, gvec_vvv, MO_16, do_vsubwod_s)
717
+TRANS(vsubwod_d_w, ALL, gvec_vvv, MO_32, do_vsubwod_s)
718
+TRANS(vsubwod_q_d, ALL, gvec_vvv, MO_64, do_vsubwod_s)
719
720
static void gen_vaddwev_u(unsigned vece, TCGv_vec t, TCGv_vec a, TCGv_vec b)
721
{
722
@@ -XXX,XX +XXX,XX @@ static void do_vaddwev_u(unsigned vece, uint32_t vd_ofs, uint32_t vj_ofs,
723
tcg_gen_gvec_3(vd_ofs, vj_ofs, vk_ofs, oprsz, maxsz, &op[vece]);
724
}
725
726
-TRANS(vaddwev_h_bu, gvec_vvv, MO_8, do_vaddwev_u)
727
-TRANS(vaddwev_w_hu, gvec_vvv, MO_16, do_vaddwev_u)
728
-TRANS(vaddwev_d_wu, gvec_vvv, MO_32, do_vaddwev_u)
729
-TRANS(vaddwev_q_du, gvec_vvv, MO_64, do_vaddwev_u)
730
+TRANS(vaddwev_h_bu, ALL, gvec_vvv, MO_8, do_vaddwev_u)
731
+TRANS(vaddwev_w_hu, ALL, gvec_vvv, MO_16, do_vaddwev_u)
732
+TRANS(vaddwev_d_wu, ALL, gvec_vvv, MO_32, do_vaddwev_u)
733
+TRANS(vaddwev_q_du, ALL, gvec_vvv, MO_64, do_vaddwev_u)
734
735
static void gen_vaddwod_u(unsigned vece, TCGv_vec t, TCGv_vec a, TCGv_vec b)
736
{
737
@@ -XXX,XX +XXX,XX @@ static void do_vaddwod_u(unsigned vece, uint32_t vd_ofs, uint32_t vj_ofs,
738
tcg_gen_gvec_3(vd_ofs, vj_ofs, vk_ofs, oprsz, maxsz, &op[vece]);
739
}
740
741
-TRANS(vaddwod_h_bu, gvec_vvv, MO_8, do_vaddwod_u)
742
-TRANS(vaddwod_w_hu, gvec_vvv, MO_16, do_vaddwod_u)
743
-TRANS(vaddwod_d_wu, gvec_vvv, MO_32, do_vaddwod_u)
744
-TRANS(vaddwod_q_du, gvec_vvv, MO_64, do_vaddwod_u)
745
+TRANS(vaddwod_h_bu, ALL, gvec_vvv, MO_8, do_vaddwod_u)
746
+TRANS(vaddwod_w_hu, ALL, gvec_vvv, MO_16, do_vaddwod_u)
747
+TRANS(vaddwod_d_wu, ALL, gvec_vvv, MO_32, do_vaddwod_u)
748
+TRANS(vaddwod_q_du, ALL, gvec_vvv, MO_64, do_vaddwod_u)
749
750
static void gen_vsubwev_u(unsigned vece, TCGv_vec t, TCGv_vec a, TCGv_vec b)
751
{
752
@@ -XXX,XX +XXX,XX @@ static void do_vsubwev_u(unsigned vece, uint32_t vd_ofs, uint32_t vj_ofs,
753
tcg_gen_gvec_3(vd_ofs, vj_ofs, vk_ofs, oprsz, maxsz, &op[vece]);
754
}
755
756
-TRANS(vsubwev_h_bu, gvec_vvv, MO_8, do_vsubwev_u)
757
-TRANS(vsubwev_w_hu, gvec_vvv, MO_16, do_vsubwev_u)
758
-TRANS(vsubwev_d_wu, gvec_vvv, MO_32, do_vsubwev_u)
759
-TRANS(vsubwev_q_du, gvec_vvv, MO_64, do_vsubwev_u)
760
+TRANS(vsubwev_h_bu, ALL, gvec_vvv, MO_8, do_vsubwev_u)
761
+TRANS(vsubwev_w_hu, ALL, gvec_vvv, MO_16, do_vsubwev_u)
762
+TRANS(vsubwev_d_wu, ALL, gvec_vvv, MO_32, do_vsubwev_u)
763
+TRANS(vsubwev_q_du, ALL, gvec_vvv, MO_64, do_vsubwev_u)
764
765
static void gen_vsubwod_u(unsigned vece, TCGv_vec t, TCGv_vec a, TCGv_vec b)
766
{
767
@@ -XXX,XX +XXX,XX @@ static void do_vsubwod_u(unsigned vece, uint32_t vd_ofs, uint32_t vj_ofs,
768
tcg_gen_gvec_3(vd_ofs, vj_ofs, vk_ofs, oprsz, maxsz, &op[vece]);
769
}
770
771
-TRANS(vsubwod_h_bu, gvec_vvv, MO_8, do_vsubwod_u)
772
-TRANS(vsubwod_w_hu, gvec_vvv, MO_16, do_vsubwod_u)
773
-TRANS(vsubwod_d_wu, gvec_vvv, MO_32, do_vsubwod_u)
774
-TRANS(vsubwod_q_du, gvec_vvv, MO_64, do_vsubwod_u)
775
+TRANS(vsubwod_h_bu, ALL, gvec_vvv, MO_8, do_vsubwod_u)
776
+TRANS(vsubwod_w_hu, ALL, gvec_vvv, MO_16, do_vsubwod_u)
777
+TRANS(vsubwod_d_wu, ALL, gvec_vvv, MO_32, do_vsubwod_u)
778
+TRANS(vsubwod_q_du, ALL, gvec_vvv, MO_64, do_vsubwod_u)
779
780
static void gen_vaddwev_u_s(unsigned vece, TCGv_vec t, TCGv_vec a, TCGv_vec b)
781
{
782
@@ -XXX,XX +XXX,XX @@ static void do_vaddwev_u_s(unsigned vece, uint32_t vd_ofs, uint32_t vj_ofs,
783
tcg_gen_gvec_3(vd_ofs, vj_ofs, vk_ofs, oprsz, maxsz, &op[vece]);
784
}
785
786
-TRANS(vaddwev_h_bu_b, gvec_vvv, MO_8, do_vaddwev_u_s)
787
-TRANS(vaddwev_w_hu_h, gvec_vvv, MO_16, do_vaddwev_u_s)
788
-TRANS(vaddwev_d_wu_w, gvec_vvv, MO_32, do_vaddwev_u_s)
789
-TRANS(vaddwev_q_du_d, gvec_vvv, MO_64, do_vaddwev_u_s)
790
+TRANS(vaddwev_h_bu_b, ALL, gvec_vvv, MO_8, do_vaddwev_u_s)
791
+TRANS(vaddwev_w_hu_h, ALL, gvec_vvv, MO_16, do_vaddwev_u_s)
792
+TRANS(vaddwev_d_wu_w, ALL, gvec_vvv, MO_32, do_vaddwev_u_s)
793
+TRANS(vaddwev_q_du_d, ALL, gvec_vvv, MO_64, do_vaddwev_u_s)
794
795
static void gen_vaddwod_u_s(unsigned vece, TCGv_vec t, TCGv_vec a, TCGv_vec b)
796
{
797
@@ -XXX,XX +XXX,XX @@ static void do_vaddwod_u_s(unsigned vece, uint32_t vd_ofs, uint32_t vj_ofs,
798
tcg_gen_gvec_3(vd_ofs, vj_ofs, vk_ofs, oprsz, maxsz, &op[vece]);
799
}
800
801
-TRANS(vaddwod_h_bu_b, gvec_vvv, MO_8, do_vaddwod_u_s)
802
-TRANS(vaddwod_w_hu_h, gvec_vvv, MO_16, do_vaddwod_u_s)
803
-TRANS(vaddwod_d_wu_w, gvec_vvv, MO_32, do_vaddwod_u_s)
804
-TRANS(vaddwod_q_du_d, gvec_vvv, MO_64, do_vaddwod_u_s)
805
+TRANS(vaddwod_h_bu_b, ALL, gvec_vvv, MO_8, do_vaddwod_u_s)
806
+TRANS(vaddwod_w_hu_h, ALL, gvec_vvv, MO_16, do_vaddwod_u_s)
807
+TRANS(vaddwod_d_wu_w, ALL, gvec_vvv, MO_32, do_vaddwod_u_s)
808
+TRANS(vaddwod_q_du_d, ALL, gvec_vvv, MO_64, do_vaddwod_u_s)
809
810
static void do_vavg(unsigned vece, TCGv_vec t, TCGv_vec a, TCGv_vec b,
811
void (*gen_shr_vec)(unsigned, TCGv_vec,
812
@@ -XXX,XX +XXX,XX @@ static void do_vavg_u(unsigned vece, uint32_t vd_ofs, uint32_t vj_ofs,
813
tcg_gen_gvec_3(vd_ofs, vj_ofs, vk_ofs, oprsz, maxsz, &op[vece]);
814
}
815
816
-TRANS(vavg_b, gvec_vvv, MO_8, do_vavg_s)
817
-TRANS(vavg_h, gvec_vvv, MO_16, do_vavg_s)
818
-TRANS(vavg_w, gvec_vvv, MO_32, do_vavg_s)
819
-TRANS(vavg_d, gvec_vvv, MO_64, do_vavg_s)
820
-TRANS(vavg_bu, gvec_vvv, MO_8, do_vavg_u)
821
-TRANS(vavg_hu, gvec_vvv, MO_16, do_vavg_u)
822
-TRANS(vavg_wu, gvec_vvv, MO_32, do_vavg_u)
823
-TRANS(vavg_du, gvec_vvv, MO_64, do_vavg_u)
824
+TRANS(vavg_b, ALL, gvec_vvv, MO_8, do_vavg_s)
825
+TRANS(vavg_h, ALL, gvec_vvv, MO_16, do_vavg_s)
826
+TRANS(vavg_w, ALL, gvec_vvv, MO_32, do_vavg_s)
827
+TRANS(vavg_d, ALL, gvec_vvv, MO_64, do_vavg_s)
828
+TRANS(vavg_bu, ALL, gvec_vvv, MO_8, do_vavg_u)
829
+TRANS(vavg_hu, ALL, gvec_vvv, MO_16, do_vavg_u)
830
+TRANS(vavg_wu, ALL, gvec_vvv, MO_32, do_vavg_u)
831
+TRANS(vavg_du, ALL, gvec_vvv, MO_64, do_vavg_u)
832
833
static void do_vavgr_s(unsigned vece, uint32_t vd_ofs, uint32_t vj_ofs,
834
uint32_t vk_ofs, uint32_t oprsz, uint32_t maxsz)
835
@@ -XXX,XX +XXX,XX @@ static void do_vavgr_u(unsigned vece, uint32_t vd_ofs, uint32_t vj_ofs,
836
tcg_gen_gvec_3(vd_ofs, vj_ofs, vk_ofs, oprsz, maxsz, &op[vece]);
837
}
838
839
-TRANS(vavgr_b, gvec_vvv, MO_8, do_vavgr_s)
840
-TRANS(vavgr_h, gvec_vvv, MO_16, do_vavgr_s)
841
-TRANS(vavgr_w, gvec_vvv, MO_32, do_vavgr_s)
842
-TRANS(vavgr_d, gvec_vvv, MO_64, do_vavgr_s)
843
-TRANS(vavgr_bu, gvec_vvv, MO_8, do_vavgr_u)
844
-TRANS(vavgr_hu, gvec_vvv, MO_16, do_vavgr_u)
845
-TRANS(vavgr_wu, gvec_vvv, MO_32, do_vavgr_u)
846
-TRANS(vavgr_du, gvec_vvv, MO_64, do_vavgr_u)
847
+TRANS(vavgr_b, ALL, gvec_vvv, MO_8, do_vavgr_s)
848
+TRANS(vavgr_h, ALL, gvec_vvv, MO_16, do_vavgr_s)
849
+TRANS(vavgr_w, ALL, gvec_vvv, MO_32, do_vavgr_s)
850
+TRANS(vavgr_d, ALL, gvec_vvv, MO_64, do_vavgr_s)
851
+TRANS(vavgr_bu, ALL, gvec_vvv, MO_8, do_vavgr_u)
852
+TRANS(vavgr_hu, ALL, gvec_vvv, MO_16, do_vavgr_u)
853
+TRANS(vavgr_wu, ALL, gvec_vvv, MO_32, do_vavgr_u)
854
+TRANS(vavgr_du, ALL, gvec_vvv, MO_64, do_vavgr_u)
855
856
static void gen_vabsd_s(unsigned vece, TCGv_vec t, TCGv_vec a, TCGv_vec b)
857
{
858
@@ -XXX,XX +XXX,XX @@ static void do_vabsd_u(unsigned vece, uint32_t vd_ofs, uint32_t vj_ofs,
859
tcg_gen_gvec_3(vd_ofs, vj_ofs, vk_ofs, oprsz, maxsz, &op[vece]);
860
}
861
862
-TRANS(vabsd_b, gvec_vvv, MO_8, do_vabsd_s)
863
-TRANS(vabsd_h, gvec_vvv, MO_16, do_vabsd_s)
864
-TRANS(vabsd_w, gvec_vvv, MO_32, do_vabsd_s)
865
-TRANS(vabsd_d, gvec_vvv, MO_64, do_vabsd_s)
866
-TRANS(vabsd_bu, gvec_vvv, MO_8, do_vabsd_u)
867
-TRANS(vabsd_hu, gvec_vvv, MO_16, do_vabsd_u)
868
-TRANS(vabsd_wu, gvec_vvv, MO_32, do_vabsd_u)
869
-TRANS(vabsd_du, gvec_vvv, MO_64, do_vabsd_u)
870
+TRANS(vabsd_b, ALL, gvec_vvv, MO_8, do_vabsd_s)
871
+TRANS(vabsd_h, ALL, gvec_vvv, MO_16, do_vabsd_s)
872
+TRANS(vabsd_w, ALL, gvec_vvv, MO_32, do_vabsd_s)
873
+TRANS(vabsd_d, ALL, gvec_vvv, MO_64, do_vabsd_s)
874
+TRANS(vabsd_bu, ALL, gvec_vvv, MO_8, do_vabsd_u)
875
+TRANS(vabsd_hu, ALL, gvec_vvv, MO_16, do_vabsd_u)
876
+TRANS(vabsd_wu, ALL, gvec_vvv, MO_32, do_vabsd_u)
877
+TRANS(vabsd_du, ALL, gvec_vvv, MO_64, do_vabsd_u)
878
879
static void gen_vadda(unsigned vece, TCGv_vec t, TCGv_vec a, TCGv_vec b)
880
{
881
@@ -XXX,XX +XXX,XX @@ static void do_vadda(unsigned vece, uint32_t vd_ofs, uint32_t vj_ofs,
882
tcg_gen_gvec_3(vd_ofs, vj_ofs, vk_ofs, oprsz, maxsz, &op[vece]);
883
}
884
885
-TRANS(vadda_b, gvec_vvv, MO_8, do_vadda)
886
-TRANS(vadda_h, gvec_vvv, MO_16, do_vadda)
887
-TRANS(vadda_w, gvec_vvv, MO_32, do_vadda)
888
-TRANS(vadda_d, gvec_vvv, MO_64, do_vadda)
889
-
890
-TRANS(vmax_b, gvec_vvv, MO_8, tcg_gen_gvec_smax)
891
-TRANS(vmax_h, gvec_vvv, MO_16, tcg_gen_gvec_smax)
892
-TRANS(vmax_w, gvec_vvv, MO_32, tcg_gen_gvec_smax)
893
-TRANS(vmax_d, gvec_vvv, MO_64, tcg_gen_gvec_smax)
894
-TRANS(vmax_bu, gvec_vvv, MO_8, tcg_gen_gvec_umax)
895
-TRANS(vmax_hu, gvec_vvv, MO_16, tcg_gen_gvec_umax)
896
-TRANS(vmax_wu, gvec_vvv, MO_32, tcg_gen_gvec_umax)
897
-TRANS(vmax_du, gvec_vvv, MO_64, tcg_gen_gvec_umax)
898
-
899
-TRANS(vmin_b, gvec_vvv, MO_8, tcg_gen_gvec_smin)
900
-TRANS(vmin_h, gvec_vvv, MO_16, tcg_gen_gvec_smin)
901
-TRANS(vmin_w, gvec_vvv, MO_32, tcg_gen_gvec_smin)
902
-TRANS(vmin_d, gvec_vvv, MO_64, tcg_gen_gvec_smin)
903
-TRANS(vmin_bu, gvec_vvv, MO_8, tcg_gen_gvec_umin)
904
-TRANS(vmin_hu, gvec_vvv, MO_16, tcg_gen_gvec_umin)
905
-TRANS(vmin_wu, gvec_vvv, MO_32, tcg_gen_gvec_umin)
906
-TRANS(vmin_du, gvec_vvv, MO_64, tcg_gen_gvec_umin)
907
+TRANS(vadda_b, ALL, gvec_vvv, MO_8, do_vadda)
908
+TRANS(vadda_h, ALL, gvec_vvv, MO_16, do_vadda)
909
+TRANS(vadda_w, ALL, gvec_vvv, MO_32, do_vadda)
910
+TRANS(vadda_d, ALL, gvec_vvv, MO_64, do_vadda)
911
+
912
+TRANS(vmax_b, ALL, gvec_vvv, MO_8, tcg_gen_gvec_smax)
913
+TRANS(vmax_h, ALL, gvec_vvv, MO_16, tcg_gen_gvec_smax)
914
+TRANS(vmax_w, ALL, gvec_vvv, MO_32, tcg_gen_gvec_smax)
915
+TRANS(vmax_d, ALL, gvec_vvv, MO_64, tcg_gen_gvec_smax)
916
+TRANS(vmax_bu, ALL, gvec_vvv, MO_8, tcg_gen_gvec_umax)
917
+TRANS(vmax_hu, ALL, gvec_vvv, MO_16, tcg_gen_gvec_umax)
918
+TRANS(vmax_wu, ALL, gvec_vvv, MO_32, tcg_gen_gvec_umax)
919
+TRANS(vmax_du, ALL, gvec_vvv, MO_64, tcg_gen_gvec_umax)
920
+
921
+TRANS(vmin_b, ALL, gvec_vvv, MO_8, tcg_gen_gvec_smin)
922
+TRANS(vmin_h, ALL, gvec_vvv, MO_16, tcg_gen_gvec_smin)
923
+TRANS(vmin_w, ALL, gvec_vvv, MO_32, tcg_gen_gvec_smin)
924
+TRANS(vmin_d, ALL, gvec_vvv, MO_64, tcg_gen_gvec_smin)
925
+TRANS(vmin_bu, ALL, gvec_vvv, MO_8, tcg_gen_gvec_umin)
926
+TRANS(vmin_hu, ALL, gvec_vvv, MO_16, tcg_gen_gvec_umin)
927
+TRANS(vmin_wu, ALL, gvec_vvv, MO_32, tcg_gen_gvec_umin)
928
+TRANS(vmin_du, ALL, gvec_vvv, MO_64, tcg_gen_gvec_umin)
929
930
static void gen_vmini_s(unsigned vece, TCGv_vec t, TCGv_vec a, int64_t imm)
931
{
932
@@ -XXX,XX +XXX,XX @@ static void do_vmini_u(unsigned vece, uint32_t vd_ofs, uint32_t vj_ofs,
933
tcg_gen_gvec_2i(vd_ofs, vj_ofs, oprsz, maxsz, imm, &op[vece]);
934
}
935
936
-TRANS(vmini_b, gvec_vv_i, MO_8, do_vmini_s)
937
-TRANS(vmini_h, gvec_vv_i, MO_16, do_vmini_s)
938
-TRANS(vmini_w, gvec_vv_i, MO_32, do_vmini_s)
939
-TRANS(vmini_d, gvec_vv_i, MO_64, do_vmini_s)
940
-TRANS(vmini_bu, gvec_vv_i, MO_8, do_vmini_u)
941
-TRANS(vmini_hu, gvec_vv_i, MO_16, do_vmini_u)
942
-TRANS(vmini_wu, gvec_vv_i, MO_32, do_vmini_u)
943
-TRANS(vmini_du, gvec_vv_i, MO_64, do_vmini_u)
944
+TRANS(vmini_b, ALL, gvec_vv_i, MO_8, do_vmini_s)
945
+TRANS(vmini_h, ALL, gvec_vv_i, MO_16, do_vmini_s)
946
+TRANS(vmini_w, ALL, gvec_vv_i, MO_32, do_vmini_s)
947
+TRANS(vmini_d, ALL, gvec_vv_i, MO_64, do_vmini_s)
948
+TRANS(vmini_bu, ALL, gvec_vv_i, MO_8, do_vmini_u)
949
+TRANS(vmini_hu, ALL, gvec_vv_i, MO_16, do_vmini_u)
950
+TRANS(vmini_wu, ALL, gvec_vv_i, MO_32, do_vmini_u)
951
+TRANS(vmini_du, ALL, gvec_vv_i, MO_64, do_vmini_u)
952
953
static void do_vmaxi_s(unsigned vece, uint32_t vd_ofs, uint32_t vj_ofs,
954
int64_t imm, uint32_t oprsz, uint32_t maxsz)
955
@@ -XXX,XX +XXX,XX @@ static void do_vmaxi_u(unsigned vece, uint32_t vd_ofs, uint32_t vj_ofs,
956
tcg_gen_gvec_2i(vd_ofs, vj_ofs, oprsz, maxsz, imm, &op[vece]);
957
}
958
959
-TRANS(vmaxi_b, gvec_vv_i, MO_8, do_vmaxi_s)
960
-TRANS(vmaxi_h, gvec_vv_i, MO_16, do_vmaxi_s)
961
-TRANS(vmaxi_w, gvec_vv_i, MO_32, do_vmaxi_s)
962
-TRANS(vmaxi_d, gvec_vv_i, MO_64, do_vmaxi_s)
963
-TRANS(vmaxi_bu, gvec_vv_i, MO_8, do_vmaxi_u)
964
-TRANS(vmaxi_hu, gvec_vv_i, MO_16, do_vmaxi_u)
965
-TRANS(vmaxi_wu, gvec_vv_i, MO_32, do_vmaxi_u)
966
-TRANS(vmaxi_du, gvec_vv_i, MO_64, do_vmaxi_u)
967
+TRANS(vmaxi_b, ALL, gvec_vv_i, MO_8, do_vmaxi_s)
968
+TRANS(vmaxi_h, ALL, gvec_vv_i, MO_16, do_vmaxi_s)
969
+TRANS(vmaxi_w, ALL, gvec_vv_i, MO_32, do_vmaxi_s)
970
+TRANS(vmaxi_d, ALL, gvec_vv_i, MO_64, do_vmaxi_s)
971
+TRANS(vmaxi_bu, ALL, gvec_vv_i, MO_8, do_vmaxi_u)
972
+TRANS(vmaxi_hu, ALL, gvec_vv_i, MO_16, do_vmaxi_u)
973
+TRANS(vmaxi_wu, ALL, gvec_vv_i, MO_32, do_vmaxi_u)
974
+TRANS(vmaxi_du, ALL, gvec_vv_i, MO_64, do_vmaxi_u)
975
976
-TRANS(vmul_b, gvec_vvv, MO_8, tcg_gen_gvec_mul)
977
-TRANS(vmul_h, gvec_vvv, MO_16, tcg_gen_gvec_mul)
978
-TRANS(vmul_w, gvec_vvv, MO_32, tcg_gen_gvec_mul)
979
-TRANS(vmul_d, gvec_vvv, MO_64, tcg_gen_gvec_mul)
980
+TRANS(vmul_b, ALL, gvec_vvv, MO_8, tcg_gen_gvec_mul)
981
+TRANS(vmul_h, ALL, gvec_vvv, MO_16, tcg_gen_gvec_mul)
982
+TRANS(vmul_w, ALL, gvec_vvv, MO_32, tcg_gen_gvec_mul)
983
+TRANS(vmul_d, ALL, gvec_vvv, MO_64, tcg_gen_gvec_mul)
984
985
static void gen_vmuh_w(TCGv_i32 t, TCGv_i32 a, TCGv_i32 b)
986
{
987
@@ -XXX,XX +XXX,XX @@ static void do_vmuh_s(unsigned vece, uint32_t vd_ofs, uint32_t vj_ofs,
988
tcg_gen_gvec_3(vd_ofs, vj_ofs, vk_ofs, oprsz, maxsz, &op[vece]);
989
}
990
991
-TRANS(vmuh_b, gvec_vvv, MO_8, do_vmuh_s)
992
-TRANS(vmuh_h, gvec_vvv, MO_16, do_vmuh_s)
993
-TRANS(vmuh_w, gvec_vvv, MO_32, do_vmuh_s)
994
-TRANS(vmuh_d, gvec_vvv, MO_64, do_vmuh_s)
995
+TRANS(vmuh_b, ALL, gvec_vvv, MO_8, do_vmuh_s)
996
+TRANS(vmuh_h, ALL, gvec_vvv, MO_16, do_vmuh_s)
997
+TRANS(vmuh_w, ALL, gvec_vvv, MO_32, do_vmuh_s)
998
+TRANS(vmuh_d, ALL, gvec_vvv, MO_64, do_vmuh_s)
999
1000
static void gen_vmuh_wu(TCGv_i32 t, TCGv_i32 a, TCGv_i32 b)
1001
{
1002
@@ -XXX,XX +XXX,XX @@ static void do_vmuh_u(unsigned vece, uint32_t vd_ofs, uint32_t vj_ofs,
1003
tcg_gen_gvec_3(vd_ofs, vj_ofs, vk_ofs, oprsz, maxsz, &op[vece]);
1004
}
1005
1006
-TRANS(vmuh_bu, gvec_vvv, MO_8, do_vmuh_u)
1007
-TRANS(vmuh_hu, gvec_vvv, MO_16, do_vmuh_u)
1008
-TRANS(vmuh_wu, gvec_vvv, MO_32, do_vmuh_u)
1009
-TRANS(vmuh_du, gvec_vvv, MO_64, do_vmuh_u)
1010
+TRANS(vmuh_bu, ALL, gvec_vvv, MO_8, do_vmuh_u)
1011
+TRANS(vmuh_hu, ALL, gvec_vvv, MO_16, do_vmuh_u)
1012
+TRANS(vmuh_wu, ALL, gvec_vvv, MO_32, do_vmuh_u)
1013
+TRANS(vmuh_du, ALL, gvec_vvv, MO_64, do_vmuh_u)
1014
1015
static void gen_vmulwev_s(unsigned vece, TCGv_vec t, TCGv_vec a, TCGv_vec b)
1016
{
1017
@@ -XXX,XX +XXX,XX @@ static void do_vmulwev_s(unsigned vece, uint32_t vd_ofs, uint32_t vj_ofs,
1018
tcg_gen_gvec_3(vd_ofs, vj_ofs, vk_ofs, oprsz, maxsz, &op[vece]);
1019
}
1020
1021
-TRANS(vmulwev_h_b, gvec_vvv, MO_8, do_vmulwev_s)
1022
-TRANS(vmulwev_w_h, gvec_vvv, MO_16, do_vmulwev_s)
1023
-TRANS(vmulwev_d_w, gvec_vvv, MO_32, do_vmulwev_s)
1024
+TRANS(vmulwev_h_b, ALL, gvec_vvv, MO_8, do_vmulwev_s)
1025
+TRANS(vmulwev_w_h, ALL, gvec_vvv, MO_16, do_vmulwev_s)
1026
+TRANS(vmulwev_d_w, ALL, gvec_vvv, MO_32, do_vmulwev_s)
1027
1028
static void tcg_gen_mulus2_i64(TCGv_i64 rl, TCGv_i64 rh,
1029
TCGv_i64 arg1, TCGv_i64 arg2)
1030
@@ -XXX,XX +XXX,XX @@ static void do_vmulwod_s(unsigned vece, uint32_t vd_ofs, uint32_t vj_ofs,
1031
tcg_gen_gvec_3(vd_ofs, vj_ofs, vk_ofs, oprsz, maxsz, &op[vece]);
1032
}
1033
1034
-TRANS(vmulwod_h_b, gvec_vvv, MO_8, do_vmulwod_s)
1035
-TRANS(vmulwod_w_h, gvec_vvv, MO_16, do_vmulwod_s)
1036
-TRANS(vmulwod_d_w, gvec_vvv, MO_32, do_vmulwod_s)
1037
+TRANS(vmulwod_h_b, ALL, gvec_vvv, MO_8, do_vmulwod_s)
1038
+TRANS(vmulwod_w_h, ALL, gvec_vvv, MO_16, do_vmulwod_s)
1039
+TRANS(vmulwod_d_w, ALL, gvec_vvv, MO_32, do_vmulwod_s)
1040
1041
static void gen_vmulwev_u(unsigned vece, TCGv_vec t, TCGv_vec a, TCGv_vec b)
1042
{
1043
@@ -XXX,XX +XXX,XX @@ static void do_vmulwev_u(unsigned vece, uint32_t vd_ofs, uint32_t vj_ofs,
1044
tcg_gen_gvec_3(vd_ofs, vj_ofs, vk_ofs, oprsz, maxsz, &op[vece]);
1045
}
1046
1047
-TRANS(vmulwev_h_bu, gvec_vvv, MO_8, do_vmulwev_u)
1048
-TRANS(vmulwev_w_hu, gvec_vvv, MO_16, do_vmulwev_u)
1049
-TRANS(vmulwev_d_wu, gvec_vvv, MO_32, do_vmulwev_u)
1050
+TRANS(vmulwev_h_bu, ALL, gvec_vvv, MO_8, do_vmulwev_u)
1051
+TRANS(vmulwev_w_hu, ALL, gvec_vvv, MO_16, do_vmulwev_u)
1052
+TRANS(vmulwev_d_wu, ALL, gvec_vvv, MO_32, do_vmulwev_u)
1053
1054
static void gen_vmulwod_u(unsigned vece, TCGv_vec t, TCGv_vec a, TCGv_vec b)
1055
{
1056
@@ -XXX,XX +XXX,XX @@ static void do_vmulwod_u(unsigned vece, uint32_t vd_ofs, uint32_t vj_ofs,
1057
tcg_gen_gvec_3(vd_ofs, vj_ofs, vk_ofs, oprsz, maxsz, &op[vece]);
1058
}
1059
1060
-TRANS(vmulwod_h_bu, gvec_vvv, MO_8, do_vmulwod_u)
1061
-TRANS(vmulwod_w_hu, gvec_vvv, MO_16, do_vmulwod_u)
1062
-TRANS(vmulwod_d_wu, gvec_vvv, MO_32, do_vmulwod_u)
1063
+TRANS(vmulwod_h_bu, ALL, gvec_vvv, MO_8, do_vmulwod_u)
1064
+TRANS(vmulwod_w_hu, ALL, gvec_vvv, MO_16, do_vmulwod_u)
1065
+TRANS(vmulwod_d_wu, ALL, gvec_vvv, MO_32, do_vmulwod_u)
1066
1067
static void gen_vmulwev_u_s(unsigned vece, TCGv_vec t, TCGv_vec a, TCGv_vec b)
1068
{
1069
@@ -XXX,XX +XXX,XX @@ static void do_vmulwev_u_s(unsigned vece, uint32_t vd_ofs, uint32_t vj_ofs,
1070
tcg_gen_gvec_3(vd_ofs, vj_ofs, vk_ofs, oprsz, maxsz, &op[vece]);
1071
}
1072
1073
-TRANS(vmulwev_h_bu_b, gvec_vvv, MO_8, do_vmulwev_u_s)
1074
-TRANS(vmulwev_w_hu_h, gvec_vvv, MO_16, do_vmulwev_u_s)
1075
-TRANS(vmulwev_d_wu_w, gvec_vvv, MO_32, do_vmulwev_u_s)
1076
+TRANS(vmulwev_h_bu_b, ALL, gvec_vvv, MO_8, do_vmulwev_u_s)
1077
+TRANS(vmulwev_w_hu_h, ALL, gvec_vvv, MO_16, do_vmulwev_u_s)
1078
+TRANS(vmulwev_d_wu_w, ALL, gvec_vvv, MO_32, do_vmulwev_u_s)
1079
1080
static void gen_vmulwod_u_s(unsigned vece, TCGv_vec t, TCGv_vec a, TCGv_vec b)
1081
{
1082
@@ -XXX,XX +XXX,XX @@ static void do_vmulwod_u_s(unsigned vece, uint32_t vd_ofs, uint32_t vj_ofs,
1083
tcg_gen_gvec_3(vd_ofs, vj_ofs, vk_ofs, oprsz, maxsz, &op[vece]);
1084
}
1085
1086
-TRANS(vmulwod_h_bu_b, gvec_vvv, MO_8, do_vmulwod_u_s)
1087
-TRANS(vmulwod_w_hu_h, gvec_vvv, MO_16, do_vmulwod_u_s)
1088
-TRANS(vmulwod_d_wu_w, gvec_vvv, MO_32, do_vmulwod_u_s)
1089
+TRANS(vmulwod_h_bu_b, ALL, gvec_vvv, MO_8, do_vmulwod_u_s)
1090
+TRANS(vmulwod_w_hu_h, ALL, gvec_vvv, MO_16, do_vmulwod_u_s)
1091
+TRANS(vmulwod_d_wu_w, ALL, gvec_vvv, MO_32, do_vmulwod_u_s)
1092
1093
static void gen_vmadd(unsigned vece, TCGv_vec t, TCGv_vec a, TCGv_vec b)
1094
{
1095
@@ -XXX,XX +XXX,XX @@ static void do_vmadd(unsigned vece, uint32_t vd_ofs, uint32_t vj_ofs,
1096
tcg_gen_gvec_3(vd_ofs, vj_ofs, vk_ofs, oprsz, maxsz, &op[vece]);
1097
}
1098
1099
-TRANS(vmadd_b, gvec_vvv, MO_8, do_vmadd)
1100
-TRANS(vmadd_h, gvec_vvv, MO_16, do_vmadd)
1101
-TRANS(vmadd_w, gvec_vvv, MO_32, do_vmadd)
1102
-TRANS(vmadd_d, gvec_vvv, MO_64, do_vmadd)
1103
+TRANS(vmadd_b, ALL, gvec_vvv, MO_8, do_vmadd)
1104
+TRANS(vmadd_h, ALL, gvec_vvv, MO_16, do_vmadd)
1105
+TRANS(vmadd_w, ALL, gvec_vvv, MO_32, do_vmadd)
1106
+TRANS(vmadd_d, ALL, gvec_vvv, MO_64, do_vmadd)
1107
1108
static void gen_vmsub(unsigned vece, TCGv_vec t, TCGv_vec a, TCGv_vec b)
1109
{
1110
@@ -XXX,XX +XXX,XX @@ static void do_vmsub(unsigned vece, uint32_t vd_ofs, uint32_t vj_ofs,
1111
tcg_gen_gvec_3(vd_ofs, vj_ofs, vk_ofs, oprsz, maxsz, &op[vece]);
1112
}
1113
1114
-TRANS(vmsub_b, gvec_vvv, MO_8, do_vmsub)
1115
-TRANS(vmsub_h, gvec_vvv, MO_16, do_vmsub)
1116
-TRANS(vmsub_w, gvec_vvv, MO_32, do_vmsub)
1117
-TRANS(vmsub_d, gvec_vvv, MO_64, do_vmsub)
1118
+TRANS(vmsub_b, ALL, gvec_vvv, MO_8, do_vmsub)
1119
+TRANS(vmsub_h, ALL, gvec_vvv, MO_16, do_vmsub)
1120
+TRANS(vmsub_w, ALL, gvec_vvv, MO_32, do_vmsub)
1121
+TRANS(vmsub_d, ALL, gvec_vvv, MO_64, do_vmsub)
1122
1123
static void gen_vmaddwev_s(unsigned vece, TCGv_vec t, TCGv_vec a, TCGv_vec b)
1124
{
1125
@@ -XXX,XX +XXX,XX @@ static void do_vmaddwev_s(unsigned vece, uint32_t vd_ofs, uint32_t vj_ofs,
1126
tcg_gen_gvec_3(vd_ofs, vj_ofs, vk_ofs, oprsz, maxsz, &op[vece]);
1127
}
1128
1129
-TRANS(vmaddwev_h_b, gvec_vvv, MO_8, do_vmaddwev_s)
1130
-TRANS(vmaddwev_w_h, gvec_vvv, MO_16, do_vmaddwev_s)
1131
-TRANS(vmaddwev_d_w, gvec_vvv, MO_32, do_vmaddwev_s)
1132
+TRANS(vmaddwev_h_b, ALL, gvec_vvv, MO_8, do_vmaddwev_s)
1133
+TRANS(vmaddwev_w_h, ALL, gvec_vvv, MO_16, do_vmaddwev_s)
1134
+TRANS(vmaddwev_d_w, ALL, gvec_vvv, MO_32, do_vmaddwev_s)
1135
1136
#define VMADD_Q(NAME, FN, idx1, idx2) \
1137
static bool trans_## NAME (DisasContext *ctx, arg_vvv *a) \
1138
@@ -XXX,XX +XXX,XX @@ static void do_vmaddwod_s(unsigned vece, uint32_t vd_ofs, uint32_t vj_ofs,
1139
tcg_gen_gvec_3(vd_ofs, vj_ofs, vk_ofs, oprsz, maxsz, &op[vece]);
1140
}
1141
1142
-TRANS(vmaddwod_h_b, gvec_vvv, MO_8, do_vmaddwod_s)
1143
-TRANS(vmaddwod_w_h, gvec_vvv, MO_16, do_vmaddwod_s)
1144
-TRANS(vmaddwod_d_w, gvec_vvv, MO_32, do_vmaddwod_s)
1145
+TRANS(vmaddwod_h_b, ALL, gvec_vvv, MO_8, do_vmaddwod_s)
1146
+TRANS(vmaddwod_w_h, ALL, gvec_vvv, MO_16, do_vmaddwod_s)
1147
+TRANS(vmaddwod_d_w, ALL, gvec_vvv, MO_32, do_vmaddwod_s)
1148
1149
static void gen_vmaddwev_u(unsigned vece, TCGv_vec t, TCGv_vec a, TCGv_vec b)
1150
{
1151
@@ -XXX,XX +XXX,XX @@ static void do_vmaddwev_u(unsigned vece, uint32_t vd_ofs, uint32_t vj_ofs,
1152
tcg_gen_gvec_3(vd_ofs, vj_ofs, vk_ofs, oprsz, maxsz, &op[vece]);
1153
}
1154
1155
-TRANS(vmaddwev_h_bu, gvec_vvv, MO_8, do_vmaddwev_u)
1156
-TRANS(vmaddwev_w_hu, gvec_vvv, MO_16, do_vmaddwev_u)
1157
-TRANS(vmaddwev_d_wu, gvec_vvv, MO_32, do_vmaddwev_u)
1158
+TRANS(vmaddwev_h_bu, ALL, gvec_vvv, MO_8, do_vmaddwev_u)
1159
+TRANS(vmaddwev_w_hu, ALL, gvec_vvv, MO_16, do_vmaddwev_u)
1160
+TRANS(vmaddwev_d_wu, ALL, gvec_vvv, MO_32, do_vmaddwev_u)
1161
1162
static void gen_vmaddwod_u(unsigned vece, TCGv_vec t, TCGv_vec a, TCGv_vec b)
1163
{
1164
@@ -XXX,XX +XXX,XX @@ static void do_vmaddwod_u(unsigned vece, uint32_t vd_ofs, uint32_t vj_ofs,
1165
tcg_gen_gvec_3(vd_ofs, vj_ofs, vk_ofs, oprsz, maxsz, &op[vece]);
1166
}
1167
1168
-TRANS(vmaddwod_h_bu, gvec_vvv, MO_8, do_vmaddwod_u)
1169
-TRANS(vmaddwod_w_hu, gvec_vvv, MO_16, do_vmaddwod_u)
1170
-TRANS(vmaddwod_d_wu, gvec_vvv, MO_32, do_vmaddwod_u)
1171
+TRANS(vmaddwod_h_bu, ALL, gvec_vvv, MO_8, do_vmaddwod_u)
1172
+TRANS(vmaddwod_w_hu, ALL, gvec_vvv, MO_16, do_vmaddwod_u)
1173
+TRANS(vmaddwod_d_wu, ALL, gvec_vvv, MO_32, do_vmaddwod_u)
1174
1175
static void gen_vmaddwev_u_s(unsigned vece, TCGv_vec t, TCGv_vec a, TCGv_vec b)
1176
{
1177
@@ -XXX,XX +XXX,XX @@ static void do_vmaddwev_u_s(unsigned vece, uint32_t vd_ofs, uint32_t vj_ofs,
1178
tcg_gen_gvec_3(vd_ofs, vj_ofs, vk_ofs, oprsz, maxsz, &op[vece]);
1179
}
1180
1181
-TRANS(vmaddwev_h_bu_b, gvec_vvv, MO_8, do_vmaddwev_u_s)
1182
-TRANS(vmaddwev_w_hu_h, gvec_vvv, MO_16, do_vmaddwev_u_s)
1183
-TRANS(vmaddwev_d_wu_w, gvec_vvv, MO_32, do_vmaddwev_u_s)
1184
+TRANS(vmaddwev_h_bu_b, ALL, gvec_vvv, MO_8, do_vmaddwev_u_s)
1185
+TRANS(vmaddwev_w_hu_h, ALL, gvec_vvv, MO_16, do_vmaddwev_u_s)
1186
+TRANS(vmaddwev_d_wu_w, ALL, gvec_vvv, MO_32, do_vmaddwev_u_s)
1187
1188
static void gen_vmaddwod_u_s(unsigned vece, TCGv_vec t, TCGv_vec a, TCGv_vec b)
1189
{
1190
@@ -XXX,XX +XXX,XX @@ static void do_vmaddwod_u_s(unsigned vece, uint32_t vd_ofs, uint32_t vj_ofs,
1191
tcg_gen_gvec_3(vd_ofs, vj_ofs, vk_ofs, oprsz, maxsz, &op[vece]);
1192
}
1193
1194
-TRANS(vmaddwod_h_bu_b, gvec_vvv, MO_8, do_vmaddwod_u_s)
1195
-TRANS(vmaddwod_w_hu_h, gvec_vvv, MO_16, do_vmaddwod_u_s)
1196
-TRANS(vmaddwod_d_wu_w, gvec_vvv, MO_32, do_vmaddwod_u_s)
1197
-
1198
-TRANS(vdiv_b, gen_vvv, gen_helper_vdiv_b)
1199
-TRANS(vdiv_h, gen_vvv, gen_helper_vdiv_h)
1200
-TRANS(vdiv_w, gen_vvv, gen_helper_vdiv_w)
1201
-TRANS(vdiv_d, gen_vvv, gen_helper_vdiv_d)
1202
-TRANS(vdiv_bu, gen_vvv, gen_helper_vdiv_bu)
1203
-TRANS(vdiv_hu, gen_vvv, gen_helper_vdiv_hu)
1204
-TRANS(vdiv_wu, gen_vvv, gen_helper_vdiv_wu)
1205
-TRANS(vdiv_du, gen_vvv, gen_helper_vdiv_du)
1206
-TRANS(vmod_b, gen_vvv, gen_helper_vmod_b)
1207
-TRANS(vmod_h, gen_vvv, gen_helper_vmod_h)
1208
-TRANS(vmod_w, gen_vvv, gen_helper_vmod_w)
1209
-TRANS(vmod_d, gen_vvv, gen_helper_vmod_d)
1210
-TRANS(vmod_bu, gen_vvv, gen_helper_vmod_bu)
1211
-TRANS(vmod_hu, gen_vvv, gen_helper_vmod_hu)
1212
-TRANS(vmod_wu, gen_vvv, gen_helper_vmod_wu)
1213
-TRANS(vmod_du, gen_vvv, gen_helper_vmod_du)
1214
+TRANS(vmaddwod_h_bu_b, ALL, gvec_vvv, MO_8, do_vmaddwod_u_s)
1215
+TRANS(vmaddwod_w_hu_h, ALL, gvec_vvv, MO_16, do_vmaddwod_u_s)
1216
+TRANS(vmaddwod_d_wu_w, ALL, gvec_vvv, MO_32, do_vmaddwod_u_s)
1217
+
1218
+TRANS(vdiv_b, ALL, gen_vvv, gen_helper_vdiv_b)
1219
+TRANS(vdiv_h, ALL, gen_vvv, gen_helper_vdiv_h)
1220
+TRANS(vdiv_w, ALL, gen_vvv, gen_helper_vdiv_w)
1221
+TRANS(vdiv_d, ALL, gen_vvv, gen_helper_vdiv_d)
1222
+TRANS(vdiv_bu, ALL, gen_vvv, gen_helper_vdiv_bu)
1223
+TRANS(vdiv_hu, ALL, gen_vvv, gen_helper_vdiv_hu)
1224
+TRANS(vdiv_wu, ALL, gen_vvv, gen_helper_vdiv_wu)
1225
+TRANS(vdiv_du, ALL, gen_vvv, gen_helper_vdiv_du)
1226
+TRANS(vmod_b, ALL, gen_vvv, gen_helper_vmod_b)
1227
+TRANS(vmod_h, ALL, gen_vvv, gen_helper_vmod_h)
1228
+TRANS(vmod_w, ALL, gen_vvv, gen_helper_vmod_w)
1229
+TRANS(vmod_d, ALL, gen_vvv, gen_helper_vmod_d)
1230
+TRANS(vmod_bu, ALL, gen_vvv, gen_helper_vmod_bu)
1231
+TRANS(vmod_hu, ALL, gen_vvv, gen_helper_vmod_hu)
1232
+TRANS(vmod_wu, ALL, gen_vvv, gen_helper_vmod_wu)
1233
+TRANS(vmod_du, ALL, gen_vvv, gen_helper_vmod_du)
1234
1235
static void gen_vsat_s(unsigned vece, TCGv_vec t, TCGv_vec a, TCGv_vec max)
1236
{
1237
@@ -XXX,XX +XXX,XX @@ static void do_vsat_s(unsigned vece, uint32_t vd_ofs, uint32_t vj_ofs,
1238
tcg_constant_i64((1ll<< imm) -1), &op[vece]);
1239
}
1240
1241
-TRANS(vsat_b, gvec_vv_i, MO_8, do_vsat_s)
1242
-TRANS(vsat_h, gvec_vv_i, MO_16, do_vsat_s)
1243
-TRANS(vsat_w, gvec_vv_i, MO_32, do_vsat_s)
1244
-TRANS(vsat_d, gvec_vv_i, MO_64, do_vsat_s)
1245
+TRANS(vsat_b, ALL, gvec_vv_i, MO_8, do_vsat_s)
1246
+TRANS(vsat_h, ALL, gvec_vv_i, MO_16, do_vsat_s)
1247
+TRANS(vsat_w, ALL, gvec_vv_i, MO_32, do_vsat_s)
1248
+TRANS(vsat_d, ALL, gvec_vv_i, MO_64, do_vsat_s)
1249
1250
static void gen_vsat_u(unsigned vece, TCGv_vec t, TCGv_vec a, TCGv_vec max)
1251
{
1252
@@ -XXX,XX +XXX,XX @@ static void do_vsat_u(unsigned vece, uint32_t vd_ofs, uint32_t vj_ofs,
1253
tcg_constant_i64(max), &op[vece]);
1254
}
1255
1256
-TRANS(vsat_bu, gvec_vv_i, MO_8, do_vsat_u)
1257
-TRANS(vsat_hu, gvec_vv_i, MO_16, do_vsat_u)
1258
-TRANS(vsat_wu, gvec_vv_i, MO_32, do_vsat_u)
1259
-TRANS(vsat_du, gvec_vv_i, MO_64, do_vsat_u)
1260
+TRANS(vsat_bu, ALL, gvec_vv_i, MO_8, do_vsat_u)
1261
+TRANS(vsat_hu, ALL, gvec_vv_i, MO_16, do_vsat_u)
1262
+TRANS(vsat_wu, ALL, gvec_vv_i, MO_32, do_vsat_u)
1263
+TRANS(vsat_du, ALL, gvec_vv_i, MO_64, do_vsat_u)
1264
1265
-TRANS(vexth_h_b, gen_vv, gen_helper_vexth_h_b)
1266
-TRANS(vexth_w_h, gen_vv, gen_helper_vexth_w_h)
1267
-TRANS(vexth_d_w, gen_vv, gen_helper_vexth_d_w)
1268
-TRANS(vexth_q_d, gen_vv, gen_helper_vexth_q_d)
1269
-TRANS(vexth_hu_bu, gen_vv, gen_helper_vexth_hu_bu)
1270
-TRANS(vexth_wu_hu, gen_vv, gen_helper_vexth_wu_hu)
1271
-TRANS(vexth_du_wu, gen_vv, gen_helper_vexth_du_wu)
1272
-TRANS(vexth_qu_du, gen_vv, gen_helper_vexth_qu_du)
1273
+TRANS(vexth_h_b, ALL, gen_vv, gen_helper_vexth_h_b)
1274
+TRANS(vexth_w_h, ALL, gen_vv, gen_helper_vexth_w_h)
1275
+TRANS(vexth_d_w, ALL, gen_vv, gen_helper_vexth_d_w)
1276
+TRANS(vexth_q_d, ALL, gen_vv, gen_helper_vexth_q_d)
1277
+TRANS(vexth_hu_bu, ALL, gen_vv, gen_helper_vexth_hu_bu)
1278
+TRANS(vexth_wu_hu, ALL, gen_vv, gen_helper_vexth_wu_hu)
1279
+TRANS(vexth_du_wu, ALL, gen_vv, gen_helper_vexth_du_wu)
1280
+TRANS(vexth_qu_du, ALL, gen_vv, gen_helper_vexth_qu_du)
1281
1282
static void gen_vsigncov(unsigned vece, TCGv_vec t, TCGv_vec a, TCGv_vec b)
1283
{
1284
@@ -XXX,XX +XXX,XX @@ static void do_vsigncov(unsigned vece, uint32_t vd_ofs, uint32_t vj_ofs,
1285
tcg_gen_gvec_3(vd_ofs, vj_ofs, vk_ofs, oprsz, maxsz, &op[vece]);
1286
}
1287
1288
-TRANS(vsigncov_b, gvec_vvv, MO_8, do_vsigncov)
1289
-TRANS(vsigncov_h, gvec_vvv, MO_16, do_vsigncov)
1290
-TRANS(vsigncov_w, gvec_vvv, MO_32, do_vsigncov)
1291
-TRANS(vsigncov_d, gvec_vvv, MO_64, do_vsigncov)
1292
+TRANS(vsigncov_b, ALL, gvec_vvv, MO_8, do_vsigncov)
1293
+TRANS(vsigncov_h, ALL, gvec_vvv, MO_16, do_vsigncov)
1294
+TRANS(vsigncov_w, ALL, gvec_vvv, MO_32, do_vsigncov)
1295
+TRANS(vsigncov_d, ALL, gvec_vvv, MO_64, do_vsigncov)
1296
1297
-TRANS(vmskltz_b, gen_vv, gen_helper_vmskltz_b)
1298
-TRANS(vmskltz_h, gen_vv, gen_helper_vmskltz_h)
1299
-TRANS(vmskltz_w, gen_vv, gen_helper_vmskltz_w)
1300
-TRANS(vmskltz_d, gen_vv, gen_helper_vmskltz_d)
1301
-TRANS(vmskgez_b, gen_vv, gen_helper_vmskgez_b)
1302
-TRANS(vmsknz_b, gen_vv, gen_helper_vmsknz_b)
1303
+TRANS(vmskltz_b, ALL, gen_vv, gen_helper_vmskltz_b)
1304
+TRANS(vmskltz_h, ALL, gen_vv, gen_helper_vmskltz_h)
1305
+TRANS(vmskltz_w, ALL, gen_vv, gen_helper_vmskltz_w)
1306
+TRANS(vmskltz_d, ALL, gen_vv, gen_helper_vmskltz_d)
1307
+TRANS(vmskgez_b, ALL, gen_vv, gen_helper_vmskgez_b)
1308
+TRANS(vmsknz_b, ALL, gen_vv, gen_helper_vmsknz_b)
1309
1310
#define EXPAND_BYTE(bit) ((uint64_t)(bit ? 0xff : 0))
1311
1312
@@ -XXX,XX +XXX,XX @@ static bool trans_vldi(DisasContext *ctx, arg_vldi *a)
1313
return true;
1314
}
1315
1316
-TRANS(vand_v, gvec_vvv, MO_64, tcg_gen_gvec_and)
1317
-TRANS(vor_v, gvec_vvv, MO_64, tcg_gen_gvec_or)
1318
-TRANS(vxor_v, gvec_vvv, MO_64, tcg_gen_gvec_xor)
1319
-TRANS(vnor_v, gvec_vvv, MO_64, tcg_gen_gvec_nor)
1320
+TRANS(vand_v, ALL, gvec_vvv, MO_64, tcg_gen_gvec_and)
1321
+TRANS(vor_v, ALL, gvec_vvv, MO_64, tcg_gen_gvec_or)
1322
+TRANS(vxor_v, ALL, gvec_vvv, MO_64, tcg_gen_gvec_xor)
1323
+TRANS(vnor_v, ALL, gvec_vvv, MO_64, tcg_gen_gvec_nor)
1324
1325
static bool trans_vandn_v(DisasContext *ctx, arg_vvv *a)
1326
{
1327
@@ -XXX,XX +XXX,XX @@ static bool trans_vandn_v(DisasContext *ctx, arg_vvv *a)
1328
tcg_gen_gvec_andc(MO_64, vd_ofs, vk_ofs, vj_ofs, 16, ctx->vl/8);
1329
return true;
1330
}
1331
-TRANS(vorn_v, gvec_vvv, MO_64, tcg_gen_gvec_orc)
1332
-TRANS(vandi_b, gvec_vv_i, MO_8, tcg_gen_gvec_andi)
1333
-TRANS(vori_b, gvec_vv_i, MO_8, tcg_gen_gvec_ori)
1334
-TRANS(vxori_b, gvec_vv_i, MO_8, tcg_gen_gvec_xori)
1335
+TRANS(vorn_v, ALL, gvec_vvv, MO_64, tcg_gen_gvec_orc)
1336
+TRANS(vandi_b, ALL, gvec_vv_i, MO_8, tcg_gen_gvec_andi)
1337
+TRANS(vori_b, ALL, gvec_vv_i, MO_8, tcg_gen_gvec_ori)
1338
+TRANS(vxori_b, ALL, gvec_vv_i, MO_8, tcg_gen_gvec_xori)
1339
1340
static void gen_vnori(unsigned vece, TCGv_vec t, TCGv_vec a, int64_t imm)
1341
{
1342
@@ -XXX,XX +XXX,XX @@ static void do_vnori_b(unsigned vece, uint32_t vd_ofs, uint32_t vj_ofs,
1343
tcg_gen_gvec_2i(vd_ofs, vj_ofs, oprsz, maxsz, imm, &op);
1344
}
1345
1346
-TRANS(vnori_b, gvec_vv_i, MO_8, do_vnori_b)
1347
-
1348
-TRANS(vsll_b, gvec_vvv, MO_8, tcg_gen_gvec_shlv)
1349
-TRANS(vsll_h, gvec_vvv, MO_16, tcg_gen_gvec_shlv)
1350
-TRANS(vsll_w, gvec_vvv, MO_32, tcg_gen_gvec_shlv)
1351
-TRANS(vsll_d, gvec_vvv, MO_64, tcg_gen_gvec_shlv)
1352
-TRANS(vslli_b, gvec_vv_i, MO_8, tcg_gen_gvec_shli)
1353
-TRANS(vslli_h, gvec_vv_i, MO_16, tcg_gen_gvec_shli)
1354
-TRANS(vslli_w, gvec_vv_i, MO_32, tcg_gen_gvec_shli)
1355
-TRANS(vslli_d, gvec_vv_i, MO_64, tcg_gen_gvec_shli)
1356
-
1357
-TRANS(vsrl_b, gvec_vvv, MO_8, tcg_gen_gvec_shrv)
1358
-TRANS(vsrl_h, gvec_vvv, MO_16, tcg_gen_gvec_shrv)
1359
-TRANS(vsrl_w, gvec_vvv, MO_32, tcg_gen_gvec_shrv)
1360
-TRANS(vsrl_d, gvec_vvv, MO_64, tcg_gen_gvec_shrv)
1361
-TRANS(vsrli_b, gvec_vv_i, MO_8, tcg_gen_gvec_shri)
1362
-TRANS(vsrli_h, gvec_vv_i, MO_16, tcg_gen_gvec_shri)
1363
-TRANS(vsrli_w, gvec_vv_i, MO_32, tcg_gen_gvec_shri)
1364
-TRANS(vsrli_d, gvec_vv_i, MO_64, tcg_gen_gvec_shri)
1365
-
1366
-TRANS(vsra_b, gvec_vvv, MO_8, tcg_gen_gvec_sarv)
1367
-TRANS(vsra_h, gvec_vvv, MO_16, tcg_gen_gvec_sarv)
1368
-TRANS(vsra_w, gvec_vvv, MO_32, tcg_gen_gvec_sarv)
1369
-TRANS(vsra_d, gvec_vvv, MO_64, tcg_gen_gvec_sarv)
1370
-TRANS(vsrai_b, gvec_vv_i, MO_8, tcg_gen_gvec_sari)
1371
-TRANS(vsrai_h, gvec_vv_i, MO_16, tcg_gen_gvec_sari)
1372
-TRANS(vsrai_w, gvec_vv_i, MO_32, tcg_gen_gvec_sari)
1373
-TRANS(vsrai_d, gvec_vv_i, MO_64, tcg_gen_gvec_sari)
1374
-
1375
-TRANS(vrotr_b, gvec_vvv, MO_8, tcg_gen_gvec_rotrv)
1376
-TRANS(vrotr_h, gvec_vvv, MO_16, tcg_gen_gvec_rotrv)
1377
-TRANS(vrotr_w, gvec_vvv, MO_32, tcg_gen_gvec_rotrv)
1378
-TRANS(vrotr_d, gvec_vvv, MO_64, tcg_gen_gvec_rotrv)
1379
-TRANS(vrotri_b, gvec_vv_i, MO_8, tcg_gen_gvec_rotri)
1380
-TRANS(vrotri_h, gvec_vv_i, MO_16, tcg_gen_gvec_rotri)
1381
-TRANS(vrotri_w, gvec_vv_i, MO_32, tcg_gen_gvec_rotri)
1382
-TRANS(vrotri_d, gvec_vv_i, MO_64, tcg_gen_gvec_rotri)
1383
-
1384
-TRANS(vsllwil_h_b, gen_vv_i, gen_helper_vsllwil_h_b)
1385
-TRANS(vsllwil_w_h, gen_vv_i, gen_helper_vsllwil_w_h)
1386
-TRANS(vsllwil_d_w, gen_vv_i, gen_helper_vsllwil_d_w)
1387
-TRANS(vextl_q_d, gen_vv, gen_helper_vextl_q_d)
1388
-TRANS(vsllwil_hu_bu, gen_vv_i, gen_helper_vsllwil_hu_bu)
1389
-TRANS(vsllwil_wu_hu, gen_vv_i, gen_helper_vsllwil_wu_hu)
1390
-TRANS(vsllwil_du_wu, gen_vv_i, gen_helper_vsllwil_du_wu)
1391
-TRANS(vextl_qu_du, gen_vv, gen_helper_vextl_qu_du)
1392
-
1393
-TRANS(vsrlr_b, gen_vvv, gen_helper_vsrlr_b)
1394
-TRANS(vsrlr_h, gen_vvv, gen_helper_vsrlr_h)
1395
-TRANS(vsrlr_w, gen_vvv, gen_helper_vsrlr_w)
1396
-TRANS(vsrlr_d, gen_vvv, gen_helper_vsrlr_d)
1397
-TRANS(vsrlri_b, gen_vv_i, gen_helper_vsrlri_b)
1398
-TRANS(vsrlri_h, gen_vv_i, gen_helper_vsrlri_h)
1399
-TRANS(vsrlri_w, gen_vv_i, gen_helper_vsrlri_w)
1400
-TRANS(vsrlri_d, gen_vv_i, gen_helper_vsrlri_d)
1401
-
1402
-TRANS(vsrar_b, gen_vvv, gen_helper_vsrar_b)
1403
-TRANS(vsrar_h, gen_vvv, gen_helper_vsrar_h)
1404
-TRANS(vsrar_w, gen_vvv, gen_helper_vsrar_w)
1405
-TRANS(vsrar_d, gen_vvv, gen_helper_vsrar_d)
1406
-TRANS(vsrari_b, gen_vv_i, gen_helper_vsrari_b)
1407
-TRANS(vsrari_h, gen_vv_i, gen_helper_vsrari_h)
1408
-TRANS(vsrari_w, gen_vv_i, gen_helper_vsrari_w)
1409
-TRANS(vsrari_d, gen_vv_i, gen_helper_vsrari_d)
1410
-
1411
-TRANS(vsrln_b_h, gen_vvv, gen_helper_vsrln_b_h)
1412
-TRANS(vsrln_h_w, gen_vvv, gen_helper_vsrln_h_w)
1413
-TRANS(vsrln_w_d, gen_vvv, gen_helper_vsrln_w_d)
1414
-TRANS(vsran_b_h, gen_vvv, gen_helper_vsran_b_h)
1415
-TRANS(vsran_h_w, gen_vvv, gen_helper_vsran_h_w)
1416
-TRANS(vsran_w_d, gen_vvv, gen_helper_vsran_w_d)
1417
-
1418
-TRANS(vsrlni_b_h, gen_vv_i, gen_helper_vsrlni_b_h)
1419
-TRANS(vsrlni_h_w, gen_vv_i, gen_helper_vsrlni_h_w)
1420
-TRANS(vsrlni_w_d, gen_vv_i, gen_helper_vsrlni_w_d)
1421
-TRANS(vsrlni_d_q, gen_vv_i, gen_helper_vsrlni_d_q)
1422
-TRANS(vsrani_b_h, gen_vv_i, gen_helper_vsrani_b_h)
1423
-TRANS(vsrani_h_w, gen_vv_i, gen_helper_vsrani_h_w)
1424
-TRANS(vsrani_w_d, gen_vv_i, gen_helper_vsrani_w_d)
1425
-TRANS(vsrani_d_q, gen_vv_i, gen_helper_vsrani_d_q)
1426
-
1427
-TRANS(vsrlrn_b_h, gen_vvv, gen_helper_vsrlrn_b_h)
1428
-TRANS(vsrlrn_h_w, gen_vvv, gen_helper_vsrlrn_h_w)
1429
-TRANS(vsrlrn_w_d, gen_vvv, gen_helper_vsrlrn_w_d)
1430
-TRANS(vsrarn_b_h, gen_vvv, gen_helper_vsrarn_b_h)
1431
-TRANS(vsrarn_h_w, gen_vvv, gen_helper_vsrarn_h_w)
1432
-TRANS(vsrarn_w_d, gen_vvv, gen_helper_vsrarn_w_d)
1433
-
1434
-TRANS(vsrlrni_b_h, gen_vv_i, gen_helper_vsrlrni_b_h)
1435
-TRANS(vsrlrni_h_w, gen_vv_i, gen_helper_vsrlrni_h_w)
1436
-TRANS(vsrlrni_w_d, gen_vv_i, gen_helper_vsrlrni_w_d)
1437
-TRANS(vsrlrni_d_q, gen_vv_i, gen_helper_vsrlrni_d_q)
1438
-TRANS(vsrarni_b_h, gen_vv_i, gen_helper_vsrarni_b_h)
1439
-TRANS(vsrarni_h_w, gen_vv_i, gen_helper_vsrarni_h_w)
1440
-TRANS(vsrarni_w_d, gen_vv_i, gen_helper_vsrarni_w_d)
1441
-TRANS(vsrarni_d_q, gen_vv_i, gen_helper_vsrarni_d_q)
1442
-
1443
-TRANS(vssrln_b_h, gen_vvv, gen_helper_vssrln_b_h)
1444
-TRANS(vssrln_h_w, gen_vvv, gen_helper_vssrln_h_w)
1445
-TRANS(vssrln_w_d, gen_vvv, gen_helper_vssrln_w_d)
1446
-TRANS(vssran_b_h, gen_vvv, gen_helper_vssran_b_h)
1447
-TRANS(vssran_h_w, gen_vvv, gen_helper_vssran_h_w)
1448
-TRANS(vssran_w_d, gen_vvv, gen_helper_vssran_w_d)
1449
-TRANS(vssrln_bu_h, gen_vvv, gen_helper_vssrln_bu_h)
1450
-TRANS(vssrln_hu_w, gen_vvv, gen_helper_vssrln_hu_w)
1451
-TRANS(vssrln_wu_d, gen_vvv, gen_helper_vssrln_wu_d)
1452
-TRANS(vssran_bu_h, gen_vvv, gen_helper_vssran_bu_h)
1453
-TRANS(vssran_hu_w, gen_vvv, gen_helper_vssran_hu_w)
1454
-TRANS(vssran_wu_d, gen_vvv, gen_helper_vssran_wu_d)
1455
-
1456
-TRANS(vssrlni_b_h, gen_vv_i, gen_helper_vssrlni_b_h)
1457
-TRANS(vssrlni_h_w, gen_vv_i, gen_helper_vssrlni_h_w)
1458
-TRANS(vssrlni_w_d, gen_vv_i, gen_helper_vssrlni_w_d)
1459
-TRANS(vssrlni_d_q, gen_vv_i, gen_helper_vssrlni_d_q)
1460
-TRANS(vssrani_b_h, gen_vv_i, gen_helper_vssrani_b_h)
1461
-TRANS(vssrani_h_w, gen_vv_i, gen_helper_vssrani_h_w)
1462
-TRANS(vssrani_w_d, gen_vv_i, gen_helper_vssrani_w_d)
1463
-TRANS(vssrani_d_q, gen_vv_i, gen_helper_vssrani_d_q)
1464
-TRANS(vssrlni_bu_h, gen_vv_i, gen_helper_vssrlni_bu_h)
1465
-TRANS(vssrlni_hu_w, gen_vv_i, gen_helper_vssrlni_hu_w)
1466
-TRANS(vssrlni_wu_d, gen_vv_i, gen_helper_vssrlni_wu_d)
1467
-TRANS(vssrlni_du_q, gen_vv_i, gen_helper_vssrlni_du_q)
1468
-TRANS(vssrani_bu_h, gen_vv_i, gen_helper_vssrani_bu_h)
1469
-TRANS(vssrani_hu_w, gen_vv_i, gen_helper_vssrani_hu_w)
1470
-TRANS(vssrani_wu_d, gen_vv_i, gen_helper_vssrani_wu_d)
1471
-TRANS(vssrani_du_q, gen_vv_i, gen_helper_vssrani_du_q)
1472
-
1473
-TRANS(vssrlrn_b_h, gen_vvv, gen_helper_vssrlrn_b_h)
1474
-TRANS(vssrlrn_h_w, gen_vvv, gen_helper_vssrlrn_h_w)
1475
-TRANS(vssrlrn_w_d, gen_vvv, gen_helper_vssrlrn_w_d)
1476
-TRANS(vssrarn_b_h, gen_vvv, gen_helper_vssrarn_b_h)
1477
-TRANS(vssrarn_h_w, gen_vvv, gen_helper_vssrarn_h_w)
1478
-TRANS(vssrarn_w_d, gen_vvv, gen_helper_vssrarn_w_d)
1479
-TRANS(vssrlrn_bu_h, gen_vvv, gen_helper_vssrlrn_bu_h)
1480
-TRANS(vssrlrn_hu_w, gen_vvv, gen_helper_vssrlrn_hu_w)
1481
-TRANS(vssrlrn_wu_d, gen_vvv, gen_helper_vssrlrn_wu_d)
1482
-TRANS(vssrarn_bu_h, gen_vvv, gen_helper_vssrarn_bu_h)
1483
-TRANS(vssrarn_hu_w, gen_vvv, gen_helper_vssrarn_hu_w)
1484
-TRANS(vssrarn_wu_d, gen_vvv, gen_helper_vssrarn_wu_d)
1485
-
1486
-TRANS(vssrlrni_b_h, gen_vv_i, gen_helper_vssrlrni_b_h)
1487
-TRANS(vssrlrni_h_w, gen_vv_i, gen_helper_vssrlrni_h_w)
1488
-TRANS(vssrlrni_w_d, gen_vv_i, gen_helper_vssrlrni_w_d)
1489
-TRANS(vssrlrni_d_q, gen_vv_i, gen_helper_vssrlrni_d_q)
1490
-TRANS(vssrarni_b_h, gen_vv_i, gen_helper_vssrarni_b_h)
1491
-TRANS(vssrarni_h_w, gen_vv_i, gen_helper_vssrarni_h_w)
1492
-TRANS(vssrarni_w_d, gen_vv_i, gen_helper_vssrarni_w_d)
1493
-TRANS(vssrarni_d_q, gen_vv_i, gen_helper_vssrarni_d_q)
1494
-TRANS(vssrlrni_bu_h, gen_vv_i, gen_helper_vssrlrni_bu_h)
1495
-TRANS(vssrlrni_hu_w, gen_vv_i, gen_helper_vssrlrni_hu_w)
1496
-TRANS(vssrlrni_wu_d, gen_vv_i, gen_helper_vssrlrni_wu_d)
1497
-TRANS(vssrlrni_du_q, gen_vv_i, gen_helper_vssrlrni_du_q)
1498
-TRANS(vssrarni_bu_h, gen_vv_i, gen_helper_vssrarni_bu_h)
1499
-TRANS(vssrarni_hu_w, gen_vv_i, gen_helper_vssrarni_hu_w)
1500
-TRANS(vssrarni_wu_d, gen_vv_i, gen_helper_vssrarni_wu_d)
1501
-TRANS(vssrarni_du_q, gen_vv_i, gen_helper_vssrarni_du_q)
1502
-
1503
-TRANS(vclo_b, gen_vv, gen_helper_vclo_b)
1504
-TRANS(vclo_h, gen_vv, gen_helper_vclo_h)
1505
-TRANS(vclo_w, gen_vv, gen_helper_vclo_w)
1506
-TRANS(vclo_d, gen_vv, gen_helper_vclo_d)
1507
-TRANS(vclz_b, gen_vv, gen_helper_vclz_b)
1508
-TRANS(vclz_h, gen_vv, gen_helper_vclz_h)
1509
-TRANS(vclz_w, gen_vv, gen_helper_vclz_w)
1510
-TRANS(vclz_d, gen_vv, gen_helper_vclz_d)
1511
-
1512
-TRANS(vpcnt_b, gen_vv, gen_helper_vpcnt_b)
1513
-TRANS(vpcnt_h, gen_vv, gen_helper_vpcnt_h)
1514
-TRANS(vpcnt_w, gen_vv, gen_helper_vpcnt_w)
1515
-TRANS(vpcnt_d, gen_vv, gen_helper_vpcnt_d)
1516
+TRANS(vnori_b, ALL, gvec_vv_i, MO_8, do_vnori_b)
1517
+
1518
+TRANS(vsll_b, ALL, gvec_vvv, MO_8, tcg_gen_gvec_shlv)
1519
+TRANS(vsll_h, ALL, gvec_vvv, MO_16, tcg_gen_gvec_shlv)
1520
+TRANS(vsll_w, ALL, gvec_vvv, MO_32, tcg_gen_gvec_shlv)
1521
+TRANS(vsll_d, ALL, gvec_vvv, MO_64, tcg_gen_gvec_shlv)
1522
+TRANS(vslli_b, ALL, gvec_vv_i, MO_8, tcg_gen_gvec_shli)
1523
+TRANS(vslli_h, ALL, gvec_vv_i, MO_16, tcg_gen_gvec_shli)
1524
+TRANS(vslli_w, ALL, gvec_vv_i, MO_32, tcg_gen_gvec_shli)
1525
+TRANS(vslli_d, ALL, gvec_vv_i, MO_64, tcg_gen_gvec_shli)
1526
+
1527
+TRANS(vsrl_b, ALL, gvec_vvv, MO_8, tcg_gen_gvec_shrv)
1528
+TRANS(vsrl_h, ALL, gvec_vvv, MO_16, tcg_gen_gvec_shrv)
1529
+TRANS(vsrl_w, ALL, gvec_vvv, MO_32, tcg_gen_gvec_shrv)
1530
+TRANS(vsrl_d, ALL, gvec_vvv, MO_64, tcg_gen_gvec_shrv)
1531
+TRANS(vsrli_b, ALL, gvec_vv_i, MO_8, tcg_gen_gvec_shri)
1532
+TRANS(vsrli_h, ALL, gvec_vv_i, MO_16, tcg_gen_gvec_shri)
1533
+TRANS(vsrli_w, ALL, gvec_vv_i, MO_32, tcg_gen_gvec_shri)
1534
+TRANS(vsrli_d, ALL, gvec_vv_i, MO_64, tcg_gen_gvec_shri)
1535
+
1536
+TRANS(vsra_b, ALL, gvec_vvv, MO_8, tcg_gen_gvec_sarv)
1537
+TRANS(vsra_h, ALL, gvec_vvv, MO_16, tcg_gen_gvec_sarv)
1538
+TRANS(vsra_w, ALL, gvec_vvv, MO_32, tcg_gen_gvec_sarv)
1539
+TRANS(vsra_d, ALL, gvec_vvv, MO_64, tcg_gen_gvec_sarv)
1540
+TRANS(vsrai_b, ALL, gvec_vv_i, MO_8, tcg_gen_gvec_sari)
1541
+TRANS(vsrai_h, ALL, gvec_vv_i, MO_16, tcg_gen_gvec_sari)
1542
+TRANS(vsrai_w, ALL, gvec_vv_i, MO_32, tcg_gen_gvec_sari)
1543
+TRANS(vsrai_d, ALL, gvec_vv_i, MO_64, tcg_gen_gvec_sari)
1544
+
1545
+TRANS(vrotr_b, ALL, gvec_vvv, MO_8, tcg_gen_gvec_rotrv)
1546
+TRANS(vrotr_h, ALL, gvec_vvv, MO_16, tcg_gen_gvec_rotrv)
1547
+TRANS(vrotr_w, ALL, gvec_vvv, MO_32, tcg_gen_gvec_rotrv)
1548
+TRANS(vrotr_d, ALL, gvec_vvv, MO_64, tcg_gen_gvec_rotrv)
1549
+TRANS(vrotri_b, ALL, gvec_vv_i, MO_8, tcg_gen_gvec_rotri)
1550
+TRANS(vrotri_h, ALL, gvec_vv_i, MO_16, tcg_gen_gvec_rotri)
1551
+TRANS(vrotri_w, ALL, gvec_vv_i, MO_32, tcg_gen_gvec_rotri)
1552
+TRANS(vrotri_d, ALL, gvec_vv_i, MO_64, tcg_gen_gvec_rotri)
1553
+
1554
+TRANS(vsllwil_h_b, ALL, gen_vv_i, gen_helper_vsllwil_h_b)
1555
+TRANS(vsllwil_w_h, ALL, gen_vv_i, gen_helper_vsllwil_w_h)
1556
+TRANS(vsllwil_d_w, ALL, gen_vv_i, gen_helper_vsllwil_d_w)
1557
+TRANS(vextl_q_d, ALL, gen_vv, gen_helper_vextl_q_d)
1558
+TRANS(vsllwil_hu_bu, ALL, gen_vv_i, gen_helper_vsllwil_hu_bu)
1559
+TRANS(vsllwil_wu_hu, ALL, gen_vv_i, gen_helper_vsllwil_wu_hu)
1560
+TRANS(vsllwil_du_wu, ALL, gen_vv_i, gen_helper_vsllwil_du_wu)
1561
+TRANS(vextl_qu_du, ALL, gen_vv, gen_helper_vextl_qu_du)
1562
+
1563
+TRANS(vsrlr_b, ALL, gen_vvv, gen_helper_vsrlr_b)
1564
+TRANS(vsrlr_h, ALL, gen_vvv, gen_helper_vsrlr_h)
1565
+TRANS(vsrlr_w, ALL, gen_vvv, gen_helper_vsrlr_w)
1566
+TRANS(vsrlr_d, ALL, gen_vvv, gen_helper_vsrlr_d)
1567
+TRANS(vsrlri_b, ALL, gen_vv_i, gen_helper_vsrlri_b)
1568
+TRANS(vsrlri_h, ALL, gen_vv_i, gen_helper_vsrlri_h)
1569
+TRANS(vsrlri_w, ALL, gen_vv_i, gen_helper_vsrlri_w)
1570
+TRANS(vsrlri_d, ALL, gen_vv_i, gen_helper_vsrlri_d)
1571
+
1572
+TRANS(vsrar_b, ALL, gen_vvv, gen_helper_vsrar_b)
1573
+TRANS(vsrar_h, ALL, gen_vvv, gen_helper_vsrar_h)
1574
+TRANS(vsrar_w, ALL, gen_vvv, gen_helper_vsrar_w)
1575
+TRANS(vsrar_d, ALL, gen_vvv, gen_helper_vsrar_d)
1576
+TRANS(vsrari_b, ALL, gen_vv_i, gen_helper_vsrari_b)
1577
+TRANS(vsrari_h, ALL, gen_vv_i, gen_helper_vsrari_h)
1578
+TRANS(vsrari_w, ALL, gen_vv_i, gen_helper_vsrari_w)
1579
+TRANS(vsrari_d, ALL, gen_vv_i, gen_helper_vsrari_d)
1580
+
1581
+TRANS(vsrln_b_h, ALL, gen_vvv, gen_helper_vsrln_b_h)
1582
+TRANS(vsrln_h_w, ALL, gen_vvv, gen_helper_vsrln_h_w)
1583
+TRANS(vsrln_w_d, ALL, gen_vvv, gen_helper_vsrln_w_d)
1584
+TRANS(vsran_b_h, ALL, gen_vvv, gen_helper_vsran_b_h)
1585
+TRANS(vsran_h_w, ALL, gen_vvv, gen_helper_vsran_h_w)
1586
+TRANS(vsran_w_d, ALL, gen_vvv, gen_helper_vsran_w_d)
1587
+
1588
+TRANS(vsrlni_b_h, ALL, gen_vv_i, gen_helper_vsrlni_b_h)
1589
+TRANS(vsrlni_h_w, ALL, gen_vv_i, gen_helper_vsrlni_h_w)
1590
+TRANS(vsrlni_w_d, ALL, gen_vv_i, gen_helper_vsrlni_w_d)
1591
+TRANS(vsrlni_d_q, ALL, gen_vv_i, gen_helper_vsrlni_d_q)
1592
+TRANS(vsrani_b_h, ALL, gen_vv_i, gen_helper_vsrani_b_h)
1593
+TRANS(vsrani_h_w, ALL, gen_vv_i, gen_helper_vsrani_h_w)
1594
+TRANS(vsrani_w_d, ALL, gen_vv_i, gen_helper_vsrani_w_d)
1595
+TRANS(vsrani_d_q, ALL, gen_vv_i, gen_helper_vsrani_d_q)
1596
+
1597
+TRANS(vsrlrn_b_h, ALL, gen_vvv, gen_helper_vsrlrn_b_h)
1598
+TRANS(vsrlrn_h_w, ALL, gen_vvv, gen_helper_vsrlrn_h_w)
1599
+TRANS(vsrlrn_w_d, ALL, gen_vvv, gen_helper_vsrlrn_w_d)
1600
+TRANS(vsrarn_b_h, ALL, gen_vvv, gen_helper_vsrarn_b_h)
1601
+TRANS(vsrarn_h_w, ALL, gen_vvv, gen_helper_vsrarn_h_w)
1602
+TRANS(vsrarn_w_d, ALL, gen_vvv, gen_helper_vsrarn_w_d)
1603
+
1604
+TRANS(vsrlrni_b_h, ALL, gen_vv_i, gen_helper_vsrlrni_b_h)
1605
+TRANS(vsrlrni_h_w, ALL, gen_vv_i, gen_helper_vsrlrni_h_w)
1606
+TRANS(vsrlrni_w_d, ALL, gen_vv_i, gen_helper_vsrlrni_w_d)
1607
+TRANS(vsrlrni_d_q, ALL, gen_vv_i, gen_helper_vsrlrni_d_q)
1608
+TRANS(vsrarni_b_h, ALL, gen_vv_i, gen_helper_vsrarni_b_h)
1609
+TRANS(vsrarni_h_w, ALL, gen_vv_i, gen_helper_vsrarni_h_w)
1610
+TRANS(vsrarni_w_d, ALL, gen_vv_i, gen_helper_vsrarni_w_d)
1611
+TRANS(vsrarni_d_q, ALL, gen_vv_i, gen_helper_vsrarni_d_q)
1612
+
1613
+TRANS(vssrln_b_h, ALL, gen_vvv, gen_helper_vssrln_b_h)
1614
+TRANS(vssrln_h_w, ALL, gen_vvv, gen_helper_vssrln_h_w)
1615
+TRANS(vssrln_w_d, ALL, gen_vvv, gen_helper_vssrln_w_d)
1616
+TRANS(vssran_b_h, ALL, gen_vvv, gen_helper_vssran_b_h)
1617
+TRANS(vssran_h_w, ALL, gen_vvv, gen_helper_vssran_h_w)
1618
+TRANS(vssran_w_d, ALL, gen_vvv, gen_helper_vssran_w_d)
1619
+TRANS(vssrln_bu_h, ALL, gen_vvv, gen_helper_vssrln_bu_h)
1620
+TRANS(vssrln_hu_w, ALL, gen_vvv, gen_helper_vssrln_hu_w)
1621
+TRANS(vssrln_wu_d, ALL, gen_vvv, gen_helper_vssrln_wu_d)
1622
+TRANS(vssran_bu_h, ALL, gen_vvv, gen_helper_vssran_bu_h)
1623
+TRANS(vssran_hu_w, ALL, gen_vvv, gen_helper_vssran_hu_w)
1624
+TRANS(vssran_wu_d, ALL, gen_vvv, gen_helper_vssran_wu_d)
1625
+
1626
+TRANS(vssrlni_b_h, ALL, gen_vv_i, gen_helper_vssrlni_b_h)
1627
+TRANS(vssrlni_h_w, ALL, gen_vv_i, gen_helper_vssrlni_h_w)
1628
+TRANS(vssrlni_w_d, ALL, gen_vv_i, gen_helper_vssrlni_w_d)
1629
+TRANS(vssrlni_d_q, ALL, gen_vv_i, gen_helper_vssrlni_d_q)
1630
+TRANS(vssrani_b_h, ALL, gen_vv_i, gen_helper_vssrani_b_h)
1631
+TRANS(vssrani_h_w, ALL, gen_vv_i, gen_helper_vssrani_h_w)
1632
+TRANS(vssrani_w_d, ALL, gen_vv_i, gen_helper_vssrani_w_d)
1633
+TRANS(vssrani_d_q, ALL, gen_vv_i, gen_helper_vssrani_d_q)
1634
+TRANS(vssrlni_bu_h, ALL, gen_vv_i, gen_helper_vssrlni_bu_h)
1635
+TRANS(vssrlni_hu_w, ALL, gen_vv_i, gen_helper_vssrlni_hu_w)
1636
+TRANS(vssrlni_wu_d, ALL, gen_vv_i, gen_helper_vssrlni_wu_d)
1637
+TRANS(vssrlni_du_q, ALL, gen_vv_i, gen_helper_vssrlni_du_q)
1638
+TRANS(vssrani_bu_h, ALL, gen_vv_i, gen_helper_vssrani_bu_h)
1639
+TRANS(vssrani_hu_w, ALL, gen_vv_i, gen_helper_vssrani_hu_w)
1640
+TRANS(vssrani_wu_d, ALL, gen_vv_i, gen_helper_vssrani_wu_d)
1641
+TRANS(vssrani_du_q, ALL, gen_vv_i, gen_helper_vssrani_du_q)
1642
+
1643
+TRANS(vssrlrn_b_h, ALL, gen_vvv, gen_helper_vssrlrn_b_h)
1644
+TRANS(vssrlrn_h_w, ALL, gen_vvv, gen_helper_vssrlrn_h_w)
1645
+TRANS(vssrlrn_w_d, ALL, gen_vvv, gen_helper_vssrlrn_w_d)
1646
+TRANS(vssrarn_b_h, ALL, gen_vvv, gen_helper_vssrarn_b_h)
1647
+TRANS(vssrarn_h_w, ALL, gen_vvv, gen_helper_vssrarn_h_w)
1648
+TRANS(vssrarn_w_d, ALL, gen_vvv, gen_helper_vssrarn_w_d)
1649
+TRANS(vssrlrn_bu_h, ALL, gen_vvv, gen_helper_vssrlrn_bu_h)
1650
+TRANS(vssrlrn_hu_w, ALL, gen_vvv, gen_helper_vssrlrn_hu_w)
1651
+TRANS(vssrlrn_wu_d, ALL, gen_vvv, gen_helper_vssrlrn_wu_d)
1652
+TRANS(vssrarn_bu_h, ALL, gen_vvv, gen_helper_vssrarn_bu_h)
1653
+TRANS(vssrarn_hu_w, ALL, gen_vvv, gen_helper_vssrarn_hu_w)
1654
+TRANS(vssrarn_wu_d, ALL, gen_vvv, gen_helper_vssrarn_wu_d)
1655
+
1656
+TRANS(vssrlrni_b_h, ALL, gen_vv_i, gen_helper_vssrlrni_b_h)
1657
+TRANS(vssrlrni_h_w, ALL, gen_vv_i, gen_helper_vssrlrni_h_w)
1658
+TRANS(vssrlrni_w_d, ALL, gen_vv_i, gen_helper_vssrlrni_w_d)
1659
+TRANS(vssrlrni_d_q, ALL, gen_vv_i, gen_helper_vssrlrni_d_q)
1660
+TRANS(vssrarni_b_h, ALL, gen_vv_i, gen_helper_vssrarni_b_h)
1661
+TRANS(vssrarni_h_w, ALL, gen_vv_i, gen_helper_vssrarni_h_w)
1662
+TRANS(vssrarni_w_d, ALL, gen_vv_i, gen_helper_vssrarni_w_d)
1663
+TRANS(vssrarni_d_q, ALL, gen_vv_i, gen_helper_vssrarni_d_q)
1664
+TRANS(vssrlrni_bu_h, ALL, gen_vv_i, gen_helper_vssrlrni_bu_h)
1665
+TRANS(vssrlrni_hu_w, ALL, gen_vv_i, gen_helper_vssrlrni_hu_w)
1666
+TRANS(vssrlrni_wu_d, ALL, gen_vv_i, gen_helper_vssrlrni_wu_d)
1667
+TRANS(vssrlrni_du_q, ALL, gen_vv_i, gen_helper_vssrlrni_du_q)
1668
+TRANS(vssrarni_bu_h, ALL, gen_vv_i, gen_helper_vssrarni_bu_h)
1669
+TRANS(vssrarni_hu_w, ALL, gen_vv_i, gen_helper_vssrarni_hu_w)
1670
+TRANS(vssrarni_wu_d, ALL, gen_vv_i, gen_helper_vssrarni_wu_d)
1671
+TRANS(vssrarni_du_q, ALL, gen_vv_i, gen_helper_vssrarni_du_q)
1672
+
1673
+TRANS(vclo_b, ALL, gen_vv, gen_helper_vclo_b)
1674
+TRANS(vclo_h, ALL, gen_vv, gen_helper_vclo_h)
1675
+TRANS(vclo_w, ALL, gen_vv, gen_helper_vclo_w)
1676
+TRANS(vclo_d, ALL, gen_vv, gen_helper_vclo_d)
1677
+TRANS(vclz_b, ALL, gen_vv, gen_helper_vclz_b)
1678
+TRANS(vclz_h, ALL, gen_vv, gen_helper_vclz_h)
1679
+TRANS(vclz_w, ALL, gen_vv, gen_helper_vclz_w)
1680
+TRANS(vclz_d, ALL, gen_vv, gen_helper_vclz_d)
1681
+
1682
+TRANS(vpcnt_b, ALL, gen_vv, gen_helper_vpcnt_b)
1683
+TRANS(vpcnt_h, ALL, gen_vv, gen_helper_vpcnt_h)
1684
+TRANS(vpcnt_w, ALL, gen_vv, gen_helper_vpcnt_w)
1685
+TRANS(vpcnt_d, ALL, gen_vv, gen_helper_vpcnt_d)
1686
1687
static void do_vbit(unsigned vece, TCGv_vec t, TCGv_vec a, TCGv_vec b,
1688
void (*func)(unsigned, TCGv_vec, TCGv_vec, TCGv_vec))
1689
@@ -XXX,XX +XXX,XX @@ static void do_vbitclr(unsigned vece, uint32_t vd_ofs, uint32_t vj_ofs,
1690
tcg_gen_gvec_3(vd_ofs, vj_ofs, vk_ofs, oprsz, maxsz, &op[vece]);
1691
}
1692
1693
-TRANS(vbitclr_b, gvec_vvv, MO_8, do_vbitclr)
1694
-TRANS(vbitclr_h, gvec_vvv, MO_16, do_vbitclr)
1695
-TRANS(vbitclr_w, gvec_vvv, MO_32, do_vbitclr)
1696
-TRANS(vbitclr_d, gvec_vvv, MO_64, do_vbitclr)
1697
+TRANS(vbitclr_b, ALL, gvec_vvv, MO_8, do_vbitclr)
1698
+TRANS(vbitclr_h, ALL, gvec_vvv, MO_16, do_vbitclr)
1699
+TRANS(vbitclr_w, ALL, gvec_vvv, MO_32, do_vbitclr)
1700
+TRANS(vbitclr_d, ALL, gvec_vvv, MO_64, do_vbitclr)
1701
1702
static void do_vbiti(unsigned vece, TCGv_vec t, TCGv_vec a, int64_t imm,
1703
void (*func)(unsigned, TCGv_vec, TCGv_vec, TCGv_vec))
1704
@@ -XXX,XX +XXX,XX @@ static void do_vbitclri(unsigned vece, uint32_t vd_ofs, uint32_t vj_ofs,
1705
tcg_gen_gvec_2i(vd_ofs, vj_ofs, oprsz, maxsz, imm, &op[vece]);
1706
}
1707
1708
-TRANS(vbitclri_b, gvec_vv_i, MO_8, do_vbitclri)
1709
-TRANS(vbitclri_h, gvec_vv_i, MO_16, do_vbitclri)
1710
-TRANS(vbitclri_w, gvec_vv_i, MO_32, do_vbitclri)
1711
-TRANS(vbitclri_d, gvec_vv_i, MO_64, do_vbitclri)
1712
+TRANS(vbitclri_b, ALL, gvec_vv_i, MO_8, do_vbitclri)
1713
+TRANS(vbitclri_h, ALL, gvec_vv_i, MO_16, do_vbitclri)
1714
+TRANS(vbitclri_w, ALL, gvec_vv_i, MO_32, do_vbitclri)
1715
+TRANS(vbitclri_d, ALL, gvec_vv_i, MO_64, do_vbitclri)
1716
1717
static void do_vbitset(unsigned vece, uint32_t vd_ofs, uint32_t vj_ofs,
1718
uint32_t vk_ofs, uint32_t oprsz, uint32_t maxsz)
1719
@@ -XXX,XX +XXX,XX @@ static void do_vbitset(unsigned vece, uint32_t vd_ofs, uint32_t vj_ofs,
1720
tcg_gen_gvec_3(vd_ofs, vj_ofs, vk_ofs, oprsz, maxsz, &op[vece]);
1721
}
1722
1723
-TRANS(vbitset_b, gvec_vvv, MO_8, do_vbitset)
1724
-TRANS(vbitset_h, gvec_vvv, MO_16, do_vbitset)
1725
-TRANS(vbitset_w, gvec_vvv, MO_32, do_vbitset)
1726
-TRANS(vbitset_d, gvec_vvv, MO_64, do_vbitset)
1727
+TRANS(vbitset_b, ALL, gvec_vvv, MO_8, do_vbitset)
1728
+TRANS(vbitset_h, ALL, gvec_vvv, MO_16, do_vbitset)
1729
+TRANS(vbitset_w, ALL, gvec_vvv, MO_32, do_vbitset)
1730
+TRANS(vbitset_d, ALL, gvec_vvv, MO_64, do_vbitset)
1731
1732
static void do_vbitseti(unsigned vece, uint32_t vd_ofs, uint32_t vj_ofs,
1733
int64_t imm, uint32_t oprsz, uint32_t maxsz)
1734
@@ -XXX,XX +XXX,XX @@ static void do_vbitseti(unsigned vece, uint32_t vd_ofs, uint32_t vj_ofs,
1735
tcg_gen_gvec_2i(vd_ofs, vj_ofs, oprsz, maxsz, imm, &op[vece]);
1736
}
1737
1738
-TRANS(vbitseti_b, gvec_vv_i, MO_8, do_vbitseti)
1739
-TRANS(vbitseti_h, gvec_vv_i, MO_16, do_vbitseti)
1740
-TRANS(vbitseti_w, gvec_vv_i, MO_32, do_vbitseti)
1741
-TRANS(vbitseti_d, gvec_vv_i, MO_64, do_vbitseti)
1742
+TRANS(vbitseti_b, ALL, gvec_vv_i, MO_8, do_vbitseti)
1743
+TRANS(vbitseti_h, ALL, gvec_vv_i, MO_16, do_vbitseti)
1744
+TRANS(vbitseti_w, ALL, gvec_vv_i, MO_32, do_vbitseti)
1745
+TRANS(vbitseti_d, ALL, gvec_vv_i, MO_64, do_vbitseti)
1746
1747
static void do_vbitrev(unsigned vece, uint32_t vd_ofs, uint32_t vj_ofs,
1748
uint32_t vk_ofs, uint32_t oprsz, uint32_t maxsz)
1749
@@ -XXX,XX +XXX,XX @@ static void do_vbitrev(unsigned vece, uint32_t vd_ofs, uint32_t vj_ofs,
1750
tcg_gen_gvec_3(vd_ofs, vj_ofs, vk_ofs, oprsz, maxsz, &op[vece]);
1751
}
1752
1753
-TRANS(vbitrev_b, gvec_vvv, MO_8, do_vbitrev)
1754
-TRANS(vbitrev_h, gvec_vvv, MO_16, do_vbitrev)
1755
-TRANS(vbitrev_w, gvec_vvv, MO_32, do_vbitrev)
1756
-TRANS(vbitrev_d, gvec_vvv, MO_64, do_vbitrev)
1757
+TRANS(vbitrev_b, ALL, gvec_vvv, MO_8, do_vbitrev)
1758
+TRANS(vbitrev_h, ALL, gvec_vvv, MO_16, do_vbitrev)
1759
+TRANS(vbitrev_w, ALL, gvec_vvv, MO_32, do_vbitrev)
1760
+TRANS(vbitrev_d, ALL, gvec_vvv, MO_64, do_vbitrev)
1761
1762
static void do_vbitrevi(unsigned vece, uint32_t vd_ofs, uint32_t vj_ofs,
1763
int64_t imm, uint32_t oprsz, uint32_t maxsz)
1764
@@ -XXX,XX +XXX,XX @@ static void do_vbitrevi(unsigned vece, uint32_t vd_ofs, uint32_t vj_ofs,
1765
tcg_gen_gvec_2i(vd_ofs, vj_ofs, oprsz, maxsz, imm, &op[vece]);
1766
}
1767
1768
-TRANS(vbitrevi_b, gvec_vv_i, MO_8, do_vbitrevi)
1769
-TRANS(vbitrevi_h, gvec_vv_i, MO_16, do_vbitrevi)
1770
-TRANS(vbitrevi_w, gvec_vv_i, MO_32, do_vbitrevi)
1771
-TRANS(vbitrevi_d, gvec_vv_i, MO_64, do_vbitrevi)
1772
-
1773
-TRANS(vfrstp_b, gen_vvv, gen_helper_vfrstp_b)
1774
-TRANS(vfrstp_h, gen_vvv, gen_helper_vfrstp_h)
1775
-TRANS(vfrstpi_b, gen_vv_i, gen_helper_vfrstpi_b)
1776
-TRANS(vfrstpi_h, gen_vv_i, gen_helper_vfrstpi_h)
1777
-
1778
-TRANS(vfadd_s, gen_vvv, gen_helper_vfadd_s)
1779
-TRANS(vfadd_d, gen_vvv, gen_helper_vfadd_d)
1780
-TRANS(vfsub_s, gen_vvv, gen_helper_vfsub_s)
1781
-TRANS(vfsub_d, gen_vvv, gen_helper_vfsub_d)
1782
-TRANS(vfmul_s, gen_vvv, gen_helper_vfmul_s)
1783
-TRANS(vfmul_d, gen_vvv, gen_helper_vfmul_d)
1784
-TRANS(vfdiv_s, gen_vvv, gen_helper_vfdiv_s)
1785
-TRANS(vfdiv_d, gen_vvv, gen_helper_vfdiv_d)
1786
-
1787
-TRANS(vfmadd_s, gen_vvvv, gen_helper_vfmadd_s)
1788
-TRANS(vfmadd_d, gen_vvvv, gen_helper_vfmadd_d)
1789
-TRANS(vfmsub_s, gen_vvvv, gen_helper_vfmsub_s)
1790
-TRANS(vfmsub_d, gen_vvvv, gen_helper_vfmsub_d)
1791
-TRANS(vfnmadd_s, gen_vvvv, gen_helper_vfnmadd_s)
1792
-TRANS(vfnmadd_d, gen_vvvv, gen_helper_vfnmadd_d)
1793
-TRANS(vfnmsub_s, gen_vvvv, gen_helper_vfnmsub_s)
1794
-TRANS(vfnmsub_d, gen_vvvv, gen_helper_vfnmsub_d)
1795
-
1796
-TRANS(vfmax_s, gen_vvv, gen_helper_vfmax_s)
1797
-TRANS(vfmax_d, gen_vvv, gen_helper_vfmax_d)
1798
-TRANS(vfmin_s, gen_vvv, gen_helper_vfmin_s)
1799
-TRANS(vfmin_d, gen_vvv, gen_helper_vfmin_d)
1800
-
1801
-TRANS(vfmaxa_s, gen_vvv, gen_helper_vfmaxa_s)
1802
-TRANS(vfmaxa_d, gen_vvv, gen_helper_vfmaxa_d)
1803
-TRANS(vfmina_s, gen_vvv, gen_helper_vfmina_s)
1804
-TRANS(vfmina_d, gen_vvv, gen_helper_vfmina_d)
1805
-
1806
-TRANS(vflogb_s, gen_vv, gen_helper_vflogb_s)
1807
-TRANS(vflogb_d, gen_vv, gen_helper_vflogb_d)
1808
-
1809
-TRANS(vfclass_s, gen_vv, gen_helper_vfclass_s)
1810
-TRANS(vfclass_d, gen_vv, gen_helper_vfclass_d)
1811
-
1812
-TRANS(vfsqrt_s, gen_vv, gen_helper_vfsqrt_s)
1813
-TRANS(vfsqrt_d, gen_vv, gen_helper_vfsqrt_d)
1814
-TRANS(vfrecip_s, gen_vv, gen_helper_vfrecip_s)
1815
-TRANS(vfrecip_d, gen_vv, gen_helper_vfrecip_d)
1816
-TRANS(vfrsqrt_s, gen_vv, gen_helper_vfrsqrt_s)
1817
-TRANS(vfrsqrt_d, gen_vv, gen_helper_vfrsqrt_d)
1818
-
1819
-TRANS(vfcvtl_s_h, gen_vv, gen_helper_vfcvtl_s_h)
1820
-TRANS(vfcvth_s_h, gen_vv, gen_helper_vfcvth_s_h)
1821
-TRANS(vfcvtl_d_s, gen_vv, gen_helper_vfcvtl_d_s)
1822
-TRANS(vfcvth_d_s, gen_vv, gen_helper_vfcvth_d_s)
1823
-TRANS(vfcvt_h_s, gen_vvv, gen_helper_vfcvt_h_s)
1824
-TRANS(vfcvt_s_d, gen_vvv, gen_helper_vfcvt_s_d)
1825
-
1826
-TRANS(vfrintrne_s, gen_vv, gen_helper_vfrintrne_s)
1827
-TRANS(vfrintrne_d, gen_vv, gen_helper_vfrintrne_d)
1828
-TRANS(vfrintrz_s, gen_vv, gen_helper_vfrintrz_s)
1829
-TRANS(vfrintrz_d, gen_vv, gen_helper_vfrintrz_d)
1830
-TRANS(vfrintrp_s, gen_vv, gen_helper_vfrintrp_s)
1831
-TRANS(vfrintrp_d, gen_vv, gen_helper_vfrintrp_d)
1832
-TRANS(vfrintrm_s, gen_vv, gen_helper_vfrintrm_s)
1833
-TRANS(vfrintrm_d, gen_vv, gen_helper_vfrintrm_d)
1834
-TRANS(vfrint_s, gen_vv, gen_helper_vfrint_s)
1835
-TRANS(vfrint_d, gen_vv, gen_helper_vfrint_d)
1836
-
1837
-TRANS(vftintrne_w_s, gen_vv, gen_helper_vftintrne_w_s)
1838
-TRANS(vftintrne_l_d, gen_vv, gen_helper_vftintrne_l_d)
1839
-TRANS(vftintrz_w_s, gen_vv, gen_helper_vftintrz_w_s)
1840
-TRANS(vftintrz_l_d, gen_vv, gen_helper_vftintrz_l_d)
1841
-TRANS(vftintrp_w_s, gen_vv, gen_helper_vftintrp_w_s)
1842
-TRANS(vftintrp_l_d, gen_vv, gen_helper_vftintrp_l_d)
1843
-TRANS(vftintrm_w_s, gen_vv, gen_helper_vftintrm_w_s)
1844
-TRANS(vftintrm_l_d, gen_vv, gen_helper_vftintrm_l_d)
1845
-TRANS(vftint_w_s, gen_vv, gen_helper_vftint_w_s)
1846
-TRANS(vftint_l_d, gen_vv, gen_helper_vftint_l_d)
1847
-TRANS(vftintrz_wu_s, gen_vv, gen_helper_vftintrz_wu_s)
1848
-TRANS(vftintrz_lu_d, gen_vv, gen_helper_vftintrz_lu_d)
1849
-TRANS(vftint_wu_s, gen_vv, gen_helper_vftint_wu_s)
1850
-TRANS(vftint_lu_d, gen_vv, gen_helper_vftint_lu_d)
1851
-TRANS(vftintrne_w_d, gen_vvv, gen_helper_vftintrne_w_d)
1852
-TRANS(vftintrz_w_d, gen_vvv, gen_helper_vftintrz_w_d)
1853
-TRANS(vftintrp_w_d, gen_vvv, gen_helper_vftintrp_w_d)
1854
-TRANS(vftintrm_w_d, gen_vvv, gen_helper_vftintrm_w_d)
1855
-TRANS(vftint_w_d, gen_vvv, gen_helper_vftint_w_d)
1856
-TRANS(vftintrnel_l_s, gen_vv, gen_helper_vftintrnel_l_s)
1857
-TRANS(vftintrneh_l_s, gen_vv, gen_helper_vftintrneh_l_s)
1858
-TRANS(vftintrzl_l_s, gen_vv, gen_helper_vftintrzl_l_s)
1859
-TRANS(vftintrzh_l_s, gen_vv, gen_helper_vftintrzh_l_s)
1860
-TRANS(vftintrpl_l_s, gen_vv, gen_helper_vftintrpl_l_s)
1861
-TRANS(vftintrph_l_s, gen_vv, gen_helper_vftintrph_l_s)
1862
-TRANS(vftintrml_l_s, gen_vv, gen_helper_vftintrml_l_s)
1863
-TRANS(vftintrmh_l_s, gen_vv, gen_helper_vftintrmh_l_s)
1864
-TRANS(vftintl_l_s, gen_vv, gen_helper_vftintl_l_s)
1865
-TRANS(vftinth_l_s, gen_vv, gen_helper_vftinth_l_s)
1866
-
1867
-TRANS(vffint_s_w, gen_vv, gen_helper_vffint_s_w)
1868
-TRANS(vffint_d_l, gen_vv, gen_helper_vffint_d_l)
1869
-TRANS(vffint_s_wu, gen_vv, gen_helper_vffint_s_wu)
1870
-TRANS(vffint_d_lu, gen_vv, gen_helper_vffint_d_lu)
1871
-TRANS(vffintl_d_w, gen_vv, gen_helper_vffintl_d_w)
1872
-TRANS(vffinth_d_w, gen_vv, gen_helper_vffinth_d_w)
1873
-TRANS(vffint_s_l, gen_vvv, gen_helper_vffint_s_l)
1874
+TRANS(vbitrevi_b, ALL, gvec_vv_i, MO_8, do_vbitrevi)
1875
+TRANS(vbitrevi_h, ALL, gvec_vv_i, MO_16, do_vbitrevi)
1876
+TRANS(vbitrevi_w, ALL, gvec_vv_i, MO_32, do_vbitrevi)
1877
+TRANS(vbitrevi_d, ALL, gvec_vv_i, MO_64, do_vbitrevi)
1878
+
1879
+TRANS(vfrstp_b, ALL, gen_vvv, gen_helper_vfrstp_b)
1880
+TRANS(vfrstp_h, ALL, gen_vvv, gen_helper_vfrstp_h)
1881
+TRANS(vfrstpi_b, ALL, gen_vv_i, gen_helper_vfrstpi_b)
1882
+TRANS(vfrstpi_h, ALL, gen_vv_i, gen_helper_vfrstpi_h)
1883
+
1884
+TRANS(vfadd_s, ALL, gen_vvv, gen_helper_vfadd_s)
1885
+TRANS(vfadd_d, ALL, gen_vvv, gen_helper_vfadd_d)
1886
+TRANS(vfsub_s, ALL, gen_vvv, gen_helper_vfsub_s)
1887
+TRANS(vfsub_d, ALL, gen_vvv, gen_helper_vfsub_d)
1888
+TRANS(vfmul_s, ALL, gen_vvv, gen_helper_vfmul_s)
1889
+TRANS(vfmul_d, ALL, gen_vvv, gen_helper_vfmul_d)
1890
+TRANS(vfdiv_s, ALL, gen_vvv, gen_helper_vfdiv_s)
1891
+TRANS(vfdiv_d, ALL, gen_vvv, gen_helper_vfdiv_d)
1892
+
1893
+TRANS(vfmadd_s, ALL, gen_vvvv, gen_helper_vfmadd_s)
1894
+TRANS(vfmadd_d, ALL, gen_vvvv, gen_helper_vfmadd_d)
1895
+TRANS(vfmsub_s, ALL, gen_vvvv, gen_helper_vfmsub_s)
1896
+TRANS(vfmsub_d, ALL, gen_vvvv, gen_helper_vfmsub_d)
1897
+TRANS(vfnmadd_s, ALL, gen_vvvv, gen_helper_vfnmadd_s)
1898
+TRANS(vfnmadd_d, ALL, gen_vvvv, gen_helper_vfnmadd_d)
1899
+TRANS(vfnmsub_s, ALL, gen_vvvv, gen_helper_vfnmsub_s)
1900
+TRANS(vfnmsub_d, ALL, gen_vvvv, gen_helper_vfnmsub_d)
1901
+
1902
+TRANS(vfmax_s, ALL, gen_vvv, gen_helper_vfmax_s)
1903
+TRANS(vfmax_d, ALL, gen_vvv, gen_helper_vfmax_d)
1904
+TRANS(vfmin_s, ALL, gen_vvv, gen_helper_vfmin_s)
1905
+TRANS(vfmin_d, ALL, gen_vvv, gen_helper_vfmin_d)
1906
+
1907
+TRANS(vfmaxa_s, ALL, gen_vvv, gen_helper_vfmaxa_s)
1908
+TRANS(vfmaxa_d, ALL, gen_vvv, gen_helper_vfmaxa_d)
1909
+TRANS(vfmina_s, ALL, gen_vvv, gen_helper_vfmina_s)
1910
+TRANS(vfmina_d, ALL, gen_vvv, gen_helper_vfmina_d)
1911
+
1912
+TRANS(vflogb_s, ALL, gen_vv, gen_helper_vflogb_s)
1913
+TRANS(vflogb_d, ALL, gen_vv, gen_helper_vflogb_d)
1914
+
1915
+TRANS(vfclass_s, ALL, gen_vv, gen_helper_vfclass_s)
1916
+TRANS(vfclass_d, ALL, gen_vv, gen_helper_vfclass_d)
1917
+
1918
+TRANS(vfsqrt_s, ALL, gen_vv, gen_helper_vfsqrt_s)
1919
+TRANS(vfsqrt_d, ALL, gen_vv, gen_helper_vfsqrt_d)
1920
+TRANS(vfrecip_s, ALL, gen_vv, gen_helper_vfrecip_s)
1921
+TRANS(vfrecip_d, ALL, gen_vv, gen_helper_vfrecip_d)
1922
+TRANS(vfrsqrt_s, ALL, gen_vv, gen_helper_vfrsqrt_s)
1923
+TRANS(vfrsqrt_d, ALL, gen_vv, gen_helper_vfrsqrt_d)
1924
+
1925
+TRANS(vfcvtl_s_h, ALL, gen_vv, gen_helper_vfcvtl_s_h)
1926
+TRANS(vfcvth_s_h, ALL, gen_vv, gen_helper_vfcvth_s_h)
1927
+TRANS(vfcvtl_d_s, ALL, gen_vv, gen_helper_vfcvtl_d_s)
1928
+TRANS(vfcvth_d_s, ALL, gen_vv, gen_helper_vfcvth_d_s)
1929
+TRANS(vfcvt_h_s, ALL, gen_vvv, gen_helper_vfcvt_h_s)
1930
+TRANS(vfcvt_s_d, ALL, gen_vvv, gen_helper_vfcvt_s_d)
1931
+
1932
+TRANS(vfrintrne_s, ALL, gen_vv, gen_helper_vfrintrne_s)
1933
+TRANS(vfrintrne_d, ALL, gen_vv, gen_helper_vfrintrne_d)
1934
+TRANS(vfrintrz_s, ALL, gen_vv, gen_helper_vfrintrz_s)
1935
+TRANS(vfrintrz_d, ALL, gen_vv, gen_helper_vfrintrz_d)
1936
+TRANS(vfrintrp_s, ALL, gen_vv, gen_helper_vfrintrp_s)
1937
+TRANS(vfrintrp_d, ALL, gen_vv, gen_helper_vfrintrp_d)
1938
+TRANS(vfrintrm_s, ALL, gen_vv, gen_helper_vfrintrm_s)
1939
+TRANS(vfrintrm_d, ALL, gen_vv, gen_helper_vfrintrm_d)
1940
+TRANS(vfrint_s, ALL, gen_vv, gen_helper_vfrint_s)
1941
+TRANS(vfrint_d, ALL, gen_vv, gen_helper_vfrint_d)
1942
+
1943
+TRANS(vftintrne_w_s, ALL, gen_vv, gen_helper_vftintrne_w_s)
1944
+TRANS(vftintrne_l_d, ALL, gen_vv, gen_helper_vftintrne_l_d)
1945
+TRANS(vftintrz_w_s, ALL, gen_vv, gen_helper_vftintrz_w_s)
1946
+TRANS(vftintrz_l_d, ALL, gen_vv, gen_helper_vftintrz_l_d)
1947
+TRANS(vftintrp_w_s, ALL, gen_vv, gen_helper_vftintrp_w_s)
1948
+TRANS(vftintrp_l_d, ALL, gen_vv, gen_helper_vftintrp_l_d)
1949
+TRANS(vftintrm_w_s, ALL, gen_vv, gen_helper_vftintrm_w_s)
1950
+TRANS(vftintrm_l_d, ALL, gen_vv, gen_helper_vftintrm_l_d)
1951
+TRANS(vftint_w_s, ALL, gen_vv, gen_helper_vftint_w_s)
1952
+TRANS(vftint_l_d, ALL, gen_vv, gen_helper_vftint_l_d)
1953
+TRANS(vftintrz_wu_s, ALL, gen_vv, gen_helper_vftintrz_wu_s)
1954
+TRANS(vftintrz_lu_d, ALL, gen_vv, gen_helper_vftintrz_lu_d)
1955
+TRANS(vftint_wu_s, ALL, gen_vv, gen_helper_vftint_wu_s)
1956
+TRANS(vftint_lu_d, ALL, gen_vv, gen_helper_vftint_lu_d)
1957
+TRANS(vftintrne_w_d, ALL, gen_vvv, gen_helper_vftintrne_w_d)
1958
+TRANS(vftintrz_w_d, ALL, gen_vvv, gen_helper_vftintrz_w_d)
1959
+TRANS(vftintrp_w_d, ALL, gen_vvv, gen_helper_vftintrp_w_d)
1960
+TRANS(vftintrm_w_d, ALL, gen_vvv, gen_helper_vftintrm_w_d)
1961
+TRANS(vftint_w_d, ALL, gen_vvv, gen_helper_vftint_w_d)
1962
+TRANS(vftintrnel_l_s, ALL, gen_vv, gen_helper_vftintrnel_l_s)
1963
+TRANS(vftintrneh_l_s, ALL, gen_vv, gen_helper_vftintrneh_l_s)
1964
+TRANS(vftintrzl_l_s, ALL, gen_vv, gen_helper_vftintrzl_l_s)
1965
+TRANS(vftintrzh_l_s, ALL, gen_vv, gen_helper_vftintrzh_l_s)
1966
+TRANS(vftintrpl_l_s, ALL, gen_vv, gen_helper_vftintrpl_l_s)
1967
+TRANS(vftintrph_l_s, ALL, gen_vv, gen_helper_vftintrph_l_s)
1968
+TRANS(vftintrml_l_s, ALL, gen_vv, gen_helper_vftintrml_l_s)
1969
+TRANS(vftintrmh_l_s, ALL, gen_vv, gen_helper_vftintrmh_l_s)
1970
+TRANS(vftintl_l_s, ALL, gen_vv, gen_helper_vftintl_l_s)
1971
+TRANS(vftinth_l_s, ALL, gen_vv, gen_helper_vftinth_l_s)
1972
+
1973
+TRANS(vffint_s_w, ALL, gen_vv, gen_helper_vffint_s_w)
1974
+TRANS(vffint_d_l, ALL, gen_vv, gen_helper_vffint_d_l)
1975
+TRANS(vffint_s_wu, ALL, gen_vv, gen_helper_vffint_s_wu)
1976
+TRANS(vffint_d_lu, ALL, gen_vv, gen_helper_vffint_d_lu)
1977
+TRANS(vffintl_d_w, ALL, gen_vv, gen_helper_vffintl_d_w)
1978
+TRANS(vffinth_d_w, ALL, gen_vv, gen_helper_vffinth_d_w)
1979
+TRANS(vffint_s_l, ALL, gen_vvv, gen_helper_vffint_s_l)
1980
1981
static bool do_cmp(DisasContext *ctx, arg_vvv *a, MemOp mop, TCGCond cond)
1982
{
1983
@@ -XXX,XX +XXX,XX @@ static bool do_## NAME ##_u(DisasContext *ctx, arg_vv_i *a, MemOp mop) \
1984
DO_CMPI_U(vslei)
1985
DO_CMPI_U(vslti)
1986
1987
-TRANS(vseq_b, do_cmp, MO_8, TCG_COND_EQ)
1988
-TRANS(vseq_h, do_cmp, MO_16, TCG_COND_EQ)
1989
-TRANS(vseq_w, do_cmp, MO_32, TCG_COND_EQ)
1990
-TRANS(vseq_d, do_cmp, MO_64, TCG_COND_EQ)
1991
-TRANS(vseqi_b, do_vseqi_s, MO_8)
1992
-TRANS(vseqi_h, do_vseqi_s, MO_16)
1993
-TRANS(vseqi_w, do_vseqi_s, MO_32)
1994
-TRANS(vseqi_d, do_vseqi_s, MO_64)
1995
-
1996
-TRANS(vsle_b, do_cmp, MO_8, TCG_COND_LE)
1997
-TRANS(vsle_h, do_cmp, MO_16, TCG_COND_LE)
1998
-TRANS(vsle_w, do_cmp, MO_32, TCG_COND_LE)
1999
-TRANS(vsle_d, do_cmp, MO_64, TCG_COND_LE)
2000
-TRANS(vslei_b, do_vslei_s, MO_8)
2001
-TRANS(vslei_h, do_vslei_s, MO_16)
2002
-TRANS(vslei_w, do_vslei_s, MO_32)
2003
-TRANS(vslei_d, do_vslei_s, MO_64)
2004
-TRANS(vsle_bu, do_cmp, MO_8, TCG_COND_LEU)
2005
-TRANS(vsle_hu, do_cmp, MO_16, TCG_COND_LEU)
2006
-TRANS(vsle_wu, do_cmp, MO_32, TCG_COND_LEU)
2007
-TRANS(vsle_du, do_cmp, MO_64, TCG_COND_LEU)
2008
-TRANS(vslei_bu, do_vslei_u, MO_8)
2009
-TRANS(vslei_hu, do_vslei_u, MO_16)
2010
-TRANS(vslei_wu, do_vslei_u, MO_32)
2011
-TRANS(vslei_du, do_vslei_u, MO_64)
2012
-
2013
-TRANS(vslt_b, do_cmp, MO_8, TCG_COND_LT)
2014
-TRANS(vslt_h, do_cmp, MO_16, TCG_COND_LT)
2015
-TRANS(vslt_w, do_cmp, MO_32, TCG_COND_LT)
2016
-TRANS(vslt_d, do_cmp, MO_64, TCG_COND_LT)
2017
-TRANS(vslti_b, do_vslti_s, MO_8)
2018
-TRANS(vslti_h, do_vslti_s, MO_16)
2019
-TRANS(vslti_w, do_vslti_s, MO_32)
2020
-TRANS(vslti_d, do_vslti_s, MO_64)
2021
-TRANS(vslt_bu, do_cmp, MO_8, TCG_COND_LTU)
2022
-TRANS(vslt_hu, do_cmp, MO_16, TCG_COND_LTU)
2023
-TRANS(vslt_wu, do_cmp, MO_32, TCG_COND_LTU)
2024
-TRANS(vslt_du, do_cmp, MO_64, TCG_COND_LTU)
2025
-TRANS(vslti_bu, do_vslti_u, MO_8)
2026
-TRANS(vslti_hu, do_vslti_u, MO_16)
2027
-TRANS(vslti_wu, do_vslti_u, MO_32)
2028
-TRANS(vslti_du, do_vslti_u, MO_64)
2029
+TRANS(vseq_b, ALL, do_cmp, MO_8, TCG_COND_EQ)
2030
+TRANS(vseq_h, ALL, do_cmp, MO_16, TCG_COND_EQ)
2031
+TRANS(vseq_w, ALL, do_cmp, MO_32, TCG_COND_EQ)
2032
+TRANS(vseq_d, ALL, do_cmp, MO_64, TCG_COND_EQ)
2033
+TRANS(vseqi_b, ALL, do_vseqi_s, MO_8)
2034
+TRANS(vseqi_h, ALL, do_vseqi_s, MO_16)
2035
+TRANS(vseqi_w, ALL, do_vseqi_s, MO_32)
2036
+TRANS(vseqi_d, ALL, do_vseqi_s, MO_64)
2037
+
2038
+TRANS(vsle_b, ALL, do_cmp, MO_8, TCG_COND_LE)
2039
+TRANS(vsle_h, ALL, do_cmp, MO_16, TCG_COND_LE)
2040
+TRANS(vsle_w, ALL, do_cmp, MO_32, TCG_COND_LE)
2041
+TRANS(vsle_d, ALL, do_cmp, MO_64, TCG_COND_LE)
2042
+TRANS(vslei_b, ALL, do_vslei_s, MO_8)
2043
+TRANS(vslei_h, ALL, do_vslei_s, MO_16)
2044
+TRANS(vslei_w, ALL, do_vslei_s, MO_32)
2045
+TRANS(vslei_d, ALL, do_vslei_s, MO_64)
2046
+TRANS(vsle_bu, ALL, do_cmp, MO_8, TCG_COND_LEU)
2047
+TRANS(vsle_hu, ALL, do_cmp, MO_16, TCG_COND_LEU)
2048
+TRANS(vsle_wu, ALL, do_cmp, MO_32, TCG_COND_LEU)
2049
+TRANS(vsle_du, ALL, do_cmp, MO_64, TCG_COND_LEU)
2050
+TRANS(vslei_bu, ALL, do_vslei_u, MO_8)
2051
+TRANS(vslei_hu, ALL, do_vslei_u, MO_16)
2052
+TRANS(vslei_wu, ALL, do_vslei_u, MO_32)
2053
+TRANS(vslei_du, ALL, do_vslei_u, MO_64)
2054
+
2055
+TRANS(vslt_b, ALL, do_cmp, MO_8, TCG_COND_LT)
2056
+TRANS(vslt_h, ALL, do_cmp, MO_16, TCG_COND_LT)
2057
+TRANS(vslt_w, ALL, do_cmp, MO_32, TCG_COND_LT)
2058
+TRANS(vslt_d, ALL, do_cmp, MO_64, TCG_COND_LT)
2059
+TRANS(vslti_b, ALL, do_vslti_s, MO_8)
2060
+TRANS(vslti_h, ALL, do_vslti_s, MO_16)
2061
+TRANS(vslti_w, ALL, do_vslti_s, MO_32)
2062
+TRANS(vslti_d, ALL, do_vslti_s, MO_64)
2063
+TRANS(vslt_bu, ALL, do_cmp, MO_8, TCG_COND_LTU)
2064
+TRANS(vslt_hu, ALL, do_cmp, MO_16, TCG_COND_LTU)
2065
+TRANS(vslt_wu, ALL, do_cmp, MO_32, TCG_COND_LTU)
2066
+TRANS(vslt_du, ALL, do_cmp, MO_64, TCG_COND_LTU)
2067
+TRANS(vslti_bu, ALL, do_vslti_u, MO_8)
2068
+TRANS(vslti_hu, ALL, do_vslti_u, MO_16)
2069
+TRANS(vslti_wu, ALL, do_vslti_u, MO_32)
2070
+TRANS(vslti_du, ALL, do_vslti_u, MO_64)
2071
2072
static bool trans_vfcmp_cond_s(DisasContext *ctx, arg_vvv_fcond *a)
2073
{
2074
@@ -XXX,XX +XXX,XX @@ static bool trans_## NAME (DisasContext *ctx, arg_cv *a) \
2075
VSET(vseteqz_v, TCG_COND_EQ)
2076
VSET(vsetnez_v, TCG_COND_NE)
2077
2078
-TRANS(vsetanyeqz_b, gen_cv, gen_helper_vsetanyeqz_b)
2079
-TRANS(vsetanyeqz_h, gen_cv, gen_helper_vsetanyeqz_h)
2080
-TRANS(vsetanyeqz_w, gen_cv, gen_helper_vsetanyeqz_w)
2081
-TRANS(vsetanyeqz_d, gen_cv, gen_helper_vsetanyeqz_d)
2082
-TRANS(vsetallnez_b, gen_cv, gen_helper_vsetallnez_b)
2083
-TRANS(vsetallnez_h, gen_cv, gen_helper_vsetallnez_h)
2084
-TRANS(vsetallnez_w, gen_cv, gen_helper_vsetallnez_w)
2085
-TRANS(vsetallnez_d, gen_cv, gen_helper_vsetallnez_d)
2086
+TRANS(vsetanyeqz_b, ALL, gen_cv, gen_helper_vsetanyeqz_b)
2087
+TRANS(vsetanyeqz_h, ALL, gen_cv, gen_helper_vsetanyeqz_h)
2088
+TRANS(vsetanyeqz_w, ALL, gen_cv, gen_helper_vsetanyeqz_w)
2089
+TRANS(vsetanyeqz_d, ALL, gen_cv, gen_helper_vsetanyeqz_d)
2090
+TRANS(vsetallnez_b, ALL, gen_cv, gen_helper_vsetallnez_b)
2091
+TRANS(vsetallnez_h, ALL, gen_cv, gen_helper_vsetallnez_h)
2092
+TRANS(vsetallnez_w, ALL, gen_cv, gen_helper_vsetallnez_w)
2093
+TRANS(vsetallnez_d, ALL, gen_cv, gen_helper_vsetallnez_d)
2094
2095
static bool trans_vinsgr2vr_b(DisasContext *ctx, arg_vr_i *a)
2096
{
2097
@@ -XXX,XX +XXX,XX @@ static bool gvec_dup(DisasContext *ctx, arg_vr *a, MemOp mop)
2098
return true;
2099
}
2100
2101
-TRANS(vreplgr2vr_b, gvec_dup, MO_8)
2102
-TRANS(vreplgr2vr_h, gvec_dup, MO_16)
2103
-TRANS(vreplgr2vr_w, gvec_dup, MO_32)
2104
-TRANS(vreplgr2vr_d, gvec_dup, MO_64)
2105
+TRANS(vreplgr2vr_b, ALL, gvec_dup, MO_8)
2106
+TRANS(vreplgr2vr_h, ALL, gvec_dup, MO_16)
2107
+TRANS(vreplgr2vr_w, ALL, gvec_dup, MO_32)
2108
+TRANS(vreplgr2vr_d, ALL, gvec_dup, MO_64)
2109
2110
static bool trans_vreplvei_b(DisasContext *ctx, arg_vv_i *a)
2111
{
2112
@@ -XXX,XX +XXX,XX @@ static bool gen_vreplve(DisasContext *ctx, arg_vvr *a, int vece, int bit,
2113
return true;
2114
}
2115
2116
-TRANS(vreplve_b, gen_vreplve, MO_8, 8, tcg_gen_ld8u_i64)
2117
-TRANS(vreplve_h, gen_vreplve, MO_16, 16, tcg_gen_ld16u_i64)
2118
-TRANS(vreplve_w, gen_vreplve, MO_32, 32, tcg_gen_ld32u_i64)
2119
-TRANS(vreplve_d, gen_vreplve, MO_64, 64, tcg_gen_ld_i64)
2120
+TRANS(vreplve_b, ALL, gen_vreplve, MO_8, 8, tcg_gen_ld8u_i64)
2121
+TRANS(vreplve_h, ALL, gen_vreplve, MO_16, 16, tcg_gen_ld16u_i64)
2122
+TRANS(vreplve_w, ALL, gen_vreplve, MO_32, 32, tcg_gen_ld32u_i64)
2123
+TRANS(vreplve_d, ALL, gen_vreplve, MO_64, 64, tcg_gen_ld_i64)
2124
2125
static bool trans_vbsll_v(DisasContext *ctx, arg_vv_i *a)
2126
{
2127
@@ -XXX,XX +XXX,XX @@ static bool trans_vbsrl_v(DisasContext *ctx, arg_vv_i *a)
2128
return true;
2129
}
2130
2131
-TRANS(vpackev_b, gen_vvv, gen_helper_vpackev_b)
2132
-TRANS(vpackev_h, gen_vvv, gen_helper_vpackev_h)
2133
-TRANS(vpackev_w, gen_vvv, gen_helper_vpackev_w)
2134
-TRANS(vpackev_d, gen_vvv, gen_helper_vpackev_d)
2135
-TRANS(vpackod_b, gen_vvv, gen_helper_vpackod_b)
2136
-TRANS(vpackod_h, gen_vvv, gen_helper_vpackod_h)
2137
-TRANS(vpackod_w, gen_vvv, gen_helper_vpackod_w)
2138
-TRANS(vpackod_d, gen_vvv, gen_helper_vpackod_d)
2139
-
2140
-TRANS(vpickev_b, gen_vvv, gen_helper_vpickev_b)
2141
-TRANS(vpickev_h, gen_vvv, gen_helper_vpickev_h)
2142
-TRANS(vpickev_w, gen_vvv, gen_helper_vpickev_w)
2143
-TRANS(vpickev_d, gen_vvv, gen_helper_vpickev_d)
2144
-TRANS(vpickod_b, gen_vvv, gen_helper_vpickod_b)
2145
-TRANS(vpickod_h, gen_vvv, gen_helper_vpickod_h)
2146
-TRANS(vpickod_w, gen_vvv, gen_helper_vpickod_w)
2147
-TRANS(vpickod_d, gen_vvv, gen_helper_vpickod_d)
2148
-
2149
-TRANS(vilvl_b, gen_vvv, gen_helper_vilvl_b)
2150
-TRANS(vilvl_h, gen_vvv, gen_helper_vilvl_h)
2151
-TRANS(vilvl_w, gen_vvv, gen_helper_vilvl_w)
2152
-TRANS(vilvl_d, gen_vvv, gen_helper_vilvl_d)
2153
-TRANS(vilvh_b, gen_vvv, gen_helper_vilvh_b)
2154
-TRANS(vilvh_h, gen_vvv, gen_helper_vilvh_h)
2155
-TRANS(vilvh_w, gen_vvv, gen_helper_vilvh_w)
2156
-TRANS(vilvh_d, gen_vvv, gen_helper_vilvh_d)
2157
-
2158
-TRANS(vshuf_b, gen_vvvv, gen_helper_vshuf_b)
2159
-TRANS(vshuf_h, gen_vvv, gen_helper_vshuf_h)
2160
-TRANS(vshuf_w, gen_vvv, gen_helper_vshuf_w)
2161
-TRANS(vshuf_d, gen_vvv, gen_helper_vshuf_d)
2162
-TRANS(vshuf4i_b, gen_vv_i, gen_helper_vshuf4i_b)
2163
-TRANS(vshuf4i_h, gen_vv_i, gen_helper_vshuf4i_h)
2164
-TRANS(vshuf4i_w, gen_vv_i, gen_helper_vshuf4i_w)
2165
-TRANS(vshuf4i_d, gen_vv_i, gen_helper_vshuf4i_d)
2166
-
2167
-TRANS(vpermi_w, gen_vv_i, gen_helper_vpermi_w)
2168
-
2169
-TRANS(vextrins_b, gen_vv_i, gen_helper_vextrins_b)
2170
-TRANS(vextrins_h, gen_vv_i, gen_helper_vextrins_h)
2171
-TRANS(vextrins_w, gen_vv_i, gen_helper_vextrins_w)
2172
-TRANS(vextrins_d, gen_vv_i, gen_helper_vextrins_d)
2173
+TRANS(vpackev_b, ALL, gen_vvv, gen_helper_vpackev_b)
2174
+TRANS(vpackev_h, ALL, gen_vvv, gen_helper_vpackev_h)
2175
+TRANS(vpackev_w, ALL, gen_vvv, gen_helper_vpackev_w)
2176
+TRANS(vpackev_d, ALL, gen_vvv, gen_helper_vpackev_d)
2177
+TRANS(vpackod_b, ALL, gen_vvv, gen_helper_vpackod_b)
2178
+TRANS(vpackod_h, ALL, gen_vvv, gen_helper_vpackod_h)
2179
+TRANS(vpackod_w, ALL, gen_vvv, gen_helper_vpackod_w)
2180
+TRANS(vpackod_d, ALL, gen_vvv, gen_helper_vpackod_d)
2181
+
2182
+TRANS(vpickev_b, ALL, gen_vvv, gen_helper_vpickev_b)
2183
+TRANS(vpickev_h, ALL, gen_vvv, gen_helper_vpickev_h)
2184
+TRANS(vpickev_w, ALL, gen_vvv, gen_helper_vpickev_w)
2185
+TRANS(vpickev_d, ALL, gen_vvv, gen_helper_vpickev_d)
2186
+TRANS(vpickod_b, ALL, gen_vvv, gen_helper_vpickod_b)
2187
+TRANS(vpickod_h, ALL, gen_vvv, gen_helper_vpickod_h)
2188
+TRANS(vpickod_w, ALL, gen_vvv, gen_helper_vpickod_w)
2189
+TRANS(vpickod_d, ALL, gen_vvv, gen_helper_vpickod_d)
2190
+
2191
+TRANS(vilvl_b, ALL, gen_vvv, gen_helper_vilvl_b)
2192
+TRANS(vilvl_h, ALL, gen_vvv, gen_helper_vilvl_h)
2193
+TRANS(vilvl_w, ALL, gen_vvv, gen_helper_vilvl_w)
2194
+TRANS(vilvl_d, ALL, gen_vvv, gen_helper_vilvl_d)
2195
+TRANS(vilvh_b, ALL, gen_vvv, gen_helper_vilvh_b)
2196
+TRANS(vilvh_h, ALL, gen_vvv, gen_helper_vilvh_h)
2197
+TRANS(vilvh_w, ALL, gen_vvv, gen_helper_vilvh_w)
2198
+TRANS(vilvh_d, ALL, gen_vvv, gen_helper_vilvh_d)
2199
+
2200
+TRANS(vshuf_b, ALL, gen_vvvv, gen_helper_vshuf_b)
2201
+TRANS(vshuf_h, ALL, gen_vvv, gen_helper_vshuf_h)
2202
+TRANS(vshuf_w, ALL, gen_vvv, gen_helper_vshuf_w)
2203
+TRANS(vshuf_d, ALL, gen_vvv, gen_helper_vshuf_d)
2204
+TRANS(vshuf4i_b, ALL, gen_vv_i, gen_helper_vshuf4i_b)
2205
+TRANS(vshuf4i_h, ALL, gen_vv_i, gen_helper_vshuf4i_h)
2206
+TRANS(vshuf4i_w, ALL, gen_vv_i, gen_helper_vshuf4i_w)
2207
+TRANS(vshuf4i_d, ALL, gen_vv_i, gen_helper_vshuf4i_d)
2208
+
2209
+TRANS(vpermi_w, ALL, gen_vv_i, gen_helper_vpermi_w)
2210
+
2211
+TRANS(vextrins_b, ALL, gen_vv_i, gen_helper_vextrins_b)
2212
+TRANS(vextrins_h, ALL, gen_vv_i, gen_helper_vextrins_h)
2213
+TRANS(vextrins_w, ALL, gen_vv_i, gen_helper_vextrins_w)
2214
+TRANS(vextrins_d, ALL, gen_vv_i, gen_helper_vextrins_d)
2215
2216
static bool trans_vld(DisasContext *ctx, arg_vr_i *a)
2217
{
2218
diff --git a/target/loongarch/insn_trans/trans_memory.c.inc b/target/loongarch/insn_trans/trans_memory.c.inc
2219
index XXXXXXX..XXXXXXX 100644
2220
--- a/target/loongarch/insn_trans/trans_memory.c.inc
2221
+++ b/target/loongarch/insn_trans/trans_memory.c.inc
2222
@@ -XXX,XX +XXX,XX @@ static bool gen_stptr(DisasContext *ctx, arg_rr_i *a, MemOp mop)
2223
return true;
2224
}
2225
2226
-TRANS(ld_b, gen_load, MO_SB)
2227
-TRANS(ld_h, gen_load, MO_TESW)
2228
-TRANS(ld_w, gen_load, MO_TESL)
2229
-TRANS(ld_d, gen_load, MO_TEUQ)
2230
-TRANS(st_b, gen_store, MO_UB)
2231
-TRANS(st_h, gen_store, MO_TEUW)
2232
-TRANS(st_w, gen_store, MO_TEUL)
2233
-TRANS(st_d, gen_store, MO_TEUQ)
2234
-TRANS(ld_bu, gen_load, MO_UB)
2235
-TRANS(ld_hu, gen_load, MO_TEUW)
2236
-TRANS(ld_wu, gen_load, MO_TEUL)
2237
-TRANS(ldx_b, gen_loadx, MO_SB)
2238
-TRANS(ldx_h, gen_loadx, MO_TESW)
2239
-TRANS(ldx_w, gen_loadx, MO_TESL)
2240
-TRANS(ldx_d, gen_loadx, MO_TEUQ)
2241
-TRANS(stx_b, gen_storex, MO_UB)
2242
-TRANS(stx_h, gen_storex, MO_TEUW)
2243
-TRANS(stx_w, gen_storex, MO_TEUL)
2244
-TRANS(stx_d, gen_storex, MO_TEUQ)
2245
-TRANS(ldx_bu, gen_loadx, MO_UB)
2246
-TRANS(ldx_hu, gen_loadx, MO_TEUW)
2247
-TRANS(ldx_wu, gen_loadx, MO_TEUL)
2248
-TRANS(ldptr_w, gen_ldptr, MO_TESL)
2249
-TRANS(stptr_w, gen_stptr, MO_TEUL)
2250
-TRANS(ldptr_d, gen_ldptr, MO_TEUQ)
2251
-TRANS(stptr_d, gen_stptr, MO_TEUQ)
2252
-TRANS(ldgt_b, gen_load_gt, MO_SB)
2253
-TRANS(ldgt_h, gen_load_gt, MO_TESW)
2254
-TRANS(ldgt_w, gen_load_gt, MO_TESL)
2255
-TRANS(ldgt_d, gen_load_gt, MO_TEUQ)
2256
-TRANS(ldle_b, gen_load_le, MO_SB)
2257
-TRANS(ldle_h, gen_load_le, MO_TESW)
2258
-TRANS(ldle_w, gen_load_le, MO_TESL)
2259
-TRANS(ldle_d, gen_load_le, MO_TEUQ)
2260
-TRANS(stgt_b, gen_store_gt, MO_UB)
2261
-TRANS(stgt_h, gen_store_gt, MO_TEUW)
2262
-TRANS(stgt_w, gen_store_gt, MO_TEUL)
2263
-TRANS(stgt_d, gen_store_gt, MO_TEUQ)
2264
-TRANS(stle_b, gen_store_le, MO_UB)
2265
-TRANS(stle_h, gen_store_le, MO_TEUW)
2266
-TRANS(stle_w, gen_store_le, MO_TEUL)
2267
-TRANS(stle_d, gen_store_le, MO_TEUQ)
2268
+TRANS(ld_b, ALL, gen_load, MO_SB)
2269
+TRANS(ld_h, ALL, gen_load, MO_TESW)
2270
+TRANS(ld_w, ALL, gen_load, MO_TESL)
2271
+TRANS(ld_d, ALL, gen_load, MO_TEUQ)
2272
+TRANS(st_b, ALL, gen_store, MO_UB)
2273
+TRANS(st_h, ALL, gen_store, MO_TEUW)
2274
+TRANS(st_w, ALL, gen_store, MO_TEUL)
2275
+TRANS(st_d, ALL, gen_store, MO_TEUQ)
2276
+TRANS(ld_bu, ALL, gen_load, MO_UB)
2277
+TRANS(ld_hu, ALL, gen_load, MO_TEUW)
2278
+TRANS(ld_wu, ALL, gen_load, MO_TEUL)
2279
+TRANS(ldx_b, ALL, gen_loadx, MO_SB)
2280
+TRANS(ldx_h, ALL, gen_loadx, MO_TESW)
2281
+TRANS(ldx_w, ALL, gen_loadx, MO_TESL)
2282
+TRANS(ldx_d, ALL, gen_loadx, MO_TEUQ)
2283
+TRANS(stx_b, ALL, gen_storex, MO_UB)
2284
+TRANS(stx_h, ALL, gen_storex, MO_TEUW)
2285
+TRANS(stx_w, ALL, gen_storex, MO_TEUL)
2286
+TRANS(stx_d, ALL, gen_storex, MO_TEUQ)
2287
+TRANS(ldx_bu, ALL, gen_loadx, MO_UB)
2288
+TRANS(ldx_hu, ALL, gen_loadx, MO_TEUW)
2289
+TRANS(ldx_wu, ALL, gen_loadx, MO_TEUL)
2290
+TRANS(ldptr_w, ALL, gen_ldptr, MO_TESL)
2291
+TRANS(stptr_w, ALL, gen_stptr, MO_TEUL)
2292
+TRANS(ldptr_d, ALL, gen_ldptr, MO_TEUQ)
2293
+TRANS(stptr_d, ALL, gen_stptr, MO_TEUQ)
2294
+TRANS(ldgt_b, ALL, gen_load_gt, MO_SB)
2295
+TRANS(ldgt_h, ALL, gen_load_gt, MO_TESW)
2296
+TRANS(ldgt_w, ALL, gen_load_gt, MO_TESL)
2297
+TRANS(ldgt_d, ALL, gen_load_gt, MO_TEUQ)
2298
+TRANS(ldle_b, ALL, gen_load_le, MO_SB)
2299
+TRANS(ldle_h, ALL, gen_load_le, MO_TESW)
2300
+TRANS(ldle_w, ALL, gen_load_le, MO_TESL)
2301
+TRANS(ldle_d, ALL, gen_load_le, MO_TEUQ)
2302
+TRANS(stgt_b, ALL, gen_store_gt, MO_UB)
2303
+TRANS(stgt_h, ALL, gen_store_gt, MO_TEUW)
2304
+TRANS(stgt_w, ALL, gen_store_gt, MO_TEUL)
2305
+TRANS(stgt_d, ALL, gen_store_gt, MO_TEUQ)
2306
+TRANS(stle_b, ALL, gen_store_le, MO_UB)
2307
+TRANS(stle_h, ALL, gen_store_le, MO_TEUW)
2308
+TRANS(stle_w, ALL, gen_store_le, MO_TEUL)
2309
+TRANS(stle_d, ALL, gen_store_le, MO_TEUQ)
2310
diff --git a/target/loongarch/insn_trans/trans_privileged.c.inc b/target/loongarch/insn_trans/trans_privileged.c.inc
2311
index XXXXXXX..XXXXXXX 100644
2312
--- a/target/loongarch/insn_trans/trans_privileged.c.inc
2313
+++ b/target/loongarch/insn_trans/trans_privileged.c.inc
2314
@@ -XXX,XX +XXX,XX @@ static bool gen_iocsrwr(DisasContext *ctx, arg_rr *a,
2315
return true;
2316
}
2317
2318
-TRANS(iocsrrd_b, gen_iocsrrd, gen_helper_iocsrrd_b)
2319
-TRANS(iocsrrd_h, gen_iocsrrd, gen_helper_iocsrrd_h)
2320
-TRANS(iocsrrd_w, gen_iocsrrd, gen_helper_iocsrrd_w)
2321
-TRANS(iocsrrd_d, gen_iocsrrd, gen_helper_iocsrrd_d)
2322
-TRANS(iocsrwr_b, gen_iocsrwr, gen_helper_iocsrwr_b)
2323
-TRANS(iocsrwr_h, gen_iocsrwr, gen_helper_iocsrwr_h)
2324
-TRANS(iocsrwr_w, gen_iocsrwr, gen_helper_iocsrwr_w)
2325
-TRANS(iocsrwr_d, gen_iocsrwr, gen_helper_iocsrwr_d)
2326
+TRANS(iocsrrd_b, ALL, gen_iocsrrd, gen_helper_iocsrrd_b)
2327
+TRANS(iocsrrd_h, ALL, gen_iocsrrd, gen_helper_iocsrrd_h)
2328
+TRANS(iocsrrd_w, ALL, gen_iocsrrd, gen_helper_iocsrrd_w)
2329
+TRANS(iocsrrd_d, ALL, gen_iocsrrd, gen_helper_iocsrrd_d)
2330
+TRANS(iocsrwr_b, ALL, gen_iocsrwr, gen_helper_iocsrwr_b)
2331
+TRANS(iocsrwr_h, ALL, gen_iocsrwr, gen_helper_iocsrwr_h)
2332
+TRANS(iocsrwr_w, ALL, gen_iocsrwr, gen_helper_iocsrwr_w)
2333
+TRANS(iocsrwr_d, ALL, gen_iocsrwr, gen_helper_iocsrwr_d)
2334
2335
static void check_mmu_idx(DisasContext *ctx)
2336
{
2337
diff --git a/target/loongarch/insn_trans/trans_shift.c.inc b/target/loongarch/insn_trans/trans_shift.c.inc
2338
index XXXXXXX..XXXXXXX 100644
2339
--- a/target/loongarch/insn_trans/trans_shift.c.inc
2340
+++ b/target/loongarch/insn_trans/trans_shift.c.inc
2341
@@ -XXX,XX +XXX,XX @@ static bool trans_srai_w(DisasContext *ctx, arg_srai_w *a)
2342
return true;
2343
}
2344
2345
-TRANS(sll_w, gen_rrr, EXT_ZERO, EXT_NONE, EXT_SIGN, gen_sll_w)
2346
-TRANS(srl_w, gen_rrr, EXT_ZERO, EXT_NONE, EXT_SIGN, gen_srl_w)
2347
-TRANS(sra_w, gen_rrr, EXT_SIGN, EXT_NONE, EXT_SIGN, gen_sra_w)
2348
-TRANS(sll_d, gen_rrr, EXT_NONE, EXT_NONE, EXT_NONE, gen_sll_d)
2349
-TRANS(srl_d, gen_rrr, EXT_NONE, EXT_NONE, EXT_NONE, gen_srl_d)
2350
-TRANS(sra_d, gen_rrr, EXT_NONE, EXT_NONE, EXT_NONE, gen_sra_d)
2351
-TRANS(rotr_w, gen_rrr, EXT_ZERO, EXT_NONE, EXT_SIGN, gen_rotr_w)
2352
-TRANS(rotr_d, gen_rrr, EXT_NONE, EXT_NONE, EXT_NONE, gen_rotr_d)
2353
-TRANS(slli_w, gen_rri_c, EXT_NONE, EXT_SIGN, tcg_gen_shli_tl)
2354
-TRANS(slli_d, gen_rri_c, EXT_NONE, EXT_NONE, tcg_gen_shli_tl)
2355
-TRANS(srli_w, gen_rri_c, EXT_ZERO, EXT_SIGN, tcg_gen_shri_tl)
2356
-TRANS(srli_d, gen_rri_c, EXT_NONE, EXT_NONE, tcg_gen_shri_tl)
2357
-TRANS(srai_d, gen_rri_c, EXT_NONE, EXT_NONE, tcg_gen_sari_tl)
2358
-TRANS(rotri_w, gen_rri_v, EXT_NONE, EXT_NONE, gen_rotr_w)
2359
-TRANS(rotri_d, gen_rri_c, EXT_NONE, EXT_NONE, tcg_gen_rotri_tl)
2360
+TRANS(sll_w, ALL, gen_rrr, EXT_ZERO, EXT_NONE, EXT_SIGN, gen_sll_w)
2361
+TRANS(srl_w, ALL, gen_rrr, EXT_ZERO, EXT_NONE, EXT_SIGN, gen_srl_w)
2362
+TRANS(sra_w, ALL, gen_rrr, EXT_SIGN, EXT_NONE, EXT_SIGN, gen_sra_w)
2363
+TRANS(sll_d, ALL, gen_rrr, EXT_NONE, EXT_NONE, EXT_NONE, gen_sll_d)
2364
+TRANS(srl_d, ALL, gen_rrr, EXT_NONE, EXT_NONE, EXT_NONE, gen_srl_d)
2365
+TRANS(sra_d, ALL, gen_rrr, EXT_NONE, EXT_NONE, EXT_NONE, gen_sra_d)
2366
+TRANS(rotr_w, ALL, gen_rrr, EXT_ZERO, EXT_NONE, EXT_SIGN, gen_rotr_w)
2367
+TRANS(rotr_d, ALL, gen_rrr, EXT_NONE, EXT_NONE, EXT_NONE, gen_rotr_d)
2368
+TRANS(slli_w, ALL, gen_rri_c, EXT_NONE, EXT_SIGN, tcg_gen_shli_tl)
2369
+TRANS(slli_d, ALL, gen_rri_c, EXT_NONE, EXT_NONE, tcg_gen_shli_tl)
2370
+TRANS(srli_w, ALL, gen_rri_c, EXT_ZERO, EXT_SIGN, tcg_gen_shri_tl)
2371
+TRANS(srli_d, ALL, gen_rri_c, EXT_NONE, EXT_NONE, tcg_gen_shri_tl)
2372
+TRANS(srai_d, ALL, gen_rri_c, EXT_NONE, EXT_NONE, tcg_gen_sari_tl)
2373
+TRANS(rotri_w, ALL, gen_rri_v, EXT_NONE, EXT_NONE, gen_rotr_w)
2374
+TRANS(rotri_d, ALL, gen_rri_c, EXT_NONE, EXT_NONE, tcg_gen_rotri_tl)
2375
diff --git a/target/loongarch/translate.h b/target/loongarch/translate.h
2376
index XXXXXXX..XXXXXXX 100644
2377
--- a/target/loongarch/translate.h
2378
+++ b/target/loongarch/translate.h
2379
@@ -XXX,XX +XXX,XX @@
2380
2381
#include "exec/translator.h"
2382
2383
-#define TRANS(NAME, FUNC, ...) \
2384
+#define TRANS(NAME, AVAIL, FUNC, ...) \
2385
static bool trans_##NAME(DisasContext *ctx, arg_##NAME * a) \
2386
- { return FUNC(ctx, a, __VA_ARGS__); }
2387
+ { return avail_##AVAIL(ctx) && FUNC(ctx, a, __VA_ARGS__); }
2388
+
2389
+#define avail_ALL(C) true
2390
2391
/*
2392
* If an operation is being performed on less than TARGET_LONG_BITS,
2393
--
2394
2.39.1
2395
2396
diff view generated by jsdifflib
New patch
[PULL 20/31] target/loongarch: Add avail_64 to check la64-only instructions
1
The la32 instructions listed in Table 2 at
2
https://loongson.github.io/LoongArch-Documentation/LoongArch-Vol1-EN.html#overview-of-basic-integer-instructions
1
3
4
Co-authored-by: Jiajie Chen <c@jia.je>
5
Signed-off-by: Song Gao <gaosong@loongson.cn>
6
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
7
Message-ID: <20230822032724.1353391-9-gaosong@loongson.cn>
8
Message-Id: <20230822071959.35620-3-philmd@linaro.org>
9
---
10
target/loongarch/insn_trans/trans_arith.c.inc | 42 ++++++----
11
.../loongarch/insn_trans/trans_atomic.c.inc | 76 +++++++++----------
12
target/loongarch/insn_trans/trans_bit.c.inc | 28 +++----
13
.../loongarch/insn_trans/trans_branch.c.inc | 4 +-
14
target/loongarch/insn_trans/trans_extra.c.inc | 24 ++++--
15
target/loongarch/insn_trans/trans_fmov.c.inc | 4 +-
16
.../loongarch/insn_trans/trans_memory.c.inc | 68 ++++++++---------
17
target/loongarch/insn_trans/trans_shift.c.inc | 24 +++---
18
target/loongarch/translate.c | 2 +
19
target/loongarch/translate.h | 3 +
20
10 files changed, 152 insertions(+), 123 deletions(-)
21
22
diff --git a/target/loongarch/insn_trans/trans_arith.c.inc b/target/loongarch/insn_trans/trans_arith.c.inc
23
index XXXXXXX..XXXXXXX 100644
24
--- a/target/loongarch/insn_trans/trans_arith.c.inc
25
+++ b/target/loongarch/insn_trans/trans_arith.c.inc
26
@@ -XXX,XX +XXX,XX @@ static bool trans_lu32i_d(DisasContext *ctx, arg_lu32i_d *a)
27
TCGv src1 = gpr_src(ctx, a->rd, EXT_NONE);
28
TCGv src2 = tcg_constant_tl(a->imm);
29
30
+ if (!avail_64(ctx)) {
31
+ return false;
32
+ }
33
+
34
tcg_gen_deposit_tl(dest, src1, src2, 32, 32);
35
gen_set_gpr(a->rd, dest, EXT_NONE);
36
37
@@ -XXX,XX +XXX,XX @@ static bool trans_lu52i_d(DisasContext *ctx, arg_lu52i_d *a)
38
TCGv src1 = gpr_src(ctx, a->rj, EXT_NONE);
39
TCGv src2 = tcg_constant_tl(a->imm);
40
41
+ if (!avail_64(ctx)) {
42
+ return false;
43
+ }
44
+
45
tcg_gen_deposit_tl(dest, src1, src2, 52, 12);
46
gen_set_gpr(a->rd, dest, EXT_NONE);
47
48
@@ -XXX,XX +XXX,XX @@ static bool trans_addu16i_d(DisasContext *ctx, arg_addu16i_d *a)
49
TCGv dest = gpr_dst(ctx, a->rd, EXT_NONE);
50
TCGv src1 = gpr_src(ctx, a->rj, EXT_NONE);
51
52
+ if (!avail_64(ctx)) {
53
+ return false;
54
+ }
55
+
56
tcg_gen_addi_tl(dest, src1, a->imm << 16);
57
gen_set_gpr(a->rd, dest, EXT_NONE);
58
59
@@ -XXX,XX +XXX,XX @@ static bool trans_addu16i_d(DisasContext *ctx, arg_addu16i_d *a)
60
}
61
62
TRANS(add_w, ALL, gen_rrr, EXT_NONE, EXT_NONE, EXT_SIGN, tcg_gen_add_tl)
63
-TRANS(add_d, ALL, gen_rrr, EXT_NONE, EXT_NONE, EXT_NONE, tcg_gen_add_tl)
64
+TRANS(add_d, 64, gen_rrr, EXT_NONE, EXT_NONE, EXT_NONE, tcg_gen_add_tl)
65
TRANS(sub_w, ALL, gen_rrr, EXT_NONE, EXT_NONE, EXT_SIGN, tcg_gen_sub_tl)
66
-TRANS(sub_d, ALL, gen_rrr, EXT_NONE, EXT_NONE, EXT_NONE, tcg_gen_sub_tl)
67
+TRANS(sub_d, 64, gen_rrr, EXT_NONE, EXT_NONE, EXT_NONE, tcg_gen_sub_tl)
68
TRANS(and, ALL, gen_rrr, EXT_NONE, EXT_NONE, EXT_NONE, tcg_gen_and_tl)
69
TRANS(or, ALL, gen_rrr, EXT_NONE, EXT_NONE, EXT_NONE, tcg_gen_or_tl)
70
TRANS(xor, ALL, gen_rrr, EXT_NONE, EXT_NONE, EXT_NONE, tcg_gen_xor_tl)
71
@@ -XXX,XX +XXX,XX @@ TRANS(orn, ALL, gen_rrr, EXT_NONE, EXT_NONE, EXT_NONE, tcg_gen_orc_tl)
72
TRANS(slt, ALL, gen_rrr, EXT_NONE, EXT_NONE, EXT_NONE, gen_slt)
73
TRANS(sltu, ALL, gen_rrr, EXT_NONE, EXT_NONE, EXT_NONE, gen_sltu)
74
TRANS(mul_w, ALL, gen_rrr, EXT_SIGN, EXT_SIGN, EXT_SIGN, tcg_gen_mul_tl)
75
-TRANS(mul_d, ALL, gen_rrr, EXT_NONE, EXT_NONE, EXT_NONE, tcg_gen_mul_tl)
76
+TRANS(mul_d, 64, gen_rrr, EXT_NONE, EXT_NONE, EXT_NONE, tcg_gen_mul_tl)
77
TRANS(mulh_w, ALL, gen_rrr, EXT_SIGN, EXT_SIGN, EXT_NONE, gen_mulh_w)
78
TRANS(mulh_wu, ALL, gen_rrr, EXT_ZERO, EXT_ZERO, EXT_NONE, gen_mulh_w)
79
-TRANS(mulh_d, ALL, gen_rrr, EXT_NONE, EXT_NONE, EXT_NONE, gen_mulh_d)
80
-TRANS(mulh_du, ALL, gen_rrr, EXT_NONE, EXT_NONE, EXT_NONE, gen_mulh_du)
81
-TRANS(mulw_d_w, ALL, gen_rrr, EXT_SIGN, EXT_SIGN, EXT_NONE, tcg_gen_mul_tl)
82
-TRANS(mulw_d_wu, ALL, gen_rrr, EXT_ZERO, EXT_ZERO, EXT_NONE, tcg_gen_mul_tl)
83
+TRANS(mulh_d, 64, gen_rrr, EXT_NONE, EXT_NONE, EXT_NONE, gen_mulh_d)
84
+TRANS(mulh_du, 64, gen_rrr, EXT_NONE, EXT_NONE, EXT_NONE, gen_mulh_du)
85
+TRANS(mulw_d_w, 64, gen_rrr, EXT_SIGN, EXT_SIGN, EXT_NONE, tcg_gen_mul_tl)
86
+TRANS(mulw_d_wu, 64, gen_rrr, EXT_ZERO, EXT_ZERO, EXT_NONE, tcg_gen_mul_tl)
87
TRANS(div_w, ALL, gen_rrr, EXT_SIGN, EXT_SIGN, EXT_SIGN, gen_div_w)
88
TRANS(mod_w, ALL, gen_rrr, EXT_SIGN, EXT_SIGN, EXT_SIGN, gen_rem_w)
89
TRANS(div_wu, ALL, gen_rrr, EXT_ZERO, EXT_ZERO, EXT_SIGN, gen_div_du)
90
TRANS(mod_wu, ALL, gen_rrr, EXT_ZERO, EXT_ZERO, EXT_SIGN, gen_rem_du)
91
-TRANS(div_d, ALL, gen_rrr, EXT_NONE, EXT_NONE, EXT_NONE, gen_div_d)
92
-TRANS(mod_d, ALL, gen_rrr, EXT_NONE, EXT_NONE, EXT_NONE, gen_rem_d)
93
-TRANS(div_du, ALL, gen_rrr, EXT_NONE, EXT_NONE, EXT_NONE, gen_div_du)
94
-TRANS(mod_du, ALL, gen_rrr, EXT_NONE, EXT_NONE, EXT_NONE, gen_rem_du)
95
+TRANS(div_d, 64, gen_rrr, EXT_NONE, EXT_NONE, EXT_NONE, gen_div_d)
96
+TRANS(mod_d, 64, gen_rrr, EXT_NONE, EXT_NONE, EXT_NONE, gen_rem_d)
97
+TRANS(div_du, 64, gen_rrr, EXT_NONE, EXT_NONE, EXT_NONE, gen_div_du)
98
+TRANS(mod_du, 64, gen_rrr, EXT_NONE, EXT_NONE, EXT_NONE, gen_rem_du)
99
TRANS(slti, ALL, gen_rri_v, EXT_NONE, EXT_NONE, gen_slt)
100
TRANS(sltui, ALL, gen_rri_v, EXT_NONE, EXT_NONE, gen_sltu)
101
TRANS(addi_w, ALL, gen_rri_c, EXT_NONE, EXT_SIGN, tcg_gen_addi_tl)
102
-TRANS(addi_d, ALL, gen_rri_c, EXT_NONE, EXT_NONE, tcg_gen_addi_tl)
103
+TRANS(addi_d, 64, gen_rri_c, EXT_NONE, EXT_NONE, tcg_gen_addi_tl)
104
TRANS(alsl_w, ALL, gen_rrr_sa, EXT_NONE, EXT_SIGN, gen_alsl)
105
-TRANS(alsl_wu, ALL, gen_rrr_sa, EXT_NONE, EXT_ZERO, gen_alsl)
106
-TRANS(alsl_d, ALL, gen_rrr_sa, EXT_NONE, EXT_NONE, gen_alsl)
107
+TRANS(alsl_wu, 64, gen_rrr_sa, EXT_NONE, EXT_ZERO, gen_alsl)
108
+TRANS(alsl_d, 64, gen_rrr_sa, EXT_NONE, EXT_NONE, gen_alsl)
109
TRANS(pcaddi, ALL, gen_pc, gen_pcaddi)
110
TRANS(pcalau12i, ALL, gen_pc, gen_pcalau12i)
111
TRANS(pcaddu12i, ALL, gen_pc, gen_pcaddu12i)
112
-TRANS(pcaddu18i, ALL, gen_pc, gen_pcaddu18i)
113
+TRANS(pcaddu18i, 64, gen_pc, gen_pcaddu18i)
114
TRANS(andi, ALL, gen_rri_c, EXT_NONE, EXT_NONE, tcg_gen_andi_tl)
115
TRANS(ori, ALL, gen_rri_c, EXT_NONE, EXT_NONE, tcg_gen_ori_tl)
116
TRANS(xori, ALL, gen_rri_c, EXT_NONE, EXT_NONE, tcg_gen_xori_tl)
117
diff --git a/target/loongarch/insn_trans/trans_atomic.c.inc b/target/loongarch/insn_trans/trans_atomic.c.inc
118
index XXXXXXX..XXXXXXX 100644
119
--- a/target/loongarch/insn_trans/trans_atomic.c.inc
120
+++ b/target/loongarch/insn_trans/trans_atomic.c.inc
121
@@ -XXX,XX +XXX,XX @@ static bool gen_am(DisasContext *ctx, arg_rrr *a,
122
123
TRANS(ll_w, ALL, gen_ll, MO_TESL)
124
TRANS(sc_w, ALL, gen_sc, MO_TESL)
125
-TRANS(ll_d, ALL, gen_ll, MO_TEUQ)
126
-TRANS(sc_d, ALL, gen_sc, MO_TEUQ)
127
-TRANS(amswap_w, ALL, gen_am, tcg_gen_atomic_xchg_tl, MO_TESL)
128
-TRANS(amswap_d, ALL, gen_am, tcg_gen_atomic_xchg_tl, MO_TEUQ)
129
-TRANS(amadd_w, ALL, gen_am, tcg_gen_atomic_fetch_add_tl, MO_TESL)
130
-TRANS(amadd_d, ALL, gen_am, tcg_gen_atomic_fetch_add_tl, MO_TEUQ)
131
-TRANS(amand_w, ALL, gen_am, tcg_gen_atomic_fetch_and_tl, MO_TESL)
132
-TRANS(amand_d, ALL, gen_am, tcg_gen_atomic_fetch_and_tl, MO_TEUQ)
133
-TRANS(amor_w, ALL, gen_am, tcg_gen_atomic_fetch_or_tl, MO_TESL)
134
-TRANS(amor_d, ALL, gen_am, tcg_gen_atomic_fetch_or_tl, MO_TEUQ)
135
-TRANS(amxor_w, ALL, gen_am, tcg_gen_atomic_fetch_xor_tl, MO_TESL)
136
-TRANS(amxor_d, ALL, gen_am, tcg_gen_atomic_fetch_xor_tl, MO_TEUQ)
137
-TRANS(ammax_w, ALL, gen_am, tcg_gen_atomic_fetch_smax_tl, MO_TESL)
138
-TRANS(ammax_d, ALL, gen_am, tcg_gen_atomic_fetch_smax_tl, MO_TEUQ)
139
-TRANS(ammin_w, ALL, gen_am, tcg_gen_atomic_fetch_smin_tl, MO_TESL)
140
-TRANS(ammin_d, ALL, gen_am, tcg_gen_atomic_fetch_smin_tl, MO_TEUQ)
141
-TRANS(ammax_wu, ALL, gen_am, tcg_gen_atomic_fetch_umax_tl, MO_TESL)
142
-TRANS(ammax_du, ALL, gen_am, tcg_gen_atomic_fetch_umax_tl, MO_TEUQ)
143
-TRANS(ammin_wu, ALL, gen_am, tcg_gen_atomic_fetch_umin_tl, MO_TESL)
144
-TRANS(ammin_du, ALL, gen_am, tcg_gen_atomic_fetch_umin_tl, MO_TEUQ)
145
-TRANS(amswap_db_w, ALL, gen_am, tcg_gen_atomic_xchg_tl, MO_TESL)
146
-TRANS(amswap_db_d, ALL, gen_am, tcg_gen_atomic_xchg_tl, MO_TEUQ)
147
-TRANS(amadd_db_w, ALL, gen_am, tcg_gen_atomic_fetch_add_tl, MO_TESL)
148
-TRANS(amadd_db_d, ALL, gen_am, tcg_gen_atomic_fetch_add_tl, MO_TEUQ)
149
-TRANS(amand_db_w, ALL, gen_am, tcg_gen_atomic_fetch_and_tl, MO_TESL)
150
-TRANS(amand_db_d, ALL, gen_am, tcg_gen_atomic_fetch_and_tl, MO_TEUQ)
151
-TRANS(amor_db_w, ALL, gen_am, tcg_gen_atomic_fetch_or_tl, MO_TESL)
152
-TRANS(amor_db_d, ALL, gen_am, tcg_gen_atomic_fetch_or_tl, MO_TEUQ)
153
-TRANS(amxor_db_w, ALL, gen_am, tcg_gen_atomic_fetch_xor_tl, MO_TESL)
154
-TRANS(amxor_db_d, ALL, gen_am, tcg_gen_atomic_fetch_xor_tl, MO_TEUQ)
155
-TRANS(ammax_db_w, ALL, gen_am, tcg_gen_atomic_fetch_smax_tl, MO_TESL)
156
-TRANS(ammax_db_d, ALL, gen_am, tcg_gen_atomic_fetch_smax_tl, MO_TEUQ)
157
-TRANS(ammin_db_w, ALL, gen_am, tcg_gen_atomic_fetch_smin_tl, MO_TESL)
158
-TRANS(ammin_db_d, ALL, gen_am, tcg_gen_atomic_fetch_smin_tl, MO_TEUQ)
159
-TRANS(ammax_db_wu, ALL, gen_am, tcg_gen_atomic_fetch_umax_tl, MO_TESL)
160
-TRANS(ammax_db_du, ALL, gen_am, tcg_gen_atomic_fetch_umax_tl, MO_TEUQ)
161
-TRANS(ammin_db_wu, ALL, gen_am, tcg_gen_atomic_fetch_umin_tl, MO_TESL)
162
-TRANS(ammin_db_du, ALL, gen_am, tcg_gen_atomic_fetch_umin_tl, MO_TEUQ)
163
+TRANS(ll_d, 64, gen_ll, MO_TEUQ)
164
+TRANS(sc_d, 64, gen_sc, MO_TEUQ)
165
+TRANS(amswap_w, 64, gen_am, tcg_gen_atomic_xchg_tl, MO_TESL)
166
+TRANS(amswap_d, 64, gen_am, tcg_gen_atomic_xchg_tl, MO_TEUQ)
167
+TRANS(amadd_w, 64, gen_am, tcg_gen_atomic_fetch_add_tl, MO_TESL)
168
+TRANS(amadd_d, 64, gen_am, tcg_gen_atomic_fetch_add_tl, MO_TEUQ)
169
+TRANS(amand_w, 64, gen_am, tcg_gen_atomic_fetch_and_tl, MO_TESL)
170
+TRANS(amand_d, 64, gen_am, tcg_gen_atomic_fetch_and_tl, MO_TEUQ)
171
+TRANS(amor_w, 64, gen_am, tcg_gen_atomic_fetch_or_tl, MO_TESL)
172
+TRANS(amor_d, 64, gen_am, tcg_gen_atomic_fetch_or_tl, MO_TEUQ)
173
+TRANS(amxor_w, 64, gen_am, tcg_gen_atomic_fetch_xor_tl, MO_TESL)
174
+TRANS(amxor_d, 64, gen_am, tcg_gen_atomic_fetch_xor_tl, MO_TEUQ)
175
+TRANS(ammax_w, 64, gen_am, tcg_gen_atomic_fetch_smax_tl, MO_TESL)
176
+TRANS(ammax_d, 64, gen_am, tcg_gen_atomic_fetch_smax_tl, MO_TEUQ)
177
+TRANS(ammin_w, 64, gen_am, tcg_gen_atomic_fetch_smin_tl, MO_TESL)
178
+TRANS(ammin_d, 64, gen_am, tcg_gen_atomic_fetch_smin_tl, MO_TEUQ)
179
+TRANS(ammax_wu, 64, gen_am, tcg_gen_atomic_fetch_umax_tl, MO_TESL)
180
+TRANS(ammax_du, 64, gen_am, tcg_gen_atomic_fetch_umax_tl, MO_TEUQ)
181
+TRANS(ammin_wu, 64, gen_am, tcg_gen_atomic_fetch_umin_tl, MO_TESL)
182
+TRANS(ammin_du, 64, gen_am, tcg_gen_atomic_fetch_umin_tl, MO_TEUQ)
183
+TRANS(amswap_db_w, 64, gen_am, tcg_gen_atomic_xchg_tl, MO_TESL)
184
+TRANS(amswap_db_d, 64, gen_am, tcg_gen_atomic_xchg_tl, MO_TEUQ)
185
+TRANS(amadd_db_w, 64, gen_am, tcg_gen_atomic_fetch_add_tl, MO_TESL)
186
+TRANS(amadd_db_d, 64, gen_am, tcg_gen_atomic_fetch_add_tl, MO_TEUQ)
187
+TRANS(amand_db_w, 64, gen_am, tcg_gen_atomic_fetch_and_tl, MO_TESL)
188
+TRANS(amand_db_d, 64, gen_am, tcg_gen_atomic_fetch_and_tl, MO_TEUQ)
189
+TRANS(amor_db_w, 64, gen_am, tcg_gen_atomic_fetch_or_tl, MO_TESL)
190
+TRANS(amor_db_d, 64, gen_am, tcg_gen_atomic_fetch_or_tl, MO_TEUQ)
191
+TRANS(amxor_db_w, 64, gen_am, tcg_gen_atomic_fetch_xor_tl, MO_TESL)
192
+TRANS(amxor_db_d, 64, gen_am, tcg_gen_atomic_fetch_xor_tl, MO_TEUQ)
193
+TRANS(ammax_db_w, 64, gen_am, tcg_gen_atomic_fetch_smax_tl, MO_TESL)
194
+TRANS(ammax_db_d, 64, gen_am, tcg_gen_atomic_fetch_smax_tl, MO_TEUQ)
195
+TRANS(ammin_db_w, 64, gen_am, tcg_gen_atomic_fetch_smin_tl, MO_TESL)
196
+TRANS(ammin_db_d, 64, gen_am, tcg_gen_atomic_fetch_smin_tl, MO_TEUQ)
197
+TRANS(ammax_db_wu, 64, gen_am, tcg_gen_atomic_fetch_umax_tl, MO_TESL)
198
+TRANS(ammax_db_du, 64, gen_am, tcg_gen_atomic_fetch_umax_tl, MO_TEUQ)
199
+TRANS(ammin_db_wu, 64, gen_am, tcg_gen_atomic_fetch_umin_tl, MO_TESL)
200
+TRANS(ammin_db_du, 64, gen_am, tcg_gen_atomic_fetch_umin_tl, MO_TEUQ)
201
diff --git a/target/loongarch/insn_trans/trans_bit.c.inc b/target/loongarch/insn_trans/trans_bit.c.inc
202
index XXXXXXX..XXXXXXX 100644
203
--- a/target/loongarch/insn_trans/trans_bit.c.inc
204
+++ b/target/loongarch/insn_trans/trans_bit.c.inc
205
@@ -XXX,XX +XXX,XX @@ TRANS(clo_w, ALL, gen_rr, EXT_NONE, EXT_NONE, gen_clo_w)
206
TRANS(clz_w, ALL, gen_rr, EXT_ZERO, EXT_NONE, gen_clz_w)
207
TRANS(cto_w, ALL, gen_rr, EXT_NONE, EXT_NONE, gen_cto_w)
208
TRANS(ctz_w, ALL, gen_rr, EXT_NONE, EXT_NONE, gen_ctz_w)
209
-TRANS(clo_d, ALL, gen_rr, EXT_NONE, EXT_NONE, gen_clo_d)
210
-TRANS(clz_d, ALL, gen_rr, EXT_NONE, EXT_NONE, gen_clz_d)
211
-TRANS(cto_d, ALL, gen_rr, EXT_NONE, EXT_NONE, gen_cto_d)
212
-TRANS(ctz_d, ALL, gen_rr, EXT_NONE, EXT_NONE, gen_ctz_d)
213
+TRANS(clo_d, 64, gen_rr, EXT_NONE, EXT_NONE, gen_clo_d)
214
+TRANS(clz_d, 64, gen_rr, EXT_NONE, EXT_NONE, gen_clz_d)
215
+TRANS(cto_d, 64, gen_rr, EXT_NONE, EXT_NONE, gen_cto_d)
216
+TRANS(ctz_d, 64, gen_rr, EXT_NONE, EXT_NONE, gen_ctz_d)
217
TRANS(revb_2h, ALL, gen_rr, EXT_NONE, EXT_SIGN, gen_revb_2h)
218
-TRANS(revb_4h, ALL, gen_rr, EXT_NONE, EXT_NONE, gen_revb_4h)
219
-TRANS(revb_2w, ALL, gen_rr, EXT_NONE, EXT_NONE, gen_revb_2w)
220
-TRANS(revb_d, ALL, gen_rr, EXT_NONE, EXT_NONE, tcg_gen_bswap64_i64)
221
-TRANS(revh_2w, ALL, gen_rr, EXT_NONE, EXT_NONE, gen_revh_2w)
222
-TRANS(revh_d, ALL, gen_rr, EXT_NONE, EXT_NONE, gen_revh_d)
223
+TRANS(revb_4h, 64, gen_rr, EXT_NONE, EXT_NONE, gen_revb_4h)
224
+TRANS(revb_2w, 64, gen_rr, EXT_NONE, EXT_NONE, gen_revb_2w)
225
+TRANS(revb_d, 64, gen_rr, EXT_NONE, EXT_NONE, tcg_gen_bswap64_i64)
226
+TRANS(revh_2w, 64, gen_rr, EXT_NONE, EXT_NONE, gen_revh_2w)
227
+TRANS(revh_d, 64, gen_rr, EXT_NONE, EXT_NONE, gen_revh_d)
228
TRANS(bitrev_4b, ALL, gen_rr, EXT_ZERO, EXT_SIGN, gen_helper_bitswap)
229
-TRANS(bitrev_8b, ALL, gen_rr, EXT_NONE, EXT_NONE, gen_helper_bitswap)
230
+TRANS(bitrev_8b, 64, gen_rr, EXT_NONE, EXT_NONE, gen_helper_bitswap)
231
TRANS(bitrev_w, ALL, gen_rr, EXT_NONE, EXT_SIGN, gen_helper_bitrev_w)
232
-TRANS(bitrev_d, ALL, gen_rr, EXT_NONE, EXT_NONE, gen_helper_bitrev_d)
233
+TRANS(bitrev_d, 64, gen_rr, EXT_NONE, EXT_NONE, gen_helper_bitrev_d)
234
TRANS(maskeqz, ALL, gen_rrr, EXT_NONE, EXT_NONE, EXT_NONE, gen_maskeqz)
235
TRANS(masknez, ALL, gen_rrr, EXT_NONE, EXT_NONE, EXT_NONE, gen_masknez)
236
TRANS(bytepick_w, ALL, gen_rrr_sa, EXT_NONE, EXT_NONE, gen_bytepick_w)
237
-TRANS(bytepick_d, ALL, gen_rrr_sa, EXT_NONE, EXT_NONE, gen_bytepick_d)
238
+TRANS(bytepick_d, 64, gen_rrr_sa, EXT_NONE, EXT_NONE, gen_bytepick_d)
239
TRANS(bstrins_w, ALL, gen_bstrins, EXT_SIGN)
240
-TRANS(bstrins_d, ALL, gen_bstrins, EXT_NONE)
241
+TRANS(bstrins_d, 64, gen_bstrins, EXT_NONE)
242
TRANS(bstrpick_w, ALL, gen_bstrpick, EXT_SIGN)
243
-TRANS(bstrpick_d, ALL, gen_bstrpick, EXT_NONE)
244
+TRANS(bstrpick_d, 64, gen_bstrpick, EXT_NONE)
245
diff --git a/target/loongarch/insn_trans/trans_branch.c.inc b/target/loongarch/insn_trans/trans_branch.c.inc
246
index XXXXXXX..XXXXXXX 100644
247
--- a/target/loongarch/insn_trans/trans_branch.c.inc
248
+++ b/target/loongarch/insn_trans/trans_branch.c.inc
249
@@ -XXX,XX +XXX,XX @@ TRANS(bltu, ALL, gen_rr_bc, TCG_COND_LTU)
250
TRANS(bgeu, ALL, gen_rr_bc, TCG_COND_GEU)
251
TRANS(beqz, ALL, gen_rz_bc, TCG_COND_EQ)
252
TRANS(bnez, ALL, gen_rz_bc, TCG_COND_NE)
253
-TRANS(bceqz, ALL, gen_cz_bc, TCG_COND_EQ)
254
-TRANS(bcnez, ALL, gen_cz_bc, TCG_COND_NE)
255
+TRANS(bceqz, 64, gen_cz_bc, TCG_COND_EQ)
256
+TRANS(bcnez, 64, gen_cz_bc, TCG_COND_NE)
257
diff --git a/target/loongarch/insn_trans/trans_extra.c.inc b/target/loongarch/insn_trans/trans_extra.c.inc
258
index XXXXXXX..XXXXXXX 100644
259
--- a/target/loongarch/insn_trans/trans_extra.c.inc
260
+++ b/target/loongarch/insn_trans/trans_extra.c.inc
261
@@ -XXX,XX +XXX,XX @@ static bool trans_asrtle_d(DisasContext *ctx, arg_asrtle_d * a)
262
TCGv src1 = gpr_src(ctx, a->rj, EXT_NONE);
263
TCGv src2 = gpr_src(ctx, a->rk, EXT_NONE);
264
265
+ if (!avail_64(ctx)) {
266
+ return false;
267
+ }
268
+
269
gen_helper_asrtle_d(cpu_env, src1, src2);
270
return true;
271
}
272
@@ -XXX,XX +XXX,XX @@ static bool trans_asrtgt_d(DisasContext *ctx, arg_asrtgt_d * a)
273
TCGv src1 = gpr_src(ctx, a->rj, EXT_NONE);
274
TCGv src2 = gpr_src(ctx, a->rk, EXT_NONE);
275
276
+ if (!avail_64(ctx)) {
277
+ return false;
278
+ }
279
+
280
gen_helper_asrtgt_d(cpu_env, src1, src2);
281
return true;
282
}
283
@@ -XXX,XX +XXX,XX @@ static bool gen_crc(DisasContext *ctx, arg_rrr *a,
284
return true;
285
}
286
287
-TRANS(crc_w_b_w, ALL, gen_crc, gen_helper_crc32, tcg_constant_tl(1))
288
-TRANS(crc_w_h_w, ALL, gen_crc, gen_helper_crc32, tcg_constant_tl(2))
289
-TRANS(crc_w_w_w, ALL, gen_crc, gen_helper_crc32, tcg_constant_tl(4))
290
-TRANS(crc_w_d_w, ALL, gen_crc, gen_helper_crc32, tcg_constant_tl(8))
291
-TRANS(crcc_w_b_w, ALL, gen_crc, gen_helper_crc32c, tcg_constant_tl(1))
292
-TRANS(crcc_w_h_w, ALL, gen_crc, gen_helper_crc32c, tcg_constant_tl(2))
293
-TRANS(crcc_w_w_w, ALL, gen_crc, gen_helper_crc32c, tcg_constant_tl(4))
294
-TRANS(crcc_w_d_w, ALL, gen_crc, gen_helper_crc32c, tcg_constant_tl(8))
295
+TRANS(crc_w_b_w, 64, gen_crc, gen_helper_crc32, tcg_constant_tl(1))
296
+TRANS(crc_w_h_w, 64, gen_crc, gen_helper_crc32, tcg_constant_tl(2))
297
+TRANS(crc_w_w_w, 64, gen_crc, gen_helper_crc32, tcg_constant_tl(4))
298
+TRANS(crc_w_d_w, 64, gen_crc, gen_helper_crc32, tcg_constant_tl(8))
299
+TRANS(crcc_w_b_w, 64, gen_crc, gen_helper_crc32c, tcg_constant_tl(1))
300
+TRANS(crcc_w_h_w, 64, gen_crc, gen_helper_crc32c, tcg_constant_tl(2))
301
+TRANS(crcc_w_w_w, 64, gen_crc, gen_helper_crc32c, tcg_constant_tl(4))
302
+TRANS(crcc_w_d_w, 64, gen_crc, gen_helper_crc32c, tcg_constant_tl(8))
303
diff --git a/target/loongarch/insn_trans/trans_fmov.c.inc b/target/loongarch/insn_trans/trans_fmov.c.inc
304
index XXXXXXX..XXXXXXX 100644
305
--- a/target/loongarch/insn_trans/trans_fmov.c.inc
306
+++ b/target/loongarch/insn_trans/trans_fmov.c.inc
307
@@ -XXX,XX +XXX,XX @@ static bool trans_movcf2gr(DisasContext *ctx, arg_movcf2gr *a)
308
TRANS(fmov_s, ALL, gen_f2f, tcg_gen_mov_tl, true)
309
TRANS(fmov_d, ALL, gen_f2f, tcg_gen_mov_tl, false)
310
TRANS(movgr2fr_w, ALL, gen_r2f, gen_movgr2fr_w)
311
-TRANS(movgr2fr_d, ALL, gen_r2f, tcg_gen_mov_tl)
312
+TRANS(movgr2fr_d, 64, gen_r2f, tcg_gen_mov_tl)
313
TRANS(movgr2frh_w, ALL, gen_r2f, gen_movgr2frh_w)
314
TRANS(movfr2gr_s, ALL, gen_f2r, tcg_gen_ext32s_tl)
315
-TRANS(movfr2gr_d, ALL, gen_f2r, tcg_gen_mov_tl)
316
+TRANS(movfr2gr_d, 64, gen_f2r, tcg_gen_mov_tl)
317
TRANS(movfrh2gr_s, ALL, gen_f2r, gen_movfrh2gr_s)
318
diff --git a/target/loongarch/insn_trans/trans_memory.c.inc b/target/loongarch/insn_trans/trans_memory.c.inc
319
index XXXXXXX..XXXXXXX 100644
320
--- a/target/loongarch/insn_trans/trans_memory.c.inc
321
+++ b/target/loongarch/insn_trans/trans_memory.c.inc
322
@@ -XXX,XX +XXX,XX @@ static bool gen_stptr(DisasContext *ctx, arg_rr_i *a, MemOp mop)
323
TRANS(ld_b, ALL, gen_load, MO_SB)
324
TRANS(ld_h, ALL, gen_load, MO_TESW)
325
TRANS(ld_w, ALL, gen_load, MO_TESL)
326
-TRANS(ld_d, ALL, gen_load, MO_TEUQ)
327
+TRANS(ld_d, 64, gen_load, MO_TEUQ)
328
TRANS(st_b, ALL, gen_store, MO_UB)
329
TRANS(st_h, ALL, gen_store, MO_TEUW)
330
TRANS(st_w, ALL, gen_store, MO_TEUL)
331
-TRANS(st_d, ALL, gen_store, MO_TEUQ)
332
+TRANS(st_d, 64, gen_store, MO_TEUQ)
333
TRANS(ld_bu, ALL, gen_load, MO_UB)
334
TRANS(ld_hu, ALL, gen_load, MO_TEUW)
335
-TRANS(ld_wu, ALL, gen_load, MO_TEUL)
336
-TRANS(ldx_b, ALL, gen_loadx, MO_SB)
337
-TRANS(ldx_h, ALL, gen_loadx, MO_TESW)
338
-TRANS(ldx_w, ALL, gen_loadx, MO_TESL)
339
-TRANS(ldx_d, ALL, gen_loadx, MO_TEUQ)
340
-TRANS(stx_b, ALL, gen_storex, MO_UB)
341
-TRANS(stx_h, ALL, gen_storex, MO_TEUW)
342
-TRANS(stx_w, ALL, gen_storex, MO_TEUL)
343
-TRANS(stx_d, ALL, gen_storex, MO_TEUQ)
344
-TRANS(ldx_bu, ALL, gen_loadx, MO_UB)
345
-TRANS(ldx_hu, ALL, gen_loadx, MO_TEUW)
346
-TRANS(ldx_wu, ALL, gen_loadx, MO_TEUL)
347
-TRANS(ldptr_w, ALL, gen_ldptr, MO_TESL)
348
-TRANS(stptr_w, ALL, gen_stptr, MO_TEUL)
349
-TRANS(ldptr_d, ALL, gen_ldptr, MO_TEUQ)
350
-TRANS(stptr_d, ALL, gen_stptr, MO_TEUQ)
351
-TRANS(ldgt_b, ALL, gen_load_gt, MO_SB)
352
-TRANS(ldgt_h, ALL, gen_load_gt, MO_TESW)
353
-TRANS(ldgt_w, ALL, gen_load_gt, MO_TESL)
354
-TRANS(ldgt_d, ALL, gen_load_gt, MO_TEUQ)
355
-TRANS(ldle_b, ALL, gen_load_le, MO_SB)
356
-TRANS(ldle_h, ALL, gen_load_le, MO_TESW)
357
-TRANS(ldle_w, ALL, gen_load_le, MO_TESL)
358
-TRANS(ldle_d, ALL, gen_load_le, MO_TEUQ)
359
-TRANS(stgt_b, ALL, gen_store_gt, MO_UB)
360
-TRANS(stgt_h, ALL, gen_store_gt, MO_TEUW)
361
-TRANS(stgt_w, ALL, gen_store_gt, MO_TEUL)
362
-TRANS(stgt_d, ALL, gen_store_gt, MO_TEUQ)
363
-TRANS(stle_b, ALL, gen_store_le, MO_UB)
364
-TRANS(stle_h, ALL, gen_store_le, MO_TEUW)
365
-TRANS(stle_w, ALL, gen_store_le, MO_TEUL)
366
-TRANS(stle_d, ALL, gen_store_le, MO_TEUQ)
367
+TRANS(ld_wu, 64, gen_load, MO_TEUL)
368
+TRANS(ldx_b, 64, gen_loadx, MO_SB)
369
+TRANS(ldx_h, 64, gen_loadx, MO_TESW)
370
+TRANS(ldx_w, 64, gen_loadx, MO_TESL)
371
+TRANS(ldx_d, 64, gen_loadx, MO_TEUQ)
372
+TRANS(stx_b, 64, gen_storex, MO_UB)
373
+TRANS(stx_h, 64, gen_storex, MO_TEUW)
374
+TRANS(stx_w, 64, gen_storex, MO_TEUL)
375
+TRANS(stx_d, 64, gen_storex, MO_TEUQ)
376
+TRANS(ldx_bu, 64, gen_loadx, MO_UB)
377
+TRANS(ldx_hu, 64, gen_loadx, MO_TEUW)
378
+TRANS(ldx_wu, 64, gen_loadx, MO_TEUL)
379
+TRANS(ldptr_w, 64, gen_ldptr, MO_TESL)
380
+TRANS(stptr_w, 64, gen_stptr, MO_TEUL)
381
+TRANS(ldptr_d, 64, gen_ldptr, MO_TEUQ)
382
+TRANS(stptr_d, 64, gen_stptr, MO_TEUQ)
383
+TRANS(ldgt_b, 64, gen_load_gt, MO_SB)
384
+TRANS(ldgt_h, 64, gen_load_gt, MO_TESW)
385
+TRANS(ldgt_w, 64, gen_load_gt, MO_TESL)
386
+TRANS(ldgt_d, 64, gen_load_gt, MO_TEUQ)
387
+TRANS(ldle_b, 64, gen_load_le, MO_SB)
388
+TRANS(ldle_h, 64, gen_load_le, MO_TESW)
389
+TRANS(ldle_w, 64, gen_load_le, MO_TESL)
390
+TRANS(ldle_d, 64, gen_load_le, MO_TEUQ)
391
+TRANS(stgt_b, 64, gen_store_gt, MO_UB)
392
+TRANS(stgt_h, 64, gen_store_gt, MO_TEUW)
393
+TRANS(stgt_w, 64, gen_store_gt, MO_TEUL)
394
+TRANS(stgt_d, 64, gen_store_gt, MO_TEUQ)
395
+TRANS(stle_b, 64, gen_store_le, MO_UB)
396
+TRANS(stle_h, 64, gen_store_le, MO_TEUW)
397
+TRANS(stle_w, 64, gen_store_le, MO_TEUL)
398
+TRANS(stle_d, 64, gen_store_le, MO_TEUQ)
399
diff --git a/target/loongarch/insn_trans/trans_shift.c.inc b/target/loongarch/insn_trans/trans_shift.c.inc
400
index XXXXXXX..XXXXXXX 100644
401
--- a/target/loongarch/insn_trans/trans_shift.c.inc
402
+++ b/target/loongarch/insn_trans/trans_shift.c.inc
403
@@ -XXX,XX +XXX,XX @@ static bool trans_srai_w(DisasContext *ctx, arg_srai_w *a)
404
TCGv dest = gpr_dst(ctx, a->rd, EXT_NONE);
405
TCGv src1 = gpr_src(ctx, a->rj, EXT_ZERO);
406
407
+ if (!avail_64(ctx)) {
408
+ return false;
409
+ }
410
+
411
tcg_gen_sextract_tl(dest, src1, a->imm, 32 - a->imm);
412
gen_set_gpr(a->rd, dest, EXT_NONE);
413
414
@@ -XXX,XX +XXX,XX @@ static bool trans_srai_w(DisasContext *ctx, arg_srai_w *a)
415
TRANS(sll_w, ALL, gen_rrr, EXT_ZERO, EXT_NONE, EXT_SIGN, gen_sll_w)
416
TRANS(srl_w, ALL, gen_rrr, EXT_ZERO, EXT_NONE, EXT_SIGN, gen_srl_w)
417
TRANS(sra_w, ALL, gen_rrr, EXT_SIGN, EXT_NONE, EXT_SIGN, gen_sra_w)
418
-TRANS(sll_d, ALL, gen_rrr, EXT_NONE, EXT_NONE, EXT_NONE, gen_sll_d)
419
-TRANS(srl_d, ALL, gen_rrr, EXT_NONE, EXT_NONE, EXT_NONE, gen_srl_d)
420
-TRANS(sra_d, ALL, gen_rrr, EXT_NONE, EXT_NONE, EXT_NONE, gen_sra_d)
421
-TRANS(rotr_w, ALL, gen_rrr, EXT_ZERO, EXT_NONE, EXT_SIGN, gen_rotr_w)
422
-TRANS(rotr_d, ALL, gen_rrr, EXT_NONE, EXT_NONE, EXT_NONE, gen_rotr_d)
423
+TRANS(sll_d, 64, gen_rrr, EXT_NONE, EXT_NONE, EXT_NONE, gen_sll_d)
424
+TRANS(srl_d, 64, gen_rrr, EXT_NONE, EXT_NONE, EXT_NONE, gen_srl_d)
425
+TRANS(sra_d, 64, gen_rrr, EXT_NONE, EXT_NONE, EXT_NONE, gen_sra_d)
426
+TRANS(rotr_w, 64, gen_rrr, EXT_ZERO, EXT_NONE, EXT_SIGN, gen_rotr_w)
427
+TRANS(rotr_d, 64, gen_rrr, EXT_NONE, EXT_NONE, EXT_NONE, gen_rotr_d)
428
TRANS(slli_w, ALL, gen_rri_c, EXT_NONE, EXT_SIGN, tcg_gen_shli_tl)
429
-TRANS(slli_d, ALL, gen_rri_c, EXT_NONE, EXT_NONE, tcg_gen_shli_tl)
430
+TRANS(slli_d, 64, gen_rri_c, EXT_NONE, EXT_NONE, tcg_gen_shli_tl)
431
TRANS(srli_w, ALL, gen_rri_c, EXT_ZERO, EXT_SIGN, tcg_gen_shri_tl)
432
-TRANS(srli_d, ALL, gen_rri_c, EXT_NONE, EXT_NONE, tcg_gen_shri_tl)
433
-TRANS(srai_d, ALL, gen_rri_c, EXT_NONE, EXT_NONE, tcg_gen_sari_tl)
434
-TRANS(rotri_w, ALL, gen_rri_v, EXT_NONE, EXT_NONE, gen_rotr_w)
435
-TRANS(rotri_d, ALL, gen_rri_c, EXT_NONE, EXT_NONE, tcg_gen_rotri_tl)
436
+TRANS(srli_d, 64, gen_rri_c, EXT_NONE, EXT_NONE, tcg_gen_shri_tl)
437
+TRANS(srai_d, 64, gen_rri_c, EXT_NONE, EXT_NONE, tcg_gen_sari_tl)
438
+TRANS(rotri_w, 64, gen_rri_v, EXT_NONE, EXT_NONE, gen_rotr_w)
439
+TRANS(rotri_d, 64, gen_rri_c, EXT_NONE, EXT_NONE, tcg_gen_rotri_tl)
440
diff --git a/target/loongarch/translate.c b/target/loongarch/translate.c
441
index XXXXXXX..XXXXXXX 100644
442
--- a/target/loongarch/translate.c
443
+++ b/target/loongarch/translate.c
444
@@ -XXX,XX +XXX,XX @@ static void loongarch_tr_init_disas_context(DisasContextBase *dcbase,
445
ctx->va32 = (ctx->base.tb->flags & HW_FLAGS_VA32) != 0;
446
447
ctx->zero = tcg_constant_tl(0);
448
+
449
+ ctx->cpucfg1 = env->cpucfg[1];
450
}
451
452
static void loongarch_tr_tb_start(DisasContextBase *dcbase, CPUState *cs)
453
diff --git a/target/loongarch/translate.h b/target/loongarch/translate.h
454
index XXXXXXX..XXXXXXX 100644
455
--- a/target/loongarch/translate.h
456
+++ b/target/loongarch/translate.h
457
@@ -XXX,XX +XXX,XX @@
458
{ return avail_##AVAIL(ctx) && FUNC(ctx, a, __VA_ARGS__); }
459
460
#define avail_ALL(C) true
461
+#define avail_64(C) (FIELD_EX32((C)->cpucfg1, CPUCFG1, ARCH) == \
462
+ CPUCFG1_ARCH_LA64)
463
464
/*
465
* If an operation is being performed on less than TARGET_LONG_BITS,
466
@@ -XXX,XX +XXX,XX @@ typedef struct DisasContext {
467
TCGv zero;
468
bool la64; /* LoongArch64 mode */
469
bool va32; /* 32-bit virtual address */
470
+ uint32_t cpucfg1;
471
} DisasContext;
472
473
void generate_exception(DisasContext *ctx, int excp);
474
--
475
2.39.1
diff view generated by jsdifflib
New patch
[PULL 21/31] target/loongarch: Add LoongArch32 cpu la132
1
From: Jiajie Chen <c@jia.je>
1
2
3
Add LoongArch32 cpu la132.
4
5
Due to lack of public documentation of la132, it is currently a
6
synthetic LoongArch32 cpu model. Details need to be added in the future.
7
8
Signed-off-by: Jiajie Chen <c@jia.je>
9
Signed-off-by: Song Gao <gaosong@loongson.cn>
10
Acked-by: Richard Henderson <richard.henderson@linaro.org>
11
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
12
Message-ID: <20230822032724.1353391-10-gaosong@loongson.cn>
13
Message-Id: <20230822071959.35620-4-philmd@linaro.org>
14
---
15
target/loongarch/cpu.c | 30 ++++++++++++++++++++++++++++++
16
1 file changed, 30 insertions(+)
17
18
diff --git a/target/loongarch/cpu.c b/target/loongarch/cpu.c
19
index XXXXXXX..XXXXXXX 100644
20
--- a/target/loongarch/cpu.c
21
+++ b/target/loongarch/cpu.c
22
@@ -XXX,XX +XXX,XX @@ static void loongarch_la464_initfn(Object *obj)
23
env->CSR_ASID = FIELD_DP64(0, CSR_ASID, ASIDBITS, 0xa);
24
}
25
26
+static void loongarch_la132_initfn(Object *obj)
27
+{
28
+ LoongArchCPU *cpu = LOONGARCH_CPU(obj);
29
+ CPULoongArchState *env = &cpu->env;
30
+
31
+ int i;
32
+
33
+ for (i = 0; i < 21; i++) {
34
+ env->cpucfg[i] = 0x0;
35
+ }
36
+
37
+ cpu->dtb_compatible = "loongarch,Loongson-1C103";
38
+ env->cpucfg[0] = 0x148042; /* PRID */
39
+
40
+ uint32_t data = 0;
41
+ data = FIELD_DP32(data, CPUCFG1, ARCH, 1); /* LA32 */
42
+ data = FIELD_DP32(data, CPUCFG1, PGMMU, 1);
43
+ data = FIELD_DP32(data, CPUCFG1, IOCSR, 1);
44
+ data = FIELD_DP32(data, CPUCFG1, PALEN, 0x1f); /* 32 bits */
45
+ data = FIELD_DP32(data, CPUCFG1, VALEN, 0x1f); /* 32 bits */
46
+ data = FIELD_DP32(data, CPUCFG1, UAL, 1);
47
+ data = FIELD_DP32(data, CPUCFG1, RI, 0);
48
+ data = FIELD_DP32(data, CPUCFG1, EP, 0);
49
+ data = FIELD_DP32(data, CPUCFG1, RPLV, 0);
50
+ data = FIELD_DP32(data, CPUCFG1, HP, 1);
51
+ data = FIELD_DP32(data, CPUCFG1, IOCSR_BRD, 1);
52
+ env->cpucfg[1] = data;
53
+}
54
+
55
static void loongarch_cpu_list_entry(gpointer data, gpointer user_data)
56
{
57
const char *typename = object_class_get_name(OBJECT_CLASS(data));
58
@@ -XXX,XX +XXX,XX @@ static const TypeInfo loongarch_cpu_type_infos[] = {
59
.class_init = loongarch64_cpu_class_init,
60
},
61
DEFINE_LOONGARCH_CPU_TYPE(64, "la464", loongarch_la464_initfn),
62
+ DEFINE_LOONGARCH_CPU_TYPE(32, "la132", loongarch_la132_initfn),
63
};
64
65
DEFINE_TYPES(loongarch_cpu_type_infos)
66
--
67
2.39.1
68
69
diff view generated by jsdifflib
New patch
[PULL 22/31] hw/loongarch: Remove restriction of la464 cores in the virt machine
1
Allow virt machine to be used with la132 instead of la464.
1
2
3
Co-authored-by: Jiajie Chen <c@jia.je>
4
Signed-off-by: Song Gao <gaosong@loongson.cn>
5
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
6
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
7
Message-ID: <20230822032724.1353391-11-gaosong@loongson.cn>
8
Message-Id: <20230822071959.35620-5-philmd@linaro.org>
9
---
10
hw/loongarch/virt.c | 5 -----
11
1 file changed, 5 deletions(-)
12
13
diff --git a/hw/loongarch/virt.c b/hw/loongarch/virt.c
14
index XXXXXXX..XXXXXXX 100644
15
--- a/hw/loongarch/virt.c
16
+++ b/hw/loongarch/virt.c
17
@@ -XXX,XX +XXX,XX @@ static void loongarch_init(MachineState *machine)
18
cpu_model = LOONGARCH_CPU_TYPE_NAME("la464");
19
}
20
21
- if (!strstr(cpu_model, "la464")) {
22
- error_report("LoongArch/TCG needs cpu type la464");
23
- exit(1);
24
- }
25
-
26
if (ram_size < 1 * GiB) {
27
error_report("ram_size must be greater than 1G.");
28
exit(1);
29
--
30
2.39.1
31
32
diff view generated by jsdifflib
New patch
[PULL 23/31] target/loongarch: Add avail_FP/FP_SP/FP_DP to check fpu instructions
1
Signed-off-by: Song Gao <gaosong@loongson.cn>
2
Acked-by: Richard Henderson <richard.henderson@linaro.org>
3
Message-ID: <20230822032724.1353391-12-gaosong@loongson.cn>
4
Message-Id: <20230822071959.35620-6-philmd@linaro.org>
5
---
6
.../loongarch/insn_trans/trans_farith.c.inc | 96 ++++++++++++-------
7
target/loongarch/insn_trans/trans_fcmp.c.inc | 8 ++
8
target/loongarch/insn_trans/trans_fcnv.c.inc | 56 +++++------
9
.../loongarch/insn_trans/trans_fmemory.c.inc | 32 +++----
10
target/loongarch/insn_trans/trans_fmov.c.inc | 48 ++++++++--
11
target/loongarch/translate.c | 1 +
12
target/loongarch/translate.h | 4 +
13
7 files changed, 159 insertions(+), 86 deletions(-)
1
14
15
diff --git a/target/loongarch/insn_trans/trans_farith.c.inc b/target/loongarch/insn_trans/trans_farith.c.inc
16
index XXXXXXX..XXXXXXX 100644
17
--- a/target/loongarch/insn_trans/trans_farith.c.inc
18
+++ b/target/loongarch/insn_trans/trans_farith.c.inc
19
@@ -XXX,XX +XXX,XX @@ static bool trans_fcopysign_s(DisasContext *ctx, arg_fcopysign_s *a)
20
TCGv src1 = get_fpr(ctx, a->fk);
21
TCGv src2 = get_fpr(ctx, a->fj);
22
23
+ if (!avail_FP_SP(ctx)) {
24
+ return false;
25
+ }
26
+
27
CHECK_FPE;
28
29
tcg_gen_deposit_i64(dest, src1, src2, 0, 31);
30
@@ -XXX,XX +XXX,XX @@ static bool trans_fcopysign_d(DisasContext *ctx, arg_fcopysign_d *a)
31
TCGv src1 = get_fpr(ctx, a->fk);
32
TCGv src2 = get_fpr(ctx, a->fj);
33
34
+ if (!avail_FP_DP(ctx)) {
35
+ return false;
36
+ }
37
+
38
CHECK_FPE;
39
40
tcg_gen_deposit_i64(dest, src1, src2, 0, 63);
41
@@ -XXX,XX +XXX,XX @@ static bool trans_fabs_s(DisasContext *ctx, arg_fabs_s *a)
42
TCGv dest = get_fpr(ctx, a->fd);
43
TCGv src = get_fpr(ctx, a->fj);
44
45
+ if (!avail_FP_SP(ctx)) {
46
+ return false;
47
+ }
48
+
49
CHECK_FPE;
50
51
tcg_gen_andi_i64(dest, src, MAKE_64BIT_MASK(0, 31));
52
@@ -XXX,XX +XXX,XX @@ static bool trans_fabs_d(DisasContext *ctx, arg_fabs_d *a)
53
TCGv dest = get_fpr(ctx, a->fd);
54
TCGv src = get_fpr(ctx, a->fj);
55
56
+ if (!avail_FP_DP(ctx)) {
57
+ return false;
58
+ }
59
+
60
CHECK_FPE;
61
62
tcg_gen_andi_i64(dest, src, MAKE_64BIT_MASK(0, 63));
63
@@ -XXX,XX +XXX,XX @@ static bool trans_fneg_s(DisasContext *ctx, arg_fneg_s *a)
64
TCGv dest = get_fpr(ctx, a->fd);
65
TCGv src = get_fpr(ctx, a->fj);
66
67
+ if (!avail_FP_SP(ctx)) {
68
+ return false;
69
+ }
70
+
71
CHECK_FPE;
72
73
tcg_gen_xori_i64(dest, src, 0x80000000);
74
@@ -XXX,XX +XXX,XX @@ static bool trans_fneg_d(DisasContext *ctx, arg_fneg_d *a)
75
TCGv dest = get_fpr(ctx, a->fd);
76
TCGv src = get_fpr(ctx, a->fj);
77
78
+ if (!avail_FP_DP(ctx)) {
79
+ return false;
80
+ }
81
+
82
CHECK_FPE;
83
84
tcg_gen_xori_i64(dest, src, 0x8000000000000000LL);
85
@@ -XXX,XX +XXX,XX @@ static bool trans_fneg_d(DisasContext *ctx, arg_fneg_d *a)
86
return true;
87
}
88
89
-TRANS(fadd_s, ALL, gen_fff, gen_helper_fadd_s)
90
-TRANS(fadd_d, ALL, gen_fff, gen_helper_fadd_d)
91
-TRANS(fsub_s, ALL, gen_fff, gen_helper_fsub_s)
92
-TRANS(fsub_d, ALL, gen_fff, gen_helper_fsub_d)
93
-TRANS(fmul_s, ALL, gen_fff, gen_helper_fmul_s)
94
-TRANS(fmul_d, ALL, gen_fff, gen_helper_fmul_d)
95
-TRANS(fdiv_s, ALL, gen_fff, gen_helper_fdiv_s)
96
-TRANS(fdiv_d, ALL, gen_fff, gen_helper_fdiv_d)
97
-TRANS(fmax_s, ALL, gen_fff, gen_helper_fmax_s)
98
-TRANS(fmax_d, ALL, gen_fff, gen_helper_fmax_d)
99
-TRANS(fmin_s, ALL, gen_fff, gen_helper_fmin_s)
100
-TRANS(fmin_d, ALL, gen_fff, gen_helper_fmin_d)
101
-TRANS(fmaxa_s, ALL, gen_fff, gen_helper_fmaxa_s)
102
-TRANS(fmaxa_d, ALL, gen_fff, gen_helper_fmaxa_d)
103
-TRANS(fmina_s, ALL, gen_fff, gen_helper_fmina_s)
104
-TRANS(fmina_d, ALL, gen_fff, gen_helper_fmina_d)
105
-TRANS(fscaleb_s, ALL, gen_fff, gen_helper_fscaleb_s)
106
-TRANS(fscaleb_d, ALL, gen_fff, gen_helper_fscaleb_d)
107
-TRANS(fsqrt_s, ALL, gen_ff, gen_helper_fsqrt_s)
108
-TRANS(fsqrt_d, ALL, gen_ff, gen_helper_fsqrt_d)
109
-TRANS(frecip_s, ALL, gen_ff, gen_helper_frecip_s)
110
-TRANS(frecip_d, ALL, gen_ff, gen_helper_frecip_d)
111
-TRANS(frsqrt_s, ALL, gen_ff, gen_helper_frsqrt_s)
112
-TRANS(frsqrt_d, ALL, gen_ff, gen_helper_frsqrt_d)
113
-TRANS(flogb_s, ALL, gen_ff, gen_helper_flogb_s)
114
-TRANS(flogb_d, ALL, gen_ff, gen_helper_flogb_d)
115
-TRANS(fclass_s, ALL, gen_ff, gen_helper_fclass_s)
116
-TRANS(fclass_d, ALL, gen_ff, gen_helper_fclass_d)
117
-TRANS(fmadd_s, ALL, gen_muladd, gen_helper_fmuladd_s, 0)
118
-TRANS(fmadd_d, ALL, gen_muladd, gen_helper_fmuladd_d, 0)
119
-TRANS(fmsub_s, ALL, gen_muladd, gen_helper_fmuladd_s, float_muladd_negate_c)
120
-TRANS(fmsub_d, ALL, gen_muladd, gen_helper_fmuladd_d, float_muladd_negate_c)
121
-TRANS(fnmadd_s, ALL, gen_muladd, gen_helper_fmuladd_s, float_muladd_negate_result)
122
-TRANS(fnmadd_d, ALL, gen_muladd, gen_helper_fmuladd_d, float_muladd_negate_result)
123
-TRANS(fnmsub_s, ALL, gen_muladd, gen_helper_fmuladd_s,
124
+TRANS(fadd_s, FP_SP, gen_fff, gen_helper_fadd_s)
125
+TRANS(fadd_d, FP_DP, gen_fff, gen_helper_fadd_d)
126
+TRANS(fsub_s, FP_SP, gen_fff, gen_helper_fsub_s)
127
+TRANS(fsub_d, FP_DP, gen_fff, gen_helper_fsub_d)
128
+TRANS(fmul_s, FP_SP, gen_fff, gen_helper_fmul_s)
129
+TRANS(fmul_d, FP_DP, gen_fff, gen_helper_fmul_d)
130
+TRANS(fdiv_s, FP_SP, gen_fff, gen_helper_fdiv_s)
131
+TRANS(fdiv_d, FP_DP, gen_fff, gen_helper_fdiv_d)
132
+TRANS(fmax_s, FP_SP, gen_fff, gen_helper_fmax_s)
133
+TRANS(fmax_d, FP_DP, gen_fff, gen_helper_fmax_d)
134
+TRANS(fmin_s, FP_SP, gen_fff, gen_helper_fmin_s)
135
+TRANS(fmin_d, FP_DP, gen_fff, gen_helper_fmin_d)
136
+TRANS(fmaxa_s, FP_SP, gen_fff, gen_helper_fmaxa_s)
137
+TRANS(fmaxa_d, FP_DP, gen_fff, gen_helper_fmaxa_d)
138
+TRANS(fmina_s, FP_SP, gen_fff, gen_helper_fmina_s)
139
+TRANS(fmina_d, FP_DP, gen_fff, gen_helper_fmina_d)
140
+TRANS(fscaleb_s, FP_SP, gen_fff, gen_helper_fscaleb_s)
141
+TRANS(fscaleb_d, FP_DP, gen_fff, gen_helper_fscaleb_d)
142
+TRANS(fsqrt_s, FP_SP, gen_ff, gen_helper_fsqrt_s)
143
+TRANS(fsqrt_d, FP_DP, gen_ff, gen_helper_fsqrt_d)
144
+TRANS(frecip_s, FP_SP, gen_ff, gen_helper_frecip_s)
145
+TRANS(frecip_d, FP_DP, gen_ff, gen_helper_frecip_d)
146
+TRANS(frsqrt_s, FP_SP, gen_ff, gen_helper_frsqrt_s)
147
+TRANS(frsqrt_d, FP_DP, gen_ff, gen_helper_frsqrt_d)
148
+TRANS(flogb_s, FP_SP, gen_ff, gen_helper_flogb_s)
149
+TRANS(flogb_d, FP_DP, gen_ff, gen_helper_flogb_d)
150
+TRANS(fclass_s, FP_SP, gen_ff, gen_helper_fclass_s)
151
+TRANS(fclass_d, FP_DP, gen_ff, gen_helper_fclass_d)
152
+TRANS(fmadd_s, FP_SP, gen_muladd, gen_helper_fmuladd_s, 0)
153
+TRANS(fmadd_d, FP_DP, gen_muladd, gen_helper_fmuladd_d, 0)
154
+TRANS(fmsub_s, FP_SP, gen_muladd, gen_helper_fmuladd_s, float_muladd_negate_c)
155
+TRANS(fmsub_d, FP_DP, gen_muladd, gen_helper_fmuladd_d, float_muladd_negate_c)
156
+TRANS(fnmadd_s, FP_SP, gen_muladd, gen_helper_fmuladd_s, float_muladd_negate_result)
157
+TRANS(fnmadd_d, FP_DP, gen_muladd, gen_helper_fmuladd_d, float_muladd_negate_result)
158
+TRANS(fnmsub_s, FP_SP, gen_muladd, gen_helper_fmuladd_s,
159
float_muladd_negate_c | float_muladd_negate_result)
160
-TRANS(fnmsub_d, ALL, gen_muladd, gen_helper_fmuladd_d,
161
+TRANS(fnmsub_d, FP_DP, gen_muladd, gen_helper_fmuladd_d,
162
float_muladd_negate_c | float_muladd_negate_result)
163
diff --git a/target/loongarch/insn_trans/trans_fcmp.c.inc b/target/loongarch/insn_trans/trans_fcmp.c.inc
164
index XXXXXXX..XXXXXXX 100644
165
--- a/target/loongarch/insn_trans/trans_fcmp.c.inc
166
+++ b/target/loongarch/insn_trans/trans_fcmp.c.inc
167
@@ -XXX,XX +XXX,XX @@ static bool trans_fcmp_cond_s(DisasContext *ctx, arg_fcmp_cond_s *a)
168
uint32_t flags;
169
void (*fn)(TCGv, TCGv_env, TCGv, TCGv, TCGv_i32);
170
171
+ if (!avail_FP_SP(ctx)) {
172
+ return false;
173
+ }
174
+
175
CHECK_FPE;
176
177
var = tcg_temp_new();
178
@@ -XXX,XX +XXX,XX @@ static bool trans_fcmp_cond_d(DisasContext *ctx, arg_fcmp_cond_d *a)
179
uint32_t flags;
180
void (*fn)(TCGv, TCGv_env, TCGv, TCGv, TCGv_i32);
181
182
+ if (!avail_FP_DP(ctx)) {
183
+ return false;
184
+ }
185
+
186
CHECK_FPE;
187
188
var = tcg_temp_new();
189
diff --git a/target/loongarch/insn_trans/trans_fcnv.c.inc b/target/loongarch/insn_trans/trans_fcnv.c.inc
190
index XXXXXXX..XXXXXXX 100644
191
--- a/target/loongarch/insn_trans/trans_fcnv.c.inc
192
+++ b/target/loongarch/insn_trans/trans_fcnv.c.inc
193
@@ -XXX,XX +XXX,XX @@
194
* Copyright (c) 2021 Loongson Technology Corporation Limited
195
*/
196
197
-TRANS(fcvt_s_d, ALL, gen_ff, gen_helper_fcvt_s_d)
198
-TRANS(fcvt_d_s, ALL, gen_ff, gen_helper_fcvt_d_s)
199
-TRANS(ftintrm_w_s, ALL, gen_ff, gen_helper_ftintrm_w_s)
200
-TRANS(ftintrm_w_d, ALL, gen_ff, gen_helper_ftintrm_w_d)
201
-TRANS(ftintrm_l_s, ALL, gen_ff, gen_helper_ftintrm_l_s)
202
-TRANS(ftintrm_l_d, ALL, gen_ff, gen_helper_ftintrm_l_d)
203
-TRANS(ftintrp_w_s, ALL, gen_ff, gen_helper_ftintrp_w_s)
204
-TRANS(ftintrp_w_d, ALL, gen_ff, gen_helper_ftintrp_w_d)
205
-TRANS(ftintrp_l_s, ALL, gen_ff, gen_helper_ftintrp_l_s)
206
-TRANS(ftintrp_l_d, ALL, gen_ff, gen_helper_ftintrp_l_d)
207
-TRANS(ftintrz_w_s, ALL, gen_ff, gen_helper_ftintrz_w_s)
208
-TRANS(ftintrz_w_d, ALL, gen_ff, gen_helper_ftintrz_w_d)
209
-TRANS(ftintrz_l_s, ALL, gen_ff, gen_helper_ftintrz_l_s)
210
-TRANS(ftintrz_l_d, ALL, gen_ff, gen_helper_ftintrz_l_d)
211
-TRANS(ftintrne_w_s, ALL, gen_ff, gen_helper_ftintrne_w_s)
212
-TRANS(ftintrne_w_d, ALL, gen_ff, gen_helper_ftintrne_w_d)
213
-TRANS(ftintrne_l_s, ALL, gen_ff, gen_helper_ftintrne_l_s)
214
-TRANS(ftintrne_l_d, ALL, gen_ff, gen_helper_ftintrne_l_d)
215
-TRANS(ftint_w_s, ALL, gen_ff, gen_helper_ftint_w_s)
216
-TRANS(ftint_w_d, ALL, gen_ff, gen_helper_ftint_w_d)
217
-TRANS(ftint_l_s, ALL, gen_ff, gen_helper_ftint_l_s)
218
-TRANS(ftint_l_d, ALL, gen_ff, gen_helper_ftint_l_d)
219
-TRANS(ffint_s_w, ALL, gen_ff, gen_helper_ffint_s_w)
220
-TRANS(ffint_s_l, ALL, gen_ff, gen_helper_ffint_s_l)
221
-TRANS(ffint_d_w, ALL, gen_ff, gen_helper_ffint_d_w)
222
-TRANS(ffint_d_l, ALL, gen_ff, gen_helper_ffint_d_l)
223
-TRANS(frint_s, ALL, gen_ff, gen_helper_frint_s)
224
-TRANS(frint_d, ALL, gen_ff, gen_helper_frint_d)
225
+TRANS(fcvt_s_d, FP_DP, gen_ff, gen_helper_fcvt_s_d)
226
+TRANS(fcvt_d_s, FP_DP, gen_ff, gen_helper_fcvt_d_s)
227
+TRANS(ftintrm_w_s, FP_SP, gen_ff, gen_helper_ftintrm_w_s)
228
+TRANS(ftintrm_w_d, FP_DP, gen_ff, gen_helper_ftintrm_w_d)
229
+TRANS(ftintrm_l_s, FP_SP, gen_ff, gen_helper_ftintrm_l_s)
230
+TRANS(ftintrm_l_d, FP_DP, gen_ff, gen_helper_ftintrm_l_d)
231
+TRANS(ftintrp_w_s, FP_SP, gen_ff, gen_helper_ftintrp_w_s)
232
+TRANS(ftintrp_w_d, FP_DP, gen_ff, gen_helper_ftintrp_w_d)
233
+TRANS(ftintrp_l_s, FP_SP, gen_ff, gen_helper_ftintrp_l_s)
234
+TRANS(ftintrp_l_d, FP_DP, gen_ff, gen_helper_ftintrp_l_d)
235
+TRANS(ftintrz_w_s, FP_SP, gen_ff, gen_helper_ftintrz_w_s)
236
+TRANS(ftintrz_w_d, FP_DP, gen_ff, gen_helper_ftintrz_w_d)
237
+TRANS(ftintrz_l_s, FP_SP, gen_ff, gen_helper_ftintrz_l_s)
238
+TRANS(ftintrz_l_d, FP_DP, gen_ff, gen_helper_ftintrz_l_d)
239
+TRANS(ftintrne_w_s, FP_SP, gen_ff, gen_helper_ftintrne_w_s)
240
+TRANS(ftintrne_w_d, FP_DP, gen_ff, gen_helper_ftintrne_w_d)
241
+TRANS(ftintrne_l_s, FP_SP, gen_ff, gen_helper_ftintrne_l_s)
242
+TRANS(ftintrne_l_d, FP_DP, gen_ff, gen_helper_ftintrne_l_d)
243
+TRANS(ftint_w_s, FP_SP, gen_ff, gen_helper_ftint_w_s)
244
+TRANS(ftint_w_d, FP_DP, gen_ff, gen_helper_ftint_w_d)
245
+TRANS(ftint_l_s, FP_SP, gen_ff, gen_helper_ftint_l_s)
246
+TRANS(ftint_l_d, FP_DP, gen_ff, gen_helper_ftint_l_d)
247
+TRANS(ffint_s_w, FP_SP, gen_ff, gen_helper_ffint_s_w)
248
+TRANS(ffint_s_l, FP_SP, gen_ff, gen_helper_ffint_s_l)
249
+TRANS(ffint_d_w, FP_DP, gen_ff, gen_helper_ffint_d_w)
250
+TRANS(ffint_d_l, FP_DP, gen_ff, gen_helper_ffint_d_l)
251
+TRANS(frint_s, FP_SP, gen_ff, gen_helper_frint_s)
252
+TRANS(frint_d, FP_DP, gen_ff, gen_helper_frint_d)
253
diff --git a/target/loongarch/insn_trans/trans_fmemory.c.inc b/target/loongarch/insn_trans/trans_fmemory.c.inc
254
index XXXXXXX..XXXXXXX 100644
255
--- a/target/loongarch/insn_trans/trans_fmemory.c.inc
256
+++ b/target/loongarch/insn_trans/trans_fmemory.c.inc
257
@@ -XXX,XX +XXX,XX @@ static bool gen_fstore_le(DisasContext *ctx, arg_frr *a, MemOp mop)
258
return true;
259
}
260
261
-TRANS(fld_s, ALL, gen_fload_i, MO_TEUL)
262
-TRANS(fst_s, ALL, gen_fstore_i, MO_TEUL)
263
-TRANS(fld_d, ALL, gen_fload_i, MO_TEUQ)
264
-TRANS(fst_d, ALL, gen_fstore_i, MO_TEUQ)
265
-TRANS(fldx_s, ALL, gen_floadx, MO_TEUL)
266
-TRANS(fldx_d, ALL, gen_floadx, MO_TEUQ)
267
-TRANS(fstx_s, ALL, gen_fstorex, MO_TEUL)
268
-TRANS(fstx_d, ALL, gen_fstorex, MO_TEUQ)
269
-TRANS(fldgt_s, ALL, gen_fload_gt, MO_TEUL)
270
-TRANS(fldgt_d, ALL, gen_fload_gt, MO_TEUQ)
271
-TRANS(fldle_s, ALL, gen_fload_le, MO_TEUL)
272
-TRANS(fldle_d, ALL, gen_fload_le, MO_TEUQ)
273
-TRANS(fstgt_s, ALL, gen_fstore_gt, MO_TEUL)
274
-TRANS(fstgt_d, ALL, gen_fstore_gt, MO_TEUQ)
275
-TRANS(fstle_s, ALL, gen_fstore_le, MO_TEUL)
276
-TRANS(fstle_d, ALL, gen_fstore_le, MO_TEUQ)
277
+TRANS(fld_s, FP_SP, gen_fload_i, MO_TEUL)
278
+TRANS(fst_s, FP_SP, gen_fstore_i, MO_TEUL)
279
+TRANS(fld_d, FP_DP, gen_fload_i, MO_TEUQ)
280
+TRANS(fst_d, FP_DP, gen_fstore_i, MO_TEUQ)
281
+TRANS(fldx_s, FP_SP, gen_floadx, MO_TEUL)
282
+TRANS(fldx_d, FP_DP, gen_floadx, MO_TEUQ)
283
+TRANS(fstx_s, FP_SP, gen_fstorex, MO_TEUL)
284
+TRANS(fstx_d, FP_DP, gen_fstorex, MO_TEUQ)
285
+TRANS(fldgt_s, FP_SP, gen_fload_gt, MO_TEUL)
286
+TRANS(fldgt_d, FP_DP, gen_fload_gt, MO_TEUQ)
287
+TRANS(fldle_s, FP_SP, gen_fload_le, MO_TEUL)
288
+TRANS(fldle_d, FP_DP, gen_fload_le, MO_TEUQ)
289
+TRANS(fstgt_s, FP_SP, gen_fstore_gt, MO_TEUL)
290
+TRANS(fstgt_d, FP_DP, gen_fstore_gt, MO_TEUQ)
291
+TRANS(fstle_s, FP_SP, gen_fstore_le, MO_TEUL)
292
+TRANS(fstle_d, FP_DP, gen_fstore_le, MO_TEUQ)
293
diff --git a/target/loongarch/insn_trans/trans_fmov.c.inc b/target/loongarch/insn_trans/trans_fmov.c.inc
294
index XXXXXXX..XXXXXXX 100644
295
--- a/target/loongarch/insn_trans/trans_fmov.c.inc
296
+++ b/target/loongarch/insn_trans/trans_fmov.c.inc
297
@@ -XXX,XX +XXX,XX @@ static bool trans_fsel(DisasContext *ctx, arg_fsel *a)
298
TCGv src2 = get_fpr(ctx, a->fk);
299
TCGv cond;
300
301
+ if (!avail_FP(ctx)) {
302
+ return false;
303
+ }
304
+
305
CHECK_FPE;
306
307
cond = tcg_temp_new();
308
@@ -XXX,XX +XXX,XX @@ static bool gen_r2f(DisasContext *ctx, arg_fr *a,
309
TCGv src = gpr_src(ctx, a->rj, EXT_NONE);
310
TCGv dest = get_fpr(ctx, a->fd);
311
312
+ if (!avail_FP(ctx)) {
313
+ return false;
314
+ }
315
+
316
CHECK_FPE;
317
318
func(dest, src);
319
@@ -XXX,XX +XXX,XX @@ static bool gen_f2r(DisasContext *ctx, arg_rf *a,
320
TCGv dest = gpr_dst(ctx, a->rd, EXT_NONE);
321
TCGv src = get_fpr(ctx, a->fj);
322
323
+ if (!avail_FP(ctx)) {
324
+ return false;
325
+ }
326
+
327
CHECK_FPE;
328
329
func(dest, src);
330
@@ -XXX,XX +XXX,XX @@ static bool trans_movgr2fcsr(DisasContext *ctx, arg_movgr2fcsr *a)
331
uint32_t mask = fcsr_mask[a->fcsrd];
332
TCGv Rj = gpr_src(ctx, a->rj, EXT_NONE);
333
334
+ if (!avail_FP(ctx)) {
335
+ return false;
336
+ }
337
+
338
CHECK_FPE;
339
340
if (mask == UINT32_MAX) {
341
@@ -XXX,XX +XXX,XX @@ static bool trans_movfcsr2gr(DisasContext *ctx, arg_movfcsr2gr *a)
342
{
343
TCGv dest = gpr_dst(ctx, a->rd, EXT_NONE);
344
345
+ if (!avail_FP(ctx)) {
346
+ return false;
347
+ }
348
+
349
CHECK_FPE;
350
351
tcg_gen_ld32u_i64(dest, cpu_env, offsetof(CPULoongArchState, fcsr0));
352
@@ -XXX,XX +XXX,XX @@ static bool trans_movfr2cf(DisasContext *ctx, arg_movfr2cf *a)
353
TCGv t0;
354
TCGv src = get_fpr(ctx, a->fj);
355
356
+ if (!avail_FP(ctx)) {
357
+ return false;
358
+ }
359
+
360
CHECK_FPE;
361
362
t0 = tcg_temp_new();
363
@@ -XXX,XX +XXX,XX @@ static bool trans_movcf2fr(DisasContext *ctx, arg_movcf2fr *a)
364
{
365
TCGv dest = get_fpr(ctx, a->fd);
366
367
+ if (!avail_FP(ctx)) {
368
+ return false;
369
+ }
370
+
371
CHECK_FPE;
372
373
tcg_gen_ld8u_tl(dest, cpu_env,
374
@@ -XXX,XX +XXX,XX @@ static bool trans_movgr2cf(DisasContext *ctx, arg_movgr2cf *a)
375
{
376
TCGv t0;
377
378
+ if (!avail_FP(ctx)) {
379
+ return false;
380
+ }
381
+
382
CHECK_FPE;
383
384
t0 = tcg_temp_new();
385
@@ -XXX,XX +XXX,XX @@ static bool trans_movgr2cf(DisasContext *ctx, arg_movgr2cf *a)
386
387
static bool trans_movcf2gr(DisasContext *ctx, arg_movcf2gr *a)
388
{
389
+ if (!avail_FP(ctx)) {
390
+ return false;
391
+ }
392
+
393
CHECK_FPE;
394
395
tcg_gen_ld8u_tl(gpr_dst(ctx, a->rd, EXT_NONE), cpu_env,
396
@@ -XXX,XX +XXX,XX @@ static bool trans_movcf2gr(DisasContext *ctx, arg_movcf2gr *a)
397
return true;
398
}
399
400
-TRANS(fmov_s, ALL, gen_f2f, tcg_gen_mov_tl, true)
401
-TRANS(fmov_d, ALL, gen_f2f, tcg_gen_mov_tl, false)
402
-TRANS(movgr2fr_w, ALL, gen_r2f, gen_movgr2fr_w)
403
+TRANS(fmov_s, FP_SP, gen_f2f, tcg_gen_mov_tl, true)
404
+TRANS(fmov_d, FP_DP, gen_f2f, tcg_gen_mov_tl, false)
405
+TRANS(movgr2fr_w, FP_SP, gen_r2f, gen_movgr2fr_w)
406
TRANS(movgr2fr_d, 64, gen_r2f, tcg_gen_mov_tl)
407
-TRANS(movgr2frh_w, ALL, gen_r2f, gen_movgr2frh_w)
408
-TRANS(movfr2gr_s, ALL, gen_f2r, tcg_gen_ext32s_tl)
409
+TRANS(movgr2frh_w, FP_DP, gen_r2f, gen_movgr2frh_w)
410
+TRANS(movfr2gr_s, FP_SP, gen_f2r, tcg_gen_ext32s_tl)
411
TRANS(movfr2gr_d, 64, gen_f2r, tcg_gen_mov_tl)
412
-TRANS(movfrh2gr_s, ALL, gen_f2r, gen_movfrh2gr_s)
413
+TRANS(movfrh2gr_s, FP_DP, gen_f2r, gen_movfrh2gr_s)
414
diff --git a/target/loongarch/translate.c b/target/loongarch/translate.c
415
index XXXXXXX..XXXXXXX 100644
416
--- a/target/loongarch/translate.c
417
+++ b/target/loongarch/translate.c
418
@@ -XXX,XX +XXX,XX @@ static void loongarch_tr_init_disas_context(DisasContextBase *dcbase,
419
ctx->zero = tcg_constant_tl(0);
420
421
ctx->cpucfg1 = env->cpucfg[1];
422
+ ctx->cpucfg2 = env->cpucfg[2];
423
}
424
425
static void loongarch_tr_tb_start(DisasContextBase *dcbase, CPUState *cs)
426
diff --git a/target/loongarch/translate.h b/target/loongarch/translate.h
427
index XXXXXXX..XXXXXXX 100644
428
--- a/target/loongarch/translate.h
429
+++ b/target/loongarch/translate.h
430
@@ -XXX,XX +XXX,XX @@
431
#define avail_ALL(C) true
432
#define avail_64(C) (FIELD_EX32((C)->cpucfg1, CPUCFG1, ARCH) == \
433
CPUCFG1_ARCH_LA64)
434
+#define avail_FP(C) (FIELD_EX32((C)->cpucfg2, CPUCFG2, FP))
435
+#define avail_FP_SP(C) (FIELD_EX32((C)->cpucfg2, CPUCFG2, FP_SP))
436
+#define avail_FP_DP(C) (FIELD_EX32((C)->cpucfg2, CPUCFG2, FP_DP))
437
438
/*
439
* If an operation is being performed on less than TARGET_LONG_BITS,
440
@@ -XXX,XX +XXX,XX @@ typedef struct DisasContext {
441
bool la64; /* LoongArch64 mode */
442
bool va32; /* 32-bit virtual address */
443
uint32_t cpucfg1;
444
+ uint32_t cpucfg2;
445
} DisasContext;
446
447
void generate_exception(DisasContext *ctx, int excp);
448
--
449
2.39.1
diff view generated by jsdifflib
New patch
[PULL 24/31] target/loongarch: Add avail_LSPW to check LSPW instructions
1
Signed-off-by: Song Gao <gaosong@loongson.cn>
2
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
3
Message-ID: <20230822032724.1353391-13-gaosong@loongson.cn>
4
Message-Id: <20230822071959.35620-7-philmd@linaro.org>
5
---
6
target/loongarch/insn_trans/trans_privileged.c.inc | 8 ++++++++
7
target/loongarch/translate.h | 1 +
8
2 files changed, 9 insertions(+)
1
9
10
diff --git a/target/loongarch/insn_trans/trans_privileged.c.inc b/target/loongarch/insn_trans/trans_privileged.c.inc
11
index XXXXXXX..XXXXXXX 100644
12
--- a/target/loongarch/insn_trans/trans_privileged.c.inc
13
+++ b/target/loongarch/insn_trans/trans_privileged.c.inc
14
@@ -XXX,XX +XXX,XX @@ static bool trans_ldpte(DisasContext *ctx, arg_ldpte *a)
15
TCGv_i32 mem_idx = tcg_constant_i32(ctx->mem_idx);
16
TCGv src1 = gpr_src(ctx, a->rj, EXT_NONE);
17
18
+ if (!avail_LSPW(ctx)) {
19
+ return true;
20
+ }
21
+
22
if (check_plv(ctx)) {
23
return false;
24
}
25
@@ -XXX,XX +XXX,XX @@ static bool trans_lddir(DisasContext *ctx, arg_lddir *a)
26
TCGv src = gpr_src(ctx, a->rj, EXT_NONE);
27
TCGv dest = gpr_dst(ctx, a->rd, EXT_NONE);
28
29
+ if (!avail_LSPW(ctx)) {
30
+ return true;
31
+ }
32
+
33
if (check_plv(ctx)) {
34
return false;
35
}
36
diff --git a/target/loongarch/translate.h b/target/loongarch/translate.h
37
index XXXXXXX..XXXXXXX 100644
38
--- a/target/loongarch/translate.h
39
+++ b/target/loongarch/translate.h
40
@@ -XXX,XX +XXX,XX @@
41
#define avail_FP(C) (FIELD_EX32((C)->cpucfg2, CPUCFG2, FP))
42
#define avail_FP_SP(C) (FIELD_EX32((C)->cpucfg2, CPUCFG2, FP_SP))
43
#define avail_FP_DP(C) (FIELD_EX32((C)->cpucfg2, CPUCFG2, FP_DP))
44
+#define avail_LSPW(C) (FIELD_EX32((C)->cpucfg2, CPUCFG2, LSPW))
45
46
/*
47
* If an operation is being performed on less than TARGET_LONG_BITS,
48
--
49
2.39.1
diff view generated by jsdifflib
New patch
[PULL 25/31] target/loongarch: Add avail_LAM to check atomic instructions
1
Signed-off-by: Song Gao <gaosong@loongson.cn>
2
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
3
Message-ID: <20230822032724.1353391-14-gaosong@loongson.cn>
4
Message-Id: <20230822071959.35620-8-philmd@linaro.org>
5
---
6
.../loongarch/insn_trans/trans_atomic.c.inc | 72 +++++++++----------
7
target/loongarch/translate.h | 1 +
8
2 files changed, 37 insertions(+), 36 deletions(-)
1
9
10
diff --git a/target/loongarch/insn_trans/trans_atomic.c.inc b/target/loongarch/insn_trans/trans_atomic.c.inc
11
index XXXXXXX..XXXXXXX 100644
12
--- a/target/loongarch/insn_trans/trans_atomic.c.inc
13
+++ b/target/loongarch/insn_trans/trans_atomic.c.inc
14
@@ -XXX,XX +XXX,XX @@ TRANS(ll_w, ALL, gen_ll, MO_TESL)
15
TRANS(sc_w, ALL, gen_sc, MO_TESL)
16
TRANS(ll_d, 64, gen_ll, MO_TEUQ)
17
TRANS(sc_d, 64, gen_sc, MO_TEUQ)
18
-TRANS(amswap_w, 64, gen_am, tcg_gen_atomic_xchg_tl, MO_TESL)
19
-TRANS(amswap_d, 64, gen_am, tcg_gen_atomic_xchg_tl, MO_TEUQ)
20
-TRANS(amadd_w, 64, gen_am, tcg_gen_atomic_fetch_add_tl, MO_TESL)
21
-TRANS(amadd_d, 64, gen_am, tcg_gen_atomic_fetch_add_tl, MO_TEUQ)
22
-TRANS(amand_w, 64, gen_am, tcg_gen_atomic_fetch_and_tl, MO_TESL)
23
-TRANS(amand_d, 64, gen_am, tcg_gen_atomic_fetch_and_tl, MO_TEUQ)
24
-TRANS(amor_w, 64, gen_am, tcg_gen_atomic_fetch_or_tl, MO_TESL)
25
-TRANS(amor_d, 64, gen_am, tcg_gen_atomic_fetch_or_tl, MO_TEUQ)
26
-TRANS(amxor_w, 64, gen_am, tcg_gen_atomic_fetch_xor_tl, MO_TESL)
27
-TRANS(amxor_d, 64, gen_am, tcg_gen_atomic_fetch_xor_tl, MO_TEUQ)
28
-TRANS(ammax_w, 64, gen_am, tcg_gen_atomic_fetch_smax_tl, MO_TESL)
29
-TRANS(ammax_d, 64, gen_am, tcg_gen_atomic_fetch_smax_tl, MO_TEUQ)
30
-TRANS(ammin_w, 64, gen_am, tcg_gen_atomic_fetch_smin_tl, MO_TESL)
31
-TRANS(ammin_d, 64, gen_am, tcg_gen_atomic_fetch_smin_tl, MO_TEUQ)
32
-TRANS(ammax_wu, 64, gen_am, tcg_gen_atomic_fetch_umax_tl, MO_TESL)
33
-TRANS(ammax_du, 64, gen_am, tcg_gen_atomic_fetch_umax_tl, MO_TEUQ)
34
-TRANS(ammin_wu, 64, gen_am, tcg_gen_atomic_fetch_umin_tl, MO_TESL)
35
-TRANS(ammin_du, 64, gen_am, tcg_gen_atomic_fetch_umin_tl, MO_TEUQ)
36
-TRANS(amswap_db_w, 64, gen_am, tcg_gen_atomic_xchg_tl, MO_TESL)
37
-TRANS(amswap_db_d, 64, gen_am, tcg_gen_atomic_xchg_tl, MO_TEUQ)
38
-TRANS(amadd_db_w, 64, gen_am, tcg_gen_atomic_fetch_add_tl, MO_TESL)
39
-TRANS(amadd_db_d, 64, gen_am, tcg_gen_atomic_fetch_add_tl, MO_TEUQ)
40
-TRANS(amand_db_w, 64, gen_am, tcg_gen_atomic_fetch_and_tl, MO_TESL)
41
-TRANS(amand_db_d, 64, gen_am, tcg_gen_atomic_fetch_and_tl, MO_TEUQ)
42
-TRANS(amor_db_w, 64, gen_am, tcg_gen_atomic_fetch_or_tl, MO_TESL)
43
-TRANS(amor_db_d, 64, gen_am, tcg_gen_atomic_fetch_or_tl, MO_TEUQ)
44
-TRANS(amxor_db_w, 64, gen_am, tcg_gen_atomic_fetch_xor_tl, MO_TESL)
45
-TRANS(amxor_db_d, 64, gen_am, tcg_gen_atomic_fetch_xor_tl, MO_TEUQ)
46
-TRANS(ammax_db_w, 64, gen_am, tcg_gen_atomic_fetch_smax_tl, MO_TESL)
47
-TRANS(ammax_db_d, 64, gen_am, tcg_gen_atomic_fetch_smax_tl, MO_TEUQ)
48
-TRANS(ammin_db_w, 64, gen_am, tcg_gen_atomic_fetch_smin_tl, MO_TESL)
49
-TRANS(ammin_db_d, 64, gen_am, tcg_gen_atomic_fetch_smin_tl, MO_TEUQ)
50
-TRANS(ammax_db_wu, 64, gen_am, tcg_gen_atomic_fetch_umax_tl, MO_TESL)
51
-TRANS(ammax_db_du, 64, gen_am, tcg_gen_atomic_fetch_umax_tl, MO_TEUQ)
52
-TRANS(ammin_db_wu, 64, gen_am, tcg_gen_atomic_fetch_umin_tl, MO_TESL)
53
-TRANS(ammin_db_du, 64, gen_am, tcg_gen_atomic_fetch_umin_tl, MO_TEUQ)
54
+TRANS(amswap_w, LAM, gen_am, tcg_gen_atomic_xchg_tl, MO_TESL)
55
+TRANS(amswap_d, LAM, gen_am, tcg_gen_atomic_xchg_tl, MO_TEUQ)
56
+TRANS(amadd_w, LAM, gen_am, tcg_gen_atomic_fetch_add_tl, MO_TESL)
57
+TRANS(amadd_d, LAM, gen_am, tcg_gen_atomic_fetch_add_tl, MO_TEUQ)
58
+TRANS(amand_w, LAM, gen_am, tcg_gen_atomic_fetch_and_tl, MO_TESL)
59
+TRANS(amand_d, LAM, gen_am, tcg_gen_atomic_fetch_and_tl, MO_TEUQ)
60
+TRANS(amor_w, LAM, gen_am, tcg_gen_atomic_fetch_or_tl, MO_TESL)
61
+TRANS(amor_d, LAM, gen_am, tcg_gen_atomic_fetch_or_tl, MO_TEUQ)
62
+TRANS(amxor_w, LAM, gen_am, tcg_gen_atomic_fetch_xor_tl, MO_TESL)
63
+TRANS(amxor_d, LAM, gen_am, tcg_gen_atomic_fetch_xor_tl, MO_TEUQ)
64
+TRANS(ammax_w, LAM, gen_am, tcg_gen_atomic_fetch_smax_tl, MO_TESL)
65
+TRANS(ammax_d, LAM, gen_am, tcg_gen_atomic_fetch_smax_tl, MO_TEUQ)
66
+TRANS(ammin_w, LAM, gen_am, tcg_gen_atomic_fetch_smin_tl, MO_TESL)
67
+TRANS(ammin_d, LAM, gen_am, tcg_gen_atomic_fetch_smin_tl, MO_TEUQ)
68
+TRANS(ammax_wu, LAM, gen_am, tcg_gen_atomic_fetch_umax_tl, MO_TESL)
69
+TRANS(ammax_du, LAM, gen_am, tcg_gen_atomic_fetch_umax_tl, MO_TEUQ)
70
+TRANS(ammin_wu, LAM, gen_am, tcg_gen_atomic_fetch_umin_tl, MO_TESL)
71
+TRANS(ammin_du, LAM, gen_am, tcg_gen_atomic_fetch_umin_tl, MO_TEUQ)
72
+TRANS(amswap_db_w, LAM, gen_am, tcg_gen_atomic_xchg_tl, MO_TESL)
73
+TRANS(amswap_db_d, LAM, gen_am, tcg_gen_atomic_xchg_tl, MO_TEUQ)
74
+TRANS(amadd_db_w, LAM, gen_am, tcg_gen_atomic_fetch_add_tl, MO_TESL)
75
+TRANS(amadd_db_d, LAM, gen_am, tcg_gen_atomic_fetch_add_tl, MO_TEUQ)
76
+TRANS(amand_db_w, LAM, gen_am, tcg_gen_atomic_fetch_and_tl, MO_TESL)
77
+TRANS(amand_db_d, LAM, gen_am, tcg_gen_atomic_fetch_and_tl, MO_TEUQ)
78
+TRANS(amor_db_w, LAM, gen_am, tcg_gen_atomic_fetch_or_tl, MO_TESL)
79
+TRANS(amor_db_d, LAM, gen_am, tcg_gen_atomic_fetch_or_tl, MO_TEUQ)
80
+TRANS(amxor_db_w, LAM, gen_am, tcg_gen_atomic_fetch_xor_tl, MO_TESL)
81
+TRANS(amxor_db_d, LAM, gen_am, tcg_gen_atomic_fetch_xor_tl, MO_TEUQ)
82
+TRANS(ammax_db_w, LAM, gen_am, tcg_gen_atomic_fetch_smax_tl, MO_TESL)
83
+TRANS(ammax_db_d, LAM, gen_am, tcg_gen_atomic_fetch_smax_tl, MO_TEUQ)
84
+TRANS(ammin_db_w, LAM, gen_am, tcg_gen_atomic_fetch_smin_tl, MO_TESL)
85
+TRANS(ammin_db_d, LAM, gen_am, tcg_gen_atomic_fetch_smin_tl, MO_TEUQ)
86
+TRANS(ammax_db_wu, LAM, gen_am, tcg_gen_atomic_fetch_umax_tl, MO_TESL)
87
+TRANS(ammax_db_du, LAM, gen_am, tcg_gen_atomic_fetch_umax_tl, MO_TEUQ)
88
+TRANS(ammin_db_wu, LAM, gen_am, tcg_gen_atomic_fetch_umin_tl, MO_TESL)
89
+TRANS(ammin_db_du, LAM, gen_am, tcg_gen_atomic_fetch_umin_tl, MO_TEUQ)
90
diff --git a/target/loongarch/translate.h b/target/loongarch/translate.h
91
index XXXXXXX..XXXXXXX 100644
92
--- a/target/loongarch/translate.h
93
+++ b/target/loongarch/translate.h
94
@@ -XXX,XX +XXX,XX @@
95
#define avail_FP_SP(C) (FIELD_EX32((C)->cpucfg2, CPUCFG2, FP_SP))
96
#define avail_FP_DP(C) (FIELD_EX32((C)->cpucfg2, CPUCFG2, FP_DP))
97
#define avail_LSPW(C) (FIELD_EX32((C)->cpucfg2, CPUCFG2, LSPW))
98
+#define avail_LAM(C) (FIELD_EX32((C)->cpucfg2, CPUCFG2, LAM))
99
100
/*
101
* If an operation is being performed on less than TARGET_LONG_BITS,
102
--
103
2.39.1
diff view generated by jsdifflib
New patch
[PULL 26/31] target/loongarch: Add avail_LSX to check LSX instructions
1
Signed-off-by: Song Gao <gaosong@loongson.cn>
2
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
3
Message-ID: <20230822032724.1353391-15-gaosong@loongson.cn>
4
Message-Id: <20230822073026.35776-1-philmd@linaro.org>
5
---
6
target/loongarch/insn_trans/trans_lsx.c.inc | 1482 ++++++++++---------
7
target/loongarch/translate.h | 2 +
8
2 files changed, 823 insertions(+), 661 deletions(-)
1
9
10
diff --git a/target/loongarch/insn_trans/trans_lsx.c.inc b/target/loongarch/insn_trans/trans_lsx.c.inc
11
index XXXXXXX..XXXXXXX 100644
12
--- a/target/loongarch/insn_trans/trans_lsx.c.inc
13
+++ b/target/loongarch/insn_trans/trans_lsx.c.inc
14
@@ -XXX,XX +XXX,XX @@ static bool gvec_subi(DisasContext *ctx, arg_vv_i *a, MemOp mop)
15
return true;
16
}
17
18
-TRANS(vadd_b, ALL, gvec_vvv, MO_8, tcg_gen_gvec_add)
19
-TRANS(vadd_h, ALL, gvec_vvv, MO_16, tcg_gen_gvec_add)
20
-TRANS(vadd_w, ALL, gvec_vvv, MO_32, tcg_gen_gvec_add)
21
-TRANS(vadd_d, ALL, gvec_vvv, MO_64, tcg_gen_gvec_add)
22
+TRANS(vadd_b, LSX, gvec_vvv, MO_8, tcg_gen_gvec_add)
23
+TRANS(vadd_h, LSX, gvec_vvv, MO_16, tcg_gen_gvec_add)
24
+TRANS(vadd_w, LSX, gvec_vvv, MO_32, tcg_gen_gvec_add)
25
+TRANS(vadd_d, LSX, gvec_vvv, MO_64, tcg_gen_gvec_add)
26
27
#define VADDSUB_Q(NAME) \
28
static bool trans_v## NAME ##_q(DisasContext *ctx, arg_vvv *a) \
29
{ \
30
TCGv_i64 rh, rl, ah, al, bh, bl; \
31
\
32
+ if (!avail_LSX(ctx)) { \
33
+ return false; \
34
+ } \
35
+ \
36
CHECK_SXE; \
37
\
38
rh = tcg_temp_new_i64(); \
39
@@ -XXX,XX +XXX,XX @@ static bool trans_v## NAME ##_q(DisasContext *ctx, arg_vvv *a) \
40
VADDSUB_Q(add)
41
VADDSUB_Q(sub)
42
43
-TRANS(vsub_b, ALL, gvec_vvv, MO_8, tcg_gen_gvec_sub)
44
-TRANS(vsub_h, ALL, gvec_vvv, MO_16, tcg_gen_gvec_sub)
45
-TRANS(vsub_w, ALL, gvec_vvv, MO_32, tcg_gen_gvec_sub)
46
-TRANS(vsub_d, ALL, gvec_vvv, MO_64, tcg_gen_gvec_sub)
47
-
48
-TRANS(vaddi_bu, ALL, gvec_vv_i, MO_8, tcg_gen_gvec_addi)
49
-TRANS(vaddi_hu, ALL, gvec_vv_i, MO_16, tcg_gen_gvec_addi)
50
-TRANS(vaddi_wu, ALL, gvec_vv_i, MO_32, tcg_gen_gvec_addi)
51
-TRANS(vaddi_du, ALL, gvec_vv_i, MO_64, tcg_gen_gvec_addi)
52
-TRANS(vsubi_bu, ALL, gvec_subi, MO_8)
53
-TRANS(vsubi_hu, ALL, gvec_subi, MO_16)
54
-TRANS(vsubi_wu, ALL, gvec_subi, MO_32)
55
-TRANS(vsubi_du, ALL, gvec_subi, MO_64)
56
-
57
-TRANS(vneg_b, ALL, gvec_vv, MO_8, tcg_gen_gvec_neg)
58
-TRANS(vneg_h, ALL, gvec_vv, MO_16, tcg_gen_gvec_neg)
59
-TRANS(vneg_w, ALL, gvec_vv, MO_32, tcg_gen_gvec_neg)
60
-TRANS(vneg_d, ALL, gvec_vv, MO_64, tcg_gen_gvec_neg)
61
-
62
-TRANS(vsadd_b, ALL, gvec_vvv, MO_8, tcg_gen_gvec_ssadd)
63
-TRANS(vsadd_h, ALL, gvec_vvv, MO_16, tcg_gen_gvec_ssadd)
64
-TRANS(vsadd_w, ALL, gvec_vvv, MO_32, tcg_gen_gvec_ssadd)
65
-TRANS(vsadd_d, ALL, gvec_vvv, MO_64, tcg_gen_gvec_ssadd)
66
-TRANS(vsadd_bu, ALL, gvec_vvv, MO_8, tcg_gen_gvec_usadd)
67
-TRANS(vsadd_hu, ALL, gvec_vvv, MO_16, tcg_gen_gvec_usadd)
68
-TRANS(vsadd_wu, ALL, gvec_vvv, MO_32, tcg_gen_gvec_usadd)
69
-TRANS(vsadd_du, ALL, gvec_vvv, MO_64, tcg_gen_gvec_usadd)
70
-TRANS(vssub_b, ALL, gvec_vvv, MO_8, tcg_gen_gvec_sssub)
71
-TRANS(vssub_h, ALL, gvec_vvv, MO_16, tcg_gen_gvec_sssub)
72
-TRANS(vssub_w, ALL, gvec_vvv, MO_32, tcg_gen_gvec_sssub)
73
-TRANS(vssub_d, ALL, gvec_vvv, MO_64, tcg_gen_gvec_sssub)
74
-TRANS(vssub_bu, ALL, gvec_vvv, MO_8, tcg_gen_gvec_ussub)
75
-TRANS(vssub_hu, ALL, gvec_vvv, MO_16, tcg_gen_gvec_ussub)
76
-TRANS(vssub_wu, ALL, gvec_vvv, MO_32, tcg_gen_gvec_ussub)
77
-TRANS(vssub_du, ALL, gvec_vvv, MO_64, tcg_gen_gvec_ussub)
78
-
79
-TRANS(vhaddw_h_b, ALL, gen_vvv, gen_helper_vhaddw_h_b)
80
-TRANS(vhaddw_w_h, ALL, gen_vvv, gen_helper_vhaddw_w_h)
81
-TRANS(vhaddw_d_w, ALL, gen_vvv, gen_helper_vhaddw_d_w)
82
-TRANS(vhaddw_q_d, ALL, gen_vvv, gen_helper_vhaddw_q_d)
83
-TRANS(vhaddw_hu_bu, ALL, gen_vvv, gen_helper_vhaddw_hu_bu)
84
-TRANS(vhaddw_wu_hu, ALL, gen_vvv, gen_helper_vhaddw_wu_hu)
85
-TRANS(vhaddw_du_wu, ALL, gen_vvv, gen_helper_vhaddw_du_wu)
86
-TRANS(vhaddw_qu_du, ALL, gen_vvv, gen_helper_vhaddw_qu_du)
87
-TRANS(vhsubw_h_b, ALL, gen_vvv, gen_helper_vhsubw_h_b)
88
-TRANS(vhsubw_w_h, ALL, gen_vvv, gen_helper_vhsubw_w_h)
89
-TRANS(vhsubw_d_w, ALL, gen_vvv, gen_helper_vhsubw_d_w)
90
-TRANS(vhsubw_q_d, ALL, gen_vvv, gen_helper_vhsubw_q_d)
91
-TRANS(vhsubw_hu_bu, ALL, gen_vvv, gen_helper_vhsubw_hu_bu)
92
-TRANS(vhsubw_wu_hu, ALL, gen_vvv, gen_helper_vhsubw_wu_hu)
93
-TRANS(vhsubw_du_wu, ALL, gen_vvv, gen_helper_vhsubw_du_wu)
94
-TRANS(vhsubw_qu_du, ALL, gen_vvv, gen_helper_vhsubw_qu_du)
95
+TRANS(vsub_b, LSX, gvec_vvv, MO_8, tcg_gen_gvec_sub)
96
+TRANS(vsub_h, LSX, gvec_vvv, MO_16, tcg_gen_gvec_sub)
97
+TRANS(vsub_w, LSX, gvec_vvv, MO_32, tcg_gen_gvec_sub)
98
+TRANS(vsub_d, LSX, gvec_vvv, MO_64, tcg_gen_gvec_sub)
99
+
100
+TRANS(vaddi_bu, LSX, gvec_vv_i, MO_8, tcg_gen_gvec_addi)
101
+TRANS(vaddi_hu, LSX, gvec_vv_i, MO_16, tcg_gen_gvec_addi)
102
+TRANS(vaddi_wu, LSX, gvec_vv_i, MO_32, tcg_gen_gvec_addi)
103
+TRANS(vaddi_du, LSX, gvec_vv_i, MO_64, tcg_gen_gvec_addi)
104
+TRANS(vsubi_bu, LSX, gvec_subi, MO_8)
105
+TRANS(vsubi_hu, LSX, gvec_subi, MO_16)
106
+TRANS(vsubi_wu, LSX, gvec_subi, MO_32)
107
+TRANS(vsubi_du, LSX, gvec_subi, MO_64)
108
+
109
+TRANS(vneg_b, LSX, gvec_vv, MO_8, tcg_gen_gvec_neg)
110
+TRANS(vneg_h, LSX, gvec_vv, MO_16, tcg_gen_gvec_neg)
111
+TRANS(vneg_w, LSX, gvec_vv, MO_32, tcg_gen_gvec_neg)
112
+TRANS(vneg_d, LSX, gvec_vv, MO_64, tcg_gen_gvec_neg)
113
+
114
+TRANS(vsadd_b, LSX, gvec_vvv, MO_8, tcg_gen_gvec_ssadd)
115
+TRANS(vsadd_h, LSX, gvec_vvv, MO_16, tcg_gen_gvec_ssadd)
116
+TRANS(vsadd_w, LSX, gvec_vvv, MO_32, tcg_gen_gvec_ssadd)
117
+TRANS(vsadd_d, LSX, gvec_vvv, MO_64, tcg_gen_gvec_ssadd)
118
+TRANS(vsadd_bu, LSX, gvec_vvv, MO_8, tcg_gen_gvec_usadd)
119
+TRANS(vsadd_hu, LSX, gvec_vvv, MO_16, tcg_gen_gvec_usadd)
120
+TRANS(vsadd_wu, LSX, gvec_vvv, MO_32, tcg_gen_gvec_usadd)
121
+TRANS(vsadd_du, LSX, gvec_vvv, MO_64, tcg_gen_gvec_usadd)
122
+TRANS(vssub_b, LSX, gvec_vvv, MO_8, tcg_gen_gvec_sssub)
123
+TRANS(vssub_h, LSX, gvec_vvv, MO_16, tcg_gen_gvec_sssub)
124
+TRANS(vssub_w, LSX, gvec_vvv, MO_32, tcg_gen_gvec_sssub)
125
+TRANS(vssub_d, LSX, gvec_vvv, MO_64, tcg_gen_gvec_sssub)
126
+TRANS(vssub_bu, LSX, gvec_vvv, MO_8, tcg_gen_gvec_ussub)
127
+TRANS(vssub_hu, LSX, gvec_vvv, MO_16, tcg_gen_gvec_ussub)
128
+TRANS(vssub_wu, LSX, gvec_vvv, MO_32, tcg_gen_gvec_ussub)
129
+TRANS(vssub_du, LSX, gvec_vvv, MO_64, tcg_gen_gvec_ussub)
130
+
131
+TRANS(vhaddw_h_b, LSX, gen_vvv, gen_helper_vhaddw_h_b)
132
+TRANS(vhaddw_w_h, LSX, gen_vvv, gen_helper_vhaddw_w_h)
133
+TRANS(vhaddw_d_w, LSX, gen_vvv, gen_helper_vhaddw_d_w)
134
+TRANS(vhaddw_q_d, LSX, gen_vvv, gen_helper_vhaddw_q_d)
135
+TRANS(vhaddw_hu_bu, LSX, gen_vvv, gen_helper_vhaddw_hu_bu)
136
+TRANS(vhaddw_wu_hu, LSX, gen_vvv, gen_helper_vhaddw_wu_hu)
137
+TRANS(vhaddw_du_wu, LSX, gen_vvv, gen_helper_vhaddw_du_wu)
138
+TRANS(vhaddw_qu_du, LSX, gen_vvv, gen_helper_vhaddw_qu_du)
139
+TRANS(vhsubw_h_b, LSX, gen_vvv, gen_helper_vhsubw_h_b)
140
+TRANS(vhsubw_w_h, LSX, gen_vvv, gen_helper_vhsubw_w_h)
141
+TRANS(vhsubw_d_w, LSX, gen_vvv, gen_helper_vhsubw_d_w)
142
+TRANS(vhsubw_q_d, LSX, gen_vvv, gen_helper_vhsubw_q_d)
143
+TRANS(vhsubw_hu_bu, LSX, gen_vvv, gen_helper_vhsubw_hu_bu)
144
+TRANS(vhsubw_wu_hu, LSX, gen_vvv, gen_helper_vhsubw_wu_hu)
145
+TRANS(vhsubw_du_wu, LSX, gen_vvv, gen_helper_vhsubw_du_wu)
146
+TRANS(vhsubw_qu_du, LSX, gen_vvv, gen_helper_vhsubw_qu_du)
147
148
static void gen_vaddwev_s(unsigned vece, TCGv_vec t, TCGv_vec a, TCGv_vec b)
149
{
150
@@ -XXX,XX +XXX,XX @@ static void do_vaddwev_s(unsigned vece, uint32_t vd_ofs, uint32_t vj_ofs,
151
tcg_gen_gvec_3(vd_ofs, vj_ofs, vk_ofs, oprsz, maxsz, &op[vece]);
152
}
153
154
-TRANS(vaddwev_h_b, ALL, gvec_vvv, MO_8, do_vaddwev_s)
155
-TRANS(vaddwev_w_h, ALL, gvec_vvv, MO_16, do_vaddwev_s)
156
-TRANS(vaddwev_d_w, ALL, gvec_vvv, MO_32, do_vaddwev_s)
157
-TRANS(vaddwev_q_d, ALL, gvec_vvv, MO_64, do_vaddwev_s)
158
+TRANS(vaddwev_h_b, LSX, gvec_vvv, MO_8, do_vaddwev_s)
159
+TRANS(vaddwev_w_h, LSX, gvec_vvv, MO_16, do_vaddwev_s)
160
+TRANS(vaddwev_d_w, LSX, gvec_vvv, MO_32, do_vaddwev_s)
161
+TRANS(vaddwev_q_d, LSX, gvec_vvv, MO_64, do_vaddwev_s)
162
163
static void gen_vaddwod_w_h(TCGv_i32 t, TCGv_i32 a, TCGv_i32 b)
164
{
165
@@ -XXX,XX +XXX,XX @@ static void do_vaddwod_s(unsigned vece, uint32_t vd_ofs, uint32_t vj_ofs,
166
tcg_gen_gvec_3(vd_ofs, vj_ofs, vk_ofs, oprsz, maxsz, &op[vece]);
167
}
168
169
-TRANS(vaddwod_h_b, ALL, gvec_vvv, MO_8, do_vaddwod_s)
170
-TRANS(vaddwod_w_h, ALL, gvec_vvv, MO_16, do_vaddwod_s)
171
-TRANS(vaddwod_d_w, ALL, gvec_vvv, MO_32, do_vaddwod_s)
172
-TRANS(vaddwod_q_d, ALL, gvec_vvv, MO_64, do_vaddwod_s)
173
+TRANS(vaddwod_h_b, LSX, gvec_vvv, MO_8, do_vaddwod_s)
174
+TRANS(vaddwod_w_h, LSX, gvec_vvv, MO_16, do_vaddwod_s)
175
+TRANS(vaddwod_d_w, LSX, gvec_vvv, MO_32, do_vaddwod_s)
176
+TRANS(vaddwod_q_d, LSX, gvec_vvv, MO_64, do_vaddwod_s)
177
178
static void gen_vsubwev_s(unsigned vece, TCGv_vec t, TCGv_vec a, TCGv_vec b)
179
{
180
@@ -XXX,XX +XXX,XX @@ static void do_vsubwev_s(unsigned vece, uint32_t vd_ofs, uint32_t vj_ofs,
181
tcg_gen_gvec_3(vd_ofs, vj_ofs, vk_ofs, oprsz, maxsz, &op[vece]);
182
}
183
184
-TRANS(vsubwev_h_b, ALL, gvec_vvv, MO_8, do_vsubwev_s)
185
-TRANS(vsubwev_w_h, ALL, gvec_vvv, MO_16, do_vsubwev_s)
186
-TRANS(vsubwev_d_w, ALL, gvec_vvv, MO_32, do_vsubwev_s)
187
-TRANS(vsubwev_q_d, ALL, gvec_vvv, MO_64, do_vsubwev_s)
188
+TRANS(vsubwev_h_b, LSX, gvec_vvv, MO_8, do_vsubwev_s)
189
+TRANS(vsubwev_w_h, LSX, gvec_vvv, MO_16, do_vsubwev_s)
190
+TRANS(vsubwev_d_w, LSX, gvec_vvv, MO_32, do_vsubwev_s)
191
+TRANS(vsubwev_q_d, LSX, gvec_vvv, MO_64, do_vsubwev_s)
192
193
static void gen_vsubwod_s(unsigned vece, TCGv_vec t, TCGv_vec a, TCGv_vec b)
194
{
195
@@ -XXX,XX +XXX,XX @@ static void do_vsubwod_s(unsigned vece, uint32_t vd_ofs, uint32_t vj_ofs,
196
tcg_gen_gvec_3(vd_ofs, vj_ofs, vk_ofs, oprsz, maxsz, &op[vece]);
197
}
198
199
-TRANS(vsubwod_h_b, ALL, gvec_vvv, MO_8, do_vsubwod_s)
200
-TRANS(vsubwod_w_h, ALL, gvec_vvv, MO_16, do_vsubwod_s)
201
-TRANS(vsubwod_d_w, ALL, gvec_vvv, MO_32, do_vsubwod_s)
202
-TRANS(vsubwod_q_d, ALL, gvec_vvv, MO_64, do_vsubwod_s)
203
+TRANS(vsubwod_h_b, LSX, gvec_vvv, MO_8, do_vsubwod_s)
204
+TRANS(vsubwod_w_h, LSX, gvec_vvv, MO_16, do_vsubwod_s)
205
+TRANS(vsubwod_d_w, LSX, gvec_vvv, MO_32, do_vsubwod_s)
206
+TRANS(vsubwod_q_d, LSX, gvec_vvv, MO_64, do_vsubwod_s)
207
208
static void gen_vaddwev_u(unsigned vece, TCGv_vec t, TCGv_vec a, TCGv_vec b)
209
{
210
@@ -XXX,XX +XXX,XX @@ static void do_vaddwev_u(unsigned vece, uint32_t vd_ofs, uint32_t vj_ofs,
211
tcg_gen_gvec_3(vd_ofs, vj_ofs, vk_ofs, oprsz, maxsz, &op[vece]);
212
}
213
214
-TRANS(vaddwev_h_bu, ALL, gvec_vvv, MO_8, do_vaddwev_u)
215
-TRANS(vaddwev_w_hu, ALL, gvec_vvv, MO_16, do_vaddwev_u)
216
-TRANS(vaddwev_d_wu, ALL, gvec_vvv, MO_32, do_vaddwev_u)
217
-TRANS(vaddwev_q_du, ALL, gvec_vvv, MO_64, do_vaddwev_u)
218
+TRANS(vaddwev_h_bu, LSX, gvec_vvv, MO_8, do_vaddwev_u)
219
+TRANS(vaddwev_w_hu, LSX, gvec_vvv, MO_16, do_vaddwev_u)
220
+TRANS(vaddwev_d_wu, LSX, gvec_vvv, MO_32, do_vaddwev_u)
221
+TRANS(vaddwev_q_du, LSX, gvec_vvv, MO_64, do_vaddwev_u)
222
223
static void gen_vaddwod_u(unsigned vece, TCGv_vec t, TCGv_vec a, TCGv_vec b)
224
{
225
@@ -XXX,XX +XXX,XX @@ static void do_vaddwod_u(unsigned vece, uint32_t vd_ofs, uint32_t vj_ofs,
226
tcg_gen_gvec_3(vd_ofs, vj_ofs, vk_ofs, oprsz, maxsz, &op[vece]);
227
}
228
229
-TRANS(vaddwod_h_bu, ALL, gvec_vvv, MO_8, do_vaddwod_u)
230
-TRANS(vaddwod_w_hu, ALL, gvec_vvv, MO_16, do_vaddwod_u)
231
-TRANS(vaddwod_d_wu, ALL, gvec_vvv, MO_32, do_vaddwod_u)
232
-TRANS(vaddwod_q_du, ALL, gvec_vvv, MO_64, do_vaddwod_u)
233
+TRANS(vaddwod_h_bu, LSX, gvec_vvv, MO_8, do_vaddwod_u)
234
+TRANS(vaddwod_w_hu, LSX, gvec_vvv, MO_16, do_vaddwod_u)
235
+TRANS(vaddwod_d_wu, LSX, gvec_vvv, MO_32, do_vaddwod_u)
236
+TRANS(vaddwod_q_du, LSX, gvec_vvv, MO_64, do_vaddwod_u)
237
238
static void gen_vsubwev_u(unsigned vece, TCGv_vec t, TCGv_vec a, TCGv_vec b)
239
{
240
@@ -XXX,XX +XXX,XX @@ static void do_vsubwev_u(unsigned vece, uint32_t vd_ofs, uint32_t vj_ofs,
241
tcg_gen_gvec_3(vd_ofs, vj_ofs, vk_ofs, oprsz, maxsz, &op[vece]);
242
}
243
244
-TRANS(vsubwev_h_bu, ALL, gvec_vvv, MO_8, do_vsubwev_u)
245
-TRANS(vsubwev_w_hu, ALL, gvec_vvv, MO_16, do_vsubwev_u)
246
-TRANS(vsubwev_d_wu, ALL, gvec_vvv, MO_32, do_vsubwev_u)
247
-TRANS(vsubwev_q_du, ALL, gvec_vvv, MO_64, do_vsubwev_u)
248
+TRANS(vsubwev_h_bu, LSX, gvec_vvv, MO_8, do_vsubwev_u)
249
+TRANS(vsubwev_w_hu, LSX, gvec_vvv, MO_16, do_vsubwev_u)
250
+TRANS(vsubwev_d_wu, LSX, gvec_vvv, MO_32, do_vsubwev_u)
251
+TRANS(vsubwev_q_du, LSX, gvec_vvv, MO_64, do_vsubwev_u)
252
253
static void gen_vsubwod_u(unsigned vece, TCGv_vec t, TCGv_vec a, TCGv_vec b)
254
{
255
@@ -XXX,XX +XXX,XX @@ static void do_vsubwod_u(unsigned vece, uint32_t vd_ofs, uint32_t vj_ofs,
256
tcg_gen_gvec_3(vd_ofs, vj_ofs, vk_ofs, oprsz, maxsz, &op[vece]);
257
}
258
259
-TRANS(vsubwod_h_bu, ALL, gvec_vvv, MO_8, do_vsubwod_u)
260
-TRANS(vsubwod_w_hu, ALL, gvec_vvv, MO_16, do_vsubwod_u)
261
-TRANS(vsubwod_d_wu, ALL, gvec_vvv, MO_32, do_vsubwod_u)
262
-TRANS(vsubwod_q_du, ALL, gvec_vvv, MO_64, do_vsubwod_u)
263
+TRANS(vsubwod_h_bu, LSX, gvec_vvv, MO_8, do_vsubwod_u)
264
+TRANS(vsubwod_w_hu, LSX, gvec_vvv, MO_16, do_vsubwod_u)
265
+TRANS(vsubwod_d_wu, LSX, gvec_vvv, MO_32, do_vsubwod_u)
266
+TRANS(vsubwod_q_du, LSX, gvec_vvv, MO_64, do_vsubwod_u)
267
268
static void gen_vaddwev_u_s(unsigned vece, TCGv_vec t, TCGv_vec a, TCGv_vec b)
269
{
270
@@ -XXX,XX +XXX,XX @@ static void do_vaddwev_u_s(unsigned vece, uint32_t vd_ofs, uint32_t vj_ofs,
271
tcg_gen_gvec_3(vd_ofs, vj_ofs, vk_ofs, oprsz, maxsz, &op[vece]);
272
}
273
274
-TRANS(vaddwev_h_bu_b, ALL, gvec_vvv, MO_8, do_vaddwev_u_s)
275
-TRANS(vaddwev_w_hu_h, ALL, gvec_vvv, MO_16, do_vaddwev_u_s)
276
-TRANS(vaddwev_d_wu_w, ALL, gvec_vvv, MO_32, do_vaddwev_u_s)
277
-TRANS(vaddwev_q_du_d, ALL, gvec_vvv, MO_64, do_vaddwev_u_s)
278
+TRANS(vaddwev_h_bu_b, LSX, gvec_vvv, MO_8, do_vaddwev_u_s)
279
+TRANS(vaddwev_w_hu_h, LSX, gvec_vvv, MO_16, do_vaddwev_u_s)
280
+TRANS(vaddwev_d_wu_w, LSX, gvec_vvv, MO_32, do_vaddwev_u_s)
281
+TRANS(vaddwev_q_du_d, LSX, gvec_vvv, MO_64, do_vaddwev_u_s)
282
283
static void gen_vaddwod_u_s(unsigned vece, TCGv_vec t, TCGv_vec a, TCGv_vec b)
284
{
285
@@ -XXX,XX +XXX,XX @@ static void do_vaddwod_u_s(unsigned vece, uint32_t vd_ofs, uint32_t vj_ofs,
286
tcg_gen_gvec_3(vd_ofs, vj_ofs, vk_ofs, oprsz, maxsz, &op[vece]);
287
}
288
289
-TRANS(vaddwod_h_bu_b, ALL, gvec_vvv, MO_8, do_vaddwod_u_s)
290
-TRANS(vaddwod_w_hu_h, ALL, gvec_vvv, MO_16, do_vaddwod_u_s)
291
-TRANS(vaddwod_d_wu_w, ALL, gvec_vvv, MO_32, do_vaddwod_u_s)
292
-TRANS(vaddwod_q_du_d, ALL, gvec_vvv, MO_64, do_vaddwod_u_s)
293
+TRANS(vaddwod_h_bu_b, LSX, gvec_vvv, MO_8, do_vaddwod_u_s)
294
+TRANS(vaddwod_w_hu_h, LSX, gvec_vvv, MO_16, do_vaddwod_u_s)
295
+TRANS(vaddwod_d_wu_w, LSX, gvec_vvv, MO_32, do_vaddwod_u_s)
296
+TRANS(vaddwod_q_du_d, LSX, gvec_vvv, MO_64, do_vaddwod_u_s)
297
298
static void do_vavg(unsigned vece, TCGv_vec t, TCGv_vec a, TCGv_vec b,
299
void (*gen_shr_vec)(unsigned, TCGv_vec,
300
@@ -XXX,XX +XXX,XX @@ static void do_vavg_u(unsigned vece, uint32_t vd_ofs, uint32_t vj_ofs,
301
tcg_gen_gvec_3(vd_ofs, vj_ofs, vk_ofs, oprsz, maxsz, &op[vece]);
302
}
303
304
-TRANS(vavg_b, ALL, gvec_vvv, MO_8, do_vavg_s)
305
-TRANS(vavg_h, ALL, gvec_vvv, MO_16, do_vavg_s)
306
-TRANS(vavg_w, ALL, gvec_vvv, MO_32, do_vavg_s)
307
-TRANS(vavg_d, ALL, gvec_vvv, MO_64, do_vavg_s)
308
-TRANS(vavg_bu, ALL, gvec_vvv, MO_8, do_vavg_u)
309
-TRANS(vavg_hu, ALL, gvec_vvv, MO_16, do_vavg_u)
310
-TRANS(vavg_wu, ALL, gvec_vvv, MO_32, do_vavg_u)
311
-TRANS(vavg_du, ALL, gvec_vvv, MO_64, do_vavg_u)
312
+TRANS(vavg_b, LSX, gvec_vvv, MO_8, do_vavg_s)
313
+TRANS(vavg_h, LSX, gvec_vvv, MO_16, do_vavg_s)
314
+TRANS(vavg_w, LSX, gvec_vvv, MO_32, do_vavg_s)
315
+TRANS(vavg_d, LSX, gvec_vvv, MO_64, do_vavg_s)
316
+TRANS(vavg_bu, LSX, gvec_vvv, MO_8, do_vavg_u)
317
+TRANS(vavg_hu, LSX, gvec_vvv, MO_16, do_vavg_u)
318
+TRANS(vavg_wu, LSX, gvec_vvv, MO_32, do_vavg_u)
319
+TRANS(vavg_du, LSX, gvec_vvv, MO_64, do_vavg_u)
320
321
static void do_vavgr_s(unsigned vece, uint32_t vd_ofs, uint32_t vj_ofs,
322
uint32_t vk_ofs, uint32_t oprsz, uint32_t maxsz)
323
@@ -XXX,XX +XXX,XX @@ static void do_vavgr_u(unsigned vece, uint32_t vd_ofs, uint32_t vj_ofs,
324
tcg_gen_gvec_3(vd_ofs, vj_ofs, vk_ofs, oprsz, maxsz, &op[vece]);
325
}
326
327
-TRANS(vavgr_b, ALL, gvec_vvv, MO_8, do_vavgr_s)
328
-TRANS(vavgr_h, ALL, gvec_vvv, MO_16, do_vavgr_s)
329
-TRANS(vavgr_w, ALL, gvec_vvv, MO_32, do_vavgr_s)
330
-TRANS(vavgr_d, ALL, gvec_vvv, MO_64, do_vavgr_s)
331
-TRANS(vavgr_bu, ALL, gvec_vvv, MO_8, do_vavgr_u)
332
-TRANS(vavgr_hu, ALL, gvec_vvv, MO_16, do_vavgr_u)
333
-TRANS(vavgr_wu, ALL, gvec_vvv, MO_32, do_vavgr_u)
334
-TRANS(vavgr_du, ALL, gvec_vvv, MO_64, do_vavgr_u)
335
+TRANS(vavgr_b, LSX, gvec_vvv, MO_8, do_vavgr_s)
336
+TRANS(vavgr_h, LSX, gvec_vvv, MO_16, do_vavgr_s)
337
+TRANS(vavgr_w, LSX, gvec_vvv, MO_32, do_vavgr_s)
338
+TRANS(vavgr_d, LSX, gvec_vvv, MO_64, do_vavgr_s)
339
+TRANS(vavgr_bu, LSX, gvec_vvv, MO_8, do_vavgr_u)
340
+TRANS(vavgr_hu, LSX, gvec_vvv, MO_16, do_vavgr_u)
341
+TRANS(vavgr_wu, LSX, gvec_vvv, MO_32, do_vavgr_u)
342
+TRANS(vavgr_du, LSX, gvec_vvv, MO_64, do_vavgr_u)
343
344
static void gen_vabsd_s(unsigned vece, TCGv_vec t, TCGv_vec a, TCGv_vec b)
345
{
346
@@ -XXX,XX +XXX,XX @@ static void do_vabsd_u(unsigned vece, uint32_t vd_ofs, uint32_t vj_ofs,
347
tcg_gen_gvec_3(vd_ofs, vj_ofs, vk_ofs, oprsz, maxsz, &op[vece]);
348
}
349
350
-TRANS(vabsd_b, ALL, gvec_vvv, MO_8, do_vabsd_s)
351
-TRANS(vabsd_h, ALL, gvec_vvv, MO_16, do_vabsd_s)
352
-TRANS(vabsd_w, ALL, gvec_vvv, MO_32, do_vabsd_s)
353
-TRANS(vabsd_d, ALL, gvec_vvv, MO_64, do_vabsd_s)
354
-TRANS(vabsd_bu, ALL, gvec_vvv, MO_8, do_vabsd_u)
355
-TRANS(vabsd_hu, ALL, gvec_vvv, MO_16, do_vabsd_u)
356
-TRANS(vabsd_wu, ALL, gvec_vvv, MO_32, do_vabsd_u)
357
-TRANS(vabsd_du, ALL, gvec_vvv, MO_64, do_vabsd_u)
358
+TRANS(vabsd_b, LSX, gvec_vvv, MO_8, do_vabsd_s)
359
+TRANS(vabsd_h, LSX, gvec_vvv, MO_16, do_vabsd_s)
360
+TRANS(vabsd_w, LSX, gvec_vvv, MO_32, do_vabsd_s)
361
+TRANS(vabsd_d, LSX, gvec_vvv, MO_64, do_vabsd_s)
362
+TRANS(vabsd_bu, LSX, gvec_vvv, MO_8, do_vabsd_u)
363
+TRANS(vabsd_hu, LSX, gvec_vvv, MO_16, do_vabsd_u)
364
+TRANS(vabsd_wu, LSX, gvec_vvv, MO_32, do_vabsd_u)
365
+TRANS(vabsd_du, LSX, gvec_vvv, MO_64, do_vabsd_u)
366
367
static void gen_vadda(unsigned vece, TCGv_vec t, TCGv_vec a, TCGv_vec b)
368
{
369
@@ -XXX,XX +XXX,XX @@ static void do_vadda(unsigned vece, uint32_t vd_ofs, uint32_t vj_ofs,
370
tcg_gen_gvec_3(vd_ofs, vj_ofs, vk_ofs, oprsz, maxsz, &op[vece]);
371
}
372
373
-TRANS(vadda_b, ALL, gvec_vvv, MO_8, do_vadda)
374
-TRANS(vadda_h, ALL, gvec_vvv, MO_16, do_vadda)
375
-TRANS(vadda_w, ALL, gvec_vvv, MO_32, do_vadda)
376
-TRANS(vadda_d, ALL, gvec_vvv, MO_64, do_vadda)
377
-
378
-TRANS(vmax_b, ALL, gvec_vvv, MO_8, tcg_gen_gvec_smax)
379
-TRANS(vmax_h, ALL, gvec_vvv, MO_16, tcg_gen_gvec_smax)
380
-TRANS(vmax_w, ALL, gvec_vvv, MO_32, tcg_gen_gvec_smax)
381
-TRANS(vmax_d, ALL, gvec_vvv, MO_64, tcg_gen_gvec_smax)
382
-TRANS(vmax_bu, ALL, gvec_vvv, MO_8, tcg_gen_gvec_umax)
383
-TRANS(vmax_hu, ALL, gvec_vvv, MO_16, tcg_gen_gvec_umax)
384
-TRANS(vmax_wu, ALL, gvec_vvv, MO_32, tcg_gen_gvec_umax)
385
-TRANS(vmax_du, ALL, gvec_vvv, MO_64, tcg_gen_gvec_umax)
386
-
387
-TRANS(vmin_b, ALL, gvec_vvv, MO_8, tcg_gen_gvec_smin)
388
-TRANS(vmin_h, ALL, gvec_vvv, MO_16, tcg_gen_gvec_smin)
389
-TRANS(vmin_w, ALL, gvec_vvv, MO_32, tcg_gen_gvec_smin)
390
-TRANS(vmin_d, ALL, gvec_vvv, MO_64, tcg_gen_gvec_smin)
391
-TRANS(vmin_bu, ALL, gvec_vvv, MO_8, tcg_gen_gvec_umin)
392
-TRANS(vmin_hu, ALL, gvec_vvv, MO_16, tcg_gen_gvec_umin)
393
-TRANS(vmin_wu, ALL, gvec_vvv, MO_32, tcg_gen_gvec_umin)
394
-TRANS(vmin_du, ALL, gvec_vvv, MO_64, tcg_gen_gvec_umin)
395
+TRANS(vadda_b, LSX, gvec_vvv, MO_8, do_vadda)
396
+TRANS(vadda_h, LSX, gvec_vvv, MO_16, do_vadda)
397
+TRANS(vadda_w, LSX, gvec_vvv, MO_32, do_vadda)
398
+TRANS(vadda_d, LSX, gvec_vvv, MO_64, do_vadda)
399
+
400
+TRANS(vmax_b, LSX, gvec_vvv, MO_8, tcg_gen_gvec_smax)
401
+TRANS(vmax_h, LSX, gvec_vvv, MO_16, tcg_gen_gvec_smax)
402
+TRANS(vmax_w, LSX, gvec_vvv, MO_32, tcg_gen_gvec_smax)
403
+TRANS(vmax_d, LSX, gvec_vvv, MO_64, tcg_gen_gvec_smax)
404
+TRANS(vmax_bu, LSX, gvec_vvv, MO_8, tcg_gen_gvec_umax)
405
+TRANS(vmax_hu, LSX, gvec_vvv, MO_16, tcg_gen_gvec_umax)
406
+TRANS(vmax_wu, LSX, gvec_vvv, MO_32, tcg_gen_gvec_umax)
407
+TRANS(vmax_du, LSX, gvec_vvv, MO_64, tcg_gen_gvec_umax)
408
+
409
+TRANS(vmin_b, LSX, gvec_vvv, MO_8, tcg_gen_gvec_smin)
410
+TRANS(vmin_h, LSX, gvec_vvv, MO_16, tcg_gen_gvec_smin)
411
+TRANS(vmin_w, LSX, gvec_vvv, MO_32, tcg_gen_gvec_smin)
412
+TRANS(vmin_d, LSX, gvec_vvv, MO_64, tcg_gen_gvec_smin)
413
+TRANS(vmin_bu, LSX, gvec_vvv, MO_8, tcg_gen_gvec_umin)
414
+TRANS(vmin_hu, LSX, gvec_vvv, MO_16, tcg_gen_gvec_umin)
415
+TRANS(vmin_wu, LSX, gvec_vvv, MO_32, tcg_gen_gvec_umin)
416
+TRANS(vmin_du, LSX, gvec_vvv, MO_64, tcg_gen_gvec_umin)
417
418
static void gen_vmini_s(unsigned vece, TCGv_vec t, TCGv_vec a, int64_t imm)
419
{
420
@@ -XXX,XX +XXX,XX @@ static void do_vmini_u(unsigned vece, uint32_t vd_ofs, uint32_t vj_ofs,
421
tcg_gen_gvec_2i(vd_ofs, vj_ofs, oprsz, maxsz, imm, &op[vece]);
422
}
423
424
-TRANS(vmini_b, ALL, gvec_vv_i, MO_8, do_vmini_s)
425
-TRANS(vmini_h, ALL, gvec_vv_i, MO_16, do_vmini_s)
426
-TRANS(vmini_w, ALL, gvec_vv_i, MO_32, do_vmini_s)
427
-TRANS(vmini_d, ALL, gvec_vv_i, MO_64, do_vmini_s)
428
-TRANS(vmini_bu, ALL, gvec_vv_i, MO_8, do_vmini_u)
429
-TRANS(vmini_hu, ALL, gvec_vv_i, MO_16, do_vmini_u)
430
-TRANS(vmini_wu, ALL, gvec_vv_i, MO_32, do_vmini_u)
431
-TRANS(vmini_du, ALL, gvec_vv_i, MO_64, do_vmini_u)
432
+TRANS(vmini_b, LSX, gvec_vv_i, MO_8, do_vmini_s)
433
+TRANS(vmini_h, LSX, gvec_vv_i, MO_16, do_vmini_s)
434
+TRANS(vmini_w, LSX, gvec_vv_i, MO_32, do_vmini_s)
435
+TRANS(vmini_d, LSX, gvec_vv_i, MO_64, do_vmini_s)
436
+TRANS(vmini_bu, LSX, gvec_vv_i, MO_8, do_vmini_u)
437
+TRANS(vmini_hu, LSX, gvec_vv_i, MO_16, do_vmini_u)
438
+TRANS(vmini_wu, LSX, gvec_vv_i, MO_32, do_vmini_u)
439
+TRANS(vmini_du, LSX, gvec_vv_i, MO_64, do_vmini_u)
440
441
static void do_vmaxi_s(unsigned vece, uint32_t vd_ofs, uint32_t vj_ofs,
442
int64_t imm, uint32_t oprsz, uint32_t maxsz)
443
@@ -XXX,XX +XXX,XX @@ static void do_vmaxi_u(unsigned vece, uint32_t vd_ofs, uint32_t vj_ofs,
444
tcg_gen_gvec_2i(vd_ofs, vj_ofs, oprsz, maxsz, imm, &op[vece]);
445
}
446
447
-TRANS(vmaxi_b, ALL, gvec_vv_i, MO_8, do_vmaxi_s)
448
-TRANS(vmaxi_h, ALL, gvec_vv_i, MO_16, do_vmaxi_s)
449
-TRANS(vmaxi_w, ALL, gvec_vv_i, MO_32, do_vmaxi_s)
450
-TRANS(vmaxi_d, ALL, gvec_vv_i, MO_64, do_vmaxi_s)
451
-TRANS(vmaxi_bu, ALL, gvec_vv_i, MO_8, do_vmaxi_u)
452
-TRANS(vmaxi_hu, ALL, gvec_vv_i, MO_16, do_vmaxi_u)
453
-TRANS(vmaxi_wu, ALL, gvec_vv_i, MO_32, do_vmaxi_u)
454
-TRANS(vmaxi_du, ALL, gvec_vv_i, MO_64, do_vmaxi_u)
455
+TRANS(vmaxi_b, LSX, gvec_vv_i, MO_8, do_vmaxi_s)
456
+TRANS(vmaxi_h, LSX, gvec_vv_i, MO_16, do_vmaxi_s)
457
+TRANS(vmaxi_w, LSX, gvec_vv_i, MO_32, do_vmaxi_s)
458
+TRANS(vmaxi_d, LSX, gvec_vv_i, MO_64, do_vmaxi_s)
459
+TRANS(vmaxi_bu, LSX, gvec_vv_i, MO_8, do_vmaxi_u)
460
+TRANS(vmaxi_hu, LSX, gvec_vv_i, MO_16, do_vmaxi_u)
461
+TRANS(vmaxi_wu, LSX, gvec_vv_i, MO_32, do_vmaxi_u)
462
+TRANS(vmaxi_du, LSX, gvec_vv_i, MO_64, do_vmaxi_u)
463
464
-TRANS(vmul_b, ALL, gvec_vvv, MO_8, tcg_gen_gvec_mul)
465
-TRANS(vmul_h, ALL, gvec_vvv, MO_16, tcg_gen_gvec_mul)
466
-TRANS(vmul_w, ALL, gvec_vvv, MO_32, tcg_gen_gvec_mul)
467
-TRANS(vmul_d, ALL, gvec_vvv, MO_64, tcg_gen_gvec_mul)
468
+TRANS(vmul_b, LSX, gvec_vvv, MO_8, tcg_gen_gvec_mul)
469
+TRANS(vmul_h, LSX, gvec_vvv, MO_16, tcg_gen_gvec_mul)
470
+TRANS(vmul_w, LSX, gvec_vvv, MO_32, tcg_gen_gvec_mul)
471
+TRANS(vmul_d, LSX, gvec_vvv, MO_64, tcg_gen_gvec_mul)
472
473
static void gen_vmuh_w(TCGv_i32 t, TCGv_i32 a, TCGv_i32 b)
474
{
475
@@ -XXX,XX +XXX,XX @@ static void do_vmuh_s(unsigned vece, uint32_t vd_ofs, uint32_t vj_ofs,
476
tcg_gen_gvec_3(vd_ofs, vj_ofs, vk_ofs, oprsz, maxsz, &op[vece]);
477
}
478
479
-TRANS(vmuh_b, ALL, gvec_vvv, MO_8, do_vmuh_s)
480
-TRANS(vmuh_h, ALL, gvec_vvv, MO_16, do_vmuh_s)
481
-TRANS(vmuh_w, ALL, gvec_vvv, MO_32, do_vmuh_s)
482
-TRANS(vmuh_d, ALL, gvec_vvv, MO_64, do_vmuh_s)
483
+TRANS(vmuh_b, LSX, gvec_vvv, MO_8, do_vmuh_s)
484
+TRANS(vmuh_h, LSX, gvec_vvv, MO_16, do_vmuh_s)
485
+TRANS(vmuh_w, LSX, gvec_vvv, MO_32, do_vmuh_s)
486
+TRANS(vmuh_d, LSX, gvec_vvv, MO_64, do_vmuh_s)
487
488
static void gen_vmuh_wu(TCGv_i32 t, TCGv_i32 a, TCGv_i32 b)
489
{
490
@@ -XXX,XX +XXX,XX @@ static void do_vmuh_u(unsigned vece, uint32_t vd_ofs, uint32_t vj_ofs,
491
tcg_gen_gvec_3(vd_ofs, vj_ofs, vk_ofs, oprsz, maxsz, &op[vece]);
492
}
493
494
-TRANS(vmuh_bu, ALL, gvec_vvv, MO_8, do_vmuh_u)
495
-TRANS(vmuh_hu, ALL, gvec_vvv, MO_16, do_vmuh_u)
496
-TRANS(vmuh_wu, ALL, gvec_vvv, MO_32, do_vmuh_u)
497
-TRANS(vmuh_du, ALL, gvec_vvv, MO_64, do_vmuh_u)
498
+TRANS(vmuh_bu, LSX, gvec_vvv, MO_8, do_vmuh_u)
499
+TRANS(vmuh_hu, LSX, gvec_vvv, MO_16, do_vmuh_u)
500
+TRANS(vmuh_wu, LSX, gvec_vvv, MO_32, do_vmuh_u)
501
+TRANS(vmuh_du, LSX, gvec_vvv, MO_64, do_vmuh_u)
502
503
static void gen_vmulwev_s(unsigned vece, TCGv_vec t, TCGv_vec a, TCGv_vec b)
504
{
505
@@ -XXX,XX +XXX,XX @@ static void do_vmulwev_s(unsigned vece, uint32_t vd_ofs, uint32_t vj_ofs,
506
tcg_gen_gvec_3(vd_ofs, vj_ofs, vk_ofs, oprsz, maxsz, &op[vece]);
507
}
508
509
-TRANS(vmulwev_h_b, ALL, gvec_vvv, MO_8, do_vmulwev_s)
510
-TRANS(vmulwev_w_h, ALL, gvec_vvv, MO_16, do_vmulwev_s)
511
-TRANS(vmulwev_d_w, ALL, gvec_vvv, MO_32, do_vmulwev_s)
512
+TRANS(vmulwev_h_b, LSX, gvec_vvv, MO_8, do_vmulwev_s)
513
+TRANS(vmulwev_w_h, LSX, gvec_vvv, MO_16, do_vmulwev_s)
514
+TRANS(vmulwev_d_w, LSX, gvec_vvv, MO_32, do_vmulwev_s)
515
516
static void tcg_gen_mulus2_i64(TCGv_i64 rl, TCGv_i64 rh,
517
TCGv_i64 arg1, TCGv_i64 arg2)
518
@@ -XXX,XX +XXX,XX @@ static bool trans_## NAME (DisasContext *ctx, arg_vvv *a) \
519
{ \
520
TCGv_i64 rh, rl, arg1, arg2; \
521
\
522
+ if (!avail_LSX(ctx)) { \
523
+ return false; \
524
+ } \
525
+ \
526
rh = tcg_temp_new_i64(); \
527
rl = tcg_temp_new_i64(); \
528
arg1 = tcg_temp_new_i64(); \
529
@@ -XXX,XX +XXX,XX @@ static void do_vmulwod_s(unsigned vece, uint32_t vd_ofs, uint32_t vj_ofs,
530
tcg_gen_gvec_3(vd_ofs, vj_ofs, vk_ofs, oprsz, maxsz, &op[vece]);
531
}
532
533
-TRANS(vmulwod_h_b, ALL, gvec_vvv, MO_8, do_vmulwod_s)
534
-TRANS(vmulwod_w_h, ALL, gvec_vvv, MO_16, do_vmulwod_s)
535
-TRANS(vmulwod_d_w, ALL, gvec_vvv, MO_32, do_vmulwod_s)
536
+TRANS(vmulwod_h_b, LSX, gvec_vvv, MO_8, do_vmulwod_s)
537
+TRANS(vmulwod_w_h, LSX, gvec_vvv, MO_16, do_vmulwod_s)
538
+TRANS(vmulwod_d_w, LSX, gvec_vvv, MO_32, do_vmulwod_s)
539
540
static void gen_vmulwev_u(unsigned vece, TCGv_vec t, TCGv_vec a, TCGv_vec b)
541
{
542
@@ -XXX,XX +XXX,XX @@ static void do_vmulwev_u(unsigned vece, uint32_t vd_ofs, uint32_t vj_ofs,
543
tcg_gen_gvec_3(vd_ofs, vj_ofs, vk_ofs, oprsz, maxsz, &op[vece]);
544
}
545
546
-TRANS(vmulwev_h_bu, ALL, gvec_vvv, MO_8, do_vmulwev_u)
547
-TRANS(vmulwev_w_hu, ALL, gvec_vvv, MO_16, do_vmulwev_u)
548
-TRANS(vmulwev_d_wu, ALL, gvec_vvv, MO_32, do_vmulwev_u)
549
+TRANS(vmulwev_h_bu, LSX, gvec_vvv, MO_8, do_vmulwev_u)
550
+TRANS(vmulwev_w_hu, LSX, gvec_vvv, MO_16, do_vmulwev_u)
551
+TRANS(vmulwev_d_wu, LSX, gvec_vvv, MO_32, do_vmulwev_u)
552
553
static void gen_vmulwod_u(unsigned vece, TCGv_vec t, TCGv_vec a, TCGv_vec b)
554
{
555
@@ -XXX,XX +XXX,XX @@ static void do_vmulwod_u(unsigned vece, uint32_t vd_ofs, uint32_t vj_ofs,
556
tcg_gen_gvec_3(vd_ofs, vj_ofs, vk_ofs, oprsz, maxsz, &op[vece]);
557
}
558
559
-TRANS(vmulwod_h_bu, ALL, gvec_vvv, MO_8, do_vmulwod_u)
560
-TRANS(vmulwod_w_hu, ALL, gvec_vvv, MO_16, do_vmulwod_u)
561
-TRANS(vmulwod_d_wu, ALL, gvec_vvv, MO_32, do_vmulwod_u)
562
+TRANS(vmulwod_h_bu, LSX, gvec_vvv, MO_8, do_vmulwod_u)
563
+TRANS(vmulwod_w_hu, LSX, gvec_vvv, MO_16, do_vmulwod_u)
564
+TRANS(vmulwod_d_wu, LSX, gvec_vvv, MO_32, do_vmulwod_u)
565
566
static void gen_vmulwev_u_s(unsigned vece, TCGv_vec t, TCGv_vec a, TCGv_vec b)
567
{
568
@@ -XXX,XX +XXX,XX @@ static void do_vmulwev_u_s(unsigned vece, uint32_t vd_ofs, uint32_t vj_ofs,
569
tcg_gen_gvec_3(vd_ofs, vj_ofs, vk_ofs, oprsz, maxsz, &op[vece]);
570
}
571
572
-TRANS(vmulwev_h_bu_b, ALL, gvec_vvv, MO_8, do_vmulwev_u_s)
573
-TRANS(vmulwev_w_hu_h, ALL, gvec_vvv, MO_16, do_vmulwev_u_s)
574
-TRANS(vmulwev_d_wu_w, ALL, gvec_vvv, MO_32, do_vmulwev_u_s)
575
+TRANS(vmulwev_h_bu_b, LSX, gvec_vvv, MO_8, do_vmulwev_u_s)
576
+TRANS(vmulwev_w_hu_h, LSX, gvec_vvv, MO_16, do_vmulwev_u_s)
577
+TRANS(vmulwev_d_wu_w, LSX, gvec_vvv, MO_32, do_vmulwev_u_s)
578
579
static void gen_vmulwod_u_s(unsigned vece, TCGv_vec t, TCGv_vec a, TCGv_vec b)
580
{
581
@@ -XXX,XX +XXX,XX @@ static void do_vmulwod_u_s(unsigned vece, uint32_t vd_ofs, uint32_t vj_ofs,
582
tcg_gen_gvec_3(vd_ofs, vj_ofs, vk_ofs, oprsz, maxsz, &op[vece]);
583
}
584
585
-TRANS(vmulwod_h_bu_b, ALL, gvec_vvv, MO_8, do_vmulwod_u_s)
586
-TRANS(vmulwod_w_hu_h, ALL, gvec_vvv, MO_16, do_vmulwod_u_s)
587
-TRANS(vmulwod_d_wu_w, ALL, gvec_vvv, MO_32, do_vmulwod_u_s)
588
+TRANS(vmulwod_h_bu_b, LSX, gvec_vvv, MO_8, do_vmulwod_u_s)
589
+TRANS(vmulwod_w_hu_h, LSX, gvec_vvv, MO_16, do_vmulwod_u_s)
590
+TRANS(vmulwod_d_wu_w, LSX, gvec_vvv, MO_32, do_vmulwod_u_s)
591
592
static void gen_vmadd(unsigned vece, TCGv_vec t, TCGv_vec a, TCGv_vec b)
593
{
594
@@ -XXX,XX +XXX,XX @@ static void do_vmadd(unsigned vece, uint32_t vd_ofs, uint32_t vj_ofs,
595
tcg_gen_gvec_3(vd_ofs, vj_ofs, vk_ofs, oprsz, maxsz, &op[vece]);
596
}
597
598
-TRANS(vmadd_b, ALL, gvec_vvv, MO_8, do_vmadd)
599
-TRANS(vmadd_h, ALL, gvec_vvv, MO_16, do_vmadd)
600
-TRANS(vmadd_w, ALL, gvec_vvv, MO_32, do_vmadd)
601
-TRANS(vmadd_d, ALL, gvec_vvv, MO_64, do_vmadd)
602
+TRANS(vmadd_b, LSX, gvec_vvv, MO_8, do_vmadd)
603
+TRANS(vmadd_h, LSX, gvec_vvv, MO_16, do_vmadd)
604
+TRANS(vmadd_w, LSX, gvec_vvv, MO_32, do_vmadd)
605
+TRANS(vmadd_d, LSX, gvec_vvv, MO_64, do_vmadd)
606
607
static void gen_vmsub(unsigned vece, TCGv_vec t, TCGv_vec a, TCGv_vec b)
608
{
609
@@ -XXX,XX +XXX,XX @@ static void do_vmsub(unsigned vece, uint32_t vd_ofs, uint32_t vj_ofs,
610
tcg_gen_gvec_3(vd_ofs, vj_ofs, vk_ofs, oprsz, maxsz, &op[vece]);
611
}
612
613
-TRANS(vmsub_b, ALL, gvec_vvv, MO_8, do_vmsub)
614
-TRANS(vmsub_h, ALL, gvec_vvv, MO_16, do_vmsub)
615
-TRANS(vmsub_w, ALL, gvec_vvv, MO_32, do_vmsub)
616
-TRANS(vmsub_d, ALL, gvec_vvv, MO_64, do_vmsub)
617
+TRANS(vmsub_b, LSX, gvec_vvv, MO_8, do_vmsub)
618
+TRANS(vmsub_h, LSX, gvec_vvv, MO_16, do_vmsub)
619
+TRANS(vmsub_w, LSX, gvec_vvv, MO_32, do_vmsub)
620
+TRANS(vmsub_d, LSX, gvec_vvv, MO_64, do_vmsub)
621
622
static void gen_vmaddwev_s(unsigned vece, TCGv_vec t, TCGv_vec a, TCGv_vec b)
623
{
624
@@ -XXX,XX +XXX,XX @@ static void do_vmaddwev_s(unsigned vece, uint32_t vd_ofs, uint32_t vj_ofs,
625
tcg_gen_gvec_3(vd_ofs, vj_ofs, vk_ofs, oprsz, maxsz, &op[vece]);
626
}
627
628
-TRANS(vmaddwev_h_b, ALL, gvec_vvv, MO_8, do_vmaddwev_s)
629
-TRANS(vmaddwev_w_h, ALL, gvec_vvv, MO_16, do_vmaddwev_s)
630
-TRANS(vmaddwev_d_w, ALL, gvec_vvv, MO_32, do_vmaddwev_s)
631
+TRANS(vmaddwev_h_b, LSX, gvec_vvv, MO_8, do_vmaddwev_s)
632
+TRANS(vmaddwev_w_h, LSX, gvec_vvv, MO_16, do_vmaddwev_s)
633
+TRANS(vmaddwev_d_w, LSX, gvec_vvv, MO_32, do_vmaddwev_s)
634
635
#define VMADD_Q(NAME, FN, idx1, idx2) \
636
static bool trans_## NAME (DisasContext *ctx, arg_vvv *a) \
637
{ \
638
TCGv_i64 rh, rl, arg1, arg2, th, tl; \
639
\
640
+ if (!avail_LSX(ctx)) { \
641
+ return false; \
642
+ } \
643
+ \
644
rh = tcg_temp_new_i64(); \
645
rl = tcg_temp_new_i64(); \
646
arg1 = tcg_temp_new_i64(); \
647
@@ -XXX,XX +XXX,XX @@ static void do_vmaddwod_s(unsigned vece, uint32_t vd_ofs, uint32_t vj_ofs,
648
tcg_gen_gvec_3(vd_ofs, vj_ofs, vk_ofs, oprsz, maxsz, &op[vece]);
649
}
650
651
-TRANS(vmaddwod_h_b, ALL, gvec_vvv, MO_8, do_vmaddwod_s)
652
-TRANS(vmaddwod_w_h, ALL, gvec_vvv, MO_16, do_vmaddwod_s)
653
-TRANS(vmaddwod_d_w, ALL, gvec_vvv, MO_32, do_vmaddwod_s)
654
+TRANS(vmaddwod_h_b, LSX, gvec_vvv, MO_8, do_vmaddwod_s)
655
+TRANS(vmaddwod_w_h, LSX, gvec_vvv, MO_16, do_vmaddwod_s)
656
+TRANS(vmaddwod_d_w, LSX, gvec_vvv, MO_32, do_vmaddwod_s)
657
658
static void gen_vmaddwev_u(unsigned vece, TCGv_vec t, TCGv_vec a, TCGv_vec b)
659
{
660
@@ -XXX,XX +XXX,XX @@ static void do_vmaddwev_u(unsigned vece, uint32_t vd_ofs, uint32_t vj_ofs,
661
tcg_gen_gvec_3(vd_ofs, vj_ofs, vk_ofs, oprsz, maxsz, &op[vece]);
662
}
663
664
-TRANS(vmaddwev_h_bu, ALL, gvec_vvv, MO_8, do_vmaddwev_u)
665
-TRANS(vmaddwev_w_hu, ALL, gvec_vvv, MO_16, do_vmaddwev_u)
666
-TRANS(vmaddwev_d_wu, ALL, gvec_vvv, MO_32, do_vmaddwev_u)
667
+TRANS(vmaddwev_h_bu, LSX, gvec_vvv, MO_8, do_vmaddwev_u)
668
+TRANS(vmaddwev_w_hu, LSX, gvec_vvv, MO_16, do_vmaddwev_u)
669
+TRANS(vmaddwev_d_wu, LSX, gvec_vvv, MO_32, do_vmaddwev_u)
670
671
static void gen_vmaddwod_u(unsigned vece, TCGv_vec t, TCGv_vec a, TCGv_vec b)
672
{
673
@@ -XXX,XX +XXX,XX @@ static void do_vmaddwod_u(unsigned vece, uint32_t vd_ofs, uint32_t vj_ofs,
674
tcg_gen_gvec_3(vd_ofs, vj_ofs, vk_ofs, oprsz, maxsz, &op[vece]);
675
}
676
677
-TRANS(vmaddwod_h_bu, ALL, gvec_vvv, MO_8, do_vmaddwod_u)
678
-TRANS(vmaddwod_w_hu, ALL, gvec_vvv, MO_16, do_vmaddwod_u)
679
-TRANS(vmaddwod_d_wu, ALL, gvec_vvv, MO_32, do_vmaddwod_u)
680
+TRANS(vmaddwod_h_bu, LSX, gvec_vvv, MO_8, do_vmaddwod_u)
681
+TRANS(vmaddwod_w_hu, LSX, gvec_vvv, MO_16, do_vmaddwod_u)
682
+TRANS(vmaddwod_d_wu, LSX, gvec_vvv, MO_32, do_vmaddwod_u)
683
684
static void gen_vmaddwev_u_s(unsigned vece, TCGv_vec t, TCGv_vec a, TCGv_vec b)
685
{
686
@@ -XXX,XX +XXX,XX @@ static void do_vmaddwev_u_s(unsigned vece, uint32_t vd_ofs, uint32_t vj_ofs,
687
tcg_gen_gvec_3(vd_ofs, vj_ofs, vk_ofs, oprsz, maxsz, &op[vece]);
688
}
689
690
-TRANS(vmaddwev_h_bu_b, ALL, gvec_vvv, MO_8, do_vmaddwev_u_s)
691
-TRANS(vmaddwev_w_hu_h, ALL, gvec_vvv, MO_16, do_vmaddwev_u_s)
692
-TRANS(vmaddwev_d_wu_w, ALL, gvec_vvv, MO_32, do_vmaddwev_u_s)
693
+TRANS(vmaddwev_h_bu_b, LSX, gvec_vvv, MO_8, do_vmaddwev_u_s)
694
+TRANS(vmaddwev_w_hu_h, LSX, gvec_vvv, MO_16, do_vmaddwev_u_s)
695
+TRANS(vmaddwev_d_wu_w, LSX, gvec_vvv, MO_32, do_vmaddwev_u_s)
696
697
static void gen_vmaddwod_u_s(unsigned vece, TCGv_vec t, TCGv_vec a, TCGv_vec b)
698
{
699
@@ -XXX,XX +XXX,XX @@ static void do_vmaddwod_u_s(unsigned vece, uint32_t vd_ofs, uint32_t vj_ofs,
700
tcg_gen_gvec_3(vd_ofs, vj_ofs, vk_ofs, oprsz, maxsz, &op[vece]);
701
}
702
703
-TRANS(vmaddwod_h_bu_b, ALL, gvec_vvv, MO_8, do_vmaddwod_u_s)
704
-TRANS(vmaddwod_w_hu_h, ALL, gvec_vvv, MO_16, do_vmaddwod_u_s)
705
-TRANS(vmaddwod_d_wu_w, ALL, gvec_vvv, MO_32, do_vmaddwod_u_s)
706
-
707
-TRANS(vdiv_b, ALL, gen_vvv, gen_helper_vdiv_b)
708
-TRANS(vdiv_h, ALL, gen_vvv, gen_helper_vdiv_h)
709
-TRANS(vdiv_w, ALL, gen_vvv, gen_helper_vdiv_w)
710
-TRANS(vdiv_d, ALL, gen_vvv, gen_helper_vdiv_d)
711
-TRANS(vdiv_bu, ALL, gen_vvv, gen_helper_vdiv_bu)
712
-TRANS(vdiv_hu, ALL, gen_vvv, gen_helper_vdiv_hu)
713
-TRANS(vdiv_wu, ALL, gen_vvv, gen_helper_vdiv_wu)
714
-TRANS(vdiv_du, ALL, gen_vvv, gen_helper_vdiv_du)
715
-TRANS(vmod_b, ALL, gen_vvv, gen_helper_vmod_b)
716
-TRANS(vmod_h, ALL, gen_vvv, gen_helper_vmod_h)
717
-TRANS(vmod_w, ALL, gen_vvv, gen_helper_vmod_w)
718
-TRANS(vmod_d, ALL, gen_vvv, gen_helper_vmod_d)
719
-TRANS(vmod_bu, ALL, gen_vvv, gen_helper_vmod_bu)
720
-TRANS(vmod_hu, ALL, gen_vvv, gen_helper_vmod_hu)
721
-TRANS(vmod_wu, ALL, gen_vvv, gen_helper_vmod_wu)
722
-TRANS(vmod_du, ALL, gen_vvv, gen_helper_vmod_du)
723
+TRANS(vmaddwod_h_bu_b, LSX, gvec_vvv, MO_8, do_vmaddwod_u_s)
724
+TRANS(vmaddwod_w_hu_h, LSX, gvec_vvv, MO_16, do_vmaddwod_u_s)
725
+TRANS(vmaddwod_d_wu_w, LSX, gvec_vvv, MO_32, do_vmaddwod_u_s)
726
+
727
+TRANS(vdiv_b, LSX, gen_vvv, gen_helper_vdiv_b)
728
+TRANS(vdiv_h, LSX, gen_vvv, gen_helper_vdiv_h)
729
+TRANS(vdiv_w, LSX, gen_vvv, gen_helper_vdiv_w)
730
+TRANS(vdiv_d, LSX, gen_vvv, gen_helper_vdiv_d)
731
+TRANS(vdiv_bu, LSX, gen_vvv, gen_helper_vdiv_bu)
732
+TRANS(vdiv_hu, LSX, gen_vvv, gen_helper_vdiv_hu)
733
+TRANS(vdiv_wu, LSX, gen_vvv, gen_helper_vdiv_wu)
734
+TRANS(vdiv_du, LSX, gen_vvv, gen_helper_vdiv_du)
735
+TRANS(vmod_b, LSX, gen_vvv, gen_helper_vmod_b)
736
+TRANS(vmod_h, LSX, gen_vvv, gen_helper_vmod_h)
737
+TRANS(vmod_w, LSX, gen_vvv, gen_helper_vmod_w)
738
+TRANS(vmod_d, LSX, gen_vvv, gen_helper_vmod_d)
739
+TRANS(vmod_bu, LSX, gen_vvv, gen_helper_vmod_bu)
740
+TRANS(vmod_hu, LSX, gen_vvv, gen_helper_vmod_hu)
741
+TRANS(vmod_wu, LSX, gen_vvv, gen_helper_vmod_wu)
742
+TRANS(vmod_du, LSX, gen_vvv, gen_helper_vmod_du)
743
744
static void gen_vsat_s(unsigned vece, TCGv_vec t, TCGv_vec a, TCGv_vec max)
745
{
746
@@ -XXX,XX +XXX,XX @@ static void do_vsat_s(unsigned vece, uint32_t vd_ofs, uint32_t vj_ofs,
747
tcg_constant_i64((1ll<< imm) -1), &op[vece]);
748
}
749
750
-TRANS(vsat_b, ALL, gvec_vv_i, MO_8, do_vsat_s)
751
-TRANS(vsat_h, ALL, gvec_vv_i, MO_16, do_vsat_s)
752
-TRANS(vsat_w, ALL, gvec_vv_i, MO_32, do_vsat_s)
753
-TRANS(vsat_d, ALL, gvec_vv_i, MO_64, do_vsat_s)
754
+TRANS(vsat_b, LSX, gvec_vv_i, MO_8, do_vsat_s)
755
+TRANS(vsat_h, LSX, gvec_vv_i, MO_16, do_vsat_s)
756
+TRANS(vsat_w, LSX, gvec_vv_i, MO_32, do_vsat_s)
757
+TRANS(vsat_d, LSX, gvec_vv_i, MO_64, do_vsat_s)
758
759
static void gen_vsat_u(unsigned vece, TCGv_vec t, TCGv_vec a, TCGv_vec max)
760
{
761
@@ -XXX,XX +XXX,XX @@ static void do_vsat_u(unsigned vece, uint32_t vd_ofs, uint32_t vj_ofs,
762
tcg_constant_i64(max), &op[vece]);
763
}
764
765
-TRANS(vsat_bu, ALL, gvec_vv_i, MO_8, do_vsat_u)
766
-TRANS(vsat_hu, ALL, gvec_vv_i, MO_16, do_vsat_u)
767
-TRANS(vsat_wu, ALL, gvec_vv_i, MO_32, do_vsat_u)
768
-TRANS(vsat_du, ALL, gvec_vv_i, MO_64, do_vsat_u)
769
+TRANS(vsat_bu, LSX, gvec_vv_i, MO_8, do_vsat_u)
770
+TRANS(vsat_hu, LSX, gvec_vv_i, MO_16, do_vsat_u)
771
+TRANS(vsat_wu, LSX, gvec_vv_i, MO_32, do_vsat_u)
772
+TRANS(vsat_du, LSX, gvec_vv_i, MO_64, do_vsat_u)
773
774
-TRANS(vexth_h_b, ALL, gen_vv, gen_helper_vexth_h_b)
775
-TRANS(vexth_w_h, ALL, gen_vv, gen_helper_vexth_w_h)
776
-TRANS(vexth_d_w, ALL, gen_vv, gen_helper_vexth_d_w)
777
-TRANS(vexth_q_d, ALL, gen_vv, gen_helper_vexth_q_d)
778
-TRANS(vexth_hu_bu, ALL, gen_vv, gen_helper_vexth_hu_bu)
779
-TRANS(vexth_wu_hu, ALL, gen_vv, gen_helper_vexth_wu_hu)
780
-TRANS(vexth_du_wu, ALL, gen_vv, gen_helper_vexth_du_wu)
781
-TRANS(vexth_qu_du, ALL, gen_vv, gen_helper_vexth_qu_du)
782
+TRANS(vexth_h_b, LSX, gen_vv, gen_helper_vexth_h_b)
783
+TRANS(vexth_w_h, LSX, gen_vv, gen_helper_vexth_w_h)
784
+TRANS(vexth_d_w, LSX, gen_vv, gen_helper_vexth_d_w)
785
+TRANS(vexth_q_d, LSX, gen_vv, gen_helper_vexth_q_d)
786
+TRANS(vexth_hu_bu, LSX, gen_vv, gen_helper_vexth_hu_bu)
787
+TRANS(vexth_wu_hu, LSX, gen_vv, gen_helper_vexth_wu_hu)
788
+TRANS(vexth_du_wu, LSX, gen_vv, gen_helper_vexth_du_wu)
789
+TRANS(vexth_qu_du, LSX, gen_vv, gen_helper_vexth_qu_du)
790
791
static void gen_vsigncov(unsigned vece, TCGv_vec t, TCGv_vec a, TCGv_vec b)
792
{
793
@@ -XXX,XX +XXX,XX @@ static void do_vsigncov(unsigned vece, uint32_t vd_ofs, uint32_t vj_ofs,
794
tcg_gen_gvec_3(vd_ofs, vj_ofs, vk_ofs, oprsz, maxsz, &op[vece]);
795
}
796
797
-TRANS(vsigncov_b, ALL, gvec_vvv, MO_8, do_vsigncov)
798
-TRANS(vsigncov_h, ALL, gvec_vvv, MO_16, do_vsigncov)
799
-TRANS(vsigncov_w, ALL, gvec_vvv, MO_32, do_vsigncov)
800
-TRANS(vsigncov_d, ALL, gvec_vvv, MO_64, do_vsigncov)
801
+TRANS(vsigncov_b, LSX, gvec_vvv, MO_8, do_vsigncov)
802
+TRANS(vsigncov_h, LSX, gvec_vvv, MO_16, do_vsigncov)
803
+TRANS(vsigncov_w, LSX, gvec_vvv, MO_32, do_vsigncov)
804
+TRANS(vsigncov_d, LSX, gvec_vvv, MO_64, do_vsigncov)
805
806
-TRANS(vmskltz_b, ALL, gen_vv, gen_helper_vmskltz_b)
807
-TRANS(vmskltz_h, ALL, gen_vv, gen_helper_vmskltz_h)
808
-TRANS(vmskltz_w, ALL, gen_vv, gen_helper_vmskltz_w)
809
-TRANS(vmskltz_d, ALL, gen_vv, gen_helper_vmskltz_d)
810
-TRANS(vmskgez_b, ALL, gen_vv, gen_helper_vmskgez_b)
811
-TRANS(vmsknz_b, ALL, gen_vv, gen_helper_vmsknz_b)
812
+TRANS(vmskltz_b, LSX, gen_vv, gen_helper_vmskltz_b)
813
+TRANS(vmskltz_h, LSX, gen_vv, gen_helper_vmskltz_h)
814
+TRANS(vmskltz_w, LSX, gen_vv, gen_helper_vmskltz_w)
815
+TRANS(vmskltz_d, LSX, gen_vv, gen_helper_vmskltz_d)
816
+TRANS(vmskgez_b, LSX, gen_vv, gen_helper_vmskgez_b)
817
+TRANS(vmsknz_b, LSX, gen_vv, gen_helper_vmsknz_b)
818
819
#define EXPAND_BYTE(bit) ((uint64_t)(bit ? 0xff : 0))
820
821
@@ -XXX,XX +XXX,XX @@ static bool trans_vldi(DisasContext *ctx, arg_vldi *a)
822
{
823
int sel, vece;
824
uint64_t value;
825
+
826
+ if (!avail_LSX(ctx)) {
827
+ return false;
828
+ }
829
+
830
CHECK_SXE;
831
832
sel = (a->imm >> 12) & 0x1;
833
@@ -XXX,XX +XXX,XX @@ static bool trans_vldi(DisasContext *ctx, arg_vldi *a)
834
return true;
835
}
836
837
-TRANS(vand_v, ALL, gvec_vvv, MO_64, tcg_gen_gvec_and)
838
-TRANS(vor_v, ALL, gvec_vvv, MO_64, tcg_gen_gvec_or)
839
-TRANS(vxor_v, ALL, gvec_vvv, MO_64, tcg_gen_gvec_xor)
840
-TRANS(vnor_v, ALL, gvec_vvv, MO_64, tcg_gen_gvec_nor)
841
+TRANS(vand_v, LSX, gvec_vvv, MO_64, tcg_gen_gvec_and)
842
+TRANS(vor_v, LSX, gvec_vvv, MO_64, tcg_gen_gvec_or)
843
+TRANS(vxor_v, LSX, gvec_vvv, MO_64, tcg_gen_gvec_xor)
844
+TRANS(vnor_v, LSX, gvec_vvv, MO_64, tcg_gen_gvec_nor)
845
846
static bool trans_vandn_v(DisasContext *ctx, arg_vvv *a)
847
{
848
uint32_t vd_ofs, vj_ofs, vk_ofs;
849
850
+ if (!avail_LSX(ctx)) {
851
+ return false;
852
+ }
853
+
854
CHECK_SXE;
855
856
vd_ofs = vec_full_offset(a->vd);
857
@@ -XXX,XX +XXX,XX @@ static bool trans_vandn_v(DisasContext *ctx, arg_vvv *a)
858
tcg_gen_gvec_andc(MO_64, vd_ofs, vk_ofs, vj_ofs, 16, ctx->vl/8);
859
return true;
860
}
861
-TRANS(vorn_v, ALL, gvec_vvv, MO_64, tcg_gen_gvec_orc)
862
-TRANS(vandi_b, ALL, gvec_vv_i, MO_8, tcg_gen_gvec_andi)
863
-TRANS(vori_b, ALL, gvec_vv_i, MO_8, tcg_gen_gvec_ori)
864
-TRANS(vxori_b, ALL, gvec_vv_i, MO_8, tcg_gen_gvec_xori)
865
+TRANS(vorn_v, LSX, gvec_vvv, MO_64, tcg_gen_gvec_orc)
866
+TRANS(vandi_b, LSX, gvec_vv_i, MO_8, tcg_gen_gvec_andi)
867
+TRANS(vori_b, LSX, gvec_vv_i, MO_8, tcg_gen_gvec_ori)
868
+TRANS(vxori_b, LSX, gvec_vv_i, MO_8, tcg_gen_gvec_xori)
869
870
static void gen_vnori(unsigned vece, TCGv_vec t, TCGv_vec a, int64_t imm)
871
{
872
@@ -XXX,XX +XXX,XX @@ static void do_vnori_b(unsigned vece, uint32_t vd_ofs, uint32_t vj_ofs,
873
tcg_gen_gvec_2i(vd_ofs, vj_ofs, oprsz, maxsz, imm, &op);
874
}
875
876
-TRANS(vnori_b, ALL, gvec_vv_i, MO_8, do_vnori_b)
877
-
878
-TRANS(vsll_b, ALL, gvec_vvv, MO_8, tcg_gen_gvec_shlv)
879
-TRANS(vsll_h, ALL, gvec_vvv, MO_16, tcg_gen_gvec_shlv)
880
-TRANS(vsll_w, ALL, gvec_vvv, MO_32, tcg_gen_gvec_shlv)
881
-TRANS(vsll_d, ALL, gvec_vvv, MO_64, tcg_gen_gvec_shlv)
882
-TRANS(vslli_b, ALL, gvec_vv_i, MO_8, tcg_gen_gvec_shli)
883
-TRANS(vslli_h, ALL, gvec_vv_i, MO_16, tcg_gen_gvec_shli)
884
-TRANS(vslli_w, ALL, gvec_vv_i, MO_32, tcg_gen_gvec_shli)
885
-TRANS(vslli_d, ALL, gvec_vv_i, MO_64, tcg_gen_gvec_shli)
886
-
887
-TRANS(vsrl_b, ALL, gvec_vvv, MO_8, tcg_gen_gvec_shrv)
888
-TRANS(vsrl_h, ALL, gvec_vvv, MO_16, tcg_gen_gvec_shrv)
889
-TRANS(vsrl_w, ALL, gvec_vvv, MO_32, tcg_gen_gvec_shrv)
890
-TRANS(vsrl_d, ALL, gvec_vvv, MO_64, tcg_gen_gvec_shrv)
891
-TRANS(vsrli_b, ALL, gvec_vv_i, MO_8, tcg_gen_gvec_shri)
892
-TRANS(vsrli_h, ALL, gvec_vv_i, MO_16, tcg_gen_gvec_shri)
893
-TRANS(vsrli_w, ALL, gvec_vv_i, MO_32, tcg_gen_gvec_shri)
894
-TRANS(vsrli_d, ALL, gvec_vv_i, MO_64, tcg_gen_gvec_shri)
895
-
896
-TRANS(vsra_b, ALL, gvec_vvv, MO_8, tcg_gen_gvec_sarv)
897
-TRANS(vsra_h, ALL, gvec_vvv, MO_16, tcg_gen_gvec_sarv)
898
-TRANS(vsra_w, ALL, gvec_vvv, MO_32, tcg_gen_gvec_sarv)
899
-TRANS(vsra_d, ALL, gvec_vvv, MO_64, tcg_gen_gvec_sarv)
900
-TRANS(vsrai_b, ALL, gvec_vv_i, MO_8, tcg_gen_gvec_sari)
901
-TRANS(vsrai_h, ALL, gvec_vv_i, MO_16, tcg_gen_gvec_sari)
902
-TRANS(vsrai_w, ALL, gvec_vv_i, MO_32, tcg_gen_gvec_sari)
903
-TRANS(vsrai_d, ALL, gvec_vv_i, MO_64, tcg_gen_gvec_sari)
904
-
905
-TRANS(vrotr_b, ALL, gvec_vvv, MO_8, tcg_gen_gvec_rotrv)
906
-TRANS(vrotr_h, ALL, gvec_vvv, MO_16, tcg_gen_gvec_rotrv)
907
-TRANS(vrotr_w, ALL, gvec_vvv, MO_32, tcg_gen_gvec_rotrv)
908
-TRANS(vrotr_d, ALL, gvec_vvv, MO_64, tcg_gen_gvec_rotrv)
909
-TRANS(vrotri_b, ALL, gvec_vv_i, MO_8, tcg_gen_gvec_rotri)
910
-TRANS(vrotri_h, ALL, gvec_vv_i, MO_16, tcg_gen_gvec_rotri)
911
-TRANS(vrotri_w, ALL, gvec_vv_i, MO_32, tcg_gen_gvec_rotri)
912
-TRANS(vrotri_d, ALL, gvec_vv_i, MO_64, tcg_gen_gvec_rotri)
913
-
914
-TRANS(vsllwil_h_b, ALL, gen_vv_i, gen_helper_vsllwil_h_b)
915
-TRANS(vsllwil_w_h, ALL, gen_vv_i, gen_helper_vsllwil_w_h)
916
-TRANS(vsllwil_d_w, ALL, gen_vv_i, gen_helper_vsllwil_d_w)
917
-TRANS(vextl_q_d, ALL, gen_vv, gen_helper_vextl_q_d)
918
-TRANS(vsllwil_hu_bu, ALL, gen_vv_i, gen_helper_vsllwil_hu_bu)
919
-TRANS(vsllwil_wu_hu, ALL, gen_vv_i, gen_helper_vsllwil_wu_hu)
920
-TRANS(vsllwil_du_wu, ALL, gen_vv_i, gen_helper_vsllwil_du_wu)
921
-TRANS(vextl_qu_du, ALL, gen_vv, gen_helper_vextl_qu_du)
922
-
923
-TRANS(vsrlr_b, ALL, gen_vvv, gen_helper_vsrlr_b)
924
-TRANS(vsrlr_h, ALL, gen_vvv, gen_helper_vsrlr_h)
925
-TRANS(vsrlr_w, ALL, gen_vvv, gen_helper_vsrlr_w)
926
-TRANS(vsrlr_d, ALL, gen_vvv, gen_helper_vsrlr_d)
927
-TRANS(vsrlri_b, ALL, gen_vv_i, gen_helper_vsrlri_b)
928
-TRANS(vsrlri_h, ALL, gen_vv_i, gen_helper_vsrlri_h)
929
-TRANS(vsrlri_w, ALL, gen_vv_i, gen_helper_vsrlri_w)
930
-TRANS(vsrlri_d, ALL, gen_vv_i, gen_helper_vsrlri_d)
931
-
932
-TRANS(vsrar_b, ALL, gen_vvv, gen_helper_vsrar_b)
933
-TRANS(vsrar_h, ALL, gen_vvv, gen_helper_vsrar_h)
934
-TRANS(vsrar_w, ALL, gen_vvv, gen_helper_vsrar_w)
935
-TRANS(vsrar_d, ALL, gen_vvv, gen_helper_vsrar_d)
936
-TRANS(vsrari_b, ALL, gen_vv_i, gen_helper_vsrari_b)
937
-TRANS(vsrari_h, ALL, gen_vv_i, gen_helper_vsrari_h)
938
-TRANS(vsrari_w, ALL, gen_vv_i, gen_helper_vsrari_w)
939
-TRANS(vsrari_d, ALL, gen_vv_i, gen_helper_vsrari_d)
940
-
941
-TRANS(vsrln_b_h, ALL, gen_vvv, gen_helper_vsrln_b_h)
942
-TRANS(vsrln_h_w, ALL, gen_vvv, gen_helper_vsrln_h_w)
943
-TRANS(vsrln_w_d, ALL, gen_vvv, gen_helper_vsrln_w_d)
944
-TRANS(vsran_b_h, ALL, gen_vvv, gen_helper_vsran_b_h)
945
-TRANS(vsran_h_w, ALL, gen_vvv, gen_helper_vsran_h_w)
946
-TRANS(vsran_w_d, ALL, gen_vvv, gen_helper_vsran_w_d)
947
-
948
-TRANS(vsrlni_b_h, ALL, gen_vv_i, gen_helper_vsrlni_b_h)
949
-TRANS(vsrlni_h_w, ALL, gen_vv_i, gen_helper_vsrlni_h_w)
950
-TRANS(vsrlni_w_d, ALL, gen_vv_i, gen_helper_vsrlni_w_d)
951
-TRANS(vsrlni_d_q, ALL, gen_vv_i, gen_helper_vsrlni_d_q)
952
-TRANS(vsrani_b_h, ALL, gen_vv_i, gen_helper_vsrani_b_h)
953
-TRANS(vsrani_h_w, ALL, gen_vv_i, gen_helper_vsrani_h_w)
954
-TRANS(vsrani_w_d, ALL, gen_vv_i, gen_helper_vsrani_w_d)
955
-TRANS(vsrani_d_q, ALL, gen_vv_i, gen_helper_vsrani_d_q)
956
-
957
-TRANS(vsrlrn_b_h, ALL, gen_vvv, gen_helper_vsrlrn_b_h)
958
-TRANS(vsrlrn_h_w, ALL, gen_vvv, gen_helper_vsrlrn_h_w)
959
-TRANS(vsrlrn_w_d, ALL, gen_vvv, gen_helper_vsrlrn_w_d)
960
-TRANS(vsrarn_b_h, ALL, gen_vvv, gen_helper_vsrarn_b_h)
961
-TRANS(vsrarn_h_w, ALL, gen_vvv, gen_helper_vsrarn_h_w)
962
-TRANS(vsrarn_w_d, ALL, gen_vvv, gen_helper_vsrarn_w_d)
963
-
964
-TRANS(vsrlrni_b_h, ALL, gen_vv_i, gen_helper_vsrlrni_b_h)
965
-TRANS(vsrlrni_h_w, ALL, gen_vv_i, gen_helper_vsrlrni_h_w)
966
-TRANS(vsrlrni_w_d, ALL, gen_vv_i, gen_helper_vsrlrni_w_d)
967
-TRANS(vsrlrni_d_q, ALL, gen_vv_i, gen_helper_vsrlrni_d_q)
968
-TRANS(vsrarni_b_h, ALL, gen_vv_i, gen_helper_vsrarni_b_h)
969
-TRANS(vsrarni_h_w, ALL, gen_vv_i, gen_helper_vsrarni_h_w)
970
-TRANS(vsrarni_w_d, ALL, gen_vv_i, gen_helper_vsrarni_w_d)
971
-TRANS(vsrarni_d_q, ALL, gen_vv_i, gen_helper_vsrarni_d_q)
972
-
973
-TRANS(vssrln_b_h, ALL, gen_vvv, gen_helper_vssrln_b_h)
974
-TRANS(vssrln_h_w, ALL, gen_vvv, gen_helper_vssrln_h_w)
975
-TRANS(vssrln_w_d, ALL, gen_vvv, gen_helper_vssrln_w_d)
976
-TRANS(vssran_b_h, ALL, gen_vvv, gen_helper_vssran_b_h)
977
-TRANS(vssran_h_w, ALL, gen_vvv, gen_helper_vssran_h_w)
978
-TRANS(vssran_w_d, ALL, gen_vvv, gen_helper_vssran_w_d)
979
-TRANS(vssrln_bu_h, ALL, gen_vvv, gen_helper_vssrln_bu_h)
980
-TRANS(vssrln_hu_w, ALL, gen_vvv, gen_helper_vssrln_hu_w)
981
-TRANS(vssrln_wu_d, ALL, gen_vvv, gen_helper_vssrln_wu_d)
982
-TRANS(vssran_bu_h, ALL, gen_vvv, gen_helper_vssran_bu_h)
983
-TRANS(vssran_hu_w, ALL, gen_vvv, gen_helper_vssran_hu_w)
984
-TRANS(vssran_wu_d, ALL, gen_vvv, gen_helper_vssran_wu_d)
985
-
986
-TRANS(vssrlni_b_h, ALL, gen_vv_i, gen_helper_vssrlni_b_h)
987
-TRANS(vssrlni_h_w, ALL, gen_vv_i, gen_helper_vssrlni_h_w)
988
-TRANS(vssrlni_w_d, ALL, gen_vv_i, gen_helper_vssrlni_w_d)
989
-TRANS(vssrlni_d_q, ALL, gen_vv_i, gen_helper_vssrlni_d_q)
990
-TRANS(vssrani_b_h, ALL, gen_vv_i, gen_helper_vssrani_b_h)
991
-TRANS(vssrani_h_w, ALL, gen_vv_i, gen_helper_vssrani_h_w)
992
-TRANS(vssrani_w_d, ALL, gen_vv_i, gen_helper_vssrani_w_d)
993
-TRANS(vssrani_d_q, ALL, gen_vv_i, gen_helper_vssrani_d_q)
994
-TRANS(vssrlni_bu_h, ALL, gen_vv_i, gen_helper_vssrlni_bu_h)
995
-TRANS(vssrlni_hu_w, ALL, gen_vv_i, gen_helper_vssrlni_hu_w)
996
-TRANS(vssrlni_wu_d, ALL, gen_vv_i, gen_helper_vssrlni_wu_d)
997
-TRANS(vssrlni_du_q, ALL, gen_vv_i, gen_helper_vssrlni_du_q)
998
-TRANS(vssrani_bu_h, ALL, gen_vv_i, gen_helper_vssrani_bu_h)
999
-TRANS(vssrani_hu_w, ALL, gen_vv_i, gen_helper_vssrani_hu_w)
1000
-TRANS(vssrani_wu_d, ALL, gen_vv_i, gen_helper_vssrani_wu_d)
1001
-TRANS(vssrani_du_q, ALL, gen_vv_i, gen_helper_vssrani_du_q)
1002
-
1003
-TRANS(vssrlrn_b_h, ALL, gen_vvv, gen_helper_vssrlrn_b_h)
1004
-TRANS(vssrlrn_h_w, ALL, gen_vvv, gen_helper_vssrlrn_h_w)
1005
-TRANS(vssrlrn_w_d, ALL, gen_vvv, gen_helper_vssrlrn_w_d)
1006
-TRANS(vssrarn_b_h, ALL, gen_vvv, gen_helper_vssrarn_b_h)
1007
-TRANS(vssrarn_h_w, ALL, gen_vvv, gen_helper_vssrarn_h_w)
1008
-TRANS(vssrarn_w_d, ALL, gen_vvv, gen_helper_vssrarn_w_d)
1009
-TRANS(vssrlrn_bu_h, ALL, gen_vvv, gen_helper_vssrlrn_bu_h)
1010
-TRANS(vssrlrn_hu_w, ALL, gen_vvv, gen_helper_vssrlrn_hu_w)
1011
-TRANS(vssrlrn_wu_d, ALL, gen_vvv, gen_helper_vssrlrn_wu_d)
1012
-TRANS(vssrarn_bu_h, ALL, gen_vvv, gen_helper_vssrarn_bu_h)
1013
-TRANS(vssrarn_hu_w, ALL, gen_vvv, gen_helper_vssrarn_hu_w)
1014
-TRANS(vssrarn_wu_d, ALL, gen_vvv, gen_helper_vssrarn_wu_d)
1015
-
1016
-TRANS(vssrlrni_b_h, ALL, gen_vv_i, gen_helper_vssrlrni_b_h)
1017
-TRANS(vssrlrni_h_w, ALL, gen_vv_i, gen_helper_vssrlrni_h_w)
1018
-TRANS(vssrlrni_w_d, ALL, gen_vv_i, gen_helper_vssrlrni_w_d)
1019
-TRANS(vssrlrni_d_q, ALL, gen_vv_i, gen_helper_vssrlrni_d_q)
1020
-TRANS(vssrarni_b_h, ALL, gen_vv_i, gen_helper_vssrarni_b_h)
1021
-TRANS(vssrarni_h_w, ALL, gen_vv_i, gen_helper_vssrarni_h_w)
1022
-TRANS(vssrarni_w_d, ALL, gen_vv_i, gen_helper_vssrarni_w_d)
1023
-TRANS(vssrarni_d_q, ALL, gen_vv_i, gen_helper_vssrarni_d_q)
1024
-TRANS(vssrlrni_bu_h, ALL, gen_vv_i, gen_helper_vssrlrni_bu_h)
1025
-TRANS(vssrlrni_hu_w, ALL, gen_vv_i, gen_helper_vssrlrni_hu_w)
1026
-TRANS(vssrlrni_wu_d, ALL, gen_vv_i, gen_helper_vssrlrni_wu_d)
1027
-TRANS(vssrlrni_du_q, ALL, gen_vv_i, gen_helper_vssrlrni_du_q)
1028
-TRANS(vssrarni_bu_h, ALL, gen_vv_i, gen_helper_vssrarni_bu_h)
1029
-TRANS(vssrarni_hu_w, ALL, gen_vv_i, gen_helper_vssrarni_hu_w)
1030
-TRANS(vssrarni_wu_d, ALL, gen_vv_i, gen_helper_vssrarni_wu_d)
1031
-TRANS(vssrarni_du_q, ALL, gen_vv_i, gen_helper_vssrarni_du_q)
1032
-
1033
-TRANS(vclo_b, ALL, gen_vv, gen_helper_vclo_b)
1034
-TRANS(vclo_h, ALL, gen_vv, gen_helper_vclo_h)
1035
-TRANS(vclo_w, ALL, gen_vv, gen_helper_vclo_w)
1036
-TRANS(vclo_d, ALL, gen_vv, gen_helper_vclo_d)
1037
-TRANS(vclz_b, ALL, gen_vv, gen_helper_vclz_b)
1038
-TRANS(vclz_h, ALL, gen_vv, gen_helper_vclz_h)
1039
-TRANS(vclz_w, ALL, gen_vv, gen_helper_vclz_w)
1040
-TRANS(vclz_d, ALL, gen_vv, gen_helper_vclz_d)
1041
-
1042
-TRANS(vpcnt_b, ALL, gen_vv, gen_helper_vpcnt_b)
1043
-TRANS(vpcnt_h, ALL, gen_vv, gen_helper_vpcnt_h)
1044
-TRANS(vpcnt_w, ALL, gen_vv, gen_helper_vpcnt_w)
1045
-TRANS(vpcnt_d, ALL, gen_vv, gen_helper_vpcnt_d)
1046
+TRANS(vnori_b, LSX, gvec_vv_i, MO_8, do_vnori_b)
1047
+
1048
+TRANS(vsll_b, LSX, gvec_vvv, MO_8, tcg_gen_gvec_shlv)
1049
+TRANS(vsll_h, LSX, gvec_vvv, MO_16, tcg_gen_gvec_shlv)
1050
+TRANS(vsll_w, LSX, gvec_vvv, MO_32, tcg_gen_gvec_shlv)
1051
+TRANS(vsll_d, LSX, gvec_vvv, MO_64, tcg_gen_gvec_shlv)
1052
+TRANS(vslli_b, LSX, gvec_vv_i, MO_8, tcg_gen_gvec_shli)
1053
+TRANS(vslli_h, LSX, gvec_vv_i, MO_16, tcg_gen_gvec_shli)
1054
+TRANS(vslli_w, LSX, gvec_vv_i, MO_32, tcg_gen_gvec_shli)
1055
+TRANS(vslli_d, LSX, gvec_vv_i, MO_64, tcg_gen_gvec_shli)
1056
+
1057
+TRANS(vsrl_b, LSX, gvec_vvv, MO_8, tcg_gen_gvec_shrv)
1058
+TRANS(vsrl_h, LSX, gvec_vvv, MO_16, tcg_gen_gvec_shrv)
1059
+TRANS(vsrl_w, LSX, gvec_vvv, MO_32, tcg_gen_gvec_shrv)
1060
+TRANS(vsrl_d, LSX, gvec_vvv, MO_64, tcg_gen_gvec_shrv)
1061
+TRANS(vsrli_b, LSX, gvec_vv_i, MO_8, tcg_gen_gvec_shri)
1062
+TRANS(vsrli_h, LSX, gvec_vv_i, MO_16, tcg_gen_gvec_shri)
1063
+TRANS(vsrli_w, LSX, gvec_vv_i, MO_32, tcg_gen_gvec_shri)
1064
+TRANS(vsrli_d, LSX, gvec_vv_i, MO_64, tcg_gen_gvec_shri)
1065
+
1066
+TRANS(vsra_b, LSX, gvec_vvv, MO_8, tcg_gen_gvec_sarv)
1067
+TRANS(vsra_h, LSX, gvec_vvv, MO_16, tcg_gen_gvec_sarv)
1068
+TRANS(vsra_w, LSX, gvec_vvv, MO_32, tcg_gen_gvec_sarv)
1069
+TRANS(vsra_d, LSX, gvec_vvv, MO_64, tcg_gen_gvec_sarv)
1070
+TRANS(vsrai_b, LSX, gvec_vv_i, MO_8, tcg_gen_gvec_sari)
1071
+TRANS(vsrai_h, LSX, gvec_vv_i, MO_16, tcg_gen_gvec_sari)
1072
+TRANS(vsrai_w, LSX, gvec_vv_i, MO_32, tcg_gen_gvec_sari)
1073
+TRANS(vsrai_d, LSX, gvec_vv_i, MO_64, tcg_gen_gvec_sari)
1074
+
1075
+TRANS(vrotr_b, LSX, gvec_vvv, MO_8, tcg_gen_gvec_rotrv)
1076
+TRANS(vrotr_h, LSX, gvec_vvv, MO_16, tcg_gen_gvec_rotrv)
1077
+TRANS(vrotr_w, LSX, gvec_vvv, MO_32, tcg_gen_gvec_rotrv)
1078
+TRANS(vrotr_d, LSX, gvec_vvv, MO_64, tcg_gen_gvec_rotrv)
1079
+TRANS(vrotri_b, LSX, gvec_vv_i, MO_8, tcg_gen_gvec_rotri)
1080
+TRANS(vrotri_h, LSX, gvec_vv_i, MO_16, tcg_gen_gvec_rotri)
1081
+TRANS(vrotri_w, LSX, gvec_vv_i, MO_32, tcg_gen_gvec_rotri)
1082
+TRANS(vrotri_d, LSX, gvec_vv_i, MO_64, tcg_gen_gvec_rotri)
1083
+
1084
+TRANS(vsllwil_h_b, LSX, gen_vv_i, gen_helper_vsllwil_h_b)
1085
+TRANS(vsllwil_w_h, LSX, gen_vv_i, gen_helper_vsllwil_w_h)
1086
+TRANS(vsllwil_d_w, LSX, gen_vv_i, gen_helper_vsllwil_d_w)
1087
+TRANS(vextl_q_d, LSX, gen_vv, gen_helper_vextl_q_d)
1088
+TRANS(vsllwil_hu_bu, LSX, gen_vv_i, gen_helper_vsllwil_hu_bu)
1089
+TRANS(vsllwil_wu_hu, LSX, gen_vv_i, gen_helper_vsllwil_wu_hu)
1090
+TRANS(vsllwil_du_wu, LSX, gen_vv_i, gen_helper_vsllwil_du_wu)
1091
+TRANS(vextl_qu_du, LSX, gen_vv, gen_helper_vextl_qu_du)
1092
+
1093
+TRANS(vsrlr_b, LSX, gen_vvv, gen_helper_vsrlr_b)
1094
+TRANS(vsrlr_h, LSX, gen_vvv, gen_helper_vsrlr_h)
1095
+TRANS(vsrlr_w, LSX, gen_vvv, gen_helper_vsrlr_w)
1096
+TRANS(vsrlr_d, LSX, gen_vvv, gen_helper_vsrlr_d)
1097
+TRANS(vsrlri_b, LSX, gen_vv_i, gen_helper_vsrlri_b)
1098
+TRANS(vsrlri_h, LSX, gen_vv_i, gen_helper_vsrlri_h)
1099
+TRANS(vsrlri_w, LSX, gen_vv_i, gen_helper_vsrlri_w)
1100
+TRANS(vsrlri_d, LSX, gen_vv_i, gen_helper_vsrlri_d)
1101
+
1102
+TRANS(vsrar_b, LSX, gen_vvv, gen_helper_vsrar_b)
1103
+TRANS(vsrar_h, LSX, gen_vvv, gen_helper_vsrar_h)
1104
+TRANS(vsrar_w, LSX, gen_vvv, gen_helper_vsrar_w)
1105
+TRANS(vsrar_d, LSX, gen_vvv, gen_helper_vsrar_d)
1106
+TRANS(vsrari_b, LSX, gen_vv_i, gen_helper_vsrari_b)
1107
+TRANS(vsrari_h, LSX, gen_vv_i, gen_helper_vsrari_h)
1108
+TRANS(vsrari_w, LSX, gen_vv_i, gen_helper_vsrari_w)
1109
+TRANS(vsrari_d, LSX, gen_vv_i, gen_helper_vsrari_d)
1110
+
1111
+TRANS(vsrln_b_h, LSX, gen_vvv, gen_helper_vsrln_b_h)
1112
+TRANS(vsrln_h_w, LSX, gen_vvv, gen_helper_vsrln_h_w)
1113
+TRANS(vsrln_w_d, LSX, gen_vvv, gen_helper_vsrln_w_d)
1114
+TRANS(vsran_b_h, LSX, gen_vvv, gen_helper_vsran_b_h)
1115
+TRANS(vsran_h_w, LSX, gen_vvv, gen_helper_vsran_h_w)
1116
+TRANS(vsran_w_d, LSX, gen_vvv, gen_helper_vsran_w_d)
1117
+
1118
+TRANS(vsrlni_b_h, LSX, gen_vv_i, gen_helper_vsrlni_b_h)
1119
+TRANS(vsrlni_h_w, LSX, gen_vv_i, gen_helper_vsrlni_h_w)
1120
+TRANS(vsrlni_w_d, LSX, gen_vv_i, gen_helper_vsrlni_w_d)
1121
+TRANS(vsrlni_d_q, LSX, gen_vv_i, gen_helper_vsrlni_d_q)
1122
+TRANS(vsrani_b_h, LSX, gen_vv_i, gen_helper_vsrani_b_h)
1123
+TRANS(vsrani_h_w, LSX, gen_vv_i, gen_helper_vsrani_h_w)
1124
+TRANS(vsrani_w_d, LSX, gen_vv_i, gen_helper_vsrani_w_d)
1125
+TRANS(vsrani_d_q, LSX, gen_vv_i, gen_helper_vsrani_d_q)
1126
+
1127
+TRANS(vsrlrn_b_h, LSX, gen_vvv, gen_helper_vsrlrn_b_h)
1128
+TRANS(vsrlrn_h_w, LSX, gen_vvv, gen_helper_vsrlrn_h_w)
1129
+TRANS(vsrlrn_w_d, LSX, gen_vvv, gen_helper_vsrlrn_w_d)
1130
+TRANS(vsrarn_b_h, LSX, gen_vvv, gen_helper_vsrarn_b_h)
1131
+TRANS(vsrarn_h_w, LSX, gen_vvv, gen_helper_vsrarn_h_w)
1132
+TRANS(vsrarn_w_d, LSX, gen_vvv, gen_helper_vsrarn_w_d)
1133
+
1134
+TRANS(vsrlrni_b_h, LSX, gen_vv_i, gen_helper_vsrlrni_b_h)
1135
+TRANS(vsrlrni_h_w, LSX, gen_vv_i, gen_helper_vsrlrni_h_w)
1136
+TRANS(vsrlrni_w_d, LSX, gen_vv_i, gen_helper_vsrlrni_w_d)
1137
+TRANS(vsrlrni_d_q, LSX, gen_vv_i, gen_helper_vsrlrni_d_q)
1138
+TRANS(vsrarni_b_h, LSX, gen_vv_i, gen_helper_vsrarni_b_h)
1139
+TRANS(vsrarni_h_w, LSX, gen_vv_i, gen_helper_vsrarni_h_w)
1140
+TRANS(vsrarni_w_d, LSX, gen_vv_i, gen_helper_vsrarni_w_d)
1141
+TRANS(vsrarni_d_q, LSX, gen_vv_i, gen_helper_vsrarni_d_q)
1142
+
1143
+TRANS(vssrln_b_h, LSX, gen_vvv, gen_helper_vssrln_b_h)
1144
+TRANS(vssrln_h_w, LSX, gen_vvv, gen_helper_vssrln_h_w)
1145
+TRANS(vssrln_w_d, LSX, gen_vvv, gen_helper_vssrln_w_d)
1146
+TRANS(vssran_b_h, LSX, gen_vvv, gen_helper_vssran_b_h)
1147
+TRANS(vssran_h_w, LSX, gen_vvv, gen_helper_vssran_h_w)
1148
+TRANS(vssran_w_d, LSX, gen_vvv, gen_helper_vssran_w_d)
1149
+TRANS(vssrln_bu_h, LSX, gen_vvv, gen_helper_vssrln_bu_h)
1150
+TRANS(vssrln_hu_w, LSX, gen_vvv, gen_helper_vssrln_hu_w)
1151
+TRANS(vssrln_wu_d, LSX, gen_vvv, gen_helper_vssrln_wu_d)
1152
+TRANS(vssran_bu_h, LSX, gen_vvv, gen_helper_vssran_bu_h)
1153
+TRANS(vssran_hu_w, LSX, gen_vvv, gen_helper_vssran_hu_w)
1154
+TRANS(vssran_wu_d, LSX, gen_vvv, gen_helper_vssran_wu_d)
1155
+
1156
+TRANS(vssrlni_b_h, LSX, gen_vv_i, gen_helper_vssrlni_b_h)
1157
+TRANS(vssrlni_h_w, LSX, gen_vv_i, gen_helper_vssrlni_h_w)
1158
+TRANS(vssrlni_w_d, LSX, gen_vv_i, gen_helper_vssrlni_w_d)
1159
+TRANS(vssrlni_d_q, LSX, gen_vv_i, gen_helper_vssrlni_d_q)
1160
+TRANS(vssrani_b_h, LSX, gen_vv_i, gen_helper_vssrani_b_h)
1161
+TRANS(vssrani_h_w, LSX, gen_vv_i, gen_helper_vssrani_h_w)
1162
+TRANS(vssrani_w_d, LSX, gen_vv_i, gen_helper_vssrani_w_d)
1163
+TRANS(vssrani_d_q, LSX, gen_vv_i, gen_helper_vssrani_d_q)
1164
+TRANS(vssrlni_bu_h, LSX, gen_vv_i, gen_helper_vssrlni_bu_h)
1165
+TRANS(vssrlni_hu_w, LSX, gen_vv_i, gen_helper_vssrlni_hu_w)
1166
+TRANS(vssrlni_wu_d, LSX, gen_vv_i, gen_helper_vssrlni_wu_d)
1167
+TRANS(vssrlni_du_q, LSX, gen_vv_i, gen_helper_vssrlni_du_q)
1168
+TRANS(vssrani_bu_h, LSX, gen_vv_i, gen_helper_vssrani_bu_h)
1169
+TRANS(vssrani_hu_w, LSX, gen_vv_i, gen_helper_vssrani_hu_w)
1170
+TRANS(vssrani_wu_d, LSX, gen_vv_i, gen_helper_vssrani_wu_d)
1171
+TRANS(vssrani_du_q, LSX, gen_vv_i, gen_helper_vssrani_du_q)
1172
+
1173
+TRANS(vssrlrn_b_h, LSX, gen_vvv, gen_helper_vssrlrn_b_h)
1174
+TRANS(vssrlrn_h_w, LSX, gen_vvv, gen_helper_vssrlrn_h_w)
1175
+TRANS(vssrlrn_w_d, LSX, gen_vvv, gen_helper_vssrlrn_w_d)
1176
+TRANS(vssrarn_b_h, LSX, gen_vvv, gen_helper_vssrarn_b_h)
1177
+TRANS(vssrarn_h_w, LSX, gen_vvv, gen_helper_vssrarn_h_w)
1178
+TRANS(vssrarn_w_d, LSX, gen_vvv, gen_helper_vssrarn_w_d)
1179
+TRANS(vssrlrn_bu_h, LSX, gen_vvv, gen_helper_vssrlrn_bu_h)
1180
+TRANS(vssrlrn_hu_w, LSX, gen_vvv, gen_helper_vssrlrn_hu_w)
1181
+TRANS(vssrlrn_wu_d, LSX, gen_vvv, gen_helper_vssrlrn_wu_d)
1182
+TRANS(vssrarn_bu_h, LSX, gen_vvv, gen_helper_vssrarn_bu_h)
1183
+TRANS(vssrarn_hu_w, LSX, gen_vvv, gen_helper_vssrarn_hu_w)
1184
+TRANS(vssrarn_wu_d, LSX, gen_vvv, gen_helper_vssrarn_wu_d)
1185
+
1186
+TRANS(vssrlrni_b_h, LSX, gen_vv_i, gen_helper_vssrlrni_b_h)
1187
+TRANS(vssrlrni_h_w, LSX, gen_vv_i, gen_helper_vssrlrni_h_w)
1188
+TRANS(vssrlrni_w_d, LSX, gen_vv_i, gen_helper_vssrlrni_w_d)
1189
+TRANS(vssrlrni_d_q, LSX, gen_vv_i, gen_helper_vssrlrni_d_q)
1190
+TRANS(vssrarni_b_h, LSX, gen_vv_i, gen_helper_vssrarni_b_h)
1191
+TRANS(vssrarni_h_w, LSX, gen_vv_i, gen_helper_vssrarni_h_w)
1192
+TRANS(vssrarni_w_d, LSX, gen_vv_i, gen_helper_vssrarni_w_d)
1193
+TRANS(vssrarni_d_q, LSX, gen_vv_i, gen_helper_vssrarni_d_q)
1194
+TRANS(vssrlrni_bu_h, LSX, gen_vv_i, gen_helper_vssrlrni_bu_h)
1195
+TRANS(vssrlrni_hu_w, LSX, gen_vv_i, gen_helper_vssrlrni_hu_w)
1196
+TRANS(vssrlrni_wu_d, LSX, gen_vv_i, gen_helper_vssrlrni_wu_d)
1197
+TRANS(vssrlrni_du_q, LSX, gen_vv_i, gen_helper_vssrlrni_du_q)
1198
+TRANS(vssrarni_bu_h, LSX, gen_vv_i, gen_helper_vssrarni_bu_h)
1199
+TRANS(vssrarni_hu_w, LSX, gen_vv_i, gen_helper_vssrarni_hu_w)
1200
+TRANS(vssrarni_wu_d, LSX, gen_vv_i, gen_helper_vssrarni_wu_d)
1201
+TRANS(vssrarni_du_q, LSX, gen_vv_i, gen_helper_vssrarni_du_q)
1202
+
1203
+TRANS(vclo_b, LSX, gen_vv, gen_helper_vclo_b)
1204
+TRANS(vclo_h, LSX, gen_vv, gen_helper_vclo_h)
1205
+TRANS(vclo_w, LSX, gen_vv, gen_helper_vclo_w)
1206
+TRANS(vclo_d, LSX, gen_vv, gen_helper_vclo_d)
1207
+TRANS(vclz_b, LSX, gen_vv, gen_helper_vclz_b)
1208
+TRANS(vclz_h, LSX, gen_vv, gen_helper_vclz_h)
1209
+TRANS(vclz_w, LSX, gen_vv, gen_helper_vclz_w)
1210
+TRANS(vclz_d, LSX, gen_vv, gen_helper_vclz_d)
1211
+
1212
+TRANS(vpcnt_b, LSX, gen_vv, gen_helper_vpcnt_b)
1213
+TRANS(vpcnt_h, LSX, gen_vv, gen_helper_vpcnt_h)
1214
+TRANS(vpcnt_w, LSX, gen_vv, gen_helper_vpcnt_w)
1215
+TRANS(vpcnt_d, LSX, gen_vv, gen_helper_vpcnt_d)
1216
1217
static void do_vbit(unsigned vece, TCGv_vec t, TCGv_vec a, TCGv_vec b,
1218
void (*func)(unsigned, TCGv_vec, TCGv_vec, TCGv_vec))
1219
@@ -XXX,XX +XXX,XX @@ static void do_vbitclr(unsigned vece, uint32_t vd_ofs, uint32_t vj_ofs,
1220
tcg_gen_gvec_3(vd_ofs, vj_ofs, vk_ofs, oprsz, maxsz, &op[vece]);
1221
}
1222
1223
-TRANS(vbitclr_b, ALL, gvec_vvv, MO_8, do_vbitclr)
1224
-TRANS(vbitclr_h, ALL, gvec_vvv, MO_16, do_vbitclr)
1225
-TRANS(vbitclr_w, ALL, gvec_vvv, MO_32, do_vbitclr)
1226
-TRANS(vbitclr_d, ALL, gvec_vvv, MO_64, do_vbitclr)
1227
+TRANS(vbitclr_b, LSX, gvec_vvv, MO_8, do_vbitclr)
1228
+TRANS(vbitclr_h, LSX, gvec_vvv, MO_16, do_vbitclr)
1229
+TRANS(vbitclr_w, LSX, gvec_vvv, MO_32, do_vbitclr)
1230
+TRANS(vbitclr_d, LSX, gvec_vvv, MO_64, do_vbitclr)
1231
1232
static void do_vbiti(unsigned vece, TCGv_vec t, TCGv_vec a, int64_t imm,
1233
void (*func)(unsigned, TCGv_vec, TCGv_vec, TCGv_vec))
1234
@@ -XXX,XX +XXX,XX @@ static void do_vbitclri(unsigned vece, uint32_t vd_ofs, uint32_t vj_ofs,
1235
tcg_gen_gvec_2i(vd_ofs, vj_ofs, oprsz, maxsz, imm, &op[vece]);
1236
}
1237
1238
-TRANS(vbitclri_b, ALL, gvec_vv_i, MO_8, do_vbitclri)
1239
-TRANS(vbitclri_h, ALL, gvec_vv_i, MO_16, do_vbitclri)
1240
-TRANS(vbitclri_w, ALL, gvec_vv_i, MO_32, do_vbitclri)
1241
-TRANS(vbitclri_d, ALL, gvec_vv_i, MO_64, do_vbitclri)
1242
+TRANS(vbitclri_b, LSX, gvec_vv_i, MO_8, do_vbitclri)
1243
+TRANS(vbitclri_h, LSX, gvec_vv_i, MO_16, do_vbitclri)
1244
+TRANS(vbitclri_w, LSX, gvec_vv_i, MO_32, do_vbitclri)
1245
+TRANS(vbitclri_d, LSX, gvec_vv_i, MO_64, do_vbitclri)
1246
1247
static void do_vbitset(unsigned vece, uint32_t vd_ofs, uint32_t vj_ofs,
1248
uint32_t vk_ofs, uint32_t oprsz, uint32_t maxsz)
1249
@@ -XXX,XX +XXX,XX @@ static void do_vbitset(unsigned vece, uint32_t vd_ofs, uint32_t vj_ofs,
1250
tcg_gen_gvec_3(vd_ofs, vj_ofs, vk_ofs, oprsz, maxsz, &op[vece]);
1251
}
1252
1253
-TRANS(vbitset_b, ALL, gvec_vvv, MO_8, do_vbitset)
1254
-TRANS(vbitset_h, ALL, gvec_vvv, MO_16, do_vbitset)
1255
-TRANS(vbitset_w, ALL, gvec_vvv, MO_32, do_vbitset)
1256
-TRANS(vbitset_d, ALL, gvec_vvv, MO_64, do_vbitset)
1257
+TRANS(vbitset_b, LSX, gvec_vvv, MO_8, do_vbitset)
1258
+TRANS(vbitset_h, LSX, gvec_vvv, MO_16, do_vbitset)
1259
+TRANS(vbitset_w, LSX, gvec_vvv, MO_32, do_vbitset)
1260
+TRANS(vbitset_d, LSX, gvec_vvv, MO_64, do_vbitset)
1261
1262
static void do_vbitseti(unsigned vece, uint32_t vd_ofs, uint32_t vj_ofs,
1263
int64_t imm, uint32_t oprsz, uint32_t maxsz)
1264
@@ -XXX,XX +XXX,XX @@ static void do_vbitseti(unsigned vece, uint32_t vd_ofs, uint32_t vj_ofs,
1265
tcg_gen_gvec_2i(vd_ofs, vj_ofs, oprsz, maxsz, imm, &op[vece]);
1266
}
1267
1268
-TRANS(vbitseti_b, ALL, gvec_vv_i, MO_8, do_vbitseti)
1269
-TRANS(vbitseti_h, ALL, gvec_vv_i, MO_16, do_vbitseti)
1270
-TRANS(vbitseti_w, ALL, gvec_vv_i, MO_32, do_vbitseti)
1271
-TRANS(vbitseti_d, ALL, gvec_vv_i, MO_64, do_vbitseti)
1272
+TRANS(vbitseti_b, LSX, gvec_vv_i, MO_8, do_vbitseti)
1273
+TRANS(vbitseti_h, LSX, gvec_vv_i, MO_16, do_vbitseti)
1274
+TRANS(vbitseti_w, LSX, gvec_vv_i, MO_32, do_vbitseti)
1275
+TRANS(vbitseti_d, LSX, gvec_vv_i, MO_64, do_vbitseti)
1276
1277
static void do_vbitrev(unsigned vece, uint32_t vd_ofs, uint32_t vj_ofs,
1278
uint32_t vk_ofs, uint32_t oprsz, uint32_t maxsz)
1279
@@ -XXX,XX +XXX,XX @@ static void do_vbitrev(unsigned vece, uint32_t vd_ofs, uint32_t vj_ofs,
1280
tcg_gen_gvec_3(vd_ofs, vj_ofs, vk_ofs, oprsz, maxsz, &op[vece]);
1281
}
1282
1283
-TRANS(vbitrev_b, ALL, gvec_vvv, MO_8, do_vbitrev)
1284
-TRANS(vbitrev_h, ALL, gvec_vvv, MO_16, do_vbitrev)
1285
-TRANS(vbitrev_w, ALL, gvec_vvv, MO_32, do_vbitrev)
1286
-TRANS(vbitrev_d, ALL, gvec_vvv, MO_64, do_vbitrev)
1287
+TRANS(vbitrev_b, LSX, gvec_vvv, MO_8, do_vbitrev)
1288
+TRANS(vbitrev_h, LSX, gvec_vvv, MO_16, do_vbitrev)
1289
+TRANS(vbitrev_w, LSX, gvec_vvv, MO_32, do_vbitrev)
1290
+TRANS(vbitrev_d, LSX, gvec_vvv, MO_64, do_vbitrev)
1291
1292
static void do_vbitrevi(unsigned vece, uint32_t vd_ofs, uint32_t vj_ofs,
1293
int64_t imm, uint32_t oprsz, uint32_t maxsz)
1294
@@ -XXX,XX +XXX,XX @@ static void do_vbitrevi(unsigned vece, uint32_t vd_ofs, uint32_t vj_ofs,
1295
tcg_gen_gvec_2i(vd_ofs, vj_ofs, oprsz, maxsz, imm, &op[vece]);
1296
}
1297
1298
-TRANS(vbitrevi_b, ALL, gvec_vv_i, MO_8, do_vbitrevi)
1299
-TRANS(vbitrevi_h, ALL, gvec_vv_i, MO_16, do_vbitrevi)
1300
-TRANS(vbitrevi_w, ALL, gvec_vv_i, MO_32, do_vbitrevi)
1301
-TRANS(vbitrevi_d, ALL, gvec_vv_i, MO_64, do_vbitrevi)
1302
-
1303
-TRANS(vfrstp_b, ALL, gen_vvv, gen_helper_vfrstp_b)
1304
-TRANS(vfrstp_h, ALL, gen_vvv, gen_helper_vfrstp_h)
1305
-TRANS(vfrstpi_b, ALL, gen_vv_i, gen_helper_vfrstpi_b)
1306
-TRANS(vfrstpi_h, ALL, gen_vv_i, gen_helper_vfrstpi_h)
1307
-
1308
-TRANS(vfadd_s, ALL, gen_vvv, gen_helper_vfadd_s)
1309
-TRANS(vfadd_d, ALL, gen_vvv, gen_helper_vfadd_d)
1310
-TRANS(vfsub_s, ALL, gen_vvv, gen_helper_vfsub_s)
1311
-TRANS(vfsub_d, ALL, gen_vvv, gen_helper_vfsub_d)
1312
-TRANS(vfmul_s, ALL, gen_vvv, gen_helper_vfmul_s)
1313
-TRANS(vfmul_d, ALL, gen_vvv, gen_helper_vfmul_d)
1314
-TRANS(vfdiv_s, ALL, gen_vvv, gen_helper_vfdiv_s)
1315
-TRANS(vfdiv_d, ALL, gen_vvv, gen_helper_vfdiv_d)
1316
-
1317
-TRANS(vfmadd_s, ALL, gen_vvvv, gen_helper_vfmadd_s)
1318
-TRANS(vfmadd_d, ALL, gen_vvvv, gen_helper_vfmadd_d)
1319
-TRANS(vfmsub_s, ALL, gen_vvvv, gen_helper_vfmsub_s)
1320
-TRANS(vfmsub_d, ALL, gen_vvvv, gen_helper_vfmsub_d)
1321
-TRANS(vfnmadd_s, ALL, gen_vvvv, gen_helper_vfnmadd_s)
1322
-TRANS(vfnmadd_d, ALL, gen_vvvv, gen_helper_vfnmadd_d)
1323
-TRANS(vfnmsub_s, ALL, gen_vvvv, gen_helper_vfnmsub_s)
1324
-TRANS(vfnmsub_d, ALL, gen_vvvv, gen_helper_vfnmsub_d)
1325
-
1326
-TRANS(vfmax_s, ALL, gen_vvv, gen_helper_vfmax_s)
1327
-TRANS(vfmax_d, ALL, gen_vvv, gen_helper_vfmax_d)
1328
-TRANS(vfmin_s, ALL, gen_vvv, gen_helper_vfmin_s)
1329
-TRANS(vfmin_d, ALL, gen_vvv, gen_helper_vfmin_d)
1330
-
1331
-TRANS(vfmaxa_s, ALL, gen_vvv, gen_helper_vfmaxa_s)
1332
-TRANS(vfmaxa_d, ALL, gen_vvv, gen_helper_vfmaxa_d)
1333
-TRANS(vfmina_s, ALL, gen_vvv, gen_helper_vfmina_s)
1334
-TRANS(vfmina_d, ALL, gen_vvv, gen_helper_vfmina_d)
1335
-
1336
-TRANS(vflogb_s, ALL, gen_vv, gen_helper_vflogb_s)
1337
-TRANS(vflogb_d, ALL, gen_vv, gen_helper_vflogb_d)
1338
-
1339
-TRANS(vfclass_s, ALL, gen_vv, gen_helper_vfclass_s)
1340
-TRANS(vfclass_d, ALL, gen_vv, gen_helper_vfclass_d)
1341
-
1342
-TRANS(vfsqrt_s, ALL, gen_vv, gen_helper_vfsqrt_s)
1343
-TRANS(vfsqrt_d, ALL, gen_vv, gen_helper_vfsqrt_d)
1344
-TRANS(vfrecip_s, ALL, gen_vv, gen_helper_vfrecip_s)
1345
-TRANS(vfrecip_d, ALL, gen_vv, gen_helper_vfrecip_d)
1346
-TRANS(vfrsqrt_s, ALL, gen_vv, gen_helper_vfrsqrt_s)
1347
-TRANS(vfrsqrt_d, ALL, gen_vv, gen_helper_vfrsqrt_d)
1348
-
1349
-TRANS(vfcvtl_s_h, ALL, gen_vv, gen_helper_vfcvtl_s_h)
1350
-TRANS(vfcvth_s_h, ALL, gen_vv, gen_helper_vfcvth_s_h)
1351
-TRANS(vfcvtl_d_s, ALL, gen_vv, gen_helper_vfcvtl_d_s)
1352
-TRANS(vfcvth_d_s, ALL, gen_vv, gen_helper_vfcvth_d_s)
1353
-TRANS(vfcvt_h_s, ALL, gen_vvv, gen_helper_vfcvt_h_s)
1354
-TRANS(vfcvt_s_d, ALL, gen_vvv, gen_helper_vfcvt_s_d)
1355
-
1356
-TRANS(vfrintrne_s, ALL, gen_vv, gen_helper_vfrintrne_s)
1357
-TRANS(vfrintrne_d, ALL, gen_vv, gen_helper_vfrintrne_d)
1358
-TRANS(vfrintrz_s, ALL, gen_vv, gen_helper_vfrintrz_s)
1359
-TRANS(vfrintrz_d, ALL, gen_vv, gen_helper_vfrintrz_d)
1360
-TRANS(vfrintrp_s, ALL, gen_vv, gen_helper_vfrintrp_s)
1361
-TRANS(vfrintrp_d, ALL, gen_vv, gen_helper_vfrintrp_d)
1362
-TRANS(vfrintrm_s, ALL, gen_vv, gen_helper_vfrintrm_s)
1363
-TRANS(vfrintrm_d, ALL, gen_vv, gen_helper_vfrintrm_d)
1364
-TRANS(vfrint_s, ALL, gen_vv, gen_helper_vfrint_s)
1365
-TRANS(vfrint_d, ALL, gen_vv, gen_helper_vfrint_d)
1366
-
1367
-TRANS(vftintrne_w_s, ALL, gen_vv, gen_helper_vftintrne_w_s)
1368
-TRANS(vftintrne_l_d, ALL, gen_vv, gen_helper_vftintrne_l_d)
1369
-TRANS(vftintrz_w_s, ALL, gen_vv, gen_helper_vftintrz_w_s)
1370
-TRANS(vftintrz_l_d, ALL, gen_vv, gen_helper_vftintrz_l_d)
1371
-TRANS(vftintrp_w_s, ALL, gen_vv, gen_helper_vftintrp_w_s)
1372
-TRANS(vftintrp_l_d, ALL, gen_vv, gen_helper_vftintrp_l_d)
1373
-TRANS(vftintrm_w_s, ALL, gen_vv, gen_helper_vftintrm_w_s)
1374
-TRANS(vftintrm_l_d, ALL, gen_vv, gen_helper_vftintrm_l_d)
1375
-TRANS(vftint_w_s, ALL, gen_vv, gen_helper_vftint_w_s)
1376
-TRANS(vftint_l_d, ALL, gen_vv, gen_helper_vftint_l_d)
1377
-TRANS(vftintrz_wu_s, ALL, gen_vv, gen_helper_vftintrz_wu_s)
1378
-TRANS(vftintrz_lu_d, ALL, gen_vv, gen_helper_vftintrz_lu_d)
1379
-TRANS(vftint_wu_s, ALL, gen_vv, gen_helper_vftint_wu_s)
1380
-TRANS(vftint_lu_d, ALL, gen_vv, gen_helper_vftint_lu_d)
1381
-TRANS(vftintrne_w_d, ALL, gen_vvv, gen_helper_vftintrne_w_d)
1382
-TRANS(vftintrz_w_d, ALL, gen_vvv, gen_helper_vftintrz_w_d)
1383
-TRANS(vftintrp_w_d, ALL, gen_vvv, gen_helper_vftintrp_w_d)
1384
-TRANS(vftintrm_w_d, ALL, gen_vvv, gen_helper_vftintrm_w_d)
1385
-TRANS(vftint_w_d, ALL, gen_vvv, gen_helper_vftint_w_d)
1386
-TRANS(vftintrnel_l_s, ALL, gen_vv, gen_helper_vftintrnel_l_s)
1387
-TRANS(vftintrneh_l_s, ALL, gen_vv, gen_helper_vftintrneh_l_s)
1388
-TRANS(vftintrzl_l_s, ALL, gen_vv, gen_helper_vftintrzl_l_s)
1389
-TRANS(vftintrzh_l_s, ALL, gen_vv, gen_helper_vftintrzh_l_s)
1390
-TRANS(vftintrpl_l_s, ALL, gen_vv, gen_helper_vftintrpl_l_s)
1391
-TRANS(vftintrph_l_s, ALL, gen_vv, gen_helper_vftintrph_l_s)
1392
-TRANS(vftintrml_l_s, ALL, gen_vv, gen_helper_vftintrml_l_s)
1393
-TRANS(vftintrmh_l_s, ALL, gen_vv, gen_helper_vftintrmh_l_s)
1394
-TRANS(vftintl_l_s, ALL, gen_vv, gen_helper_vftintl_l_s)
1395
-TRANS(vftinth_l_s, ALL, gen_vv, gen_helper_vftinth_l_s)
1396
-
1397
-TRANS(vffint_s_w, ALL, gen_vv, gen_helper_vffint_s_w)
1398
-TRANS(vffint_d_l, ALL, gen_vv, gen_helper_vffint_d_l)
1399
-TRANS(vffint_s_wu, ALL, gen_vv, gen_helper_vffint_s_wu)
1400
-TRANS(vffint_d_lu, ALL, gen_vv, gen_helper_vffint_d_lu)
1401
-TRANS(vffintl_d_w, ALL, gen_vv, gen_helper_vffintl_d_w)
1402
-TRANS(vffinth_d_w, ALL, gen_vv, gen_helper_vffinth_d_w)
1403
-TRANS(vffint_s_l, ALL, gen_vvv, gen_helper_vffint_s_l)
1404
+TRANS(vbitrevi_b, LSX, gvec_vv_i, MO_8, do_vbitrevi)
1405
+TRANS(vbitrevi_h, LSX, gvec_vv_i, MO_16, do_vbitrevi)
1406
+TRANS(vbitrevi_w, LSX, gvec_vv_i, MO_32, do_vbitrevi)
1407
+TRANS(vbitrevi_d, LSX, gvec_vv_i, MO_64, do_vbitrevi)
1408
+
1409
+TRANS(vfrstp_b, LSX, gen_vvv, gen_helper_vfrstp_b)
1410
+TRANS(vfrstp_h, LSX, gen_vvv, gen_helper_vfrstp_h)
1411
+TRANS(vfrstpi_b, LSX, gen_vv_i, gen_helper_vfrstpi_b)
1412
+TRANS(vfrstpi_h, LSX, gen_vv_i, gen_helper_vfrstpi_h)
1413
+
1414
+TRANS(vfadd_s, LSX, gen_vvv, gen_helper_vfadd_s)
1415
+TRANS(vfadd_d, LSX, gen_vvv, gen_helper_vfadd_d)
1416
+TRANS(vfsub_s, LSX, gen_vvv, gen_helper_vfsub_s)
1417
+TRANS(vfsub_d, LSX, gen_vvv, gen_helper_vfsub_d)
1418
+TRANS(vfmul_s, LSX, gen_vvv, gen_helper_vfmul_s)
1419
+TRANS(vfmul_d, LSX, gen_vvv, gen_helper_vfmul_d)
1420
+TRANS(vfdiv_s, LSX, gen_vvv, gen_helper_vfdiv_s)
1421
+TRANS(vfdiv_d, LSX, gen_vvv, gen_helper_vfdiv_d)
1422
+
1423
+TRANS(vfmadd_s, LSX, gen_vvvv, gen_helper_vfmadd_s)
1424
+TRANS(vfmadd_d, LSX, gen_vvvv, gen_helper_vfmadd_d)
1425
+TRANS(vfmsub_s, LSX, gen_vvvv, gen_helper_vfmsub_s)
1426
+TRANS(vfmsub_d, LSX, gen_vvvv, gen_helper_vfmsub_d)
1427
+TRANS(vfnmadd_s, LSX, gen_vvvv, gen_helper_vfnmadd_s)
1428
+TRANS(vfnmadd_d, LSX, gen_vvvv, gen_helper_vfnmadd_d)
1429
+TRANS(vfnmsub_s, LSX, gen_vvvv, gen_helper_vfnmsub_s)
1430
+TRANS(vfnmsub_d, LSX, gen_vvvv, gen_helper_vfnmsub_d)
1431
+
1432
+TRANS(vfmax_s, LSX, gen_vvv, gen_helper_vfmax_s)
1433
+TRANS(vfmax_d, LSX, gen_vvv, gen_helper_vfmax_d)
1434
+TRANS(vfmin_s, LSX, gen_vvv, gen_helper_vfmin_s)
1435
+TRANS(vfmin_d, LSX, gen_vvv, gen_helper_vfmin_d)
1436
+
1437
+TRANS(vfmaxa_s, LSX, gen_vvv, gen_helper_vfmaxa_s)
1438
+TRANS(vfmaxa_d, LSX, gen_vvv, gen_helper_vfmaxa_d)
1439
+TRANS(vfmina_s, LSX, gen_vvv, gen_helper_vfmina_s)
1440
+TRANS(vfmina_d, LSX, gen_vvv, gen_helper_vfmina_d)
1441
+
1442
+TRANS(vflogb_s, LSX, gen_vv, gen_helper_vflogb_s)
1443
+TRANS(vflogb_d, LSX, gen_vv, gen_helper_vflogb_d)
1444
+
1445
+TRANS(vfclass_s, LSX, gen_vv, gen_helper_vfclass_s)
1446
+TRANS(vfclass_d, LSX, gen_vv, gen_helper_vfclass_d)
1447
+
1448
+TRANS(vfsqrt_s, LSX, gen_vv, gen_helper_vfsqrt_s)
1449
+TRANS(vfsqrt_d, LSX, gen_vv, gen_helper_vfsqrt_d)
1450
+TRANS(vfrecip_s, LSX, gen_vv, gen_helper_vfrecip_s)
1451
+TRANS(vfrecip_d, LSX, gen_vv, gen_helper_vfrecip_d)
1452
+TRANS(vfrsqrt_s, LSX, gen_vv, gen_helper_vfrsqrt_s)
1453
+TRANS(vfrsqrt_d, LSX, gen_vv, gen_helper_vfrsqrt_d)
1454
+
1455
+TRANS(vfcvtl_s_h, LSX, gen_vv, gen_helper_vfcvtl_s_h)
1456
+TRANS(vfcvth_s_h, LSX, gen_vv, gen_helper_vfcvth_s_h)
1457
+TRANS(vfcvtl_d_s, LSX, gen_vv, gen_helper_vfcvtl_d_s)
1458
+TRANS(vfcvth_d_s, LSX, gen_vv, gen_helper_vfcvth_d_s)
1459
+TRANS(vfcvt_h_s, LSX, gen_vvv, gen_helper_vfcvt_h_s)
1460
+TRANS(vfcvt_s_d, LSX, gen_vvv, gen_helper_vfcvt_s_d)
1461
+
1462
+TRANS(vfrintrne_s, LSX, gen_vv, gen_helper_vfrintrne_s)
1463
+TRANS(vfrintrne_d, LSX, gen_vv, gen_helper_vfrintrne_d)
1464
+TRANS(vfrintrz_s, LSX, gen_vv, gen_helper_vfrintrz_s)
1465
+TRANS(vfrintrz_d, LSX, gen_vv, gen_helper_vfrintrz_d)
1466
+TRANS(vfrintrp_s, LSX, gen_vv, gen_helper_vfrintrp_s)
1467
+TRANS(vfrintrp_d, LSX, gen_vv, gen_helper_vfrintrp_d)
1468
+TRANS(vfrintrm_s, LSX, gen_vv, gen_helper_vfrintrm_s)
1469
+TRANS(vfrintrm_d, LSX, gen_vv, gen_helper_vfrintrm_d)
1470
+TRANS(vfrint_s, LSX, gen_vv, gen_helper_vfrint_s)
1471
+TRANS(vfrint_d, LSX, gen_vv, gen_helper_vfrint_d)
1472
+
1473
+TRANS(vftintrne_w_s, LSX, gen_vv, gen_helper_vftintrne_w_s)
1474
+TRANS(vftintrne_l_d, LSX, gen_vv, gen_helper_vftintrne_l_d)
1475
+TRANS(vftintrz_w_s, LSX, gen_vv, gen_helper_vftintrz_w_s)
1476
+TRANS(vftintrz_l_d, LSX, gen_vv, gen_helper_vftintrz_l_d)
1477
+TRANS(vftintrp_w_s, LSX, gen_vv, gen_helper_vftintrp_w_s)
1478
+TRANS(vftintrp_l_d, LSX, gen_vv, gen_helper_vftintrp_l_d)
1479
+TRANS(vftintrm_w_s, LSX, gen_vv, gen_helper_vftintrm_w_s)
1480
+TRANS(vftintrm_l_d, LSX, gen_vv, gen_helper_vftintrm_l_d)
1481
+TRANS(vftint_w_s, LSX, gen_vv, gen_helper_vftint_w_s)
1482
+TRANS(vftint_l_d, LSX, gen_vv, gen_helper_vftint_l_d)
1483
+TRANS(vftintrz_wu_s, LSX, gen_vv, gen_helper_vftintrz_wu_s)
1484
+TRANS(vftintrz_lu_d, LSX, gen_vv, gen_helper_vftintrz_lu_d)
1485
+TRANS(vftint_wu_s, LSX, gen_vv, gen_helper_vftint_wu_s)
1486
+TRANS(vftint_lu_d, LSX, gen_vv, gen_helper_vftint_lu_d)
1487
+TRANS(vftintrne_w_d, LSX, gen_vvv, gen_helper_vftintrne_w_d)
1488
+TRANS(vftintrz_w_d, LSX, gen_vvv, gen_helper_vftintrz_w_d)
1489
+TRANS(vftintrp_w_d, LSX, gen_vvv, gen_helper_vftintrp_w_d)
1490
+TRANS(vftintrm_w_d, LSX, gen_vvv, gen_helper_vftintrm_w_d)
1491
+TRANS(vftint_w_d, LSX, gen_vvv, gen_helper_vftint_w_d)
1492
+TRANS(vftintrnel_l_s, LSX, gen_vv, gen_helper_vftintrnel_l_s)
1493
+TRANS(vftintrneh_l_s, LSX, gen_vv, gen_helper_vftintrneh_l_s)
1494
+TRANS(vftintrzl_l_s, LSX, gen_vv, gen_helper_vftintrzl_l_s)
1495
+TRANS(vftintrzh_l_s, LSX, gen_vv, gen_helper_vftintrzh_l_s)
1496
+TRANS(vftintrpl_l_s, LSX, gen_vv, gen_helper_vftintrpl_l_s)
1497
+TRANS(vftintrph_l_s, LSX, gen_vv, gen_helper_vftintrph_l_s)
1498
+TRANS(vftintrml_l_s, LSX, gen_vv, gen_helper_vftintrml_l_s)
1499
+TRANS(vftintrmh_l_s, LSX, gen_vv, gen_helper_vftintrmh_l_s)
1500
+TRANS(vftintl_l_s, LSX, gen_vv, gen_helper_vftintl_l_s)
1501
+TRANS(vftinth_l_s, LSX, gen_vv, gen_helper_vftinth_l_s)
1502
+
1503
+TRANS(vffint_s_w, LSX, gen_vv, gen_helper_vffint_s_w)
1504
+TRANS(vffint_d_l, LSX, gen_vv, gen_helper_vffint_d_l)
1505
+TRANS(vffint_s_wu, LSX, gen_vv, gen_helper_vffint_s_wu)
1506
+TRANS(vffint_d_lu, LSX, gen_vv, gen_helper_vffint_d_lu)
1507
+TRANS(vffintl_d_w, LSX, gen_vv, gen_helper_vffintl_d_w)
1508
+TRANS(vffinth_d_w, LSX, gen_vv, gen_helper_vffinth_d_w)
1509
+TRANS(vffint_s_l, LSX, gen_vvv, gen_helper_vffint_s_l)
1510
1511
static bool do_cmp(DisasContext *ctx, arg_vvv *a, MemOp mop, TCGCond cond)
1512
{
1513
@@ -XXX,XX +XXX,XX @@ static bool do_## NAME ##_u(DisasContext *ctx, arg_vv_i *a, MemOp mop) \
1514
DO_CMPI_U(vslei)
1515
DO_CMPI_U(vslti)
1516
1517
-TRANS(vseq_b, ALL, do_cmp, MO_8, TCG_COND_EQ)
1518
-TRANS(vseq_h, ALL, do_cmp, MO_16, TCG_COND_EQ)
1519
-TRANS(vseq_w, ALL, do_cmp, MO_32, TCG_COND_EQ)
1520
-TRANS(vseq_d, ALL, do_cmp, MO_64, TCG_COND_EQ)
1521
-TRANS(vseqi_b, ALL, do_vseqi_s, MO_8)
1522
-TRANS(vseqi_h, ALL, do_vseqi_s, MO_16)
1523
-TRANS(vseqi_w, ALL, do_vseqi_s, MO_32)
1524
-TRANS(vseqi_d, ALL, do_vseqi_s, MO_64)
1525
-
1526
-TRANS(vsle_b, ALL, do_cmp, MO_8, TCG_COND_LE)
1527
-TRANS(vsle_h, ALL, do_cmp, MO_16, TCG_COND_LE)
1528
-TRANS(vsle_w, ALL, do_cmp, MO_32, TCG_COND_LE)
1529
-TRANS(vsle_d, ALL, do_cmp, MO_64, TCG_COND_LE)
1530
-TRANS(vslei_b, ALL, do_vslei_s, MO_8)
1531
-TRANS(vslei_h, ALL, do_vslei_s, MO_16)
1532
-TRANS(vslei_w, ALL, do_vslei_s, MO_32)
1533
-TRANS(vslei_d, ALL, do_vslei_s, MO_64)
1534
-TRANS(vsle_bu, ALL, do_cmp, MO_8, TCG_COND_LEU)
1535
-TRANS(vsle_hu, ALL, do_cmp, MO_16, TCG_COND_LEU)
1536
-TRANS(vsle_wu, ALL, do_cmp, MO_32, TCG_COND_LEU)
1537
-TRANS(vsle_du, ALL, do_cmp, MO_64, TCG_COND_LEU)
1538
-TRANS(vslei_bu, ALL, do_vslei_u, MO_8)
1539
-TRANS(vslei_hu, ALL, do_vslei_u, MO_16)
1540
-TRANS(vslei_wu, ALL, do_vslei_u, MO_32)
1541
-TRANS(vslei_du, ALL, do_vslei_u, MO_64)
1542
-
1543
-TRANS(vslt_b, ALL, do_cmp, MO_8, TCG_COND_LT)
1544
-TRANS(vslt_h, ALL, do_cmp, MO_16, TCG_COND_LT)
1545
-TRANS(vslt_w, ALL, do_cmp, MO_32, TCG_COND_LT)
1546
-TRANS(vslt_d, ALL, do_cmp, MO_64, TCG_COND_LT)
1547
-TRANS(vslti_b, ALL, do_vslti_s, MO_8)
1548
-TRANS(vslti_h, ALL, do_vslti_s, MO_16)
1549
-TRANS(vslti_w, ALL, do_vslti_s, MO_32)
1550
-TRANS(vslti_d, ALL, do_vslti_s, MO_64)
1551
-TRANS(vslt_bu, ALL, do_cmp, MO_8, TCG_COND_LTU)
1552
-TRANS(vslt_hu, ALL, do_cmp, MO_16, TCG_COND_LTU)
1553
-TRANS(vslt_wu, ALL, do_cmp, MO_32, TCG_COND_LTU)
1554
-TRANS(vslt_du, ALL, do_cmp, MO_64, TCG_COND_LTU)
1555
-TRANS(vslti_bu, ALL, do_vslti_u, MO_8)
1556
-TRANS(vslti_hu, ALL, do_vslti_u, MO_16)
1557
-TRANS(vslti_wu, ALL, do_vslti_u, MO_32)
1558
-TRANS(vslti_du, ALL, do_vslti_u, MO_64)
1559
+TRANS(vseq_b, LSX, do_cmp, MO_8, TCG_COND_EQ)
1560
+TRANS(vseq_h, LSX, do_cmp, MO_16, TCG_COND_EQ)
1561
+TRANS(vseq_w, LSX, do_cmp, MO_32, TCG_COND_EQ)
1562
+TRANS(vseq_d, LSX, do_cmp, MO_64, TCG_COND_EQ)
1563
+TRANS(vseqi_b, LSX, do_vseqi_s, MO_8)
1564
+TRANS(vseqi_h, LSX, do_vseqi_s, MO_16)
1565
+TRANS(vseqi_w, LSX, do_vseqi_s, MO_32)
1566
+TRANS(vseqi_d, LSX, do_vseqi_s, MO_64)
1567
+
1568
+TRANS(vsle_b, LSX, do_cmp, MO_8, TCG_COND_LE)
1569
+TRANS(vsle_h, LSX, do_cmp, MO_16, TCG_COND_LE)
1570
+TRANS(vsle_w, LSX, do_cmp, MO_32, TCG_COND_LE)
1571
+TRANS(vsle_d, LSX, do_cmp, MO_64, TCG_COND_LE)
1572
+TRANS(vslei_b, LSX, do_vslei_s, MO_8)
1573
+TRANS(vslei_h, LSX, do_vslei_s, MO_16)
1574
+TRANS(vslei_w, LSX, do_vslei_s, MO_32)
1575
+TRANS(vslei_d, LSX, do_vslei_s, MO_64)
1576
+TRANS(vsle_bu, LSX, do_cmp, MO_8, TCG_COND_LEU)
1577
+TRANS(vsle_hu, LSX, do_cmp, MO_16, TCG_COND_LEU)
1578
+TRANS(vsle_wu, LSX, do_cmp, MO_32, TCG_COND_LEU)
1579
+TRANS(vsle_du, LSX, do_cmp, MO_64, TCG_COND_LEU)
1580
+TRANS(vslei_bu, LSX, do_vslei_u, MO_8)
1581
+TRANS(vslei_hu, LSX, do_vslei_u, MO_16)
1582
+TRANS(vslei_wu, LSX, do_vslei_u, MO_32)
1583
+TRANS(vslei_du, LSX, do_vslei_u, MO_64)
1584
+
1585
+TRANS(vslt_b, LSX, do_cmp, MO_8, TCG_COND_LT)
1586
+TRANS(vslt_h, LSX, do_cmp, MO_16, TCG_COND_LT)
1587
+TRANS(vslt_w, LSX, do_cmp, MO_32, TCG_COND_LT)
1588
+TRANS(vslt_d, LSX, do_cmp, MO_64, TCG_COND_LT)
1589
+TRANS(vslti_b, LSX, do_vslti_s, MO_8)
1590
+TRANS(vslti_h, LSX, do_vslti_s, MO_16)
1591
+TRANS(vslti_w, LSX, do_vslti_s, MO_32)
1592
+TRANS(vslti_d, LSX, do_vslti_s, MO_64)
1593
+TRANS(vslt_bu, LSX, do_cmp, MO_8, TCG_COND_LTU)
1594
+TRANS(vslt_hu, LSX, do_cmp, MO_16, TCG_COND_LTU)
1595
+TRANS(vslt_wu, LSX, do_cmp, MO_32, TCG_COND_LTU)
1596
+TRANS(vslt_du, LSX, do_cmp, MO_64, TCG_COND_LTU)
1597
+TRANS(vslti_bu, LSX, do_vslti_u, MO_8)
1598
+TRANS(vslti_hu, LSX, do_vslti_u, MO_16)
1599
+TRANS(vslti_wu, LSX, do_vslti_u, MO_32)
1600
+TRANS(vslti_du, LSX, do_vslti_u, MO_64)
1601
1602
static bool trans_vfcmp_cond_s(DisasContext *ctx, arg_vvv_fcond *a)
1603
{
1604
@@ -XXX,XX +XXX,XX @@ static bool trans_vfcmp_cond_s(DisasContext *ctx, arg_vvv_fcond *a)
1605
TCGv_i32 vj = tcg_constant_i32(a->vj);
1606
TCGv_i32 vk = tcg_constant_i32(a->vk);
1607
1608
+ if (!avail_LSX(ctx)) {
1609
+ return false;
1610
+ }
1611
+
1612
CHECK_SXE;
1613
1614
fn = (a->fcond & 1 ? gen_helper_vfcmp_s_s : gen_helper_vfcmp_c_s);
1615
@@ -XXX,XX +XXX,XX @@ static bool trans_vfcmp_cond_d(DisasContext *ctx, arg_vvv_fcond *a)
1616
TCGv_i32 vj = tcg_constant_i32(a->vj);
1617
TCGv_i32 vk = tcg_constant_i32(a->vk);
1618
1619
+ if (!avail_LSX(ctx)) {
1620
+ return false;
1621
+ }
1622
+
1623
+ CHECK_SXE;
1624
+
1625
fn = (a->fcond & 1 ? gen_helper_vfcmp_s_d : gen_helper_vfcmp_c_d);
1626
flags = get_fcmp_flags(a->fcond >> 1);
1627
fn(cpu_env, vd, vj, vk, tcg_constant_i32(flags));
1628
@@ -XXX,XX +XXX,XX @@ static bool trans_vfcmp_cond_d(DisasContext *ctx, arg_vvv_fcond *a)
1629
1630
static bool trans_vbitsel_v(DisasContext *ctx, arg_vvvv *a)
1631
{
1632
+ if (!avail_LSX(ctx)) {
1633
+ return false;
1634
+ }
1635
+
1636
CHECK_SXE;
1637
1638
tcg_gen_gvec_bitsel(MO_64, vec_full_offset(a->vd), vec_full_offset(a->va),
1639
@@ -XXX,XX +XXX,XX @@ static bool trans_vbitseli_b(DisasContext *ctx, arg_vv_i *a)
1640
.load_dest = true
1641
};
1642
1643
+ if (!avail_LSX(ctx)) {
1644
+ return false;
1645
+ }
1646
+
1647
CHECK_SXE;
1648
1649
tcg_gen_gvec_2i(vec_full_offset(a->vd), vec_full_offset(a->vj),
1650
@@ -XXX,XX +XXX,XX @@ static bool trans_## NAME (DisasContext *ctx, arg_cv *a) \
1651
get_vreg64(ah, a->vj, 1); \
1652
get_vreg64(al, a->vj, 0); \
1653
\
1654
+ if (!avail_LSX(ctx)) { \
1655
+ return false; \
1656
+ } \
1657
+ \
1658
CHECK_SXE; \
1659
tcg_gen_or_i64(t1, al, ah); \
1660
tcg_gen_setcondi_i64(COND, t1, t1, 0); \
1661
@@ -XXX,XX +XXX,XX @@ static bool trans_## NAME (DisasContext *ctx, arg_cv *a) \
1662
VSET(vseteqz_v, TCG_COND_EQ)
1663
VSET(vsetnez_v, TCG_COND_NE)
1664
1665
-TRANS(vsetanyeqz_b, ALL, gen_cv, gen_helper_vsetanyeqz_b)
1666
-TRANS(vsetanyeqz_h, ALL, gen_cv, gen_helper_vsetanyeqz_h)
1667
-TRANS(vsetanyeqz_w, ALL, gen_cv, gen_helper_vsetanyeqz_w)
1668
-TRANS(vsetanyeqz_d, ALL, gen_cv, gen_helper_vsetanyeqz_d)
1669
-TRANS(vsetallnez_b, ALL, gen_cv, gen_helper_vsetallnez_b)
1670
-TRANS(vsetallnez_h, ALL, gen_cv, gen_helper_vsetallnez_h)
1671
-TRANS(vsetallnez_w, ALL, gen_cv, gen_helper_vsetallnez_w)
1672
-TRANS(vsetallnez_d, ALL, gen_cv, gen_helper_vsetallnez_d)
1673
+TRANS(vsetanyeqz_b, LSX, gen_cv, gen_helper_vsetanyeqz_b)
1674
+TRANS(vsetanyeqz_h, LSX, gen_cv, gen_helper_vsetanyeqz_h)
1675
+TRANS(vsetanyeqz_w, LSX, gen_cv, gen_helper_vsetanyeqz_w)
1676
+TRANS(vsetanyeqz_d, LSX, gen_cv, gen_helper_vsetanyeqz_d)
1677
+TRANS(vsetallnez_b, LSX, gen_cv, gen_helper_vsetallnez_b)
1678
+TRANS(vsetallnez_h, LSX, gen_cv, gen_helper_vsetallnez_h)
1679
+TRANS(vsetallnez_w, LSX, gen_cv, gen_helper_vsetallnez_w)
1680
+TRANS(vsetallnez_d, LSX, gen_cv, gen_helper_vsetallnez_d)
1681
1682
static bool trans_vinsgr2vr_b(DisasContext *ctx, arg_vr_i *a)
1683
{
1684
TCGv src = gpr_src(ctx, a->rj, EXT_NONE);
1685
+
1686
+ if (!avail_LSX(ctx)) {
1687
+ return false;
1688
+ }
1689
+
1690
CHECK_SXE;
1691
tcg_gen_st8_i64(src, cpu_env,
1692
offsetof(CPULoongArchState, fpr[a->vd].vreg.B(a->imm)));
1693
@@ -XXX,XX +XXX,XX @@ static bool trans_vinsgr2vr_b(DisasContext *ctx, arg_vr_i *a)
1694
static bool trans_vinsgr2vr_h(DisasContext *ctx, arg_vr_i *a)
1695
{
1696
TCGv src = gpr_src(ctx, a->rj, EXT_NONE);
1697
+
1698
+ if (!avail_LSX(ctx)) {
1699
+ return false;
1700
+ }
1701
+
1702
CHECK_SXE;
1703
tcg_gen_st16_i64(src, cpu_env,
1704
offsetof(CPULoongArchState, fpr[a->vd].vreg.H(a->imm)));
1705
@@ -XXX,XX +XXX,XX @@ static bool trans_vinsgr2vr_h(DisasContext *ctx, arg_vr_i *a)
1706
static bool trans_vinsgr2vr_w(DisasContext *ctx, arg_vr_i *a)
1707
{
1708
TCGv src = gpr_src(ctx, a->rj, EXT_NONE);
1709
+
1710
+ if (!avail_LSX(ctx)) {
1711
+ return false;
1712
+ }
1713
+
1714
CHECK_SXE;
1715
tcg_gen_st32_i64(src, cpu_env,
1716
offsetof(CPULoongArchState, fpr[a->vd].vreg.W(a->imm)));
1717
@@ -XXX,XX +XXX,XX @@ static bool trans_vinsgr2vr_w(DisasContext *ctx, arg_vr_i *a)
1718
static bool trans_vinsgr2vr_d(DisasContext *ctx, arg_vr_i *a)
1719
{
1720
TCGv src = gpr_src(ctx, a->rj, EXT_NONE);
1721
+
1722
+ if (!avail_LSX(ctx)) {
1723
+ return false;
1724
+ }
1725
+
1726
CHECK_SXE;
1727
tcg_gen_st_i64(src, cpu_env,
1728
offsetof(CPULoongArchState, fpr[a->vd].vreg.D(a->imm)));
1729
@@ -XXX,XX +XXX,XX @@ static bool trans_vinsgr2vr_d(DisasContext *ctx, arg_vr_i *a)
1730
static bool trans_vpickve2gr_b(DisasContext *ctx, arg_rv_i *a)
1731
{
1732
TCGv dst = gpr_dst(ctx, a->rd, EXT_NONE);
1733
+
1734
+ if (!avail_LSX(ctx)) {
1735
+ return false;
1736
+ }
1737
+
1738
CHECK_SXE;
1739
tcg_gen_ld8s_i64(dst, cpu_env,
1740
offsetof(CPULoongArchState, fpr[a->vj].vreg.B(a->imm)));
1741
@@ -XXX,XX +XXX,XX @@ static bool trans_vpickve2gr_b(DisasContext *ctx, arg_rv_i *a)
1742
static bool trans_vpickve2gr_h(DisasContext *ctx, arg_rv_i *a)
1743
{
1744
TCGv dst = gpr_dst(ctx, a->rd, EXT_NONE);
1745
+
1746
+ if (!avail_LSX(ctx)) {
1747
+ return false;
1748
+ }
1749
+
1750
CHECK_SXE;
1751
tcg_gen_ld16s_i64(dst, cpu_env,
1752
offsetof(CPULoongArchState, fpr[a->vj].vreg.H(a->imm)));
1753
@@ -XXX,XX +XXX,XX @@ static bool trans_vpickve2gr_h(DisasContext *ctx, arg_rv_i *a)
1754
static bool trans_vpickve2gr_w(DisasContext *ctx, arg_rv_i *a)
1755
{
1756
TCGv dst = gpr_dst(ctx, a->rd, EXT_NONE);
1757
+
1758
+ if (!avail_LSX(ctx)) {
1759
+ return false;
1760
+ }
1761
+
1762
CHECK_SXE;
1763
tcg_gen_ld32s_i64(dst, cpu_env,
1764
offsetof(CPULoongArchState, fpr[a->vj].vreg.W(a->imm)));
1765
@@ -XXX,XX +XXX,XX @@ static bool trans_vpickve2gr_w(DisasContext *ctx, arg_rv_i *a)
1766
static bool trans_vpickve2gr_d(DisasContext *ctx, arg_rv_i *a)
1767
{
1768
TCGv dst = gpr_dst(ctx, a->rd, EXT_NONE);
1769
+
1770
+ if (!avail_LSX(ctx)) {
1771
+ return false;
1772
+ }
1773
+
1774
CHECK_SXE;
1775
tcg_gen_ld_i64(dst, cpu_env,
1776
offsetof(CPULoongArchState, fpr[a->vj].vreg.D(a->imm)));
1777
@@ -XXX,XX +XXX,XX @@ static bool trans_vpickve2gr_d(DisasContext *ctx, arg_rv_i *a)
1778
static bool trans_vpickve2gr_bu(DisasContext *ctx, arg_rv_i *a)
1779
{
1780
TCGv dst = gpr_dst(ctx, a->rd, EXT_NONE);
1781
+
1782
+ if (!avail_LSX(ctx)) {
1783
+ return false;
1784
+ }
1785
+
1786
CHECK_SXE;
1787
tcg_gen_ld8u_i64(dst, cpu_env,
1788
offsetof(CPULoongArchState, fpr[a->vj].vreg.B(a->imm)));
1789
@@ -XXX,XX +XXX,XX @@ static bool trans_vpickve2gr_bu(DisasContext *ctx, arg_rv_i *a)
1790
static bool trans_vpickve2gr_hu(DisasContext *ctx, arg_rv_i *a)
1791
{
1792
TCGv dst = gpr_dst(ctx, a->rd, EXT_NONE);
1793
+
1794
+ if (!avail_LSX(ctx)) {
1795
+ return false;
1796
+ }
1797
+
1798
CHECK_SXE;
1799
tcg_gen_ld16u_i64(dst, cpu_env,
1800
offsetof(CPULoongArchState, fpr[a->vj].vreg.H(a->imm)));
1801
@@ -XXX,XX +XXX,XX @@ static bool trans_vpickve2gr_hu(DisasContext *ctx, arg_rv_i *a)
1802
static bool trans_vpickve2gr_wu(DisasContext *ctx, arg_rv_i *a)
1803
{
1804
TCGv dst = gpr_dst(ctx, a->rd, EXT_NONE);
1805
+
1806
+ if (!avail_LSX(ctx)) {
1807
+ return false;
1808
+ }
1809
+
1810
CHECK_SXE;
1811
tcg_gen_ld32u_i64(dst, cpu_env,
1812
offsetof(CPULoongArchState, fpr[a->vj].vreg.W(a->imm)));
1813
@@ -XXX,XX +XXX,XX @@ static bool trans_vpickve2gr_wu(DisasContext *ctx, arg_rv_i *a)
1814
static bool trans_vpickve2gr_du(DisasContext *ctx, arg_rv_i *a)
1815
{
1816
TCGv dst = gpr_dst(ctx, a->rd, EXT_NONE);
1817
+
1818
+ if (!avail_LSX(ctx)) {
1819
+ return false;
1820
+ }
1821
+
1822
CHECK_SXE;
1823
tcg_gen_ld_i64(dst, cpu_env,
1824
offsetof(CPULoongArchState, fpr[a->vj].vreg.D(a->imm)));
1825
@@ -XXX,XX +XXX,XX @@ static bool trans_vpickve2gr_du(DisasContext *ctx, arg_rv_i *a)
1826
static bool gvec_dup(DisasContext *ctx, arg_vr *a, MemOp mop)
1827
{
1828
TCGv src = gpr_src(ctx, a->rj, EXT_NONE);
1829
+
1830
+ if (!avail_LSX(ctx)) {
1831
+ return false;
1832
+ }
1833
+
1834
CHECK_SXE;
1835
1836
tcg_gen_gvec_dup_i64(mop, vec_full_offset(a->vd),
1837
@@ -XXX,XX +XXX,XX @@ static bool gvec_dup(DisasContext *ctx, arg_vr *a, MemOp mop)
1838
return true;
1839
}
1840
1841
-TRANS(vreplgr2vr_b, ALL, gvec_dup, MO_8)
1842
-TRANS(vreplgr2vr_h, ALL, gvec_dup, MO_16)
1843
-TRANS(vreplgr2vr_w, ALL, gvec_dup, MO_32)
1844
-TRANS(vreplgr2vr_d, ALL, gvec_dup, MO_64)
1845
+TRANS(vreplgr2vr_b, LSX, gvec_dup, MO_8)
1846
+TRANS(vreplgr2vr_h, LSX, gvec_dup, MO_16)
1847
+TRANS(vreplgr2vr_w, LSX, gvec_dup, MO_32)
1848
+TRANS(vreplgr2vr_d, LSX, gvec_dup, MO_64)
1849
1850
static bool trans_vreplvei_b(DisasContext *ctx, arg_vv_i *a)
1851
{
1852
+ if (!avail_LSX(ctx)) {
1853
+ return false;
1854
+ }
1855
+
1856
CHECK_SXE;
1857
tcg_gen_gvec_dup_mem(MO_8,vec_full_offset(a->vd),
1858
offsetof(CPULoongArchState,
1859
@@ -XXX,XX +XXX,XX @@ static bool trans_vreplvei_b(DisasContext *ctx, arg_vv_i *a)
1860
1861
static bool trans_vreplvei_h(DisasContext *ctx, arg_vv_i *a)
1862
{
1863
+ if (!avail_LSX(ctx)) {
1864
+ return false;
1865
+ }
1866
+
1867
CHECK_SXE;
1868
tcg_gen_gvec_dup_mem(MO_16, vec_full_offset(a->vd),
1869
offsetof(CPULoongArchState,
1870
@@ -XXX,XX +XXX,XX @@ static bool trans_vreplvei_h(DisasContext *ctx, arg_vv_i *a)
1871
}
1872
static bool trans_vreplvei_w(DisasContext *ctx, arg_vv_i *a)
1873
{
1874
+ if (!avail_LSX(ctx)) {
1875
+ return false;
1876
+ }
1877
+
1878
CHECK_SXE;
1879
tcg_gen_gvec_dup_mem(MO_32, vec_full_offset(a->vd),
1880
offsetof(CPULoongArchState,
1881
@@ -XXX,XX +XXX,XX @@ static bool trans_vreplvei_w(DisasContext *ctx, arg_vv_i *a)
1882
}
1883
static bool trans_vreplvei_d(DisasContext *ctx, arg_vv_i *a)
1884
{
1885
+ if (!avail_LSX(ctx)) {
1886
+ return false;
1887
+ }
1888
+
1889
CHECK_SXE;
1890
tcg_gen_gvec_dup_mem(MO_64, vec_full_offset(a->vd),
1891
offsetof(CPULoongArchState,
1892
@@ -XXX,XX +XXX,XX @@ static bool gen_vreplve(DisasContext *ctx, arg_vvr *a, int vece, int bit,
1893
TCGv_ptr t1 = tcg_temp_new_ptr();
1894
TCGv_i64 t2 = tcg_temp_new_i64();
1895
1896
+ if (!avail_LSX(ctx)) {
1897
+ return false;
1898
+ }
1899
+
1900
CHECK_SXE;
1901
1902
tcg_gen_andi_i64(t0, gpr_src(ctx, a->rk, EXT_NONE), (LSX_LEN/bit) -1);
1903
@@ -XXX,XX +XXX,XX @@ static bool gen_vreplve(DisasContext *ctx, arg_vvr *a, int vece, int bit,
1904
return true;
1905
}
1906
1907
-TRANS(vreplve_b, ALL, gen_vreplve, MO_8, 8, tcg_gen_ld8u_i64)
1908
-TRANS(vreplve_h, ALL, gen_vreplve, MO_16, 16, tcg_gen_ld16u_i64)
1909
-TRANS(vreplve_w, ALL, gen_vreplve, MO_32, 32, tcg_gen_ld32u_i64)
1910
-TRANS(vreplve_d, ALL, gen_vreplve, MO_64, 64, tcg_gen_ld_i64)
1911
+TRANS(vreplve_b, LSX, gen_vreplve, MO_8, 8, tcg_gen_ld8u_i64)
1912
+TRANS(vreplve_h, LSX, gen_vreplve, MO_16, 16, tcg_gen_ld16u_i64)
1913
+TRANS(vreplve_w, LSX, gen_vreplve, MO_32, 32, tcg_gen_ld32u_i64)
1914
+TRANS(vreplve_d, LSX, gen_vreplve, MO_64, 64, tcg_gen_ld_i64)
1915
1916
static bool trans_vbsll_v(DisasContext *ctx, arg_vv_i *a)
1917
{
1918
int ofs;
1919
TCGv_i64 desthigh, destlow, high, low;
1920
1921
+ if (!avail_LSX(ctx)) {
1922
+ return false;
1923
+ }
1924
+
1925
CHECK_SXE;
1926
1927
desthigh = tcg_temp_new_i64();
1928
@@ -XXX,XX +XXX,XX @@ static bool trans_vbsrl_v(DisasContext *ctx, arg_vv_i *a)
1929
TCGv_i64 desthigh, destlow, high, low;
1930
int ofs;
1931
1932
+ if (!avail_LSX(ctx)) {
1933
+ return false;
1934
+ }
1935
+
1936
CHECK_SXE;
1937
1938
desthigh = tcg_temp_new_i64();
1939
@@ -XXX,XX +XXX,XX @@ static bool trans_vbsrl_v(DisasContext *ctx, arg_vv_i *a)
1940
return true;
1941
}
1942
1943
-TRANS(vpackev_b, ALL, gen_vvv, gen_helper_vpackev_b)
1944
-TRANS(vpackev_h, ALL, gen_vvv, gen_helper_vpackev_h)
1945
-TRANS(vpackev_w, ALL, gen_vvv, gen_helper_vpackev_w)
1946
-TRANS(vpackev_d, ALL, gen_vvv, gen_helper_vpackev_d)
1947
-TRANS(vpackod_b, ALL, gen_vvv, gen_helper_vpackod_b)
1948
-TRANS(vpackod_h, ALL, gen_vvv, gen_helper_vpackod_h)
1949
-TRANS(vpackod_w, ALL, gen_vvv, gen_helper_vpackod_w)
1950
-TRANS(vpackod_d, ALL, gen_vvv, gen_helper_vpackod_d)
1951
-
1952
-TRANS(vpickev_b, ALL, gen_vvv, gen_helper_vpickev_b)
1953
-TRANS(vpickev_h, ALL, gen_vvv, gen_helper_vpickev_h)
1954
-TRANS(vpickev_w, ALL, gen_vvv, gen_helper_vpickev_w)
1955
-TRANS(vpickev_d, ALL, gen_vvv, gen_helper_vpickev_d)
1956
-TRANS(vpickod_b, ALL, gen_vvv, gen_helper_vpickod_b)
1957
-TRANS(vpickod_h, ALL, gen_vvv, gen_helper_vpickod_h)
1958
-TRANS(vpickod_w, ALL, gen_vvv, gen_helper_vpickod_w)
1959
-TRANS(vpickod_d, ALL, gen_vvv, gen_helper_vpickod_d)
1960
-
1961
-TRANS(vilvl_b, ALL, gen_vvv, gen_helper_vilvl_b)
1962
-TRANS(vilvl_h, ALL, gen_vvv, gen_helper_vilvl_h)
1963
-TRANS(vilvl_w, ALL, gen_vvv, gen_helper_vilvl_w)
1964
-TRANS(vilvl_d, ALL, gen_vvv, gen_helper_vilvl_d)
1965
-TRANS(vilvh_b, ALL, gen_vvv, gen_helper_vilvh_b)
1966
-TRANS(vilvh_h, ALL, gen_vvv, gen_helper_vilvh_h)
1967
-TRANS(vilvh_w, ALL, gen_vvv, gen_helper_vilvh_w)
1968
-TRANS(vilvh_d, ALL, gen_vvv, gen_helper_vilvh_d)
1969
-
1970
-TRANS(vshuf_b, ALL, gen_vvvv, gen_helper_vshuf_b)
1971
-TRANS(vshuf_h, ALL, gen_vvv, gen_helper_vshuf_h)
1972
-TRANS(vshuf_w, ALL, gen_vvv, gen_helper_vshuf_w)
1973
-TRANS(vshuf_d, ALL, gen_vvv, gen_helper_vshuf_d)
1974
-TRANS(vshuf4i_b, ALL, gen_vv_i, gen_helper_vshuf4i_b)
1975
-TRANS(vshuf4i_h, ALL, gen_vv_i, gen_helper_vshuf4i_h)
1976
-TRANS(vshuf4i_w, ALL, gen_vv_i, gen_helper_vshuf4i_w)
1977
-TRANS(vshuf4i_d, ALL, gen_vv_i, gen_helper_vshuf4i_d)
1978
-
1979
-TRANS(vpermi_w, ALL, gen_vv_i, gen_helper_vpermi_w)
1980
-
1981
-TRANS(vextrins_b, ALL, gen_vv_i, gen_helper_vextrins_b)
1982
-TRANS(vextrins_h, ALL, gen_vv_i, gen_helper_vextrins_h)
1983
-TRANS(vextrins_w, ALL, gen_vv_i, gen_helper_vextrins_w)
1984
-TRANS(vextrins_d, ALL, gen_vv_i, gen_helper_vextrins_d)
1985
+TRANS(vpackev_b, LSX, gen_vvv, gen_helper_vpackev_b)
1986
+TRANS(vpackev_h, LSX, gen_vvv, gen_helper_vpackev_h)
1987
+TRANS(vpackev_w, LSX, gen_vvv, gen_helper_vpackev_w)
1988
+TRANS(vpackev_d, LSX, gen_vvv, gen_helper_vpackev_d)
1989
+TRANS(vpackod_b, LSX, gen_vvv, gen_helper_vpackod_b)
1990
+TRANS(vpackod_h, LSX, gen_vvv, gen_helper_vpackod_h)
1991
+TRANS(vpackod_w, LSX, gen_vvv, gen_helper_vpackod_w)
1992
+TRANS(vpackod_d, LSX, gen_vvv, gen_helper_vpackod_d)
1993
+
1994
+TRANS(vpickev_b, LSX, gen_vvv, gen_helper_vpickev_b)
1995
+TRANS(vpickev_h, LSX, gen_vvv, gen_helper_vpickev_h)
1996
+TRANS(vpickev_w, LSX, gen_vvv, gen_helper_vpickev_w)
1997
+TRANS(vpickev_d, LSX, gen_vvv, gen_helper_vpickev_d)
1998
+TRANS(vpickod_b, LSX, gen_vvv, gen_helper_vpickod_b)
1999
+TRANS(vpickod_h, LSX, gen_vvv, gen_helper_vpickod_h)
2000
+TRANS(vpickod_w, LSX, gen_vvv, gen_helper_vpickod_w)
2001
+TRANS(vpickod_d, LSX, gen_vvv, gen_helper_vpickod_d)
2002
+
2003
+TRANS(vilvl_b, LSX, gen_vvv, gen_helper_vilvl_b)
2004
+TRANS(vilvl_h, LSX, gen_vvv, gen_helper_vilvl_h)
2005
+TRANS(vilvl_w, LSX, gen_vvv, gen_helper_vilvl_w)
2006
+TRANS(vilvl_d, LSX, gen_vvv, gen_helper_vilvl_d)
2007
+TRANS(vilvh_b, LSX, gen_vvv, gen_helper_vilvh_b)
2008
+TRANS(vilvh_h, LSX, gen_vvv, gen_helper_vilvh_h)
2009
+TRANS(vilvh_w, LSX, gen_vvv, gen_helper_vilvh_w)
2010
+TRANS(vilvh_d, LSX, gen_vvv, gen_helper_vilvh_d)
2011
+
2012
+TRANS(vshuf_b, LSX, gen_vvvv, gen_helper_vshuf_b)
2013
+TRANS(vshuf_h, LSX, gen_vvv, gen_helper_vshuf_h)
2014
+TRANS(vshuf_w, LSX, gen_vvv, gen_helper_vshuf_w)
2015
+TRANS(vshuf_d, LSX, gen_vvv, gen_helper_vshuf_d)
2016
+TRANS(vshuf4i_b, LSX, gen_vv_i, gen_helper_vshuf4i_b)
2017
+TRANS(vshuf4i_h, LSX, gen_vv_i, gen_helper_vshuf4i_h)
2018
+TRANS(vshuf4i_w, LSX, gen_vv_i, gen_helper_vshuf4i_w)
2019
+TRANS(vshuf4i_d, LSX, gen_vv_i, gen_helper_vshuf4i_d)
2020
+
2021
+TRANS(vpermi_w, LSX, gen_vv_i, gen_helper_vpermi_w)
2022
+
2023
+TRANS(vextrins_b, LSX, gen_vv_i, gen_helper_vextrins_b)
2024
+TRANS(vextrins_h, LSX, gen_vv_i, gen_helper_vextrins_h)
2025
+TRANS(vextrins_w, LSX, gen_vv_i, gen_helper_vextrins_w)
2026
+TRANS(vextrins_d, LSX, gen_vv_i, gen_helper_vextrins_d)
2027
2028
static bool trans_vld(DisasContext *ctx, arg_vr_i *a)
2029
{
2030
@@ -XXX,XX +XXX,XX @@ static bool trans_vld(DisasContext *ctx, arg_vr_i *a)
2031
TCGv_i64 rl, rh;
2032
TCGv_i128 val;
2033
2034
+ if (!avail_LSX(ctx)) {
2035
+ return false;
2036
+ }
2037
+
2038
CHECK_SXE;
2039
2040
addr = gpr_src(ctx, a->rj, EXT_NONE);
2041
@@ -XXX,XX +XXX,XX @@ static bool trans_vst(DisasContext *ctx, arg_vr_i *a)
2042
TCGv_i128 val;
2043
TCGv_i64 ah, al;
2044
2045
+ if (!avail_LSX(ctx)) {
2046
+ return false;
2047
+ }
2048
+
2049
CHECK_SXE;
2050
2051
addr = gpr_src(ctx, a->rj, EXT_NONE);
2052
@@ -XXX,XX +XXX,XX @@ static bool trans_vldx(DisasContext *ctx, arg_vrr *a)
2053
TCGv_i64 rl, rh;
2054
TCGv_i128 val;
2055
2056
+ if (!avail_LSX(ctx)) {
2057
+ return false;
2058
+ }
2059
+
2060
CHECK_SXE;
2061
2062
src1 = gpr_src(ctx, a->rj, EXT_NONE);
2063
@@ -XXX,XX +XXX,XX @@ static bool trans_vstx(DisasContext *ctx, arg_vrr *a)
2064
TCGv_i64 ah, al;
2065
TCGv_i128 val;
2066
2067
+ if (!avail_LSX(ctx)) {
2068
+ return false;
2069
+ }
2070
+
2071
CHECK_SXE;
2072
2073
src1 = gpr_src(ctx, a->rj, EXT_NONE);
2074
@@ -XXX,XX +XXX,XX @@ static bool trans_## NAME (DisasContext *ctx, arg_vr_i *a) \
2075
TCGv addr; \
2076
TCGv_i64 val; \
2077
\
2078
+ if (!avail_LSX(ctx)) { \
2079
+ return false; \
2080
+ } \
2081
+ \
2082
CHECK_SXE; \
2083
\
2084
addr = gpr_src(ctx, a->rj, EXT_NONE); \
2085
@@ -XXX,XX +XXX,XX @@ static bool trans_## NAME (DisasContext *ctx, arg_vr_ii *a) \
2086
TCGv addr; \
2087
TCGv_i64 val; \
2088
\
2089
+ if (!avail_LSX(ctx)) { \
2090
+ return false; \
2091
+ } \
2092
+ \
2093
CHECK_SXE; \
2094
\
2095
addr = gpr_src(ctx, a->rj, EXT_NONE); \
2096
diff --git a/target/loongarch/translate.h b/target/loongarch/translate.h
2097
index XXXXXXX..XXXXXXX 100644
2098
--- a/target/loongarch/translate.h
2099
+++ b/target/loongarch/translate.h
2100
@@ -XXX,XX +XXX,XX @@
2101
#define avail_FP_DP(C) (FIELD_EX32((C)->cpucfg2, CPUCFG2, FP_DP))
2102
#define avail_LSPW(C) (FIELD_EX32((C)->cpucfg2, CPUCFG2, LSPW))
2103
#define avail_LAM(C) (FIELD_EX32((C)->cpucfg2, CPUCFG2, LAM))
2104
+#define avail_LSX(C) (FIELD_EX32((C)->cpucfg2, CPUCFG2, LSX))
2105
+
2106
2107
/*
2108
* If an operation is being performed on less than TARGET_LONG_BITS,
2109
--
2110
2.39.1
diff view generated by jsdifflib
New patch
[PULL 27/31] target/loongarch: Add avail_IOCSR to check iocsr instructions
1
Signed-off-by: Song Gao <gaosong@loongson.cn>
2
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
3
Message-ID: <20230822032724.1353391-16-gaosong@loongson.cn>
4
Message-Id: <20230822072219.35719-1-philmd@linaro.org>
5
---
6
.../loongarch/insn_trans/trans_privileged.c.inc | 16 ++++++++--------
7
target/loongarch/translate.h | 2 +-
8
2 files changed, 9 insertions(+), 9 deletions(-)
1
9
10
diff --git a/target/loongarch/insn_trans/trans_privileged.c.inc b/target/loongarch/insn_trans/trans_privileged.c.inc
11
index XXXXXXX..XXXXXXX 100644
12
--- a/target/loongarch/insn_trans/trans_privileged.c.inc
13
+++ b/target/loongarch/insn_trans/trans_privileged.c.inc
14
@@ -XXX,XX +XXX,XX @@ static bool gen_iocsrwr(DisasContext *ctx, arg_rr *a,
15
return true;
16
}
17
18
-TRANS(iocsrrd_b, ALL, gen_iocsrrd, gen_helper_iocsrrd_b)
19
-TRANS(iocsrrd_h, ALL, gen_iocsrrd, gen_helper_iocsrrd_h)
20
-TRANS(iocsrrd_w, ALL, gen_iocsrrd, gen_helper_iocsrrd_w)
21
-TRANS(iocsrrd_d, ALL, gen_iocsrrd, gen_helper_iocsrrd_d)
22
-TRANS(iocsrwr_b, ALL, gen_iocsrwr, gen_helper_iocsrwr_b)
23
-TRANS(iocsrwr_h, ALL, gen_iocsrwr, gen_helper_iocsrwr_h)
24
-TRANS(iocsrwr_w, ALL, gen_iocsrwr, gen_helper_iocsrwr_w)
25
-TRANS(iocsrwr_d, ALL, gen_iocsrwr, gen_helper_iocsrwr_d)
26
+TRANS(iocsrrd_b, IOCSR, gen_iocsrrd, gen_helper_iocsrrd_b)
27
+TRANS(iocsrrd_h, IOCSR, gen_iocsrrd, gen_helper_iocsrrd_h)
28
+TRANS(iocsrrd_w, IOCSR, gen_iocsrrd, gen_helper_iocsrrd_w)
29
+TRANS(iocsrrd_d, IOCSR, gen_iocsrrd, gen_helper_iocsrrd_d)
30
+TRANS(iocsrwr_b, IOCSR, gen_iocsrwr, gen_helper_iocsrwr_b)
31
+TRANS(iocsrwr_h, IOCSR, gen_iocsrwr, gen_helper_iocsrwr_h)
32
+TRANS(iocsrwr_w, IOCSR, gen_iocsrwr, gen_helper_iocsrwr_w)
33
+TRANS(iocsrwr_d, IOCSR, gen_iocsrwr, gen_helper_iocsrwr_d)
34
35
static void check_mmu_idx(DisasContext *ctx)
36
{
37
diff --git a/target/loongarch/translate.h b/target/loongarch/translate.h
38
index XXXXXXX..XXXXXXX 100644
39
--- a/target/loongarch/translate.h
40
+++ b/target/loongarch/translate.h
41
@@ -XXX,XX +XXX,XX @@
42
#define avail_LSPW(C) (FIELD_EX32((C)->cpucfg2, CPUCFG2, LSPW))
43
#define avail_LAM(C) (FIELD_EX32((C)->cpucfg2, CPUCFG2, LAM))
44
#define avail_LSX(C) (FIELD_EX32((C)->cpucfg2, CPUCFG2, LSX))
45
-
46
+#define avail_IOCSR(C) (FIELD_EX32((C)->cpucfg1, CPUCFG1, IOCSR))
47
48
/*
49
* If an operation is being performed on less than TARGET_LONG_BITS,
50
--
51
2.39.1
diff view generated by jsdifflib
New patch
[PULL 28/31] target/loongarch: cpu: Implement get_arch_id callback
1
From: Bibo Mao <maobibo@loongson.cn>
1
2
3
Implement the callback for getting the architecture-dependent CPU
4
ID, the cpu ID is physical id described in ACPI MADT table, this
5
will be used for cpu hotplug.
6
7
Signed-off-by: Bibo Mao <maobibo@loongson.cn>
8
Reviewed-by: Song Gao <gaosong@loongson.cn>
9
Message-Id: <20230824005007.2000525-1-maobibo@loongson.cn>
10
Signed-off-by: Song Gao <gaosong@loongson.cn>
11
---
12
hw/loongarch/virt.c | 2 ++
13
target/loongarch/cpu.c | 8 ++++++++
14
target/loongarch/cpu.h | 1 +
15
3 files changed, 11 insertions(+)
16
17
diff --git a/hw/loongarch/virt.c b/hw/loongarch/virt.c
18
index XXXXXXX..XXXXXXX 100644
19
--- a/hw/loongarch/virt.c
20
+++ b/hw/loongarch/virt.c
21
@@ -XXX,XX +XXX,XX @@ static void loongarch_init(MachineState *machine)
22
cpu = cpu_create(machine->cpu_type);
23
cpu->cpu_index = i;
24
machine->possible_cpus->cpus[i].cpu = OBJECT(cpu);
25
+ lacpu = LOONGARCH_CPU(cpu);
26
+ lacpu->phy_id = machine->possible_cpus->cpus[i].arch_id;
27
}
28
fdt_add_cpu_nodes(lams);
29
30
diff --git a/target/loongarch/cpu.c b/target/loongarch/cpu.c
31
index XXXXXXX..XXXXXXX 100644
32
--- a/target/loongarch/cpu.c
33
+++ b/target/loongarch/cpu.c
34
@@ -XXX,XX +XXX,XX @@ static struct TCGCPUOps loongarch_tcg_ops = {
35
static const struct SysemuCPUOps loongarch_sysemu_ops = {
36
.get_phys_page_debug = loongarch_cpu_get_phys_page_debug,
37
};
38
+
39
+static int64_t loongarch_cpu_get_arch_id(CPUState *cs)
40
+{
41
+ LoongArchCPU *cpu = LOONGARCH_CPU(cs);
42
+
43
+ return cpu->phy_id;
44
+}
45
#endif
46
47
static void loongarch_cpu_class_init(ObjectClass *c, void *data)
48
@@ -XXX,XX +XXX,XX @@ static void loongarch_cpu_class_init(ObjectClass *c, void *data)
49
cc->set_pc = loongarch_cpu_set_pc;
50
cc->get_pc = loongarch_cpu_get_pc;
51
#ifndef CONFIG_USER_ONLY
52
+ cc->get_arch_id = loongarch_cpu_get_arch_id;
53
dc->vmsd = &vmstate_loongarch_cpu;
54
cc->sysemu_ops = &loongarch_sysemu_ops;
55
#endif
56
diff --git a/target/loongarch/cpu.h b/target/loongarch/cpu.h
57
index XXXXXXX..XXXXXXX 100644
58
--- a/target/loongarch/cpu.h
59
+++ b/target/loongarch/cpu.h
60
@@ -XXX,XX +XXX,XX @@ struct ArchCPU {
61
CPUNegativeOffsetState neg;
62
CPULoongArchState env;
63
QEMUTimer timer;
64
+ uint32_t phy_id;
65
66
/* 'compatible' string for this CPU for Linux device trees */
67
const char *dtb_compatible;
68
--
69
2.39.1
diff view generated by jsdifflib
New patch
[PULL 29/31] hw/intc/loongarch_pch: fix edge triggered irq handling
1
From: Bibo Mao <maobibo@loongson.cn>
1
2
3
For edge triggered irq, qemu_irq_pulse is used to inject irq. It will
4
set irq with high level and low level soon to simluate pulse irq.
5
6
For edge triggered irq, irq is injected and set as pending at rising
7
level, do not clear irq at lowering level. LoongArch pch interrupt will
8
clear irq for lowering level irq, there will be problem. ACPI ged deivce
9
is edge-triggered irq, it is used for cpu/memory hotplug.
10
11
This patch fixes memory hotplug issue on LoongArch virt machine.
12
13
Signed-off-by: Bibo Mao <maobibo@loongson.cn>
14
Reviewed-by: Song Gao <gaosong@loongson.cn>
15
Message-Id: <20230707091557.1474790-1-maobibo@loongson.cn>
16
Signed-off-by: Song Gao <gaosong@loongson.cn>
17
---
18
hw/intc/loongarch_pch_pic.c | 7 ++++++-
19
1 file changed, 6 insertions(+), 1 deletion(-)
20
21
diff --git a/hw/intc/loongarch_pch_pic.c b/hw/intc/loongarch_pch_pic.c
22
index XXXXXXX..XXXXXXX 100644
23
--- a/hw/intc/loongarch_pch_pic.c
24
+++ b/hw/intc/loongarch_pch_pic.c
25
@@ -XXX,XX +XXX,XX @@ static void pch_pic_update_irq(LoongArchPCHPIC *s, uint64_t mask, int level)
26
qemu_set_irq(s->parent_irq[s->htmsi_vector[irq]], 1);
27
}
28
} else {
29
- val = mask & s->intisr;
30
+ /*
31
+ * intirr means requested pending irq
32
+ * do not clear pending irq for edge-triggered on lowering edge
33
+ */
34
+ val = mask & s->intisr & ~s->intirr;
35
if (val) {
36
irq = ctz64(val);
37
s->intisr &= ~MAKE_64BIT_MASK(irq, 1);
38
@@ -XXX,XX +XXX,XX @@ static void pch_pic_irq_handler(void *opaque, int irq, int level)
39
/* Edge triggered */
40
if (level) {
41
if ((s->last_intirr & mask) == 0) {
42
+ /* marked pending on a rising edge */
43
s->intirr |= mask;
44
}
45
s->last_intirr |= mask;
46
--
47
2.39.1
diff view generated by jsdifflib
[PULL 1/1] hw/intc/loongarch_ipi: Bring back all 4 IPI mailboxes
[PULL 30/31] target/loongarch: Split fcc register to fcc0-7 in gdbstub
1
From: Jiaxun Yang <jiaxun.yang@flygoat.com>
1
From: Jiajie Chen <c@jia.je>
2
2
3
As per "Loongson 3A5000/3B5000 Processor Reference Manual",
3
Since GDB 13.1(GDB commit ea3352172), GDB LoongArch changed to use
4
Loongson 3A5000's IPI implementation have 4 mailboxes per
4
fcc0-7 instead of fcc register. This commit partially reverts commit
5
core.
5
2f149c759 (`target/loongarch: Update gdb_set_fpu() and gdb_get_fpu()`)
6
to match the behavior of GDB.
6
7
7
However, in 78464f023b54 ("hw/loongarch/virt: Modify ipi as
8
Note that it is a breaking change for GDB 13.0 or earlier, but it is
8
percpu device"), the number of IPI mailboxes was reduced to
9
also required for GDB 13.1 or later to work.
9
one, which mismatches actual hardware.
10
10
11
It won't affect LoongArch based system as LoongArch boot code
11
Signed-off-by: Jiajie Chen <c@jia.je>
12
only uses the first mailbox, however MIPS based Loongson boot
12
Acked-by: Song Gao <gaosong@loongson.cn>
13
code uses all 4 mailboxes.
13
Message-Id: <20230808054315.3391465-1-c@jia.je>
14
15
Fixes Coverity CID: 1512452, 1512453
16
Fixes: 78464f023b54 ("hw/loongarch/virt: Modify ipi as percpu device")
17
Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
18
Reviewed-by: Song Gao <gaosong@loongson.cn>
19
Message-Id: <20230521102307.87081-2-jiaxun.yang@flygoat.com>
20
Signed-off-by: Song Gao <gaosong@loongson.cn>
14
Signed-off-by: Song Gao <gaosong@loongson.cn>
21
---
15
---
22
hw/intc/loongarch_ipi.c | 6 +++---
16
gdb-xml/loongarch-fpu.xml | 9 ++++++++-
23
include/hw/intc/loongarch_ipi.h | 4 +++-
17
target/loongarch/gdbstub.c | 16 +++++++---------
24
2 files changed, 6 insertions(+), 4 deletions(-)
18
2 files changed, 15 insertions(+), 10 deletions(-)
25
19
26
diff --git a/hw/intc/loongarch_ipi.c b/hw/intc/loongarch_ipi.c
20
diff --git a/gdb-xml/loongarch-fpu.xml b/gdb-xml/loongarch-fpu.xml
27
index XXXXXXX..XXXXXXX 100644
21
index XXXXXXX..XXXXXXX 100644
28
--- a/hw/intc/loongarch_ipi.c
22
--- a/gdb-xml/loongarch-fpu.xml
29
+++ b/hw/intc/loongarch_ipi.c
23
+++ b/gdb-xml/loongarch-fpu.xml
30
@@ -XXX,XX +XXX,XX @@ static void loongarch_ipi_init(Object *obj)
24
@@ -XXX,XX +XXX,XX @@
31
25
<reg name="f29" bitsize="64" type="fputype" group="float"/>
32
static const VMStateDescription vmstate_ipi_core = {
26
<reg name="f30" bitsize="64" type="fputype" group="float"/>
33
.name = "ipi-single",
27
<reg name="f31" bitsize="64" type="fputype" group="float"/>
34
- .version_id = 1,
28
- <reg name="fcc" bitsize="64" type="uint64" group="float"/>
35
- .minimum_version_id = 1,
29
+ <reg name="fcc0" bitsize="8" type="uint8" group="float"/>
36
+ .version_id = 2,
30
+ <reg name="fcc1" bitsize="8" type="uint8" group="float"/>
37
+ .minimum_version_id = 2,
31
+ <reg name="fcc2" bitsize="8" type="uint8" group="float"/>
38
.fields = (VMStateField[]) {
32
+ <reg name="fcc3" bitsize="8" type="uint8" group="float"/>
39
VMSTATE_UINT32(status, IPICore),
33
+ <reg name="fcc4" bitsize="8" type="uint8" group="float"/>
40
VMSTATE_UINT32(en, IPICore),
34
+ <reg name="fcc5" bitsize="8" type="uint8" group="float"/>
41
VMSTATE_UINT32(set, IPICore),
35
+ <reg name="fcc6" bitsize="8" type="uint8" group="float"/>
42
VMSTATE_UINT32(clear, IPICore),
36
+ <reg name="fcc7" bitsize="8" type="uint8" group="float"/>
43
- VMSTATE_UINT32_ARRAY(buf, IPICore, 2),
37
<reg name="fcsr" bitsize="32" type="uint32" group="float"/>
44
+ VMSTATE_UINT32_ARRAY(buf, IPICore, IPI_MBX_NUM * 2),
38
</feature>
45
VMSTATE_END_OF_LIST()
39
diff --git a/target/loongarch/gdbstub.c b/target/loongarch/gdbstub.c
40
index XXXXXXX..XXXXXXX 100644
41
--- a/target/loongarch/gdbstub.c
42
+++ b/target/loongarch/gdbstub.c
43
@@ -XXX,XX +XXX,XX @@ static int loongarch_gdb_get_fpu(CPULoongArchState *env,
44
{
45
if (0 <= n && n < 32) {
46
return gdb_get_reg64(mem_buf, env->fpr[n].vreg.D(0));
47
- } else if (n == 32) {
48
- uint64_t val = read_fcc(env);
49
- return gdb_get_reg64(mem_buf, val);
50
- } else if (n == 33) {
51
+ } else if (32 <= n && n < 40) {
52
+ return gdb_get_reg8(mem_buf, env->cf[n - 32]);
53
+ } else if (n == 40) {
54
return gdb_get_reg32(mem_buf, env->fcsr0);
46
}
55
}
47
};
56
return 0;
48
diff --git a/include/hw/intc/loongarch_ipi.h b/include/hw/intc/loongarch_ipi.h
57
@@ -XXX,XX +XXX,XX @@ static int loongarch_gdb_set_fpu(CPULoongArchState *env,
49
index XXXXXXX..XXXXXXX 100644
58
if (0 <= n && n < 32) {
50
--- a/include/hw/intc/loongarch_ipi.h
59
env->fpr[n].vreg.D(0) = ldq_p(mem_buf);
51
+++ b/include/hw/intc/loongarch_ipi.h
60
length = 8;
52
@@ -XXX,XX +XXX,XX @@
61
- } else if (n == 32) {
53
#define MAIL_SEND_OFFSET 0
62
- uint64_t val = ldq_p(mem_buf);
54
#define ANY_SEND_OFFSET (IOCSR_ANY_SEND - IOCSR_MAIL_SEND)
63
- write_fcc(env, val);
55
64
- length = 8;
56
+#define IPI_MBX_NUM 4
65
- } else if (n == 33) {
57
+
66
+ } else if (32 <= n && n < 40) {
58
#define TYPE_LOONGARCH_IPI "loongarch_ipi"
67
+ env->cf[n - 32] = ldub_p(mem_buf);
59
OBJECT_DECLARE_SIMPLE_TYPE(LoongArchIPI, LOONGARCH_IPI)
68
+ length = 1;
60
69
+ } else if (n == 40) {
61
@@ -XXX,XX +XXX,XX @@ typedef struct IPICore {
70
env->fcsr0 = ldl_p(mem_buf);
62
uint32_t set;
71
length = 4;
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uint32_t clear;
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}
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/* 64bit buf divide into 2 32bit buf */
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- uint32_t buf[2];
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+ uint32_t buf[IPI_MBX_NUM * 2];
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qemu_irq irq;
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} IPICore;
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--
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--
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2.39.1
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2.39.1
diff view generated by jsdifflib
New patch
[PULL 31/31] hw/loongarch: Fix ACPI processor id off-by-one error
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From: Jiajie Chen <c@jia.je>
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In hw/acpi/aml-build.c:build_pptt() function, the code assumes that the
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ACPI processor id equals to the cpu index, for example if we have 8
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cpus, then the ACPI processor id should be in range 0-7.
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However, in hw/loongarch/acpi-build.c:build_madt() function we broke the
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assumption. If we have 8 cpus again, the ACPI processor id in MADT table
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would be in range 1-8. It violates the following description taken from
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ACPI spec 6.4 table 5.138:
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If the processor structure represents an actual processor, this field
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must match the value of ACPI processor ID field in the processor’s entry
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in the MADT.
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It will break the latest Linux 6.5-rc6 with the
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following error message:
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ACPI PPTT: PPTT table found, but unable to locate core 7 (8)
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Invalid BIOS PPTT
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Here 7 is the last cpu index, 8 is the ACPI processor id learned from
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MADT.
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With this patch, Linux can properly detect SMT threads when "-smp
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8,sockets=1,cores=4,threads=2" is passed:
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Thread(s) per core: 2
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Core(s) per socket: 2
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Socket(s): 2
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The detection of number of sockets is still wrong, but that is out of
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scope of the commit.
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Signed-off-by: Jiajie Chen <c@jia.je>
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Reviewed-by: Bibo Mao <maobibo@loongson.cn>
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Message-Id: <20230820105658.99123-2-c@jia.je>
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Signed-off-by: Song Gao <gaosong@loongson.cn>
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---
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hw/loongarch/acpi-build.c | 2 +-
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1 file changed, 1 insertion(+), 1 deletion(-)
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diff --git a/hw/loongarch/acpi-build.c b/hw/loongarch/acpi-build.c
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index XXXXXXX..XXXXXXX 100644
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--- a/hw/loongarch/acpi-build.c
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+++ b/hw/loongarch/acpi-build.c
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@@ -XXX,XX +XXX,XX @@ build_madt(GArray *table_data, BIOSLinker *linker, LoongArchMachineState *lams)
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build_append_int_noprefix(table_data, 17, 1); /* Type */
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build_append_int_noprefix(table_data, 15, 1); /* Length */
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build_append_int_noprefix(table_data, 1, 1); /* Version */
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- build_append_int_noprefix(table_data, i + 1, 4); /* ACPI Processor ID */
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+ build_append_int_noprefix(table_data, i, 4); /* ACPI Processor ID */
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build_append_int_noprefix(table_data, arch_id, 4); /* Core ID */
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build_append_int_noprefix(table_data, 1, 4); /* Flags */
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}
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--
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2.39.1
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diff view generated by jsdifflib

Patchew 2.1-devel-b67e4c2

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