The following changes since commit b0dd9a7d6dd15a6898e9c585b521e6bec79b25aa:

  Open 8.2 development tree (2023-08-22 07:14:07 -0700)

are available in the Git repository at:

  https://gitlab.com/gaosong/qemu.git tags/pull-loongarch-20230824

for you to fetch changes up to 3f6bec4a9f7c159d32d49f6df5c2c3d587b953b9:

  hw/loongarch: Fix ACPI processor id off-by-one error (2023-08-24 16:58:16 +0800)

----------------------------------------------------------------
pull-loongarch-20230824

* Add la32 & va32 support for loongarch64-softmmu;
* Cleanups in preparation of loongarch32 support;
* Add some checks before translating instructions;
* Split fcc register to fcc0-7 in gdbstub;
* Fix ACPI processor id off-by-one error;
* Implement get_arch_id callback;
* Fix edge triggered irq handling.

----------------------------------------------------------------
Bibo Mao (2):
      target/loongarch: cpu: Implement get_arch_id callback
      hw/intc/loongarch_pch: fix edge triggered irq handling

Jiajie Chen (16):
      target/loongarch: Add function to check current arch
      target/loongarch: Add new object class for loongarch32 cpus
      target/loongarch: Add GDB support for loongarch32 mode
      target/loongarch: Support LoongArch32 TLB entry
      target/loongarch: Support LoongArch32 DMW
      target/loongarch: Support LoongArch32 VPPN
      target/loongarch: Add LA64 & VA32 to DisasContext
      target/loongarch: Extract make_address_x() helper
      target/loongarch: Extract make_address_i() helper
      target/loongarch: Extract make_address_pc() helper
      target/loongarch: Extract set_pc() helper
      target/loongarch: Truncate high 32 bits of address in VA32 mode
      target/loongarch: Sign extend results in VA32 mode
      target/loongarch: Add LoongArch32 cpu la132
      target/loongarch: Split fcc register to fcc0-7 in gdbstub
      hw/loongarch: Fix ACPI processor id off-by-one error

Philippe Mathieu-Daudé (4):
      target/loongarch: Log I/O write accesses to CSR registers
      target/loongarch: Remove duplicated disas_set_info assignment
      target/loongarch: Introduce abstract TYPE_LOONGARCH64_CPU
      target/loongarch: Extract 64-bit specifics to loongarch64_cpu_class_init

Song Gao (9):
      target/loongarch: Fix loongarch_la464_initfn() misses setting LSPW
      target/loongarch: Add a check parameter to the TRANS macro
      target/loongarch: Add avail_64 to check la64-only instructions
      hw/loongarch: Remove restriction of la464 cores in the virt machine
      target/loongarch: Add avail_FP/FP_SP/FP_DP to check fpu instructions
      target/loongarch: Add avail_LSPW to check LSPW instructions
      target/loongarch: Add avail_LAM to check atomic instructions
      target/loongarch: Add avail_LSX to check LSX instructions
      target/loongarch: Add avail_IOCSR to check iocsr instructions

 configs/targets/loongarch64-softmmu.mak            |    2 +-
 gdb-xml/loongarch-base32.xml                       |   45 +
 gdb-xml/loongarch-fpu.xml                          |    9 +-
 hw/intc/loongarch_pch_pic.c                        |    7 +-
 hw/loongarch/acpi-build.c                          |    2 +-
 hw/loongarch/virt.c                                |    7 +-
 target/loongarch/cpu-csr.h                         |   22 +-
 target/loongarch/cpu.c                             |  110 +-
 target/loongarch/cpu.h                             |   35 +
 target/loongarch/gdbstub.c                         |   50 +-
 target/loongarch/insn_trans/trans_arith.c.inc      |   98 +-
 target/loongarch/insn_trans/trans_atomic.c.inc     |   85 +-
 target/loongarch/insn_trans/trans_bit.c.inc        |   56 +-
 target/loongarch/insn_trans/trans_branch.c.inc     |   27 +-
 target/loongarch/insn_trans/trans_extra.c.inc      |   24 +-
 target/loongarch/insn_trans/trans_farith.c.inc     |   96 +-
 target/loongarch/insn_trans/trans_fcmp.c.inc       |    8 +
 target/loongarch/insn_trans/trans_fcnv.c.inc       |   56 +-
 target/loongarch/insn_trans/trans_fmemory.c.inc    |   62 +-
 target/loongarch/insn_trans/trans_fmov.c.inc       |   52 +-
 target/loongarch/insn_trans/trans_lsx.c.inc        | 1520 +++++++++++---------
 target/loongarch/insn_trans/trans_memory.c.inc     |  118 +-
 target/loongarch/insn_trans/trans_privileged.c.inc |   24 +-
 target/loongarch/insn_trans/trans_shift.c.inc      |   34 +-
 target/loongarch/op_helper.c                       |    4 +-
 target/loongarch/tlb_helper.c                      |   66 +-
 target/loongarch/translate.c                       |   46 +
 target/loongarch/translate.h                       |   19 +-
 28 files changed, 1591 insertions(+), 1093 deletions(-)
 create mode 100644 gdb-xml/loongarch-base32.xml

Applied, thanks.

Please update the changelog at https://wiki.qemu.org/ChangeLog/8.2 for any user-visible changes.