[PULL 0/2] target-arm queue
[PULL v2 00/32] target-arm queue
1
This bug seemed worth fixing for 8.0 since we need an rc4 anyway:
1
For some reason the xilinx can bus patches built in my local config
2
we were using uninitialized data for the guarded bit when
2
but not in the merge-test ones; dropped those.
3
combining stage 1 and stage 2 attrs.
4
3
5
thanks
6
-- PMM
4
-- PMM
7
5
8
The following changes since commit 08dede07030973c1053868bc64de7e10bfa02ad6:
6
The following changes since commit a68694cd1f3e5448cca814ff39b871f9ebd71ed5:
9
7
10
Merge tag 'pull-ppc-20230409' of https://github.com/legoater/qemu into staging (2023-04-10 11:47:52 +0100)
8
Merge remote-tracking branch 'remotes/philmd-gitlab/tags/edk2-next-20200914' into staging (2020-09-14 12:18:58 +0100)
11
9
12
are available in the Git repository at:
10
are available in the Git repository at:
13
11
14
https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20230410
12
https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20200914-1
15
13
16
for you to fetch changes up to 8539dc00552e8ea60420856fc1262c8299bc6308:
14
for you to fetch changes up to 4fe986dd4480308ecf07200cfbd3c3d494a0f639:
17
15
18
target/arm: Copy guarded bit in combine_cacheattrs (2023-04-10 14:31:40 +0100)
16
tests/acceptance: console boot tests for quanta-gsj (2020-09-14 14:24:59 +0100)
19
17
20
----------------------------------------------------------------
18
----------------------------------------------------------------
21
target-arm: Fix bug where we weren't initializing
19
* hw/misc/a9scu: Do not allow invalid CPU count
22
guarded bit state when combining S1/S2 attrs
20
* hw/misc/a9scu: Minor cleanups
21
* hw/timer/armv7m_systick: assert that board code set system_clock_scale
22
* decodetree: Improve identifier matching
23
* target/arm: Clean up neon fp insn size field decode
24
* target/arm: Remove KVM support for 32-bit Arm hosts
25
* hw/arm/mps2: New board models mps2-an386, mps2-an500
26
* Deprecate Unicore32 port
27
* Deprecate lm32 port
28
* target/arm: Count PMU events when MDCR.SPME is set
29
* hw/arm: versal-virt: Correct the tx/rx GEM clocks
30
* New Nuvoton iBMC board models npcm750-evb, quanta-gsj
23
31
24
----------------------------------------------------------------
32
----------------------------------------------------------------
25
Richard Henderson (2):
33
Aaron Lindsay (1):
26
target/arm: PTE bit GP only applies to stage1
34
target/arm: Count PMU events when MDCR.SPME is set
27
target/arm: Copy guarded bit in combine_cacheattrs
28
35
29
target/arm/ptw.c | 11 ++++++-----
36
Edgar E. Iglesias (1):
30
1 file changed, 6 insertions(+), 5 deletions(-)
37
hw/arm: versal-virt: Correct the tx/rx GEM clocks
38
39
Havard Skinnemoen (14):
40
hw/misc: Add NPCM7xx System Global Control Registers device model
41
hw/misc: Add NPCM7xx Clock Controller device model
42
hw/timer: Add NPCM7xx Timer device model
43
hw/arm: Add NPCM730 and NPCM750 SoC models
44
hw/arm: Add two NPCM7xx-based machines
45
roms: Add virtual Boot ROM for NPCM7xx SoCs
46
hw/arm: Load -bios image as a boot ROM for npcm7xx
47
hw/nvram: NPCM7xx OTP device model
48
hw/mem: Stubbed out NPCM7xx Memory Controller model
49
hw/ssi: NPCM7xx Flash Interface Unit device model
50
hw/arm: Wire up BMC boot flash for npcm750-evb and quanta-gsj
51
hw/arm/npcm7xx: add board setup stub for CPU and UART clocks
52
docs/system: Add Nuvoton machine documentation
53
tests/acceptance: console boot tests for quanta-gsj
54
55
Peter Maydell (11):
56
hw/timer/armv7m_systick: assert that board code set system_clock_scale
57
target/arm: Convert Neon 3-same-fp size field to MO_* in decode
58
target/arm: Convert Neon VCVT fp size field to MO_* in decode
59
target/arm: Convert VCMLA, VCADD size field to MO_* in decode
60
target/arm: Remove KVM support for 32-bit Arm hosts
61
target/arm: Remove no-longer-reachable 32-bit KVM code
62
hw/arm/mps2: New board model mps2-an386
63
hw/arm/mps2: New board model mps2-an500
64
docs/system/arm/mps2.rst: Make board list consistent
65
Deprecate Unicore32 port
66
Deprecate lm32 port
67
68
Philippe Mathieu-Daudé (4):
69
hw/misc/a9scu: Do not allow invalid CPU count
70
hw/misc/a9scu: Simplify setting MemoryRegionOps::valid fields
71
hw/misc/a9scu: Simplify setting MemoryRegionOps::impl fields
72
hw/misc/a9scu: Report unimplemented accesses with qemu_log_mask(UNIMP)
73
74
Richard Henderson (1):
75
decodetree: Improve identifier matching
76
77
docs/system/arm/mps2.rst | 20 +-
78
docs/system/arm/nuvoton.rst | 92 +++++
79
docs/system/deprecated.rst | 32 +-
80
docs/system/target-arm.rst | 1 +
81
configure | 2 +-
82
default-configs/arm-softmmu.mak | 1 +
83
include/hw/arm/npcm7xx.h | 112 +++++++
84
include/hw/mem/npcm7xx_mc.h | 36 ++
85
include/hw/misc/npcm7xx_clk.h | 48 +++
86
include/hw/misc/npcm7xx_gcr.h | 43 +++
87
include/hw/nvram/npcm7xx_otp.h | 79 +++++
88
include/hw/ssi/npcm7xx_fiu.h | 73 ++++
89
include/hw/timer/npcm7xx_timer.h | 78 +++++
90
target/arm/kvm-consts.h | 7 -
91
target/arm/kvm_arm.h | 6 -
92
target/arm/neon-dp.decode | 18 +-
93
target/arm/neon-shared.decode | 18 +-
94
tests/decode/succ_ident1.decode | 7 +
95
hw/arm/mps2.c | 97 +++++-
96
hw/arm/npcm7xx.c | 532 +++++++++++++++++++++++++++++
97
hw/arm/npcm7xx_boards.c | 197 +++++++++++
98
hw/arm/xlnx-versal-virt.c | 2 +-
99
hw/mem/npcm7xx_mc.c | 84 +++++
100
hw/misc/a9scu.c | 59 ++--
101
hw/misc/npcm7xx_clk.c | 266 +++++++++++++++
102
hw/misc/npcm7xx_gcr.c | 269 +++++++++++++++
103
hw/nvram/npcm7xx_otp.c | 440 ++++++++++++++++++++++++
104
hw/ssi/npcm7xx_fiu.c | 572 +++++++++++++++++++++++++++++++
105
hw/timer/armv7m_systick.c | 8 +
106
hw/timer/npcm7xx_timer.c | 543 ++++++++++++++++++++++++++++++
107
target/arm/cpu.c | 101 +++---
108
target/arm/helper.c | 2 +-
109
target/arm/kvm.c | 7 -
110
target/arm/kvm32.c | 595 ---------------------------------
111
.gitmodules | 3 +
112
MAINTAINERS | 10 +
113
hw/arm/Kconfig | 9 +
114
hw/arm/meson.build | 1 +
115
hw/mem/meson.build | 1 +
116
hw/misc/meson.build | 4 +
117
hw/misc/trace-events | 8 +
118
hw/nvram/meson.build | 1 +
119
hw/ssi/meson.build | 1 +
120
hw/ssi/trace-events | 11 +
121
hw/timer/meson.build | 1 +
122
hw/timer/trace-events | 5 +
123
pc-bios/README | 6 +
124
pc-bios/meson.build | 1 +
125
pc-bios/npcm7xx_bootrom.bin | Bin 0 -> 768 bytes
126
roms/Makefile | 7 +
127
roms/vbootrom | 1 +
128
scripts/decodetree.py | 46 ++-
129
target/arm/meson.build | 5 +-
130
target/arm/translate-neon.c.inc | 42 ++-
131
tests/acceptance/boot_linux_console.py | 83 +++++
132
55 files changed, 3910 insertions(+), 783 deletions(-)
133
create mode 100644 docs/system/arm/nuvoton.rst
134
create mode 100644 include/hw/arm/npcm7xx.h
135
create mode 100644 include/hw/mem/npcm7xx_mc.h
136
create mode 100644 include/hw/misc/npcm7xx_clk.h
137
create mode 100644 include/hw/misc/npcm7xx_gcr.h
138
create mode 100644 include/hw/nvram/npcm7xx_otp.h
139
create mode 100644 include/hw/ssi/npcm7xx_fiu.h
140
create mode 100644 include/hw/timer/npcm7xx_timer.h
141
create mode 100644 tests/decode/succ_ident1.decode
142
create mode 100644 hw/arm/npcm7xx.c
143
create mode 100644 hw/arm/npcm7xx_boards.c
144
create mode 100644 hw/mem/npcm7xx_mc.c
145
create mode 100644 hw/misc/npcm7xx_clk.c
146
create mode 100644 hw/misc/npcm7xx_gcr.c
147
create mode 100644 hw/nvram/npcm7xx_otp.c
148
create mode 100644 hw/ssi/npcm7xx_fiu.c
149
create mode 100644 hw/timer/npcm7xx_timer.c
150
delete mode 100644 target/arm/kvm32.c
151
create mode 100644 pc-bios/npcm7xx_bootrom.bin
152
create mode 160000 roms/vbootrom
153
diff view generated by jsdifflib
[PULL 1/2] target/arm: PTE bit GP only applies to stage1
Deleted patch
1
From: Richard Henderson <richard.henderson@linaro.org>
2
1
3
Only perform the extract of GP during the stage1 walk.
4
5
Reported-by: Peter Maydell <peter.maydell@linaro.org>
6
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
7
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
8
Message-id: 20230407185149.3253946-2-richard.henderson@linaro.org
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
---
11
target/arm/ptw.c | 10 +++++-----
12
1 file changed, 5 insertions(+), 5 deletions(-)
13
14
diff --git a/target/arm/ptw.c b/target/arm/ptw.c
15
index XXXXXXX..XXXXXXX 100644
16
--- a/target/arm/ptw.c
17
+++ b/target/arm/ptw.c
18
@@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_lpae(CPUARMState *env, S1Translate *ptw,
19
result->f.attrs.secure = false;
20
}
21
22
- /* When in aarch64 mode, and BTI is enabled, remember GP in the TLB. */
23
- if (aarch64 && cpu_isar_feature(aa64_bti, cpu)) {
24
- result->f.guarded = extract64(attrs, 50, 1); /* GP */
25
- }
26
-
27
if (regime_is_stage2(mmu_idx)) {
28
result->cacheattrs.is_s2_format = true;
29
result->cacheattrs.attrs = extract32(attrs, 2, 4);
30
@@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_lpae(CPUARMState *env, S1Translate *ptw,
31
assert(attrindx <= 7);
32
result->cacheattrs.is_s2_format = false;
33
result->cacheattrs.attrs = extract64(mair, attrindx * 8, 8);
34
+
35
+ /* When in aarch64 mode, and BTI is enabled, remember GP in the TLB. */
36
+ if (aarch64 && cpu_isar_feature(aa64_bti, cpu)) {
37
+ result->f.guarded = extract64(attrs, 50, 1); /* GP */
38
+ }
39
}
40
41
/*
42
--
43
2.34.1
diff view generated by jsdifflib
[PULL 2/2] target/arm: Copy guarded bit in combine_cacheattrs
Deleted patch
1
From: Richard Henderson <richard.henderson@linaro.org>
2
1
3
The guarded bit comes from the stage1 walk.
4
5
Fixes: Coverity CID 1507929
6
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
7
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
8
Message-id: 20230407185149.3253946-3-richard.henderson@linaro.org
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
---
11
target/arm/ptw.c | 1 +
12
1 file changed, 1 insertion(+)
13
14
diff --git a/target/arm/ptw.c b/target/arm/ptw.c
15
index XXXXXXX..XXXXXXX 100644
16
--- a/target/arm/ptw.c
17
+++ b/target/arm/ptw.c
18
@@ -XXX,XX +XXX,XX @@ static ARMCacheAttrs combine_cacheattrs(uint64_t hcr,
19
20
assert(!s1.is_s2_format);
21
ret.is_s2_format = false;
22
+ ret.guarded = s1.guarded;
23
24
if (s1.attrs == 0xf0) {
25
tagged = true;
26
--
27
2.34.1
diff view generated by jsdifflib

Patchew 2.1-devel-b67e4c2

© 2016 - 2025 Red Hat, Inc.