[PULL 0/2] target-arm queue
[PULL v2 00/46] target-arm queue
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This bug seemed worth fixing for 8.0 since we need an rc4 anyway:
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v1->v2 changes: dropped the last 6 patches from rth as there's
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we were using uninitialized data for the guarded bit when
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a problem with one of them that's too complicated to try to
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combining stage 1 and stage 2 attrs.
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fix up.
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thanks
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thanks
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-- PMM
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-- PMM
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The following changes since commit 08dede07030973c1053868bc64de7e10bfa02ad6:
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The following changes since commit a8c6af67e1e8d460e2c6e87070807e0a02c0fec2:
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Merge tag 'pull-ppc-20230409' of https://github.com/legoater/qemu into staging (2023-04-10 11:47:52 +0100)
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Merge remote-tracking branch 'remotes/dgibson/tags/ppc-for-5.0-20200221' into staging (2020-02-21 14:20:42 +0000)
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are available in the Git repository at:
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are available in the Git repository at:
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https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20230410
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https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20200221-1
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for you to fetch changes up to 8539dc00552e8ea60420856fc1262c8299bc6308:
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for you to fetch changes up to 9eb4f58918a851fb46895fd9b7ce579afeac9d02:
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target/arm: Copy guarded bit in combine_cacheattrs (2023-04-10 14:31:40 +0100)
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target/arm: Set MVFR0.FPSP for ARMv5 cpus (2020-02-21 16:07:03 +0000)
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----------------------------------------------------------------
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----------------------------------------------------------------
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target-arm: Fix bug where we weren't initializing
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target-arm queue:
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guarded bit state when combining S1/S2 attrs
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* aspeed/scu: Implement chip ID register
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* hw/misc/iotkit-secctl: Fix writing to 'PPC Interrupt Clear' register
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* mainstone: Make providing flash images non-mandatory
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* z2: Make providing flash images non-mandatory
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* Fix failures to flush SVE high bits after AdvSIMD INS/ZIP/UZP/TRN/TBL/TBX/EXT
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* Minor performance improvement: spend less time recalculating hflags values
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* Code cleanup to isar_feature function tests
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* Implement ARMv8.1-PMU and ARMv8.4-PMU extensions
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* Bugfix: correct handling of PMCR_EL0.LC bit
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* Bugfix: correct definition of PMCRDP
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* Correctly implement ACTLR2, HACTLR2
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* allwinner: Wire up USB ports
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* Vectorize emulation of USHL, SSHL, PMUL*
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* xilinx_spips: Correct the number of dummy cycles for the FAST_READ_4 cmd
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* sh4: Fix PCI ISA IO memory subregion
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----------------------------------------------------------------
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----------------------------------------------------------------
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Richard Henderson (2):
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Francisco Iglesias (1):
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target/arm: PTE bit GP only applies to stage1
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xilinx_spips: Correct the number of dummy cycles for the FAST_READ_4 cmd
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target/arm: Copy guarded bit in combine_cacheattrs
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target/arm/ptw.c | 11 ++++++-----
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Guenter Roeck (6):
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1 file changed, 6 insertions(+), 5 deletions(-)
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mainstone: Make providing flash images non-mandatory
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z2: Make providing flash images non-mandatory
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hw: usb: hcd-ohci: Move OHCISysBusState and TYPE_SYSBUS_OHCI to include file
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hcd-ehci: Introduce "companion-enable" sysbus property
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arm: allwinner: Wire up USB ports
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sh4: Fix PCI ISA IO memory subregion
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Joel Stanley (2):
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aspeed/scu: Create separate write callbacks
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aspeed/scu: Implement chip ID register
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Peter Maydell (21):
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target/arm: Add _aa32_ to isar_feature functions testing 32-bit ID registers
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target/arm: Check aa32_pan in take_aarch32_exception(), not aa64_pan
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target/arm: Add isar_feature_any_fp16 and document naming/usage conventions
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target/arm: Define and use any_predinv isar_feature test
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target/arm: Factor out PMU register definitions
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target/arm: Add and use FIELD definitions for ID_AA64DFR0_EL1
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target/arm: Use FIELD macros for clearing ID_DFR0 PERFMON field
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target/arm: Define an aa32_pmu_8_1 isar feature test function
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target/arm: Add _aa64_ and _any_ versions of pmu_8_1 isar checks
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target/arm: Stop assuming DBGDIDR always exists
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target/arm: Move DBGDIDR into ARMISARegisters
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target/arm: Read debug-related ID registers from KVM
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target/arm: Implement ARMv8.1-PMU extension
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target/arm: Implement ARMv8.4-PMU extension
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target/arm: Provide ARMv8.4-PMU in '-cpu max'
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target/arm: Correct definition of PMCRDP
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target/arm: Correct handling of PMCR_EL0.LC bit
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target/arm: Test correct register in aa32_pan and aa32_ats1e1 checks
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target/arm: Use isar_feature function for testing AA32HPD feature
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target/arm: Use FIELD_EX32 for testing 32-bit fields
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target/arm: Correctly implement ACTLR2, HACTLR2
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Philippe Mathieu-Daudé (1):
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hw/misc/iotkit-secctl: Fix writing to 'PPC Interrupt Clear' register
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Richard Henderson (15):
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target/arm: Flush high bits of sve register after AdvSIMD EXT
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target/arm: Flush high bits of sve register after AdvSIMD TBL/TBX
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target/arm: Flush high bits of sve register after AdvSIMD ZIP/UZP/TRN
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target/arm: Flush high bits of sve register after AdvSIMD INS
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target/arm: Use bit 55 explicitly for pauth
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target/arm: Fix select for aa64_va_parameters_both
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target/arm: Remove ttbr1_valid check from get_phys_addr_lpae
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target/arm: Split out aa64_va_parameter_tbi, aa64_va_parameter_tbid
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target/arm: Vectorize USHL and SSHL
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target/arm: Convert PMUL.8 to gvec
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target/arm: Convert PMULL.64 to gvec
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target/arm: Convert PMULL.8 to gvec
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target/arm: Rename isar_feature_aa32_simd_r32
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target/arm: Use isar_feature_aa32_simd_r32 more places
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target/arm: Set MVFR0.FPSP for ARMv5 cpus
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hw/usb/hcd-ohci.h | 16 ++
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include/hw/arm/allwinner-a10.h | 6 +
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target/arm/cpu.h | 145 ++++++++++---
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target/arm/helper-sve.h | 2 +
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target/arm/helper.h | 21 +-
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target/arm/internals.h | 47 ++++-
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target/arm/translate.h | 6 +
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hw/arm/allwinner-a10.c | 43 ++++
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hw/arm/mainstone.c | 11 +-
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hw/arm/z2.c | 6 -
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hw/intc/armv7m_nvic.c | 10 +-
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hw/misc/aspeed_scu.c | 93 ++++++--
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hw/misc/iotkit-secctl.c | 2 +-
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hw/sh4/sh_pci.c | 11 +-
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hw/ssi/xilinx_spips.c | 2 +-
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hw/usb/hcd-ehci-sysbus.c | 2 +
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hw/usb/hcd-ohci.c | 15 --
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linux-user/elfload.c | 4 +-
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target/arm/cpu.c | 169 +++++++--------
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target/arm/cpu64.c | 58 +++--
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target/arm/debug_helper.c | 6 +-
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target/arm/helper.c | 468 +++++++++++++++++++++++------------------
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target/arm/kvm32.c | 25 +++
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target/arm/kvm64.c | 46 ++++
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target/arm/neon_helper.c | 117 -----------
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target/arm/pauth_helper.c | 3 +-
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target/arm/translate-a64.c | 92 ++++----
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target/arm/translate-vfp.inc.c | 53 ++---
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target/arm/translate.c | 356 ++++++++++++++++++++++++++-----
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target/arm/vec_helper.c | 211 +++++++++++++++++++
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target/arm/vfp_helper.c | 2 +-
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31 files changed, 1377 insertions(+), 671 deletions(-)
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diff view generated by jsdifflib
[PULL 1/2] target/arm: PTE bit GP only applies to stage1
Deleted patch
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From: Richard Henderson <richard.henderson@linaro.org>
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Only perform the extract of GP during the stage1 walk.
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Reported-by: Peter Maydell <peter.maydell@linaro.org>
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Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
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Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
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Message-id: 20230407185149.3253946-2-richard.henderson@linaro.org
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Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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---
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target/arm/ptw.c | 10 +++++-----
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1 file changed, 5 insertions(+), 5 deletions(-)
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diff --git a/target/arm/ptw.c b/target/arm/ptw.c
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index XXXXXXX..XXXXXXX 100644
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--- a/target/arm/ptw.c
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+++ b/target/arm/ptw.c
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@@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_lpae(CPUARMState *env, S1Translate *ptw,
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result->f.attrs.secure = false;
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}
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- /* When in aarch64 mode, and BTI is enabled, remember GP in the TLB. */
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- if (aarch64 && cpu_isar_feature(aa64_bti, cpu)) {
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- result->f.guarded = extract64(attrs, 50, 1); /* GP */
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- }
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-
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if (regime_is_stage2(mmu_idx)) {
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result->cacheattrs.is_s2_format = true;
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result->cacheattrs.attrs = extract32(attrs, 2, 4);
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@@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_lpae(CPUARMState *env, S1Translate *ptw,
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assert(attrindx <= 7);
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result->cacheattrs.is_s2_format = false;
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result->cacheattrs.attrs = extract64(mair, attrindx * 8, 8);
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+
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+ /* When in aarch64 mode, and BTI is enabled, remember GP in the TLB. */
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+ if (aarch64 && cpu_isar_feature(aa64_bti, cpu)) {
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+ result->f.guarded = extract64(attrs, 50, 1); /* GP */
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+ }
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}
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/*
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--
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2.34.1
diff view generated by jsdifflib
[PULL 2/2] target/arm: Copy guarded bit in combine_cacheattrs
Deleted patch
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From: Richard Henderson <richard.henderson@linaro.org>
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The guarded bit comes from the stage1 walk.
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Fixes: Coverity CID 1507929
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Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
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Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
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Message-id: 20230407185149.3253946-3-richard.henderson@linaro.org
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Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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---
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target/arm/ptw.c | 1 +
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1 file changed, 1 insertion(+)
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diff --git a/target/arm/ptw.c b/target/arm/ptw.c
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index XXXXXXX..XXXXXXX 100644
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--- a/target/arm/ptw.c
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+++ b/target/arm/ptw.c
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@@ -XXX,XX +XXX,XX @@ static ARMCacheAttrs combine_cacheattrs(uint64_t hcr,
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assert(!s1.is_s2_format);
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ret.is_s2_format = false;
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+ ret.guarded = s1.guarded;
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if (s1.attrs == 0xf0) {
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tagged = true;
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--
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2.34.1
diff view generated by jsdifflib

Patchew 2.1-devel-b67e4c2

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