v1->v2 changes: dropped the last 6 patches from rth as there's
a problem with one of them that's too complicated to try to
fix up.
thanks
-- PMM
The following changes since commit a8c6af67e1e8d460e2c6e87070807e0a02c0fec2:
Merge remote-tracking branch 'remotes/dgibson/tags/ppc-for-5.0-20200221' into staging (2020-02-21 14:20:42 +0000)
are available in the Git repository at:
https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20200221-1
for you to fetch changes up to 9eb4f58918a851fb46895fd9b7ce579afeac9d02:
target/arm: Set MVFR0.FPSP for ARMv5 cpus (2020-02-21 16:07:03 +0000)
----------------------------------------------------------------
target-arm queue:
* aspeed/scu: Implement chip ID register
* hw/misc/iotkit-secctl: Fix writing to 'PPC Interrupt Clear' register
* mainstone: Make providing flash images non-mandatory
* z2: Make providing flash images non-mandatory
* Fix failures to flush SVE high bits after AdvSIMD INS/ZIP/UZP/TRN/TBL/TBX/EXT
* Minor performance improvement: spend less time recalculating hflags values
* Code cleanup to isar_feature function tests
* Implement ARMv8.1-PMU and ARMv8.4-PMU extensions
* Bugfix: correct handling of PMCR_EL0.LC bit
* Bugfix: correct definition of PMCRDP
* Correctly implement ACTLR2, HACTLR2
* allwinner: Wire up USB ports
* Vectorize emulation of USHL, SSHL, PMUL*
* xilinx_spips: Correct the number of dummy cycles for the FAST_READ_4 cmd
* sh4: Fix PCI ISA IO memory subregion
----------------------------------------------------------------
Francisco Iglesias (1):
xilinx_spips: Correct the number of dummy cycles for the FAST_READ_4 cmd
Guenter Roeck (6):
mainstone: Make providing flash images non-mandatory
z2: Make providing flash images non-mandatory
hw: usb: hcd-ohci: Move OHCISysBusState and TYPE_SYSBUS_OHCI to include file
hcd-ehci: Introduce "companion-enable" sysbus property
arm: allwinner: Wire up USB ports
sh4: Fix PCI ISA IO memory subregion
Joel Stanley (2):
aspeed/scu: Create separate write callbacks
aspeed/scu: Implement chip ID register
Peter Maydell (21):
target/arm: Add _aa32_ to isar_feature functions testing 32-bit ID registers
target/arm: Check aa32_pan in take_aarch32_exception(), not aa64_pan
target/arm: Add isar_feature_any_fp16 and document naming/usage conventions
target/arm: Define and use any_predinv isar_feature test
target/arm: Factor out PMU register definitions
target/arm: Add and use FIELD definitions for ID_AA64DFR0_EL1
target/arm: Use FIELD macros for clearing ID_DFR0 PERFMON field
target/arm: Define an aa32_pmu_8_1 isar feature test function
target/arm: Add _aa64_ and _any_ versions of pmu_8_1 isar checks
target/arm: Stop assuming DBGDIDR always exists
target/arm: Move DBGDIDR into ARMISARegisters
target/arm: Read debug-related ID registers from KVM
target/arm: Implement ARMv8.1-PMU extension
target/arm: Implement ARMv8.4-PMU extension
target/arm: Provide ARMv8.4-PMU in '-cpu max'
target/arm: Correct definition of PMCRDP
target/arm: Correct handling of PMCR_EL0.LC bit
target/arm: Test correct register in aa32_pan and aa32_ats1e1 checks
target/arm: Use isar_feature function for testing AA32HPD feature
target/arm: Use FIELD_EX32 for testing 32-bit fields
target/arm: Correctly implement ACTLR2, HACTLR2
Philippe Mathieu-Daudé (1):
hw/misc/iotkit-secctl: Fix writing to 'PPC Interrupt Clear' register
Richard Henderson (15):
target/arm: Flush high bits of sve register after AdvSIMD EXT
target/arm: Flush high bits of sve register after AdvSIMD TBL/TBX
target/arm: Flush high bits of sve register after AdvSIMD ZIP/UZP/TRN
target/arm: Flush high bits of sve register after AdvSIMD INS
target/arm: Use bit 55 explicitly for pauth
target/arm: Fix select for aa64_va_parameters_both
target/arm: Remove ttbr1_valid check from get_phys_addr_lpae
target/arm: Split out aa64_va_parameter_tbi, aa64_va_parameter_tbid
target/arm: Vectorize USHL and SSHL
target/arm: Convert PMUL.8 to gvec
target/arm: Convert PMULL.64 to gvec
target/arm: Convert PMULL.8 to gvec
target/arm: Rename isar_feature_aa32_simd_r32
target/arm: Use isar_feature_aa32_simd_r32 more places
target/arm: Set MVFR0.FPSP for ARMv5 cpus
hw/usb/hcd-ohci.h | 16 ++
include/hw/arm/allwinner-a10.h | 6 +
target/arm/cpu.h | 145 ++++++++++---
target/arm/helper-sve.h | 2 +
target/arm/helper.h | 21 +-
target/arm/internals.h | 47 ++++-
target/arm/translate.h | 6 +
hw/arm/allwinner-a10.c | 43 ++++
hw/arm/mainstone.c | 11 +-
hw/arm/z2.c | 6 -
hw/intc/armv7m_nvic.c | 10 +-
hw/misc/aspeed_scu.c | 93 ++++++--
hw/misc/iotkit-secctl.c | 2 +-
hw/sh4/sh_pci.c | 11 +-
hw/ssi/xilinx_spips.c | 2 +-
hw/usb/hcd-ehci-sysbus.c | 2 +
hw/usb/hcd-ohci.c | 15 --
linux-user/elfload.c | 4 +-
target/arm/cpu.c | 169 +++++++--------
target/arm/cpu64.c | 58 +++--
target/arm/debug_helper.c | 6 +-
target/arm/helper.c | 468 +++++++++++++++++++++++------------------
target/arm/kvm32.c | 25 +++
target/arm/kvm64.c | 46 ++++
target/arm/neon_helper.c | 117 -----------
target/arm/pauth_helper.c | 3 +-
target/arm/translate-a64.c | 92 ++++----
target/arm/translate-vfp.inc.c | 53 ++---
target/arm/translate.c | 356 ++++++++++++++++++++++++++-----
target/arm/vec_helper.c | 211 +++++++++++++++++++
target/arm/vfp_helper.c | 2 +-
31 files changed, 1377 insertions(+), 671 deletions(-)