Hi,

This v5 is based on top of:

"[PATCH v2 00/19] remove MISA ext_N flags from cpu->cfg"

We went from 25 patches to 9 because we no longer need to mirror changes
from env->misa_ext to cpu->cfg.ext_N back and forth. A lot of patches
got cut because of it.

write_misa() now uses the validate function as is, without the need to
changing it to use an 'ext' value. Rolling back env->misa_ext on
validation failure is trivial enough to not justify the extra effort of
making the validate functions use an 'ext' var. 

I also decided to dropped the patches that were splitting MISA
validation from the regular validation. A small change was done in
riscv_cpu_validate_set_extensions() to prevent it from writing
env->misa_ext_mask during write_misa(). Fragmenting the validation at
this point would just make us call 2 validate functions instead of just
one, without any tangible benefits. 

Another notable change is that we're not handling RVE and RVG in
separate. The only special handling done is when disabling extensions
that disables RVG.


Patches missing acks: patch 9. 


Changes from v4:
- the following patches were dropped:
  - target/riscv: move pmp and epmp validations to validate_set_extensions()
  - target/riscv/cpu.c: avoid set_misa() in validate_set_extensions()
  - target/riscv/cpu.c: set cpu config in set_misa()
  - target/riscv/cpu.c: redesign register_cpu_props()
  - target/riscv: put env->misa_ext <-> cpu->cfg code into helpers
  - target/riscv: add RVG
  - target/riscv/cpu.c: split RVG code from validate_set_extensions()
  - target/riscv/cpu.c: add riscv_cpu_validate_misa_ext()
  - target/riscv: move riscv_cpu_validate_v() to validate_misa_ext()
  - target/riscv: error out on priv failure for RVH
  - target/riscv: write env->misa_ext* in register_generic_cpu_props()
  - target/riscv: make validate_misa_ext() use a misa_ext val
  - target/riscv: split riscv_cpu_validate_set_extensions()
  - target/riscv: use misa_ext val in riscv_cpu_validate_extensions()
  - target/riscv: update cpu->cfg misa bits in commit_cpu_cfg()
  - target/riscv: handle RVG updates in write_misa()
- patch 9:
  - use riscv_cpu_validate_set_extensions() directly
  - do not handle RVE and RVG separately
  - handle RVG disable if any of its dependencies are disabled
- v4 link: https://lists.gnu.org/archive/html/qemu-devel/2023-03/msg05785.html

Daniel Henrique Barboza (9):
  target/riscv/cpu.c: add riscv_cpu_validate_v()
  target/riscv/cpu.c: remove set_vext_version()
  target/riscv/cpu.c: remove set_priv_version()
  target/riscv: add PRIV_VERSION_LATEST
  target/riscv/cpu.c: add priv_spec validate/disable_exts helpers
  target/riscv/cpu.c: add riscv_cpu_validate_misa_mxl()
  target/riscv/cpu.c: validate extensions before riscv_timer_init()
  target/riscv/cpu.c: remove cfg setup from riscv_cpu_init()
  target/riscv: rework write_misa()

 target/riscv/cpu.c | 331 +++++++++++++++++++++++++++------------------
 target/riscv/cpu.h |   3 +
 target/riscv/csr.c |  47 +++----
 3 files changed, 222 insertions(+), 159 deletions(-)

-- 
2.39.2