From nobody Wed May 8 22:12:36 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1680025072; cv=none; d=zohomail.com; s=zohoarc; b=HcQgMcwyAVH2q8QB7EQYW5gAqLD8EwWj4inD7jrhK8W9tkoGMH7XJ4ECR9CKsCq/ymRkrvQoZqmkocLYW3/HVxMACskMIbBe/u3OSS2Srgeox08rUnFg5zZlnSjhTvrUqmw1wgkgVv+IzRfrvHFXtTmAUdZpR7tQWnNUUtcu3SI= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1680025072; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=492Vk2cHqmetgd74FBCPwN62VV5sp+gd1vork/TOft8=; b=L97omZtXvea1SE4R0HzmyDerEsWM5E3mkzENRguG4pm2TLQtgfIgTKjoEzOX6VnVwZGXAOiG6s4T9NCZz1Mw6p5tLb9vUeeq+KNsSsOFLAhehztK+Z96XDBXtFxixHDWAb5ffl9GQmP5nZFgS5vfV/RZPNKJhlYGnasPu9gtwCM= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1680025071996373.40676873823975; Tue, 28 Mar 2023 10:37:51 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1phDEm-00086j-1i; Tue, 28 Mar 2023 13:36:00 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1phDEk-00086K-D7 for qemu-devel@nongnu.org; Tue, 28 Mar 2023 13:35:58 -0400 Received: from mail-oa1-x36.google.com ([2001:4860:4864:20::36]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1phDEi-0005K6-On for qemu-devel@nongnu.org; Tue, 28 Mar 2023 13:35:58 -0400 Received: by mail-oa1-x36.google.com with SMTP id 586e51a60fabf-17ebba88c60so13518265fac.3 for ; Tue, 28 Mar 2023 10:35:56 -0700 (PDT) Received: from grind.. ([177.95.89.231]) by smtp.gmail.com with ESMTPSA id m2-20020a9d6442000000b0069f0a85fa36sm11635654otl.57.2023.03.28.10.35.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 28 Mar 2023 10:35:54 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1680024955; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=492Vk2cHqmetgd74FBCPwN62VV5sp+gd1vork/TOft8=; b=ieYls4fpyXIbyPxHV7APwRg9CU5FpfYI+o5jed58vHRnl2Sov5IZvr3WQ9zFF2qmam jxFYGEfodi5XLUbRw92Nb/T1q2fvGF/l2XXd8jaCuiv6FdGYpI5ta/3ndFwMtbzlLe+n VOevtCqGnMIxWG9oLDDa2A+UDanFEWqWbi5Ysgdp5Z2zWLywbQB276QzdGL7gJDfSBKA s0UzBTuuFUzcQ43P4L3Z2oZyk+0rHnWc5+kLyy+882vi6vDSqhrKrtmP87G2E2SpIMxE GAks2DTLoRT3uLT+MOlVL9I8iXWBEzQzu0fGtyFMR9JhzEjCr096Fh+e43igZ5hya733 h80Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1680024955; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=492Vk2cHqmetgd74FBCPwN62VV5sp+gd1vork/TOft8=; b=asK4IMFuHGGNNIxeZ19xSEm6Ik9GlwmPXja9gK+CpMqtkrOaJaqALZDbQhPEEKE6Bx T26RM0UNZ8qq6ysO3FbUiYEimOSRBTOag9Z862lFJpjQxBmab7QoSItVF+vJRQ7R16lo WPqGefhF4FNRNIev4Uh9ZFtNL5zxaJUW4yERG7uUxc0eK2IieyukJ/+7/wHtl20j2Wiw 5MWjnMfzXi2Uj49BOihp+iYs03mTcvUKcejJzkSOjy/RMVa/wB+85+znCS/Cxtn75u07 JQVzzbcIquoNuyHsVN1U6F9wXXGZadraS9JkFYAIWuoYPmp+v5cDN4JG3z4joP/hy2Wp RFKA== X-Gm-Message-State: AAQBX9eb3LnnJbUSiuFRHYVw0A66cxkstCfK8xGdHpmMl2mQ2MadDjRf CUmKKFTS8lV9HlpqmELUZrFz7gbGmsV9ZnbtjI4= X-Google-Smtp-Source: AKy350b3yhhkaBbs1LRAmuvwpNluxcFmBEXmQDIeOCv3Z3d95v//8lbnF8I7wuYzI8ubAx+5fjze3A== X-Received: by 2002:a05:6870:c192:b0:17e:e1ac:2efe with SMTP id h18-20020a056870c19200b0017ee1ac2efemr10431982oad.44.1680024955313; Tue, 28 Mar 2023 10:35:55 -0700 (PDT) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, bmeng@tinylab.org, liweiwei@iscas.ac.cn, zhiwei_liu@linux.alibaba.com, palmer@rivosinc.com, Daniel Henrique Barboza Subject: [PATCH v5 1/9] target/riscv/cpu.c: add riscv_cpu_validate_v() Date: Tue, 28 Mar 2023 14:35:35 -0300 Message-Id: <20230328173543.431342-2-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230328173543.431342-1-dbarboza@ventanamicro.com> References: <20230328173543.431342-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2001:4860:4864:20::36; envelope-from=dbarboza@ventanamicro.com; helo=mail-oa1-x36.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ventanamicro.com) X-ZM-MESSAGEID: 1680025073415100011 Content-Type: text/plain; charset="utf-8" The RVV verification will error out if fails and it's being done at the end of riscv_cpu_validate_set_extensions(), after we've already set some extensions that are dependent on RVV. Let's put it in its own function and do it earlier. Signed-off-by: Daniel Henrique Barboza Reviewed-by: LIU Zhiwei --- target/riscv/cpu.c | 89 +++++++++++++++++++++++++--------------------- 1 file changed, 48 insertions(+), 41 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 08cf5e9815..bd6d65365b 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -791,6 +791,46 @@ static void riscv_cpu_disas_set_info(CPUState *s, disa= ssemble_info *info) } } =20 +static void riscv_cpu_validate_v(CPURISCVState *env, RISCVCPUConfig *cfg, + Error **errp) +{ + int vext_version =3D VEXT_VERSION_1_00_0; + + if (!is_power_of_2(cfg->vlen)) { + error_setg(errp, "Vector extension VLEN must be power of 2"); + return; + } + if (cfg->vlen > RV_VLEN_MAX || cfg->vlen < 128) { + error_setg(errp, + "Vector extension implementation only supports VLEN " + "in the range [128, %d]", RV_VLEN_MAX); + return; + } + if (!is_power_of_2(cfg->elen)) { + error_setg(errp, "Vector extension ELEN must be power of 2"); + return; + } + if (cfg->elen > 64 || cfg->elen < 8) { + error_setg(errp, + "Vector extension implementation only supports ELEN " + "in the range [8, 64]"); + return; + } + if (cfg->vext_spec) { + if (!g_strcmp0(cfg->vext_spec, "v1.0")) { + vext_version =3D VEXT_VERSION_1_00_0; + } else { + error_setg(errp, "Unsupported vector spec version '%s'", + cfg->vext_spec); + return; + } + } else { + qemu_log("vector version is not specified, " + "use the default value v1.0\n"); + } + set_vext_version(env, vext_version); +} + /* * Check consistency between chosen extensions while setting * cpu->cfg accordingly. @@ -798,6 +838,7 @@ static void riscv_cpu_disas_set_info(CPUState *s, disas= semble_info *info) static void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp) { CPURISCVState *env =3D &cpu->env; + Error *local_err =3D NULL; =20 /* Do some ISA extension error checking */ if (riscv_has_ext(env, RVG) && @@ -866,8 +907,14 @@ static void riscv_cpu_validate_set_extensions(RISCVCPU= *cpu, Error **errp) return; } =20 - /* The V vector extension depends on the Zve64d extension */ if (riscv_has_ext(env, RVV)) { + riscv_cpu_validate_v(env, &cpu->cfg, &local_err); + if (local_err !=3D NULL) { + error_propagate(errp, local_err); + return; + } + + /* The V vector extension depends on the Zve64d extension */ cpu->cfg.ext_zve64d =3D true; } =20 @@ -948,46 +995,6 @@ static void riscv_cpu_validate_set_extensions(RISCVCPU= *cpu, Error **errp) cpu->cfg.ext_zksed =3D true; cpu->cfg.ext_zksh =3D true; } - - if (riscv_has_ext(env, RVV)) { - int vext_version =3D VEXT_VERSION_1_00_0; - if (!is_power_of_2(cpu->cfg.vlen)) { - error_setg(errp, - "Vector extension VLEN must be power of 2"); - return; - } - if (cpu->cfg.vlen > RV_VLEN_MAX || cpu->cfg.vlen < 128) { - error_setg(errp, - "Vector extension implementation only supports VLEN= " - "in the range [128, %d]", RV_VLEN_MAX); - return; - } - if (!is_power_of_2(cpu->cfg.elen)) { - error_setg(errp, - "Vector extension ELEN must be power of 2"); - return; - } - if (cpu->cfg.elen > 64 || cpu->cfg.elen < 8) { - error_setg(errp, - "Vector extension implementation only supports ELEN= " - "in the range [8, 64]"); - return; - } - if (cpu->cfg.vext_spec) { - if (!g_strcmp0(cpu->cfg.vext_spec, "v1.0")) { - vext_version =3D VEXT_VERSION_1_00_0; - } else { - error_setg(errp, - "Unsupported vector spec version '%s'", - cpu->cfg.vext_spec); - return; - } - } else { - qemu_log("vector version is not specified, " - "use the default value v1.0\n"); - } - set_vext_version(env, vext_version); - } } =20 #ifndef CONFIG_USER_ONLY --=20 2.39.2 From nobody Wed May 8 22:12:36 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1680024975; cv=none; d=zohomail.com; s=zohoarc; b=EKvobiyn86A1zw42/T5fexEz9q8Id2IysrovXIZhO7RIqCDO5BE+/urDuSMo0roetXJV5/ta1yJ0qT/MwK6lcuceXd8hKwCk5WBVRSXxr93Va05SbOj8ewo/XxBeK1UP1kublOdjen9Iev/5RjCzFxkKg7SOJnEZZ7RDEA9gHjw= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; 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([177.95.89.231]) by smtp.gmail.com with ESMTPSA id m2-20020a9d6442000000b0069f0a85fa36sm11635654otl.57.2023.03.28.10.35.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 28 Mar 2023 10:35:58 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1680024958; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=aCyQ646C0mVMkPcWOjWnws2MgdEze6R0Nd3WdD81i8Q=; b=CsRPpSJPtUSh8tPmGpXlfmZzGO4Paz+6STdXdRuv+pnUA2UpjJ3Iv2iFYsqD7yuAP6 Ayzj0FvL0bclfHfCDYs+vHr3gIkcrJ71CkSsLF1LztUVh5kI2QgeY5JiwA6NuEKpFohQ m65Pab5t0N5GxTpiKFJpIN+W0/nE+l9js3QSy4+Fq0CF8J/RBhnE5Ex0xW++chN8Jv+p cdhgYdcVVAAabVSrKdIjxTRNb/yXOn79U6/Ps0sEpyh9EpPo25AWL5VPbko5sQN8sAzF 7ReIejd4jWuYaytPNTYYIJ6AAQtl+Jc8NYfJ+/s0qDMtuktvnxEObPnEz6If9sWrEI7D X0yQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1680024958; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=aCyQ646C0mVMkPcWOjWnws2MgdEze6R0Nd3WdD81i8Q=; b=CcU+DIHz9TZJ4OKy+XbApm9Q4GLtRS4MgwOMciT5NEwktLywdJK/UZxYnvo51SCePf pLSky6HXKoCJs7I+0Q8ps4d3VkgqpudWx51m4cccLKwA+scelzJcqRIppA5Mh1NyHLVq 7WeqBwlmYLHtBkgYcFXq76QEPqVDMstnzXnbY77/g3znrOVljcSwdftOfxxBWi+icKu4 3y2GA4sImO4QPYhweC9pkW/qvCLCTTsk0NACqx4n0l5c6UQN1BY7IVBmvOXLfa0gVbgE gGcSZ2B0zvTX3XIGMIqa9jkGqI9NhRs2Tki913TwntQsAI12naMvSUZtoQxYaSsoQMIw IHhw== X-Gm-Message-State: AAQBX9fOZGZ2fQUdYEwxSmFt6qQzWYSPzuIQkGKdHgBvNi6F8mhWEIbG OlFKJ/ZN2mQbbD7Hg9yagNTs2ZZH6L9MY5NKKBw= X-Google-Smtp-Source: AKy350ZfubuarN6lwqTLfWiguIVedSf10RLtT5j6FZeaLSQfUZPQgtwxbQPds7k0wEOxHURL6bMLWA== X-Received: by 2002:a05:6870:631d:b0:177:b6ed:a154 with SMTP id s29-20020a056870631d00b00177b6eda154mr9981392oao.34.1680024958651; Tue, 28 Mar 2023 10:35:58 -0700 (PDT) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, bmeng@tinylab.org, liweiwei@iscas.ac.cn, zhiwei_liu@linux.alibaba.com, palmer@rivosinc.com, Daniel Henrique Barboza Subject: [PATCH v5 2/9] target/riscv/cpu.c: remove set_vext_version() Date: Tue, 28 Mar 2023 14:35:36 -0300 Message-Id: <20230328173543.431342-3-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230328173543.431342-1-dbarboza@ventanamicro.com> References: <20230328173543.431342-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2001:4860:4864:20::2f; envelope-from=dbarboza@ventanamicro.com; helo=mail-oa1-x2f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ventanamicro.com) X-ZM-MESSAGEID: 1680024976610100007 Content-Type: text/plain; charset="utf-8" This setter is doing nothing else but setting env->vext_ver. Assign the value directly. Signed-off-by: Daniel Henrique Barboza Reviewed-by: LIU Zhiwei --- target/riscv/cpu.c | 7 +------ 1 file changed, 1 insertion(+), 6 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index bd6d65365b..f59e52ae4d 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -246,11 +246,6 @@ static void set_priv_version(CPURISCVState *env, int p= riv_ver) env->priv_ver =3D priv_ver; } =20 -static void set_vext_version(CPURISCVState *env, int vext_ver) -{ - env->vext_ver =3D vext_ver; -} - #ifndef CONFIG_USER_ONLY static uint8_t satp_mode_from_str(const char *satp_mode_str) { @@ -828,7 +823,7 @@ static void riscv_cpu_validate_v(CPURISCVState *env, RI= SCVCPUConfig *cfg, qemu_log("vector version is not specified, " "use the default value v1.0\n"); } - set_vext_version(env, vext_version); + env->vext_ver =3D vext_version; } =20 /* --=20 2.39.2 From nobody Wed May 8 22:12:36 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1680025070; cv=none; d=zohomail.com; s=zohoarc; b=PknQ8TfuEADLgz9GKn843x44NSvIG9pSlUsxYHSBCmFhbnh1/E8+hiCVppac4+Fd/svGt1Oslobw9FY/3yjeCkjTSSCskxUicKRZp+2ExF1olD/bJh+JwpF2ufjJ60ozz3XjEFnfBsRd393WV1UU7QBok9sY1SNDF8CLx5DQNII= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1680025070; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=nG8maGkUaqGATRWGqElr61HEeYmxQ4huBBDCKZeHzyk=; b=FTSjvCniYzPhSQHX4Xo4fAbMI0KmX86BlWOyVezt+qJRx3RoMNPc756D2KfKMEDnDG5B0MlN+pDc3IfgupTLzdRJwt6c8VbSsTZd5NslEdRBrs2Ybltb2HgRemCcRd5/I177uPk5LowhUA4m4dB/iehbaoyJDSuMmeQn2k7dC1A= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1680025070889929.8197445557854; Tue, 28 Mar 2023 10:37:50 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1phDEs-00088k-8w; Tue, 28 Mar 2023 13:36:06 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1phDEr-00088G-E5 for qemu-devel@nongnu.org; Tue, 28 Mar 2023 13:36:05 -0400 Received: from mail-oa1-x2c.google.com ([2001:4860:4864:20::2c]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1phDEp-0005OX-6R for qemu-devel@nongnu.org; Tue, 28 Mar 2023 13:36:05 -0400 Received: by mail-oa1-x2c.google.com with SMTP id 586e51a60fabf-17aaa51a911so13514048fac.5 for ; Tue, 28 Mar 2023 10:36:02 -0700 (PDT) Received: from grind.. ([177.95.89.231]) by smtp.gmail.com with ESMTPSA id m2-20020a9d6442000000b0069f0a85fa36sm11635654otl.57.2023.03.28.10.35.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 28 Mar 2023 10:36:01 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1680024961; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=nG8maGkUaqGATRWGqElr61HEeYmxQ4huBBDCKZeHzyk=; b=gPunUNSQCq4pi6QfzXcwZSrGengR/72lTs1K4d4nm3zXTzev+5oXOsTBnTCq9Bbnx2 fBlGQLk0UzCkkJh7bQYvc59+fZP0k+YkXrsZq8u6pWdf+tN50LIKIe99AlVEj2uMoL37 HI2+1Lw8QZ/tnIYCZVuQkqz8xuTKyU6vU3qfN7MPT5iwLEJFRg1UuxMA8DaSX9kGXhxP 3QAdHoJTyC04oPX9Ms3qkWDVoGYTjLqbfv5+eW2UhxSOjrSb8R6Jur6oBd0MpdHxzUg0 7HTsG9z1GdZ1nfuxX39sKs4baxRqo1TIKqBliqdvC6c6+RmxTeP85Hvq8coo+Ew39qS8 Lunw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1680024961; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=nG8maGkUaqGATRWGqElr61HEeYmxQ4huBBDCKZeHzyk=; b=iOPEngp3Wk5cSjW4RX/unPhAgRMPoAslOJ/+4uYTaDg9X8uxYBtopAvgPnP39DAX7a Zml3oIT/fp40zAwHHoXLEzBUrldCavMjIZEJNMcAqj2C5b8HGkoYDvZYS/wAfD/Dp4w5 haRDwNWKNOKiinliBiVlcsjyb4d7y/eoOu9dsYhAnQmH7B3pm9n4s6UExeKFhp16c00p 63+Bgoqyu6b+srMp4SJcNye1N1txYRGYk/Y197RvMjnfyrYYlNuSEUm7slfk2cmPbJrX JX2HA0lSco+tos1CQW/HRFXMhPxD1Qrf4fNKbCktf21rml3Lrjw1xuynQfnL+MqwRKXc 47KQ== X-Gm-Message-State: AO0yUKUNPBkLnwvc6/3xvCBf70l8GQ+JBizIv4b2P6nH1LOZDWhr00sB SyKFXnDSIa3y933krsKPQvnkumUUfDpPwNR7qdg= X-Google-Smtp-Source: AK7set8fbtrpGavhHRzEzOuRJCle53ntABuZjbHmkTYcIgejKAIjeLOXgQ3N4izVG8Jt81sCORi8ig== X-Received: by 2002:a05:6870:ec86:b0:17a:b060:7b0c with SMTP id eo6-20020a056870ec8600b0017ab0607b0cmr10356313oab.41.1680024961677; Tue, 28 Mar 2023 10:36:01 -0700 (PDT) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, bmeng@tinylab.org, liweiwei@iscas.ac.cn, zhiwei_liu@linux.alibaba.com, palmer@rivosinc.com, Daniel Henrique Barboza Subject: [PATCH v5 3/9] target/riscv/cpu.c: remove set_priv_version() Date: Tue, 28 Mar 2023 14:35:37 -0300 Message-Id: <20230328173543.431342-4-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230328173543.431342-1-dbarboza@ventanamicro.com> References: <20230328173543.431342-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2001:4860:4864:20::2c; envelope-from=dbarboza@ventanamicro.com; helo=mail-oa1-x2c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ventanamicro.com) X-ZM-MESSAGEID: 1680025071409100001 Content-Type: text/plain; charset="utf-8" The setter is doing nothing special. Just set env->priv_ver directly. Signed-off-by: Daniel Henrique Barboza Reviewed-by: LIU Zhiwei --- target/riscv/cpu.c | 29 ++++++++++++----------------- 1 file changed, 12 insertions(+), 17 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index f59e52ae4d..b40d76fcb9 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -241,11 +241,6 @@ static void set_misa(CPURISCVState *env, RISCVMXL mxl,= uint32_t ext) env->misa_ext_mask =3D env->misa_ext =3D ext; } =20 -static void set_priv_version(CPURISCVState *env, int priv_ver) -{ - env->priv_ver =3D priv_ver; -} - #ifndef CONFIG_USER_ONLY static uint8_t satp_mode_from_str(const char *satp_mode_str) { @@ -344,7 +339,7 @@ static void riscv_any_cpu_init(Object *obj) VM_1_10_SV32 : VM_1_10_SV57); #endif =20 - set_priv_version(env, PRIV_VERSION_1_12_0); + env->priv_ver =3D PRIV_VERSION_1_12_0; } =20 #if defined(TARGET_RISCV64) @@ -355,7 +350,7 @@ static void rv64_base_cpu_init(Object *obj) set_misa(env, MXL_RV64, 0); riscv_cpu_add_user_properties(obj); /* Set latest version of privileged specification */ - set_priv_version(env, PRIV_VERSION_1_12_0); + env->priv_ver =3D PRIV_VERSION_1_12_0; #ifndef CONFIG_USER_ONLY set_satp_mode_max_supported(RISCV_CPU(obj), VM_1_10_SV57); #endif @@ -365,7 +360,7 @@ static void rv64_sifive_u_cpu_init(Object *obj) { CPURISCVState *env =3D &RISCV_CPU(obj)->env; set_misa(env, MXL_RV64, RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU); - set_priv_version(env, PRIV_VERSION_1_10_0); + env->priv_ver =3D PRIV_VERSION_1_10_0; #ifndef CONFIG_USER_ONLY set_satp_mode_max_supported(RISCV_CPU(obj), VM_1_10_SV39); #endif @@ -377,7 +372,7 @@ static void rv64_sifive_e_cpu_init(Object *obj) RISCVCPU *cpu =3D RISCV_CPU(obj); =20 set_misa(env, MXL_RV64, RVI | RVM | RVA | RVC | RVU); - set_priv_version(env, PRIV_VERSION_1_10_0); + env->priv_ver =3D PRIV_VERSION_1_10_0; cpu->cfg.mmu =3D false; #ifndef CONFIG_USER_ONLY set_satp_mode_max_supported(cpu, VM_1_10_MBARE); @@ -390,7 +385,7 @@ static void rv64_thead_c906_cpu_init(Object *obj) RISCVCPU *cpu =3D RISCV_CPU(obj); =20 set_misa(env, MXL_RV64, RVG | RVC | RVS | RVU); - set_priv_version(env, PRIV_VERSION_1_11_0); + env->priv_ver =3D PRIV_VERSION_1_11_0; =20 cpu->cfg.ext_zfh =3D true; cpu->cfg.mmu =3D true; @@ -424,7 +419,7 @@ static void rv128_base_cpu_init(Object *obj) set_misa(env, MXL_RV128, 0); riscv_cpu_add_user_properties(obj); /* Set latest version of privileged specification */ - set_priv_version(env, PRIV_VERSION_1_12_0); + env->priv_ver =3D PRIV_VERSION_1_12_0; #ifndef CONFIG_USER_ONLY set_satp_mode_max_supported(RISCV_CPU(obj), VM_1_10_SV57); #endif @@ -437,7 +432,7 @@ static void rv32_base_cpu_init(Object *obj) set_misa(env, MXL_RV32, 0); riscv_cpu_add_user_properties(obj); /* Set latest version of privileged specification */ - set_priv_version(env, PRIV_VERSION_1_12_0); + env->priv_ver =3D PRIV_VERSION_1_12_0; #ifndef CONFIG_USER_ONLY set_satp_mode_max_supported(RISCV_CPU(obj), VM_1_10_SV32); #endif @@ -447,7 +442,7 @@ static void rv32_sifive_u_cpu_init(Object *obj) { CPURISCVState *env =3D &RISCV_CPU(obj)->env; set_misa(env, MXL_RV32, RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU); - set_priv_version(env, PRIV_VERSION_1_10_0); + env->priv_ver =3D PRIV_VERSION_1_10_0; #ifndef CONFIG_USER_ONLY set_satp_mode_max_supported(RISCV_CPU(obj), VM_1_10_SV32); #endif @@ -459,7 +454,7 @@ static void rv32_sifive_e_cpu_init(Object *obj) RISCVCPU *cpu =3D RISCV_CPU(obj); =20 set_misa(env, MXL_RV32, RVI | RVM | RVA | RVC | RVU); - set_priv_version(env, PRIV_VERSION_1_10_0); + env->priv_ver =3D PRIV_VERSION_1_10_0; cpu->cfg.mmu =3D false; #ifndef CONFIG_USER_ONLY set_satp_mode_max_supported(cpu, VM_1_10_MBARE); @@ -472,7 +467,7 @@ static void rv32_ibex_cpu_init(Object *obj) RISCVCPU *cpu =3D RISCV_CPU(obj); =20 set_misa(env, MXL_RV32, RVI | RVM | RVC | RVU); - set_priv_version(env, PRIV_VERSION_1_11_0); + env->priv_ver =3D PRIV_VERSION_1_11_0; cpu->cfg.mmu =3D false; #ifndef CONFIG_USER_ONLY set_satp_mode_max_supported(cpu, VM_1_10_MBARE); @@ -486,7 +481,7 @@ static void rv32_imafcu_nommu_cpu_init(Object *obj) RISCVCPU *cpu =3D RISCV_CPU(obj); =20 set_misa(env, MXL_RV32, RVI | RVM | RVA | RVF | RVC | RVU); - set_priv_version(env, PRIV_VERSION_1_10_0); + env->priv_ver =3D PRIV_VERSION_1_10_0; cpu->cfg.mmu =3D false; #ifndef CONFIG_USER_ONLY set_satp_mode_max_supported(cpu, VM_1_10_MBARE); @@ -1114,7 +1109,7 @@ static void riscv_cpu_realize(DeviceState *dev, Error= **errp) } =20 if (priv_version >=3D PRIV_VERSION_1_10_0) { - set_priv_version(env, priv_version); + env->priv_ver =3D priv_version; } =20 riscv_cpu_validate_misa_priv(env, &local_err); --=20 2.39.2 From nobody Wed May 8 22:12:36 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1680025053; cv=none; d=zohomail.com; s=zohoarc; b=B5N5nqAKKYLqr6BEl4Mp+R+UDshaCzW/xsgSOSO1lnkXBAvYd14xTtjjbUhOre3mgxMwDB/MvRYCdtxOahdpQOFvvADj212mVBlxGCIYRtUxPIFQ3wTKGlZDZh6Ol8z+AOYSKhka1tieHO/E+dA+pCLs+cwfLRReB+CQdWAjrc0= ARC-Message-Signature: i=1; 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([177.95.89.231]) by smtp.gmail.com with ESMTPSA id m2-20020a9d6442000000b0069f0a85fa36sm11635654otl.57.2023.03.28.10.36.01 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 28 Mar 2023 10:36:04 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1680024965; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=WOGslirMLBk4tm9faQsGEqmRXTsjgllDNHucBeLo/+s=; b=HDOelelsPEZGAxZ4RDnO0J/zcmFS1FKHMU7WmYi4wrxTlXepe9SzedAlMFxxTiwis3 kruMdOFhvmZoQ3t3lQOr/GlIrGx/KBWH+OVTAWvSQcsebfzMl+nnx6azju5cZaX/kaVe M5SzYr3sKlhdGsD3yO40DkBDhzjBdMkei6TUPQtSfH76c3lDlsCZ1EYPXfbd/Tipf9/9 LaqmcsZmGJHYDpM42IJ3ll8QEcFD1HefyETcGBal7GQeI7E1m2t3m6CVMSrhlPpZJDrv 1QVrj5GYqlAvdEUkWide0OFT5L4/gPaHa5o0oUtA0ZpZxDtClak06CgN2kEgTKJo9obc BoWw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1680024965; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=WOGslirMLBk4tm9faQsGEqmRXTsjgllDNHucBeLo/+s=; b=zOzZ1gMWWpvgL5uoVvvOhSFEIf2TzShTtn4JAetoroUxnQowsGKMaKcb52R4f4OAOi 8e72FxLIGJlZa2ePUKMFHid/Do6qbHwEvPhRh49nR9njAfkc64kZcvFxi+iLFPNl0RFl KIG16CJpGT+sS/OtTWb6Mv4NmpAuJ5xEkWhUy8HFqQ1m5+CKB7Gi/qwU00oGqSJPfxho wodUXopWHP4hEfabeSmBaXeShUrh1CMVkvOu/gIUgsFe9vQSjEZb57bdCu96ydwvHGeu hKgM+HPEmXooVFWxjrKD3MXTxXc52o+TTMWtrPSxVThqACMOB2Dfr6Bi7lkGuaNpX4FN 4yDg== X-Gm-Message-State: AAQBX9cWpDR1y35kFwdq6Q7/XzPdpo97WV6L2d9KlvEeWzbB9qjCTis6 FLN9sPIuKo5Gq1mIHShPitNXbvaYBy9tsRnT/z0= X-Google-Smtp-Source: AKy350ZLyaEbLwcPySu2Zx1sFBsb62tuaPxvAplOgVLq68/IgF/kS6RjqSZnees1Mt+TCQmfOwPNJw== X-Received: by 2002:a05:6870:89a3:b0:17e:da36:665a with SMTP id f35-20020a05687089a300b0017eda36665amr9114356oaq.8.1680024964913; Tue, 28 Mar 2023 10:36:04 -0700 (PDT) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, bmeng@tinylab.org, liweiwei@iscas.ac.cn, zhiwei_liu@linux.alibaba.com, palmer@rivosinc.com, Daniel Henrique Barboza , Richard Henderson Subject: [PATCH v5 4/9] target/riscv: add PRIV_VERSION_LATEST Date: Tue, 28 Mar 2023 14:35:38 -0300 Message-Id: <20230328173543.431342-5-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230328173543.431342-1-dbarboza@ventanamicro.com> References: <20230328173543.431342-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2001:4860:4864:20::36; envelope-from=dbarboza@ventanamicro.com; helo=mail-oa1-x36.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ventanamicro.com) X-ZM-MESSAGEID: 1680025055273100001 Content-Type: text/plain; charset="utf-8" All these generic CPUs are using the latest priv available, at this moment PRIV_VERSION_1_12_0: - riscv_any_cpu_init() - rv32_base_cpu_init() - rv64_base_cpu_init() - rv128_base_cpu_init() Create a new PRIV_VERSION_LATEST enum and use it in those cases. I'll make it easier to update everything at once when a new priv version is available. Signed-off-by: Daniel Henrique Barboza Reviewed-by: Richard Henderson Reviewed-by: LIU Zhiwei --- target/riscv/cpu.c | 8 ++++---- target/riscv/cpu.h | 2 ++ 2 files changed, 6 insertions(+), 4 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index b40d76fcb9..e13528d932 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -339,7 +339,7 @@ static void riscv_any_cpu_init(Object *obj) VM_1_10_SV32 : VM_1_10_SV57); #endif =20 - env->priv_ver =3D PRIV_VERSION_1_12_0; + env->priv_ver =3D PRIV_VERSION_LATEST; } =20 #if defined(TARGET_RISCV64) @@ -350,7 +350,7 @@ static void rv64_base_cpu_init(Object *obj) set_misa(env, MXL_RV64, 0); riscv_cpu_add_user_properties(obj); /* Set latest version of privileged specification */ - env->priv_ver =3D PRIV_VERSION_1_12_0; + env->priv_ver =3D PRIV_VERSION_LATEST; #ifndef CONFIG_USER_ONLY set_satp_mode_max_supported(RISCV_CPU(obj), VM_1_10_SV57); #endif @@ -419,7 +419,7 @@ static void rv128_base_cpu_init(Object *obj) set_misa(env, MXL_RV128, 0); riscv_cpu_add_user_properties(obj); /* Set latest version of privileged specification */ - env->priv_ver =3D PRIV_VERSION_1_12_0; + env->priv_ver =3D PRIV_VERSION_LATEST; #ifndef CONFIG_USER_ONLY set_satp_mode_max_supported(RISCV_CPU(obj), VM_1_10_SV57); #endif @@ -432,7 +432,7 @@ static void rv32_base_cpu_init(Object *obj) set_misa(env, MXL_RV32, 0); riscv_cpu_add_user_properties(obj); /* Set latest version of privileged specification */ - env->priv_ver =3D PRIV_VERSION_1_12_0; + env->priv_ver =3D PRIV_VERSION_LATEST; #ifndef CONFIG_USER_ONLY set_satp_mode_max_supported(RISCV_CPU(obj), VM_1_10_SV32); #endif diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 02f26130d5..03b5cc2cf4 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -86,6 +86,8 @@ enum { PRIV_VERSION_1_10_0 =3D 0, PRIV_VERSION_1_11_0, PRIV_VERSION_1_12_0, + + PRIV_VERSION_LATEST =3D PRIV_VERSION_1_12_0, }; =20 #define VEXT_VERSION_1_00_0 0x00010000 --=20 2.39.2 From nobody Wed May 8 22:12:36 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1680025042; cv=none; d=zohomail.com; s=zohoarc; b=ULvT5bMTaUyowdcqvf7TrWWHxk8RYD3mCxPf7lw8AqU51ETJroYL938ZRrfLVfGrKzTKzBUgxTp7J40eWPNH1yG/4OwsJVM8ma7QxB+1TISip/ud+71FAr7vRNAfX6XNrYGldxeelD1R5375I3RNA73QzqjfugVq0OWdbt6/He4= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1680025042; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=PJcYGrOPMg7QXNcY0p66T+ViExnDIcZu7iLjZ7e1LxM=; b=T3hDTlir5sfbpk1eCWBrSfzQengQ6qDOfN8PsCQom1vSAn2goiVWdJmtIcHdDdOAGS8cTvxw02o2vQNY2DrrsBq49j1eFqReNVf9015sUFF1uv3fb0Atf2BCRkj3EdNAz8UbxPduni9izYF9tYskC/79ZIIoZC8F4EG5kTHF+8U= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1680025042780380.6148485660973; Tue, 28 Mar 2023 10:37:22 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1phDEz-0008ET-2L; Tue, 28 Mar 2023 13:36:13 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1phDEw-0008AG-UB for qemu-devel@nongnu.org; Tue, 28 Mar 2023 13:36:10 -0400 Received: from mail-oa1-x36.google.com ([2001:4860:4864:20::36]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1phDEv-0005SX-4S for qemu-devel@nongnu.org; Tue, 28 Mar 2023 13:36:10 -0400 Received: by mail-oa1-x36.google.com with SMTP id 586e51a60fabf-17ac5ee3f9cso13485791fac.12 for ; Tue, 28 Mar 2023 10:36:08 -0700 (PDT) Received: from grind.. ([177.95.89.231]) by smtp.gmail.com with ESMTPSA id m2-20020a9d6442000000b0069f0a85fa36sm11635654otl.57.2023.03.28.10.36.05 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 28 Mar 2023 10:36:07 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1680024968; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=PJcYGrOPMg7QXNcY0p66T+ViExnDIcZu7iLjZ7e1LxM=; b=lhzROKocApK5moxF1SqV9GPrkktn7J1w1Yh5WOc9Yqyal8IEdTz1f2u9Of9+EaGvzK KQGBkCE6CicjCCQh+ewadKNeBFSGu/qkTG82dFLE/r7Vot9nN9cpL7zmP2mdLK3uVEAr 3mVItwyhDwB/OrDbYKZcs4cqmJ/p70Ml5oVTTHVSrzqwWASDPNaBpUzxWdp5d019hvPP n5R78/4OMCIn4VNRyKKikemMiO3gHiWLpnAnP+bY5BCgL1w8cQYcRx0qX3KV0Fhh4E+V 7tjL4kzp4JOz4VgWlfhrXMY2A8dXkVtGeQxAfEDv3+IjV4F5pSE4TeWN70eyhHnocWwP bVYg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1680024968; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=PJcYGrOPMg7QXNcY0p66T+ViExnDIcZu7iLjZ7e1LxM=; b=nFI9bWdhQ3KC0+VdwiatQKM/GqZk2fU9FJ09JNj+E1FUeLKvhrMYynaYaluzqx5LDj 0QqwwJYdjGhA8LGK4wxo2nLI0oc/XD4FM/VTKRO48gJYm6V4gXXLUOwKemQUc66DyVzK YKFAE2TD75dExRN2vyG7x4I5cmUpVx2xkpxjIZZfuID4yoIZ1vAtRq6mOrCL5S3V1Cax ncHW2OAGlkKgKG07/pQRH/OlvnWGXHmyXg62vxq4U2xIHsjRrX3tQ3tPgfrws5hn354I 9zD+FkWaag5JS4k9AuCnrrIW2sKl4Afi4SJlqOqRqo5sw2lqv19j3G437UjlLGIvvFGk pOKQ== X-Gm-Message-State: AAQBX9eMEwr7utKTthwWPLp7UOiNIbCHAmOb/TYD+kyxdrgmXSkkMpKc Rhfqf3pJZPe4oXZvWdw1n7atzvovjKIF6hivSuA= X-Google-Smtp-Source: AKy350ZqGPEkbVgidhLxsWISBF6t6bfhcGpmOCu7lkfDBXSrg+R6x6KoOPWP8+eVN77rz+Z4ZiEi9A== X-Received: by 2002:a05:6870:d62a:b0:17a:d3bb:2f64 with SMTP id a42-20020a056870d62a00b0017ad3bb2f64mr10976530oaq.56.1680024967809; Tue, 28 Mar 2023 10:36:07 -0700 (PDT) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, bmeng@tinylab.org, liweiwei@iscas.ac.cn, zhiwei_liu@linux.alibaba.com, palmer@rivosinc.com, Daniel Henrique Barboza Subject: [PATCH v5 5/9] target/riscv/cpu.c: add priv_spec validate/disable_exts helpers Date: Tue, 28 Mar 2023 14:35:39 -0300 Message-Id: <20230328173543.431342-6-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230328173543.431342-1-dbarboza@ventanamicro.com> References: <20230328173543.431342-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2001:4860:4864:20::36; envelope-from=dbarboza@ventanamicro.com; helo=mail-oa1-x36.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ventanamicro.com) X-ZM-MESSAGEID: 1680025043131100001 Content-Type: text/plain; charset="utf-8" We're doing env->priv_spec validation and assignment at the start of riscv_cpu_realize(), which is fine, but then we're doing a force disable on extensions that aren't compatible with the priv version. This second step is being done too early. The disabled extensions might be re-enabled again in riscv_cpu_validate_set_extensions() by accident. A better place to put this code is at the end of riscv_cpu_validate_set_extensions() after all the validations are completed. Add a new helper, riscv_cpu_disable_priv_spec_isa_exts(), to disable the extesions after the validation is done. While we're at it, create a riscv_cpu_validate_priv_spec() helper to host all env->priv_spec related validation to unclog riscv_cpu_realize a bit. Signed-off-by: Daniel Henrique Barboza Reviewed-by: LIU Zhiwei --- target/riscv/cpu.c | 91 ++++++++++++++++++++++++++++------------------ 1 file changed, 56 insertions(+), 35 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index e13528d932..a9042b190d 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -821,6 +821,52 @@ static void riscv_cpu_validate_v(CPURISCVState *env, R= ISCVCPUConfig *cfg, env->vext_ver =3D vext_version; } =20 +static void riscv_cpu_validate_priv_spec(RISCVCPU *cpu, Error **errp) +{ + CPURISCVState *env =3D &cpu->env; + int priv_version =3D -1; + + if (cpu->cfg.priv_spec) { + if (!g_strcmp0(cpu->cfg.priv_spec, "v1.12.0")) { + priv_version =3D PRIV_VERSION_1_12_0; + } else if (!g_strcmp0(cpu->cfg.priv_spec, "v1.11.0")) { + priv_version =3D PRIV_VERSION_1_11_0; + } else if (!g_strcmp0(cpu->cfg.priv_spec, "v1.10.0")) { + priv_version =3D PRIV_VERSION_1_10_0; + } else { + error_setg(errp, + "Unsupported privilege spec version '%s'", + cpu->cfg.priv_spec); + return; + } + + env->priv_ver =3D priv_version; + } +} + +static void riscv_cpu_disable_priv_spec_isa_exts(RISCVCPU *cpu) +{ + CPURISCVState *env =3D &cpu->env; + int i; + + /* Force disable extensions if priv spec version does not match */ + for (i =3D 0; i < ARRAY_SIZE(isa_edata_arr); i++) { + if (isa_ext_is_enabled(cpu, &isa_edata_arr[i]) && + (env->priv_ver < isa_edata_arr[i].min_version)) { + isa_ext_update_enabled(cpu, &isa_edata_arr[i], false); +#ifndef CONFIG_USER_ONLY + warn_report("disabling %s extension for hart 0x" TARGET_FMT_lx + " because privilege spec version does not match", + isa_edata_arr[i].name, env->mhartid); +#else + warn_report("disabling %s extension because " + "privilege spec version does not match", + isa_edata_arr[i].name); +#endif + } + } +} + /* * Check consistency between chosen extensions while setting * cpu->cfg accordingly. @@ -985,6 +1031,12 @@ static void riscv_cpu_validate_set_extensions(RISCVCP= U *cpu, Error **errp) cpu->cfg.ext_zksed =3D true; cpu->cfg.ext_zksh =3D true; } + + /* + * Disable isa extensions based on priv spec after we + * validated and set everything we need. + */ + riscv_cpu_disable_priv_spec_isa_exts(cpu); } =20 #ifndef CONFIG_USER_ONLY @@ -1084,7 +1136,6 @@ static void riscv_cpu_realize(DeviceState *dev, Error= **errp) CPURISCVState *env =3D &cpu->env; RISCVCPUClass *mcc =3D RISCV_CPU_GET_CLASS(dev); CPUClass *cc =3D CPU_CLASS(mcc); - int i, priv_version =3D -1; Error *local_err =3D NULL; =20 cpu_exec_realizefn(cs, &local_err); @@ -1093,23 +1144,10 @@ static void riscv_cpu_realize(DeviceState *dev, Err= or **errp) return; } =20 - if (cpu->cfg.priv_spec) { - if (!g_strcmp0(cpu->cfg.priv_spec, "v1.12.0")) { - priv_version =3D PRIV_VERSION_1_12_0; - } else if (!g_strcmp0(cpu->cfg.priv_spec, "v1.11.0")) { - priv_version =3D PRIV_VERSION_1_11_0; - } else if (!g_strcmp0(cpu->cfg.priv_spec, "v1.10.0")) { - priv_version =3D PRIV_VERSION_1_10_0; - } else { - error_setg(errp, - "Unsupported privilege spec version '%s'", - cpu->cfg.priv_spec); - return; - } - } - - if (priv_version >=3D PRIV_VERSION_1_10_0) { - env->priv_ver =3D priv_version; + riscv_cpu_validate_priv_spec(cpu, &local_err); + if (local_err !=3D NULL) { + error_propagate(errp, local_err); + return; } =20 riscv_cpu_validate_misa_priv(env, &local_err); @@ -1118,23 +1156,6 @@ static void riscv_cpu_realize(DeviceState *dev, Erro= r **errp) return; } =20 - /* Force disable extensions if priv spec version does not match */ - for (i =3D 0; i < ARRAY_SIZE(isa_edata_arr); i++) { - if (isa_ext_is_enabled(cpu, &isa_edata_arr[i]) && - (env->priv_ver < isa_edata_arr[i].min_version)) { - isa_ext_update_enabled(cpu, &isa_edata_arr[i], false); -#ifndef CONFIG_USER_ONLY - warn_report("disabling %s extension for hart 0x" TARGET_FMT_lx - " because privilege spec version does not match", - isa_edata_arr[i].name, env->mhartid); -#else - warn_report("disabling %s extension because " - "privilege spec version does not match", - isa_edata_arr[i].name); -#endif - } - } - if (cpu->cfg.epmp && !cpu->cfg.pmp) { /* * Enhanced PMP should only be available --=20 2.39.2 From nobody Wed May 8 22:12:36 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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([177.95.89.231]) by smtp.gmail.com with ESMTPSA id m2-20020a9d6442000000b0069f0a85fa36sm11635654otl.57.2023.03.28.10.36.08 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 28 Mar 2023 10:36:10 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1680024970; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=rUOwa3wbbfPfghjgjPGJgBy5tq7nZVthZ1BaaaPp4qs=; b=cXDHq3H3OD+VAcSM29Fqamh7NkMbqcAWuujIkQkWbHYT4vb9Pc1miWJZA4gtmDwRpw qHIlnuwNZAcaanbDNK0llMi2SGVuhtsEJAJJ33we8M5DqJzD3NirYBJHWC+HQd9TxC5w kJhYU95nUqPtdwyDm065Jqh38NlFVClSbDsjgwPJTfv3gLpdyS2mIYN5NHhjb9g4tSWh 2Ok9dcXQ7GMQpzzetkCdJQgfkflltuG64rJ/Civs1Oj3FG2JF1zQMma4vEfey9//fgLs IDq1auz64FB1Ki6zbE4UIZRtxfrJEQBon2d1rUr2PCdzxmI+rzptN+eWNgfU40zH+XK4 vBng== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1680024970; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=rUOwa3wbbfPfghjgjPGJgBy5tq7nZVthZ1BaaaPp4qs=; b=zUkeaiZtwBI3/PUYYDx4JPvXAQaRG0LU05G8Jky8yr73CilLsSJclEoPcgPIdI7Ij9 /uggN8s0+Xo/MEUBZ5aDneTIW5Z94fyQ1Set2WPBizZ3SO5pc3L6JNs2HFElhVfYLHUy EmDeEyeFMTgZAhIsEV9psJCu9ijfVz7Nq03woc7yInZ14slHT2j+WpOEgBxvnzEfkaiE ysGk7/yaYfegvdQytx6VcS34MbWMMT+HKvYPslZoWHUlLJlmaG0TbRo1HYHKzWd+3fK1 c99dqckAdefjclEw1qfPgMxzFR+R+dbi00yo7b06Zxar4uDnqsxwtor/zcYchGDpH9Bj IuYQ== X-Gm-Message-State: AAQBX9e9hvVVxjqIOZqh6UBaCfh3gIhVjk01M0UZBqTdAHY+iuEgFjcB 02h8Q0jqpH8vL7MajpKwro+Aqh1qXyHlPkYzOhU= X-Google-Smtp-Source: AK7set+uDUAHKa6j1wDxm8tRC9pSObQkJz+tEJMEl7owZWDg6dXvbPCZVvqxwHYbO7Za10Z9z+YAOQ== X-Received: by 2002:a05:6870:3846:b0:17a:cfe4:3782 with SMTP id z6-20020a056870384600b0017acfe43782mr10571377oal.11.1680024970687; Tue, 28 Mar 2023 10:36:10 -0700 (PDT) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, bmeng@tinylab.org, liweiwei@iscas.ac.cn, zhiwei_liu@linux.alibaba.com, palmer@rivosinc.com, Daniel Henrique Barboza Subject: [PATCH v5 6/9] target/riscv/cpu.c: add riscv_cpu_validate_misa_mxl() Date: Tue, 28 Mar 2023 14:35:40 -0300 Message-Id: <20230328173543.431342-7-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230328173543.431342-1-dbarboza@ventanamicro.com> References: <20230328173543.431342-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2001:4860:4864:20::36; envelope-from=dbarboza@ventanamicro.com; helo=mail-oa1-x36.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ventanamicro.com) X-ZM-MESSAGEID: 1680025051505100003 Content-Type: text/plain; charset="utf-8" Let's remove more code that is open coded in riscv_cpu_realize() and put it into a helper. Let's also add an error message instead of just asserting out if env->misa_mxl_max !=3D env->misa_mlx. Signed-off-by: Daniel Henrique Barboza Reviewed-by: LIU Zhiwei --- target/riscv/cpu.c | 50 ++++++++++++++++++++++++++++++---------------- 1 file changed, 33 insertions(+), 17 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index a9042b190d..05878846f9 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -867,6 +867,33 @@ static void riscv_cpu_disable_priv_spec_isa_exts(RISCV= CPU *cpu) } } =20 +static void riscv_cpu_validate_misa_mxl(RISCVCPU *cpu, Error **errp) +{ + RISCVCPUClass *mcc =3D RISCV_CPU_GET_CLASS(cpu); + CPUClass *cc =3D CPU_CLASS(mcc); + CPURISCVState *env =3D &cpu->env; + + /* Validate that MISA_MXL is set properly. */ + switch (env->misa_mxl_max) { +#ifdef TARGET_RISCV64 + case MXL_RV64: + case MXL_RV128: + cc->gdb_core_xml_file =3D "riscv-64bit-cpu.xml"; + break; +#endif + case MXL_RV32: + cc->gdb_core_xml_file =3D "riscv-32bit-cpu.xml"; + break; + default: + g_assert_not_reached(); + } + + if (env->misa_mxl_max !=3D env->misa_mxl) { + error_setg(errp, "misa_mxl_max must be equal to misa_mxl"); + return; + } +} + /* * Check consistency between chosen extensions while setting * cpu->cfg accordingly. @@ -1135,7 +1162,6 @@ static void riscv_cpu_realize(DeviceState *dev, Error= **errp) RISCVCPU *cpu =3D RISCV_CPU(dev); CPURISCVState *env =3D &cpu->env; RISCVCPUClass *mcc =3D RISCV_CPU_GET_CLASS(dev); - CPUClass *cc =3D CPU_CLASS(mcc); Error *local_err =3D NULL; =20 cpu_exec_realizefn(cs, &local_err); @@ -1144,6 +1170,12 @@ static void riscv_cpu_realize(DeviceState *dev, Erro= r **errp) return; } =20 + riscv_cpu_validate_misa_mxl(cpu, &local_err); + if (local_err !=3D NULL) { + error_propagate(errp, local_err); + return; + } + riscv_cpu_validate_priv_spec(cpu, &local_err); if (local_err !=3D NULL) { error_propagate(errp, local_err); @@ -1172,22 +1204,6 @@ static void riscv_cpu_realize(DeviceState *dev, Erro= r **errp) } #endif /* CONFIG_USER_ONLY */ =20 - /* Validate that MISA_MXL is set properly. */ - switch (env->misa_mxl_max) { -#ifdef TARGET_RISCV64 - case MXL_RV64: - case MXL_RV128: - cc->gdb_core_xml_file =3D "riscv-64bit-cpu.xml"; - break; -#endif - case MXL_RV32: - cc->gdb_core_xml_file =3D "riscv-32bit-cpu.xml"; - break; - default: - g_assert_not_reached(); - } - assert(env->misa_mxl_max =3D=3D env->misa_mxl); - riscv_cpu_validate_set_extensions(cpu, &local_err); if (local_err !=3D NULL) { error_propagate(errp, local_err); --=20 2.39.2 From nobody Wed May 8 22:12:36 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1680025009; cv=none; d=zohomail.com; s=zohoarc; b=GSWtazzlaXT+KvwrCuSWiNRwjfUciuU6Fx5K3e/8SjWVFl7H8/gdjR7SfvQ940azziLT7Uv7G7NKFV8bP5zRnGRk3U42o/uPn714HG5J/Msw6/igmZLWh72cZtHQI9UC6toqqRuDcvUuAiL/Xx/UC8sFrq1TLHccKphDuXfd9gg= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1680025009; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=0NoB6geIo+deBuKwjgIqMS5WPUG4xrppd24DiTg9tyg=; b=D1dPhUYHVbBHxfD2qg7B5Uwvtml48Xy4og1rbsSbgGI4xeCC7SyEe9XijnsnZJO9u8d213/hLoohN7Z3PanHek7vCKMtcaIHhLAQjuXk97VHyxmahD17sPqoQ+Nxj621Rrc+vpHYoSesG+lC62uHXGleuwqc6XNULH2A3rpC60A= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1680025009001649.2309282164243; Tue, 28 Mar 2023 10:36:49 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1phDF5-0008QF-Rc; Tue, 28 Mar 2023 13:36:19 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1phDF2-0008Ke-5C for qemu-devel@nongnu.org; Tue, 28 Mar 2023 13:36:16 -0400 Received: from mail-oa1-x2f.google.com ([2001:4860:4864:20::2f]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1phDF0-0005SF-JJ for qemu-devel@nongnu.org; Tue, 28 Mar 2023 13:36:15 -0400 Received: by mail-oa1-x2f.google.com with SMTP id 586e51a60fabf-17aceccdcf6so13506079fac.9 for ; Tue, 28 Mar 2023 10:36:14 -0700 (PDT) Received: from grind.. ([177.95.89.231]) by smtp.gmail.com with ESMTPSA id m2-20020a9d6442000000b0069f0a85fa36sm11635654otl.57.2023.03.28.10.36.11 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 28 Mar 2023 10:36:13 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1680024973; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=0NoB6geIo+deBuKwjgIqMS5WPUG4xrppd24DiTg9tyg=; b=G+WgUD1qOa9VemkvWmpWxvOvvhao3i+xEUmeGTZcIpKDEtG9SH4hOdwX5e27hysVht 962aThRNNcF0rnivUMdCBVhyXW6e131bgoojIigYCinEWXHfg1xorMt5T/StzAO80JBZ Y66pUJK1wq1/JoBNalVNvevKQlrW6ndfOUG42dJXbzHLTXJfOQ/qMeyxxiqP9IBeD7uI gblwrmmPJEQZ4eNArSZ5CCd1o8/Ywwhscge/G5C8sKbAiNW9PjHaE49JztIngCWDqaWm GB9KRKQkuAB5VoZ4fXfB0Ta0avyHEYPfN19wv9AwvZ3vt7t5rG7BBJauR/azwAjcfcmW SeHg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1680024973; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=0NoB6geIo+deBuKwjgIqMS5WPUG4xrppd24DiTg9tyg=; b=FAQKV1RKWX/Oz0qMvnbjVkkUmwojHx6L90YNQw40BwPT3PK89ZQH+wVfCC4eOMn2rm 88qFOKhunJMLYsOSBIs9N1VY51SxQCy3aohJqyVyAmbIZZoYLEmPP5Xi27ZEscNDdJgB xVZ9+3qx0RN9ha60dYwcoryLfiKf7dLIyAs5jQ/JvDmODvUypi2ipCivUssOwXNnNjiW RM57tDTHEMsJ+hWlf0v9t3dEEDggdEJcFWH2CJ64J559+9SY44BNWNp8iJVbvKpDMsoG 7/4kVffkmKjsuKj0EbJGgHeZKif8HwTGDn4aQYI2XXyhr1Ys86mLkAC0XoPDE8V7zEdG jVQQ== X-Gm-Message-State: AAQBX9e2RW7nMQOiATcVPjXzQYsgzElxvQ1pdfdtqz3AzwsWwmO83PK2 3XKf/P7AvAGge4FQIlR4YrQQXSpKhIv8wC+qkEo= X-Google-Smtp-Source: AKy350Yv0fVYYFaHeNNPOMbxyE6+txxu+TR+y80r6PKZj/NVUPHPTWhtgwHoU0zednXS7n9i6wloLA== X-Received: by 2002:a05:6870:ea84:b0:177:be5e:4532 with SMTP id s4-20020a056870ea8400b00177be5e4532mr12052926oap.10.1680024973658; Tue, 28 Mar 2023 10:36:13 -0700 (PDT) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, bmeng@tinylab.org, liweiwei@iscas.ac.cn, zhiwei_liu@linux.alibaba.com, palmer@rivosinc.com, Daniel Henrique Barboza Subject: [PATCH v5 7/9] target/riscv/cpu.c: validate extensions before riscv_timer_init() Date: Tue, 28 Mar 2023 14:35:41 -0300 Message-Id: <20230328173543.431342-8-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230328173543.431342-1-dbarboza@ventanamicro.com> References: <20230328173543.431342-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2001:4860:4864:20::2f; envelope-from=dbarboza@ventanamicro.com; helo=mail-oa1-x2f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ventanamicro.com) X-ZM-MESSAGEID: 1680025010632100003 Content-Type: text/plain; charset="utf-8" There is no need to init timers if we're not even sure that our extensions are valid. Execute riscv_cpu_validate_set_extensions() before riscv_timer_init(). Signed-off-by: Daniel Henrique Barboza Reviewed-by: LIU Zhiwei --- target/riscv/cpu.c | 11 ++++------- 1 file changed, 4 insertions(+), 7 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 05878846f9..1a095ce8e3 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -1197,13 +1197,6 @@ static void riscv_cpu_realize(DeviceState *dev, Erro= r **errp) return; } =20 - -#ifndef CONFIG_USER_ONLY - if (cpu->cfg.ext_sstc) { - riscv_timer_init(cpu); - } -#endif /* CONFIG_USER_ONLY */ - riscv_cpu_validate_set_extensions(cpu, &local_err); if (local_err !=3D NULL) { error_propagate(errp, local_err); @@ -1211,6 +1204,10 @@ static void riscv_cpu_realize(DeviceState *dev, Erro= r **errp) } =20 #ifndef CONFIG_USER_ONLY + if (cpu->cfg.ext_sstc) { + riscv_timer_init(cpu); + } + if (cpu->cfg.pmu_num) { if (!riscv_pmu_init(cpu, cpu->cfg.pmu_num) && cpu->cfg.ext_sscofpm= f) { cpu->pmu_timer =3D timer_new_ns(QEMU_CLOCK_VIRTUAL, --=20 2.39.2 From nobody Wed May 8 22:12:36 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1680025070; cv=none; d=zohomail.com; s=zohoarc; b=e25QQev2ui1SWqjdrZrAPqAyxZqsqpxT6UuizcZeG2m2B4bBEbI+R4BZViwGV0IIqcjS7+rVer+jNGg317KFf8VTL6BTziYC9EMf4zu6zNkzm1zdIPCt5czdcu/rQC0RlCT3ODHaDUEKwFXXpr29J20LjrvYqiF0ESo0x6NCasw= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1680025070; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=DDaQ2R9j+YZadEd8RsWddkKQl6CU1ROQqG4vvLAYOl8=; b=QfmkRcR+e/pG2Zg8tAPrspTOWsv6AunlPGx6oyYPeWA6/4dfw051uazsw5Tcm+X7l/K1fm0q0PEcyNcR/1mf8vuK9zgozNSO+mQmc0G0uxVsgydz5QlwVuBX29hkaKfonI9Qa1YPZuCafg3k26ntgoG9LVVz2Ma+zCdSTyMroR4= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1680025070844392.6159249693909; Tue, 28 Mar 2023 10:37:50 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1phDFA-0008RY-Aa; Tue, 28 Mar 2023 13:36:25 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1phDF6-0008Qh-74 for qemu-devel@nongnu.org; Tue, 28 Mar 2023 13:36:20 -0400 Received: from mail-oa1-x2e.google.com ([2001:4860:4864:20::2e]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1phDF4-0005Yp-3y for qemu-devel@nongnu.org; Tue, 28 Mar 2023 13:36:19 -0400 Received: by mail-oa1-x2e.google.com with SMTP id 586e51a60fabf-17683b570b8so13473815fac.13 for ; Tue, 28 Mar 2023 10:36:17 -0700 (PDT) Received: from grind.. ([177.95.89.231]) by smtp.gmail.com with ESMTPSA id m2-20020a9d6442000000b0069f0a85fa36sm11635654otl.57.2023.03.28.10.36.14 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 28 Mar 2023 10:36:16 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1680024976; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=DDaQ2R9j+YZadEd8RsWddkKQl6CU1ROQqG4vvLAYOl8=; b=nY8NuQSAJPkSkOD4Kj82NZzHCGFutaLLNDXT+kmEkU9FDB9Pf/8BaKheGR+C3umwGD ZnC7tkHKuSyGR4LaeiGrv/wyHqcqOA8P0JEHmXzAfjgxJ+yAm/yXZsISutbSj2vs0R7K Urm3BMIwkgQevR8MAYJikhrFIN1vmIKVJz4GZau86jFpGF9Jq8AK7rckwxYIxw418cr2 X3gw2BJbRWfGj7+FV29pDcUu4TyCqnCA2/vEeh+TrxNi1QuEbqjorQJ1Q63mi8yT/D9W 6tmMxd9REJoan3AcIweRBElM4jk9eWAdyfFjfyWflfN+SsKfBnm5O+B/1YzPQt5TawVM 0qnQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1680024976; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=DDaQ2R9j+YZadEd8RsWddkKQl6CU1ROQqG4vvLAYOl8=; b=DAmXypYc6AO3mHmT5esHe+hEYZzzl6iCXPpFy7JzE8iadU1Jy4ERNUYVcJTJHCxpeb F0smhJxnUtrSNg/kRiFr2mEGrRAKgppfu2mlUqHI9d8qj76BahvnweN2MSiT/iBcq9Ji tt6BIkbD/xLLextAMNW26WYZ/lE3blBwADl1B6TiTDR3+0mKCM633dXFIjF7k2HSdsCm uqswIc7LxdWPvH15B03kXNUwgFmzVZcGSgl2F6JkhZBI6T317EOr3PgLa2Gmx40TMNaG kvL1k8k5d3c943UGchZQaxAVqm8quKZnKk70f/save1Po9O0zetxthiy+3PJsQNvnaYZ UtOg== X-Gm-Message-State: AAQBX9fbUtceYypyc2O5EW+Kvv/UaQLaGEZxIbetpWLNUc3Hb/DJr6Sr O0xfO5aBkxDX95z9z2H8t78m/g4YXN3pQbvVV0k= X-Google-Smtp-Source: AKy350aoiOwedHRdXilk4pYKK26ZfznsfPOSfSECC4bE17YIP2r6Q+uxhn4tOAs/gCoIJE5QC7Xn0A== X-Received: by 2002:a05:6870:f10d:b0:17f:769c:62a5 with SMTP id k13-20020a056870f10d00b0017f769c62a5mr3668331oac.49.1680024976639; Tue, 28 Mar 2023 10:36:16 -0700 (PDT) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, bmeng@tinylab.org, liweiwei@iscas.ac.cn, zhiwei_liu@linux.alibaba.com, palmer@rivosinc.com, Daniel Henrique Barboza Subject: [PATCH v5 8/9] target/riscv/cpu.c: remove cfg setup from riscv_cpu_init() Date: Tue, 28 Mar 2023 14:35:42 -0300 Message-Id: <20230328173543.431342-9-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230328173543.431342-1-dbarboza@ventanamicro.com> References: <20230328173543.431342-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2001:4860:4864:20::2e; envelope-from=dbarboza@ventanamicro.com; helo=mail-oa1-x2e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ventanamicro.com) X-ZM-MESSAGEID: 1680025071506100003 Content-Type: text/plain; charset="utf-8" We have 4 config settings being done in riscv_cpu_init(): ext_ifencei, ext_icsr, mmu and pmp. This is also the constructor of the "riscv-cpu" device, which happens to be the parent device of every RISC-V cpu. The result is that these 4 configs are being set every time, and every other CPU should always account for them. CPUs such as sifive_e need to disable settings that aren't enabled simply because the parent class happens to be enabling it. Moving all configurations from the parent class to each CPU will centralize the config of each CPU into its own init(), which is clearer than having to account to whatever happens to be set in the parent device. These settings are also being set in register_cpu_props() when no 'misa_ext' is set, so for these CPUs we don't need changes. Named CPUs will receive all cfgs that the parent were setting into their init(). Signed-off-by: Daniel Henrique Barboza Reviewed-by: LIU Zhiwei --- target/riscv/cpu.c | 60 ++++++++++++++++++++++++++++++++++++---------- 1 file changed, 48 insertions(+), 12 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 1a095ce8e3..cd924029d4 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -326,7 +326,8 @@ static void set_satp_mode_default_map(RISCVCPU *cpu) =20 static void riscv_any_cpu_init(Object *obj) { - CPURISCVState *env =3D &RISCV_CPU(obj)->env; + RISCVCPU *cpu =3D RISCV_CPU(obj); + CPURISCVState *env =3D &cpu->env; #if defined(TARGET_RISCV32) set_misa(env, MXL_RV32, RVI | RVM | RVA | RVF | RVD | RVC | RVU); #elif defined(TARGET_RISCV64) @@ -340,6 +341,12 @@ static void riscv_any_cpu_init(Object *obj) #endif =20 env->priv_ver =3D PRIV_VERSION_LATEST; + + /* inherited from parent obj via riscv_cpu_init() */ + cpu->cfg.ext_ifencei =3D true; + cpu->cfg.ext_icsr =3D true; + cpu->cfg.mmu =3D true; + cpu->cfg.pmp =3D true; } =20 #if defined(TARGET_RISCV64) @@ -358,12 +365,19 @@ static void rv64_base_cpu_init(Object *obj) =20 static void rv64_sifive_u_cpu_init(Object *obj) { - CPURISCVState *env =3D &RISCV_CPU(obj)->env; + RISCVCPU *cpu =3D RISCV_CPU(obj); + CPURISCVState *env =3D &cpu->env; set_misa(env, MXL_RV64, RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU); env->priv_ver =3D PRIV_VERSION_1_10_0; #ifndef CONFIG_USER_ONLY set_satp_mode_max_supported(RISCV_CPU(obj), VM_1_10_SV39); #endif + + /* inherited from parent obj via riscv_cpu_init() */ + cpu->cfg.ext_ifencei =3D true; + cpu->cfg.ext_icsr =3D true; + cpu->cfg.mmu =3D true; + cpu->cfg.pmp =3D true; } =20 static void rv64_sifive_e_cpu_init(Object *obj) @@ -373,10 +387,14 @@ static void rv64_sifive_e_cpu_init(Object *obj) =20 set_misa(env, MXL_RV64, RVI | RVM | RVA | RVC | RVU); env->priv_ver =3D PRIV_VERSION_1_10_0; - cpu->cfg.mmu =3D false; #ifndef CONFIG_USER_ONLY set_satp_mode_max_supported(cpu, VM_1_10_MBARE); #endif + + /* inherited from parent obj via riscv_cpu_init() */ + cpu->cfg.ext_ifencei =3D true; + cpu->cfg.ext_icsr =3D true; + cpu->cfg.pmp =3D true; } =20 static void rv64_thead_c906_cpu_init(Object *obj) @@ -404,6 +422,10 @@ static void rv64_thead_c906_cpu_init(Object *obj) #ifndef CONFIG_USER_ONLY set_satp_mode_max_supported(cpu, VM_1_10_SV39); #endif + + /* inherited from parent obj via riscv_cpu_init() */ + cpu->cfg.ext_ifencei =3D true; + cpu->cfg.pmp =3D true; } =20 static void rv128_base_cpu_init(Object *obj) @@ -440,12 +462,19 @@ static void rv32_base_cpu_init(Object *obj) =20 static void rv32_sifive_u_cpu_init(Object *obj) { - CPURISCVState *env =3D &RISCV_CPU(obj)->env; + RISCVCPU *cpu =3D RISCV_CPU(obj); + CPURISCVState *env =3D &cpu->env; set_misa(env, MXL_RV32, RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU); env->priv_ver =3D PRIV_VERSION_1_10_0; #ifndef CONFIG_USER_ONLY set_satp_mode_max_supported(RISCV_CPU(obj), VM_1_10_SV32); #endif + + /* inherited from parent obj via riscv_cpu_init() */ + cpu->cfg.ext_ifencei =3D true; + cpu->cfg.ext_icsr =3D true; + cpu->cfg.mmu =3D true; + cpu->cfg.pmp =3D true; } =20 static void rv32_sifive_e_cpu_init(Object *obj) @@ -455,10 +484,14 @@ static void rv32_sifive_e_cpu_init(Object *obj) =20 set_misa(env, MXL_RV32, RVI | RVM | RVA | RVC | RVU); env->priv_ver =3D PRIV_VERSION_1_10_0; - cpu->cfg.mmu =3D false; #ifndef CONFIG_USER_ONLY set_satp_mode_max_supported(cpu, VM_1_10_MBARE); #endif + + /* inherited from parent obj via riscv_cpu_init() */ + cpu->cfg.ext_ifencei =3D true; + cpu->cfg.ext_icsr =3D true; + cpu->cfg.pmp =3D true; } =20 static void rv32_ibex_cpu_init(Object *obj) @@ -468,11 +501,15 @@ static void rv32_ibex_cpu_init(Object *obj) =20 set_misa(env, MXL_RV32, RVI | RVM | RVC | RVU); env->priv_ver =3D PRIV_VERSION_1_11_0; - cpu->cfg.mmu =3D false; #ifndef CONFIG_USER_ONLY set_satp_mode_max_supported(cpu, VM_1_10_MBARE); #endif cpu->cfg.epmp =3D true; + + /* inherited from parent obj via riscv_cpu_init() */ + cpu->cfg.ext_ifencei =3D true; + cpu->cfg.ext_icsr =3D true; + cpu->cfg.pmp =3D true; } =20 static void rv32_imafcu_nommu_cpu_init(Object *obj) @@ -482,10 +519,14 @@ static void rv32_imafcu_nommu_cpu_init(Object *obj) =20 set_misa(env, MXL_RV32, RVI | RVM | RVA | RVF | RVC | RVU); env->priv_ver =3D PRIV_VERSION_1_10_0; - cpu->cfg.mmu =3D false; #ifndef CONFIG_USER_ONLY set_satp_mode_max_supported(cpu, VM_1_10_MBARE); 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([177.95.89.231]) by smtp.gmail.com with ESMTPSA id m2-20020a9d6442000000b0069f0a85fa36sm11635654otl.57.2023.03.28.10.36.16 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 28 Mar 2023 10:36:19 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1680024981; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=IB6MPIytqxPwEACYywxPrY0MXu0k/dW8FvoTWQSwXRo=; b=LN6ogcDA0OGCey2tSwbevc0KhoNJzDKPSmpXSSlJ+6C0yP76yxX2La7Ky+cgqWDM7m Y2uqcmJE50r2M2oidJjzDW/a2s5mUa5UguEI1NtumJQb6XmhBiR8TLC+KXThlLFTNxJ2 OxxCSRI/NG7eE11C6qIPWrKZ6IhR7fky8V4VAzPk1gyg0OceJZl20m5783lzc5HiJK4l zdjzY38T19i0iuTRHPKvL+AgoYCwyL5449oz9zTT9fn5EIA3wKyrE8SXQ4kYN2AxCPkv AC2XfMK60UApB9sa8gJpt9FuxMo8mTSgkFv63Mn/BgFJ4LvG7jnAVnnAOaIEZbUwXWcB uHow== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1680024981; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=IB6MPIytqxPwEACYywxPrY0MXu0k/dW8FvoTWQSwXRo=; b=d8GuhnAPLcj8E+fTCNiIqYHHevnUAMaD2cwpHKj0nOKHEsVZHdYogIqSSzGOaj+cSE PqwMLcZJggM52hgQnh38eoAe+a2BaTyykWS20sf57+l2KDkEEttdy4zmy5wrnFNAKz/B b+C2prwSgLtIrVENcltVzLsx9ldCcFq0PU7sEQ3c8j5bE1b77N5NEM9uzC+9G1WgLhwH oAkUhfiUs14gbXGRRzd+UO12gUeY26DbYxorAulyWGvPHtAzKLMMJqr4XWoEqwrPMn4y JSUrsob0pDjSev7Dh3Y8gMsrIKIZQqUPhfUUUxxaDRtyJJPVqW+bfVqh//NEXPagC3Nn xNqQ== X-Gm-Message-State: AO0yUKULqFDAta15R+99p/o5qn6Ufj187TNFwkF5WjGckKiqFs1XkTw7 7fNAz3yHo7FFoMM7ImDNDUerQOxRMHs3AGhtHTo= X-Google-Smtp-Source: AKy350bE8dGRR3oWBJX+l2ZOI+L2mfS7JoCduWB9Sk8ElnJvUoA9B07U7WrdOmLZtULozPFJstMraQ== X-Received: by 2002:a05:6870:3911:b0:17a:da6b:ad91 with SMTP id b17-20020a056870391100b0017ada6bad91mr10193787oap.2.1680024979772; Tue, 28 Mar 2023 10:36:19 -0700 (PDT) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, bmeng@tinylab.org, liweiwei@iscas.ac.cn, zhiwei_liu@linux.alibaba.com, palmer@rivosinc.com, Daniel Henrique Barboza Subject: [PATCH v5 9/9] target/riscv: rework write_misa() Date: Tue, 28 Mar 2023 14:35:43 -0300 Message-Id: <20230328173543.431342-10-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230328173543.431342-1-dbarboza@ventanamicro.com> References: <20230328173543.431342-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2001:4860:4864:20::2e; envelope-from=dbarboza@ventanamicro.com; helo=mail-oa1-x2e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ventanamicro.com) X-ZM-MESSAGEID: 1680025085561100001 Content-Type: text/plain; charset="utf-8" write_misa() must use as much common logic as possible. We want to open code just the bits that are exclusive to the CSR write operation and TCG internals. Our validation is done with riscv_cpu_validate_set_extensions(), but we need a small tweak first. When enabling RVG we're doing: env->misa_ext |=3D RVI | RVM | RVA | RVF | RVD; env->misa_ext_mask =3D env->misa_ext; This works fine for realize() time but this can potentially overwrite env->misa_ext_mask if we reutilize the function for write_misa(). Instead of doing misa_ext_mask =3D misa_ext, sum up the RVG extensions in misa_ext_mask as well. This won't change realize() time behavior (misa_ext_mask is still =3D=3D misa_ext) and will ensure that write_misa() won't change misa_ext_mask by accident. After that, rewrite write_misa() to work as follows: - mask the write using misa_ext_mask to avoid enabling unsupported extensions; - suppress RVC if the next insn isn't aligned; - disable RVG if any of RVG dependencies are being disabled by the user; - assign env->misa_ext and run riscv_cpu_validate_set_extensions(). On error, rollback to the previous values of misa_ext and misa_ext_mask; - on success, check if there's a chance that misa_ext_mask was overwritten during the process and restore it; - handle RVF and MSTATUS_FS and continue as usual. Let's keep write_misa() as experimental for now until this logic gains enough mileage. Signed-off-by: Daniel Henrique Barboza Reviewed-by: Weiwei Li --- target/riscv/cpu.c | 4 ++-- target/riscv/cpu.h | 1 + target/riscv/csr.c | 47 ++++++++++++++++++++-------------------------- 3 files changed, 23 insertions(+), 29 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index cd924029d4..d722674791 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -939,7 +939,7 @@ static void riscv_cpu_validate_misa_mxl(RISCVCPU *cpu, = Error **errp) * Check consistency between chosen extensions while setting * cpu->cfg accordingly. */ -static void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp) +void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp) { CPURISCVState *env =3D &cpu->env; Error *local_err =3D NULL; @@ -955,7 +955,7 @@ static void riscv_cpu_validate_set_extensions(RISCVCPU = *cpu, Error **errp) cpu->cfg.ext_ifencei =3D true; =20 env->misa_ext |=3D RVI | RVM | RVA | RVF | RVD; - env->misa_ext_mask =3D env->misa_ext; + env->misa_ext_mask |=3D RVI | RVM | RVA | RVF | RVD; } =20 if (riscv_has_ext(env, RVI) && riscv_has_ext(env, RVE)) { diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 03b5cc2cf4..13f6566962 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -575,6 +575,7 @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, in= t size, bool probe, uintptr_t retaddr); char *riscv_isa_string(RISCVCPU *cpu); void riscv_cpu_list(void); +void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp); =20 #define cpu_list riscv_cpu_list #define cpu_mmu_index riscv_cpu_mmu_index diff --git a/target/riscv/csr.c b/target/riscv/csr.c index d522efc0b6..37fd619b17 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -1343,39 +1343,18 @@ static RISCVException read_misa(CPURISCVState *env,= int csrno, static RISCVException write_misa(CPURISCVState *env, int csrno, target_ulong val) { + RISCVCPU *cpu =3D env_archcpu(env); + uint32_t orig_misa_ext =3D env->misa_ext; + Error *local_err =3D NULL; + if (!riscv_cpu_cfg(env)->misa_w) { /* drop write to misa */ return RISCV_EXCP_NONE; } =20 - /* 'I' or 'E' must be present */ - if (!(val & (RVI | RVE))) { - /* It is not, drop write to misa */ - return RISCV_EXCP_NONE; - } - - /* 'E' excludes all other extensions */ - if (val & RVE) { - /* - * when we support 'E' we can do "val =3D RVE;" however - * for now we just drop writes if 'E' is present. - */ - return RISCV_EXCP_NONE; - } - - /* - * misa.MXL writes are not supported by QEMU. - * Drop writes to those bits. - */ - /* Mask extensions that are not supported by this hart */ val &=3D env->misa_ext_mask; =20 - /* 'D' depends on 'F', so clear 'D' if 'F' is not present */ - if ((val & RVD) && !(val & RVF)) { - val &=3D ~RVD; - } - /* * Suppress 'C' if next instruction is not aligned * TODO: this should check next_pc @@ -1384,18 +1363,32 @@ static RISCVException write_misa(CPURISCVState *env= , int csrno, val &=3D ~RVC; } =20 + /* Disable RVG if any of its dependencies are disabled */ + if (!(val & RVI && val & RVM && val & RVA && + val & RVF && val & RVD)) { + val &=3D ~RVG; + } + /* If nothing changed, do nothing. */ if (val =3D=3D env->misa_ext) { return RISCV_EXCP_NONE; } =20 - if (!(val & RVF)) { + env->misa_ext =3D val; + riscv_cpu_validate_set_extensions(cpu, &local_err); + if (local_err !=3D NULL) { + /* Rollback on validation error */ + env->misa_ext =3D orig_misa_ext; + + return RISCV_EXCP_NONE; + } + + if (!(env->misa_ext & RVF)) { env->mstatus &=3D ~MSTATUS_FS; } =20 /* flush translation cache */ tb_flush(env_cpu(env)); - env->misa_ext =3D val; env->xl =3D riscv_cpu_mxl(env); return RISCV_EXCP_NONE; } --=20 2.39.2