Hi,

This is a work I was intending to do later but the reviews in the
"[PATCH for-8.1 v4 00/25] target/riscv: rework CPU extensions
validation" series [1] really made me realize it's better to do it now.

We store CPU extension state in two places: cpu->cfg.ext_N flags and
env->misa_ext. This was done a while ago when the cpu->cfg object was
introduced, where cpu->cfg.ext_N flags are exposed to users to allow
them to enable/disable extensions.

This forces the code to always have to mirror env->misa_ext and
cpu->cfg.ext_N changes. The code in target/riscv/cpu.c uses the cfg
flags, and the rest of the code uses env->misa_ext. This worked for us
so far, but when implemeting write_misa() this really started to get in
the way - we have a handful of patches and code juggling happening there
just to deal with cpu->cfg and env->misa_ext mirroring.

In the end, what we need is to provide users with a way to set CPU MISA
extensions.  It doesn't have to be in cpu->cfg.ext_N, and in this series
we're going to address that. In patch 3 we have the machinery used to
expose the same MISA user flags we have today, but updating directly in
env->misa_ext*. Patches 4 and onward will then eliminate each
cpu->cfg.ext_N flag for each MISA bit we have, until we eliminate all of
cpu->cfg.ext_N flags from the code.

It is worth mentioning that patch 3 had a strong inspiration from
hw/ppc/spapr_caps.c, the code that handles PowerPC64 capabilities for
the pSeries machine. 

After this series, we'll have a more pleasant time dealing with user
input in the extensions code. I'll postpone the v5 of [1] until we get
this in a good shape, since this cleanup will really go a long way in
the centralization work.

The only behavioral change made is in patch 2, where we're erroring out
in the RVH priv spec mismatch instead of silently disabling. User API is
still the same, default values of each extension is still the same.


[1] https://lists.gnu.org/archive/html/qemu-devel/2023-03/msg05785.html


Daniel Henrique Barboza (19):
  target/riscv: sync env->misa_ext* with cpu->cfg in realize()
  target/riscv: remove MISA properties from isa_edata_arr[]
  target/riscv: introduce riscv_cpu_add_misa_properties()
  target/riscv: remove cpu->cfg.ext_a
  target/riscv: remove cpu->cfg.ext_c
  target/riscv: remove cpu->cfg.ext_d
  target/riscv: remove cpu->cfg.ext_f
  target/riscv: remove cpu->cfg.ext_i
  target/riscv: remove cpu->cfg.ext_e
  target/riscv: remove cpu->cfg.ext_m
  target/riscv: remove cpu->cfg.ext_s
  target/riscv: remove cpu->cfg.ext_u
  target/riscv: remove cpu->cfg.ext_h
  target/riscv: remove cpu->cfg.ext_j
  target/riscv: remove cpu->cfg.ext_v
  target/riscv: remove riscv_cpu_sync_misa_cfg()
  target/riscv: remove cfg.ext_g setup from rv64_thead_c906_cpu_init()
  target/riscv: add RVG and remove cpu->cfg.ext_g
  target/riscv/cpu.c: redesign register_cpu_props()

 target/riscv/cpu.c | 268 ++++++++++++++++++++++++---------------------
 target/riscv/cpu.h |  19 +---
 2 files changed, 144 insertions(+), 143 deletions(-)

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2.39.2