From nobody Thu May 2 00:48:52 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1679921235; cv=none; d=zohomail.com; s=zohoarc; b=DhaPcGSVj0Q/tW/Y7jJjd2hjpM2iOlfkNNqOU8MX91YuZFP5As67sB4/pG1+6V+Brodb9JQUI2Op9lmZ0+4L05k5IM+zmvLxbcGXXGsux0DASXAGgiCayOBgktLROfDPmedCTB0R3b02Z7ghMfgNHqPaycjy9+g0FwXwf/4GP4k= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1679921235; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=h0ARKpciyvlJkpzF/9XoqQBhluoMcoyy701jOPuzAdA=; b=aU0VD43H6inLswTAaVPwivIIOYAwIl5qnwjSWpVtjTb4+6nKaW7onGALv/ceqgRP9NWPa253AyHmSfs3G+N5iPCfLuDzRnyHm6NIdgIFAhaLQH9KDtz5oYOiGU4AxE2gEBivP/2Pbt9o9eSEZxQBnVdj/5ASQ9m2ky2wCkNvVqM= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1679921235213596.0959147597616; Mon, 27 Mar 2023 05:47:15 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pgmBi-00083R-Lv; Mon, 27 Mar 2023 08:43:02 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pgmBg-00082x-Nv for qemu-devel@nongnu.org; Mon, 27 Mar 2023 08:43:00 -0400 Received: from mail-oi1-x22b.google.com ([2607:f8b0:4864:20::22b]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pgmBe-00020r-Pb for qemu-devel@nongnu.org; Mon, 27 Mar 2023 08:43:00 -0400 Received: by mail-oi1-x22b.google.com with SMTP id bj20so6218994oib.3 for ; Mon, 27 Mar 2023 05:42:58 -0700 (PDT) Received: from grind.. ([177.95.89.231]) by smtp.gmail.com with ESMTPSA id m206-20020acabcd7000000b0037d7f4eb7e8sm11136677oif.31.2023.03.27.05.42.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 27 Mar 2023 05:42:56 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1679920976; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=h0ARKpciyvlJkpzF/9XoqQBhluoMcoyy701jOPuzAdA=; b=A9gV6LZgc+WbcE1d5XzkR+MEjRNhgRY6MLjXoQqPkW2SRFwhpxeC94Fzx2M88D4/UD Ua0psaYwtzWCA30S1qB64VOtJ1vxC9gZbtAPLVpuea2g2BPyUYA+GW8mXYDnup9zby/a rkSV/l7pYj26S1OrHfnTbc83chztFYux3WZ0rkpI3FD2Rf13tO4xJOOc6hymGMJi/Ryf 13YHaUdDqTNV6nGU0w94K56Xdsvlstb4sK0fVMRSRdQxQDGk3hrwUunJrDLBRw4o9ol9 yTGbQVGPNnhkPgO1dEfG9ox1DN8eZKmkVQGHQaoCT8k8/STMjJFmUphmFvgctJHYZQkk skIA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1679920976; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=h0ARKpciyvlJkpzF/9XoqQBhluoMcoyy701jOPuzAdA=; b=rFy7frOZvFWeNnmswBiEHQP4iWySaxmpHeyBtIe6iv+Q3Tug1kWBbRahzQU19MqhZb rRvokzR/mAkPKXYtUNcmOn9K15t42chibtgm+4SSK9zfpKw5dKjDQXp4mQlTrJYpKxlx baDx8NkM44ZRvmWDn1TTfg8U/kYr40kAc3TA9I3C3fhywGngFDENiCKOpxhk21lOXcjS jacWGwB51+X5Aow/1ZeUePDa+GDP0PbaXXDk62xlMz0Q2TBvO/o20bW8rRQdL+BRJriy OvKoleIfeKeNrMALxQColzWhLQ14QYXMF9WYLc2XIAcbcFIc4wkUnziqHmhDg33o/RqA nYKw== X-Gm-Message-State: AO0yUKUAPvZaQnwJlhHWOV4bREl82LCkBAejWa4YMwMJUpf7wzQq1jEZ bsbDQbnyJnXRCRHWBHd+OV+ENUK4Dgbs+0UhAv4= X-Google-Smtp-Source: AK7set+tZSmMed1wBFf94RQh66jivgypARjn3Zy7yQXtvomK0JohMsHhRIyZkTdgrl0G67SChYGz/w== X-Received: by 2002:a05:6808:917:b0:386:e8aa:cd20 with SMTP id w23-20020a056808091700b00386e8aacd20mr4874416oih.15.1679920976547; Mon, 27 Mar 2023 05:42:56 -0700 (PDT) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, bmeng@tinylab.org, liweiwei@iscas.ac.cn, zhiwei_liu@linux.alibaba.com, palmer@rivosinc.com, Daniel Henrique Barboza Subject: [PATCH 01/19] target/riscv: sync env->misa_ext* with cpu->cfg in realize() Date: Mon, 27 Mar 2023 09:42:29 -0300 Message-Id: <20230327124247.106595-2-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230327124247.106595-1-dbarboza@ventanamicro.com> References: <20230327124247.106595-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::22b; envelope-from=dbarboza@ventanamicro.com; helo=mail-oi1-x22b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ventanamicro.com) X-ZM-MESSAGEID: 1679921235641100001 Content-Type: text/plain; charset="utf-8" When riscv_cpu_realize() starts we're guaranteed to have cpu->cfg.ext_N properties updated. The same can't be said about env->misa_ext*, since the user might enable/disable MISA extensions in the command line, and env->misa_ext* won't caught these changes. The current solution is to sync everything at the end of validate_set_extensions(), checking every cpu->cfg.ext_N value to do a set_misa() in the end. The last change we're making in the MISA cfg flags are in the G extension logic, enabling IMAFG if cpu->cfg_ext.g is enabled. Otherwise we're not making any changes in MISA bits ever since realize() starts. There's no reason to postpone misa_ext updates until the end of the validation. Let's do it earlier, during realize(), in a new helper called riscv_cpu_sync_misa_cfg(). If cpu->cfg.ext_g is enabled, do it again by updating env->misa_ext* directly. This is a pre-requisite to allow riscv_cpu_validate_set_extensions() to use riscv_has_ext() instead of cpu->cfg.ext_N to validate the MISA extensions, which is our end goal here. Signed-off-by: Daniel Henrique Barboza --- target/riscv/cpu.c | 94 +++++++++++++++++++++++++++------------------- 1 file changed, 56 insertions(+), 38 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 1e97473af2..2711d80e16 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -804,12 +804,11 @@ static void riscv_cpu_disas_set_info(CPUState *s, dis= assemble_info *info) =20 /* * Check consistency between chosen extensions while setting - * cpu->cfg accordingly, doing a set_misa() in the end. + * cpu->cfg accordingly. */ static void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp) { CPURISCVState *env =3D &cpu->env; - uint32_t ext =3D 0; =20 /* Do some ISA extension error checking */ if (cpu->cfg.ext_g && !(cpu->cfg.ext_i && cpu->cfg.ext_m && @@ -824,6 +823,9 @@ static void riscv_cpu_validate_set_extensions(RISCVCPU = *cpu, Error **errp) cpu->cfg.ext_d =3D true; cpu->cfg.ext_icsr =3D true; cpu->cfg.ext_ifencei =3D true; + + env->misa_ext |=3D RVI | RVM | RVA | RVF | RVD; + env->misa_ext_mask =3D env->misa_ext; } =20 if (cpu->cfg.ext_i && cpu->cfg.ext_e) { @@ -962,39 +964,8 @@ static void riscv_cpu_validate_set_extensions(RISCVCPU= *cpu, Error **errp) cpu->cfg.ext_zksh =3D true; } =20 - if (cpu->cfg.ext_i) { - ext |=3D RVI; - } - if (cpu->cfg.ext_e) { - ext |=3D RVE; - } - if (cpu->cfg.ext_m) { - ext |=3D RVM; - } - if (cpu->cfg.ext_a) { - ext |=3D RVA; - } - if (cpu->cfg.ext_f) { - ext |=3D RVF; - } - if (cpu->cfg.ext_d) { - ext |=3D RVD; - } - if (cpu->cfg.ext_c) { - ext |=3D RVC; - } - if (cpu->cfg.ext_s) { - ext |=3D RVS; - } - if (cpu->cfg.ext_u) { - ext |=3D RVU; - } - if (cpu->cfg.ext_h) { - ext |=3D RVH; - } if (cpu->cfg.ext_v) { int vext_version =3D VEXT_VERSION_1_00_0; - ext |=3D RVV; if (!is_power_of_2(cpu->cfg.vlen)) { error_setg(errp, "Vector extension VLEN must be power of 2"); @@ -1032,11 +1003,6 @@ static void riscv_cpu_validate_set_extensions(RISCVC= PU *cpu, Error **errp) } set_vext_version(env, vext_version); } - if (cpu->cfg.ext_j) { - ext |=3D RVJ; - } - - set_misa(env, env->misa_mxl, ext); } =20 #ifndef CONFIG_USER_ONLY @@ -1121,6 +1087,50 @@ static void riscv_cpu_finalize_features(RISCVCPU *cp= u, Error **errp) #endif } =20 +static void riscv_cpu_sync_misa_cfg(CPURISCVState *env) +{ + uint32_t ext =3D 0; + + if (riscv_cpu_cfg(env)->ext_i) { + ext |=3D RVI; + } + if (riscv_cpu_cfg(env)->ext_e) { + ext |=3D RVE; + } + if (riscv_cpu_cfg(env)->ext_m) { + ext |=3D RVM; + } + if (riscv_cpu_cfg(env)->ext_a) { + ext |=3D RVA; + } + if (riscv_cpu_cfg(env)->ext_f) { + ext |=3D RVF; + } + if (riscv_cpu_cfg(env)->ext_d) { + ext |=3D RVD; + } + if (riscv_cpu_cfg(env)->ext_c) { + ext |=3D RVC; + } + if (riscv_cpu_cfg(env)->ext_s) { + ext |=3D RVS; + } + if (riscv_cpu_cfg(env)->ext_u) { + ext |=3D RVU; + } + if (riscv_cpu_cfg(env)->ext_h) { + ext |=3D RVH; + } + if (riscv_cpu_cfg(env)->ext_v) { + ext |=3D RVV; + } + if (riscv_cpu_cfg(env)->ext_j) { + ext |=3D RVJ; + } + + env->misa_ext =3D env->misa_ext_mask =3D ext; +} + static void riscv_cpu_realize(DeviceState *dev, Error **errp) { CPUState *cs =3D CPU(dev); @@ -1156,6 +1166,14 @@ static void riscv_cpu_realize(DeviceState *dev, Erro= r **errp) set_priv_version(env, priv_version); } =20 + /* + * We can't be sure of whether we set defaults during cpu_init() + * or whether the user enabled/disabled some bits via cpu->cfg + * flags. Sync env->misa_ext with cpu->cfg now to allow us to + * use just env->misa_ext later. + */ + riscv_cpu_sync_misa_cfg(env); + /* Force disable extensions if priv spec version does not match */ for (i =3D 0; i < ARRAY_SIZE(isa_edata_arr); i++) { if (isa_ext_is_enabled(cpu, &isa_edata_arr[i]) && --=20 2.39.2 From nobody Thu May 2 00:48:52 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1679921085; cv=none; d=zohomail.com; s=zohoarc; b=U1gXc+LXRwXZgHPNT2E3qPjPUaXlyZVbUrho5tR6aVsQixb2Vw8fnTxnbR6FGSOOh/sUi+Mfttmt1Ct+EderUEjnHb9s5U3gwcLTRInOquW0g/Rf4y4AcZz9BarWXSImncEzyaxhstDbVNgT2AKWiGEUgJXFLfYYdgBIwFgXq9I= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1679921085; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=YK09g81E8Kwzpq/ZRgaoIicZXmv7nuC/L4OwvxnL+TA=; b=hOe/frDuOvNO7Mno/RBCMoPWa7ihsMK/sDwJd0uM1dMfzTMfrd1dqGZ0jCnmBoJmJlOMyq6qPjP9PhZ5hxcxe/oN8HUK6J4T7cGVZZcnfV1teFgTMO/YUW/rw8fpwpmcaFGGyz5pNJo9/2HPioa5ZgoiiJULsjGSg0T+bKjetG4= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1679921085463833.243569889232; Mon, 27 Mar 2023 05:44:45 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pgmBl-00084h-B8; Mon, 27 Mar 2023 08:43:05 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pgmBj-00083v-L0 for qemu-devel@nongnu.org; Mon, 27 Mar 2023 08:43:03 -0400 Received: from mail-oi1-x22c.google.com ([2607:f8b0:4864:20::22c]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pgmBi-00027s-3q for qemu-devel@nongnu.org; Mon, 27 Mar 2023 08:43:03 -0400 Received: by mail-oi1-x22c.google.com with SMTP id w133so6222212oib.1 for ; Mon, 27 Mar 2023 05:43:01 -0700 (PDT) Received: from grind.. ([177.95.89.231]) by smtp.gmail.com with ESMTPSA id m206-20020acabcd7000000b0037d7f4eb7e8sm11136677oif.31.2023.03.27.05.42.56 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 27 Mar 2023 05:42:59 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1679920980; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=YK09g81E8Kwzpq/ZRgaoIicZXmv7nuC/L4OwvxnL+TA=; b=C5DwHfMzJgQifHHAWMIilqKkIP9Z/ZXtQLxKTAcFub/H4XJQzjyXQPI69IiEPRgREq ++FQlmdaDm6UD7Bk/ekp8oUNZEMrq+6pzPNEy5C2a7ytzEA8aJcYERN8aWO7PGTMK/Qd nEMf6AdKs05AZcGUa4m17AeKjbqlL+Kqhn4wQOmTLmkkwGH+Uo7MqQw1CvVFvDTLAiUg RB0dQt2XKlmrGh00ZWd4imohQGIfpFBi74srYq6NO0r6QXuYxJtsHSF6yuYEozvgSqaW wxnb9OCgCcEm0XXE6YGOQktyFNRjgKfBVe0i4+kdHwn3f+fakLTFQ3bsBu9/NK0969Hg upfA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1679920980; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=YK09g81E8Kwzpq/ZRgaoIicZXmv7nuC/L4OwvxnL+TA=; b=ZGhJOLHe1JhHngGTBd+U2qWC8BF4MwnfHLKQLBqNRD/fPOcxxEn82wLJ9AU2rwt5kC unhIWZtWyZHYqiiBiciz87TdCy40OlOW7fW1ERQNl8ePozBYdbxOYHVj7GBmx9/t1JfW ROIM78iBqcImrv4N/EZTcxZNKe5H1UwKzu5U8KRtmRF7RP724oHTvPZjwrxR5AZ5pfws V9PsjQXd4gE7rG6sZAzFBDkcCZVqRv9MLejp4l4JsKgNM8wGPTGMS3kbWopXQJGgLe0x wcHa68J8Jl9SNgXT8i4MZU8oTZGbO0BiGljCxmdgoWdPlcrE1tiveIscTBChgWq9d92i zqXQ== X-Gm-Message-State: AO0yUKXWHc5vNihNFAztaNU6TXV3+Mww4sf2244mdRhY3bmFJLPgL99E z5YRSV+pLZsNppZrQM02LhbSIG65QbI6IvJtZbI= X-Google-Smtp-Source: AK7set+HerrpDD7icUsWRnknu/DyJ8ISNTzKdRBAYUliQc38h7L8EeTgPEA3ohR7R5x/hNfbA9M+XQ== X-Received: by 2002:a05:6808:3a84:b0:37b:2252:b94c with SMTP id fb4-20020a0568083a8400b0037b2252b94cmr5424634oib.4.1679920979508; Mon, 27 Mar 2023 05:42:59 -0700 (PDT) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, bmeng@tinylab.org, liweiwei@iscas.ac.cn, zhiwei_liu@linux.alibaba.com, palmer@rivosinc.com, Daniel Henrique Barboza Subject: [PATCH 02/19] target/riscv: remove MISA properties from isa_edata_arr[] Date: Mon, 27 Mar 2023 09:42:30 -0300 Message-Id: <20230327124247.106595-3-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230327124247.106595-1-dbarboza@ventanamicro.com> References: <20230327124247.106595-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::22c; envelope-from=dbarboza@ventanamicro.com; helo=mail-oi1-x22c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ventanamicro.com) X-ZM-MESSAGEID: 1679921086894100006 Content-Type: text/plain; charset="utf-8" The code that disables extensions if there's a priv version mismatch uses cpu->cfg.ext_N properties to do its job. We're aiming to not rely on cpu->cfg.ext_N props for MISA bits. Split the MISA related verifications in a new function, removing it from isa_edata_arr[]. We're also erroring it out instead of disabling, making the cpu_init() function responsible for running an adequate priv spec for the MISA extensions it wants to use. Note that the RVV verification is being ignored since we're always have at least PRIV_VERSION_1_10_0. Signed-off-by: Daniel Henrique Barboza --- target/riscv/cpu.c | 19 +++++++++++++++++-- 1 file changed, 17 insertions(+), 2 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 2711d80e16..21c0c637e4 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -72,10 +72,11 @@ struct isa_ext_data { * 4. Non-standard extensions (starts with 'X') must be listed after all * standard extensions. They must be separated from other multi-letter * extensions by an underscore. + * + * Single letter extensions are checked in riscv_cpu_validate_misa_priv() + * instead. */ static const struct isa_ext_data isa_edata_arr[] =3D { - ISA_EXT_DATA_ENTRY(h, false, PRIV_VERSION_1_12_0, ext_h), - ISA_EXT_DATA_ENTRY(v, false, PRIV_VERSION_1_10_0, ext_v), ISA_EXT_DATA_ENTRY(zicbom, true, PRIV_VERSION_1_12_0, ext_icbom), ISA_EXT_DATA_ENTRY(zicboz, true, PRIV_VERSION_1_12_0, ext_icboz), ISA_EXT_DATA_ENTRY(zicond, true, PRIV_VERSION_1_12_0, ext_zicond), @@ -1131,6 +1132,14 @@ static void riscv_cpu_sync_misa_cfg(CPURISCVState *e= nv) env->misa_ext =3D env->misa_ext_mask =3D ext; } =20 +static void riscv_cpu_validate_misa_priv(CPURISCVState *env, Error **errp) +{ + if (riscv_has_ext(env, RVH) && env->priv_ver < PRIV_VERSION_1_12_0) { + error_setg(errp, "H extension requires priv spec 1.12.0"); + return; + } +} + static void riscv_cpu_realize(DeviceState *dev, Error **errp) { CPUState *cs =3D CPU(dev); @@ -1174,6 +1183,12 @@ static void riscv_cpu_realize(DeviceState *dev, Erro= r **errp) */ riscv_cpu_sync_misa_cfg(env); =20 + riscv_cpu_validate_misa_priv(env, &local_err); + if (local_err !=3D NULL) { + error_propagate(errp, local_err); + return; + } + /* Force disable extensions if priv spec version does not match */ for (i =3D 0; i < ARRAY_SIZE(isa_edata_arr); i++) { if (isa_ext_is_enabled(cpu, &isa_edata_arr[i]) && --=20 2.39.2 From nobody Thu May 2 00:48:52 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1679921058; cv=none; d=zohomail.com; s=zohoarc; b=GMFlf6tH8qqPtA7PMeIhyiMhL5G1cBX0xsKM5a3ve8W/eA29DOg2xmZBdhUd2ZLJgW2outjVBPePJ5TBnbs/Udo+GV0NbZ1w7WLtYb4REP5KpsM9SzwMj3fHUAb8g8/M5mhK0x4XydNKKdmThTzlXBCCP2TspcwobMZ0ApylRsw= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1679921058; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=jeg3GxSDxmmA0MBD21AJ7I14mC68S1GlN34RqLnYtvU=; b=SS9AfUxTXW8YbZWCapYP18UNiFfiEPv994QZM16nqrtzpCRIIOzBE3KfV9wSNnbyS1xO111iU9Zn41JbfHSeYb8yZgo017Uq+DrzlM/xNGo55NamNByeZI0cLiMEOYJQNT3eVt8wxH5h0TN3pKaxG3/rB9RZmAielaG8KARgrTc= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1679921058809307.980848121337; Mon, 27 Mar 2023 05:44:18 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pgmBm-00085K-Vw; Mon, 27 Mar 2023 08:43:07 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pgmBl-00084m-T2 for qemu-devel@nongnu.org; Mon, 27 Mar 2023 08:43:05 -0400 Received: from mail-oa1-x36.google.com ([2001:4860:4864:20::36]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pgmBk-0002Ak-1P for qemu-devel@nongnu.org; Mon, 27 Mar 2023 08:43:05 -0400 Received: by mail-oa1-x36.google.com with SMTP id 586e51a60fabf-17aaa51a911so9093738fac.5 for ; Mon, 27 Mar 2023 05:43:03 -0700 (PDT) Received: from grind.. ([177.95.89.231]) by smtp.gmail.com with ESMTPSA id m206-20020acabcd7000000b0037d7f4eb7e8sm11136677oif.31.2023.03.27.05.42.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 27 Mar 2023 05:43:02 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1679920982; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=jeg3GxSDxmmA0MBD21AJ7I14mC68S1GlN34RqLnYtvU=; b=Vwlj8mi9y92puZnB/cwjz3GttSugT8RYme541GySJeio5FhFulsWrqu2xY2EUbRWNy 7vC1wUBRuzlimNzFudwNiJuvEDYy3CUpWATWEY9r8Q7muiRPmbTf9wQckbsx6F3aoOhy 9JpLcTcNFJXJqTwMFYbVT8mcbdgm1b/ks1wd3WSzH4dO7M+jEzzXLc+Cw0K8B7p/OhcE 0LHO2OYRWB1Dp1z6WB7sb+JkfHRAas5NQZuvLT/cdrymRC82bEmnNrJ6qZK3hAeOCI22 E9JOIf/CfClJeUGLhEXF90I/mmp9XoP7FMY7F/Yj2f/Znp6j7W4UzMuf0moepGjENKTk r3wA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1679920982; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=jeg3GxSDxmmA0MBD21AJ7I14mC68S1GlN34RqLnYtvU=; b=5HL+225CoFobr2T5/f8NY99N3jMq7/ddOX4D6cw62+iaw4RngYS6b6TyD0hOhAGSnn y0zU0hZlUYcKZ0JaSLrsM8bmjgZZ2Rb1AJEEBJD9pzmNr9qusAlqO6e7ErRRrDShc2GG r6x5rzqmGmu7HoVO+hQqajGagVymtASDxaBu0jeqcfCpY+3r8ajkFfQewyMaUW5v3zD0 SmKrzyhWd9qFFAi/Fhrc4BCW9XqMQ62K2dBocqUNdVaUMk8PVo8Wu36z+yRWAdMj5J6Y LSox4x7qmxk3tvdL4kmiqXqytW9wDiWTPNokRg0PUI53Cm/b823Ccbj7NeoJLL3jZcys yd4Q== X-Gm-Message-State: AAQBX9d8JQY0yxwamJTQJWMjE3JsQ2dn12+9Iw1rf3BvdeQUAutqQG4f tjYJJM1jAbcXuDdwwwuEJ7PXjMd2TnMSUWRLi8s= X-Google-Smtp-Source: AK7set/yEAZvOT9HwYaWzLS5CMps64wIa5Y6Sbj86nZvd3vH4ekwl9yY0yDu9c/oJ9zpP1w37ty8Jw== X-Received: by 2002:a05:6870:d24f:b0:163:8b58:ab23 with SMTP id h15-20020a056870d24f00b001638b58ab23mr6910583oac.35.1679920982494; Mon, 27 Mar 2023 05:43:02 -0700 (PDT) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, bmeng@tinylab.org, liweiwei@iscas.ac.cn, zhiwei_liu@linux.alibaba.com, palmer@rivosinc.com, Daniel Henrique Barboza Subject: [PATCH 03/19] target/riscv: introduce riscv_cpu_add_misa_properties() Date: Mon, 27 Mar 2023 09:42:31 -0300 Message-Id: <20230327124247.106595-4-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230327124247.106595-1-dbarboza@ventanamicro.com> References: <20230327124247.106595-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2001:4860:4864:20::36; envelope-from=dbarboza@ventanamicro.com; helo=mail-oa1-x36.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ventanamicro.com) X-ZM-MESSAGEID: 1679921060805100011 Content-Type: text/plain; charset="utf-8" Ever since RISCVCPUConfig got introduced users are able to set CPU extensio= ns in the command line. User settings are reflected in the cpu->cfg object for later use. These properties are used in the target/riscv/cpu.c code, most notably in riscv_cpu_validate_set_extensions(), where most of our realize time validations are made. And then there's env->misa_ext, the field where the MISA extensions are set, that is read everywhere else. We need to keep env->misa_ext updated with cpu->cfg settings, since our validations rely on it, forcing us to make register_cpu_props() write cpu->cfg.ext_N flags to cover for named CPUs that aren't used named properties but also needs to go through the same validation steps. Failing to so will make those name CPUs fail validation (see c66ffcd5358b for more info). Not only that, but we also need to sync env->misa_ext with cpu->cfg again during realize() time to catch any change the user might have done, since the rest of the code relies on that. Making cpu->cfg.ext_N and env->misa_ext reflect each other is not needed. What we want is a way for users to enable/disable MISA extensions, and there's nothing stopping us from letting the user write env->misa_ext directly. Here are the artifacts that will enable us to do that: - RISCVCPUMisaExtConfig will declare each MISA property; - cpu_set_misa_ext_cfg() is the setter for each property. We'll write env->misa_ext and env->misa_ext_mask with the appropriate misa_bit; cutting off cpu->cfg.ext_N from the logic; - cpu_get_misa_ext_cfg() is a getter that will retrieve the current val of the property based on env->misa_ext; - riscv_cpu_add_misa_properties() will be called in register_cpu_props() to init all MISA properties from the misa_ext_cfgs[] array. With this infrastructure we'll start to get rid of each cpu->cfg.ext_N attribute in the next patches. Signed-off-by: Daniel Henrique Barboza --- target/riscv/cpu.c | 65 ++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 65 insertions(+) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 21c0c637e4..c33ba86085 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -1394,6 +1394,69 @@ static void riscv_cpu_init(Object *obj) #endif /* CONFIG_USER_ONLY */ } =20 +typedef struct RISCVCPUMisaExtConfig { + const char *name; + const char *description; + target_ulong misa_bit; + bool enabled; +} RISCVCPUMisaExtConfig; + +static void cpu_set_misa_ext_cfg(Object *obj, Visitor *v, const char *name, + void *opaque, Error **errp) +{ + RISCVCPUMisaExtConfig *misa_ext_cfg =3D opaque; + target_ulong misa_bit =3D misa_ext_cfg->misa_bit; + RISCVCPU *cpu =3D RISCV_CPU(obj); + CPURISCVState *env =3D &cpu->env; + bool value; + + if (!visit_type_bool(v, name, &value, errp)) { + return; + } + + if (value) { + env->misa_ext |=3D misa_bit; + env->misa_ext_mask |=3D misa_bit; + } else { + env->misa_ext &=3D ~misa_bit; + env->misa_ext_mask &=3D ~misa_bit; + } +} + +static void cpu_get_misa_ext_cfg(Object *obj, Visitor *v, const char *name, + void *opaque, Error **errp) +{ + RISCVCPUMisaExtConfig *misa_ext_cfg =3D opaque; + target_ulong misa_bit =3D misa_ext_cfg->misa_bit; + RISCVCPU *cpu =3D RISCV_CPU(obj); + CPURISCVState *env =3D &cpu->env; + bool value; + + value =3D env->misa_ext & misa_bit; + + visit_type_bool(v, name, &value, errp); +} + +static RISCVCPUMisaExtConfig misa_ext_cfgs[] =3D {}; + +static void riscv_cpu_add_misa_properties(Object *cpu_obj) +{ + int i; + + for (i =3D 0; i < ARRAY_SIZE(misa_ext_cfgs); i++) { + RISCVCPUMisaExtConfig *misa_cfg =3D &misa_ext_cfgs[i]; + g_autofree char *name =3D g_strdup_printf("%s", misa_cfg->name); + g_autofree char *desc =3D g_strdup_printf("%s", misa_cfg->descript= ion); + + object_property_add(cpu_obj, name, "bool", + cpu_get_misa_ext_cfg, + cpu_set_misa_ext_cfg, + NULL, misa_cfg); + object_property_set_description(cpu_obj, name, desc); + object_property_set_bool(cpu_obj, name, misa_cfg->enabled, NULL); + } +} + static Property riscv_cpu_extensions[] =3D { /* Defaults for standard extensions */ DEFINE_PROP_BOOL("i", RISCVCPU, cfg.ext_i, true), @@ -1531,6 +1594,8 @@ static void register_cpu_props(Object *obj) return; } =20 + riscv_cpu_add_misa_properties(obj); + for (prop =3D riscv_cpu_extensions; prop && prop->name; prop++) { qdev_property_add_static(dev, prop); } --=20 2.39.2 From nobody Thu May 2 00:48:52 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1679921084; cv=none; d=zohomail.com; s=zohoarc; b=QVMO2KElYNFs3JOz/gYUWf/nDkFIPwHT40m5ugSGPAbFGjQs2nXGNCWE7384nlyBHbCaMHu0zXw+kcRHDYoFfh7EyiUX5Q/60SSD/cFqkmXwk73LDys4rr0Qu1ha+jJWBdW+FvYVEeFG2nFmg8PARFmFdMRVubYSXf1Od8tcOoA= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1679921084; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=DAcHpKaxiY6Az83ZJ4/BliDw22FGWTTkygO0Lj2z+Rg=; b=Ao2Qpk5J445DK5Zs4g8/zd/wFq7fg4302VleDqiAWfkzI58sq5MRBckLS17Fe7HyRwin8CyFimadM4C6KmI6Xo2FJNvCYQ4T1Z22RhDyCzwVTsgfVdQOYjODYQuOA+b5LI4Y/VaTA0gEIJF+7kjqAErIE+8fHlP1ztevQzP/Ktk= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1679921084731844.3055249744893; Mon, 27 Mar 2023 05:44:44 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pgmBq-00086N-Bg; Mon, 27 Mar 2023 08:43:10 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pgmBo-00085o-9W for qemu-devel@nongnu.org; Mon, 27 Mar 2023 08:43:08 -0400 Received: from mail-oi1-x22c.google.com ([2607:f8b0:4864:20::22c]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pgmBm-00027s-KC for qemu-devel@nongnu.org; Mon, 27 Mar 2023 08:43:08 -0400 Received: by mail-oi1-x22c.google.com with SMTP id w133so6222430oib.1 for ; Mon, 27 Mar 2023 05:43:06 -0700 (PDT) Received: from grind.. ([177.95.89.231]) by smtp.gmail.com with ESMTPSA id m206-20020acabcd7000000b0037d7f4eb7e8sm11136677oif.31.2023.03.27.05.43.02 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 27 Mar 2023 05:43:05 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1679920985; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=DAcHpKaxiY6Az83ZJ4/BliDw22FGWTTkygO0Lj2z+Rg=; b=pHfaOPjMZVz0bVHOWSun6NGJl28E64QP3mLTB3LMb7fjLWxS9aQqQK4FSjTwtbeHXu RYOAdTEP0L0LZxaZXiYF6dYsMC3SimnQ+aVk+2YLXQNokkvlfUSnniW/vac9vNnbGoTB hS5iKHv+4BOAacdFVVjMzlniCOW0DH5sJXnSEXSxkpIu0VmidDU/j3MrRx7vI5Ti9xn+ OstCtEfWQTbXThknymsP5mGuekwSADnOEzJWc3AjxQj/rJ8rwz7taLqWfgSnmJ0zW1nR gXQ9CkLEVhfckxcpV6JEpOUZgmK2BBL0A2JIDmRUx5JbtsoNgRcQlP/4Qd8qAeXWevyt 7c2A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1679920985; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=DAcHpKaxiY6Az83ZJ4/BliDw22FGWTTkygO0Lj2z+Rg=; b=i8LoDU5KyiKD9bYKJzrV3jnQXrW9fe7rqDdWp6pY7s7tHpti6VgDf6mi325+MnIN1Y bWd1tOSEns0lf0o/WIOtjU2SpnCcAsRU4FVmsEzeEASRc+Vlil6+XWMJDK6zcHdXEeMk Afyz4mYxVWbDzsGnxudcBAjIl0OX0lNcQ1l6Pt0v38ls0E3w4zV52Orqn/3SzibiNfZF LTix4T2Z85hjCAp8+e5fzZC/WJ6KLu6Jec4kc8IeHl3fFg+LbEz/5QaEvxDwFmGeLjA+ /V4Q52+Ua3xu0Q/oc2hWEgeoKpWf+Q7ly1e9ubPrmf2mJZxNHkqUrHBhj6Si0LFOz4R1 Vi+Q== X-Gm-Message-State: AO0yUKXD0xw/jiEIJy3m3fOUJHpQKcP0bd0/zcrEZcHA/2BEzDoK8NUg PDbAgbQoaUEUQ/CpytaXJ+q9AauzrG1sJCSPDAs= X-Google-Smtp-Source: AK7set88a7K9jTK0RhuSS0rLEnCAAkgMT9r7ZCOFYfc+GxfonmiQrLyws+6QEEilxshiFuXINoE5fA== X-Received: by 2002:a54:4418:0:b0:387:5323:6aae with SMTP id k24-20020a544418000000b0038753236aaemr4826149oiw.27.1679920985605; Mon, 27 Mar 2023 05:43:05 -0700 (PDT) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, bmeng@tinylab.org, liweiwei@iscas.ac.cn, zhiwei_liu@linux.alibaba.com, palmer@rivosinc.com, Daniel Henrique Barboza Subject: [PATCH 04/19] target/riscv: remove cpu->cfg.ext_a Date: Mon, 27 Mar 2023 09:42:32 -0300 Message-Id: <20230327124247.106595-5-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230327124247.106595-1-dbarboza@ventanamicro.com> References: <20230327124247.106595-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::22c; envelope-from=dbarboza@ventanamicro.com; helo=mail-oi1-x22c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ventanamicro.com) X-ZM-MESSAGEID: 1679921086863100005 Content-Type: text/plain; charset="utf-8" Create a new "a" RISCVCPUMisaExtConfig property that will update env->misa_ext* with RVA. Instances of cpu->cfg.ext_a and similar are replaced with riscv_has_ext(env, RVA). Remove the old "a" property and 'ext_a' from RISCVCPUConfig. Signed-off-by: Daniel Henrique Barboza --- target/riscv/cpu.c | 16 ++++++++-------- target/riscv/cpu.h | 1 - 2 files changed, 8 insertions(+), 9 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index c33ba86085..d2484396c4 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -813,13 +813,12 @@ static void riscv_cpu_validate_set_extensions(RISCVCP= U *cpu, Error **errp) =20 /* Do some ISA extension error checking */ if (cpu->cfg.ext_g && !(cpu->cfg.ext_i && cpu->cfg.ext_m && - cpu->cfg.ext_a && cpu->cfg.ext_f && - cpu->cfg.ext_d && + riscv_has_ext(env, RVA) && + cpu->cfg.ext_f && cpu->cfg.ext_d && cpu->cfg.ext_icsr && cpu->cfg.ext_ifencei)) { warn_report("Setting G will also set IMAFD_Zicsr_Zifencei"); cpu->cfg.ext_i =3D true; cpu->cfg.ext_m =3D true; - cpu->cfg.ext_a =3D true; cpu->cfg.ext_f =3D true; cpu->cfg.ext_d =3D true; cpu->cfg.ext_icsr =3D true; @@ -863,7 +862,7 @@ static void riscv_cpu_validate_set_extensions(RISCVCPU = *cpu, Error **errp) return; } =20 - if ((cpu->cfg.ext_zawrs) && !cpu->cfg.ext_a) { + if ((cpu->cfg.ext_zawrs) && !riscv_has_ext(env, RVA)) { error_setg(errp, "Zawrs extension requires A extension"); return; } @@ -1101,7 +1100,7 @@ static void riscv_cpu_sync_misa_cfg(CPURISCVState *en= v) if (riscv_cpu_cfg(env)->ext_m) { ext |=3D RVM; } - if (riscv_cpu_cfg(env)->ext_a) { + if (riscv_has_ext(env, RVA)) { ext |=3D RVA; } if (riscv_cpu_cfg(env)->ext_f) { @@ -1437,7 +1436,10 @@ static void cpu_get_misa_ext_cfg(Object *obj, Visito= r *v, const char *name, visit_type_bool(v, name, &value, errp); } =20 -static RISCVCPUMisaExtConfig misa_ext_cfgs[] =3D {}; +static RISCVCPUMisaExtConfig misa_ext_cfgs[] =3D { + {.name =3D "a", .description =3D "Atomic instructions", + .misa_bit =3D RVA, .enabled =3D true}, +}; =20 static void riscv_cpu_add_misa_properties(Object *cpu_obj) { @@ -1463,7 +1465,6 @@ static Property riscv_cpu_extensions[] =3D { DEFINE_PROP_BOOL("e", RISCVCPU, cfg.ext_e, false), DEFINE_PROP_BOOL("g", RISCVCPU, cfg.ext_g, false), DEFINE_PROP_BOOL("m", RISCVCPU, cfg.ext_m, true), - DEFINE_PROP_BOOL("a", RISCVCPU, cfg.ext_a, true), DEFINE_PROP_BOOL("f", RISCVCPU, cfg.ext_f, true), DEFINE_PROP_BOOL("d", RISCVCPU, cfg.ext_d, true), DEFINE_PROP_BOOL("c", RISCVCPU, cfg.ext_c, true), @@ -1577,7 +1578,6 @@ static void register_cpu_props(Object *obj) cpu->cfg.ext_i =3D misa_ext & RVI; cpu->cfg.ext_e =3D misa_ext & RVE; cpu->cfg.ext_m =3D misa_ext & RVM; - cpu->cfg.ext_a =3D misa_ext & RVA; cpu->cfg.ext_f =3D misa_ext & RVF; cpu->cfg.ext_d =3D misa_ext & RVD; cpu->cfg.ext_v =3D misa_ext & RVV; diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 638e47c75a..f703888310 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -422,7 +422,6 @@ struct RISCVCPUConfig { bool ext_e; bool ext_g; bool ext_m; - bool ext_a; bool ext_f; bool ext_d; bool ext_c; --=20 2.39.2 From nobody Thu May 2 00:48:52 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1679921150; cv=none; d=zohomail.com; s=zohoarc; b=ZLBh9StSc+tTIy4fv9Us//h99jcjogT/GSpyUThY8d1I0Q8nw5g3NgCDcmtpwGCOz7phHQYou87Q0H3Cm5D1LPhvYexB/aGEKExtDa9PhJIWj/hlEraMKeWKQmqqciAg4tIAuK7drx5Rm2o6nA7Yvgjg8gOs7aaGb17wLX1Y11g= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1679921150; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=lphPf4lH+JzyZgr/nUY1W1Qn9cEYCwvMtSDywTf53DU=; b=aLYc0WvXiFOXgU03Emhx/r+ZiD5b98cS8kJIE3okEjBVelpvNqWANWGDphM461nHqESwkwWEpsIwds/wrSgJYArR2wRBp1aVsv8ny3SY2KZPotOmS2ZHzljDbTaQnz1eFXbbnfdgp8snh4N5PTh6snIAK735vMVHGJpFDZdI7yg= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1679921150837189.8713057647584; Mon, 27 Mar 2023 05:45:50 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pgmBs-00087a-Ir; Mon, 27 Mar 2023 08:43:12 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pgmBr-000875-I1 for qemu-devel@nongnu.org; Mon, 27 Mar 2023 08:43:11 -0400 Received: from mail-oi1-x22b.google.com ([2607:f8b0:4864:20::22b]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pgmBp-0002NI-VF for qemu-devel@nongnu.org; Mon, 27 Mar 2023 08:43:11 -0400 Received: by mail-oi1-x22b.google.com with SMTP id r16so6126570oij.5 for ; Mon, 27 Mar 2023 05:43:09 -0700 (PDT) Received: from grind.. ([177.95.89.231]) by smtp.gmail.com with ESMTPSA id m206-20020acabcd7000000b0037d7f4eb7e8sm11136677oif.31.2023.03.27.05.43.05 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 27 Mar 2023 05:43:08 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1679920988; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=lphPf4lH+JzyZgr/nUY1W1Qn9cEYCwvMtSDywTf53DU=; b=NznUf9NGPijtOxGOfDNVqXmjhtCvD06w0cXdzFjN6VQze50z2wGJX5m0KLeQAZSsGm ETJQ3YJajecS6Uurm6AIjq7zibJ+odGJDlYtwc+IyLSJGLSKG1de5k8IrGtnlwF9RYFJ JhT2nISCaORTDogNDJvsziW/vtIZgkh67SNmokzdM5CEBZb0QPNkiNjtR/gYhidu952x UjT7rOjTfcBanlVyze7s0XwsxFIEcpztyHDFk3C7XmoH0+O5eMzRK9td3Mky1W0e6B1g ph1eKejVNlacDuHmd1tl7C4UPY2yzC3o880qxjuXMjmYoiEavJgZvXMCExRSodNcksUn a9fA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1679920988; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=lphPf4lH+JzyZgr/nUY1W1Qn9cEYCwvMtSDywTf53DU=; b=bgrzTMoAaH50jxYvm/2xbZfawitcNdz5CwZjB7ykpmQW/a0hlK65PXjDQIzo+L90Ed 26nfvPR+xQbfv/7aPVkIMZtbEHh/2KEr4QsbHQF/ZAurWCKQIFxSNB8VL91OnNctyw3M Lfq+ZZt8CADYCFWURzlE1oRy312TpeGgEGEK0izAX2K4xqknIVt88CN9rFoteR9TwKaa Bz3PhZf3vhIaIIqOmJcchMO6VftukHUIa+T5A1QXaT7+rqamfk/aJbtsDLafZFLFDfwM XK6e2UrAlRShWI46/QEV+0z0yZodgkpwdShL7194iv897E/aKVrsD8uYbBNbvzWpjqj9 1nDw== X-Gm-Message-State: AO0yUKUtGDtUiigT51bo4sbFKmWkitpzJR+zqBOO8q1RtIiiQV8tKvsh W3zChJ9Kxi4Gt0ouPpvsDsVArYS14lOBNVVL8Yc= X-Google-Smtp-Source: AK7set98jmyY0Nj4OFg6FLiyUWXuzBpGupPqQx0N4WY9uSLCihpf6Xy4pPr8DD8/GIYotwbGdZzLfg== X-Received: by 2002:a54:4418:0:b0:378:6ca0:11e9 with SMTP id k24-20020a544418000000b003786ca011e9mr4861392oiw.28.1679920988664; Mon, 27 Mar 2023 05:43:08 -0700 (PDT) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, bmeng@tinylab.org, liweiwei@iscas.ac.cn, zhiwei_liu@linux.alibaba.com, palmer@rivosinc.com, Daniel Henrique Barboza Subject: [PATCH 05/19] target/riscv: remove cpu->cfg.ext_c Date: Mon, 27 Mar 2023 09:42:33 -0300 Message-Id: <20230327124247.106595-6-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230327124247.106595-1-dbarboza@ventanamicro.com> References: <20230327124247.106595-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::22b; envelope-from=dbarboza@ventanamicro.com; helo=mail-oi1-x22b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ventanamicro.com) X-ZM-MESSAGEID: 1679921151305100005 Content-Type: text/plain; charset="utf-8" Create a new "c" RISCVCPUMisaExtConfig property that will update env->misa_ext* with RVC. Instances of cpu->cfg.ext_c and similar are replaced with riscv_has_ext(env, RVC). Remove the old "c" property and 'ext_c' from RISCVCPUConfig. Signed-off-by: Daniel Henrique Barboza --- target/riscv/cpu.c | 7 +++---- target/riscv/cpu.h | 1 - 2 files changed, 3 insertions(+), 5 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index d2484396c4..694b1fc421 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -401,7 +401,6 @@ static void rv64_thead_c906_cpu_init(Object *obj) set_priv_version(env, PRIV_VERSION_1_11_0); =20 cpu->cfg.ext_g =3D true; - cpu->cfg.ext_c =3D true; cpu->cfg.ext_u =3D true; cpu->cfg.ext_s =3D true; cpu->cfg.ext_icsr =3D true; @@ -1109,7 +1108,7 @@ static void riscv_cpu_sync_misa_cfg(CPURISCVState *en= v) if (riscv_cpu_cfg(env)->ext_d) { ext |=3D RVD; } - if (riscv_cpu_cfg(env)->ext_c) { + if (riscv_has_ext(env, RVC)) { ext |=3D RVC; } if (riscv_cpu_cfg(env)->ext_s) { @@ -1439,6 +1438,8 @@ static void cpu_get_misa_ext_cfg(Object *obj, Visitor= *v, const char *name, static RISCVCPUMisaExtConfig misa_ext_cfgs[] =3D { {.name =3D "a", .description =3D "Atomic instructions", .misa_bit =3D RVA, .enabled =3D true}, + {.name =3D "c", .description =3D "Compressed instructions", + .misa_bit =3D RVC, .enabled =3D true}, }; =20 static void riscv_cpu_add_misa_properties(Object *cpu_obj) @@ -1467,7 +1468,6 @@ static Property riscv_cpu_extensions[] =3D { DEFINE_PROP_BOOL("m", RISCVCPU, cfg.ext_m, true), DEFINE_PROP_BOOL("f", RISCVCPU, cfg.ext_f, true), DEFINE_PROP_BOOL("d", RISCVCPU, cfg.ext_d, true), - DEFINE_PROP_BOOL("c", RISCVCPU, cfg.ext_c, true), DEFINE_PROP_BOOL("s", RISCVCPU, cfg.ext_s, true), DEFINE_PROP_BOOL("u", RISCVCPU, cfg.ext_u, true), DEFINE_PROP_BOOL("v", RISCVCPU, cfg.ext_v, false), @@ -1581,7 +1581,6 @@ static void register_cpu_props(Object *obj) cpu->cfg.ext_f =3D misa_ext & RVF; cpu->cfg.ext_d =3D misa_ext & RVD; cpu->cfg.ext_v =3D misa_ext & RVV; - cpu->cfg.ext_c =3D misa_ext & RVC; cpu->cfg.ext_s =3D misa_ext & RVS; cpu->cfg.ext_u =3D misa_ext & RVU; cpu->cfg.ext_h =3D misa_ext & RVH; diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index f703888310..c6dc24d236 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -424,7 +424,6 @@ struct RISCVCPUConfig { bool ext_m; bool ext_f; bool ext_d; - bool ext_c; bool ext_s; bool ext_u; bool ext_h; --=20 2.39.2 From nobody Thu May 2 00:48:52 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1679921181; cv=none; d=zohomail.com; s=zohoarc; b=Te2tx1S2VUIRGY8p/T+U4XEy3FVjHxjTlAWXCHNKKeeXCFcwLQX9AzT4mmQsJbTJABgXxx3jWpl+ZwlPPf0HZbSiNbfLSWEiyI+Fc48tpUP13/4PiFya5a+w56C6sTr0H21gJXcMLQNyy8Gv2hmLtGQPpvufRIauyIrwi98XVu4= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1679921181; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=f3PH2TFnkeB901Qn7wyy8VwwnpPrKXV0pkbhUywbe3I=; b=M0C2DVQuSyno5JY0aANy8dnpYp9USLGVczMJE8RiJ7epYZT8mt7Fdx/NXPUw95g3fB3gqCLyx56kPp7UpmQMq/AzqJxQzsXyXopwgqzgTEpOIAAjPw1ex2hHUGztWNjOCRWg4tKWEaeidH4fyTxOv4I2z/lrw2uGn37K4c0qjvs= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1679921181147496.6247166209697; Mon, 27 Mar 2023 05:46:21 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pgmBv-00088F-KH; Mon, 27 Mar 2023 08:43:15 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pgmBu-00087s-CT for qemu-devel@nongnu.org; Mon, 27 Mar 2023 08:43:14 -0400 Received: from mail-oi1-x22b.google.com ([2607:f8b0:4864:20::22b]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pgmBs-00027G-OC for qemu-devel@nongnu.org; Mon, 27 Mar 2023 08:43:14 -0400 Received: by mail-oi1-x22b.google.com with SMTP id l18so6187733oic.13 for ; Mon, 27 Mar 2023 05:43:12 -0700 (PDT) Received: from grind.. ([177.95.89.231]) by smtp.gmail.com with ESMTPSA id m206-20020acabcd7000000b0037d7f4eb7e8sm11136677oif.31.2023.03.27.05.43.09 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 27 Mar 2023 05:43:11 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1679920991; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=f3PH2TFnkeB901Qn7wyy8VwwnpPrKXV0pkbhUywbe3I=; b=eXxlbEtVq/2YjzY4EWcM09EbFSx44UolK3nmqb7O0kLERrclZupJ90+GSmvwyzGxl+ GMwSXVhbaYzxb+G1NVhkjCeyDfuUyX547etJmOQJ51DxD5/f9/Puz+FtqSUvHzsAogMW pr30t+QZ6cHQ0G2zQgvndSdfI7GH/aZWlP2tAyQcoxg2IwKjSxrH2za5s804Y5N4PqtX NRRNo6QL7XWFiE+oYOMk+q1hxNKvp+/cFAo0DHz18NXNG7tVq2kXaP7Jz06rRrUZwc7U IAeI3w1Ltm58csZU6p2K1RSquhrILhdlPPbH65EtAUeoWBI0OiSpB5ydltwiMWT3bNIC FL6Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1679920991; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=f3PH2TFnkeB901Qn7wyy8VwwnpPrKXV0pkbhUywbe3I=; b=d58l+Te1BUc0Jp/V3dLcYyrIorAo9xUC/C12CgEz3X9HFiT+VzP8PHAAKTJPIYTWpR O462hO9HdE0PxZPTwZuGm0AVrnwj6OIaw3O91Cz6K3Puhbi8655bO/M/FwUC+k0RWUcp 4Tlptn1HKhy1jlOv1lE8JIWphr957SiZJuDnZf0UbzQ80SLFWQ0SfJSdltdSCY1k08uN pH6C/4gdHQaaVn4iuHbBuRqims38TpShxnYQ3Q44uQIJggqxzkqrSOwVxVOlHeIftSHR csx5H1pcMseOPSRwQ4hyvfYybc/I+8w2UReZNPRInoiIEqRLgCCchfAv7dVTXaYKqFNX EzkQ== X-Gm-Message-State: AO0yUKWIKOkjlUvoJPLkgXnFjyl0obkgwTxyhvgZrb23V8b/KycFMakI 8YJDtC+OmS/4ZwqolyunPZXlvTlgMKhNut/iEvQ= X-Google-Smtp-Source: AK7set+mOcYLOAU4qxzHkfZ8YJlzhPm0ulmlp3KviybiNgZFkEz1LXdVbm1Ee0/CDyte8klFYrEfHQ== X-Received: by 2002:a05:6808:23c7:b0:386:c241:c43b with SMTP id bq7-20020a05680823c700b00386c241c43bmr6316680oib.20.1679920991628; Mon, 27 Mar 2023 05:43:11 -0700 (PDT) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, bmeng@tinylab.org, liweiwei@iscas.ac.cn, zhiwei_liu@linux.alibaba.com, palmer@rivosinc.com, Daniel Henrique Barboza Subject: [PATCH 06/19] target/riscv: remove cpu->cfg.ext_d Date: Mon, 27 Mar 2023 09:42:34 -0300 Message-Id: <20230327124247.106595-7-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230327124247.106595-1-dbarboza@ventanamicro.com> References: <20230327124247.106595-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::22b; envelope-from=dbarboza@ventanamicro.com; helo=mail-oi1-x22b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ventanamicro.com) X-ZM-MESSAGEID: 1679921181408100001 Content-Type: text/plain; charset="utf-8" Create a new "d" RISCVCPUMisaExtConfig property that will update env->misa_ext* with RVD. Instances of cpu->cfg.ext_d and similar are replaced with riscv_has_ext(env, RVD). Remove the old "d" property and 'ext_d' from RISCVCPUConfig. Signed-off-by: Daniel Henrique Barboza --- target/riscv/cpu.c | 13 ++++++------- target/riscv/cpu.h | 1 - 2 files changed, 6 insertions(+), 8 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 694b1fc421..701441b822 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -813,13 +813,12 @@ static void riscv_cpu_validate_set_extensions(RISCVCP= U *cpu, Error **errp) /* Do some ISA extension error checking */ if (cpu->cfg.ext_g && !(cpu->cfg.ext_i && cpu->cfg.ext_m && riscv_has_ext(env, RVA) && - cpu->cfg.ext_f && cpu->cfg.ext_d && + cpu->cfg.ext_f && riscv_has_ext(env, RVD) && cpu->cfg.ext_icsr && cpu->cfg.ext_ifencei)) { warn_report("Setting G will also set IMAFD_Zicsr_Zifencei"); cpu->cfg.ext_i =3D true; cpu->cfg.ext_m =3D true; cpu->cfg.ext_f =3D true; - cpu->cfg.ext_d =3D true; cpu->cfg.ext_icsr =3D true; cpu->cfg.ext_ifencei =3D true; =20 @@ -875,7 +874,7 @@ static void riscv_cpu_validate_set_extensions(RISCVCPU = *cpu, Error **errp) return; } =20 - if (cpu->cfg.ext_d && !cpu->cfg.ext_f) { + if (riscv_has_ext(env, RVD) && !cpu->cfg.ext_f) { error_setg(errp, "D extension requires F extension"); return; } @@ -895,7 +894,7 @@ static void riscv_cpu_validate_set_extensions(RISCVCPU = *cpu, Error **errp) cpu->cfg.ext_zve32f =3D true; } =20 - if (cpu->cfg.ext_zve64d && !cpu->cfg.ext_d) { + if (cpu->cfg.ext_zve64d && !riscv_has_ext(env, RVD)) { error_setg(errp, "Zve64d/V extensions require D extension"); return; } @@ -1105,7 +1104,7 @@ static void riscv_cpu_sync_misa_cfg(CPURISCVState *en= v) if (riscv_cpu_cfg(env)->ext_f) { ext |=3D RVF; } - if (riscv_cpu_cfg(env)->ext_d) { + if (riscv_has_ext(env, RVD)) { ext |=3D RVD; } if (riscv_has_ext(env, RVC)) { @@ -1440,6 +1439,8 @@ static RISCVCPUMisaExtConfig misa_ext_cfgs[] =3D { .misa_bit =3D RVA, .enabled =3D true}, {.name =3D "c", .description =3D "Compressed instructions", .misa_bit =3D RVC, .enabled =3D true}, + {.name =3D "d", .description =3D "Double-precision float point", + .misa_bit =3D RVD, .enabled =3D true}, }; =20 static void riscv_cpu_add_misa_properties(Object *cpu_obj) @@ -1467,7 +1468,6 @@ static Property riscv_cpu_extensions[] =3D { DEFINE_PROP_BOOL("g", RISCVCPU, cfg.ext_g, false), DEFINE_PROP_BOOL("m", RISCVCPU, cfg.ext_m, true), DEFINE_PROP_BOOL("f", RISCVCPU, cfg.ext_f, true), - DEFINE_PROP_BOOL("d", RISCVCPU, cfg.ext_d, true), DEFINE_PROP_BOOL("s", RISCVCPU, cfg.ext_s, true), DEFINE_PROP_BOOL("u", RISCVCPU, cfg.ext_u, true), DEFINE_PROP_BOOL("v", RISCVCPU, cfg.ext_v, false), @@ -1579,7 +1579,6 @@ static void register_cpu_props(Object *obj) cpu->cfg.ext_e =3D misa_ext & RVE; cpu->cfg.ext_m =3D misa_ext & RVM; cpu->cfg.ext_f =3D misa_ext & RVF; - cpu->cfg.ext_d =3D misa_ext & RVD; cpu->cfg.ext_v =3D misa_ext & RVV; cpu->cfg.ext_s =3D misa_ext & RVS; cpu->cfg.ext_u =3D misa_ext & RVU; diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index c6dc24d236..e4cf79e36f 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -423,7 +423,6 @@ struct RISCVCPUConfig { bool ext_g; bool ext_m; bool ext_f; - bool ext_d; bool ext_s; bool ext_u; bool ext_h; --=20 2.39.2 From nobody Thu May 2 00:48:52 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1679921055; cv=none; d=zohomail.com; s=zohoarc; b=n0phKflmLte9dl1ZX3LaWY7Qq97F0nHdqqlk7lI1K3R/ysRJF5R4c2pilJppLQoqGWgV372C6ed0fyabqiVE/AfJq0iBhYmzZwke8wNCTaprzFIUOaqpNc3S6ucMqH+bxGmC65NGEWyGiwcHWb0If2JNlLER60fHDX7rGCocvYU= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1679921055; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=260ddSViQ+qG/nsoedtmdoKkBRJmsmI1Vq9ms8jWkMg=; b=E2fve2NKxavZT9rMZC0cjTJNgnK5DK+g/MdNBlfhnftlNG0dK7GatO/3K1R04Ewk4r4msfOh7WhTlcoug27ruuzAq8fOHafr6VYymngoklMA0lhvgUGlBZsReNQJsQEsdocmgQZx3MlunmDycXYzO0f0TPJPEMbMY20enfjA7nk= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1679921055705757.3668888726478; Mon, 27 Mar 2023 05:44:15 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pgmBz-00089M-9Y; Mon, 27 Mar 2023 08:43:19 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pgmBx-00088u-TW for qemu-devel@nongnu.org; Mon, 27 Mar 2023 08:43:17 -0400 Received: from mail-oi1-x229.google.com ([2607:f8b0:4864:20::229]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pgmBw-0002Xh-9N for qemu-devel@nongnu.org; Mon, 27 Mar 2023 08:43:17 -0400 Received: by mail-oi1-x229.google.com with SMTP id f17so6198195oiw.10 for ; Mon, 27 Mar 2023 05:43:15 -0700 (PDT) Received: from grind.. ([177.95.89.231]) by smtp.gmail.com with ESMTPSA id m206-20020acabcd7000000b0037d7f4eb7e8sm11136677oif.31.2023.03.27.05.43.12 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 27 Mar 2023 05:43:14 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1679920994; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=260ddSViQ+qG/nsoedtmdoKkBRJmsmI1Vq9ms8jWkMg=; b=YlF7qDRRSA0Ry9+c0ZAG5CS4SpTeuwUSjArDNrtZfDhyROp9LszUHQb+131CQJuR8+ Ic2YjAOxBK2t9RzRaTwZbjAfT8iAT+7DD+1k+WdRxs6sWKmWOCLMf4n5Dac2jEd3bYAx 8ahWWjAbuwDjBho8T2Y4Vd3Ud7qIybadhG6gTMmlQFPZ++b9x8v4Ppjhl0BTeJobdVnV 7bABCAuegtzFmFlX8+gb0HlrH/mty7R+nASnQWKFsd4BuRzOK4pqsalbTx2tPpjq8Nvb 6uhgtsZui3HFWycUm6ahQyl9CUjkMMCkcpC6cvaIp2B60Svmi54wktmyGUijZ8yQoxTt iaTw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1679920994; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=260ddSViQ+qG/nsoedtmdoKkBRJmsmI1Vq9ms8jWkMg=; b=Qus/g6LSGmXJv/M1N8IKrQTf0Fo2E2Hb9nthXvKjtfXHO+HIhknu0ukqmvJxGLMnzl XKmf5qAU5jTM8Q0xAKz1DbTmuqW/gWEMrx9AvOwRrAlT+sATwURmtL7QDvaei67sCEVv HuFGk9L9E9SMUrbxKo+hlM6s0sZrICB6s153wcqID8UzY2B0SnDHGbaU+b1XCS6J1qrm ztTbspdxbm8hySDSYUfHuloyNjjRv9k74K4ExkDAB8XstcMcjTQTOrexexAUR1BXmAYV RNgEZtRTNwd/JDOX/9Gl3MZoDJdLOzdo2dT+z/manHabjUnwnNpk5HLwd5e+hxhsdhaT FPVg== X-Gm-Message-State: AO0yUKWMW2sARmtnlKyQYo1KmOJYc9h1IUaULYdfUsOjNUtK9ycAvQLv EdHgm5hW/ogFH7ZxXxOCx2TQJTBsImiYErhV5eA= X-Google-Smtp-Source: AK7set+5PpFuIUAHCODAKguARq+/zrXz1+H75QhB5FTTm+Vo1mnTsrZNfe9/WnpvNgWO69pCFqcu7A== X-Received: by 2002:a05:6808:659:b0:37f:84bf:f260 with SMTP id z25-20020a056808065900b0037f84bff260mr4713186oih.15.1679920994650; Mon, 27 Mar 2023 05:43:14 -0700 (PDT) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, bmeng@tinylab.org, liweiwei@iscas.ac.cn, zhiwei_liu@linux.alibaba.com, palmer@rivosinc.com, Daniel Henrique Barboza Subject: [PATCH 07/19] target/riscv: remove cpu->cfg.ext_f Date: Mon, 27 Mar 2023 09:42:35 -0300 Message-Id: <20230327124247.106595-8-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230327124247.106595-1-dbarboza@ventanamicro.com> References: <20230327124247.106595-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::229; envelope-from=dbarboza@ventanamicro.com; helo=mail-oi1-x229.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ventanamicro.com) X-ZM-MESSAGEID: 1679921056743100003 Content-Type: text/plain; charset="utf-8" Create a new "f" RISCVCPUMisaExtConfig property that will update env->misa_ext* with RVF. Instances of cpu->cfg.ext_f and similar are replaced with riscv_has_ext(env, RVF). Remove the old "f" property and 'ext_f' from RISCVCPUConfig. Signed-off-by: Daniel Henrique Barboza --- target/riscv/cpu.c | 20 ++++++++++---------- target/riscv/cpu.h | 1 - 2 files changed, 10 insertions(+), 11 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 701441b822..eb94db527d 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -813,12 +813,12 @@ static void riscv_cpu_validate_set_extensions(RISCVCP= U *cpu, Error **errp) /* Do some ISA extension error checking */ if (cpu->cfg.ext_g && !(cpu->cfg.ext_i && cpu->cfg.ext_m && riscv_has_ext(env, RVA) && - cpu->cfg.ext_f && riscv_has_ext(env, RVD) && + riscv_has_ext(env, RVF) && + riscv_has_ext(env, RVD) && cpu->cfg.ext_icsr && cpu->cfg.ext_ifencei)) { warn_report("Setting G will also set IMAFD_Zicsr_Zifencei"); cpu->cfg.ext_i =3D true; cpu->cfg.ext_m =3D true; - cpu->cfg.ext_f =3D true; cpu->cfg.ext_icsr =3D true; cpu->cfg.ext_ifencei =3D true; =20 @@ -855,7 +855,7 @@ static void riscv_cpu_validate_set_extensions(RISCVCPU = *cpu, Error **errp) return; } =20 - if (cpu->cfg.ext_f && !cpu->cfg.ext_icsr) { + if (riscv_has_ext(env, RVF) && !cpu->cfg.ext_icsr) { error_setg(errp, "F extension requires Zicsr"); return; } @@ -869,12 +869,12 @@ static void riscv_cpu_validate_set_extensions(RISCVCP= U *cpu, Error **errp) cpu->cfg.ext_zfhmin =3D true; } =20 - if (cpu->cfg.ext_zfhmin && !cpu->cfg.ext_f) { + if (cpu->cfg.ext_zfhmin && !riscv_has_ext(env, RVF)) { error_setg(errp, "Zfh/Zfhmin extensions require F extension"); return; } =20 - if (riscv_has_ext(env, RVD) && !cpu->cfg.ext_f) { + if (riscv_has_ext(env, RVD) && !riscv_has_ext(env, RVF)) { error_setg(errp, "D extension requires F extension"); return; } @@ -899,7 +899,7 @@ static void riscv_cpu_validate_set_extensions(RISCVCPU = *cpu, Error **errp) return; } =20 - if (cpu->cfg.ext_zve32f && !cpu->cfg.ext_f) { + if (cpu->cfg.ext_zve32f && !riscv_has_ext(env, RVF)) { error_setg(errp, "Zve32f/Zve64f extensions require F extension"); return; } @@ -932,7 +932,7 @@ static void riscv_cpu_validate_set_extensions(RISCVCPU = *cpu, Error **errp) error_setg(errp, "Zfinx extension requires Zicsr"); return; } - if (cpu->cfg.ext_f) { + if (riscv_has_ext(env, RVF)) { error_setg(errp, "Zfinx cannot be supported together with F extensio= n"); return; @@ -1101,7 +1101,7 @@ static void riscv_cpu_sync_misa_cfg(CPURISCVState *en= v) if (riscv_has_ext(env, RVA)) { ext |=3D RVA; } - if (riscv_cpu_cfg(env)->ext_f) { + if (riscv_has_ext(env, RVF)) { ext |=3D RVF; } if (riscv_has_ext(env, RVD)) { @@ -1441,6 +1441,8 @@ static RISCVCPUMisaExtConfig misa_ext_cfgs[] =3D { .misa_bit =3D RVC, .enabled =3D true}, {.name =3D "d", .description =3D "Double-precision float point", .misa_bit =3D RVD, .enabled =3D true}, + {.name =3D "f", .description =3D "Single-precision float point", + .misa_bit =3D RVF, .enabled =3D true}, }; =20 static void riscv_cpu_add_misa_properties(Object *cpu_obj) @@ -1467,7 +1469,6 @@ static Property riscv_cpu_extensions[] =3D { DEFINE_PROP_BOOL("e", RISCVCPU, cfg.ext_e, false), DEFINE_PROP_BOOL("g", RISCVCPU, cfg.ext_g, false), DEFINE_PROP_BOOL("m", RISCVCPU, cfg.ext_m, true), - DEFINE_PROP_BOOL("f", RISCVCPU, cfg.ext_f, true), DEFINE_PROP_BOOL("s", RISCVCPU, cfg.ext_s, true), DEFINE_PROP_BOOL("u", RISCVCPU, cfg.ext_u, true), DEFINE_PROP_BOOL("v", RISCVCPU, cfg.ext_v, false), @@ -1578,7 +1579,6 @@ static void register_cpu_props(Object *obj) cpu->cfg.ext_i =3D misa_ext & RVI; cpu->cfg.ext_e =3D misa_ext & RVE; cpu->cfg.ext_m =3D misa_ext & RVM; - cpu->cfg.ext_f =3D misa_ext & RVF; cpu->cfg.ext_v =3D misa_ext & RVV; cpu->cfg.ext_s =3D misa_ext & RVS; cpu->cfg.ext_u =3D misa_ext & RVU; diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index e4cf79e36f..ce23b1c431 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -422,7 +422,6 @@ struct RISCVCPUConfig { bool ext_e; bool ext_g; bool ext_m; - bool ext_f; bool ext_s; bool ext_u; bool ext_h; --=20 2.39.2 From nobody Thu May 2 00:48:52 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1679921056; cv=none; d=zohomail.com; s=zohoarc; b=AFrHjIdkNQnfnm/yuvoIahroIqO/Ubt+jCZOwt+hnBTXBR1J5apd/KH4FGg/IALETqK8cDA9/WAocVFC170ziNmHW4mlaEQvrWyx5hK3e/fPpHkvna0h0XXBiVwbJ1gK5sob0RnjLZL5fVZ3vxRyp9rqyV142dgishGKMPMFips= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1679921056; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=NPLIW+K5HEFU7Rrime8mCAa0g38NlXjUK3vYsdXHVIg=; b=oDTv+PRyguncLFGfh/HyKHHhZPYsGrggOzsf5sR5XDarXJlLC5qSfFN15p1mNNlx0Gz/CV6EFj0PMPTMqNMobx+RvPHszaxKXKoMkFoqEQW491U7JzaOXEYGI9M66ICLBQ/urFRlzUvhA34oxieQUXO23W1tMu31se9nn3Zyp3I= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1679921056812198.22628573599832; Mon, 27 Mar 2023 05:44:16 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pgmC2-0008AV-VS; Mon, 27 Mar 2023 08:43:22 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pgmC1-00089m-1g for qemu-devel@nongnu.org; Mon, 27 Mar 2023 08:43:21 -0400 Received: from mail-oi1-x22b.google.com ([2607:f8b0:4864:20::22b]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pgmBy-00027G-Ri for qemu-devel@nongnu.org; Mon, 27 Mar 2023 08:43:20 -0400 Received: by mail-oi1-x22b.google.com with SMTP id l18so6188001oic.13 for ; Mon, 27 Mar 2023 05:43:18 -0700 (PDT) Received: from grind.. ([177.95.89.231]) by smtp.gmail.com with ESMTPSA id m206-20020acabcd7000000b0037d7f4eb7e8sm11136677oif.31.2023.03.27.05.43.14 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 27 Mar 2023 05:43:17 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1679920998; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=NPLIW+K5HEFU7Rrime8mCAa0g38NlXjUK3vYsdXHVIg=; b=Sjz+B5Jly1i4WQncLW++lxlmzzdkvHu6tbjEUKLe0C7V8977polQMFeKFZYw43Mqzs v5udpe7hklkOnU9f0x1ZhkyD5a7uTFkGsfsT6XMM9BnfDV/bTFfhtXRrz57z2sq8zTSy wXEkQVKbnjnYoAEM5CZBRpMxzddaNqBx6eIALcOp92nykY8/t66QDfTRvIgzkzI5FqfV SKSOFpnQhmMJQlETVc7J4MsGOaO1eeFQp8foJF2PGKaJa3dvkGpzBpyfEFIkX6g3/4nj ryYpz8EDeiGPQtd0kpUM5sw1WThlHEruUW2r1ab3Rhc8Ta0v7jhnIpSPt1QEUa96L+VT nMTg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1679920998; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=NPLIW+K5HEFU7Rrime8mCAa0g38NlXjUK3vYsdXHVIg=; b=qEJ+/Cyna+wfWLAb9UZCfOOm30hz3o7rht6mVvsijkmUJk6mDTsEaAnEmuXSlVxUwU q9iJFj0X0PsZbe4ppZmrtHpkOYnQ7fd/DM+ZjDJlALGhMYZ4WLS7zZHaS5SRMI/2yfVI yD0u4OiXYsIo3cIuICJPVODtQdfNXqgmOoaFjvHxxjUg80xLSMSDO/yo03VU3WM3rsBf ysEhyoor1rh4XmqPQaWbNueF0yzAruO5P1OfXntMmrGS1gyzw6DtWCBUHTWV20oRiEgx vIzUqoGbbQbz6u+ajmTfF9kbxZr6eVY6VwcE4U6Q89KpxujAvwM3ixK4WMvnOGmpFnz/ 1Yuw== X-Gm-Message-State: AO0yUKU0tBpD39fn7jkp7tMsdPv+3iH12bWNe92wLqwFZD8BhTle5AYR T8otqpgpOz1QJQkVtmgPz7616oWhrOEZ8Sl3WNI= X-Google-Smtp-Source: AK7set/JUWTqI5/M4tACC2MogXaH+UnRNM5eEsU/khsstMdJNhqZ+k+A+MiYf/1rXpu0tdeZZ4YuPw== X-Received: by 2002:a05:6808:3087:b0:387:5258:393c with SMTP id bl7-20020a056808308700b003875258393cmr6836171oib.31.1679920997894; Mon, 27 Mar 2023 05:43:17 -0700 (PDT) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, bmeng@tinylab.org, liweiwei@iscas.ac.cn, zhiwei_liu@linux.alibaba.com, palmer@rivosinc.com, Daniel Henrique Barboza Subject: [PATCH 08/19] target/riscv: remove cpu->cfg.ext_i Date: Mon, 27 Mar 2023 09:42:36 -0300 Message-Id: <20230327124247.106595-9-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230327124247.106595-1-dbarboza@ventanamicro.com> References: <20230327124247.106595-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::22b; envelope-from=dbarboza@ventanamicro.com; helo=mail-oi1-x22b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ventanamicro.com) X-ZM-MESSAGEID: 1679921058770100007 Content-Type: text/plain; charset="utf-8" Create a new "i" RISCVCPUMisaExtConfig property that will update env->misa_ext* with RVI. Instances of cpu->cfg.ext_i and similar are replaced with riscv_has_ext(env, RVI). Remove the old "i" property and 'ext_i' from RISCVCPUConfig. Signed-off-by: Daniel Henrique Barboza --- target/riscv/cpu.c | 15 +++++++-------- target/riscv/cpu.h | 1 - 2 files changed, 7 insertions(+), 9 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index eb94db527d..e3d9496405 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -811,13 +811,12 @@ static void riscv_cpu_validate_set_extensions(RISCVCP= U *cpu, Error **errp) CPURISCVState *env =3D &cpu->env; =20 /* Do some ISA extension error checking */ - if (cpu->cfg.ext_g && !(cpu->cfg.ext_i && cpu->cfg.ext_m && + if (cpu->cfg.ext_g && !(riscv_has_ext(env, RVI) && cpu->cfg.ext_m && riscv_has_ext(env, RVA) && riscv_has_ext(env, RVF) && riscv_has_ext(env, RVD) && cpu->cfg.ext_icsr && cpu->cfg.ext_ifencei)) { warn_report("Setting G will also set IMAFD_Zicsr_Zifencei"); - cpu->cfg.ext_i =3D true; cpu->cfg.ext_m =3D true; cpu->cfg.ext_icsr =3D true; cpu->cfg.ext_ifencei =3D true; @@ -826,13 +825,13 @@ static void riscv_cpu_validate_set_extensions(RISCVCP= U *cpu, Error **errp) env->misa_ext_mask =3D env->misa_ext; } =20 - if (cpu->cfg.ext_i && cpu->cfg.ext_e) { + if (riscv_has_ext(env, RVI) && cpu->cfg.ext_e) { error_setg(errp, "I and E extensions are incompatible"); return; } =20 - if (!cpu->cfg.ext_i && !cpu->cfg.ext_e) { + if (!riscv_has_ext(env, RVI) && !cpu->cfg.ext_e) { error_setg(errp, "Either I or E extension must be set"); return; @@ -844,7 +843,7 @@ static void riscv_cpu_validate_set_extensions(RISCVCPU = *cpu, Error **errp) return; } =20 - if (cpu->cfg.ext_h && !cpu->cfg.ext_i) { + if (cpu->cfg.ext_h && !riscv_has_ext(env, RVI)) { error_setg(errp, "H depends on an I base integer ISA with 32 x registers= "); return; @@ -1089,7 +1088,7 @@ static void riscv_cpu_sync_misa_cfg(CPURISCVState *en= v) { uint32_t ext =3D 0; =20 - if (riscv_cpu_cfg(env)->ext_i) { + if (riscv_has_ext(env, RVI)) { ext |=3D RVI; } if (riscv_cpu_cfg(env)->ext_e) { @@ -1443,6 +1442,8 @@ static RISCVCPUMisaExtConfig misa_ext_cfgs[] =3D { .misa_bit =3D RVD, .enabled =3D true}, {.name =3D "f", .description =3D "Single-precision float point", .misa_bit =3D RVF, .enabled =3D true}, + {.name =3D "i", .description =3D "Base integer instruction set", + .misa_bit =3D RVI, .enabled =3D true}, }; =20 static void riscv_cpu_add_misa_properties(Object *cpu_obj) @@ -1465,7 +1466,6 @@ static void riscv_cpu_add_misa_properties(Object *cpu= _obj) =20 static Property riscv_cpu_extensions[] =3D { /* Defaults for standard extensions */ - DEFINE_PROP_BOOL("i", RISCVCPU, cfg.ext_i, true), DEFINE_PROP_BOOL("e", RISCVCPU, cfg.ext_e, false), DEFINE_PROP_BOOL("g", RISCVCPU, cfg.ext_g, false), DEFINE_PROP_BOOL("m", RISCVCPU, cfg.ext_m, true), @@ -1576,7 +1576,6 @@ static void register_cpu_props(Object *obj) * later on. */ if (cpu->env.misa_ext !=3D 0) { - cpu->cfg.ext_i =3D misa_ext & RVI; cpu->cfg.ext_e =3D misa_ext & RVE; cpu->cfg.ext_m =3D misa_ext & RVM; cpu->cfg.ext_v =3D misa_ext & RVV; diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index ce23b1c431..573bf85ff1 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -418,7 +418,6 @@ typedef struct { } RISCVSATPMap; =20 struct RISCVCPUConfig { - bool ext_i; bool ext_e; bool ext_g; bool ext_m; --=20 2.39.2 From nobody Thu May 2 00:48:52 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1679921079; cv=none; d=zohomail.com; s=zohoarc; b=C4D4CqLGSZCsFaXyAGRtpPiq3NAsVX0w91RPoVgD/EpS/s9LM/9qqvddc2CKKC9GkkPlfhSmSkqeP4S2k1FBcv8XErh5WAFwShOvOQD//BlMn+bo/HhHlQMQCSy6md6LXeSBmhnrnsDLlPwo5Fv5L57NSf21/QRbmPcWqrnwEos= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1679921079; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=CcBA7LXJYSzTcI4ioO/yN8kqidR7az1J8tyV5XXcKnQ=; b=m34B52l66Jt4tw5d93Cl7JxFEKP6l2p40SBtlUbjexhoZX+x3SSEZWiZlrZoI2EqR4E7dwPErlIzqHxepqzn2mww1V07fSoKNb1GQkUs/vBq4rGbd9eZc7MfsuT/oMuEuYlp782BnLSRPGoXI8Pz7gabFEGvqxrVOLaaibiY8F0= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 167992107954054.55380161057633; Mon, 27 Mar 2023 05:44:39 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pgmC5-0008Av-7R; Mon, 27 Mar 2023 08:43:25 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pgmC3-0008Ae-HF for qemu-devel@nongnu.org; Mon, 27 Mar 2023 08:43:23 -0400 Received: from mail-oi1-x22c.google.com ([2607:f8b0:4864:20::22c]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pgmC1-00027s-Vp for qemu-devel@nongnu.org; Mon, 27 Mar 2023 08:43:23 -0400 Received: by mail-oi1-x22c.google.com with SMTP id w133so6223051oib.1 for ; Mon, 27 Mar 2023 05:43:21 -0700 (PDT) Received: from grind.. ([177.95.89.231]) by smtp.gmail.com with ESMTPSA id m206-20020acabcd7000000b0037d7f4eb7e8sm11136677oif.31.2023.03.27.05.43.18 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 27 Mar 2023 05:43:20 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1679921001; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=CcBA7LXJYSzTcI4ioO/yN8kqidR7az1J8tyV5XXcKnQ=; b=d+fsnQAhKJSRS78C6w0fdV0mMwXBt32KnP45h4Pj2KgWzU3wumRZmfO8ihRxiPW6p/ A4LlX14P0II6rYeXe2j+O+cRe2Ife8JofkBTHA/qL4gwOC9CepnxDEfGG7q5YhqzTXK7 Ru6KNEdK8cIFQfNCDVmGBIFe2IcZPIClDmNR6wNlEen+KzQgKuxKbA2sXbuxtKew66Tk BNMKq+jaogw2EiT3wOCrsfmTymmhInNXqJ7d/+BlhLD9jPN2ais/1Cs/f9TBIwtPyWHu SlvxYcAauhacCuI5a/pQa30Tox+EsyPmistji+VkUBcP4VD1RcliWDTdTjUv8ZtCt6oM 8C/g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1679921001; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=CcBA7LXJYSzTcI4ioO/yN8kqidR7az1J8tyV5XXcKnQ=; b=dQQAgOsGmTQMx1+f10okXqjJdJvOGqm1h5PbfkoUFpiFTkSSvb6op7VQqwy8pLFiu/ rIRoyc1DPfTtgQOVu6ZG4nrr0Tfe9JkkcOr8p8IM3EaM+o+FuOKbqad3/NrZK+56Xamt JRpAn8smyG224kJaN1Jkw/xJaNK3d+8sikr5Gz2Vzn536Lht434t0dCRoUKwhOKnjm14 vJg1BfjNoaE2UxuosEXpt/THOTKn6IFr85r601s2pbI9RaHZvIr9UV/p+Z5HrdAwXVsL DRXKY+45brHZD/bCXdYyEe4CS51TnKK2KMT1FZ25AfxLZC/7VxkekxMb5SYSLK493Mm3 xiUg== X-Gm-Message-State: AO0yUKUnnvQ56i54l06cHR7Pcy7uW5bJLkZlvTz0I8KMIrYPF/yaig6L +X+UmI4xiyW24cHYXXVQN44ooKVpe7wU3Lse2S8= X-Google-Smtp-Source: AK7set8Q02vdnjyv5lEoPkx7/HqUg/u4i3emHTjuF8Yf1b0gGsGsCkKRiUcZnHy3j0IrHMVdvqSCNQ== X-Received: by 2002:a05:6808:21a0:b0:386:cb87:d205 with SMTP id be32-20020a05680821a000b00386cb87d205mr7146786oib.47.1679921000934; Mon, 27 Mar 2023 05:43:20 -0700 (PDT) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, bmeng@tinylab.org, liweiwei@iscas.ac.cn, zhiwei_liu@linux.alibaba.com, palmer@rivosinc.com, Daniel Henrique Barboza Subject: [PATCH 09/19] target/riscv: remove cpu->cfg.ext_e Date: Mon, 27 Mar 2023 09:42:37 -0300 Message-Id: <20230327124247.106595-10-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230327124247.106595-1-dbarboza@ventanamicro.com> References: <20230327124247.106595-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::22c; envelope-from=dbarboza@ventanamicro.com; helo=mail-oi1-x22c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ventanamicro.com) X-ZM-MESSAGEID: 1679921080871100003 Content-Type: text/plain; charset="utf-8" Create a new "e" RISCVCPUMisaExtConfig property that will update env->misa_ext* with RVE. Instances of cpu->cfg.ext_e and similar are replaced with riscv_has_ext(env, RVE). Remove the old "e" property and 'ext_e' from RISCVCPUConfig. Signed-off-by: Daniel Henrique Barboza --- target/riscv/cpu.c | 10 +++++----- target/riscv/cpu.h | 1 - 2 files changed, 5 insertions(+), 6 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index e3d9496405..65e4a76bae 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -825,13 +825,13 @@ static void riscv_cpu_validate_set_extensions(RISCVCP= U *cpu, Error **errp) env->misa_ext_mask =3D env->misa_ext; } =20 - if (riscv_has_ext(env, RVI) && cpu->cfg.ext_e) { + if (riscv_has_ext(env, RVI) && riscv_has_ext(env, RVE)) { error_setg(errp, "I and E extensions are incompatible"); return; } =20 - if (!riscv_has_ext(env, RVI) && !cpu->cfg.ext_e) { + if (!riscv_has_ext(env, RVI) && !riscv_has_ext(env, RVE)) { error_setg(errp, "Either I or E extension must be set"); return; @@ -1091,7 +1091,7 @@ static void riscv_cpu_sync_misa_cfg(CPURISCVState *en= v) if (riscv_has_ext(env, RVI)) { ext |=3D RVI; } - if (riscv_cpu_cfg(env)->ext_e) { + if (riscv_has_ext(env, RVE)) { ext |=3D RVE; } if (riscv_cpu_cfg(env)->ext_m) { @@ -1444,6 +1444,8 @@ static RISCVCPUMisaExtConfig misa_ext_cfgs[] =3D { .misa_bit =3D RVF, .enabled =3D true}, {.name =3D "i", .description =3D "Base integer instruction set", .misa_bit =3D RVI, .enabled =3D true}, + {.name =3D "e", .description =3D "Base integer instruction set (embedd= ed)", + .misa_bit =3D RVE, .enabled =3D false}, }; =20 static void riscv_cpu_add_misa_properties(Object *cpu_obj) @@ -1466,7 +1468,6 @@ static void riscv_cpu_add_misa_properties(Object *cpu= _obj) =20 static Property riscv_cpu_extensions[] =3D { /* Defaults for standard extensions */ - DEFINE_PROP_BOOL("e", RISCVCPU, cfg.ext_e, false), DEFINE_PROP_BOOL("g", RISCVCPU, cfg.ext_g, false), DEFINE_PROP_BOOL("m", RISCVCPU, cfg.ext_m, true), DEFINE_PROP_BOOL("s", RISCVCPU, cfg.ext_s, true), @@ -1576,7 +1577,6 @@ static void register_cpu_props(Object *obj) * later on. */ if (cpu->env.misa_ext !=3D 0) { - cpu->cfg.ext_e =3D misa_ext & RVE; cpu->cfg.ext_m =3D misa_ext & RVM; cpu->cfg.ext_v =3D misa_ext & RVV; cpu->cfg.ext_s =3D misa_ext & RVS; diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 573bf85ff1..cc0b9e73ac 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -418,7 +418,6 @@ typedef struct { } RISCVSATPMap; =20 struct RISCVCPUConfig { - bool ext_e; bool ext_g; bool ext_m; bool ext_s; --=20 2.39.2 From nobody Thu May 2 00:48:52 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1679921152; cv=none; d=zohomail.com; s=zohoarc; b=SSGY57mcKeAFkZR2+0MjJb3MnNtDLrgGvRudy5pokgiqlvfM4vmko34ofaL/xTYr1fDL2gyqeywpqQrxdqnm5v31CC6hwps9WQK8Vz21ZMWFPIogEdBoU5hxBHNOxaA3kJ2IXTVRHHK2orep1wttBJo+DATcT7ttH7+z748Ufuc= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1679921152; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=lVBWSjIdw3gkUFHTty+q6ErZT4MfbOFOY3bgWzhoIZw=; b=lDyYmxKoF1nkeGGTXzrhKBBC2926Rkl5Y8GPXFkAhaaugC9wGn9jX8Bgy72Vejs07tqZ7YjM+ZdEFjuHH5K31G81yaHTjm7oyrnX1FnguTSAYJsnoxvTsIXUBnZ2zb60tiB8JWXMsTjPeNvRNvYCsnLK/kpZtr1c5JJ5VIP/lqw= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1679921152088449.19057733175487; Mon, 27 Mar 2023 05:45:52 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pgmC8-0008Du-C1; Mon, 27 Mar 2023 08:43:28 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pgmC7-0008DK-Cu for qemu-devel@nongnu.org; Mon, 27 Mar 2023 08:43:27 -0400 Received: from mail-oi1-x22c.google.com ([2607:f8b0:4864:20::22c]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pgmC5-00020I-E1 for qemu-devel@nongnu.org; Mon, 27 Mar 2023 08:43:27 -0400 Received: by mail-oi1-x22c.google.com with SMTP id y184so6208881oiy.8 for ; Mon, 27 Mar 2023 05:43:25 -0700 (PDT) Received: from grind.. ([177.95.89.231]) by smtp.gmail.com with ESMTPSA id m206-20020acabcd7000000b0037d7f4eb7e8sm11136677oif.31.2023.03.27.05.43.21 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 27 Mar 2023 05:43:23 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1679921004; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=lVBWSjIdw3gkUFHTty+q6ErZT4MfbOFOY3bgWzhoIZw=; b=OENU0qlB/RsgfzhpkG1geJOfLzFXlmwTevOHTFakyxcuS4bpnsn98BFjAT1mupOmD/ FKvJsV3zvY9B5kGXnRohGK5c9bagwu/8QSUkJJ+ZJ3gPgkAPNtr/GuBn0Nzl9pRc/Z7d +T+9avC5bmz4ZQxqoHZuN3HAxV5FBQ7z0+GBU4/fDpDILnlce6Nocqoxc6aiXB2sPwQV igE7zpBOzlU28+okKZxuV6+4mgKka19/2DJEqZMQwU1ojiPnDaq4QdPao2pLuDTx8cSo a9pJao88hqevs6jKt+bUOOXOJy6Sqz5jDmihi4puL86cExYXzxzpsIpRMTR2qVuY4A/1 Y3Ig== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1679921004; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=lVBWSjIdw3gkUFHTty+q6ErZT4MfbOFOY3bgWzhoIZw=; b=cMv7EVnhz2FqyUqbUNToXX6dKupIXRM8iCEv0nZLnOi3ttcHsffbd2pqkUOLWfhrW+ m5VQ2Q4OJmKQYgRLsb8gfyZ5amNrx6/LG4Lg7WIo/tdK9OX4FWIiAaKin2C7TIvO0K/n UzGGuDYNHKB1McNb/dwKcXHESxKcUyURGhwwdBODkU2UzGnjY3nZ0ZJDt6NX/nD30F/3 gY1trdqnP2ixYbnmRTDeKY1DnVvFrKKizfU6esyEe+QvaFdTp1vaZBVMWfHZwEe8K6Aj pEEE1iHmHFVVOorChyluQtjYt7UOi7RR2N3fkI7kegeIipMIdQPXCjgzS4IGIGFwllq8 MFQA== X-Gm-Message-State: AO0yUKV0skO2f4+hWXl9er3Ekc920faUkJ/J91HrsAZQV/cTiIOrGp3x ko6PV7cxlroo1w/mgEjSTs3KCSf+R91IBGTrXmw= X-Google-Smtp-Source: AK7set+kH6KE7H37jXsBBYt0Lvk4F9DW7FTdSogLzSC55hTeYanaOu56yBAwsvlr/aYR6IkjKipgUQ== X-Received: by 2002:a54:4f03:0:b0:35e:1a0f:7dea with SMTP id e3-20020a544f03000000b0035e1a0f7deamr5252689oiy.12.1679921003875; Mon, 27 Mar 2023 05:43:23 -0700 (PDT) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, bmeng@tinylab.org, liweiwei@iscas.ac.cn, zhiwei_liu@linux.alibaba.com, palmer@rivosinc.com, Daniel Henrique Barboza Subject: [PATCH 10/19] target/riscv: remove cpu->cfg.ext_m Date: Mon, 27 Mar 2023 09:42:38 -0300 Message-Id: <20230327124247.106595-11-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230327124247.106595-1-dbarboza@ventanamicro.com> References: <20230327124247.106595-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::22c; envelope-from=dbarboza@ventanamicro.com; helo=mail-oi1-x22c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ventanamicro.com) X-ZM-MESSAGEID: 1679921153311100011 Content-Type: text/plain; charset="utf-8" Create a new "m" RISCVCPUMisaExtConfig property that will update env->misa_ext* with RVM. Instances of cpu->cfg.ext_m and similar are replaced with riscv_has_ext(env, RVM). Remove the old "m" property and 'ext_m' from RISCVCPUConfig. Signed-off-by: Daniel Henrique Barboza --- target/riscv/cpu.c | 10 +++++----- target/riscv/cpu.h | 1 - 2 files changed, 5 insertions(+), 6 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 65e4a76bae..9f4d8fe7e8 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -811,13 +811,13 @@ static void riscv_cpu_validate_set_extensions(RISCVCP= U *cpu, Error **errp) CPURISCVState *env =3D &cpu->env; =20 /* Do some ISA extension error checking */ - if (cpu->cfg.ext_g && !(riscv_has_ext(env, RVI) && cpu->cfg.ext_m && + if (cpu->cfg.ext_g && !(riscv_has_ext(env, RVI) && + riscv_has_ext(env, RVM) && riscv_has_ext(env, RVA) && riscv_has_ext(env, RVF) && riscv_has_ext(env, RVD) && cpu->cfg.ext_icsr && cpu->cfg.ext_ifencei)) { warn_report("Setting G will also set IMAFD_Zicsr_Zifencei"); - cpu->cfg.ext_m =3D true; cpu->cfg.ext_icsr =3D true; cpu->cfg.ext_ifencei =3D true; =20 @@ -1094,7 +1094,7 @@ static void riscv_cpu_sync_misa_cfg(CPURISCVState *en= v) if (riscv_has_ext(env, RVE)) { ext |=3D RVE; } - if (riscv_cpu_cfg(env)->ext_m) { + if (riscv_has_ext(env, RVM)) { ext |=3D RVM; } if (riscv_has_ext(env, RVA)) { @@ -1446,6 +1446,8 @@ static RISCVCPUMisaExtConfig misa_ext_cfgs[] =3D { .misa_bit =3D RVI, .enabled =3D true}, {.name =3D "e", .description =3D "Base integer instruction set (embedd= ed)", .misa_bit =3D RVE, .enabled =3D false}, + {.name =3D "m", .description =3D "Integer multiplication and division", + .misa_bit =3D RVM, .enabled =3D true}, }; =20 static void riscv_cpu_add_misa_properties(Object *cpu_obj) @@ -1469,7 +1471,6 @@ static void riscv_cpu_add_misa_properties(Object *cpu= _obj) static Property riscv_cpu_extensions[] =3D { /* Defaults for standard extensions */ DEFINE_PROP_BOOL("g", RISCVCPU, cfg.ext_g, false), - DEFINE_PROP_BOOL("m", RISCVCPU, cfg.ext_m, true), DEFINE_PROP_BOOL("s", RISCVCPU, cfg.ext_s, true), DEFINE_PROP_BOOL("u", RISCVCPU, cfg.ext_u, true), DEFINE_PROP_BOOL("v", RISCVCPU, cfg.ext_v, false), @@ -1577,7 +1578,6 @@ static void register_cpu_props(Object *obj) * later on. */ if (cpu->env.misa_ext !=3D 0) { - cpu->cfg.ext_m =3D misa_ext & RVM; cpu->cfg.ext_v =3D misa_ext & RVV; cpu->cfg.ext_s =3D misa_ext & RVS; cpu->cfg.ext_u =3D misa_ext & RVU; diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index cc0b9e73ac..7a42c80b7d 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -419,7 +419,6 @@ typedef struct { =20 struct RISCVCPUConfig { bool ext_g; - bool ext_m; bool ext_s; bool ext_u; bool ext_h; --=20 2.39.2 From nobody Thu May 2 00:48:52 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1679921106; cv=none; d=zohomail.com; s=zohoarc; b=Js1wqqHmN8GXIIo7eq2ZJ6JubgBq6plVIoBd2CBEQLt+YVAoWOJDCoiowK3EPUYpj8KoyD6OBZ9uZ/mB8puHURE/8dl51LX9AzVDu60udypm4dBHKV4mCDsJS5PuNAHcwFj485mu2XVCyXoz7w5cX9Wn8ARXpbDB0umKuXfyLo0= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1679921106; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=OSF/2nxdcwDZKN3dSMKYqw7KHIdYOdgDb/smyRYwUwQ=; b=oHXy2MVojSjHM0FRJm5kIgGqBOjI9ZVsGxVm+Fzw0Um8PzRKDkns+eftOZ6QIR841MSt/yvgibdFjUUX9ldgBYNB2SKW8ixImF1cjSWgRv8AxDDbrqNWfJiElSUbgx0mL9i6WypvXuE0rKv+k8IE2e/Mzh9gShYGl/I2t4kNdig= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1679921106815647.1695059669314; Mon, 27 Mar 2023 05:45:06 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pgmCB-0008Ex-Uw; Mon, 27 Mar 2023 08:43:31 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pgmCA-0008EX-Dz for qemu-devel@nongnu.org; Mon, 27 Mar 2023 08:43:30 -0400 Received: from mail-oa1-x33.google.com ([2001:4860:4864:20::33]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pgmC8-0002r2-9J for qemu-devel@nongnu.org; Mon, 27 Mar 2023 08:43:30 -0400 Received: by mail-oa1-x33.google.com with SMTP id 586e51a60fabf-17aa62d0a4aso9094413fac.4 for ; Mon, 27 Mar 2023 05:43:27 -0700 (PDT) Received: from grind.. ([177.95.89.231]) by smtp.gmail.com with ESMTPSA id m206-20020acabcd7000000b0037d7f4eb7e8sm11136677oif.31.2023.03.27.05.43.24 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 27 Mar 2023 05:43:26 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1679921007; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=OSF/2nxdcwDZKN3dSMKYqw7KHIdYOdgDb/smyRYwUwQ=; b=WoAbOhTN+S2UgyzReQvmRLvhbIe+W+TX1lFiVV2D2xaRWD54czCRL9DBBTBFDNgcAc 6pOpIYu0A6RyKNtMzYZeSFkSFjDwqQcVqenIzJ+JUTM/gVLwplh9ZOH/Vprj6UDlacq8 +8fKy886oHB1FBmu+NYx6pvPoNP+aiFX2Cq/Pxq5zMsrdLcCiyIai05R+0QyfubSuT1Z RbMobxB3X20oLLnkmUHJE6tydJWvLPb/msJNr5OzDXrgawcVxSC71BP1eVBxYmkyrBYY jHI++uEI5rQAzOpLNUWwJ/gkydCtV47S44ddo5yzi/8wuh+KipiIstnTsIXc5qcGIlm+ FW/A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1679921007; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=OSF/2nxdcwDZKN3dSMKYqw7KHIdYOdgDb/smyRYwUwQ=; b=glt0/phJal+Lq4YWMyWPhm66AFmIoPvO02pF0dldmCYdH80+rpsTidGPgfvJeeQwhc DQj1fGrqyqCQE2HCAcEqvtkqIMcRWFz74m8z4h+sHJpyeK0hPKufooa2xt+c499hIDF4 t2a4ohORlOXhADznoUbn1VEpHfi43AiWwTIfSk4Aza2+Ju8N0y7NORlh+ERYTM7gozdl 4Ujn70bhjQMgAhRmNdKqX4hmDLhTGBf7dhlw1eCQy+p4/5yhD6vVTvUa8WdQ1pZhfoWO F2mJyCLBA4YD9AuhV5MoytSGpzqOv5v0k7mrs8ow7j5vQK3sWHPdLFoJJH6orAe05C0d eNOg== X-Gm-Message-State: AO0yUKWBc779AqrVIBMjQxekgozYgQ0fFJH9Y0E5vl2161/epTWk43RZ i5yZt/aFKC/GlUad7ORK9UM5tlnZTo5QGcUcges= X-Google-Smtp-Source: AKy350ZWTwYeYksgD/xVbvLsRm6fwvkcHg7uTeW8bqXY179cfdgbzx7pBCVjGDVVTYuG9eKmfkEX3Q== X-Received: by 2002:a05:6870:a454:b0:176:26b7:44b3 with SMTP id n20-20020a056870a45400b0017626b744b3mr8255958oal.36.1679921006846; Mon, 27 Mar 2023 05:43:26 -0700 (PDT) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, bmeng@tinylab.org, liweiwei@iscas.ac.cn, zhiwei_liu@linux.alibaba.com, palmer@rivosinc.com, Daniel Henrique Barboza Subject: [PATCH 11/19] target/riscv: remove cpu->cfg.ext_s Date: Mon, 27 Mar 2023 09:42:39 -0300 Message-Id: <20230327124247.106595-12-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230327124247.106595-1-dbarboza@ventanamicro.com> References: <20230327124247.106595-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2001:4860:4864:20::33; envelope-from=dbarboza@ventanamicro.com; helo=mail-oa1-x33.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ventanamicro.com) X-ZM-MESSAGEID: 1679921109080100003 Content-Type: text/plain; charset="utf-8" Create a new "s" RISCVCPUMisaExtConfig property that will update env->misa_ext* with RVS. Instances of cpu->cfg.ext_s and similar are replaced with riscv_has_ext(env, RVS). Remove the old "s" property and 'ext_s' from RISCVCPUConfig. Signed-off-by: Daniel Henrique Barboza --- target/riscv/cpu.c | 11 +++++------ target/riscv/cpu.h | 1 - 2 files changed, 5 insertions(+), 7 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 9f4d8fe7e8..d657ad2fcf 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -402,7 +402,6 @@ static void rv64_thead_c906_cpu_init(Object *obj) =20 cpu->cfg.ext_g =3D true; cpu->cfg.ext_u =3D true; - cpu->cfg.ext_s =3D true; cpu->cfg.ext_icsr =3D true; cpu->cfg.ext_zfh =3D true; cpu->cfg.mmu =3D true; @@ -837,7 +836,7 @@ static void riscv_cpu_validate_set_extensions(RISCVCPU = *cpu, Error **errp) return; } =20 - if (cpu->cfg.ext_s && !cpu->cfg.ext_u) { + if (riscv_has_ext(env, RVS) && !cpu->cfg.ext_u) { error_setg(errp, "Setting S extension without U extension is illegal"); return; @@ -849,7 +848,7 @@ static void riscv_cpu_validate_set_extensions(RISCVCPU = *cpu, Error **errp) return; } =20 - if (cpu->cfg.ext_h && !cpu->cfg.ext_s) { + if (cpu->cfg.ext_h && !riscv_has_ext(env, RVS)) { error_setg(errp, "H extension implicitly requires S-mode"); return; } @@ -1109,7 +1108,7 @@ static void riscv_cpu_sync_misa_cfg(CPURISCVState *en= v) if (riscv_has_ext(env, RVC)) { ext |=3D RVC; } - if (riscv_cpu_cfg(env)->ext_s) { + if (riscv_has_ext(env, RVS)) { ext |=3D RVS; } if (riscv_cpu_cfg(env)->ext_u) { @@ -1448,6 +1447,8 @@ static RISCVCPUMisaExtConfig misa_ext_cfgs[] =3D { .misa_bit =3D RVE, .enabled =3D false}, {.name =3D "m", .description =3D "Integer multiplication and division", .misa_bit =3D RVM, .enabled =3D true}, + {.name =3D "s", .description =3D "Supervisor-level instructions", + .misa_bit =3D RVS, .enabled =3D true}, }; =20 static void riscv_cpu_add_misa_properties(Object *cpu_obj) @@ -1471,7 +1472,6 @@ static void riscv_cpu_add_misa_properties(Object *cpu= _obj) static Property riscv_cpu_extensions[] =3D { /* Defaults for standard extensions */ DEFINE_PROP_BOOL("g", RISCVCPU, cfg.ext_g, false), - DEFINE_PROP_BOOL("s", RISCVCPU, cfg.ext_s, true), DEFINE_PROP_BOOL("u", RISCVCPU, cfg.ext_u, true), DEFINE_PROP_BOOL("v", RISCVCPU, cfg.ext_v, false), DEFINE_PROP_BOOL("h", RISCVCPU, cfg.ext_h, true), @@ -1579,7 +1579,6 @@ static void register_cpu_props(Object *obj) */ if (cpu->env.misa_ext !=3D 0) { cpu->cfg.ext_v =3D misa_ext & RVV; - cpu->cfg.ext_s =3D misa_ext & RVS; cpu->cfg.ext_u =3D misa_ext & RVU; cpu->cfg.ext_h =3D misa_ext & RVH; cpu->cfg.ext_j =3D misa_ext & RVJ; diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 7a42c80b7d..fc35aa7509 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -419,7 +419,6 @@ typedef struct { =20 struct RISCVCPUConfig { bool ext_g; - bool ext_s; bool ext_u; bool ext_h; bool ext_j; --=20 2.39.2 From nobody Thu May 2 00:48:52 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1679921113; cv=none; d=zohomail.com; s=zohoarc; b=F5R5HP+ef6iWYzV8qL2gm1JVm8CAZBDZgmdeJDIj+FT9HKGA+T5OkwdMODlnPpcVvdEvgW0OxGUIpeok3QYU7F9WQYRjcHrWbjth7Nb7RtasvgL0BOF+ga9T5yrBYTCCSpX7VqhL+Jwlsw6aLX5B7ykKubFg35Iuv6wAs0oa9Xw= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1679921113; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=CX5TUXO30u9OEj//bxH1SGp4tY23FdOQO1o2JzGdBug=; b=imxgHTJY2HqMVzqrTXYrPhVfIRjE9Cp3sOe8xpZtyXGEqpIBncBFQ1i4/MGH4tkkr0CG6DDWuic6vXjHTTz/WWkGm+fEyFZeAy+L3SFrBAd09/KzfjOaq7KPXWIMZ1U/YbTkKy4K55byeLGlnyQsRslKKFb5HF3MH4e0CPliLIw= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1679921113545975.5564851097428; Mon, 27 Mar 2023 05:45:13 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pgmCF-0008He-4T; Mon, 27 Mar 2023 08:43:35 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pgmCD-0008Fa-S4 for qemu-devel@nongnu.org; Mon, 27 Mar 2023 08:43:33 -0400 Received: from mail-oi1-x22f.google.com ([2607:f8b0:4864:20::22f]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pgmCB-0002tz-Ce for qemu-devel@nongnu.org; Mon, 27 Mar 2023 08:43:33 -0400 Received: by mail-oi1-x22f.google.com with SMTP id b19so6211086oib.7 for ; Mon, 27 Mar 2023 05:43:30 -0700 (PDT) Received: from grind.. ([177.95.89.231]) by smtp.gmail.com with ESMTPSA id m206-20020acabcd7000000b0037d7f4eb7e8sm11136677oif.31.2023.03.27.05.43.27 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 27 Mar 2023 05:43:29 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1679921010; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=CX5TUXO30u9OEj//bxH1SGp4tY23FdOQO1o2JzGdBug=; b=hZ4n8rXxxEcBJNxyPbUApQgnmve1IiQ+U0/9IaObHzghuLm2k1jn0nh4rDmv4Mk7QB hwZltFt4tRjU7YRm+S0VkRIToNfGldSW+0rEdXM9PQT5doIxZoBNFi2Ks2ABHfghPuBt BTj7F3jVKzyEIgkJKO1y1X/PnkmIfoDlIqgT8fG0KyfLPxnyNHqhxiqwkGAYnIi7bv7U jnZXmL303dZ1XVZubmtyanU4XhtuJUomSQ9gLm5ap5kl/eeR/P7X9bXajiIpkF/Ra2e3 DEACNUUHAURgAWmrtOo0KD1px2cQRe/ckRAWu14Lwh7SdrTRCxJAAKauJnQnqvuNhCQj UJng== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1679921010; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=CX5TUXO30u9OEj//bxH1SGp4tY23FdOQO1o2JzGdBug=; b=TzYFykYF0tioXt3S73i+ZiSv3x7lMUduPK/OWYVox/olimrbQ1Bj3pFtTigzj9X81p h9DalE/FFogrf2JmPelYsFV+dYkUAnbzBGIoSpyVQ/vWbNcX1P//05+m107MmC33U9FX eOQLdL5tiQvJDWeFewgL7RqQFV95J9gXxLnJqtBuujD2olejTSPy9SMy/3T6DQXlMMEr RSoA3ORtGE5CBIHEnAezzEux1q8i5b/tRwZglJp0b9+tvVNg2XmVg94b///qTIvVkaXg qHmyme3b8UM4gzNLxaK0vPprNLfZZBrpPZbxGhsWNWsMYhZEttW8aRgl+Ze9NNcsfQfI /JTg== X-Gm-Message-State: AO0yUKVy6jHNTNrj3pgyiSyzP0Jadb/YjADzMGnQWEzAcCGvcU5ummsE 6/vkpc7Wh48WPmEjmWk/+h1mIMbdmzvQut9iux0= X-Google-Smtp-Source: AK7set+JKkaszTFGpeQ7mTl1DYC5JLzEUC43UFUHNygtBasnCkLAcJ/5oBXDZx149I6V5ETBp7zfvg== X-Received: by 2002:a05:6808:192:b0:386:ca93:7ada with SMTP id w18-20020a056808019200b00386ca937adamr5174561oic.57.1679921009842; Mon, 27 Mar 2023 05:43:29 -0700 (PDT) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, bmeng@tinylab.org, liweiwei@iscas.ac.cn, zhiwei_liu@linux.alibaba.com, palmer@rivosinc.com, Daniel Henrique Barboza Subject: [PATCH 12/19] target/riscv: remove cpu->cfg.ext_u Date: Mon, 27 Mar 2023 09:42:40 -0300 Message-Id: <20230327124247.106595-13-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230327124247.106595-1-dbarboza@ventanamicro.com> References: <20230327124247.106595-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::22f; envelope-from=dbarboza@ventanamicro.com; helo=mail-oi1-x22f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ventanamicro.com) X-ZM-MESSAGEID: 1679921115029100003 Content-Type: text/plain; charset="utf-8" Create a new "u" RISCVCPUMisaExtConfig property that will update env->misa_ext* with RVU. Instances of cpu->cfg.ext_u and similar are replaced with riscv_has_ext(env, RVU). Remove the old "u" property and 'ext_u' from RISCVCPUConfig. Signed-off-by: Daniel Henrique Barboza --- target/riscv/cpu.c | 9 ++++----- target/riscv/cpu.h | 1 - 2 files changed, 4 insertions(+), 6 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index d657ad2fcf..12bc307992 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -401,7 +401,6 @@ static void rv64_thead_c906_cpu_init(Object *obj) set_priv_version(env, PRIV_VERSION_1_11_0); =20 cpu->cfg.ext_g =3D true; - cpu->cfg.ext_u =3D true; cpu->cfg.ext_icsr =3D true; cpu->cfg.ext_zfh =3D true; cpu->cfg.mmu =3D true; @@ -836,7 +835,7 @@ static void riscv_cpu_validate_set_extensions(RISCVCPU = *cpu, Error **errp) return; } =20 - if (riscv_has_ext(env, RVS) && !cpu->cfg.ext_u) { + if (riscv_has_ext(env, RVS) && !riscv_has_ext(env, RVU)) { error_setg(errp, "Setting S extension without U extension is illegal"); return; @@ -1111,7 +1110,7 @@ static void riscv_cpu_sync_misa_cfg(CPURISCVState *en= v) if (riscv_has_ext(env, RVS)) { ext |=3D RVS; } - if (riscv_cpu_cfg(env)->ext_u) { + if (riscv_has_ext(env, RVU)) { ext |=3D RVU; } if (riscv_cpu_cfg(env)->ext_h) { @@ -1449,6 +1448,8 @@ static RISCVCPUMisaExtConfig misa_ext_cfgs[] =3D { .misa_bit =3D RVM, .enabled =3D true}, {.name =3D "s", .description =3D "Supervisor-level instructions", .misa_bit =3D RVS, .enabled =3D true}, + {.name =3D "u", .description =3D "User-level instructions", + .misa_bit =3D RVU, .enabled =3D true}, }; =20 static void riscv_cpu_add_misa_properties(Object *cpu_obj) @@ -1472,7 +1473,6 @@ static void riscv_cpu_add_misa_properties(Object *cpu= _obj) static Property riscv_cpu_extensions[] =3D { /* Defaults for standard extensions */ DEFINE_PROP_BOOL("g", RISCVCPU, cfg.ext_g, false), - DEFINE_PROP_BOOL("u", RISCVCPU, cfg.ext_u, true), DEFINE_PROP_BOOL("v", RISCVCPU, cfg.ext_v, false), DEFINE_PROP_BOOL("h", RISCVCPU, cfg.ext_h, true), DEFINE_PROP_UINT8("pmu-num", RISCVCPU, cfg.pmu_num, 16), @@ -1579,7 +1579,6 @@ static void register_cpu_props(Object *obj) */ if (cpu->env.misa_ext !=3D 0) { cpu->cfg.ext_v =3D misa_ext & RVV; - cpu->cfg.ext_u =3D misa_ext & RVU; cpu->cfg.ext_h =3D misa_ext & RVH; cpu->cfg.ext_j =3D misa_ext & RVJ; =20 diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index fc35aa7509..7b98cf4dd7 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -419,7 +419,6 @@ typedef struct { =20 struct RISCVCPUConfig { bool ext_g; - bool ext_u; bool ext_h; bool ext_j; bool ext_v; --=20 2.39.2 From nobody Thu May 2 00:48:52 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1679921266; cv=none; d=zohomail.com; s=zohoarc; b=Afc1TEG5M+FLRWamcCIeJYGRmTObO2uiraofOSe0goh1neUXODe6lQLp2TH/EcgksyDj1iGH8MqoJVm58w5bMGRTxuImutP1wZZHEi6aug0ck/l421SLOurdm15+3ECNkXrrTKcnAXlVLCVhGWscEZFmyEJeHQPv1oBqbukZ6to= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1679921266; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=eYHD/dU5AEUk8d0p56l7hhWifzBU2kcS2dCrz8eKOb8=; b=Axw3maZDxif9hUPp8c0xHgAQGn80i1VzaJVhyGwwxepJ7OX4DTUYhjYbcisrCuOI6qm8kByKSFMCGgZYYvvAJX3TBULOKEzLZ0SSVNALCoqJCin2EC1iu2IV9VFLYcDmW57O7akgU0dNiJOO/Y6Mn/7QlIYtarwTXs3ieNeQbDo= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1679921266954538.0199431764212; Mon, 27 Mar 2023 05:47:46 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pgmCH-0008KW-HE; Mon, 27 Mar 2023 08:43:37 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pgmCF-0008I7-Bi for qemu-devel@nongnu.org; Mon, 27 Mar 2023 08:43:35 -0400 Received: from mail-oi1-x22c.google.com ([2607:f8b0:4864:20::22c]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pgmCD-0001wg-O6 for qemu-devel@nongnu.org; Mon, 27 Mar 2023 08:43:35 -0400 Received: by mail-oi1-x22c.google.com with SMTP id r84so4930046oih.11 for ; Mon, 27 Mar 2023 05:43:33 -0700 (PDT) Received: from grind.. ([177.95.89.231]) by smtp.gmail.com with ESMTPSA id m206-20020acabcd7000000b0037d7f4eb7e8sm11136677oif.31.2023.03.27.05.43.30 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 27 Mar 2023 05:43:32 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1679921012; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=eYHD/dU5AEUk8d0p56l7hhWifzBU2kcS2dCrz8eKOb8=; b=L8fCM2LpIplfj5ar3fE7Z0XRcsxveE2M08XZxSFhNzfB7BZLI1q4UOm9u6ydgv3F48 SDZLsHpXpFI4ECtZNPAsoWCbZf+/cLl3cQATFj8xaXiZvEyr2jVlFdDpg9e5PtMDt0yu +9xTs9d7DqZ3ej6dVviyQBEsEa+B78N9a5H9SnbOc+MK6OwyEaPZOPk/AMUphoTI9FXb ggOj7P8CyrB6sWmvbfPqbE8Q1IcoicHKNEFZIoatvioHcfEUAUS/7KpvGyTbNXpB4Jp7 qIf51P/xpaIHUP5gu7rn/j6Fec7aUiplcUl6l5KxAqyhrsjZVPUDJWNTy57YnjfAvHuj B3bA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1679921012; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=eYHD/dU5AEUk8d0p56l7hhWifzBU2kcS2dCrz8eKOb8=; b=yt9HZJKZm0Nfu5Xv1QvcvfAV599VD2XppqKW+RlilUEqjQIIiqbIto4vL+d9m0Ifuy tz6GHbmIOj0ynd/p+RyZphMnyn949Mw5IiyYZFVGJiOmb8cVId8Bw+Pe2hHhL5pwbrHr na0X0tMTajZYixi72nn+lugQuS0IiAGf0XIidk6o15d4EoCwQAhfJgOzwLvqts4Y4wlk qCbmEYwln5c/V0Y16dXuFIjZLHBONDkCPnXPl1Feze1TE8rayP4RpmU/m8DuHHZT+rkm xnQhC2TWVkf3AKqWBwYWUZw6l0jQ7L+tcHi/JV5SyIdWnK1Z2vfFFMaW4o8An0UEzyhN kMTg== X-Gm-Message-State: AO0yUKVxA2sysK6ERK56Q7XkvWAAyQvfAieKioM8s64w3sQsW4+IEZYF 0zPuqUdIlZRYURgZ8PlbzHDoLKu+vM/DCIrP7wM= X-Google-Smtp-Source: AK7set9oLtHrFh4hgkLAawIG82p2aPG6gd0fQqGvne90tVb1hADDUNmN5qW7+AXC81U3M4TxbKoskA== X-Received: by 2002:a05:6808:394a:b0:383:d1e3:38f9 with SMTP id en10-20020a056808394a00b00383d1e338f9mr5362562oib.16.1679921012788; Mon, 27 Mar 2023 05:43:32 -0700 (PDT) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, bmeng@tinylab.org, liweiwei@iscas.ac.cn, zhiwei_liu@linux.alibaba.com, palmer@rivosinc.com, Daniel Henrique Barboza Subject: [PATCH 13/19] target/riscv: remove cpu->cfg.ext_h Date: Mon, 27 Mar 2023 09:42:41 -0300 Message-Id: <20230327124247.106595-14-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230327124247.106595-1-dbarboza@ventanamicro.com> References: <20230327124247.106595-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::22c; envelope-from=dbarboza@ventanamicro.com; helo=mail-oi1-x22c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ventanamicro.com) X-ZM-MESSAGEID: 1679921267850100003 Content-Type: text/plain; charset="utf-8" Create a new "h" RISCVCPUMisaExtConfig property that will update env->misa_ext* with RVH. Instances of cpu->cfg.ext_h and similar are replaced with riscv_has_ext(env, RVH). Remove the old "h" property and 'ext_h' from RISCVCPUConfig. Signed-off-by: Daniel Henrique Barboza --- target/riscv/cpu.c | 10 +++++----- target/riscv/cpu.h | 1 - 2 files changed, 5 insertions(+), 6 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 12bc307992..90c8fc0f30 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -841,13 +841,13 @@ static void riscv_cpu_validate_set_extensions(RISCVCP= U *cpu, Error **errp) return; } =20 - if (cpu->cfg.ext_h && !riscv_has_ext(env, RVI)) { + if (riscv_has_ext(env, RVH) && !riscv_has_ext(env, RVI)) { error_setg(errp, "H depends on an I base integer ISA with 32 x registers= "); return; } =20 - if (cpu->cfg.ext_h && !riscv_has_ext(env, RVS)) { + if (riscv_has_ext(env, RVH) && !riscv_has_ext(env, RVS)) { error_setg(errp, "H extension implicitly requires S-mode"); return; } @@ -1113,7 +1113,7 @@ static void riscv_cpu_sync_misa_cfg(CPURISCVState *en= v) if (riscv_has_ext(env, RVU)) { ext |=3D RVU; } - if (riscv_cpu_cfg(env)->ext_h) { + if (riscv_has_ext(env, RVH)) { ext |=3D RVH; } if (riscv_cpu_cfg(env)->ext_v) { @@ -1450,6 +1450,8 @@ static RISCVCPUMisaExtConfig misa_ext_cfgs[] =3D { .misa_bit =3D RVS, .enabled =3D true}, {.name =3D "u", .description =3D "User-level instructions", .misa_bit =3D RVU, .enabled =3D true}, + {.name =3D "h", .description =3D "Hypervisor", + .misa_bit =3D RVH, .enabled =3D true}, }; =20 static void riscv_cpu_add_misa_properties(Object *cpu_obj) @@ -1474,7 +1476,6 @@ static Property riscv_cpu_extensions[] =3D { /* Defaults for standard extensions */ DEFINE_PROP_BOOL("g", RISCVCPU, cfg.ext_g, false), DEFINE_PROP_BOOL("v", RISCVCPU, cfg.ext_v, false), - DEFINE_PROP_BOOL("h", RISCVCPU, cfg.ext_h, true), DEFINE_PROP_UINT8("pmu-num", RISCVCPU, cfg.pmu_num, 16), DEFINE_PROP_BOOL("sscofpmf", RISCVCPU, cfg.ext_sscofpmf, false), DEFINE_PROP_BOOL("Zifencei", RISCVCPU, cfg.ext_ifencei, true), @@ -1579,7 +1580,6 @@ static void register_cpu_props(Object *obj) */ if (cpu->env.misa_ext !=3D 0) { cpu->cfg.ext_v =3D misa_ext & RVV; - cpu->cfg.ext_h =3D misa_ext & RVH; cpu->cfg.ext_j =3D misa_ext & RVJ; =20 /* diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 7b98cf4dd7..f3cb28443c 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -419,7 +419,6 @@ typedef struct { =20 struct RISCVCPUConfig { bool ext_g; - bool ext_h; bool ext_j; bool ext_v; bool ext_zba; --=20 2.39.2 From nobody Thu May 2 00:48:52 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1679921092; cv=none; d=zohomail.com; s=zohoarc; b=VHMseEzGA8UaD5kMjas3THvIpouCmh/i0D6B7WnnZF0n+rokWvTro1O2YhEvJOa5SpwASwrO6W955N9c8UnbmfYIFBcu4H88lL48mbJS/MO23msrpmNmw9T4AdlZ2s8kp8oZy8hnWf3sIe+TTsRqe2ZFp0FiLxwAS4hR00EN470= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1679921092; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=vq/xPb0BGeP1/p/eR3juVD9psMw0Nrkru0VCkDWX58s=; b=VoX+b+No6RxlVTg0zlSxlAYqn6UP1AYBcqVqBhaeX+wSYOpySK1o6rXNOTOIdZWghWLBOvEThopgzgmWI/nQu1Cs4PjI1oMpMN63RWVXKPCheDrJpDRx0FSHvxcC1mTzAsrSL0HeCCBO7mnJmc02iSWGQNW5YJkEhLBJ9KmFVF0= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1679921092648156.65908518431706; Mon, 27 Mar 2023 05:44:52 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pgmCK-0008Mt-OI; Mon, 27 Mar 2023 08:43:40 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pgmCI-0008LC-72 for qemu-devel@nongnu.org; Mon, 27 Mar 2023 08:43:38 -0400 Received: from mail-oi1-x22b.google.com ([2607:f8b0:4864:20::22b]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pgmCG-00020r-Of for qemu-devel@nongnu.org; Mon, 27 Mar 2023 08:43:37 -0400 Received: by mail-oi1-x22b.google.com with SMTP id bj20so6220433oib.3 for ; Mon, 27 Mar 2023 05:43:36 -0700 (PDT) Received: from grind.. ([177.95.89.231]) by smtp.gmail.com with ESMTPSA id m206-20020acabcd7000000b0037d7f4eb7e8sm11136677oif.31.2023.03.27.05.43.33 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 27 Mar 2023 05:43:35 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1679921016; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=vq/xPb0BGeP1/p/eR3juVD9psMw0Nrkru0VCkDWX58s=; b=jTw0gjjND1X6zfG7n0gpjNNFy3qrBWePEDlRdONiDJZWXGYm0g3LPKsY482kd/3Kwx Lk4TVWWmxOcAanv2t0S7eaBxi1VTU5scejcTQCbqnnKikD2XyXYTfZSjBW+sR6DB/7Cp q3fbiXPtu067qdnqEA1eWRvSIqS+l+RYsj9JuDDThDiIMPmnv3hw+l2VyZEXa/ygmYj7 nKyMXuY87oqlNCQW0KTOep09v2c19PdpQ8CT7JRgnEZvK7PpTs1QXZ/Vv/R6fqXQ6d8y 18ghHmoCDsERB374ll9CgkYIg3M+/pILRZFkVDVg2n7KTIueXJnohxiMa/xwUySbxq5N EfWQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1679921016; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=vq/xPb0BGeP1/p/eR3juVD9psMw0Nrkru0VCkDWX58s=; b=SsEfRwYKpR9KM5mi0qOFFELX5YSXobvkR608exonEhEDez9W7p5uCqCxw1VgQR49XK 4cms+iKcFh+bXGSxsEuNUZcLUDXbD9RdjYKPQElMsVnb73uzDeecnENkutlK4VMC9bXE I0etoLHVjlI/ObBjCd+45pnNDLYbzDjNgt4VCr0F3s2kTGMN7aECzJTeP2Q96nekCCxm Yim2Q/0mwF2Bv+FchkdsVEiDH+woVjzNfrzJZohI0LqMuKowMnHJ1Cs+VkuIsETeEj9s gusM9jrbp9mzUH/omBFGfhy6VBrYS4wKNIDJlZuIUZVFwKRTlMJ/0zi3Yfp7xOcIfJkS 280Q== X-Gm-Message-State: AO0yUKVwrk9+rLHm8M7RYMi3IJ51JGc4V/5KKOd6DHumelVLjVNBmdnU wYsM6Sn+4CtGpvcwJKaIYEd/1Gft/63S90a1jmw= X-Google-Smtp-Source: AK7set+U4qZi37wu0JYoMcUXcUnl//i8lYCMCxKWtUlLTXDNGFFb7OG62qlY4OJBBB/QVi3fXdG3gQ== X-Received: by 2002:aca:f01:0:b0:384:2b1d:45a with SMTP id 1-20020aca0f01000000b003842b1d045amr4626846oip.30.1679921015727; Mon, 27 Mar 2023 05:43:35 -0700 (PDT) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, bmeng@tinylab.org, liweiwei@iscas.ac.cn, zhiwei_liu@linux.alibaba.com, palmer@rivosinc.com, Daniel Henrique Barboza Subject: [PATCH 14/19] target/riscv: remove cpu->cfg.ext_j Date: Mon, 27 Mar 2023 09:42:42 -0300 Message-Id: <20230327124247.106595-15-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230327124247.106595-1-dbarboza@ventanamicro.com> References: <20230327124247.106595-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::22b; envelope-from=dbarboza@ventanamicro.com; helo=mail-oi1-x22b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ventanamicro.com) X-ZM-MESSAGEID: 1679921094952100003 Content-Type: text/plain; charset="utf-8" Create a new "j" RISCVCPUMisaExtConfig property that will update env->misa_ext* with RVJ. Instances of cpu->cfg.ext_j and similar are replaced with riscv_has_ext(env, RVJ). Remove the old "j" property and 'ext_j' from RISCVCPUConfig. Signed-off-by: Daniel Henrique Barboza --- target/riscv/cpu.c | 6 +++--- target/riscv/cpu.h | 1 - 2 files changed, 3 insertions(+), 4 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 90c8fc0f30..8589f7bd67 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -1119,7 +1119,7 @@ static void riscv_cpu_sync_misa_cfg(CPURISCVState *en= v) if (riscv_cpu_cfg(env)->ext_v) { ext |=3D RVV; } - if (riscv_cpu_cfg(env)->ext_j) { + if (riscv_has_ext(env, RVJ)) { ext |=3D RVJ; } =20 @@ -1452,6 +1452,8 @@ static RISCVCPUMisaExtConfig misa_ext_cfgs[] =3D { .misa_bit =3D RVU, .enabled =3D true}, {.name =3D "h", .description =3D "Hypervisor", .misa_bit =3D RVH, .enabled =3D true}, + {.name =3D "x-j", .description =3D "Dynamic translated languages", + .misa_bit =3D RVJ, .enabled =3D false}, }; =20 static void riscv_cpu_add_misa_properties(Object *cpu_obj) @@ -1548,7 +1550,6 @@ static Property riscv_cpu_extensions[] =3D { =20 /* These are experimental so mark with 'x-' */ DEFINE_PROP_BOOL("x-zicond", RISCVCPU, cfg.ext_zicond, false), - DEFINE_PROP_BOOL("x-j", RISCVCPU, cfg.ext_j, false), /* ePMP 0.9.3 */ DEFINE_PROP_BOOL("x-epmp", RISCVCPU, cfg.epmp, false), DEFINE_PROP_BOOL("x-smaia", RISCVCPU, cfg.ext_smaia, false), @@ -1580,7 +1581,6 @@ static void register_cpu_props(Object *obj) */ if (cpu->env.misa_ext !=3D 0) { cpu->cfg.ext_v =3D misa_ext & RVV; - cpu->cfg.ext_j =3D misa_ext & RVJ; =20 /* * We don't want to set the default riscv_cpu_extensions diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index f3cb28443c..43a40ba950 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -419,7 +419,6 @@ typedef struct { =20 struct RISCVCPUConfig { bool ext_g; - bool ext_j; bool ext_v; bool ext_zba; bool ext_zbb; --=20 2.39.2 From nobody Thu May 2 00:48:52 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1679921100; cv=none; d=zohomail.com; s=zohoarc; b=fTIh0ZRZj3R797nLmSBMokQRnatM/YLW086jL3neUmmIYtlsJO/CPUJDANN3H0IqAp8AwQIukTv36ItTx6cbFO+GL+vvcLC6QgUEY1tR8FaoDXvdZOs232FNxXbOlOw3ic/5I9RM8TbJBlgN2/DXF+6q75N0pnS/4WkS6BsqVbg= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1679921100; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=qZo0zuFzW/6E8wzP0x1oyPEKFDfqPNS1VIiCzvKskPk=; b=ek0dDrlku3j8mxWj6MKWROL6mlo7FLlNeXrhRUv2IdbZ5RwuyxQZyiw5oIWKp+xOo7kydaNzsDPYTTXYI3MTDisDDdsA7acj2WgBj4y6NthYiG1FvTPMHP8j1AGLzRIonRjBDRCeQ9OMrVp2XIwA/9Pe6UhUqFsWGjGf1VmkwQU= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1679921100103142.43545190911323; Mon, 27 Mar 2023 05:45:00 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pgmCN-00008x-62; Mon, 27 Mar 2023 08:43:43 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pgmCM-0008S0-0L for qemu-devel@nongnu.org; Mon, 27 Mar 2023 08:43:42 -0400 Received: from mail-oi1-x22c.google.com ([2607:f8b0:4864:20::22c]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pgmCJ-0001wg-Pa for qemu-devel@nongnu.org; Mon, 27 Mar 2023 08:43:41 -0400 Received: by mail-oi1-x22c.google.com with SMTP id r84so4930252oih.11 for ; Mon, 27 Mar 2023 05:43:39 -0700 (PDT) Received: from grind.. ([177.95.89.231]) by smtp.gmail.com with ESMTPSA id m206-20020acabcd7000000b0037d7f4eb7e8sm11136677oif.31.2023.03.27.05.43.36 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 27 Mar 2023 05:43:38 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1679921019; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=qZo0zuFzW/6E8wzP0x1oyPEKFDfqPNS1VIiCzvKskPk=; b=USpLm4jq3DluAsXshcuQ/jYt5XznmrZxEHMtT4BZ4TFu6SH+UwM/VUQiTWmmVhrXUn j2ruiMBi6nqdg7FJTP+celR/RsAJ3jSqTH6i3bxZNq1/8J4KajhXAnzZ63UZ/RavEQei xwRk9TC43fNBq9EEi1NXaxwgNRN/08cfNu7dWIWg8H1R9Wl8/2iks8c9UgNgZbPZiZ88 ka+H+gXITPF02nanfbe3dyaa1LzlQgUFZy9goGNU66yQRpfvPKZhrUBSnn70P++pSPuj BEU3eJqktE/vavkBDkLDbb0NJtA2Ht1UJDO2xUvJ7Ojv3phW975dxMG7AzQg3WmsNvVO XsKA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1679921019; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=qZo0zuFzW/6E8wzP0x1oyPEKFDfqPNS1VIiCzvKskPk=; b=xAeXNKEknkfDZUzyGSAEAQbhQLT6AkEt6kmSynWcV4fVeGb/rojFP+4w8JBg055Q3e TmnfY4zFjiwHKPZF4jdIAvuDJ9kid5OQ5Zd9CisFTyr4Cpzf+AQFQWWswPeSXA1Z4nez aQwmmTMX7G3gWfv/140qFMHPL9DGmSR0LVt266hKaQvn7vK6kcd/Kfd1D/VXSI8LyzQX Dde8NqxjRepJzxj5ccnOciwhBvG0YnH6WAtMOC61FzUXJf+r0+BTcMynWWdq7LVKk3vi PYTwXIBOxejM+XnSgyZX4fkGgdeyentMUVcX5TOiwbGp/EPLAf3OxPfjuOUNfwQY67fU hbfA== X-Gm-Message-State: AO0yUKW/d/1fsGkdhpARP8BA4w+b67w6PHBHrrIjnLIoVMV07uFaJ4KT U9jLejfAB97Ro9WOD0nR5JJsMW3N7IeCmPW2oDw= X-Google-Smtp-Source: AK7set+dAcWpWbVd0Wd6yGB+6JiwIX1/9Oj0KvbdNmqNjpZMW6ORyDeRRBcdCnFoden2bVWXgwG00A== X-Received: by 2002:aca:2217:0:b0:387:6a3b:5a86 with SMTP id b23-20020aca2217000000b003876a3b5a86mr4865070oic.28.1679921018837; Mon, 27 Mar 2023 05:43:38 -0700 (PDT) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, bmeng@tinylab.org, liweiwei@iscas.ac.cn, zhiwei_liu@linux.alibaba.com, palmer@rivosinc.com, Daniel Henrique Barboza Subject: [PATCH 15/19] target/riscv: remove cpu->cfg.ext_v Date: Mon, 27 Mar 2023 09:42:43 -0300 Message-Id: <20230327124247.106595-16-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230327124247.106595-1-dbarboza@ventanamicro.com> References: <20230327124247.106595-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::22c; envelope-from=dbarboza@ventanamicro.com; helo=mail-oi1-x22c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ventanamicro.com) X-ZM-MESSAGEID: 1679921101166100003 Content-Type: text/plain; charset="utf-8" Create a new "v" RISCVCPUMisaExtConfig property that will update env->misa_ext* with RVV. Instances of cpu->cfg.ext_v and similar are replaced with riscv_has_ext(env, RVV). Remove the old "v" property and 'ext_v' from RISCVCPUConfig. Signed-off-by: Daniel Henrique Barboza --- target/riscv/cpu.c | 12 +++++------- target/riscv/cpu.h | 1 - 2 files changed, 5 insertions(+), 8 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 8589f7bd67..025d1f6258 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -877,7 +877,7 @@ static void riscv_cpu_validate_set_extensions(RISCVCPU = *cpu, Error **errp) } =20 /* The V vector extension depends on the Zve64d extension */ - if (cpu->cfg.ext_v) { + if (riscv_has_ext(env, RVV)) { cpu->cfg.ext_zve64d =3D true; } =20 @@ -959,7 +959,7 @@ static void riscv_cpu_validate_set_extensions(RISCVCPU = *cpu, Error **errp) cpu->cfg.ext_zksh =3D true; } =20 - if (cpu->cfg.ext_v) { + if (riscv_has_ext(env, RVV)) { int vext_version =3D VEXT_VERSION_1_00_0; if (!is_power_of_2(cpu->cfg.vlen)) { error_setg(errp, @@ -1116,7 +1116,7 @@ static void riscv_cpu_sync_misa_cfg(CPURISCVState *en= v) if (riscv_has_ext(env, RVH)) { ext |=3D RVH; } - if (riscv_cpu_cfg(env)->ext_v) { + if (riscv_has_ext(env, RVV)) { ext |=3D RVV; } if (riscv_has_ext(env, RVJ)) { @@ -1454,6 +1454,8 @@ static RISCVCPUMisaExtConfig misa_ext_cfgs[] =3D { .misa_bit =3D RVH, .enabled =3D true}, {.name =3D "x-j", .description =3D "Dynamic translated languages", .misa_bit =3D RVJ, .enabled =3D false}, + {.name =3D "v", .description =3D "Vector operations", + .misa_bit =3D RVV, .enabled =3D false}, }; =20 static void riscv_cpu_add_misa_properties(Object *cpu_obj) @@ -1477,7 +1479,6 @@ static void riscv_cpu_add_misa_properties(Object *cpu= _obj) static Property riscv_cpu_extensions[] =3D { /* Defaults for standard extensions */ DEFINE_PROP_BOOL("g", RISCVCPU, cfg.ext_g, false), - DEFINE_PROP_BOOL("v", RISCVCPU, cfg.ext_v, false), DEFINE_PROP_UINT8("pmu-num", RISCVCPU, cfg.pmu_num, 16), DEFINE_PROP_BOOL("sscofpmf", RISCVCPU, cfg.ext_sscofpmf, false), DEFINE_PROP_BOOL("Zifencei", RISCVCPU, cfg.ext_ifencei, true), @@ -1570,7 +1571,6 @@ static Property riscv_cpu_extensions[] =3D { static void register_cpu_props(Object *obj) { RISCVCPU *cpu =3D RISCV_CPU(obj); - uint32_t misa_ext =3D cpu->env.misa_ext; Property *prop; DeviceState *dev =3D DEVICE(obj); =20 @@ -1580,8 +1580,6 @@ static void register_cpu_props(Object *obj) * later on. */ if (cpu->env.misa_ext !=3D 0) { - cpu->cfg.ext_v =3D misa_ext & RVV; - /* * We don't want to set the default riscv_cpu_extensions * in this case. diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 43a40ba950..c0280ace2a 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -419,7 +419,6 @@ typedef struct { =20 struct RISCVCPUConfig { bool ext_g; - bool ext_v; bool ext_zba; bool ext_zbb; bool ext_zbc; --=20 2.39.2 From nobody Thu May 2 00:48:52 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1679921166; cv=none; d=zohomail.com; s=zohoarc; b=Ksi8aoZzqPvJHAn9aVbcad8mgk/aYPLNsZG8MHTURxTtOKXWage30g5QIyQqWNLPnkpekO68UvtQ8SvMEPymGKVrSt3YtkQji8ah1WQnvTWMOPJyAsMKf6xkTDI15BbahxOvD1quhAF0i0Cb5AHqIpjKy06gsUTb56brIksgxAM= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1679921166; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=q2VVvJozrKwcizVRNwPco566fLw5fVqjzs3N7kh8V3g=; b=d1xFcfFyzGNxxWIrnuwiiYeMo2h01JSrJ6kgPS36GAjQRRnoy3GV+rBi+B/V9R4XxWaZeHqYOrTpN8XCYAkSPvHpQb/gFtymD8K4YEOuGXwd0ZlGKHoxRz/TtbBc+HjLIxRvISMERy4sT+yw+nNaMIxj51ODdVZHFQGEKPgewws= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 167992116664058.018847394547265; Mon, 27 Mar 2023 05:46:06 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pgmCR-0000Yi-1F; Mon, 27 Mar 2023 08:43:48 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pgmCO-0000Kt-V5 for qemu-devel@nongnu.org; Mon, 27 Mar 2023 08:43:44 -0400 Received: from mail-oa1-x36.google.com ([2001:4860:4864:20::36]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pgmCN-00039y-5n for qemu-devel@nongnu.org; Mon, 27 Mar 2023 08:43:44 -0400 Received: by mail-oa1-x36.google.com with SMTP id 586e51a60fabf-177ca271cb8so9109549fac.2 for ; Mon, 27 Mar 2023 05:43:42 -0700 (PDT) Received: from grind.. ([177.95.89.231]) by smtp.gmail.com with ESMTPSA id m206-20020acabcd7000000b0037d7f4eb7e8sm11136677oif.31.2023.03.27.05.43.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 27 Mar 2023 05:43:41 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1679921021; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=q2VVvJozrKwcizVRNwPco566fLw5fVqjzs3N7kh8V3g=; b=CkW7BwzzGNMGTC6g/6jcFkdG1E4AWQeuRvJokYQvT8O/SAYxbW3Oyf6c23+Jj/DxpJ 02F7aluPoWWxviIIFjtpZhQx2NFJCLe8j55k/JD2RiZHwDrfPqnIVkOWpqR6NNi10LNG nJWgl4niUaekxDBwHSBHguFzojU5jP45nSBT/QMZhwiTml7de4TmmYvI8cbSbDfHMHuy TdXTJYMC7lQcEeZ90YPhfCODXVIA8bRQuUaMcIqlSbDSaSYabpdDMIaFhgNTl5El3eZe iNogn1U+yLMLwqkd2U0A4lfpyW1CXpjC03+cjLiqHde7Rtgzxg17jbCYYa32rMOsEoPR hPew== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1679921021; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=q2VVvJozrKwcizVRNwPco566fLw5fVqjzs3N7kh8V3g=; b=kgW7fTAW6/F4wrnfbPq5gKpBQ7OxfPG4U3LkV+hcuRbfCmGElBUNTAmngbPGzcOrDa DIVmGidToyDFxDVvX43iyeb8Y8qO9Ra47OYHHbo7g4jjhka5rIDP7h4tK60RtMO5qM4l 1Ln26EHnG4I75zN3oKAwhH8uXiKo6lRhsp0cyO4hHk4S9Xlm7kQZu3FkTDImMHHXniTX sc53AaV8x7iq4KfkefJG5stQt5K+tDDZm2e+REjNjNcsrCZC/BRP7IFYvIRVZkfayZ/R QdYEW8nknTCF6gEYQY3G7JTMKq549upYhH1vS/+VXri2wygyHWkmZUW68xJFMlrWrQeB 0ETg== X-Gm-Message-State: AAQBX9eKmJvsakGVoJEhdsUFd01b9KeOQve2WYAR9FuIW6i3zs+hirtH /6HaJgC1pOoJxqclf1I0FTLYrIo6nBQ8StzT++w= X-Google-Smtp-Source: AK7set8zWmeqOvAFlpY5Z13XlbNsh8PRfEbtDmWnC1W2db+8xpl+7S9FofuMtsdEPLkvmVH7u7ZrXQ== X-Received: by 2002:a05:6870:e40d:b0:169:dcba:1ec9 with SMTP id n13-20020a056870e40d00b00169dcba1ec9mr8666586oag.41.1679921021761; Mon, 27 Mar 2023 05:43:41 -0700 (PDT) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, bmeng@tinylab.org, liweiwei@iscas.ac.cn, zhiwei_liu@linux.alibaba.com, palmer@rivosinc.com, Daniel Henrique Barboza Subject: [PATCH 16/19] target/riscv: remove riscv_cpu_sync_misa_cfg() Date: Mon, 27 Mar 2023 09:42:44 -0300 Message-Id: <20230327124247.106595-17-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230327124247.106595-1-dbarboza@ventanamicro.com> References: <20230327124247.106595-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2001:4860:4864:20::36; envelope-from=dbarboza@ventanamicro.com; helo=mail-oa1-x36.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ventanamicro.com) X-ZM-MESSAGEID: 1679921167415100001 Content-Type: text/plain; charset="utf-8" This function was created to move the sync between cpu->cfg.ext_N bit changes to env->misa_ext* from the validation step to an ealier step, giving us a guarantee that we could use either cpu->cfg.ext_N or riscv_has_ext(env,N) in the validation. We don't have any cpu->cfg.ext_N left that has an existing MISA bit (cfg.ext_g will be handled shortly). The function is now a no-op, simply copying the existing values of misa_ext* back to misa_ext*. Remove it. Signed-off-by: Daniel Henrique Barboza --- target/riscv/cpu.c | 52 ---------------------------------------------- 1 file changed, 52 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 025d1f6258..81c8e0d541 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -1082,50 +1082,6 @@ static void riscv_cpu_finalize_features(RISCVCPU *cp= u, Error **errp) #endif } =20 -static void riscv_cpu_sync_misa_cfg(CPURISCVState *env) -{ - uint32_t ext =3D 0; - - if (riscv_has_ext(env, RVI)) { - ext |=3D RVI; - } - if (riscv_has_ext(env, RVE)) { - ext |=3D RVE; - } - if (riscv_has_ext(env, RVM)) { - ext |=3D RVM; - } - if (riscv_has_ext(env, RVA)) { - ext |=3D RVA; - } - if (riscv_has_ext(env, RVF)) { - ext |=3D RVF; - } - if (riscv_has_ext(env, RVD)) { - ext |=3D RVD; - } - if (riscv_has_ext(env, RVC)) { - ext |=3D RVC; - } - if (riscv_has_ext(env, RVS)) { - ext |=3D RVS; - } - if (riscv_has_ext(env, RVU)) { - ext |=3D RVU; - } - if (riscv_has_ext(env, RVH)) { - ext |=3D RVH; - } - if (riscv_has_ext(env, RVV)) { - ext |=3D RVV; - } - if (riscv_has_ext(env, RVJ)) { - ext |=3D RVJ; - } - - env->misa_ext =3D env->misa_ext_mask =3D ext; -} - static void riscv_cpu_validate_misa_priv(CPURISCVState *env, Error **errp) { if (riscv_has_ext(env, RVH) && env->priv_ver < PRIV_VERSION_1_12_0) { @@ -1169,14 +1125,6 @@ static void riscv_cpu_realize(DeviceState *dev, Erro= r **errp) set_priv_version(env, priv_version); } =20 - /* - * We can't be sure of whether we set defaults during cpu_init() - * or whether the user enabled/disabled some bits via cpu->cfg - * flags. Sync env->misa_ext with cpu->cfg now to allow us to - * use just env->misa_ext later. - */ - riscv_cpu_sync_misa_cfg(env); - riscv_cpu_validate_misa_priv(env, &local_err); if (local_err !=3D NULL) { error_propagate(errp, local_err); --=20 2.39.2 From nobody Thu May 2 00:48:52 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1679921149; cv=none; d=zohomail.com; s=zohoarc; b=a820QABW7goIhqTJtG3JwJaw98BsuJfUpnxuvcnoxUXQRpG5CCLa2lSo9gDN1ZQt9chS0JP9UoGjSPPQWEQBO0pMz4RPpcV03H3LCphoGGkfSCZrdhQCsC33rk7/HQIyV9iyXTyOIf0osEUiI+BXPm4mYv/28cW1AJHh5Jo98ww= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1679921149; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=ynbViB4clOt5B5SrVJqlPDKEgBdFVdkLq8E38RQB1tA=; b=dB1QoJG7eIKZohdfG9wX+QY4ueim2ZTErSEouGk/n2e+sM2KpH2v9Qp2VTn7HaLdGjagL/nkWmR2x5qO4/EtcIBaIHdZVYO2zOOjHkHxy1SraWL3Yew3cvy3iY/qU6zHY0XbaoptXsfAA1tGuIPmJzevsUb731XzLpJL1bAZlIk= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1679921149720146.96513883070077; Mon, 27 Mar 2023 05:45:49 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pgmCW-0000ix-4b; Mon, 27 Mar 2023 08:43:52 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pgmCR-0000ZW-FZ for qemu-devel@nongnu.org; Mon, 27 Mar 2023 08:43:48 -0400 Received: from mail-oi1-x22c.google.com ([2607:f8b0:4864:20::22c]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pgmCP-00020I-ST for qemu-devel@nongnu.org; Mon, 27 Mar 2023 08:43:47 -0400 Received: by mail-oi1-x22c.google.com with SMTP id y184so6209630oiy.8 for ; Mon, 27 Mar 2023 05:43:45 -0700 (PDT) Received: from grind.. ([177.95.89.231]) by smtp.gmail.com with ESMTPSA id m206-20020acabcd7000000b0037d7f4eb7e8sm11136677oif.31.2023.03.27.05.43.42 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 27 Mar 2023 05:43:44 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1679921024; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=ynbViB4clOt5B5SrVJqlPDKEgBdFVdkLq8E38RQB1tA=; b=J8NrbPVOW3qHk2oUxVoGvj0RAFfV29rt1ABASllRE3GvSgFNDHV8aNuGcPxf9UO603 iffpA54xSj8bXx2xVy2b/Bpt1cRa0LdVW5h7TCJ8AiW2qWdth6i0v/zDv4mS7DkSh4wV xQqrkGQKbpM5CJjw7TVVkS3RNcOeIgDTO9c7NSelYO17YXqt0wYhGA0Z5572TO3UHlee vgiBu1SwPjD/McZeRcVygfJnit9AK0BSnnYxb5xYTOPIvW3h/Hg1kbUYxqS7rktKWlEv VWBaRM3uNJ50jr7R//VEU7EuaRb7xWNSOL11hs95aD7+yPuUvJul59dZNEWrA/Alvqaw Erlg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1679921024; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=ynbViB4clOt5B5SrVJqlPDKEgBdFVdkLq8E38RQB1tA=; b=x2OlL6LHlbxuoN3QHmGhGNUz+hrN6P7y7+EzjUju6L2iNt5goKzMkcVhkA4/ds7tiJ taxNg8eIm1Uqh/2N1AemjVg11FbjTT86hErgcnyZvMvdTJPqarwy0lL7biSipJZlrJ8r nBocqf4fIjL0oSzz+FvHqOfDzMUxleYGn0HHa8PFT0UOGSxNq2lWAowLF0CZeaG+rjNn qrE+LVIvJbrf1LA64NIQP4cN6zj1lrort/3PvAB7ZeVcTgEV1NRaNBvhey2yD19pHUk+ ygwxlwygUYtHYbz4XH3ee5gdrcte1hUzVD+I5Eyyv0gVAs55ge2tJL0trB0AqjVb/PX6 xzew== X-Gm-Message-State: AAQBX9ehSbfc8zhZWCqgDI1xQFQ74FiYfYjsEy3vZ7QkZFt+NLUuUDzp 1SvlM0dG3HITYmvEO7R27MyQzIw0jom+mgaaUb8= X-Google-Smtp-Source: AKy350agHaXZ2N3C7jws744uDzQuv1mz+pYVXVyu455sJe/0JU28aA1EP7ogMUpLZnwD54vEI/Z78w== X-Received: by 2002:aca:190b:0:b0:389:3512:2a45 with SMTP id l11-20020aca190b000000b0038935122a45mr873186oii.10.1679921024697; Mon, 27 Mar 2023 05:43:44 -0700 (PDT) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, bmeng@tinylab.org, liweiwei@iscas.ac.cn, zhiwei_liu@linux.alibaba.com, palmer@rivosinc.com, Daniel Henrique Barboza Subject: [PATCH 17/19] target/riscv: remove cfg.ext_g setup from rv64_thead_c906_cpu_init() Date: Mon, 27 Mar 2023 09:42:45 -0300 Message-Id: <20230327124247.106595-18-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230327124247.106595-1-dbarboza@ventanamicro.com> References: <20230327124247.106595-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::22c; envelope-from=dbarboza@ventanamicro.com; helo=mail-oi1-x22c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ventanamicro.com) X-ZM-MESSAGEID: 1679921151308100006 Content-Type: text/plain; charset="utf-8" This CPU is enabling G via cfg.ext_g and, at the same time, setting IMAFD in set_misa() and cfg.ext_icsr. riscv_cpu_validate_set_extensions() is already doing that, so there's no need for cpu_init() setups to worry about setting G and its extensions. Signed-off-by: Daniel Henrique Barboza --- target/riscv/cpu.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 81c8e0d541..3078d1a097 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -397,11 +397,10 @@ static void rv64_thead_c906_cpu_init(Object *obj) CPURISCVState *env =3D &RISCV_CPU(obj)->env; RISCVCPU *cpu =3D RISCV_CPU(obj); =20 - set_misa(env, MXL_RV64, RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU); + set_misa(env, MXL_RV64, RVC | RVS | RVU); set_priv_version(env, PRIV_VERSION_1_11_0); =20 cpu->cfg.ext_g =3D true; - cpu->cfg.ext_icsr =3D true; cpu->cfg.ext_zfh =3D true; cpu->cfg.mmu =3D true; cpu->cfg.ext_xtheadba =3D true; --=20 2.39.2 From nobody Thu May 2 00:48:52 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1679921102; cv=none; d=zohomail.com; s=zohoarc; b=iZx7gwgCpwsxJI3Rg3NRcovc+VBhe4r7rmRRKlziQgcnS7cQwdAPPhvt9DoitUlEPUwbYhoAKdR030JF5lUS0k0UKx080eSTgWSbZRR4VGUfHIhChBMHKJJPqYFdAFescCGYFAM8iZUa1j7G0H5lqTg5lsgsdiUr9/RobagsF/k= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1679921102; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=ytCsdO2qt4E+YWGo/+oG6BWbmPNF3ykb1weTQ7hLL8s=; b=lC8ChuCecQHaLXNgMWkuLqVyJI8vHYRJ6ev4v6HmtA6Xm/5hFogSw6j560I/lRSFcbqgDsQfrq+iQhTGOS1MWRpXQenuTrwcOqMxAdrm0TzVHXYgfBYAQYkFQx474rFSevuVcLw/7xoVgQNdvgIVaSpHCvoUBR+jCZenp15nnGI= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1679921102828171.82330056756143; Mon, 27 Mar 2023 05:45:02 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pgmCd-0000rN-OF; Mon, 27 Mar 2023 08:43:59 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pgmCV-0000jL-SP for qemu-devel@nongnu.org; Mon, 27 Mar 2023 08:43:52 -0400 Received: from mail-oi1-x22e.google.com ([2607:f8b0:4864:20::22e]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pgmCT-0003JK-60 for qemu-devel@nongnu.org; Mon, 27 Mar 2023 08:43:51 -0400 Received: by mail-oi1-x22e.google.com with SMTP id r16so6128075oij.5 for ; Mon, 27 Mar 2023 05:43:48 -0700 (PDT) Received: from grind.. ([177.95.89.231]) by smtp.gmail.com with ESMTPSA id m206-20020acabcd7000000b0037d7f4eb7e8sm11136677oif.31.2023.03.27.05.43.44 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 27 Mar 2023 05:43:47 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1679921027; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=ytCsdO2qt4E+YWGo/+oG6BWbmPNF3ykb1weTQ7hLL8s=; b=njkB0VTIgHUOmdFMXiSQBp7mwnapVFSP/tnGRaxujZJigcWBtSXRVfaD+PL6cVIQeo Nl7haJTg3I3SVeDkC8Wkeiyx4xab7dLQLeqkzgvEsITUS7her0mxNczODtnfUmI4bgeP 5s4yN2r+fPHVVPg0L391GVnQdg/mJhsf0Ogcv/dz5pFeL3Hu4j6Z6poarunFs6MFRgwd mV8TotAfQr+p9f3uBhaRXW7Vjczv+utaztCa1Vb44cLXAWDTihKZdCWYSYHAErYeLF07 o6lfIcmG9Cw1PP6fJgHKMjjJKXLQ+2u//Fu2B4xWl4k4+KLtpQGmdd0LoZ+x9iA8NRYs /b4Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1679921027; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=ytCsdO2qt4E+YWGo/+oG6BWbmPNF3ykb1weTQ7hLL8s=; b=ui+zRzsBagyE7uW69xxdbljlkAv0j/YU4pQN6QqHbtLGW5PCHNPzqwFWL/2s5astAu 05OQxZKNLNs22Bok6AoujJ+eNWD/CFiJTMtrdg09bVB+NZltYUTs0EGJbj71WJYNv4Fx UnJFh4it8N/tlF0qDSBaixHQFiS33V3NkuddFDqmJfK3JUtEZfX3DxGuA7Vih/CNuddH YQqpRrc2QfTfqw4GLBOflZBBJUFDNLRawqRBQ0ykzwCSfZcuq8DINVNd4tnVxjclL8u1 3C5jTfwbnsJdTXnkodheAHNnK+kvuwhzxSo0FLLEzTuZZbXKYM5C2JS5/MVPRXDmWIHM 2pjA== X-Gm-Message-State: AAQBX9f3vBSCqIi6okYofAQh+LDusT30j2ATT8wWsT6iwiY3whxaPUtK OAG1XN56SouMet8TNunKbJsl1KD8ZTcZw83LjU0= X-Google-Smtp-Source: AKy350Z/VwunFjYdXljdZumLmj3k/vSe7L4SnGYKts1APFBWiX+I7l9Sz9vvN34JZ4mEeYYHxLgCcw== X-Received: by 2002:a54:4813:0:b0:389:1e16:7aad with SMTP id j19-20020a544813000000b003891e167aadmr2023843oij.41.1679921027558; Mon, 27 Mar 2023 05:43:47 -0700 (PDT) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, bmeng@tinylab.org, liweiwei@iscas.ac.cn, zhiwei_liu@linux.alibaba.com, palmer@rivosinc.com, Daniel Henrique Barboza Subject: [PATCH 18/19] target/riscv: add RVG and remove cpu->cfg.ext_g Date: Mon, 27 Mar 2023 09:42:46 -0300 Message-Id: <20230327124247.106595-19-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230327124247.106595-1-dbarboza@ventanamicro.com> References: <20230327124247.106595-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::22e; envelope-from=dbarboza@ventanamicro.com; helo=mail-oi1-x22e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ventanamicro.com) X-ZM-MESSAGEID: 1679921105045100003 Content-Type: text/plain; charset="utf-8" We're still have one RISCVCPUConfig MISA flag, 'ext_g'. We'll remove it the same way we did with the others: create a "g" RISCVCPUMisaExtConfig property, remove the old "g" property, remove all instances of 'cfg.ext_g' and use riscv_has_ext(env, RVG). The caveat is that we don't have RVG, so add it. RVG will be used right off the bat in set_misa() of rv64_thead_c906_cpu_init() because the CPU is enabling G via the now removed 'ext_g' flag. After this patch, there are no more MISA extensions represented by flags in RISCVCPUConfig. Signed-off-by: Daniel Henrique Barboza --- target/riscv/cpu.c | 17 ++++++++--------- target/riscv/cpu.h | 2 +- 2 files changed, 9 insertions(+), 10 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 3078d1a097..01755036f0 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -397,10 +397,9 @@ static void rv64_thead_c906_cpu_init(Object *obj) CPURISCVState *env =3D &RISCV_CPU(obj)->env; RISCVCPU *cpu =3D RISCV_CPU(obj); =20 - set_misa(env, MXL_RV64, RVC | RVS | RVU); + set_misa(env, MXL_RV64, RVG | RVC | RVS | RVU); set_priv_version(env, PRIV_VERSION_1_11_0); =20 - cpu->cfg.ext_g =3D true; cpu->cfg.ext_zfh =3D true; cpu->cfg.mmu =3D true; cpu->cfg.ext_xtheadba =3D true; @@ -808,12 +807,11 @@ static void riscv_cpu_validate_set_extensions(RISCVCP= U *cpu, Error **errp) CPURISCVState *env =3D &cpu->env; =20 /* Do some ISA extension error checking */ - if (cpu->cfg.ext_g && !(riscv_has_ext(env, RVI) && - riscv_has_ext(env, RVM) && - riscv_has_ext(env, RVA) && - riscv_has_ext(env, RVF) && - riscv_has_ext(env, RVD) && - cpu->cfg.ext_icsr && cpu->cfg.ext_ifencei)) { + if (riscv_has_ext(env, RVG) && + !(riscv_has_ext(env, RVI) && riscv_has_ext(env, RVM) && + riscv_has_ext(env, RVA) && riscv_has_ext(env, RVF) && + riscv_has_ext(env, RVD) && + cpu->cfg.ext_icsr && cpu->cfg.ext_ifencei)) { warn_report("Setting G will also set IMAFD_Zicsr_Zifencei"); cpu->cfg.ext_icsr =3D true; cpu->cfg.ext_ifencei =3D true; @@ -1403,6 +1401,8 @@ static RISCVCPUMisaExtConfig misa_ext_cfgs[] =3D { .misa_bit =3D RVJ, .enabled =3D false}, {.name =3D "v", .description =3D "Vector operations", .misa_bit =3D RVV, .enabled =3D false}, + {.name =3D "g", .description =3D "General purpose (IMAFD_Zicsr_Zifence= i)", + .misa_bit =3D RVG, .enabled =3D false}, }; =20 static void riscv_cpu_add_misa_properties(Object *cpu_obj) @@ -1425,7 +1425,6 @@ static void riscv_cpu_add_misa_properties(Object *cpu= _obj) =20 static Property riscv_cpu_extensions[] =3D { /* Defaults for standard extensions */ - DEFINE_PROP_BOOL("g", RISCVCPU, cfg.ext_g, false), DEFINE_PROP_UINT8("pmu-num", RISCVCPU, cfg.pmu_num, 16), DEFINE_PROP_BOOL("sscofpmf", RISCVCPU, cfg.ext_sscofpmf, false), DEFINE_PROP_BOOL("Zifencei", RISCVCPU, cfg.ext_ifencei, true), diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index c0280ace2a..ce92e8393d 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -81,6 +81,7 @@ #define RVU RV('U') #define RVH RV('H') #define RVJ RV('J') +#define RVG RV('G') =20 =20 /* Privileged specification version */ @@ -418,7 +419,6 @@ typedef struct { } RISCVSATPMap; =20 struct RISCVCPUConfig { - bool ext_g; bool ext_zba; bool ext_zbb; bool ext_zbc; --=20 2.39.2 From nobody Thu May 2 00:48:52 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1679921223; cv=none; d=zohomail.com; s=zohoarc; b=fZNIOQ88Cl6E5q2P+8FIWBUaLKBnx7+mr9KZZd7HjTyXa33n6GgoPhID/ImXTzFSle+siFQPeIWGp4vDGmnCcB4M/AASmsIhrJbFNPIrAQRyk6WSFWeC7CQjiKYRxUj3/W9zItOC5iQ3gNuaLB9BL7t8GJPWvAXmKl8ol6/LabA= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1679921223; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=Yo8MiHaBZQap8NhMe2aiy9oMmnlYjocTnpesmXBKmzY=; b=a61NyZ1ne+33OJCzSHVU5DVJODapSRFNFws6DYoUU1DY6/JX34RI/DGtNEuA3lC3ayDSHE15BW22j38/EJdAirrWE+Jod0iwU0pNnCwKss+Zi7OzzMtDhJSwy81AIXY+S8+kcAIjdbYOHEtcD1MEq0pYlNIyeVTCrFd7uL9QHs4= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1679921223131195.0546304691792; Mon, 27 Mar 2023 05:47:03 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pgmCi-00017D-G3; Mon, 27 Mar 2023 08:44:04 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pgmCY-0000nD-2b for qemu-devel@nongnu.org; Mon, 27 Mar 2023 08:43:54 -0400 Received: from mail-oa1-x34.google.com ([2001:4860:4864:20::34]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pgmCV-00039R-JJ for qemu-devel@nongnu.org; Mon, 27 Mar 2023 08:43:53 -0400 Received: by mail-oa1-x34.google.com with SMTP id 586e51a60fabf-17aceccdcf6so9087173fac.9 for ; Mon, 27 Mar 2023 05:43:51 -0700 (PDT) Received: from grind.. ([177.95.89.231]) by smtp.gmail.com with ESMTPSA id m206-20020acabcd7000000b0037d7f4eb7e8sm11136677oif.31.2023.03.27.05.43.47 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 27 Mar 2023 05:43:50 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1679921030; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=Yo8MiHaBZQap8NhMe2aiy9oMmnlYjocTnpesmXBKmzY=; b=awui2fwGKZ6mnvwmPFAXLuBYS0Qiv8T0TcGvwsyotvw8rJgIgK2EhmBIjLehsOz2Af QMm0l5BuVeBO791cUwg4bcUQVPS8E9GF4SOUqRaaM2u4OQiXQmvavRS7z0nok9oW2+8r WnllAvtW5Zh4Kr+61o9/lbnAa5UQ5oUVVO2VHX9aOXKWIhpI2SSjplRJh54hUr/dzKD3 REH+vn/vi9+UiQF1vRU8F2/SKCfF0ri39wGfjVm5NQf3ZM40GhFyM1W6gL4lYiN52mvE E57wwb97zMPzuuUU9fUwhcERH3O7PcvsvSfUlFE6AwO5LANZIkdAlQfmicc3Z6+de9u4 B5Og== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1679921030; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=Yo8MiHaBZQap8NhMe2aiy9oMmnlYjocTnpesmXBKmzY=; b=NJUkEKIRYyAp/RLv2fHwkRhw3nl4Iv8suWFDPU2qqJpxnD5iIO7xpfQfT0BpuL1n/Q io9tUxLDffMwF+kaYi5ObthYnVj+R1aWGMbU/JsqTnDYOnQsNCsliQHu5Qxi/9dp6Wn3 iWj5j/3SQFExZtqfZbZW0cFQi+0hZmzSzASLyKshskDQnyCxOBnU7seuA6CGL9JvAdTa lA/fUuYntcp7dA0rGVHZpN3HA1IrggE4ytjZnSr0S8EcRIc4aGuKszZk6Y+KPyEy39P8 zUTMRHL+bBtefewewyECuREiP0LVKrIVy5mQ0BjfgAEDZfFp3Azj3YKfY3Q693gtF9Zk NCpA== X-Gm-Message-State: AAQBX9d+MyOxtzhKrC8mj32LUrkXcaq64Mo8RZp8IVqAvJjH3LVYq2Xl RztDg7Unk6WBn0xB34YS45INv7oVKHRAHYtTT3E= X-Google-Smtp-Source: AKy350aUlp1RsZAIuRv7W/ZH56h8O6P2WnMO6qzXfhDWJnwmM8YUH0aBP1oa7CMXz0tN8aCq4PGk2Q== X-Received: by 2002:a05:6870:8302:b0:176:be86:3c7d with SMTP id p2-20020a056870830200b00176be863c7dmr6864191oae.52.1679921030490; Mon, 27 Mar 2023 05:43:50 -0700 (PDT) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, bmeng@tinylab.org, liweiwei@iscas.ac.cn, zhiwei_liu@linux.alibaba.com, palmer@rivosinc.com, Daniel Henrique Barboza Subject: [PATCH 19/19] target/riscv/cpu.c: redesign register_cpu_props() Date: Mon, 27 Mar 2023 09:42:47 -0300 Message-Id: <20230327124247.106595-20-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230327124247.106595-1-dbarboza@ventanamicro.com> References: <20230327124247.106595-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2001:4860:4864:20::34; envelope-from=dbarboza@ventanamicro.com; helo=mail-oa1-x34.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ventanamicro.com) X-ZM-MESSAGEID: 1679921223658100001 Content-Type: text/plain; charset="utf-8" The function is now a no-op for all cpu_init() callers that are setting a non-zero misa value in set_misa(), since it's no longer used to sync cpu->cfg props with env->misa_ext bits. Remove it in those cases. While we're at it, rename the function to match what it's actually doing: create user properties to set/remove CPU extensions. Make a note that it will overwrite env->misa_ext with the defaults set by each user property. Update the MISA bits comment in cpu.h as well. Signed-off-by: Daniel Henrique Barboza --- target/riscv/cpu.c | 41 ++++++++++------------------------------- target/riscv/cpu.h | 5 +---- 2 files changed, 11 insertions(+), 35 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 01755036f0..08cf5e9815 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -222,7 +222,7 @@ static const char * const riscv_intr_names[] =3D { "reserved" }; =20 -static void register_cpu_props(Object *obj); +static void riscv_cpu_add_user_properties(Object *obj); =20 const char *riscv_cpu_get_trap_name(target_ulong cause, bool async) { @@ -350,7 +350,6 @@ static void riscv_any_cpu_init(Object *obj) #endif =20 set_priv_version(env, PRIV_VERSION_1_12_0); - register_cpu_props(obj); } =20 #if defined(TARGET_RISCV64) @@ -359,7 +358,7 @@ static void rv64_base_cpu_init(Object *obj) CPURISCVState *env =3D &RISCV_CPU(obj)->env; /* We set this in the realise function */ set_misa(env, MXL_RV64, 0); - register_cpu_props(obj); + riscv_cpu_add_user_properties(obj); /* Set latest version of privileged specification */ set_priv_version(env, PRIV_VERSION_1_12_0); #ifndef CONFIG_USER_ONLY @@ -371,7 +370,6 @@ static void rv64_sifive_u_cpu_init(Object *obj) { CPURISCVState *env =3D &RISCV_CPU(obj)->env; set_misa(env, MXL_RV64, RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU); - register_cpu_props(obj); set_priv_version(env, PRIV_VERSION_1_10_0); #ifndef CONFIG_USER_ONLY set_satp_mode_max_supported(RISCV_CPU(obj), VM_1_10_SV39); @@ -384,7 +382,6 @@ static void rv64_sifive_e_cpu_init(Object *obj) RISCVCPU *cpu =3D RISCV_CPU(obj); =20 set_misa(env, MXL_RV64, RVI | RVM | RVA | RVC | RVU); - register_cpu_props(obj); set_priv_version(env, PRIV_VERSION_1_10_0); cpu->cfg.mmu =3D false; #ifndef CONFIG_USER_ONLY @@ -430,7 +427,7 @@ static void rv128_base_cpu_init(Object *obj) CPURISCVState *env =3D &RISCV_CPU(obj)->env; /* We set this in the realise function */ set_misa(env, MXL_RV128, 0); - register_cpu_props(obj); + riscv_cpu_add_user_properties(obj); /* Set latest version of privileged specification */ set_priv_version(env, PRIV_VERSION_1_12_0); #ifndef CONFIG_USER_ONLY @@ -443,7 +440,7 @@ static void rv32_base_cpu_init(Object *obj) CPURISCVState *env =3D &RISCV_CPU(obj)->env; /* We set this in the realise function */ set_misa(env, MXL_RV32, 0); - register_cpu_props(obj); + riscv_cpu_add_user_properties(obj); /* Set latest version of privileged specification */ set_priv_version(env, PRIV_VERSION_1_12_0); #ifndef CONFIG_USER_ONLY @@ -455,7 +452,6 @@ static void rv32_sifive_u_cpu_init(Object *obj) { CPURISCVState *env =3D &RISCV_CPU(obj)->env; set_misa(env, MXL_RV32, RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU); - register_cpu_props(obj); set_priv_version(env, PRIV_VERSION_1_10_0); #ifndef CONFIG_USER_ONLY set_satp_mode_max_supported(RISCV_CPU(obj), VM_1_10_SV32); @@ -468,7 +464,6 @@ static void rv32_sifive_e_cpu_init(Object *obj) RISCVCPU *cpu =3D RISCV_CPU(obj); =20 set_misa(env, MXL_RV32, RVI | RVM | RVA | RVC | RVU); - register_cpu_props(obj); set_priv_version(env, PRIV_VERSION_1_10_0); cpu->cfg.mmu =3D false; #ifndef CONFIG_USER_ONLY @@ -482,7 +477,6 @@ static void rv32_ibex_cpu_init(Object *obj) RISCVCPU *cpu =3D RISCV_CPU(obj); =20 set_misa(env, MXL_RV32, RVI | RVM | RVC | RVU); - register_cpu_props(obj); set_priv_version(env, PRIV_VERSION_1_11_0); cpu->cfg.mmu =3D false; #ifndef CONFIG_USER_ONLY @@ -497,7 +491,6 @@ static void rv32_imafcu_nommu_cpu_init(Object *obj) RISCVCPU *cpu =3D RISCV_CPU(obj); =20 set_misa(env, MXL_RV32, RVI | RVM | RVA | RVF | RVC | RVU); - register_cpu_props(obj); set_priv_version(env, PRIV_VERSION_1_10_0); cpu->cfg.mmu =3D false; #ifndef CONFIG_USER_ONLY @@ -515,7 +508,7 @@ static void riscv_host_cpu_init(Object *obj) #elif defined(TARGET_RISCV64) set_misa(env, MXL_RV64, 0); #endif - register_cpu_props(obj); + riscv_cpu_add_user_properties(obj); } #endif =20 @@ -1509,30 +1502,16 @@ static Property riscv_cpu_extensions[] =3D { }; =20 /* - * Register CPU props based on env.misa_ext. If a non-zero - * value was set, register only the required cpu->cfg.ext_* - * properties and leave. env.misa_ext =3D 0 means that we want - * all the default properties to be registered. + * Add CPU properties with user-facing flags. + * + * This will overwrite existing env->misa_ext values with the + * defaults set via riscv_cpu_add_misa_properties(). */ -static void register_cpu_props(Object *obj) +static void riscv_cpu_add_user_properties(Object *obj) { - RISCVCPU *cpu =3D RISCV_CPU(obj); Property *prop; DeviceState *dev =3D DEVICE(obj); =20 - /* - * If misa_ext is not zero, set cfg properties now to - * allow them to be read during riscv_cpu_realize() - * later on. - */ - if (cpu->env.misa_ext !=3D 0) { - /* - * We don't want to set the default riscv_cpu_extensions - * in this case. - */ - return; - } - riscv_cpu_add_misa_properties(obj); =20 for (prop =3D riscv_cpu_extensions; prop && prop->name; prop++) { diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index ce92e8393d..02f26130d5 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -65,10 +65,7 @@ =20 #define RV(x) ((target_ulong)1 << (x - 'A')) =20 -/* - * Consider updating register_cpu_props() when adding - * new MISA bits here. - */ +/* Consider updating misa_ext_cfgs[] when adding new MISA bits here */ #define RVI RV('I') #define RVE RV('E') /* E and I are mutually exclusive */ #define RVM RV('M') --=20 2.39.2