We're getting ready to use riscv_cpu_validate_set_extensions() to unify
the handling of write_misa() with the rest of the code base. But first
we need to deal with RVG.

The 'G' virtual extension enables a set of extensions in the CPU. At
this moment, this is done at the start of our validation step in
riscv_cpu_validate_set_extensions(). This means that enabling G will
enable other extensions in the CPU before resuming the validation.

This also means that, in case a write_misa() validation fails, we're
going to set cpu->cfg attributes that are unrelated to misa_ext bits
(icsr and ifencei). These would be 2 extra states that we would need to
store to fallback from a validation failure.

Since write_misa() is still on experimental state let's make our lives
easier for now and disable RVG updates.

Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
---
 target/riscv/csr.c | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index d522efc0b6..918d442ebd 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -1348,6 +1348,11 @@ static RISCVException write_misa(CPURISCVState *env, int csrno,
         return RISCV_EXCP_NONE;
     }
 
+    /* Changing 'G' state is unsupported */
+    if (val & RVG) {
+        return RISCV_EXCP_NONE;
+    }
+
     /* 'I' or 'E' must be present */
     if (!(val & (RVI | RVE))) {
         /* It is not, drop write to misa */
-- 
2.39.2

On 2023/3/15 00:49, Daniel Henrique Barboza wrote:
> We're getting ready to use riscv_cpu_validate_set_extensions() to unify
> the handling of write_misa() with the rest of the code base. But first
> we need to deal with RVG.
>
> The 'G' virtual extension enables a set of extensions in the CPU. At
> this moment, this is done at the start of our validation step in
> riscv_cpu_validate_set_extensions(). This means that enabling G will
> enable other extensions in the CPU before resuming the validation.
>
> This also means that, in case a write_misa() validation fails, we're
> going to set cpu->cfg attributes that are unrelated to misa_ext bits
> (icsr and ifencei). These would be 2 extra states that we would need to
> store to fallback from a validation failure.
>
> Since write_misa() is still on experimental state let's make our lives
> easier for now and disable RVG updates.
>
> Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
> ---
>   target/riscv/csr.c | 5 +++++
>   1 file changed, 5 insertions(+)
>
> diff --git a/target/riscv/csr.c b/target/riscv/csr.c
> index d522efc0b6..918d442ebd 100644
> --- a/target/riscv/csr.c
> +++ b/target/riscv/csr.c
> @@ -1348,6 +1348,11 @@ static RISCVException write_misa(CPURISCVState *env, int csrno,
>           return RISCV_EXCP_NONE;
>       }
>   
> +    /* Changing 'G' state is unsupported */
> +    if (val & RVG) {
> +        return RISCV_EXCP_NONE;
> +    }
> +

'val & G' is not equal  "Changing 'G'" .

Regards,

Weiwei Li

>       /* 'I' or 'E' must be present */
>       if (!(val & (RVI | RVE))) {
>           /* It is not, drop write to misa */