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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::329; envelope-from=dbarboza@ventanamicro.com; helo=mail-ot1-x329.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ventanamicro.com) X-ZM-MESSAGEID: 1678812691316100005 Content-Type: text/plain; charset="utf-8" We're getting ready to use riscv_cpu_validate_set_extensions() to unify the handling of write_misa() with the rest of the code base. But first we need to deal with RVG. The 'G' virtual extension enables a set of extensions in the CPU. At this moment, this is done at the start of our validation step in riscv_cpu_validate_set_extensions(). This means that enabling G will enable other extensions in the CPU before resuming the validation. This also means that, in case a write_misa() validation fails, we're going to set cpu->cfg attributes that are unrelated to misa_ext bits (icsr and ifencei). These would be 2 extra states that we would need to store to fallback from a validation failure. Since write_misa() is still on experimental state let's make our lives easier for now and disable RVG updates. Signed-off-by: Daniel Henrique Barboza --- target/riscv/csr.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/target/riscv/csr.c b/target/riscv/csr.c index d522efc0b6..918d442ebd 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -1348,6 +1348,11 @@ static RISCVException write_misa(CPURISCVState *env,= int csrno, return RISCV_EXCP_NONE; } =20 + /* Changing 'G' state is unsupported */ + if (val & RVG) { + return RISCV_EXCP_NONE; + } + /* 'I' or 'E' must be present */ if (!(val & (RVI | RVE))) { /* It is not, drop write to misa */ --=20 2.39.2