Hi,
On 3/10/23 13:03, Lawrence Hunter wrote:
> NB: this is an update over the patch series submitted today (2023/03/10) at 09:11. It fixes some accidental mangling of commits 02, 04 and 08/45.
>
> This patchset provides an implementation for Zvkb, Zvkned, Zvknh, Zvksh, Zvkg, and Zvksed of the draft RISC-V vector cryptography extensions as per the 20230303 version of the specification(1) (1fcbb30). Please note that the Zvkt data-independent execution latency extension has not been implemented, and we would recommend not using these patches in an environment where timing attacks are an issue.
>
> Work performed by Dickon, Lawrence, Nazar, Kiran, and William from Codethink sponsored by SiFive, as well as Max Chou and Frank Chang from SiFive.
>
> For convenience we have created a git repo with our patches on top of a recent master. https://github.com/CodethinkLabs/qemu-ct
>
> 1. https://github.com/riscv/riscv-crypto/releases
For the next versions I suggest CCing qemu-riscv@nongnu.org as well. It's an
easier way to keep track of RISC-V contributions since qemu-devel has a lot of
traffic.
Thanks,
Daniel
>
> Dickon Hood (2):
> qemu/bitops.h: Limit rotate amounts
> target/riscv: Add vrol.[vv,vx] and vror.[vv,vx,vi] decoding,
> translation and execution support
>
> Kiran Ostrolenk (7):
> target/riscv: Refactor some of the generic vector functionality
> target/riscv: Refactor some of the generic vector functionality
> target/riscv: Refactor some of the generic vector functionality
> target/riscv: Add vsha2ms.vv decoding, translation and execution
> support
> target/riscv: Add zvksh cpu property
> target/riscv: Add vsm3c.vi decoding, translation and execution support
> target/riscv: Expose zvksh cpu property
>
> Lawrence Hunter (17):
> target/riscv: Add vclmul.vv decoding, translation and execution
> support
> target/riscv: Add vclmul.vx decoding, translation and execution
> support
> target/riscv: Add vclmulh.vv decoding, translation and execution
> support
> target/riscv: Add vclmulh.vx decoding, translation and execution
> support
> target/riscv: Add vaesef.vv decoding, translation and execution
> support
> target/riscv: Add vaesef.vs decoding, translation and execution
> support
> target/riscv: Add vaesdf.vv decoding, translation and execution
> support
> target/riscv: Add vaesdf.vs decoding, translation and execution
> support
> target/riscv: Add vaesdm.vv decoding, translation and execution
> support
> target/riscv: Add vaesdm.vs decoding, translation and execution
> support
> target/riscv: Add vaesz.vs decoding, translation and execution support
> target/riscv: Add vsha2c[hl].vv decoding, translation and execution
> support
> target/riscv: Add vsm3me.vv decoding, translation and execution
> support
> target/riscv: Add zvkg cpu property
> target/riscv: Add vgmul.vv decoding, translation and execution support
> target/riscv: Add vghsh.vv decoding, translation and execution support
> target/riscv: Expose zvkg cpu property
>
> Max Chou (5):
> crypto: Create sm4_subword
> crypto: Add SM4 constant parameter CK
> target/riscv: Add zvksed cfg property
> target/riscv: Add Zvksed support
> target/riscv: Expose Zvksed property
>
> Nazar Kazakov (11):
> target/riscv: Add zvkb cpu property
> target/riscv: Refactor some of the generic vector functionality
> target/riscv: Add vrev8.v decoding, translation and execution support
> target/riscv: Add vandn.[vv,vx] decoding, translation and execution
> support
> target/riscv: Expose zvkb cpu property
> target/riscv: Add zvkned cpu property
> target/riscv: Add vaeskf1.vi decoding, translation and execution
> support
> target/riscv: Add vaeskf2.vi decoding, translation and execution
> support
> target/riscv: Expose zvkned cpu property
> target/riscv: Add zvknh cpu properties
> target/riscv: Expose zvknh cpu properties
>
> William Salmon (3):
> target/riscv: Add vbrev8.v decoding, translation and execution support
> target/riscv: Add vaesem.vv decoding, translation and execution
> support
> target/riscv: Add vaesem.vs decoding, translation and execution
> support
>
> accel/tcg/tcg-runtime-gvec.c | 11 +
> accel/tcg/tcg-runtime.h | 1 +
> crypto/sm4.c | 10 +
> include/crypto/sm4.h | 9 +
> include/qemu/bitops.h | 24 +-
> target/arm/tcg/crypto_helper.c | 10 +-
> target/riscv/cpu.c | 36 +
> target/riscv/cpu.h | 7 +
> target/riscv/helper.h | 71 ++
> target/riscv/insn32.decode | 49 +
> target/riscv/insn_trans/trans_rvv.c.inc | 93 +-
> target/riscv/insn_trans/trans_rvzvkb.c.inc | 220 ++++
> target/riscv/insn_trans/trans_rvzvkg.c.inc | 40 +
> target/riscv/insn_trans/trans_rvzvkned.c.inc | 170 +++
> target/riscv/insn_trans/trans_rvzvknh.c.inc | 84 ++
> target/riscv/insn_trans/trans_rvzvksed.c.inc | 57 +
> target/riscv/insn_trans/trans_rvzvksh.c.inc | 43 +
> target/riscv/meson.build | 4 +-
> target/riscv/op_helper.c | 5 +
> target/riscv/translate.c | 6 +
> target/riscv/vcrypto_helper.c | 1001 ++++++++++++++++++
> target/riscv/vector_helper.c | 240 +----
> target/riscv/vector_internals.c | 81 ++
> target/riscv/vector_internals.h | 222 ++++
> 24 files changed, 2192 insertions(+), 302 deletions(-)
> create mode 100644 target/riscv/insn_trans/trans_rvzvkb.c.inc
> create mode 100644 target/riscv/insn_trans/trans_rvzvkg.c.inc
> create mode 100644 target/riscv/insn_trans/trans_rvzvkned.c.inc
> create mode 100644 target/riscv/insn_trans/trans_rvzvknh.c.inc
> create mode 100644 target/riscv/insn_trans/trans_rvzvksed.c.inc
> create mode 100644 target/riscv/insn_trans/trans_rvzvksh.c.inc
> create mode 100644 target/riscv/vcrypto_helper.c
> create mode 100644 target/riscv/vector_internals.c
> create mode 100644 target/riscv/vector_internals.h
>