crypto/sm4.c | 10 + include/crypto/sm4.h | 9 + target/arm/tcg/crypto_helper.c | 10 +- target/riscv/cpu.c | 37 + target/riscv/cpu_cfg.h | 8 + target/riscv/helper.h | 98 +++ target/riscv/insn32.decode | 58 ++ target/riscv/insn_trans/trans_rvv.c.inc | 171 ++-- target/riscv/insn_trans/trans_rvvk.c.inc | 606 ++++++++++++++ target/riscv/meson.build | 4 +- target/riscv/translate.c | 1 + target/riscv/vcrypto_helper.c | 970 +++++++++++++++++++++++ target/riscv/vector_helper.c | 243 +----- target/riscv/vector_internals.c | 81 ++ target/riscv/vector_internals.h | 228 ++++++ 15 files changed, 2179 insertions(+), 355 deletions(-) create mode 100644 target/riscv/insn_trans/trans_rvvk.c.inc create mode 100644 target/riscv/vcrypto_helper.c create mode 100644 target/riscv/vector_internals.c create mode 100644 target/riscv/vector_internals.h
This patchset provides an implementation for Zvbb, Zvbc, Zvkned, Zvknh,
Zvksh, Zvkg, and Zvksed of the draft RISC-V vector cryptography
extensions as per the v20230620 version of the specification(1)(168e7b4).
This is an update to the patchset submitted to qemu-devel on
Wed, 12 Jul 2023 00:31:21 +0800
v2:
Squashed commits into one commit per extension with separate
commits for each refactoring.
Unified trans_rvzvk*.c.inc files into one trans_rvvk.c.inc.
Style fixes in insn32.decode and other files.
Added macros for EGS values in translation functions.
Updated from v20230303 to v20230407 of the spec:
Zvkb has been split into Zvbb and Zvbc.
vbrev, vclz, vctz, vcpop and vwsll have been added to Zvbb.
v3:
New patch 03/19 removes redundant “cpu_vl == 0” checks from
trans_rvv.c.inc.
Introduction of new tcg ops has been factored out of patch 11/19
and into 09/19.
These ops are now added to non riscv-specific files.
v4:
New patch 08/17 fixes the tcg_gen_gvec_andcs temporary variable
issue.
Patch 09/17 fixes imm mode for vror.vi.
Rebased to riscv-to-apply.next branch (de395bb):
Replace vstart constraint checking by TCG op.
Verified by code examples provided by vector crypto spec repository
(riscv-crypto).
v5:
Imported aes-round.h for Zvkned extension.
Rebased to 20230620110758.787479-1-richard.henderson@linaro.org
Exposed the properties of v4 patch 17/17 to the patches that the
extension was added.
Removed v4 patch 08/17 that is queued to tcg-next.
v6:
Resent the same content becaue v5 was splitted by broken
git-send-mail
v7:
Fixed endian issues
Replace the TCG ops of vstart & vl EGS checking by helper function
Changed the SEW selection of vsha2c[hl].vv to TCG translation
v8:
Rebased to the riscv-to-apply.next branch
Fixed cross win32 build issue
Removed redundent swap in AES key expanding (vaeskf1 & vaeskf2)
As v20230620 is a frozen version, we are not expecting any significant
changes to the specification or this patch series.
Please note that the Zvkt data-independent execution latency extension
(and all extensions including it) has not been implemented, and we
would recommend not using these patches in an environment where timing
attacks are an issue.
Work performed by Dickon, Lawrence, Nazar, Kiran, and William from
Codethink sponsored by SiFive, as well as Max Chou and Frank Chang
from SiFive.
https://github.com/riscv/riscv-crypto/releases
Thanks to those who have already reviewed:
Daniel Henrique Barboza dbarboza@ventanamicro.com
[PATCH v4 09/17] target/riscv: Add Zvbb ISA extension support
[PATCH v4 10/17] target/riscv: Add Zvkned ISA extension support
[PATCH v4 11/17] target/riscv: Add Zvknh ISA extension support
[PATCH v4 12/17] target/riscv: Add Zvksh ISA extension support
[PATCH v4 13/17] target/riscv: Add Zvkg ISA extension support
Weiwei Li liweiwei@iscas.ac.cn
[PATCH v3 01/19] target/riscv: Refactor some of the generic vector functionality
[PATCH v3 02/19] target/riscv: Refactor vector-vector translation macro
[PATCH v3 03/19] target/riscv: Remove redundant "cpu_vl == 0" checks
[PATCH v3 05/19] target/riscv: Move vector translation checks
[PATCH v3 06/19] target/riscv: Refactor translation of vector-widening instruction
[PATCH v3 07/19] target/riscv: Refactor some of the generic vector functionality
[PATCH v3 19/19] target/riscv: Expose Zvk* and Zvb[b, c] cpu properties
Richard Henderson richard.henderson@linaro.org
[PATCH v2 02/17] target/riscv: Refactor vector-vector translation macro
[PATCH v2 04/17] target/riscv: Move vector translation checks
[PATCH v2 05/17] target/riscv: Refactor translation of vector-widening instruction
[PATCH v2 07/17] qemu/bitops.h: Limit rotate amounts
[PATCH v2 08/17] qemu/host-utils.h: Add clz and ctz functions for lower-bit integers
[PATCH v2 14/17] crypto: Create sm4_subword
Alistair Francis alistair.francis@wdc.com
[PATCH v2 02/17] target/riscv: Refactor vector-vector translation macro
Philipp Tomsich philipp.tomsich@vrull.eu
Various v1 reviews
Christoph Müllner christoph.muellner@vrull.eu
Various v1 reviews
Dickon Hood (2):
target/riscv: Refactor translation of vector-widening instruction
target/riscv: Add Zvbb ISA extension support
Kiran Ostrolenk (4):
target/riscv: Refactor some of the generic vector functionality
target/riscv: Refactor vector-vector translation macro
target/riscv: Refactor some of the generic vector functionality
target/riscv: Add Zvknh ISA extension support
Lawrence Hunter (2):
target/riscv: Add Zvbc ISA extension support
target/riscv: Add Zvksh ISA extension support
Max Chou (3):
crypto: Create sm4_subword
crypto: Add SM4 constant parameter CK
target/riscv: Add Zvksed ISA extension support
Nazar Kazakov (4):
target/riscv: Remove redundant "cpu_vl == 0" checks
target/riscv: Move vector translation checks
target/riscv: Add Zvkned ISA extension support
target/riscv: Add Zvkg ISA extension support
crypto/sm4.c | 10 +
include/crypto/sm4.h | 9 +
target/arm/tcg/crypto_helper.c | 10 +-
target/riscv/cpu.c | 37 +
target/riscv/cpu_cfg.h | 8 +
target/riscv/helper.h | 98 +++
target/riscv/insn32.decode | 58 ++
target/riscv/insn_trans/trans_rvv.c.inc | 171 ++--
target/riscv/insn_trans/trans_rvvk.c.inc | 606 ++++++++++++++
target/riscv/meson.build | 4 +-
target/riscv/translate.c | 1 +
target/riscv/vcrypto_helper.c | 970 +++++++++++++++++++++++
target/riscv/vector_helper.c | 243 +-----
target/riscv/vector_internals.c | 81 ++
target/riscv/vector_internals.h | 228 ++++++
15 files changed, 2179 insertions(+), 355 deletions(-)
create mode 100644 target/riscv/insn_trans/trans_rvvk.c.inc
create mode 100644 target/riscv/vcrypto_helper.c
create mode 100644 target/riscv/vector_internals.c
create mode 100644 target/riscv/vector_internals.h
--
2.34.1
On Tue, Jul 11, 2023 at 12:59 PM Max Chou <max.chou@sifive.com> wrote: > > This patchset provides an implementation for Zvbb, Zvbc, Zvkned, Zvknh, > Zvksh, Zvkg, and Zvksed of the draft RISC-V vector cryptography > extensions as per the v20230620 version of the specification(1)(168e7b4). > This is an update to the patchset submitted to qemu-devel on > Wed, 12 Jul 2023 00:31:21 +0800 > > v2: > > Squashed commits into one commit per extension with separate > commits for each refactoring. > Unified trans_rvzvk*.c.inc files into one trans_rvvk.c.inc. > Style fixes in insn32.decode and other files. > Added macros for EGS values in translation functions. > Updated from v20230303 to v20230407 of the spec: > Zvkb has been split into Zvbb and Zvbc. > vbrev, vclz, vctz, vcpop and vwsll have been added to Zvbb. > > v3: > > New patch 03/19 removes redundant “cpu_vl == 0” checks from > trans_rvv.c.inc. > Introduction of new tcg ops has been factored out of patch 11/19 > and into 09/19. > These ops are now added to non riscv-specific files. > > v4: > > New patch 08/17 fixes the tcg_gen_gvec_andcs temporary variable > issue. > Patch 09/17 fixes imm mode for vror.vi. > Rebased to riscv-to-apply.next branch (de395bb): > Replace vstart constraint checking by TCG op. > Verified by code examples provided by vector crypto spec repository > (riscv-crypto). > > v5: > > Imported aes-round.h for Zvkned extension. > Rebased to 20230620110758.787479-1-richard.henderson@linaro.org > Exposed the properties of v4 patch 17/17 to the patches that the > extension was added. > Removed v4 patch 08/17 that is queued to tcg-next. > > v6: > > Resent the same content becaue v5 was splitted by broken > git-send-mail > > v7: > > Fixed endian issues > Replace the TCG ops of vstart & vl EGS checking by helper function > Changed the SEW selection of vsha2c[hl].vv to TCG translation > > v8: > > Rebased to the riscv-to-apply.next branch > Fixed cross win32 build issue > Removed redundent swap in AES key expanding (vaeskf1 & vaeskf2) > > > As v20230620 is a frozen version, we are not expecting any significant > changes to the specification or this patch series. > > Please note that the Zvkt data-independent execution latency extension > (and all extensions including it) has not been implemented, and we > would recommend not using these patches in an environment where timing > attacks are an issue. > > Work performed by Dickon, Lawrence, Nazar, Kiran, and William from > Codethink sponsored by SiFive, as well as Max Chou and Frank Chang > from SiFive. > > https://github.com/riscv/riscv-crypto/releases > > Thanks to those who have already reviewed: > > Daniel Henrique Barboza dbarboza@ventanamicro.com > [PATCH v4 09/17] target/riscv: Add Zvbb ISA extension support > [PATCH v4 10/17] target/riscv: Add Zvkned ISA extension support > [PATCH v4 11/17] target/riscv: Add Zvknh ISA extension support > [PATCH v4 12/17] target/riscv: Add Zvksh ISA extension support > [PATCH v4 13/17] target/riscv: Add Zvkg ISA extension support > Weiwei Li liweiwei@iscas.ac.cn > [PATCH v3 01/19] target/riscv: Refactor some of the generic vector functionality > [PATCH v3 02/19] target/riscv: Refactor vector-vector translation macro > [PATCH v3 03/19] target/riscv: Remove redundant "cpu_vl == 0" checks > [PATCH v3 05/19] target/riscv: Move vector translation checks > [PATCH v3 06/19] target/riscv: Refactor translation of vector-widening instruction > [PATCH v3 07/19] target/riscv: Refactor some of the generic vector functionality > [PATCH v3 19/19] target/riscv: Expose Zvk* and Zvb[b, c] cpu properties > Richard Henderson richard.henderson@linaro.org > [PATCH v2 02/17] target/riscv: Refactor vector-vector translation macro > [PATCH v2 04/17] target/riscv: Move vector translation checks > [PATCH v2 05/17] target/riscv: Refactor translation of vector-widening instruction > [PATCH v2 07/17] qemu/bitops.h: Limit rotate amounts > [PATCH v2 08/17] qemu/host-utils.h: Add clz and ctz functions for lower-bit integers > [PATCH v2 14/17] crypto: Create sm4_subword > Alistair Francis alistair.francis@wdc.com > [PATCH v2 02/17] target/riscv: Refactor vector-vector translation macro > Philipp Tomsich philipp.tomsich@vrull.eu > Various v1 reviews > Christoph Müllner christoph.muellner@vrull.eu > Various v1 reviews > > Dickon Hood (2): > target/riscv: Refactor translation of vector-widening instruction > target/riscv: Add Zvbb ISA extension support > > Kiran Ostrolenk (4): > target/riscv: Refactor some of the generic vector functionality > target/riscv: Refactor vector-vector translation macro > target/riscv: Refactor some of the generic vector functionality > target/riscv: Add Zvknh ISA extension support > > Lawrence Hunter (2): > target/riscv: Add Zvbc ISA extension support > target/riscv: Add Zvksh ISA extension support > > Max Chou (3): > crypto: Create sm4_subword > crypto: Add SM4 constant parameter CK > target/riscv: Add Zvksed ISA extension support > > Nazar Kazakov (4): > target/riscv: Remove redundant "cpu_vl == 0" checks > target/riscv: Move vector translation checks > target/riscv: Add Zvkned ISA extension support > target/riscv: Add Zvkg ISA extension support Thanks! Applied to riscv-to-apply.next Alistair > > crypto/sm4.c | 10 + > include/crypto/sm4.h | 9 + > target/arm/tcg/crypto_helper.c | 10 +- > target/riscv/cpu.c | 37 + > target/riscv/cpu_cfg.h | 8 + > target/riscv/helper.h | 98 +++ > target/riscv/insn32.decode | 58 ++ > target/riscv/insn_trans/trans_rvv.c.inc | 171 ++-- > target/riscv/insn_trans/trans_rvvk.c.inc | 606 ++++++++++++++ > target/riscv/meson.build | 4 +- > target/riscv/translate.c | 1 + > target/riscv/vcrypto_helper.c | 970 +++++++++++++++++++++++ > target/riscv/vector_helper.c | 243 +----- > target/riscv/vector_internals.c | 81 ++ > target/riscv/vector_internals.h | 228 ++++++ > 15 files changed, 2179 insertions(+), 355 deletions(-) > create mode 100644 target/riscv/insn_trans/trans_rvvk.c.inc > create mode 100644 target/riscv/vcrypto_helper.c > create mode 100644 target/riscv/vector_internals.c > create mode 100644 target/riscv/vector_internals.h > > -- > 2.34.1 >
On 2023/8/2 10:54 PM, Alistair Francis wrote: > On Tue, Jul 11, 2023 at 12:59 PM Max Chou <max.chou@sifive.com> wrote: >> This patchset provides an implementation for Zvbb, Zvbc, Zvkned, Zvknh, >> Zvksh, Zvkg, and Zvksed of the draft RISC-V vector cryptography >> extensions as per the v20230620 version of the specification(1)(168e7b4). >> This is an update to the patchset submitted to qemu-devel on >> Wed, 12 Jul 2023 00:31:21 +0800 >> >> v2: >> >> Squashed commits into one commit per extension with separate >> commits for each refactoring. >> Unified trans_rvzvk*.c.inc files into one trans_rvvk.c.inc. >> Style fixes in insn32.decode and other files. >> Added macros for EGS values in translation functions. >> Updated from v20230303 to v20230407 of the spec: >> Zvkb has been split into Zvbb and Zvbc. >> vbrev, vclz, vctz, vcpop and vwsll have been added to Zvbb. >> >> v3: >> >> New patch 03/19 removes redundant “cpu_vl == 0” checks from >> trans_rvv.c.inc. >> Introduction of new tcg ops has been factored out of patch 11/19 >> and into 09/19. >> These ops are now added to non riscv-specific files. >> >> v4: >> >> New patch 08/17 fixes the tcg_gen_gvec_andcs temporary variable >> issue. >> Patch 09/17 fixes imm mode for vror.vi. >> Rebased to riscv-to-apply.next branch (de395bb): >> Replace vstart constraint checking by TCG op. >> Verified by code examples provided by vector crypto spec repository >> (riscv-crypto). >> >> v5: >> >> Imported aes-round.h for Zvkned extension. >> Rebased to 20230620110758.787479-1-richard.henderson@linaro.org >> Exposed the properties of v4 patch 17/17 to the patches that the >> extension was added. >> Removed v4 patch 08/17 that is queued to tcg-next. >> >> v6: >> >> Resent the same content becaue v5 was splitted by broken >> git-send-mail >> >> v7: >> >> Fixed endian issues >> Replace the TCG ops of vstart & vl EGS checking by helper function >> Changed the SEW selection of vsha2c[hl].vv to TCG translation >> >> v8: >> >> Rebased to the riscv-to-apply.next branch >> Fixed cross win32 build issue >> Removed redundent swap in AES key expanding (vaeskf1 & vaeskf2) >> >> >> As v20230620 is a frozen version, we are not expecting any significant >> changes to the specification or this patch series. >> >> Please note that the Zvkt data-independent execution latency extension >> (and all extensions including it) has not been implemented, and we >> would recommend not using these patches in an environment where timing >> attacks are an issue. >> >> Work performed by Dickon, Lawrence, Nazar, Kiran, and William from >> Codethink sponsored by SiFive, as well as Max Chou and Frank Chang >> from SiFive. >> >> https://github.com/riscv/riscv-crypto/releases >> >> Thanks to those who have already reviewed: >> >> Daniel Henrique Barboza dbarboza@ventanamicro.com >> [PATCH v4 09/17] target/riscv: Add Zvbb ISA extension support >> [PATCH v4 10/17] target/riscv: Add Zvkned ISA extension support >> [PATCH v4 11/17] target/riscv: Add Zvknh ISA extension support >> [PATCH v4 12/17] target/riscv: Add Zvksh ISA extension support >> [PATCH v4 13/17] target/riscv: Add Zvkg ISA extension support >> Weiwei Li liweiwei@iscas.ac.cn >> [PATCH v3 01/19] target/riscv: Refactor some of the generic vector functionality >> [PATCH v3 02/19] target/riscv: Refactor vector-vector translation macro >> [PATCH v3 03/19] target/riscv: Remove redundant "cpu_vl == 0" checks >> [PATCH v3 05/19] target/riscv: Move vector translation checks >> [PATCH v3 06/19] target/riscv: Refactor translation of vector-widening instruction >> [PATCH v3 07/19] target/riscv: Refactor some of the generic vector functionality >> [PATCH v3 19/19] target/riscv: Expose Zvk* and Zvb[b, c] cpu properties >> Richard Henderson richard.henderson@linaro.org >> [PATCH v2 02/17] target/riscv: Refactor vector-vector translation macro >> [PATCH v2 04/17] target/riscv: Move vector translation checks >> [PATCH v2 05/17] target/riscv: Refactor translation of vector-widening instruction >> [PATCH v2 07/17] qemu/bitops.h: Limit rotate amounts >> [PATCH v2 08/17] qemu/host-utils.h: Add clz and ctz functions for lower-bit integers >> [PATCH v2 14/17] crypto: Create sm4_subword >> Alistair Francis alistair.francis@wdc.com >> [PATCH v2 02/17] target/riscv: Refactor vector-vector translation macro >> Philipp Tomsich philipp.tomsich@vrull.eu >> Various v1 reviews >> Christoph Müllner christoph.muellner@vrull.eu >> Various v1 reviews >> >> Dickon Hood (2): >> target/riscv: Refactor translation of vector-widening instruction >> target/riscv: Add Zvbb ISA extension support >> >> Kiran Ostrolenk (4): >> target/riscv: Refactor some of the generic vector functionality >> target/riscv: Refactor vector-vector translation macro >> target/riscv: Refactor some of the generic vector functionality >> target/riscv: Add Zvknh ISA extension support >> >> Lawrence Hunter (2): >> target/riscv: Add Zvbc ISA extension support >> target/riscv: Add Zvksh ISA extension support >> >> Max Chou (3): >> crypto: Create sm4_subword >> crypto: Add SM4 constant parameter CK >> target/riscv: Add Zvksed ISA extension support >> >> Nazar Kazakov (4): >> target/riscv: Remove redundant "cpu_vl == 0" checks >> target/riscv: Move vector translation checks >> target/riscv: Add Zvkned ISA extension support >> target/riscv: Add Zvkg ISA extension support > Thanks! > > Applied to riscv-to-apply.next > > Alistair Thanks! We will send another patch set after the vector cryptographic spec is ratified for the corresponding update (e.g. remove the `x-` prefix from the cpu options, etc.). And with the disassembler support and the `Zvkt` & other shorthand extensions support. Max > >> crypto/sm4.c | 10 + >> include/crypto/sm4.h | 9 + >> target/arm/tcg/crypto_helper.c | 10 +- >> target/riscv/cpu.c | 37 + >> target/riscv/cpu_cfg.h | 8 + >> target/riscv/helper.h | 98 +++ >> target/riscv/insn32.decode | 58 ++ >> target/riscv/insn_trans/trans_rvv.c.inc | 171 ++-- >> target/riscv/insn_trans/trans_rvvk.c.inc | 606 ++++++++++++++ >> target/riscv/meson.build | 4 +- >> target/riscv/translate.c | 1 + >> target/riscv/vcrypto_helper.c | 970 +++++++++++++++++++++++ >> target/riscv/vector_helper.c | 243 +----- >> target/riscv/vector_internals.c | 81 ++ >> target/riscv/vector_internals.h | 228 ++++++ >> 15 files changed, 2179 insertions(+), 355 deletions(-) >> create mode 100644 target/riscv/insn_trans/trans_rvvk.c.inc >> create mode 100644 target/riscv/vcrypto_helper.c >> create mode 100644 target/riscv/vector_internals.c >> create mode 100644 target/riscv/vector_internals.h >> >> -- >> 2.34.1 >>
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