1 | The following changes since commit f003dd8d81f7d88f4b1f8802309eaa76f6eb223a: | 1 | Hi; here's the latest round of arm patches. I have included also |
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2 | my patchset for the RTC devices to avoid keeping time_t and | ||
3 | time_t diffs in 32-bit variables. | ||
2 | 4 | ||
3 | Merge tag 'pull-tcg-20230305' of https://gitlab.com/rth7680/qemu into staging (2023-03-06 10:20:04 +0000) | 5 | thanks |
6 | -- PMM | ||
7 | |||
8 | The following changes since commit 156618d9ea67f2f2e31d9dedd97f2dcccbe6808c: | ||
9 | |||
10 | Merge tag 'block-pull-request' of https://gitlab.com/stefanha/qemu into staging (2023-08-30 09:20:27 -0400) | ||
4 | 11 | ||
5 | are available in the Git repository at: | 12 | are available in the Git repository at: |
6 | 13 | ||
7 | https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20230306 | 14 | https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20230831 |
8 | 15 | ||
9 | for you to fetch changes up to 2ddc45954f97cd1d7ee5cbca0def05e980d1da9f: | 16 | for you to fetch changes up to e73b8bb8a3e9a162f70e9ffbf922d4fafc96bbfb: |
10 | 17 | ||
11 | hw: arm: allwinner-h3: Fix and complete H3 i2c devices (2023-03-06 15:31:24 +0000) | 18 | hw/arm: Set number of MPU regions correctly for an505, an521, an524 (2023-08-31 11:07:02 +0100) |
12 | 19 | ||
13 | ---------------------------------------------------------------- | 20 | ---------------------------------------------------------------- |
14 | target-arm queue: | 21 | target-arm queue: |
15 | * allwinner-h3: Fix I2C controller model for Sun6i SoCs | 22 | * Some of the preliminary patches for Cortex-A710 support |
16 | * allwinner-h3: Add missing i2c controllers | 23 | * i.MX7 and i.MX6UL refactoring |
17 | * Expose M-profile system registers to gdbstub | 24 | * Implement SRC device for i.MX7 |
18 | * Expose pauth information to gdbstub | 25 | * Catch illegal-exception-return from EL3 with bad NSE/NS |
19 | * Support direct boot for Linux/arm64 EFI zboot images | 26 | * Use 64-bit offsets for holding time_t differences in RTC devices |
20 | * Fix incorrect stage 2 MMU setup validation | 27 | * Model correct number of MPU regions for an505, an521, an524 boards |
21 | 28 | ||
22 | ---------------------------------------------------------------- | 29 | ---------------------------------------------------------------- |
23 | Ard Biesheuvel (1): | 30 | Alex Bennée (1): |
24 | hw: arm: Support direct boot for Linux/arm64 EFI zboot images | 31 | target/arm: properly document FEAT_CRC32 |
25 | 32 | ||
26 | David Reiss (2): | 33 | Jean-Christophe Dubois (6): |
27 | target/arm: Export arm_v7m_mrs_control | 34 | Remove i.MX7 IOMUX GPR device from i.MX6UL |
28 | target/arm: Export arm_v7m_get_sp_ptr | 35 | Refactor i.MX6UL processor code |
36 | Add i.MX6UL missing devices. | ||
37 | Refactor i.MX7 processor code | ||
38 | Add i.MX7 missing TZ devices and memory regions | ||
39 | Add i.MX7 SRC device implementation | ||
29 | 40 | ||
30 | Richard Henderson (16): | 41 | Peter Maydell (8): |
31 | target/arm: Normalize aarch64 gdbstub get/set function names | 42 | target/arm: Catch illegal-exception-return from EL3 with bad NSE/NS |
32 | target/arm: Unexport arm_gen_dynamic_sysreg_xml | 43 | hw/rtc/m48t59: Use 64-bit arithmetic in set_alarm() |
33 | target/arm: Move arm_gen_dynamic_svereg_xml to gdbstub64.c | 44 | hw/rtc/twl92230: Use int64_t for sec_offset and alm_sec |
34 | target/arm: Split out output_vector_union_type | 45 | hw/rtc/aspeed_rtc: Use 64-bit offset for holding time_t difference |
35 | target/arm: Simplify register counting in arm_gen_dynamic_svereg_xml | 46 | rtc: Use time_t for passing and returning time offsets |
36 | target/arm: Hoist pred_width in arm_gen_dynamic_svereg_xml | 47 | target/arm: Do all "ARM_FEATURE_X implies Y" checks in post_init |
37 | target/arm: Fix svep width in arm_gen_dynamic_svereg_xml | 48 | hw/arm/armv7m: Add mpu-ns-regions and mpu-s-regions properties |
38 | target/arm: Add name argument to output_vector_union_type | 49 | hw/arm: Set number of MPU regions correctly for an505, an521, an524 |
39 | target/arm: Simplify iteration over bit widths | ||
40 | target/arm: Create pauth_ptr_mask | ||
41 | target/arm: Implement gdbstub pauth extension | ||
42 | target/arm: Implement gdbstub m-profile systemreg and secext | ||
43 | target/arm: Handle m-profile in arm_is_secure | ||
44 | target/arm: Stub arm_hcr_el2_eff for m-profile | ||
45 | target/arm: Diagnose incorrect usage of arm_is_secure subroutines | ||
46 | target/arm: Rewrite check_s2_mmu_setup | ||
47 | 50 | ||
48 | qianfan Zhao (2): | 51 | Richard Henderson (9): |
49 | hw: allwinner-i2c: Fix TWI_CNTR_INT_FLAG on SUN6i SoCs | 52 | target/arm: Reduce dcz_blocksize to uint8_t |
50 | hw: arm: allwinner-h3: Fix and complete H3 i2c devices | 53 | target/arm: Allow cpu to configure GM blocksize |
54 | target/arm: Support more GM blocksizes | ||
55 | target/arm: When tag memory is not present, set MTE=1 | ||
56 | target/arm: Introduce make_ccsidr64 | ||
57 | target/arm: Apply access checks to neoverse-n1 special registers | ||
58 | target/arm: Apply access checks to neoverse-v1 special registers | ||
59 | target/arm: Suppress FEAT_TRBE (Trace Buffer Extension) | ||
60 | target/arm: Implement FEAT_HPDS2 as a no-op | ||
51 | 61 | ||
52 | configs/targets/aarch64-linux-user.mak | 2 +- | 62 | docs/system/arm/emulation.rst | 2 + |
53 | configs/targets/aarch64-softmmu.mak | 2 +- | 63 | include/hw/arm/armsse.h | 5 + |
54 | configs/targets/aarch64_be-linux-user.mak | 2 +- | 64 | include/hw/arm/armv7m.h | 8 + |
55 | include/hw/arm/allwinner-h3.h | 6 + | 65 | include/hw/arm/fsl-imx6ul.h | 158 ++++++++++++++++--- |
56 | include/hw/i2c/allwinner-i2c.h | 6 + | 66 | include/hw/arm/fsl-imx7.h | 338 ++++++++++++++++++++++++++++++----------- |
57 | include/hw/loader.h | 19 ++ | 67 | include/hw/misc/imx7_src.h | 66 ++++++++ |
58 | target/arm/cpu.h | 17 +- | 68 | include/hw/rtc/aspeed_rtc.h | 2 +- |
59 | target/arm/internals.h | 34 +++- | 69 | include/sysemu/rtc.h | 4 +- |
60 | hw/arm/allwinner-h3.c | 29 +++- | 70 | target/arm/cpregs.h | 2 + |
61 | hw/arm/boot.c | 6 + | 71 | target/arm/cpu.h | 5 +- |
62 | hw/core/loader.c | 91 ++++++++++ | 72 | target/arm/internals.h | 6 - |
63 | hw/i2c/allwinner-i2c.c | 26 ++- | 73 | target/arm/tcg/translate.h | 2 + |
64 | target/arm/gdbstub.c | 278 ++++++++++++++++++------------ | 74 | hw/arm/armsse.c | 16 ++ |
65 | target/arm/gdbstub64.c | 175 ++++++++++++++++++- | 75 | hw/arm/armv7m.c | 21 +++ |
66 | target/arm/helper.c | 3 + | 76 | hw/arm/fsl-imx6ul.c | 174 +++++++++++++-------- |
67 | target/arm/ptw.c | 173 +++++++++++-------- | 77 | hw/arm/fsl-imx7.c | 201 +++++++++++++++++++----- |
68 | target/arm/tcg/m_helper.c | 90 +++++----- | 78 | hw/arm/mps2-tz.c | 29 ++++ |
69 | target/arm/tcg/pauth_helper.c | 26 ++- | 79 | hw/misc/imx7_src.c | 276 +++++++++++++++++++++++++++++++++ |
70 | gdb-xml/aarch64-pauth.xml | 15 ++ | 80 | hw/rtc/aspeed_rtc.c | 5 +- |
71 | 19 files changed, 742 insertions(+), 258 deletions(-) | 81 | hw/rtc/m48t59.c | 2 +- |
72 | create mode 100644 gdb-xml/aarch64-pauth.xml | 82 | hw/rtc/twl92230.c | 4 +- |
83 | softmmu/rtc.c | 4 +- | ||
84 | target/arm/cpu.c | 207 ++++++++++++++----------- | ||
85 | target/arm/helper.c | 15 +- | ||
86 | target/arm/tcg/cpu32.c | 2 +- | ||
87 | target/arm/tcg/cpu64.c | 102 +++++++++---- | ||
88 | target/arm/tcg/helper-a64.c | 9 ++ | ||
89 | target/arm/tcg/mte_helper.c | 90 ++++++++--- | ||
90 | target/arm/tcg/translate-a64.c | 5 +- | ||
91 | hw/misc/meson.build | 1 + | ||
92 | hw/misc/trace-events | 4 + | ||
93 | 31 files changed, 1393 insertions(+), 372 deletions(-) | ||
94 | create mode 100644 include/hw/misc/imx7_src.h | ||
95 | create mode 100644 hw/misc/imx7_src.c | ||
96 | diff view generated by jsdifflib |
1 | From: Richard Henderson <richard.henderson@linaro.org> | 1 | From: Richard Henderson <richard.henderson@linaro.org> |
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2 | 2 | ||
3 | In several places we use arm_is_secure_below_el3 and | 3 | This value is only 4 bits wide. |
4 | arm_is_el3_or_mon separately from arm_is_secure. | ||
5 | These functions make no sense for m-profile, and | ||
6 | would indicate prior incorrect feature testing. | ||
7 | 4 | ||
8 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | 5 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> |
6 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | ||
9 | Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> | 7 | Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> |
10 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | 8 | Message-id: 20230811214031.171020-2-richard.henderson@linaro.org |
11 | Message-id: 20230227225832.816605-4-richard.henderson@linaro.org | ||
12 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 9 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
13 | --- | 10 | --- |
14 | target/arm/cpu.h | 5 ++++- | 11 | target/arm/cpu.h | 3 ++- |
15 | 1 file changed, 4 insertions(+), 1 deletion(-) | 12 | 1 file changed, 2 insertions(+), 1 deletion(-) |
16 | 13 | ||
17 | diff --git a/target/arm/cpu.h b/target/arm/cpu.h | 14 | diff --git a/target/arm/cpu.h b/target/arm/cpu.h |
18 | index XXXXXXX..XXXXXXX 100644 | 15 | index XXXXXXX..XXXXXXX 100644 |
19 | --- a/target/arm/cpu.h | 16 | --- a/target/arm/cpu.h |
20 | +++ b/target/arm/cpu.h | 17 | +++ b/target/arm/cpu.h |
21 | @@ -XXX,XX +XXX,XX @@ static inline int arm_feature(CPUARMState *env, int feature) | 18 | @@ -XXX,XX +XXX,XX @@ struct ArchCPU { |
22 | void arm_cpu_finalize_features(ARMCPU *cpu, Error **errp); | 19 | bool prop_lpa2; |
23 | 20 | ||
24 | #if !defined(CONFIG_USER_ONLY) | 21 | /* DCZ blocksize, in log_2(words), ie low 4 bits of DCZID_EL0 */ |
25 | -/* Return true if exception levels below EL3 are in secure state, | 22 | - uint32_t dcz_blocksize; |
26 | +/* | 23 | + uint8_t dcz_blocksize; |
27 | + * Return true if exception levels below EL3 are in secure state, | 24 | + |
28 | * or would be following an exception return to that level. | 25 | uint64_t rvbar_prop; /* Property/input signals. */ |
29 | * Unlike arm_is_secure() (which is always a question about the | 26 | |
30 | * _current_ state of the CPU) this doesn't care about the current | 27 | /* Configurable aspects of GIC cpu interface (which is part of the CPU) */ |
31 | @@ -XXX,XX +XXX,XX @@ void arm_cpu_finalize_features(ARMCPU *cpu, Error **errp); | ||
32 | */ | ||
33 | static inline bool arm_is_secure_below_el3(CPUARMState *env) | ||
34 | { | ||
35 | + assert(!arm_feature(env, ARM_FEATURE_M)); | ||
36 | if (arm_feature(env, ARM_FEATURE_EL3)) { | ||
37 | return !(env->cp15.scr_el3 & SCR_NS); | ||
38 | } else { | ||
39 | @@ -XXX,XX +XXX,XX @@ static inline bool arm_is_secure_below_el3(CPUARMState *env) | ||
40 | /* Return true if the CPU is AArch64 EL3 or AArch32 Mon */ | ||
41 | static inline bool arm_is_el3_or_mon(CPUARMState *env) | ||
42 | { | ||
43 | + assert(!arm_feature(env, ARM_FEATURE_M)); | ||
44 | if (arm_feature(env, ARM_FEATURE_EL3)) { | ||
45 | if (is_a64(env) && extract32(env->pstate, 2, 2) == 3) { | ||
46 | /* CPU currently in AArch64 state and EL3 */ | ||
47 | -- | 28 | -- |
48 | 2.34.1 | 29 | 2.34.1 |
49 | 30 | ||
50 | 31 | diff view generated by jsdifflib |
1 | From: Richard Henderson <richard.henderson@linaro.org> | 1 | From: Richard Henderson <richard.henderson@linaro.org> |
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2 | 2 | ||
3 | The function is only used for aarch64, so move it to the | 3 | Previously we hard-coded the blocksize with GMID_EL1_BS. |
4 | file that has the other aarch64 gdbstub stuff. Move the | 4 | But the value we choose for -cpu max does not match the |
5 | declaration to internals.h. | 5 | value that cortex-a710 uses. |
6 | 6 | ||
7 | Reviewed-by: Fabiano Rosas <farosas@suse.de> | 7 | Mirror the way we handle dcz_blocksize. |
8 | Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> | 8 | |
9 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
9 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | 10 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> |
10 | Message-id: 20230227213329.793795-4-richard.henderson@linaro.org | 11 | Message-id: 20230811214031.171020-3-richard.henderson@linaro.org |
11 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 12 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
12 | --- | 13 | --- |
13 | target/arm/cpu.h | 6 --- | 14 | target/arm/cpu.h | 2 ++ |
14 | target/arm/internals.h | 1 + | 15 | target/arm/internals.h | 6 ----- |
15 | target/arm/gdbstub.c | 120 ----------------------------------------- | 16 | target/arm/tcg/translate.h | 2 ++ |
16 | target/arm/gdbstub64.c | 118 ++++++++++++++++++++++++++++++++++++++++ | 17 | target/arm/helper.c | 11 +++++--- |
17 | 4 files changed, 119 insertions(+), 126 deletions(-) | 18 | target/arm/tcg/cpu64.c | 1 + |
19 | target/arm/tcg/mte_helper.c | 46 ++++++++++++++++++++++------------ | ||
20 | target/arm/tcg/translate-a64.c | 5 ++-- | ||
21 | 7 files changed, 45 insertions(+), 28 deletions(-) | ||
18 | 22 | ||
19 | diff --git a/target/arm/cpu.h b/target/arm/cpu.h | 23 | diff --git a/target/arm/cpu.h b/target/arm/cpu.h |
20 | index XXXXXXX..XXXXXXX 100644 | 24 | index XXXXXXX..XXXXXXX 100644 |
21 | --- a/target/arm/cpu.h | 25 | --- a/target/arm/cpu.h |
22 | +++ b/target/arm/cpu.h | 26 | +++ b/target/arm/cpu.h |
23 | @@ -XXX,XX +XXX,XX @@ hwaddr arm_cpu_get_phys_page_attrs_debug(CPUState *cpu, vaddr addr, | 27 | @@ -XXX,XX +XXX,XX @@ struct ArchCPU { |
24 | int arm_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg); | 28 | |
25 | int arm_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); | 29 | /* DCZ blocksize, in log_2(words), ie low 4 bits of DCZID_EL0 */ |
26 | 30 | uint8_t dcz_blocksize; | |
27 | -/* | 31 | + /* GM blocksize, in log_2(words), ie low 4 bits of GMID_EL0 */ |
28 | - * Helpers to dynamically generates XML descriptions of the sysregs | 32 | + uint8_t gm_blocksize; |
29 | - * and SVE registers. Returns the number of registers in each set. | 33 | |
30 | - */ | 34 | uint64_t rvbar_prop; /* Property/input signals. */ |
31 | -int arm_gen_dynamic_svereg_xml(CPUState *cpu, int base_reg); | 35 | |
32 | - | ||
33 | /* Returns the dynamically generated XML for the gdb stub. | ||
34 | * Returns a pointer to the XML contents for the specified XML file or NULL | ||
35 | * if the XML name doesn't match the predefined one. | ||
36 | diff --git a/target/arm/internals.h b/target/arm/internals.h | 36 | diff --git a/target/arm/internals.h b/target/arm/internals.h |
37 | index XXXXXXX..XXXXXXX 100644 | 37 | index XXXXXXX..XXXXXXX 100644 |
38 | --- a/target/arm/internals.h | 38 | --- a/target/arm/internals.h |
39 | +++ b/target/arm/internals.h | 39 | +++ b/target/arm/internals.h |
40 | @@ -XXX,XX +XXX,XX @@ static inline uint64_t pmu_counter_mask(CPUARMState *env) | 40 | @@ -XXX,XX +XXX,XX @@ void arm_log_exception(CPUState *cs); |
41 | |||
42 | #endif /* !CONFIG_USER_ONLY */ | ||
43 | |||
44 | -/* | ||
45 | - * The log2 of the words in the tag block, for GMID_EL1.BS. | ||
46 | - * The is the maximum, 256 bytes, which manipulates 64-bits of tags. | ||
47 | - */ | ||
48 | -#define GMID_EL1_BS 6 | ||
49 | - | ||
50 | /* | ||
51 | * SVE predicates are 1/8 the size of SVE vectors, and cannot use | ||
52 | * the same simd_desc() encoding due to restrictions on size. | ||
53 | diff --git a/target/arm/tcg/translate.h b/target/arm/tcg/translate.h | ||
54 | index XXXXXXX..XXXXXXX 100644 | ||
55 | --- a/target/arm/tcg/translate.h | ||
56 | +++ b/target/arm/tcg/translate.h | ||
57 | @@ -XXX,XX +XXX,XX @@ typedef struct DisasContext { | ||
58 | int8_t btype; | ||
59 | /* A copy of cpu->dcz_blocksize. */ | ||
60 | uint8_t dcz_blocksize; | ||
61 | + /* A copy of cpu->gm_blocksize. */ | ||
62 | + uint8_t gm_blocksize; | ||
63 | /* True if this page is guarded. */ | ||
64 | bool guarded_page; | ||
65 | /* Bottom two bits of XScale c15_cpar coprocessor access control reg */ | ||
66 | diff --git a/target/arm/helper.c b/target/arm/helper.c | ||
67 | index XXXXXXX..XXXXXXX 100644 | ||
68 | --- a/target/arm/helper.c | ||
69 | +++ b/target/arm/helper.c | ||
70 | @@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo mte_reginfo[] = { | ||
71 | .opc0 = 3, .opc1 = 0, .crn = 1, .crm = 0, .opc2 = 6, | ||
72 | .access = PL1_RW, .accessfn = access_mte, | ||
73 | .fieldoffset = offsetof(CPUARMState, cp15.gcr_el1) }, | ||
74 | - { .name = "GMID_EL1", .state = ARM_CP_STATE_AA64, | ||
75 | - .opc0 = 3, .opc1 = 1, .crn = 0, .crm = 0, .opc2 = 4, | ||
76 | - .access = PL1_R, .accessfn = access_aa64_tid5, | ||
77 | - .type = ARM_CP_CONST, .resetvalue = GMID_EL1_BS }, | ||
78 | { .name = "TCO", .state = ARM_CP_STATE_AA64, | ||
79 | .opc0 = 3, .opc1 = 3, .crn = 4, .crm = 2, .opc2 = 7, | ||
80 | .type = ARM_CP_NO_RAW, | ||
81 | @@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu) | ||
82 | * then define only a RAZ/WI version of PSTATE.TCO. | ||
83 | */ | ||
84 | if (cpu_isar_feature(aa64_mte, cpu)) { | ||
85 | + ARMCPRegInfo gmid_reginfo = { | ||
86 | + .name = "GMID_EL1", .state = ARM_CP_STATE_AA64, | ||
87 | + .opc0 = 3, .opc1 = 1, .crn = 0, .crm = 0, .opc2 = 4, | ||
88 | + .access = PL1_R, .accessfn = access_aa64_tid5, | ||
89 | + .type = ARM_CP_CONST, .resetvalue = cpu->gm_blocksize, | ||
90 | + }; | ||
91 | + define_one_arm_cp_reg(cpu, &gmid_reginfo); | ||
92 | define_arm_cp_regs(cpu, mte_reginfo); | ||
93 | define_arm_cp_regs(cpu, mte_el0_cacheop_reginfo); | ||
94 | } else if (cpu_isar_feature(aa64_mte_insn_reg, cpu)) { | ||
95 | diff --git a/target/arm/tcg/cpu64.c b/target/arm/tcg/cpu64.c | ||
96 | index XXXXXXX..XXXXXXX 100644 | ||
97 | --- a/target/arm/tcg/cpu64.c | ||
98 | +++ b/target/arm/tcg/cpu64.c | ||
99 | @@ -XXX,XX +XXX,XX @@ void aarch64_max_tcg_initfn(Object *obj) | ||
100 | cpu->ctr = 0x80038003; /* 32 byte I and D cacheline size, VIPT icache */ | ||
101 | cpu->dcz_blocksize = 7; /* 512 bytes */ | ||
102 | #endif | ||
103 | + cpu->gm_blocksize = 6; /* 256 bytes */ | ||
104 | |||
105 | cpu->sve_vq.supported = MAKE_64BIT_MASK(0, ARM_MAX_VQ); | ||
106 | cpu->sme_vq.supported = SVE_VQ_POW2_MAP; | ||
107 | diff --git a/target/arm/tcg/mte_helper.c b/target/arm/tcg/mte_helper.c | ||
108 | index XXXXXXX..XXXXXXX 100644 | ||
109 | --- a/target/arm/tcg/mte_helper.c | ||
110 | +++ b/target/arm/tcg/mte_helper.c | ||
111 | @@ -XXX,XX +XXX,XX @@ void HELPER(st2g_stub)(CPUARMState *env, uint64_t ptr) | ||
112 | } | ||
41 | } | 113 | } |
42 | 114 | ||
43 | #ifdef TARGET_AARCH64 | 115 | -#define LDGM_STGM_SIZE (4 << GMID_EL1_BS) |
44 | +int arm_gen_dynamic_svereg_xml(CPUState *cpu, int base_reg); | 116 | - |
45 | int aarch64_gdb_get_sve_reg(CPUARMState *env, GByteArray *buf, int reg); | 117 | uint64_t HELPER(ldgm)(CPUARMState *env, uint64_t ptr) |
46 | int aarch64_gdb_set_sve_reg(CPUARMState *env, uint8_t *buf, int reg); | 118 | { |
47 | int aarch64_gdb_get_fpu_reg(CPUARMState *env, GByteArray *buf, int reg); | 119 | int mmu_idx = cpu_mmu_index(env, false); |
48 | diff --git a/target/arm/gdbstub.c b/target/arm/gdbstub.c | 120 | uintptr_t ra = GETPC(); |
49 | index XXXXXXX..XXXXXXX 100644 | 121 | + int gm_bs = env_archcpu(env)->gm_blocksize; |
50 | --- a/target/arm/gdbstub.c | 122 | + int gm_bs_bytes = 4 << gm_bs; |
51 | +++ b/target/arm/gdbstub.c | 123 | void *tag_mem; |
52 | @@ -XXX,XX +XXX,XX @@ static int arm_gen_dynamic_sysreg_xml(CPUState *cs, int base_reg) | 124 | |
53 | return cpu->dyn_sysreg_xml.num; | 125 | - ptr = QEMU_ALIGN_DOWN(ptr, LDGM_STGM_SIZE); |
126 | + ptr = QEMU_ALIGN_DOWN(ptr, gm_bs_bytes); | ||
127 | |||
128 | /* Trap if accessing an invalid page. */ | ||
129 | tag_mem = allocation_tag_mem(env, mmu_idx, ptr, MMU_DATA_LOAD, | ||
130 | - LDGM_STGM_SIZE, MMU_DATA_LOAD, | ||
131 | - LDGM_STGM_SIZE / (2 * TAG_GRANULE), ra); | ||
132 | + gm_bs_bytes, MMU_DATA_LOAD, | ||
133 | + gm_bs_bytes / (2 * TAG_GRANULE), ra); | ||
134 | |||
135 | /* The tag is squashed to zero if the page does not support tags. */ | ||
136 | if (!tag_mem) { | ||
137 | return 0; | ||
138 | } | ||
139 | |||
140 | - QEMU_BUILD_BUG_ON(GMID_EL1_BS != 6); | ||
141 | /* | ||
142 | - * We are loading 64-bits worth of tags. The ordering of elements | ||
143 | - * within the word corresponds to a 64-bit little-endian operation. | ||
144 | + * The ordering of elements within the word corresponds to | ||
145 | + * a little-endian operation. | ||
146 | */ | ||
147 | - return ldq_le_p(tag_mem); | ||
148 | + switch (gm_bs) { | ||
149 | + case 6: | ||
150 | + /* 256 bytes -> 16 tags -> 64 result bits */ | ||
151 | + return ldq_le_p(tag_mem); | ||
152 | + default: | ||
153 | + /* cpu configured with unsupported gm blocksize. */ | ||
154 | + g_assert_not_reached(); | ||
155 | + } | ||
54 | } | 156 | } |
55 | 157 | ||
56 | -struct TypeSize { | 158 | void HELPER(stgm)(CPUARMState *env, uint64_t ptr, uint64_t val) |
57 | - const char *gdb_type; | ||
58 | - int size; | ||
59 | - const char sz, suffix; | ||
60 | -}; | ||
61 | - | ||
62 | -static const struct TypeSize vec_lanes[] = { | ||
63 | - /* quads */ | ||
64 | - { "uint128", 128, 'q', 'u' }, | ||
65 | - { "int128", 128, 'q', 's' }, | ||
66 | - /* 64 bit */ | ||
67 | - { "ieee_double", 64, 'd', 'f' }, | ||
68 | - { "uint64", 64, 'd', 'u' }, | ||
69 | - { "int64", 64, 'd', 's' }, | ||
70 | - /* 32 bit */ | ||
71 | - { "ieee_single", 32, 's', 'f' }, | ||
72 | - { "uint32", 32, 's', 'u' }, | ||
73 | - { "int32", 32, 's', 's' }, | ||
74 | - /* 16 bit */ | ||
75 | - { "ieee_half", 16, 'h', 'f' }, | ||
76 | - { "uint16", 16, 'h', 'u' }, | ||
77 | - { "int16", 16, 'h', 's' }, | ||
78 | - /* bytes */ | ||
79 | - { "uint8", 8, 'b', 'u' }, | ||
80 | - { "int8", 8, 'b', 's' }, | ||
81 | -}; | ||
82 | - | ||
83 | - | ||
84 | -int arm_gen_dynamic_svereg_xml(CPUState *cs, int base_reg) | ||
85 | -{ | ||
86 | - ARMCPU *cpu = ARM_CPU(cs); | ||
87 | - GString *s = g_string_new(NULL); | ||
88 | - DynamicGDBXMLInfo *info = &cpu->dyn_svereg_xml; | ||
89 | - g_autoptr(GString) ts = g_string_new(""); | ||
90 | - int i, j, bits, reg_width = (cpu->sve_max_vq * 128); | ||
91 | - info->num = 0; | ||
92 | - g_string_printf(s, "<?xml version=\"1.0\"?>"); | ||
93 | - g_string_append_printf(s, "<!DOCTYPE target SYSTEM \"gdb-target.dtd\">"); | ||
94 | - g_string_append_printf(s, "<feature name=\"org.gnu.gdb.aarch64.sve\">"); | ||
95 | - | ||
96 | - /* First define types and totals in a whole VL */ | ||
97 | - for (i = 0; i < ARRAY_SIZE(vec_lanes); i++) { | ||
98 | - int count = reg_width / vec_lanes[i].size; | ||
99 | - g_string_printf(ts, "svev%c%c", vec_lanes[i].sz, vec_lanes[i].suffix); | ||
100 | - g_string_append_printf(s, | ||
101 | - "<vector id=\"%s\" type=\"%s\" count=\"%d\"/>", | ||
102 | - ts->str, vec_lanes[i].gdb_type, count); | ||
103 | - } | ||
104 | - /* | ||
105 | - * Now define a union for each size group containing unsigned and | ||
106 | - * signed and potentially float versions of each size from 128 to | ||
107 | - * 8 bits. | ||
108 | - */ | ||
109 | - for (bits = 128, i = 0; bits >= 8; bits /= 2, i++) { | ||
110 | - const char suf[] = { 'q', 'd', 's', 'h', 'b' }; | ||
111 | - g_string_append_printf(s, "<union id=\"svevn%c\">", suf[i]); | ||
112 | - for (j = 0; j < ARRAY_SIZE(vec_lanes); j++) { | ||
113 | - if (vec_lanes[j].size == bits) { | ||
114 | - g_string_append_printf(s, "<field name=\"%c\" type=\"svev%c%c\"/>", | ||
115 | - vec_lanes[j].suffix, | ||
116 | - vec_lanes[j].sz, vec_lanes[j].suffix); | ||
117 | - } | ||
118 | - } | ||
119 | - g_string_append(s, "</union>"); | ||
120 | - } | ||
121 | - /* And now the final union of unions */ | ||
122 | - g_string_append(s, "<union id=\"svev\">"); | ||
123 | - for (bits = 128, i = 0; bits >= 8; bits /= 2, i++) { | ||
124 | - const char suf[] = { 'q', 'd', 's', 'h', 'b' }; | ||
125 | - g_string_append_printf(s, "<field name=\"%c\" type=\"svevn%c\"/>", | ||
126 | - suf[i], suf[i]); | ||
127 | - } | ||
128 | - g_string_append(s, "</union>"); | ||
129 | - | ||
130 | - /* Finally the sve prefix type */ | ||
131 | - g_string_append_printf(s, | ||
132 | - "<vector id=\"svep\" type=\"uint8\" count=\"%d\"/>", | ||
133 | - reg_width / 8); | ||
134 | - | ||
135 | - /* Then define each register in parts for each vq */ | ||
136 | - for (i = 0; i < 32; i++) { | ||
137 | - g_string_append_printf(s, | ||
138 | - "<reg name=\"z%d\" bitsize=\"%d\"" | ||
139 | - " regnum=\"%d\" type=\"svev\"/>", | ||
140 | - i, reg_width, base_reg++); | ||
141 | - info->num++; | ||
142 | - } | ||
143 | - /* fpscr & status registers */ | ||
144 | - g_string_append_printf(s, "<reg name=\"fpsr\" bitsize=\"32\"" | ||
145 | - " regnum=\"%d\" group=\"float\"" | ||
146 | - " type=\"int\"/>", base_reg++); | ||
147 | - g_string_append_printf(s, "<reg name=\"fpcr\" bitsize=\"32\"" | ||
148 | - " regnum=\"%d\" group=\"float\"" | ||
149 | - " type=\"int\"/>", base_reg++); | ||
150 | - info->num += 2; | ||
151 | - | ||
152 | - for (i = 0; i < 16; i++) { | ||
153 | - g_string_append_printf(s, | ||
154 | - "<reg name=\"p%d\" bitsize=\"%d\"" | ||
155 | - " regnum=\"%d\" type=\"svep\"/>", | ||
156 | - i, cpu->sve_max_vq * 16, base_reg++); | ||
157 | - info->num++; | ||
158 | - } | ||
159 | - g_string_append_printf(s, | ||
160 | - "<reg name=\"ffr\" bitsize=\"%d\"" | ||
161 | - " regnum=\"%d\" group=\"vector\"" | ||
162 | - " type=\"svep\"/>", | ||
163 | - cpu->sve_max_vq * 16, base_reg++); | ||
164 | - g_string_append_printf(s, | ||
165 | - "<reg name=\"vg\" bitsize=\"64\"" | ||
166 | - " regnum=\"%d\" type=\"int\"/>", | ||
167 | - base_reg++); | ||
168 | - info->num += 2; | ||
169 | - g_string_append_printf(s, "</feature>"); | ||
170 | - cpu->dyn_svereg_xml.desc = g_string_free(s, false); | ||
171 | - | ||
172 | - return cpu->dyn_svereg_xml.num; | ||
173 | -} | ||
174 | - | ||
175 | - | ||
176 | const char *arm_gdb_get_dynamic_xml(CPUState *cs, const char *xmlname) | ||
177 | { | 159 | { |
178 | ARMCPU *cpu = ARM_CPU(cs); | 160 | int mmu_idx = cpu_mmu_index(env, false); |
179 | diff --git a/target/arm/gdbstub64.c b/target/arm/gdbstub64.c | 161 | uintptr_t ra = GETPC(); |
180 | index XXXXXXX..XXXXXXX 100644 | 162 | + int gm_bs = env_archcpu(env)->gm_blocksize; |
181 | --- a/target/arm/gdbstub64.c | 163 | + int gm_bs_bytes = 4 << gm_bs; |
182 | +++ b/target/arm/gdbstub64.c | 164 | void *tag_mem; |
183 | @@ -XXX,XX +XXX,XX @@ int aarch64_gdb_set_sve_reg(CPUARMState *env, uint8_t *buf, int reg) | 165 | |
184 | 166 | - ptr = QEMU_ALIGN_DOWN(ptr, LDGM_STGM_SIZE); | |
185 | return 0; | 167 | + ptr = QEMU_ALIGN_DOWN(ptr, gm_bs_bytes); |
168 | |||
169 | /* Trap if accessing an invalid page. */ | ||
170 | tag_mem = allocation_tag_mem(env, mmu_idx, ptr, MMU_DATA_STORE, | ||
171 | - LDGM_STGM_SIZE, MMU_DATA_LOAD, | ||
172 | - LDGM_STGM_SIZE / (2 * TAG_GRANULE), ra); | ||
173 | + gm_bs_bytes, MMU_DATA_LOAD, | ||
174 | + gm_bs_bytes / (2 * TAG_GRANULE), ra); | ||
175 | |||
176 | /* | ||
177 | * Tag store only happens if the page support tags, | ||
178 | @@ -XXX,XX +XXX,XX @@ void HELPER(stgm)(CPUARMState *env, uint64_t ptr, uint64_t val) | ||
179 | return; | ||
180 | } | ||
181 | |||
182 | - QEMU_BUILD_BUG_ON(GMID_EL1_BS != 6); | ||
183 | /* | ||
184 | - * We are storing 64-bits worth of tags. The ordering of elements | ||
185 | - * within the word corresponds to a 64-bit little-endian operation. | ||
186 | + * The ordering of elements within the word corresponds to | ||
187 | + * a little-endian operation. | ||
188 | */ | ||
189 | - stq_le_p(tag_mem, val); | ||
190 | + switch (gm_bs) { | ||
191 | + case 6: | ||
192 | + stq_le_p(tag_mem, val); | ||
193 | + break; | ||
194 | + default: | ||
195 | + /* cpu configured with unsupported gm blocksize. */ | ||
196 | + g_assert_not_reached(); | ||
197 | + } | ||
186 | } | 198 | } |
187 | + | 199 | |
188 | +struct TypeSize { | 200 | void HELPER(stzgm_tags)(CPUARMState *env, uint64_t ptr, uint64_t val) |
189 | + const char *gdb_type; | 201 | diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c |
190 | + short size; | 202 | index XXXXXXX..XXXXXXX 100644 |
191 | + char sz, suffix; | 203 | --- a/target/arm/tcg/translate-a64.c |
192 | +}; | 204 | +++ b/target/arm/tcg/translate-a64.c |
193 | + | 205 | @@ -XXX,XX +XXX,XX @@ static bool trans_STGM(DisasContext *s, arg_ldst_tag *a) |
194 | +static const struct TypeSize vec_lanes[] = { | 206 | gen_helper_stgm(cpu_env, addr, tcg_rt); |
195 | + /* quads */ | 207 | } else { |
196 | + { "uint128", 128, 'q', 'u' }, | 208 | MMUAccessType acc = MMU_DATA_STORE; |
197 | + { "int128", 128, 'q', 's' }, | 209 | - int size = 4 << GMID_EL1_BS; |
198 | + /* 64 bit */ | 210 | + int size = 4 << s->gm_blocksize; |
199 | + { "ieee_double", 64, 'd', 'f' }, | 211 | |
200 | + { "uint64", 64, 'd', 'u' }, | 212 | clean_addr = clean_data_tbi(s, addr); |
201 | + { "int64", 64, 'd', 's' }, | 213 | tcg_gen_andi_i64(clean_addr, clean_addr, -size); |
202 | + /* 32 bit */ | 214 | @@ -XXX,XX +XXX,XX @@ static bool trans_LDGM(DisasContext *s, arg_ldst_tag *a) |
203 | + { "ieee_single", 32, 's', 'f' }, | 215 | gen_helper_ldgm(tcg_rt, cpu_env, addr); |
204 | + { "uint32", 32, 's', 'u' }, | 216 | } else { |
205 | + { "int32", 32, 's', 's' }, | 217 | MMUAccessType acc = MMU_DATA_LOAD; |
206 | + /* 16 bit */ | 218 | - int size = 4 << GMID_EL1_BS; |
207 | + { "ieee_half", 16, 'h', 'f' }, | 219 | + int size = 4 << s->gm_blocksize; |
208 | + { "uint16", 16, 'h', 'u' }, | 220 | |
209 | + { "int16", 16, 'h', 's' }, | 221 | clean_addr = clean_data_tbi(s, addr); |
210 | + /* bytes */ | 222 | tcg_gen_andi_i64(clean_addr, clean_addr, -size); |
211 | + { "uint8", 8, 'b', 'u' }, | 223 | @@ -XXX,XX +XXX,XX @@ static void aarch64_tr_init_disas_context(DisasContextBase *dcbase, |
212 | + { "int8", 8, 'b', 's' }, | 224 | dc->cp_regs = arm_cpu->cp_regs; |
213 | +}; | 225 | dc->features = env->features; |
214 | + | 226 | dc->dcz_blocksize = arm_cpu->dcz_blocksize; |
215 | +int arm_gen_dynamic_svereg_xml(CPUState *cs, int base_reg) | 227 | + dc->gm_blocksize = arm_cpu->gm_blocksize; |
216 | +{ | 228 | |
217 | + ARMCPU *cpu = ARM_CPU(cs); | 229 | #ifdef CONFIG_USER_ONLY |
218 | + GString *s = g_string_new(NULL); | 230 | /* In sve_probe_page, we assume TBI is enabled. */ |
219 | + DynamicGDBXMLInfo *info = &cpu->dyn_svereg_xml; | ||
220 | + g_autoptr(GString) ts = g_string_new(""); | ||
221 | + int i, j, bits, reg_width = (cpu->sve_max_vq * 128); | ||
222 | + info->num = 0; | ||
223 | + g_string_printf(s, "<?xml version=\"1.0\"?>"); | ||
224 | + g_string_append_printf(s, "<!DOCTYPE target SYSTEM \"gdb-target.dtd\">"); | ||
225 | + g_string_append_printf(s, "<feature name=\"org.gnu.gdb.aarch64.sve\">"); | ||
226 | + | ||
227 | + /* First define types and totals in a whole VL */ | ||
228 | + for (i = 0; i < ARRAY_SIZE(vec_lanes); i++) { | ||
229 | + int count = reg_width / vec_lanes[i].size; | ||
230 | + g_string_printf(ts, "svev%c%c", vec_lanes[i].sz, vec_lanes[i].suffix); | ||
231 | + g_string_append_printf(s, | ||
232 | + "<vector id=\"%s\" type=\"%s\" count=\"%d\"/>", | ||
233 | + ts->str, vec_lanes[i].gdb_type, count); | ||
234 | + } | ||
235 | + /* | ||
236 | + * Now define a union for each size group containing unsigned and | ||
237 | + * signed and potentially float versions of each size from 128 to | ||
238 | + * 8 bits. | ||
239 | + */ | ||
240 | + for (bits = 128, i = 0; bits >= 8; bits /= 2, i++) { | ||
241 | + const char suf[] = { 'q', 'd', 's', 'h', 'b' }; | ||
242 | + g_string_append_printf(s, "<union id=\"svevn%c\">", suf[i]); | ||
243 | + for (j = 0; j < ARRAY_SIZE(vec_lanes); j++) { | ||
244 | + if (vec_lanes[j].size == bits) { | ||
245 | + g_string_append_printf(s, "<field name=\"%c\" type=\"svev%c%c\"/>", | ||
246 | + vec_lanes[j].suffix, | ||
247 | + vec_lanes[j].sz, vec_lanes[j].suffix); | ||
248 | + } | ||
249 | + } | ||
250 | + g_string_append(s, "</union>"); | ||
251 | + } | ||
252 | + /* And now the final union of unions */ | ||
253 | + g_string_append(s, "<union id=\"svev\">"); | ||
254 | + for (bits = 128, i = 0; bits >= 8; bits /= 2, i++) { | ||
255 | + const char suf[] = { 'q', 'd', 's', 'h', 'b' }; | ||
256 | + g_string_append_printf(s, "<field name=\"%c\" type=\"svevn%c\"/>", | ||
257 | + suf[i], suf[i]); | ||
258 | + } | ||
259 | + g_string_append(s, "</union>"); | ||
260 | + | ||
261 | + /* Finally the sve prefix type */ | ||
262 | + g_string_append_printf(s, | ||
263 | + "<vector id=\"svep\" type=\"uint8\" count=\"%d\"/>", | ||
264 | + reg_width / 8); | ||
265 | + | ||
266 | + /* Then define each register in parts for each vq */ | ||
267 | + for (i = 0; i < 32; i++) { | ||
268 | + g_string_append_printf(s, | ||
269 | + "<reg name=\"z%d\" bitsize=\"%d\"" | ||
270 | + " regnum=\"%d\" type=\"svev\"/>", | ||
271 | + i, reg_width, base_reg++); | ||
272 | + info->num++; | ||
273 | + } | ||
274 | + /* fpscr & status registers */ | ||
275 | + g_string_append_printf(s, "<reg name=\"fpsr\" bitsize=\"32\"" | ||
276 | + " regnum=\"%d\" group=\"float\"" | ||
277 | + " type=\"int\"/>", base_reg++); | ||
278 | + g_string_append_printf(s, "<reg name=\"fpcr\" bitsize=\"32\"" | ||
279 | + " regnum=\"%d\" group=\"float\"" | ||
280 | + " type=\"int\"/>", base_reg++); | ||
281 | + info->num += 2; | ||
282 | + | ||
283 | + for (i = 0; i < 16; i++) { | ||
284 | + g_string_append_printf(s, | ||
285 | + "<reg name=\"p%d\" bitsize=\"%d\"" | ||
286 | + " regnum=\"%d\" type=\"svep\"/>", | ||
287 | + i, cpu->sve_max_vq * 16, base_reg++); | ||
288 | + info->num++; | ||
289 | + } | ||
290 | + g_string_append_printf(s, | ||
291 | + "<reg name=\"ffr\" bitsize=\"%d\"" | ||
292 | + " regnum=\"%d\" group=\"vector\"" | ||
293 | + " type=\"svep\"/>", | ||
294 | + cpu->sve_max_vq * 16, base_reg++); | ||
295 | + g_string_append_printf(s, | ||
296 | + "<reg name=\"vg\" bitsize=\"64\"" | ||
297 | + " regnum=\"%d\" type=\"int\"/>", | ||
298 | + base_reg++); | ||
299 | + info->num += 2; | ||
300 | + g_string_append_printf(s, "</feature>"); | ||
301 | + info->desc = g_string_free(s, false); | ||
302 | + | ||
303 | + return info->num; | ||
304 | +} | ||
305 | -- | 231 | -- |
306 | 2.34.1 | 232 | 2.34.1 |
307 | |||
308 | diff view generated by jsdifflib |
1 | From: Richard Henderson <richard.henderson@linaro.org> | 1 | From: Richard Henderson <richard.henderson@linaro.org> |
---|---|---|---|
2 | 2 | ||
3 | The upstream gdb xml only implements {MSP,PSP}{,_NS,S}, but | 3 | Support all of the easy GM block sizes. |
4 | go ahead and implement the other system registers as well. | 4 | Use direct memory operations, since the pointers are aligned. |
5 | 5 | ||
6 | Since there is significant overlap between the two, implement | 6 | While BS=2 (16 bytes, 1 tag) is a legal setting, that requires |
7 | them with common code. The only exception is the systemreg | 7 | an atomic store of one nibble. This is not difficult, but there |
8 | view of CONTROL, which merges the banked bits as per MRS. | 8 | is also no point in supporting it until required. |
9 | 9 | ||
10 | Signed-off-by: David Reiss <dreiss@meta.com> | 10 | Note that cortex-a710 sets GM blocksize to match its cacheline |
11 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | 11 | size of 64 bytes. I expect many implementations will also |
12 | Message-id: 20230227213329.793795-15-richard.henderson@linaro.org | 12 | match the cacheline, which makes 16 bytes very unlikely. |
13 | [rth: Substatial rewrite using enumerator and shared code.] | 13 | |
14 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | 14 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> |
15 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | 15 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> |
16 | Message-id: 20230811214031.171020-4-richard.henderson@linaro.org | ||
16 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 17 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
17 | --- | 18 | --- |
18 | target/arm/cpu.h | 2 + | 19 | target/arm/cpu.c | 18 +++++++++--- |
19 | target/arm/gdbstub.c | 178 +++++++++++++++++++++++++++++++++++++++++++ | 20 | target/arm/tcg/mte_helper.c | 56 +++++++++++++++++++++++++++++++------ |
20 | 2 files changed, 180 insertions(+) | 21 | 2 files changed, 62 insertions(+), 12 deletions(-) |
21 | 22 | ||
22 | diff --git a/target/arm/cpu.h b/target/arm/cpu.h | 23 | diff --git a/target/arm/cpu.c b/target/arm/cpu.c |
23 | index XXXXXXX..XXXXXXX 100644 | 24 | index XXXXXXX..XXXXXXX 100644 |
24 | --- a/target/arm/cpu.h | 25 | --- a/target/arm/cpu.c |
25 | +++ b/target/arm/cpu.h | 26 | +++ b/target/arm/cpu.c |
26 | @@ -XXX,XX +XXX,XX @@ struct ArchCPU { | 27 | @@ -XXX,XX +XXX,XX @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp) |
27 | 28 | ID_PFR1, VIRTUALIZATION, 0); | |
28 | DynamicGDBXMLInfo dyn_sysreg_xml; | 29 | } |
29 | DynamicGDBXMLInfo dyn_svereg_xml; | 30 | |
30 | + DynamicGDBXMLInfo dyn_m_systemreg_xml; | 31 | + if (cpu_isar_feature(aa64_mte, cpu)) { |
31 | + DynamicGDBXMLInfo dyn_m_secextreg_xml; | 32 | + /* |
32 | 33 | + * The architectural range of GM blocksize is 2-6, however qemu | |
33 | /* Timers used by the generic (architected) timer */ | 34 | + * doesn't support blocksize of 2 (see HELPER(ldgm)). |
34 | QEMUTimer *gt_timer[NUM_GTIMERS]; | 35 | + */ |
35 | diff --git a/target/arm/gdbstub.c b/target/arm/gdbstub.c | 36 | + if (tcg_enabled()) { |
37 | + assert(cpu->gm_blocksize >= 3 && cpu->gm_blocksize <= 6); | ||
38 | + } | ||
39 | + | ||
40 | #ifndef CONFIG_USER_ONLY | ||
41 | - if (cpu->tag_memory == NULL && cpu_isar_feature(aa64_mte, cpu)) { | ||
42 | /* | ||
43 | * Disable the MTE feature bits if we do not have tag-memory | ||
44 | * provided by the machine. | ||
45 | */ | ||
46 | - cpu->isar.id_aa64pfr1 = | ||
47 | - FIELD_DP64(cpu->isar.id_aa64pfr1, ID_AA64PFR1, MTE, 0); | ||
48 | - } | ||
49 | + if (cpu->tag_memory == NULL) { | ||
50 | + cpu->isar.id_aa64pfr1 = | ||
51 | + FIELD_DP64(cpu->isar.id_aa64pfr1, ID_AA64PFR1, MTE, 0); | ||
52 | + } | ||
53 | #endif | ||
54 | + } | ||
55 | |||
56 | if (tcg_enabled()) { | ||
57 | /* | ||
58 | diff --git a/target/arm/tcg/mte_helper.c b/target/arm/tcg/mte_helper.c | ||
36 | index XXXXXXX..XXXXXXX 100644 | 59 | index XXXXXXX..XXXXXXX 100644 |
37 | --- a/target/arm/gdbstub.c | 60 | --- a/target/arm/tcg/mte_helper.c |
38 | +++ b/target/arm/gdbstub.c | 61 | +++ b/target/arm/tcg/mte_helper.c |
39 | @@ -XXX,XX +XXX,XX @@ static int arm_gen_dynamic_sysreg_xml(CPUState *cs, int base_reg) | 62 | @@ -XXX,XX +XXX,XX @@ uint64_t HELPER(ldgm)(CPUARMState *env, uint64_t ptr) |
40 | return cpu->dyn_sysreg_xml.num; | 63 | int gm_bs = env_archcpu(env)->gm_blocksize; |
64 | int gm_bs_bytes = 4 << gm_bs; | ||
65 | void *tag_mem; | ||
66 | + uint64_t ret; | ||
67 | + int shift; | ||
68 | |||
69 | ptr = QEMU_ALIGN_DOWN(ptr, gm_bs_bytes); | ||
70 | |||
71 | @@ -XXX,XX +XXX,XX @@ uint64_t HELPER(ldgm)(CPUARMState *env, uint64_t ptr) | ||
72 | |||
73 | /* | ||
74 | * The ordering of elements within the word corresponds to | ||
75 | - * a little-endian operation. | ||
76 | + * a little-endian operation. Computation of shift comes from | ||
77 | + * | ||
78 | + * index = address<LOG2_TAG_GRANULE+3:LOG2_TAG_GRANULE> | ||
79 | + * data<index*4+3:index*4> = tag | ||
80 | + * | ||
81 | + * Because of the alignment of ptr above, BS=6 has shift=0. | ||
82 | + * All memory operations are aligned. Defer support for BS=2, | ||
83 | + * requiring insertion or extraction of a nibble, until we | ||
84 | + * support a cpu that requires it. | ||
85 | */ | ||
86 | switch (gm_bs) { | ||
87 | + case 3: | ||
88 | + /* 32 bytes -> 2 tags -> 8 result bits */ | ||
89 | + ret = *(uint8_t *)tag_mem; | ||
90 | + break; | ||
91 | + case 4: | ||
92 | + /* 64 bytes -> 4 tags -> 16 result bits */ | ||
93 | + ret = cpu_to_le16(*(uint16_t *)tag_mem); | ||
94 | + break; | ||
95 | + case 5: | ||
96 | + /* 128 bytes -> 8 tags -> 32 result bits */ | ||
97 | + ret = cpu_to_le32(*(uint32_t *)tag_mem); | ||
98 | + break; | ||
99 | case 6: | ||
100 | /* 256 bytes -> 16 tags -> 64 result bits */ | ||
101 | - return ldq_le_p(tag_mem); | ||
102 | + return cpu_to_le64(*(uint64_t *)tag_mem); | ||
103 | default: | ||
104 | - /* cpu configured with unsupported gm blocksize. */ | ||
105 | + /* | ||
106 | + * CPU configured with unsupported/invalid gm blocksize. | ||
107 | + * This is detected early in arm_cpu_realizefn. | ||
108 | + */ | ||
109 | g_assert_not_reached(); | ||
110 | } | ||
111 | + shift = extract64(ptr, LOG2_TAG_GRANULE, 4) * 4; | ||
112 | + return ret << shift; | ||
41 | } | 113 | } |
42 | 114 | ||
43 | +typedef enum { | 115 | void HELPER(stgm)(CPUARMState *env, uint64_t ptr, uint64_t val) |
44 | + M_SYSREG_MSP, | 116 | @@ -XXX,XX +XXX,XX @@ void HELPER(stgm)(CPUARMState *env, uint64_t ptr, uint64_t val) |
45 | + M_SYSREG_PSP, | 117 | int gm_bs = env_archcpu(env)->gm_blocksize; |
46 | + M_SYSREG_PRIMASK, | 118 | int gm_bs_bytes = 4 << gm_bs; |
47 | + M_SYSREG_CONTROL, | 119 | void *tag_mem; |
48 | + M_SYSREG_BASEPRI, | 120 | + int shift; |
49 | + M_SYSREG_FAULTMASK, | 121 | |
50 | + M_SYSREG_MSPLIM, | 122 | ptr = QEMU_ALIGN_DOWN(ptr, gm_bs_bytes); |
51 | + M_SYSREG_PSPLIM, | 123 | |
52 | +} MProfileSysreg; | 124 | @@ -XXX,XX +XXX,XX @@ void HELPER(stgm)(CPUARMState *env, uint64_t ptr, uint64_t val) |
53 | + | 125 | return; |
54 | +static const struct { | 126 | } |
55 | + const char *name; | 127 | |
56 | + int feature; | 128 | - /* |
57 | +} m_sysreg_def[] = { | 129 | - * The ordering of elements within the word corresponds to |
58 | + [M_SYSREG_MSP] = { "msp", ARM_FEATURE_M }, | 130 | - * a little-endian operation. |
59 | + [M_SYSREG_PSP] = { "psp", ARM_FEATURE_M }, | 131 | - */ |
60 | + [M_SYSREG_PRIMASK] = { "primask", ARM_FEATURE_M }, | 132 | + /* See LDGM for comments on BS and on shift. */ |
61 | + [M_SYSREG_CONTROL] = { "control", ARM_FEATURE_M }, | 133 | + shift = extract64(ptr, LOG2_TAG_GRANULE, 4) * 4; |
62 | + [M_SYSREG_BASEPRI] = { "basepri", ARM_FEATURE_M_MAIN }, | 134 | + val >>= shift; |
63 | + [M_SYSREG_FAULTMASK] = { "faultmask", ARM_FEATURE_M_MAIN }, | 135 | switch (gm_bs) { |
64 | + [M_SYSREG_MSPLIM] = { "msplim", ARM_FEATURE_V8 }, | 136 | + case 3: |
65 | + [M_SYSREG_PSPLIM] = { "psplim", ARM_FEATURE_V8 }, | 137 | + /* 32 bytes -> 2 tags -> 8 result bits */ |
66 | +}; | 138 | + *(uint8_t *)tag_mem = val; |
67 | + | ||
68 | +static uint32_t *m_sysreg_ptr(CPUARMState *env, MProfileSysreg reg, bool sec) | ||
69 | +{ | ||
70 | + uint32_t *ptr; | ||
71 | + | ||
72 | + switch (reg) { | ||
73 | + case M_SYSREG_MSP: | ||
74 | + ptr = arm_v7m_get_sp_ptr(env, sec, false, true); | ||
75 | + break; | 139 | + break; |
76 | + case M_SYSREG_PSP: | 140 | + case 4: |
77 | + ptr = arm_v7m_get_sp_ptr(env, sec, true, true); | 141 | + /* 64 bytes -> 4 tags -> 16 result bits */ |
142 | + *(uint16_t *)tag_mem = cpu_to_le16(val); | ||
78 | + break; | 143 | + break; |
79 | + case M_SYSREG_MSPLIM: | 144 | + case 5: |
80 | + ptr = &env->v7m.msplim[sec]; | 145 | + /* 128 bytes -> 8 tags -> 32 result bits */ |
146 | + *(uint32_t *)tag_mem = cpu_to_le32(val); | ||
81 | + break; | 147 | + break; |
82 | + case M_SYSREG_PSPLIM: | 148 | case 6: |
83 | + ptr = &env->v7m.psplim[sec]; | 149 | - stq_le_p(tag_mem, val); |
84 | + break; | 150 | + /* 256 bytes -> 16 tags -> 64 result bits */ |
85 | + case M_SYSREG_PRIMASK: | 151 | + *(uint64_t *)tag_mem = cpu_to_le64(val); |
86 | + ptr = &env->v7m.primask[sec]; | 152 | break; |
87 | + break; | 153 | default: |
88 | + case M_SYSREG_BASEPRI: | 154 | /* cpu configured with unsupported gm blocksize. */ |
89 | + ptr = &env->v7m.basepri[sec]; | ||
90 | + break; | ||
91 | + case M_SYSREG_FAULTMASK: | ||
92 | + ptr = &env->v7m.faultmask[sec]; | ||
93 | + break; | ||
94 | + case M_SYSREG_CONTROL: | ||
95 | + ptr = &env->v7m.control[sec]; | ||
96 | + break; | ||
97 | + default: | ||
98 | + return NULL; | ||
99 | + } | ||
100 | + return arm_feature(env, m_sysreg_def[reg].feature) ? ptr : NULL; | ||
101 | +} | ||
102 | + | ||
103 | +static int m_sysreg_get(CPUARMState *env, GByteArray *buf, | ||
104 | + MProfileSysreg reg, bool secure) | ||
105 | +{ | ||
106 | + uint32_t *ptr = m_sysreg_ptr(env, reg, secure); | ||
107 | + | ||
108 | + if (ptr == NULL) { | ||
109 | + return 0; | ||
110 | + } | ||
111 | + return gdb_get_reg32(buf, *ptr); | ||
112 | +} | ||
113 | + | ||
114 | +static int arm_gdb_get_m_systemreg(CPUARMState *env, GByteArray *buf, int reg) | ||
115 | +{ | ||
116 | + /* | ||
117 | + * Here, we emulate MRS instruction, where CONTROL has a mix of | ||
118 | + * banked and non-banked bits. | ||
119 | + */ | ||
120 | + if (reg == M_SYSREG_CONTROL) { | ||
121 | + return gdb_get_reg32(buf, arm_v7m_mrs_control(env, env->v7m.secure)); | ||
122 | + } | ||
123 | + return m_sysreg_get(env, buf, reg, env->v7m.secure); | ||
124 | +} | ||
125 | + | ||
126 | +static int arm_gdb_set_m_systemreg(CPUARMState *env, uint8_t *buf, int reg) | ||
127 | +{ | ||
128 | + return 0; /* TODO */ | ||
129 | +} | ||
130 | + | ||
131 | +static int arm_gen_dynamic_m_systemreg_xml(CPUState *cs, int orig_base_reg) | ||
132 | +{ | ||
133 | + ARMCPU *cpu = ARM_CPU(cs); | ||
134 | + CPUARMState *env = &cpu->env; | ||
135 | + GString *s = g_string_new(NULL); | ||
136 | + int base_reg = orig_base_reg; | ||
137 | + int i; | ||
138 | + | ||
139 | + g_string_printf(s, "<?xml version=\"1.0\"?>"); | ||
140 | + g_string_append_printf(s, "<!DOCTYPE target SYSTEM \"gdb-target.dtd\">"); | ||
141 | + g_string_append_printf(s, "<feature name=\"org.gnu.gdb.arm.m-system\">\n"); | ||
142 | + | ||
143 | + for (i = 0; i < ARRAY_SIZE(m_sysreg_def); i++) { | ||
144 | + if (arm_feature(env, m_sysreg_def[i].feature)) { | ||
145 | + g_string_append_printf(s, | ||
146 | + "<reg name=\"%s\" bitsize=\"32\" regnum=\"%d\"/>\n", | ||
147 | + m_sysreg_def[i].name, base_reg++); | ||
148 | + } | ||
149 | + } | ||
150 | + | ||
151 | + g_string_append_printf(s, "</feature>"); | ||
152 | + cpu->dyn_m_systemreg_xml.desc = g_string_free(s, false); | ||
153 | + cpu->dyn_m_systemreg_xml.num = base_reg - orig_base_reg; | ||
154 | + | ||
155 | + return cpu->dyn_m_systemreg_xml.num; | ||
156 | +} | ||
157 | + | ||
158 | +#ifndef CONFIG_USER_ONLY | ||
159 | +/* | ||
160 | + * For user-only, we see the non-secure registers via m_systemreg above. | ||
161 | + * For secext, encode the non-secure view as even and secure view as odd. | ||
162 | + */ | ||
163 | +static int arm_gdb_get_m_secextreg(CPUARMState *env, GByteArray *buf, int reg) | ||
164 | +{ | ||
165 | + return m_sysreg_get(env, buf, reg >> 1, reg & 1); | ||
166 | +} | ||
167 | + | ||
168 | +static int arm_gdb_set_m_secextreg(CPUARMState *env, uint8_t *buf, int reg) | ||
169 | +{ | ||
170 | + return 0; /* TODO */ | ||
171 | +} | ||
172 | + | ||
173 | +static int arm_gen_dynamic_m_secextreg_xml(CPUState *cs, int orig_base_reg) | ||
174 | +{ | ||
175 | + ARMCPU *cpu = ARM_CPU(cs); | ||
176 | + GString *s = g_string_new(NULL); | ||
177 | + int base_reg = orig_base_reg; | ||
178 | + int i; | ||
179 | + | ||
180 | + g_string_printf(s, "<?xml version=\"1.0\"?>"); | ||
181 | + g_string_append_printf(s, "<!DOCTYPE target SYSTEM \"gdb-target.dtd\">"); | ||
182 | + g_string_append_printf(s, "<feature name=\"org.gnu.gdb.arm.secext\">\n"); | ||
183 | + | ||
184 | + for (i = 0; i < ARRAY_SIZE(m_sysreg_def); i++) { | ||
185 | + g_string_append_printf(s, | ||
186 | + "<reg name=\"%s_ns\" bitsize=\"32\" regnum=\"%d\"/>\n", | ||
187 | + m_sysreg_def[i].name, base_reg++); | ||
188 | + g_string_append_printf(s, | ||
189 | + "<reg name=\"%s_s\" bitsize=\"32\" regnum=\"%d\"/>\n", | ||
190 | + m_sysreg_def[i].name, base_reg++); | ||
191 | + } | ||
192 | + | ||
193 | + g_string_append_printf(s, "</feature>"); | ||
194 | + cpu->dyn_m_secextreg_xml.desc = g_string_free(s, false); | ||
195 | + cpu->dyn_m_secextreg_xml.num = base_reg - orig_base_reg; | ||
196 | + | ||
197 | + return cpu->dyn_m_secextreg_xml.num; | ||
198 | +} | ||
199 | +#endif | ||
200 | + | ||
201 | const char *arm_gdb_get_dynamic_xml(CPUState *cs, const char *xmlname) | ||
202 | { | ||
203 | ARMCPU *cpu = ARM_CPU(cs); | ||
204 | @@ -XXX,XX +XXX,XX @@ const char *arm_gdb_get_dynamic_xml(CPUState *cs, const char *xmlname) | ||
205 | return cpu->dyn_sysreg_xml.desc; | ||
206 | } else if (strcmp(xmlname, "sve-registers.xml") == 0) { | ||
207 | return cpu->dyn_svereg_xml.desc; | ||
208 | + } else if (strcmp(xmlname, "arm-m-system.xml") == 0) { | ||
209 | + return cpu->dyn_m_systemreg_xml.desc; | ||
210 | +#ifndef CONFIG_USER_ONLY | ||
211 | + } else if (strcmp(xmlname, "arm-m-secext.xml") == 0) { | ||
212 | + return cpu->dyn_m_secextreg_xml.desc; | ||
213 | +#endif | ||
214 | } | ||
215 | return NULL; | ||
216 | } | ||
217 | @@ -XXX,XX +XXX,XX @@ void arm_cpu_register_gdb_regs_for_features(ARMCPU *cpu) | ||
218 | arm_gen_dynamic_sysreg_xml(cs, cs->gdb_num_regs), | ||
219 | "system-registers.xml", 0); | ||
220 | |||
221 | + if (arm_feature(env, ARM_FEATURE_M)) { | ||
222 | + gdb_register_coprocessor(cs, | ||
223 | + arm_gdb_get_m_systemreg, arm_gdb_set_m_systemreg, | ||
224 | + arm_gen_dynamic_m_systemreg_xml(cs, cs->gdb_num_regs), | ||
225 | + "arm-m-system.xml", 0); | ||
226 | +#ifndef CONFIG_USER_ONLY | ||
227 | + if (arm_feature(env, ARM_FEATURE_M_SECURITY)) { | ||
228 | + gdb_register_coprocessor(cs, | ||
229 | + arm_gdb_get_m_secextreg, arm_gdb_set_m_secextreg, | ||
230 | + arm_gen_dynamic_m_secextreg_xml(cs, cs->gdb_num_regs), | ||
231 | + "arm-m-secext.xml", 0); | ||
232 | + } | ||
233 | +#endif | ||
234 | + } | ||
235 | } | ||
236 | -- | 155 | -- |
237 | 2.34.1 | 156 | 2.34.1 | diff view generated by jsdifflib |
1 | From: Richard Henderson <richard.henderson@linaro.org> | 1 | From: Richard Henderson <richard.henderson@linaro.org> |
---|---|---|---|
2 | 2 | ||
3 | Order suf[] by the log8 of the width. | 3 | When the cpu support MTE, but the system does not, reduce cpu |
4 | Use ARRAY_SIZE instead of hard-coding 128. | 4 | support to user instructions at EL0 instead of completely |
5 | disabling MTE. If we encounter a cpu implementation which does | ||
6 | something else, we can revisit this setting. | ||
5 | 7 | ||
6 | This changes the order of the union definitions, | 8 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> |
7 | but retains the order of the union-of-union members. | ||
8 | |||
9 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | 9 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> |
10 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | 10 | Message-id: 20230811214031.171020-5-richard.henderson@linaro.org |
11 | Message-id: 20230227213329.793795-10-richard.henderson@linaro.org | ||
12 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 11 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
13 | --- | 12 | --- |
14 | target/arm/gdbstub64.c | 10 ++++++---- | 13 | target/arm/cpu.c | 7 ++++--- |
15 | 1 file changed, 6 insertions(+), 4 deletions(-) | 14 | 1 file changed, 4 insertions(+), 3 deletions(-) |
16 | 15 | ||
17 | diff --git a/target/arm/gdbstub64.c b/target/arm/gdbstub64.c | 16 | diff --git a/target/arm/cpu.c b/target/arm/cpu.c |
18 | index XXXXXXX..XXXXXXX 100644 | 17 | index XXXXXXX..XXXXXXX 100644 |
19 | --- a/target/arm/gdbstub64.c | 18 | --- a/target/arm/cpu.c |
20 | +++ b/target/arm/gdbstub64.c | 19 | +++ b/target/arm/cpu.c |
21 | @@ -XXX,XX +XXX,XX @@ static void output_vector_union_type(GString *s, int reg_width, | 20 | @@ -XXX,XX +XXX,XX @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp) |
22 | { "int8", 8, 'b', 's' }, | 21 | |
23 | }; | 22 | #ifndef CONFIG_USER_ONLY |
24 | 23 | /* | |
25 | - static const char suf[] = { 'q', 'd', 's', 'h', 'b' }; | 24 | - * Disable the MTE feature bits if we do not have tag-memory |
26 | - int i, j, bits; | 25 | - * provided by the machine. |
27 | + static const char suf[] = { 'b', 'h', 's', 'd', 'q' }; | 26 | + * If we do not have tag-memory provided by the machine, |
28 | + int i, j; | 27 | + * reduce MTE support to instructions enabled at EL0. |
29 | 28 | + * This matches Cortex-A710 BROADCASTMTE input being LOW. | |
30 | /* First define types and totals in a whole VL */ | 29 | */ |
31 | for (i = 0; i < ARRAY_SIZE(vec_lanes); i++) { | 30 | if (cpu->tag_memory == NULL) { |
32 | @@ -XXX,XX +XXX,XX @@ static void output_vector_union_type(GString *s, int reg_width, | 31 | cpu->isar.id_aa64pfr1 = |
33 | * signed and potentially float versions of each size from 128 to | 32 | - FIELD_DP64(cpu->isar.id_aa64pfr1, ID_AA64PFR1, MTE, 0); |
34 | * 8 bits. | 33 | + FIELD_DP64(cpu->isar.id_aa64pfr1, ID_AA64PFR1, MTE, 1); |
35 | */ | 34 | } |
36 | - for (bits = 128, i = 0; bits >= 8; bits /= 2, i++) { | 35 | #endif |
37 | + for (i = 0; i < ARRAY_SIZE(suf); i++) { | ||
38 | + int bits = 8 << i; | ||
39 | + | ||
40 | g_string_append_printf(s, "<union id=\"%sn%c\">", name, suf[i]); | ||
41 | for (j = 0; j < ARRAY_SIZE(vec_lanes); j++) { | ||
42 | if (vec_lanes[j].size == bits) { | ||
43 | @@ -XXX,XX +XXX,XX @@ static void output_vector_union_type(GString *s, int reg_width, | ||
44 | |||
45 | /* And now the final union of unions */ | ||
46 | g_string_append_printf(s, "<union id=\"%s\">", name); | ||
47 | - for (bits = 128, i = 0; bits >= 8; bits /= 2, i++) { | ||
48 | + for (i = ARRAY_SIZE(suf) - 1; i >= 0; i--) { | ||
49 | g_string_append_printf(s, "<field name=\"%c\" type=\"%sn%c\"/>", | ||
50 | suf[i], name, suf[i]); | ||
51 | } | 36 | } |
52 | -- | 37 | -- |
53 | 2.34.1 | 38 | 2.34.1 | diff view generated by jsdifflib |
1 | From: Richard Henderson <richard.henderson@linaro.org> | 1 | From: Richard Henderson <richard.henderson@linaro.org> |
---|---|---|---|
2 | 2 | ||
3 | Create a subroutine for creating the union of unions | 3 | Do not hard-code the constants for Neoverse V1. |
4 | of the various type sizes that a vector may contain. | ||
5 | 4 | ||
6 | Reviewed-by: Fabiano Rosas <farosas@suse.de> | 5 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> |
7 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | 6 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> |
8 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | 7 | Message-id: 20230811214031.171020-6-richard.henderson@linaro.org |
9 | Message-id: 20230227213329.793795-5-richard.henderson@linaro.org | ||
10 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 8 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
11 | --- | 9 | --- |
12 | target/arm/gdbstub64.c | 83 +++++++++++++++++++++++------------------- | 10 | target/arm/tcg/cpu64.c | 48 ++++++++++++++++++++++++++++-------------- |
13 | 1 file changed, 45 insertions(+), 38 deletions(-) | 11 | 1 file changed, 32 insertions(+), 16 deletions(-) |
14 | 12 | ||
15 | diff --git a/target/arm/gdbstub64.c b/target/arm/gdbstub64.c | 13 | diff --git a/target/arm/tcg/cpu64.c b/target/arm/tcg/cpu64.c |
16 | index XXXXXXX..XXXXXXX 100644 | 14 | index XXXXXXX..XXXXXXX 100644 |
17 | --- a/target/arm/gdbstub64.c | 15 | --- a/target/arm/tcg/cpu64.c |
18 | +++ b/target/arm/gdbstub64.c | 16 | +++ b/target/arm/tcg/cpu64.c |
19 | @@ -XXX,XX +XXX,XX @@ int aarch64_gdb_set_sve_reg(CPUARMState *env, uint8_t *buf, int reg) | 17 | @@ -XXX,XX +XXX,XX @@ |
20 | return 0; | 18 | #include "qemu/module.h" |
21 | } | 19 | #include "qapi/visitor.h" |
22 | 20 | #include "hw/qdev-properties.h" | |
23 | -struct TypeSize { | 21 | +#include "qemu/units.h" |
24 | - const char *gdb_type; | 22 | #include "internals.h" |
25 | - short size; | 23 | #include "cpregs.h" |
26 | - char sz, suffix; | 24 | |
27 | -}; | 25 | +static uint64_t make_ccsidr64(unsigned assoc, unsigned linesize, |
28 | - | 26 | + unsigned cachesize) |
29 | -static const struct TypeSize vec_lanes[] = { | 27 | +{ |
30 | - /* quads */ | 28 | + unsigned lg_linesize = ctz32(linesize); |
31 | - { "uint128", 128, 'q', 'u' }, | 29 | + unsigned sets; |
32 | - { "int128", 128, 'q', 's' }, | ||
33 | - /* 64 bit */ | ||
34 | - { "ieee_double", 64, 'd', 'f' }, | ||
35 | - { "uint64", 64, 'd', 'u' }, | ||
36 | - { "int64", 64, 'd', 's' }, | ||
37 | - /* 32 bit */ | ||
38 | - { "ieee_single", 32, 's', 'f' }, | ||
39 | - { "uint32", 32, 's', 'u' }, | ||
40 | - { "int32", 32, 's', 's' }, | ||
41 | - /* 16 bit */ | ||
42 | - { "ieee_half", 16, 'h', 'f' }, | ||
43 | - { "uint16", 16, 'h', 'u' }, | ||
44 | - { "int16", 16, 'h', 's' }, | ||
45 | - /* bytes */ | ||
46 | - { "uint8", 8, 'b', 'u' }, | ||
47 | - { "int8", 8, 'b', 's' }, | ||
48 | -}; | ||
49 | - | ||
50 | -int arm_gen_dynamic_svereg_xml(CPUState *cs, int base_reg) | ||
51 | +static void output_vector_union_type(GString *s, int reg_width) | ||
52 | { | ||
53 | - ARMCPU *cpu = ARM_CPU(cs); | ||
54 | - GString *s = g_string_new(NULL); | ||
55 | - DynamicGDBXMLInfo *info = &cpu->dyn_svereg_xml; | ||
56 | + struct TypeSize { | ||
57 | + const char *gdb_type; | ||
58 | + short size; | ||
59 | + char sz, suffix; | ||
60 | + }; | ||
61 | + | 30 | + |
62 | + static const struct TypeSize vec_lanes[] = { | 31 | + /* |
63 | + /* quads */ | 32 | + * The 64-bit CCSIDR_EL1 format is: |
64 | + { "uint128", 128, 'q', 'u' }, | 33 | + * [55:32] number of sets - 1 |
65 | + { "int128", 128, 'q', 's' }, | 34 | + * [23:3] associativity - 1 |
66 | + /* 64 bit */ | 35 | + * [2:0] log2(linesize) - 4 |
67 | + { "ieee_double", 64, 'd', 'f' }, | 36 | + * so 0 == 16 bytes, 1 == 32 bytes, 2 == 64 bytes, etc |
68 | + { "uint64", 64, 'd', 'u' }, | 37 | + */ |
69 | + { "int64", 64, 'd', 's' }, | 38 | + assert(assoc != 0); |
70 | + /* 32 bit */ | 39 | + assert(is_power_of_2(linesize)); |
71 | + { "ieee_single", 32, 's', 'f' }, | 40 | + assert(lg_linesize >= 4 && lg_linesize <= 7 + 4); |
72 | + { "uint32", 32, 's', 'u' }, | ||
73 | + { "int32", 32, 's', 's' }, | ||
74 | + /* 16 bit */ | ||
75 | + { "ieee_half", 16, 'h', 'f' }, | ||
76 | + { "uint16", 16, 'h', 'u' }, | ||
77 | + { "int16", 16, 'h', 's' }, | ||
78 | + /* bytes */ | ||
79 | + { "uint8", 8, 'b', 'u' }, | ||
80 | + { "int8", 8, 'b', 's' }, | ||
81 | + }; | ||
82 | + | 41 | + |
83 | + static const char suf[] = { 'q', 'd', 's', 'h', 'b' }; | 42 | + /* sets * associativity * linesize == cachesize. */ |
43 | + sets = cachesize / (assoc * linesize); | ||
44 | + assert(cachesize % (assoc * linesize) == 0); | ||
84 | + | 45 | + |
85 | g_autoptr(GString) ts = g_string_new(""); | 46 | + return ((uint64_t)(sets - 1) << 32) |
86 | - int i, j, bits, reg_width = (cpu->sve_max_vq * 128); | 47 | + | ((assoc - 1) << 3) |
87 | - info->num = 0; | 48 | + | (lg_linesize - 4); |
88 | - g_string_printf(s, "<?xml version=\"1.0\"?>"); | ||
89 | - g_string_append_printf(s, "<!DOCTYPE target SYSTEM \"gdb-target.dtd\">"); | ||
90 | - g_string_append_printf(s, "<feature name=\"org.gnu.gdb.aarch64.sve\">"); | ||
91 | + int i, j, bits; | ||
92 | |||
93 | /* First define types and totals in a whole VL */ | ||
94 | for (i = 0; i < ARRAY_SIZE(vec_lanes); i++) { | ||
95 | @@ -XXX,XX +XXX,XX @@ int arm_gen_dynamic_svereg_xml(CPUState *cs, int base_reg) | ||
96 | * 8 bits. | ||
97 | */ | ||
98 | for (bits = 128, i = 0; bits >= 8; bits /= 2, i++) { | ||
99 | - const char suf[] = { 'q', 'd', 's', 'h', 'b' }; | ||
100 | g_string_append_printf(s, "<union id=\"svevn%c\">", suf[i]); | ||
101 | for (j = 0; j < ARRAY_SIZE(vec_lanes); j++) { | ||
102 | if (vec_lanes[j].size == bits) { | ||
103 | @@ -XXX,XX +XXX,XX @@ int arm_gen_dynamic_svereg_xml(CPUState *cs, int base_reg) | ||
104 | /* And now the final union of unions */ | ||
105 | g_string_append(s, "<union id=\"svev\">"); | ||
106 | for (bits = 128, i = 0; bits >= 8; bits /= 2, i++) { | ||
107 | - const char suf[] = { 'q', 'd', 's', 'h', 'b' }; | ||
108 | g_string_append_printf(s, "<field name=\"%c\" type=\"svevn%c\"/>", | ||
109 | suf[i], suf[i]); | ||
110 | } | ||
111 | g_string_append(s, "</union>"); | ||
112 | +} | 49 | +} |
113 | + | 50 | + |
114 | +int arm_gen_dynamic_svereg_xml(CPUState *cs, int base_reg) | 51 | static void aarch64_a35_initfn(Object *obj) |
115 | +{ | 52 | { |
116 | + ARMCPU *cpu = ARM_CPU(cs); | 53 | ARMCPU *cpu = ARM_CPU(obj); |
117 | + GString *s = g_string_new(NULL); | 54 | @@ -XXX,XX +XXX,XX @@ static void aarch64_neoverse_v1_initfn(Object *obj) |
118 | + DynamicGDBXMLInfo *info = &cpu->dyn_svereg_xml; | 55 | * The Neoverse-V1 r1p2 TRM lists 32-bit format CCSIDR_EL1 values, |
119 | + int i, reg_width = (cpu->sve_max_vq * 128); | 56 | * but also says it implements CCIDX, which means they should be |
120 | + info->num = 0; | 57 | * 64-bit format. So we here use values which are based on the textual |
121 | + g_string_printf(s, "<?xml version=\"1.0\"?>"); | 58 | - * information in chapter 2 of the TRM (and on the fact that |
122 | + g_string_append_printf(s, "<!DOCTYPE target SYSTEM \"gdb-target.dtd\">"); | 59 | - * sets * associativity * linesize == cachesize). |
123 | + g_string_append_printf(s, "<feature name=\"org.gnu.gdb.aarch64.sve\">"); | 60 | - * |
124 | + | 61 | - * The 64-bit CCSIDR_EL1 format is: |
125 | + output_vector_union_type(s, reg_width); | 62 | - * [55:32] number of sets - 1 |
126 | 63 | - * [23:3] associativity - 1 | |
127 | /* Finally the sve prefix type */ | 64 | - * [2:0] log2(linesize) - 4 |
128 | g_string_append_printf(s, | 65 | - * so 0 == 16 bytes, 1 == 32 bytes, 2 == 64 bytes, etc |
66 | - * | ||
67 | - * L1: 4-way set associative 64-byte line size, total size 64K, | ||
68 | - * so sets is 256. | ||
69 | + * information in chapter 2 of the TRM: | ||
70 | * | ||
71 | + * L1: 4-way set associative 64-byte line size, total size 64K. | ||
72 | * L2: 8-way set associative, 64 byte line size, either 512K or 1MB. | ||
73 | - * We pick 1MB, so this has 2048 sets. | ||
74 | - * | ||
75 | * L3: No L3 (this matches the CLIDR_EL1 value). | ||
76 | */ | ||
77 | - cpu->ccsidr[0] = 0x000000ff0000001aull; /* 64KB L1 dcache */ | ||
78 | - cpu->ccsidr[1] = 0x000000ff0000001aull; /* 64KB L1 icache */ | ||
79 | - cpu->ccsidr[2] = 0x000007ff0000003aull; /* 1MB L2 cache */ | ||
80 | + cpu->ccsidr[0] = make_ccsidr64(4, 64, 64 * KiB); /* L1 dcache */ | ||
81 | + cpu->ccsidr[1] = cpu->ccsidr[0]; /* L1 icache */ | ||
82 | + cpu->ccsidr[2] = make_ccsidr64(8, 64, 1 * MiB); /* L2 cache */ | ||
83 | |||
84 | /* From 3.2.115 SCTLR_EL3 */ | ||
85 | cpu->reset_sctlr = 0x30c50838; | ||
129 | -- | 86 | -- |
130 | 2.34.1 | 87 | 2.34.1 | diff view generated by jsdifflib |
1 | From: Richard Henderson <richard.henderson@linaro.org> | 1 | From: Richard Henderson <richard.henderson@linaro.org> |
---|---|---|---|
2 | 2 | ||
3 | M-profile doesn't have HCR_EL2. While we could test features | 3 | Access to many of the special registers is enabled or disabled |
4 | before each call, zero is a generally safe return value to | 4 | by ACTLR_EL[23], which we implement as constant 0, which means |
5 | disable the code in the caller. This test is required to | 5 | that all writes outside EL3 should trap. |
6 | avoid an assert in arm_is_secure_below_el3. | ||
7 | 6 | ||
7 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | ||
8 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | 8 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> |
9 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | 9 | Message-id: 20230811214031.171020-7-richard.henderson@linaro.org |
10 | Message-id: 20230227225832.816605-3-richard.henderson@linaro.org | ||
11 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 10 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
12 | --- | 11 | --- |
13 | target/arm/helper.c | 3 +++ | 12 | target/arm/cpregs.h | 2 ++ |
14 | 1 file changed, 3 insertions(+) | 13 | target/arm/helper.c | 4 ++-- |
14 | target/arm/tcg/cpu64.c | 46 +++++++++++++++++++++++++++++++++--------- | ||
15 | 3 files changed, 41 insertions(+), 11 deletions(-) | ||
15 | 16 | ||
17 | diff --git a/target/arm/cpregs.h b/target/arm/cpregs.h | ||
18 | index XXXXXXX..XXXXXXX 100644 | ||
19 | --- a/target/arm/cpregs.h | ||
20 | +++ b/target/arm/cpregs.h | ||
21 | @@ -XXX,XX +XXX,XX @@ static inline void define_cortex_a72_a57_a53_cp_reginfo(ARMCPU *cpu) { } | ||
22 | void define_cortex_a72_a57_a53_cp_reginfo(ARMCPU *cpu); | ||
23 | #endif | ||
24 | |||
25 | +CPAccessResult access_tvm_trvm(CPUARMState *, const ARMCPRegInfo *, bool); | ||
26 | + | ||
27 | #endif /* TARGET_ARM_CPREGS_H */ | ||
16 | diff --git a/target/arm/helper.c b/target/arm/helper.c | 28 | diff --git a/target/arm/helper.c b/target/arm/helper.c |
17 | index XXXXXXX..XXXXXXX 100644 | 29 | index XXXXXXX..XXXXXXX 100644 |
18 | --- a/target/arm/helper.c | 30 | --- a/target/arm/helper.c |
19 | +++ b/target/arm/helper.c | 31 | +++ b/target/arm/helper.c |
20 | @@ -XXX,XX +XXX,XX @@ uint64_t arm_hcr_el2_eff_secstate(CPUARMState *env, bool secure) | 32 | @@ -XXX,XX +XXX,XX @@ static CPAccessResult access_tpm(CPUARMState *env, const ARMCPRegInfo *ri, |
21 | 33 | } | |
22 | uint64_t arm_hcr_el2_eff(CPUARMState *env) | 34 | |
35 | /* Check for traps from EL1 due to HCR_EL2.TVM and HCR_EL2.TRVM. */ | ||
36 | -static CPAccessResult access_tvm_trvm(CPUARMState *env, const ARMCPRegInfo *ri, | ||
37 | - bool isread) | ||
38 | +CPAccessResult access_tvm_trvm(CPUARMState *env, const ARMCPRegInfo *ri, | ||
39 | + bool isread) | ||
23 | { | 40 | { |
24 | + if (arm_feature(env, ARM_FEATURE_M)) { | 41 | if (arm_current_el(env) == 1) { |
25 | + return 0; | 42 | uint64_t trap = isread ? HCR_TRVM : HCR_TVM; |
43 | diff --git a/target/arm/tcg/cpu64.c b/target/arm/tcg/cpu64.c | ||
44 | index XXXXXXX..XXXXXXX 100644 | ||
45 | --- a/target/arm/tcg/cpu64.c | ||
46 | +++ b/target/arm/tcg/cpu64.c | ||
47 | @@ -XXX,XX +XXX,XX @@ static void aarch64_a64fx_initfn(Object *obj) | ||
48 | /* TODO: Add A64FX specific HPC extension registers */ | ||
49 | } | ||
50 | |||
51 | +static CPAccessResult access_actlr_w(CPUARMState *env, const ARMCPRegInfo *r, | ||
52 | + bool read) | ||
53 | +{ | ||
54 | + if (!read) { | ||
55 | + int el = arm_current_el(env); | ||
56 | + | ||
57 | + /* Because ACTLR_EL2 is constant 0, writes below EL2 trap to EL2. */ | ||
58 | + if (el < 2 && arm_is_el2_enabled(env)) { | ||
59 | + return CP_ACCESS_TRAP_EL2; | ||
60 | + } | ||
61 | + /* Because ACTLR_EL3 is constant 0, writes below EL3 trap to EL3. */ | ||
62 | + if (el < 3 && arm_feature(env, ARM_FEATURE_EL3)) { | ||
63 | + return CP_ACCESS_TRAP_EL3; | ||
64 | + } | ||
26 | + } | 65 | + } |
27 | return arm_hcr_el2_eff_secstate(env, arm_is_secure_below_el3(env)); | 66 | + return CP_ACCESS_OK; |
28 | } | 67 | +} |
29 | 68 | + | |
69 | static const ARMCPRegInfo neoverse_n1_cp_reginfo[] = { | ||
70 | { .name = "ATCR_EL1", .state = ARM_CP_STATE_AA64, | ||
71 | .opc0 = 3, .opc1 = 0, .crn = 15, .crm = 7, .opc2 = 0, | ||
72 | - .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, | ||
73 | + .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0, | ||
74 | + /* Traps and enables are the same as for TCR_EL1. */ | ||
75 | + .accessfn = access_tvm_trvm, .fgt = FGT_TCR_EL1, }, | ||
76 | { .name = "ATCR_EL2", .state = ARM_CP_STATE_AA64, | ||
77 | .opc0 = 3, .opc1 = 4, .crn = 15, .crm = 7, .opc2 = 0, | ||
78 | .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, | ||
79 | @@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo neoverse_n1_cp_reginfo[] = { | ||
80 | .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, | ||
81 | { .name = "CPUACTLR_EL1", .state = ARM_CP_STATE_AA64, | ||
82 | .opc0 = 3, .opc1 = 0, .crn = 15, .crm = 1, .opc2 = 0, | ||
83 | - .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, | ||
84 | + .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0, | ||
85 | + .accessfn = access_actlr_w }, | ||
86 | { .name = "CPUACTLR2_EL1", .state = ARM_CP_STATE_AA64, | ||
87 | .opc0 = 3, .opc1 = 0, .crn = 15, .crm = 1, .opc2 = 1, | ||
88 | - .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, | ||
89 | + .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0, | ||
90 | + .accessfn = access_actlr_w }, | ||
91 | { .name = "CPUACTLR3_EL1", .state = ARM_CP_STATE_AA64, | ||
92 | .opc0 = 3, .opc1 = 0, .crn = 15, .crm = 1, .opc2 = 2, | ||
93 | - .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, | ||
94 | + .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0, | ||
95 | + .accessfn = access_actlr_w }, | ||
96 | /* | ||
97 | * Report CPUCFR_EL1.SCU as 1, as we do not implement the DSU | ||
98 | * (and in particular its system registers). | ||
99 | @@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo neoverse_n1_cp_reginfo[] = { | ||
100 | .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 4 }, | ||
101 | { .name = "CPUECTLR_EL1", .state = ARM_CP_STATE_AA64, | ||
102 | .opc0 = 3, .opc1 = 0, .crn = 15, .crm = 1, .opc2 = 4, | ||
103 | - .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0x961563010 }, | ||
104 | + .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0x961563010, | ||
105 | + .accessfn = access_actlr_w }, | ||
106 | { .name = "CPUPCR_EL3", .state = ARM_CP_STATE_AA64, | ||
107 | .opc0 = 3, .opc1 = 6, .crn = 15, .crm = 8, .opc2 = 1, | ||
108 | .access = PL3_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, | ||
109 | @@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo neoverse_n1_cp_reginfo[] = { | ||
110 | .access = PL3_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, | ||
111 | { .name = "CPUPWRCTLR_EL1", .state = ARM_CP_STATE_AA64, | ||
112 | .opc0 = 3, .opc1 = 0, .crn = 15, .crm = 2, .opc2 = 7, | ||
113 | - .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, | ||
114 | + .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0, | ||
115 | + .accessfn = access_actlr_w }, | ||
116 | { .name = "ERXPFGCDN_EL1", .state = ARM_CP_STATE_AA64, | ||
117 | .opc0 = 3, .opc1 = 0, .crn = 15, .crm = 2, .opc2 = 2, | ||
118 | - .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, | ||
119 | + .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0, | ||
120 | + .accessfn = access_actlr_w }, | ||
121 | { .name = "ERXPFGCTL_EL1", .state = ARM_CP_STATE_AA64, | ||
122 | .opc0 = 3, .opc1 = 0, .crn = 15, .crm = 2, .opc2 = 1, | ||
123 | - .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, | ||
124 | + .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0, | ||
125 | + .accessfn = access_actlr_w }, | ||
126 | { .name = "ERXPFGF_EL1", .state = ARM_CP_STATE_AA64, | ||
127 | .opc0 = 3, .opc1 = 0, .crn = 15, .crm = 2, .opc2 = 0, | ||
128 | - .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, | ||
129 | + .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0, | ||
130 | + .accessfn = access_actlr_w }, | ||
131 | }; | ||
132 | |||
133 | static void define_neoverse_n1_cp_reginfo(ARMCPU *cpu) | ||
30 | -- | 134 | -- |
31 | 2.34.1 | 135 | 2.34.1 | diff view generated by jsdifflib |
1 | From: Richard Henderson <richard.henderson@linaro.org> | 1 | From: Richard Henderson <richard.henderson@linaro.org> |
---|---|---|---|
2 | 2 | ||
3 | Keep the logic for pauth within pauth_helper.c, and expose | 3 | There is only one additional EL1 register modeled, which |
4 | a helper function for use with the gdbstub pac extension. | 4 | also needs to use access_actlr_w. |
5 | 5 | ||
6 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | ||
6 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | 7 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> |
7 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | 8 | Message-id: 20230811214031.171020-8-richard.henderson@linaro.org |
8 | Message-id: 20230227213329.793795-11-richard.henderson@linaro.org | ||
9 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 9 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
10 | --- | 10 | --- |
11 | target/arm/internals.h | 10 ++++++++++ | 11 | target/arm/tcg/cpu64.c | 3 ++- |
12 | target/arm/tcg/pauth_helper.c | 26 ++++++++++++++++++++++---- | 12 | 1 file changed, 2 insertions(+), 1 deletion(-) |
13 | 2 files changed, 32 insertions(+), 4 deletions(-) | ||
14 | 13 | ||
15 | diff --git a/target/arm/internals.h b/target/arm/internals.h | 14 | diff --git a/target/arm/tcg/cpu64.c b/target/arm/tcg/cpu64.c |
16 | index XXXXXXX..XXXXXXX 100644 | 15 | index XXXXXXX..XXXXXXX 100644 |
17 | --- a/target/arm/internals.h | 16 | --- a/target/arm/tcg/cpu64.c |
18 | +++ b/target/arm/internals.h | 17 | +++ b/target/arm/tcg/cpu64.c |
19 | @@ -XXX,XX +XXX,XX @@ int exception_target_el(CPUARMState *env); | 18 | @@ -XXX,XX +XXX,XX @@ static void define_neoverse_n1_cp_reginfo(ARMCPU *cpu) |
20 | bool arm_singlestep_active(CPUARMState *env); | 19 | static const ARMCPRegInfo neoverse_v1_cp_reginfo[] = { |
21 | bool arm_generate_debug_exceptions(CPUARMState *env); | 20 | { .name = "CPUECTLR2_EL1", .state = ARM_CP_STATE_AA64, |
22 | 21 | .opc0 = 3, .opc1 = 0, .crn = 15, .crm = 1, .opc2 = 5, | |
23 | +/** | 22 | - .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, |
24 | + * pauth_ptr_mask: | 23 | + .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0, |
25 | + * @env: cpu context | 24 | + .accessfn = access_actlr_w }, |
26 | + * @ptr: selects between TTBR0 and TTBR1 | 25 | { .name = "CPUPPMCR_EL3", .state = ARM_CP_STATE_AA64, |
27 | + * @data: selects between TBI and TBID | 26 | .opc0 = 3, .opc1 = 6, .crn = 15, .crm = 2, .opc2 = 0, |
28 | + * | 27 | .access = PL3_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, |
29 | + * Return a mask of the bits of @ptr that contain the authentication code. | ||
30 | + */ | ||
31 | +uint64_t pauth_ptr_mask(CPUARMState *env, uint64_t ptr, bool data); | ||
32 | + | ||
33 | /* Add the cpreg definitions for debug related system registers */ | ||
34 | void define_debug_regs(ARMCPU *cpu); | ||
35 | |||
36 | diff --git a/target/arm/tcg/pauth_helper.c b/target/arm/tcg/pauth_helper.c | ||
37 | index XXXXXXX..XXXXXXX 100644 | ||
38 | --- a/target/arm/tcg/pauth_helper.c | ||
39 | +++ b/target/arm/tcg/pauth_helper.c | ||
40 | @@ -XXX,XX +XXX,XX @@ static uint64_t pauth_addpac(CPUARMState *env, uint64_t ptr, uint64_t modifier, | ||
41 | return pac | ext | ptr; | ||
42 | } | ||
43 | |||
44 | -static uint64_t pauth_original_ptr(uint64_t ptr, ARMVAParameters param) | ||
45 | +static uint64_t pauth_ptr_mask_internal(ARMVAParameters param) | ||
46 | { | ||
47 | - /* Note that bit 55 is used whether or not the regime has 2 ranges. */ | ||
48 | - uint64_t extfield = sextract64(ptr, 55, 1); | ||
49 | int bot_pac_bit = 64 - param.tsz; | ||
50 | int top_pac_bit = 64 - 8 * param.tbi; | ||
51 | |||
52 | - return deposit64(ptr, bot_pac_bit, top_pac_bit - bot_pac_bit, extfield); | ||
53 | + return MAKE_64BIT_MASK(bot_pac_bit, top_pac_bit - bot_pac_bit); | ||
54 | +} | ||
55 | + | ||
56 | +static uint64_t pauth_original_ptr(uint64_t ptr, ARMVAParameters param) | ||
57 | +{ | ||
58 | + uint64_t mask = pauth_ptr_mask_internal(param); | ||
59 | + | ||
60 | + /* Note that bit 55 is used whether or not the regime has 2 ranges. */ | ||
61 | + if (extract64(ptr, 55, 1)) { | ||
62 | + return ptr | mask; | ||
63 | + } else { | ||
64 | + return ptr & ~mask; | ||
65 | + } | ||
66 | +} | ||
67 | + | ||
68 | +uint64_t pauth_ptr_mask(CPUARMState *env, uint64_t ptr, bool data) | ||
69 | +{ | ||
70 | + ARMMMUIdx mmu_idx = arm_stage1_mmu_idx(env); | ||
71 | + ARMVAParameters param = aa64_va_parameters(env, ptr, mmu_idx, data); | ||
72 | + | ||
73 | + return pauth_ptr_mask_internal(param); | ||
74 | } | ||
75 | |||
76 | static uint64_t pauth_auth(CPUARMState *env, uint64_t ptr, uint64_t modifier, | ||
77 | -- | 28 | -- |
78 | 2.34.1 | 29 | 2.34.1 | diff view generated by jsdifflib |
1 | From: Richard Henderson <richard.henderson@linaro.org> | 1 | From: Richard Henderson <richard.henderson@linaro.org> |
---|---|---|---|
2 | 2 | ||
3 | Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1421 | 3 | Like FEAT_TRF (Self-hosted Trace Extension), suppress tracing |
4 | external to the cpu, which is out of scope for QEMU. | ||
5 | |||
6 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | ||
4 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | 7 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> |
5 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | 8 | Message-id: 20230811214031.171020-10-richard.henderson@linaro.org |
6 | Message-id: 20230227225832.816605-2-richard.henderson@linaro.org | ||
7 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 9 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
8 | --- | 10 | --- |
9 | target/arm/cpu.h | 3 +++ | 11 | target/arm/cpu.c | 3 +++ |
10 | 1 file changed, 3 insertions(+) | 12 | 1 file changed, 3 insertions(+) |
11 | 13 | ||
12 | diff --git a/target/arm/cpu.h b/target/arm/cpu.h | 14 | diff --git a/target/arm/cpu.c b/target/arm/cpu.c |
13 | index XXXXXXX..XXXXXXX 100644 | 15 | index XXXXXXX..XXXXXXX 100644 |
14 | --- a/target/arm/cpu.h | 16 | --- a/target/arm/cpu.c |
15 | +++ b/target/arm/cpu.h | 17 | +++ b/target/arm/cpu.c |
16 | @@ -XXX,XX +XXX,XX @@ static inline bool arm_is_el3_or_mon(CPUARMState *env) | 18 | @@ -XXX,XX +XXX,XX @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp) |
17 | /* Return true if the processor is in secure state */ | 19 | /* FEAT_SPE (Statistical Profiling Extension) */ |
18 | static inline bool arm_is_secure(CPUARMState *env) | 20 | cpu->isar.id_aa64dfr0 = |
19 | { | 21 | FIELD_DP64(cpu->isar.id_aa64dfr0, ID_AA64DFR0, PMSVER, 0); |
20 | + if (arm_feature(env, ARM_FEATURE_M)) { | 22 | + /* FEAT_TRBE (Trace Buffer Extension) */ |
21 | + return env->v7m.secure; | 23 | + cpu->isar.id_aa64dfr0 = |
22 | + } | 24 | + FIELD_DP64(cpu->isar.id_aa64dfr0, ID_AA64DFR0, TRACEBUFFER, 0); |
23 | if (arm_is_el3_or_mon(env)) { | 25 | /* FEAT_TRF (Self-hosted Trace Extension) */ |
24 | return true; | 26 | cpu->isar.id_aa64dfr0 = |
25 | } | 27 | FIELD_DP64(cpu->isar.id_aa64dfr0, ID_AA64DFR0, TRACEFILT, 0); |
26 | -- | 28 | -- |
27 | 2.34.1 | 29 | 2.34.1 | diff view generated by jsdifflib |
1 | From: Richard Henderson <richard.henderson@linaro.org> | 1 | From: Richard Henderson <richard.henderson@linaro.org> |
---|---|---|---|
2 | 2 | ||
3 | Define svep based on the size of the predicates, | 3 | This feature allows the operating system to set TCR_ELx.HWU* |
4 | not the primary vector registers. | 4 | to allow the implementation to use the PBHA bits from the |
5 | block and page descriptors for for IMPLEMENTATION DEFINED | ||
6 | purposes. Since QEMU has no need to use these bits, we may | ||
7 | simply ignore them. | ||
5 | 8 | ||
9 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | ||
6 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | 10 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> |
7 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | 11 | Message-id: 20230811214031.171020-11-richard.henderson@linaro.org |
8 | Message-id: 20230227213329.793795-8-richard.henderson@linaro.org | ||
9 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 12 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
10 | --- | 13 | --- |
11 | target/arm/gdbstub64.c | 2 +- | 14 | docs/system/arm/emulation.rst | 1 + |
12 | 1 file changed, 1 insertion(+), 1 deletion(-) | 15 | target/arm/tcg/cpu32.c | 2 +- |
16 | target/arm/tcg/cpu64.c | 2 +- | ||
17 | 3 files changed, 3 insertions(+), 2 deletions(-) | ||
13 | 18 | ||
14 | diff --git a/target/arm/gdbstub64.c b/target/arm/gdbstub64.c | 19 | diff --git a/docs/system/arm/emulation.rst b/docs/system/arm/emulation.rst |
15 | index XXXXXXX..XXXXXXX 100644 | 20 | index XXXXXXX..XXXXXXX 100644 |
16 | --- a/target/arm/gdbstub64.c | 21 | --- a/docs/system/arm/emulation.rst |
17 | +++ b/target/arm/gdbstub64.c | 22 | +++ b/docs/system/arm/emulation.rst |
18 | @@ -XXX,XX +XXX,XX @@ int arm_gen_dynamic_svereg_xml(CPUState *cs, int orig_base_reg) | 23 | @@ -XXX,XX +XXX,XX @@ the following architecture extensions: |
19 | /* Create the predicate vector type. */ | 24 | - FEAT_HAFDBS (Hardware management of the access flag and dirty bit state) |
20 | g_string_append_printf(s, | 25 | - FEAT_HCX (Support for the HCRX_EL2 register) |
21 | "<vector id=\"svep\" type=\"uint8\" count=\"%d\"/>", | 26 | - FEAT_HPDS (Hierarchical permission disables) |
22 | - reg_width / 8); | 27 | +- FEAT_HPDS2 (Translation table page-based hardware attributes) |
23 | + pred_width / 8); | 28 | - FEAT_I8MM (AArch64 Int8 matrix multiplication instructions) |
24 | 29 | - FEAT_IDST (ID space trap handling) | |
25 | /* Define the vector registers. */ | 30 | - FEAT_IESB (Implicit error synchronization event) |
26 | for (i = 0; i < 32; i++) { | 31 | diff --git a/target/arm/tcg/cpu32.c b/target/arm/tcg/cpu32.c |
32 | index XXXXXXX..XXXXXXX 100644 | ||
33 | --- a/target/arm/tcg/cpu32.c | ||
34 | +++ b/target/arm/tcg/cpu32.c | ||
35 | @@ -XXX,XX +XXX,XX @@ void aa32_max_features(ARMCPU *cpu) | ||
36 | cpu->isar.id_mmfr3 = t; | ||
37 | |||
38 | t = cpu->isar.id_mmfr4; | ||
39 | - t = FIELD_DP32(t, ID_MMFR4, HPDS, 1); /* FEAT_AA32HPD */ | ||
40 | + t = FIELD_DP32(t, ID_MMFR4, HPDS, 2); /* FEAT_HPDS2 */ | ||
41 | t = FIELD_DP32(t, ID_MMFR4, AC2, 1); /* ACTLR2, HACTLR2 */ | ||
42 | t = FIELD_DP32(t, ID_MMFR4, CNP, 1); /* FEAT_TTCNP */ | ||
43 | t = FIELD_DP32(t, ID_MMFR4, XNX, 1); /* FEAT_XNX */ | ||
44 | diff --git a/target/arm/tcg/cpu64.c b/target/arm/tcg/cpu64.c | ||
45 | index XXXXXXX..XXXXXXX 100644 | ||
46 | --- a/target/arm/tcg/cpu64.c | ||
47 | +++ b/target/arm/tcg/cpu64.c | ||
48 | @@ -XXX,XX +XXX,XX @@ void aarch64_max_tcg_initfn(Object *obj) | ||
49 | t = FIELD_DP64(t, ID_AA64MMFR1, HAFDBS, 2); /* FEAT_HAFDBS */ | ||
50 | t = FIELD_DP64(t, ID_AA64MMFR1, VMIDBITS, 2); /* FEAT_VMID16 */ | ||
51 | t = FIELD_DP64(t, ID_AA64MMFR1, VH, 1); /* FEAT_VHE */ | ||
52 | - t = FIELD_DP64(t, ID_AA64MMFR1, HPDS, 1); /* FEAT_HPDS */ | ||
53 | + t = FIELD_DP64(t, ID_AA64MMFR1, HPDS, 2); /* FEAT_HPDS2 */ | ||
54 | t = FIELD_DP64(t, ID_AA64MMFR1, LO, 1); /* FEAT_LOR */ | ||
55 | t = FIELD_DP64(t, ID_AA64MMFR1, PAN, 3); /* FEAT_PAN3 */ | ||
56 | t = FIELD_DP64(t, ID_AA64MMFR1, XNX, 1); /* FEAT_XNX */ | ||
27 | -- | 57 | -- |
28 | 2.34.1 | 58 | 2.34.1 | diff view generated by jsdifflib |
1 | From: Richard Henderson <richard.henderson@linaro.org> | 1 | From: Alex Bennée <alex.bennee@linaro.org> |
---|---|---|---|
2 | 2 | ||
3 | Rather than increment base_reg and num, compute num from the change | 3 | This is a mandatory feature for Armv8.1 architectures but we don't |
4 | to base_reg at the end. Clean up some nearby comments. | 4 | state the feature clearly in our emulation list. Also include |
5 | FEAT_CRC32 comment in aarch64_max_tcg_initfn for ease of grepping. | ||
5 | 6 | ||
6 | Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> | 7 | Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> |
7 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | 8 | Signed-off-by: Alex Bennée <alex.bennee@linaro.org> |
8 | Message-id: 20230227213329.793795-6-richard.henderson@linaro.org | 9 | Message-id: 20230824075406.1515566-1-alex.bennee@linaro.org |
10 | Cc: qemu-stable@nongnu.org | ||
11 | Message-Id: <20230222110104.3996971-1-alex.bennee@linaro.org> | ||
12 | [PMM: pluralize 'instructions' in docs] | ||
9 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 13 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
10 | --- | 14 | --- |
11 | target/arm/gdbstub64.c | 27 ++++++++++++++++----------- | 15 | docs/system/arm/emulation.rst | 1 + |
12 | 1 file changed, 16 insertions(+), 11 deletions(-) | 16 | target/arm/tcg/cpu64.c | 2 +- |
17 | 2 files changed, 2 insertions(+), 1 deletion(-) | ||
13 | 18 | ||
14 | diff --git a/target/arm/gdbstub64.c b/target/arm/gdbstub64.c | 19 | diff --git a/docs/system/arm/emulation.rst b/docs/system/arm/emulation.rst |
15 | index XXXXXXX..XXXXXXX 100644 | 20 | index XXXXXXX..XXXXXXX 100644 |
16 | --- a/target/arm/gdbstub64.c | 21 | --- a/docs/system/arm/emulation.rst |
17 | +++ b/target/arm/gdbstub64.c | 22 | +++ b/docs/system/arm/emulation.rst |
18 | @@ -XXX,XX +XXX,XX @@ static void output_vector_union_type(GString *s, int reg_width) | 23 | @@ -XXX,XX +XXX,XX @@ the following architecture extensions: |
19 | g_string_append(s, "</union>"); | 24 | - FEAT_BBM at level 2 (Translation table break-before-make levels) |
20 | } | 25 | - FEAT_BF16 (AArch64 BFloat16 instructions) |
21 | 26 | - FEAT_BTI (Branch Target Identification) | |
22 | -int arm_gen_dynamic_svereg_xml(CPUState *cs, int base_reg) | 27 | +- FEAT_CRC32 (CRC32 instructions) |
23 | +int arm_gen_dynamic_svereg_xml(CPUState *cs, int orig_base_reg) | 28 | - FEAT_CSV2 (Cache speculation variant 2) |
24 | { | 29 | - FEAT_CSV2_1p1 (Cache speculation variant 2, version 1.1) |
25 | ARMCPU *cpu = ARM_CPU(cs); | 30 | - FEAT_CSV2_1p2 (Cache speculation variant 2, version 1.2) |
26 | GString *s = g_string_new(NULL); | 31 | diff --git a/target/arm/tcg/cpu64.c b/target/arm/tcg/cpu64.c |
27 | DynamicGDBXMLInfo *info = &cpu->dyn_svereg_xml; | 32 | index XXXXXXX..XXXXXXX 100644 |
28 | - int i, reg_width = (cpu->sve_max_vq * 128); | 33 | --- a/target/arm/tcg/cpu64.c |
29 | - info->num = 0; | 34 | +++ b/target/arm/tcg/cpu64.c |
30 | + int reg_width = cpu->sve_max_vq * 128; | 35 | @@ -XXX,XX +XXX,XX @@ void aarch64_max_tcg_initfn(Object *obj) |
31 | + int base_reg = orig_base_reg; | 36 | t = FIELD_DP64(t, ID_AA64ISAR0, AES, 2); /* FEAT_PMULL */ |
32 | + int i; | 37 | t = FIELD_DP64(t, ID_AA64ISAR0, SHA1, 1); /* FEAT_SHA1 */ |
33 | + | 38 | t = FIELD_DP64(t, ID_AA64ISAR0, SHA2, 2); /* FEAT_SHA512 */ |
34 | g_string_printf(s, "<?xml version=\"1.0\"?>"); | 39 | - t = FIELD_DP64(t, ID_AA64ISAR0, CRC32, 1); |
35 | g_string_append_printf(s, "<!DOCTYPE target SYSTEM \"gdb-target.dtd\">"); | 40 | + t = FIELD_DP64(t, ID_AA64ISAR0, CRC32, 1); /* FEAT_CRC32 */ |
36 | g_string_append_printf(s, "<feature name=\"org.gnu.gdb.aarch64.sve\">"); | 41 | t = FIELD_DP64(t, ID_AA64ISAR0, ATOMIC, 2); /* FEAT_LSE */ |
37 | 42 | t = FIELD_DP64(t, ID_AA64ISAR0, RDM, 1); /* FEAT_RDM */ | |
38 | + /* Create the vector union type. */ | 43 | t = FIELD_DP64(t, ID_AA64ISAR0, SHA3, 1); /* FEAT_SHA3 */ |
39 | output_vector_union_type(s, reg_width); | ||
40 | |||
41 | - /* Finally the sve prefix type */ | ||
42 | + /* Create the predicate vector type. */ | ||
43 | g_string_append_printf(s, | ||
44 | "<vector id=\"svep\" type=\"uint8\" count=\"%d\"/>", | ||
45 | reg_width / 8); | ||
46 | |||
47 | - /* Then define each register in parts for each vq */ | ||
48 | + /* Define the vector registers. */ | ||
49 | for (i = 0; i < 32; i++) { | ||
50 | g_string_append_printf(s, | ||
51 | "<reg name=\"z%d\" bitsize=\"%d\"" | ||
52 | " regnum=\"%d\" type=\"svev\"/>", | ||
53 | i, reg_width, base_reg++); | ||
54 | - info->num++; | ||
55 | } | ||
56 | + | ||
57 | /* fpscr & status registers */ | ||
58 | g_string_append_printf(s, "<reg name=\"fpsr\" bitsize=\"32\"" | ||
59 | " regnum=\"%d\" group=\"float\"" | ||
60 | @@ -XXX,XX +XXX,XX @@ int arm_gen_dynamic_svereg_xml(CPUState *cs, int base_reg) | ||
61 | g_string_append_printf(s, "<reg name=\"fpcr\" bitsize=\"32\"" | ||
62 | " regnum=\"%d\" group=\"float\"" | ||
63 | " type=\"int\"/>", base_reg++); | ||
64 | - info->num += 2; | ||
65 | |||
66 | + /* Define the predicate registers. */ | ||
67 | for (i = 0; i < 16; i++) { | ||
68 | g_string_append_printf(s, | ||
69 | "<reg name=\"p%d\" bitsize=\"%d\"" | ||
70 | " regnum=\"%d\" type=\"svep\"/>", | ||
71 | i, cpu->sve_max_vq * 16, base_reg++); | ||
72 | - info->num++; | ||
73 | } | ||
74 | g_string_append_printf(s, | ||
75 | "<reg name=\"ffr\" bitsize=\"%d\"" | ||
76 | " regnum=\"%d\" group=\"vector\"" | ||
77 | " type=\"svep\"/>", | ||
78 | cpu->sve_max_vq * 16, base_reg++); | ||
79 | + | ||
80 | + /* Define the vector length pseudo-register. */ | ||
81 | g_string_append_printf(s, | ||
82 | "<reg name=\"vg\" bitsize=\"64\"" | ||
83 | " regnum=\"%d\" type=\"int\"/>", | ||
84 | base_reg++); | ||
85 | - info->num += 2; | ||
86 | - g_string_append_printf(s, "</feature>"); | ||
87 | - info->desc = g_string_free(s, false); | ||
88 | |||
89 | + g_string_append_printf(s, "</feature>"); | ||
90 | + | ||
91 | + info->desc = g_string_free(s, false); | ||
92 | + info->num = base_reg - orig_base_reg; | ||
93 | return info->num; | ||
94 | } | ||
95 | -- | 44 | -- |
96 | 2.34.1 | 45 | 2.34.1 |
97 | 46 | ||
98 | 47 | diff view generated by jsdifflib |
New patch | |||
---|---|---|---|
1 | From: Jean-Christophe Dubois <jcd@tribudubois.net> | ||
1 | 2 | ||
3 | i.MX7 IOMUX GPR device is not equivalent to i.MX6UL IOMUXC GPR device. | ||
4 | In particular, register 22 is not present on i.MX6UL and this is actualy | ||
5 | The only register that is really emulated in the i.MX7 IOMUX GPR device. | ||
6 | |||
7 | Note: The i.MX6UL code is actually also implementing the IOMUX GPR device | ||
8 | as an unimplemented device at the same bus adress and the 2 instantiations | ||
9 | were actualy colliding. So we go back to the unimplemented device for now. | ||
10 | |||
11 | Signed-off-by: Jean-Christophe Dubois <jcd@tribudubois.net> | ||
12 | Message-id: 48681bf51ee97646479bb261bee19abebbc8074e.1692964892.git.jcd@tribudubois.net | ||
13 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
14 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
15 | --- | ||
16 | include/hw/arm/fsl-imx6ul.h | 2 -- | ||
17 | hw/arm/fsl-imx6ul.c | 11 ----------- | ||
18 | 2 files changed, 13 deletions(-) | ||
19 | |||
20 | diff --git a/include/hw/arm/fsl-imx6ul.h b/include/hw/arm/fsl-imx6ul.h | ||
21 | index XXXXXXX..XXXXXXX 100644 | ||
22 | --- a/include/hw/arm/fsl-imx6ul.h | ||
23 | +++ b/include/hw/arm/fsl-imx6ul.h | ||
24 | @@ -XXX,XX +XXX,XX @@ | ||
25 | #include "hw/misc/imx6ul_ccm.h" | ||
26 | #include "hw/misc/imx6_src.h" | ||
27 | #include "hw/misc/imx7_snvs.h" | ||
28 | -#include "hw/misc/imx7_gpr.h" | ||
29 | #include "hw/intc/imx_gpcv2.h" | ||
30 | #include "hw/watchdog/wdt_imx2.h" | ||
31 | #include "hw/gpio/imx_gpio.h" | ||
32 | @@ -XXX,XX +XXX,XX @@ struct FslIMX6ULState { | ||
33 | IMX6SRCState src; | ||
34 | IMX7SNVSState snvs; | ||
35 | IMXGPCv2State gpcv2; | ||
36 | - IMX7GPRState gpr; | ||
37 | IMXSPIState spi[FSL_IMX6UL_NUM_ECSPIS]; | ||
38 | IMXI2CState i2c[FSL_IMX6UL_NUM_I2CS]; | ||
39 | IMXSerialState uart[FSL_IMX6UL_NUM_UARTS]; | ||
40 | diff --git a/hw/arm/fsl-imx6ul.c b/hw/arm/fsl-imx6ul.c | ||
41 | index XXXXXXX..XXXXXXX 100644 | ||
42 | --- a/hw/arm/fsl-imx6ul.c | ||
43 | +++ b/hw/arm/fsl-imx6ul.c | ||
44 | @@ -XXX,XX +XXX,XX @@ static void fsl_imx6ul_init(Object *obj) | ||
45 | */ | ||
46 | object_initialize_child(obj, "snvs", &s->snvs, TYPE_IMX7_SNVS); | ||
47 | |||
48 | - /* | ||
49 | - * GPR | ||
50 | - */ | ||
51 | - object_initialize_child(obj, "gpr", &s->gpr, TYPE_IMX7_GPR); | ||
52 | - | ||
53 | /* | ||
54 | * GPIOs 1 to 5 | ||
55 | */ | ||
56 | @@ -XXX,XX +XXX,XX @@ static void fsl_imx6ul_realize(DeviceState *dev, Error **errp) | ||
57 | FSL_IMX6UL_WDOGn_IRQ[i])); | ||
58 | } | ||
59 | |||
60 | - /* | ||
61 | - * GPR | ||
62 | - */ | ||
63 | - sysbus_realize(SYS_BUS_DEVICE(&s->gpr), &error_abort); | ||
64 | - sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpr), 0, FSL_IMX6UL_IOMUXC_GPR_ADDR); | ||
65 | - | ||
66 | /* | ||
67 | * SDMA | ||
68 | */ | ||
69 | -- | ||
70 | 2.34.1 | diff view generated by jsdifflib |
1 | From: qianfan Zhao <qianfanguijin@163.com> | 1 | From: Jean-Christophe Dubois <jcd@tribudubois.net> |
---|---|---|---|
2 | 2 | ||
3 | Allwinner h3 has 4 twi(i2c) devices named twi0, twi1, twi2 and r_twi. | 3 | * Add Addr and size definition for most i.MX6UL devices in i.MX6UL header file. |
4 | The registers are compatible with TYPE_AW_I2C_SUN6I, write 1 to clear | 4 | * Use those newly defined named constants whenever possible. |
5 | control register's INT_FLAG bit. | 5 | * Standardize the way we init a familly of unimplemented devices |
6 | - SAI | ||
7 | - PWM | ||
8 | - CAN | ||
9 | * Add/rework few comments | ||
6 | 10 | ||
7 | Signed-off-by: qianfan Zhao <qianfanguijin@163.com> | 11 | Signed-off-by: Jean-Christophe Dubois <jcd@tribudubois.net> |
8 | Reviewed-by: Strahinja Jankovic <strahinja.p.jankovic@gmail.com> | 12 | Message-id: d579043fbd4e4b490370783fda43fc02c8e9be75.1692964892.git.jcd@tribudubois.net |
9 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | 13 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> |
10 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 14 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
11 | --- | 15 | --- |
12 | include/hw/arm/allwinner-h3.h | 6 ++++++ | 16 | include/hw/arm/fsl-imx6ul.h | 156 +++++++++++++++++++++++++++++++----- |
13 | hw/arm/allwinner-h3.c | 29 +++++++++++++++++++++++++---- | 17 | hw/arm/fsl-imx6ul.c | 147 ++++++++++++++++++++++----------- |
14 | 2 files changed, 31 insertions(+), 4 deletions(-) | 18 | 2 files changed, 232 insertions(+), 71 deletions(-) |
15 | 19 | ||
16 | diff --git a/include/hw/arm/allwinner-h3.h b/include/hw/arm/allwinner-h3.h | 20 | diff --git a/include/hw/arm/fsl-imx6ul.h b/include/hw/arm/fsl-imx6ul.h |
17 | index XXXXXXX..XXXXXXX 100644 | 21 | index XXXXXXX..XXXXXXX 100644 |
18 | --- a/include/hw/arm/allwinner-h3.h | 22 | --- a/include/hw/arm/fsl-imx6ul.h |
19 | +++ b/include/hw/arm/allwinner-h3.h | 23 | +++ b/include/hw/arm/fsl-imx6ul.h |
20 | @@ -XXX,XX +XXX,XX @@ enum { | 24 | @@ -XXX,XX +XXX,XX @@ |
21 | AW_H3_DEV_UART3, | 25 | #include "exec/memory.h" |
22 | AW_H3_DEV_EMAC, | 26 | #include "cpu.h" |
23 | AW_H3_DEV_TWI0, | 27 | #include "qom/object.h" |
24 | + AW_H3_DEV_TWI1, | 28 | +#include "qemu/units.h" |
25 | + AW_H3_DEV_TWI2, | 29 | |
26 | AW_H3_DEV_DRAMCOM, | 30 | #define TYPE_FSL_IMX6UL "fsl-imx6ul" |
27 | AW_H3_DEV_DRAMCTL, | 31 | OBJECT_DECLARE_SIMPLE_TYPE(FslIMX6ULState, FSL_IMX6UL) |
28 | AW_H3_DEV_DRAMPHY, | 32 | @@ -XXX,XX +XXX,XX @@ enum FslIMX6ULConfiguration { |
29 | @@ -XXX,XX +XXX,XX @@ enum { | 33 | FSL_IMX6UL_NUM_ADCS = 2, |
30 | AW_H3_DEV_GIC_VCPU, | 34 | FSL_IMX6UL_NUM_USB_PHYS = 2, |
31 | AW_H3_DEV_RTC, | 35 | FSL_IMX6UL_NUM_USBS = 2, |
32 | AW_H3_DEV_CPUCFG, | 36 | + FSL_IMX6UL_NUM_SAIS = 3, |
33 | + AW_H3_DEV_R_TWI, | 37 | + FSL_IMX6UL_NUM_CANS = 2, |
34 | AW_H3_DEV_SDRAM | 38 | + FSL_IMX6UL_NUM_PWMS = 4, |
35 | }; | 39 | }; |
36 | 40 | ||
37 | @@ -XXX,XX +XXX,XX @@ struct AwH3State { | 41 | struct FslIMX6ULState { |
38 | AwSidState sid; | 42 | @@ -XXX,XX +XXX,XX @@ struct FslIMX6ULState { |
39 | AwSdHostState mmc0; | 43 | |
40 | AWI2CState i2c0; | 44 | enum FslIMX6ULMemoryMap { |
41 | + AWI2CState i2c1; | 45 | FSL_IMX6UL_MMDC_ADDR = 0x80000000, |
42 | + AWI2CState i2c2; | 46 | - FSL_IMX6UL_MMDC_SIZE = 2 * 1024 * 1024 * 1024UL, |
43 | + AWI2CState r_twi; | 47 | + FSL_IMX6UL_MMDC_SIZE = (2 * GiB), |
44 | AwSun8iEmacState emac; | 48 | |
45 | AwRtcState rtc; | 49 | FSL_IMX6UL_QSPI1_MEM_ADDR = 0x60000000, |
46 | GICState gic; | 50 | - FSL_IMX6UL_EIM_ALIAS_ADDR = 0x58000000, |
47 | diff --git a/hw/arm/allwinner-h3.c b/hw/arm/allwinner-h3.c | 51 | - FSL_IMX6UL_EIM_CS_ADDR = 0x50000000, |
52 | - FSL_IMX6UL_AES_ENCRYPT_ADDR = 0x10000000, | ||
53 | - FSL_IMX6UL_QSPI1_RX_ADDR = 0x0C000000, | ||
54 | + FSL_IMX6UL_QSPI1_MEM_SIZE = (256 * MiB), | ||
55 | |||
56 | - /* AIPS-2 */ | ||
57 | + FSL_IMX6UL_EIM_ALIAS_ADDR = 0x58000000, | ||
58 | + FSL_IMX6UL_EIM_ALIAS_SIZE = (128 * MiB), | ||
59 | + | ||
60 | + FSL_IMX6UL_EIM_CS_ADDR = 0x50000000, | ||
61 | + FSL_IMX6UL_EIM_CS_SIZE = (128 * MiB), | ||
62 | + | ||
63 | + FSL_IMX6UL_AES_ENCRYPT_ADDR = 0x10000000, | ||
64 | + FSL_IMX6UL_AES_ENCRYPT_SIZE = (1 * MiB), | ||
65 | + | ||
66 | + FSL_IMX6UL_QSPI1_RX_ADDR = 0x0C000000, | ||
67 | + FSL_IMX6UL_QSPI1_RX_SIZE = (32 * MiB), | ||
68 | + | ||
69 | + /* AIPS-2 Begin */ | ||
70 | FSL_IMX6UL_UART6_ADDR = 0x021FC000, | ||
71 | + | ||
72 | FSL_IMX6UL_I2C4_ADDR = 0x021F8000, | ||
73 | + | ||
74 | FSL_IMX6UL_UART5_ADDR = 0x021F4000, | ||
75 | FSL_IMX6UL_UART4_ADDR = 0x021F0000, | ||
76 | FSL_IMX6UL_UART3_ADDR = 0x021EC000, | ||
77 | FSL_IMX6UL_UART2_ADDR = 0x021E8000, | ||
78 | + | ||
79 | FSL_IMX6UL_WDOG3_ADDR = 0x021E4000, | ||
80 | + | ||
81 | FSL_IMX6UL_QSPI_ADDR = 0x021E0000, | ||
82 | + FSL_IMX6UL_QSPI_SIZE = 0x500, | ||
83 | + | ||
84 | FSL_IMX6UL_SYS_CNT_CTRL_ADDR = 0x021DC000, | ||
85 | + FSL_IMX6UL_SYS_CNT_CTRL_SIZE = (16 * KiB), | ||
86 | + | ||
87 | FSL_IMX6UL_SYS_CNT_CMP_ADDR = 0x021D8000, | ||
88 | + FSL_IMX6UL_SYS_CNT_CMP_SIZE = (16 * KiB), | ||
89 | + | ||
90 | FSL_IMX6UL_SYS_CNT_RD_ADDR = 0x021D4000, | ||
91 | + FSL_IMX6UL_SYS_CNT_RD_SIZE = (16 * KiB), | ||
92 | + | ||
93 | FSL_IMX6UL_TZASC_ADDR = 0x021D0000, | ||
94 | + FSL_IMX6UL_TZASC_SIZE = (16 * KiB), | ||
95 | + | ||
96 | FSL_IMX6UL_PXP_ADDR = 0x021CC000, | ||
97 | + FSL_IMX6UL_PXP_SIZE = (16 * KiB), | ||
98 | + | ||
99 | FSL_IMX6UL_LCDIF_ADDR = 0x021C8000, | ||
100 | + FSL_IMX6UL_LCDIF_SIZE = 0x100, | ||
101 | + | ||
102 | FSL_IMX6UL_CSI_ADDR = 0x021C4000, | ||
103 | + FSL_IMX6UL_CSI_SIZE = 0x100, | ||
104 | + | ||
105 | FSL_IMX6UL_CSU_ADDR = 0x021C0000, | ||
106 | + FSL_IMX6UL_CSU_SIZE = (16 * KiB), | ||
107 | + | ||
108 | FSL_IMX6UL_OCOTP_CTRL_ADDR = 0x021BC000, | ||
109 | + FSL_IMX6UL_OCOTP_CTRL_SIZE = (4 * KiB), | ||
110 | + | ||
111 | FSL_IMX6UL_EIM_ADDR = 0x021B8000, | ||
112 | + FSL_IMX6UL_EIM_SIZE = 0x100, | ||
113 | + | ||
114 | FSL_IMX6UL_SIM2_ADDR = 0x021B4000, | ||
115 | + | ||
116 | FSL_IMX6UL_MMDC_CFG_ADDR = 0x021B0000, | ||
117 | + FSL_IMX6UL_MMDC_CFG_SIZE = (4 * KiB), | ||
118 | + | ||
119 | FSL_IMX6UL_ROMCP_ADDR = 0x021AC000, | ||
120 | + FSL_IMX6UL_ROMCP_SIZE = 0x300, | ||
121 | + | ||
122 | FSL_IMX6UL_I2C3_ADDR = 0x021A8000, | ||
123 | FSL_IMX6UL_I2C2_ADDR = 0x021A4000, | ||
124 | FSL_IMX6UL_I2C1_ADDR = 0x021A0000, | ||
125 | + | ||
126 | FSL_IMX6UL_ADC2_ADDR = 0x0219C000, | ||
127 | FSL_IMX6UL_ADC1_ADDR = 0x02198000, | ||
128 | + FSL_IMX6UL_ADCn_SIZE = 0x100, | ||
129 | + | ||
130 | FSL_IMX6UL_USDHC2_ADDR = 0x02194000, | ||
131 | FSL_IMX6UL_USDHC1_ADDR = 0x02190000, | ||
132 | - FSL_IMX6UL_SIM1_ADDR = 0x0218C000, | ||
133 | - FSL_IMX6UL_ENET1_ADDR = 0x02188000, | ||
134 | - FSL_IMX6UL_USBO2_USBMISC_ADDR = 0x02184800, | ||
135 | - FSL_IMX6UL_USBO2_USB_ADDR = 0x02184000, | ||
136 | - FSL_IMX6UL_USBO2_PL301_ADDR = 0x02180000, | ||
137 | - FSL_IMX6UL_AIPS2_CFG_ADDR = 0x0217C000, | ||
138 | - FSL_IMX6UL_CAAM_ADDR = 0x02140000, | ||
139 | - FSL_IMX6UL_A7MPCORE_DAP_ADDR = 0x02100000, | ||
140 | |||
141 | - /* AIPS-1 */ | ||
142 | + FSL_IMX6UL_SIM1_ADDR = 0x0218C000, | ||
143 | + FSL_IMX6UL_SIMn_SIZE = (16 * KiB), | ||
144 | + | ||
145 | + FSL_IMX6UL_ENET1_ADDR = 0x02188000, | ||
146 | + | ||
147 | + FSL_IMX6UL_USBO2_USBMISC_ADDR = 0x02184800, | ||
148 | + FSL_IMX6UL_USBO2_USB1_ADDR = 0x02184000, | ||
149 | + FSL_IMX6UL_USBO2_USB2_ADDR = 0x02184200, | ||
150 | + | ||
151 | + FSL_IMX6UL_USBO2_PL301_ADDR = 0x02180000, | ||
152 | + FSL_IMX6UL_USBO2_PL301_SIZE = (16 * KiB), | ||
153 | + | ||
154 | + FSL_IMX6UL_AIPS2_CFG_ADDR = 0x0217C000, | ||
155 | + FSL_IMX6UL_AIPS2_CFG_SIZE = 0x100, | ||
156 | + | ||
157 | + FSL_IMX6UL_CAAM_ADDR = 0x02140000, | ||
158 | + FSL_IMX6UL_CAAM_SIZE = (16 * KiB), | ||
159 | + | ||
160 | + FSL_IMX6UL_A7MPCORE_DAP_ADDR = 0x02100000, | ||
161 | + FSL_IMX6UL_A7MPCORE_DAP_SIZE = (4 * KiB), | ||
162 | + /* AIPS-2 End */ | ||
163 | + | ||
164 | + /* AIPS-1 Begin */ | ||
165 | FSL_IMX6UL_PWM8_ADDR = 0x020FC000, | ||
166 | FSL_IMX6UL_PWM7_ADDR = 0x020F8000, | ||
167 | FSL_IMX6UL_PWM6_ADDR = 0x020F4000, | ||
168 | FSL_IMX6UL_PWM5_ADDR = 0x020F0000, | ||
169 | + | ||
170 | FSL_IMX6UL_SDMA_ADDR = 0x020EC000, | ||
171 | + FSL_IMX6UL_SDMA_SIZE = 0x300, | ||
172 | + | ||
173 | FSL_IMX6UL_GPT2_ADDR = 0x020E8000, | ||
174 | + | ||
175 | FSL_IMX6UL_IOMUXC_GPR_ADDR = 0x020E4000, | ||
176 | + FSL_IMX6UL_IOMUXC_GPR_SIZE = 0x40, | ||
177 | + | ||
178 | FSL_IMX6UL_IOMUXC_ADDR = 0x020E0000, | ||
179 | + FSL_IMX6UL_IOMUXC_SIZE = 0x700, | ||
180 | + | ||
181 | FSL_IMX6UL_GPC_ADDR = 0x020DC000, | ||
182 | + | ||
183 | FSL_IMX6UL_SRC_ADDR = 0x020D8000, | ||
184 | + | ||
185 | FSL_IMX6UL_EPIT2_ADDR = 0x020D4000, | ||
186 | FSL_IMX6UL_EPIT1_ADDR = 0x020D0000, | ||
187 | + | ||
188 | FSL_IMX6UL_SNVS_HP_ADDR = 0x020CC000, | ||
189 | + | ||
190 | FSL_IMX6UL_USBPHY2_ADDR = 0x020CA000, | ||
191 | - FSL_IMX6UL_USBPHY2_SIZE = (4 * 1024), | ||
192 | FSL_IMX6UL_USBPHY1_ADDR = 0x020C9000, | ||
193 | - FSL_IMX6UL_USBPHY1_SIZE = (4 * 1024), | ||
194 | + | ||
195 | FSL_IMX6UL_ANALOG_ADDR = 0x020C8000, | ||
196 | + FSL_IMX6UL_ANALOG_SIZE = 0x300, | ||
197 | + | ||
198 | FSL_IMX6UL_CCM_ADDR = 0x020C4000, | ||
199 | + | ||
200 | FSL_IMX6UL_WDOG2_ADDR = 0x020C0000, | ||
201 | FSL_IMX6UL_WDOG1_ADDR = 0x020BC000, | ||
202 | + | ||
203 | FSL_IMX6UL_KPP_ADDR = 0x020B8000, | ||
204 | + FSL_IMX6UL_KPP_SIZE = 0x10, | ||
205 | + | ||
206 | FSL_IMX6UL_ENET2_ADDR = 0x020B4000, | ||
207 | + | ||
208 | FSL_IMX6UL_SNVS_LP_ADDR = 0x020B0000, | ||
209 | + FSL_IMX6UL_SNVS_LP_SIZE = (16 * KiB), | ||
210 | + | ||
211 | FSL_IMX6UL_GPIO5_ADDR = 0x020AC000, | ||
212 | FSL_IMX6UL_GPIO4_ADDR = 0x020A8000, | ||
213 | FSL_IMX6UL_GPIO3_ADDR = 0x020A4000, | ||
214 | FSL_IMX6UL_GPIO2_ADDR = 0x020A0000, | ||
215 | FSL_IMX6UL_GPIO1_ADDR = 0x0209C000, | ||
216 | + | ||
217 | FSL_IMX6UL_GPT1_ADDR = 0x02098000, | ||
218 | + | ||
219 | FSL_IMX6UL_CAN2_ADDR = 0x02094000, | ||
220 | FSL_IMX6UL_CAN1_ADDR = 0x02090000, | ||
221 | + FSL_IMX6UL_CANn_SIZE = (4 * KiB), | ||
222 | + | ||
223 | FSL_IMX6UL_PWM4_ADDR = 0x0208C000, | ||
224 | FSL_IMX6UL_PWM3_ADDR = 0x02088000, | ||
225 | FSL_IMX6UL_PWM2_ADDR = 0x02084000, | ||
226 | FSL_IMX6UL_PWM1_ADDR = 0x02080000, | ||
227 | + FSL_IMX6UL_PWMn_SIZE = 0x20, | ||
228 | + | ||
229 | FSL_IMX6UL_AIPS1_CFG_ADDR = 0x0207C000, | ||
230 | + FSL_IMX6UL_AIPS1_CFG_SIZE = (16 * KiB), | ||
231 | + | ||
232 | FSL_IMX6UL_BEE_ADDR = 0x02044000, | ||
233 | + FSL_IMX6UL_BEE_SIZE = (16 * KiB), | ||
234 | + | ||
235 | FSL_IMX6UL_TOUCH_CTRL_ADDR = 0x02040000, | ||
236 | + FSL_IMX6UL_TOUCH_CTRL_SIZE = 0x100, | ||
237 | + | ||
238 | FSL_IMX6UL_SPBA_ADDR = 0x0203C000, | ||
239 | + FSL_IMX6UL_SPBA_SIZE = 0x100, | ||
240 | + | ||
241 | FSL_IMX6UL_ASRC_ADDR = 0x02034000, | ||
242 | + FSL_IMX6UL_ASRC_SIZE = 0x100, | ||
243 | + | ||
244 | FSL_IMX6UL_SAI3_ADDR = 0x02030000, | ||
245 | FSL_IMX6UL_SAI2_ADDR = 0x0202C000, | ||
246 | FSL_IMX6UL_SAI1_ADDR = 0x02028000, | ||
247 | + FSL_IMX6UL_SAIn_SIZE = 0x200, | ||
248 | + | ||
249 | FSL_IMX6UL_UART8_ADDR = 0x02024000, | ||
250 | FSL_IMX6UL_UART1_ADDR = 0x02020000, | ||
251 | FSL_IMX6UL_UART7_ADDR = 0x02018000, | ||
252 | + | ||
253 | FSL_IMX6UL_ECSPI4_ADDR = 0x02014000, | ||
254 | FSL_IMX6UL_ECSPI3_ADDR = 0x02010000, | ||
255 | FSL_IMX6UL_ECSPI2_ADDR = 0x0200C000, | ||
256 | FSL_IMX6UL_ECSPI1_ADDR = 0x02008000, | ||
257 | + | ||
258 | FSL_IMX6UL_SPDIF_ADDR = 0x02004000, | ||
259 | + FSL_IMX6UL_SPDIF_SIZE = 0x100, | ||
260 | + /* AIPS-1 End */ | ||
261 | + | ||
262 | + FSL_IMX6UL_BCH_ADDR = 0x01808000, | ||
263 | + FSL_IMX6UL_BCH_SIZE = 0x200, | ||
264 | + | ||
265 | + FSL_IMX6UL_GPMI_ADDR = 0x01806000, | ||
266 | + FSL_IMX6UL_GPMI_SIZE = 0x200, | ||
267 | |||
268 | FSL_IMX6UL_APBH_DMA_ADDR = 0x01804000, | ||
269 | - FSL_IMX6UL_APBH_DMA_SIZE = (32 * 1024), | ||
270 | + FSL_IMX6UL_APBH_DMA_SIZE = (4 * KiB), | ||
271 | |||
272 | FSL_IMX6UL_A7MPCORE_ADDR = 0x00A00000, | ||
273 | |||
274 | FSL_IMX6UL_OCRAM_ALIAS_ADDR = 0x00920000, | ||
275 | - FSL_IMX6UL_OCRAM_ALIAS_SIZE = 0x00060000, | ||
276 | + FSL_IMX6UL_OCRAM_ALIAS_SIZE = (384 * KiB), | ||
277 | + | ||
278 | FSL_IMX6UL_OCRAM_MEM_ADDR = 0x00900000, | ||
279 | - FSL_IMX6UL_OCRAM_MEM_SIZE = 0x00020000, | ||
280 | + FSL_IMX6UL_OCRAM_MEM_SIZE = (128 * KiB), | ||
281 | + | ||
282 | FSL_IMX6UL_CAAM_MEM_ADDR = 0x00100000, | ||
283 | - FSL_IMX6UL_CAAM_MEM_SIZE = 0x00008000, | ||
284 | + FSL_IMX6UL_CAAM_MEM_SIZE = (32 * KiB), | ||
285 | + | ||
286 | FSL_IMX6UL_ROM_ADDR = 0x00000000, | ||
287 | - FSL_IMX6UL_ROM_SIZE = 0x00018000, | ||
288 | + FSL_IMX6UL_ROM_SIZE = (96 * KiB), | ||
289 | }; | ||
290 | |||
291 | enum FslIMX6ULIRQs { | ||
292 | diff --git a/hw/arm/fsl-imx6ul.c b/hw/arm/fsl-imx6ul.c | ||
48 | index XXXXXXX..XXXXXXX 100644 | 293 | index XXXXXXX..XXXXXXX 100644 |
49 | --- a/hw/arm/allwinner-h3.c | 294 | --- a/hw/arm/fsl-imx6ul.c |
50 | +++ b/hw/arm/allwinner-h3.c | 295 | +++ b/hw/arm/fsl-imx6ul.c |
51 | @@ -XXX,XX +XXX,XX @@ const hwaddr allwinner_h3_memmap[] = { | 296 | @@ -XXX,XX +XXX,XX @@ static void fsl_imx6ul_init(Object *obj) |
52 | [AW_H3_DEV_UART2] = 0x01c28800, | 297 | object_initialize_child(obj, "snvs", &s->snvs, TYPE_IMX7_SNVS); |
53 | [AW_H3_DEV_UART3] = 0x01c28c00, | 298 | |
54 | [AW_H3_DEV_TWI0] = 0x01c2ac00, | 299 | /* |
55 | + [AW_H3_DEV_TWI1] = 0x01c2b000, | 300 | - * GPIOs 1 to 5 |
56 | + [AW_H3_DEV_TWI2] = 0x01c2b400, | 301 | + * GPIOs |
57 | [AW_H3_DEV_EMAC] = 0x01c30000, | 302 | */ |
58 | [AW_H3_DEV_DRAMCOM] = 0x01c62000, | 303 | for (i = 0; i < FSL_IMX6UL_NUM_GPIOS; i++) { |
59 | [AW_H3_DEV_DRAMCTL] = 0x01c63000, | 304 | snprintf(name, NAME_SIZE, "gpio%d", i); |
60 | @@ -XXX,XX +XXX,XX @@ const hwaddr allwinner_h3_memmap[] = { | 305 | @@ -XXX,XX +XXX,XX @@ static void fsl_imx6ul_init(Object *obj) |
61 | [AW_H3_DEV_GIC_VCPU] = 0x01c86000, | 306 | } |
62 | [AW_H3_DEV_RTC] = 0x01f00000, | 307 | |
63 | [AW_H3_DEV_CPUCFG] = 0x01f01c00, | 308 | /* |
64 | + [AW_H3_DEV_R_TWI] = 0x01f02400, | 309 | - * GPT 1, 2 |
65 | [AW_H3_DEV_SDRAM] = 0x40000000 | 310 | + * GPTs |
66 | }; | 311 | */ |
67 | 312 | for (i = 0; i < FSL_IMX6UL_NUM_GPTS; i++) { | |
68 | @@ -XXX,XX +XXX,XX @@ struct AwH3Unimplemented { | 313 | snprintf(name, NAME_SIZE, "gpt%d", i); |
69 | { "uart1", 0x01c28400, 1 * KiB }, | 314 | @@ -XXX,XX +XXX,XX @@ static void fsl_imx6ul_init(Object *obj) |
70 | { "uart2", 0x01c28800, 1 * KiB }, | 315 | } |
71 | { "uart3", 0x01c28c00, 1 * KiB }, | 316 | |
72 | - { "twi1", 0x01c2b000, 1 * KiB }, | 317 | /* |
73 | - { "twi2", 0x01c2b400, 1 * KiB }, | 318 | - * EPIT 1, 2 |
74 | { "scr", 0x01c2c400, 1 * KiB }, | 319 | + * EPITs |
75 | { "gpu", 0x01c40000, 64 * KiB }, | 320 | */ |
76 | { "hstmr", 0x01c60000, 4 * KiB }, | 321 | for (i = 0; i < FSL_IMX6UL_NUM_EPITS; i++) { |
77 | @@ -XXX,XX +XXX,XX @@ struct AwH3Unimplemented { | 322 | snprintf(name, NAME_SIZE, "epit%d", i + 1); |
78 | { "r_prcm", 0x01f01400, 1 * KiB }, | 323 | @@ -XXX,XX +XXX,XX @@ static void fsl_imx6ul_init(Object *obj) |
79 | { "r_twd", 0x01f01800, 1 * KiB }, | 324 | } |
80 | { "r_cir-rx", 0x01f02000, 1 * KiB }, | 325 | |
81 | - { "r_twi", 0x01f02400, 1 * KiB }, | 326 | /* |
82 | { "r_uart", 0x01f02800, 1 * KiB }, | 327 | - * eCSPI |
83 | { "r_pio", 0x01f02c00, 1 * KiB }, | 328 | + * eCSPIs |
84 | { "r_pwm", 0x01f03800, 1 * KiB }, | 329 | */ |
85 | @@ -XXX,XX +XXX,XX @@ enum { | 330 | for (i = 0; i < FSL_IMX6UL_NUM_ECSPIS; i++) { |
86 | AW_H3_GIC_SPI_UART2 = 2, | 331 | snprintf(name, NAME_SIZE, "spi%d", i + 1); |
87 | AW_H3_GIC_SPI_UART3 = 3, | 332 | @@ -XXX,XX +XXX,XX @@ static void fsl_imx6ul_init(Object *obj) |
88 | AW_H3_GIC_SPI_TWI0 = 6, | 333 | } |
89 | + AW_H3_GIC_SPI_TWI1 = 7, | 334 | |
90 | + AW_H3_GIC_SPI_TWI2 = 8, | 335 | /* |
91 | AW_H3_GIC_SPI_TIMER0 = 18, | 336 | - * I2C |
92 | AW_H3_GIC_SPI_TIMER1 = 19, | 337 | + * I2Cs |
93 | + AW_H3_GIC_SPI_R_TWI = 44, | 338 | */ |
94 | AW_H3_GIC_SPI_MMC0 = 60, | 339 | for (i = 0; i < FSL_IMX6UL_NUM_I2CS; i++) { |
95 | AW_H3_GIC_SPI_EHCI0 = 72, | 340 | snprintf(name, NAME_SIZE, "i2c%d", i + 1); |
96 | AW_H3_GIC_SPI_OHCI0 = 73, | 341 | @@ -XXX,XX +XXX,XX @@ static void fsl_imx6ul_init(Object *obj) |
97 | @@ -XXX,XX +XXX,XX @@ static void allwinner_h3_init(Object *obj) | 342 | } |
98 | 343 | ||
99 | object_initialize_child(obj, "rtc", &s->rtc, TYPE_AW_RTC_SUN6I); | 344 | /* |
100 | 345 | - * UART | |
101 | - object_initialize_child(obj, "twi0", &s->i2c0, TYPE_AW_I2C); | 346 | + * UARTs |
102 | + object_initialize_child(obj, "twi0", &s->i2c0, TYPE_AW_I2C_SUN6I); | 347 | */ |
103 | + object_initialize_child(obj, "twi1", &s->i2c1, TYPE_AW_I2C_SUN6I); | 348 | for (i = 0; i < FSL_IMX6UL_NUM_UARTS; i++) { |
104 | + object_initialize_child(obj, "twi2", &s->i2c2, TYPE_AW_I2C_SUN6I); | 349 | snprintf(name, NAME_SIZE, "uart%d", i); |
105 | + object_initialize_child(obj, "r_twi", &s->r_twi, TYPE_AW_I2C_SUN6I); | 350 | @@ -XXX,XX +XXX,XX @@ static void fsl_imx6ul_init(Object *obj) |
106 | } | 351 | } |
107 | 352 | ||
108 | static void allwinner_h3_realize(DeviceState *dev, Error **errp) | 353 | /* |
109 | @@ -XXX,XX +XXX,XX @@ static void allwinner_h3_realize(DeviceState *dev, Error **errp) | 354 | - * Ethernet |
110 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->i2c0), 0, | 355 | + * Ethernets |
111 | qdev_get_gpio_in(DEVICE(&s->gic), AW_H3_GIC_SPI_TWI0)); | 356 | */ |
112 | 357 | for (i = 0; i < FSL_IMX6UL_NUM_ETHS; i++) { | |
113 | + sysbus_realize(SYS_BUS_DEVICE(&s->i2c1), &error_fatal); | 358 | snprintf(name, NAME_SIZE, "eth%d", i); |
114 | + sysbus_mmio_map(SYS_BUS_DEVICE(&s->i2c1), 0, s->memmap[AW_H3_DEV_TWI1]); | 359 | object_initialize_child(obj, name, &s->eth[i], TYPE_IMX_ENET); |
115 | + sysbus_connect_irq(SYS_BUS_DEVICE(&s->i2c1), 0, | 360 | } |
116 | + qdev_get_gpio_in(DEVICE(&s->gic), AW_H3_GIC_SPI_TWI1)); | 361 | |
117 | + | 362 | - /* USB */ |
118 | + sysbus_realize(SYS_BUS_DEVICE(&s->i2c2), &error_fatal); | 363 | + /* |
119 | + sysbus_mmio_map(SYS_BUS_DEVICE(&s->i2c2), 0, s->memmap[AW_H3_DEV_TWI2]); | 364 | + * USB PHYs |
120 | + sysbus_connect_irq(SYS_BUS_DEVICE(&s->i2c2), 0, | 365 | + */ |
121 | + qdev_get_gpio_in(DEVICE(&s->gic), AW_H3_GIC_SPI_TWI2)); | 366 | for (i = 0; i < FSL_IMX6UL_NUM_USB_PHYS; i++) { |
122 | + | 367 | snprintf(name, NAME_SIZE, "usbphy%d", i); |
123 | + sysbus_realize(SYS_BUS_DEVICE(&s->r_twi), &error_fatal); | 368 | object_initialize_child(obj, name, &s->usbphy[i], TYPE_IMX_USBPHY); |
124 | + sysbus_mmio_map(SYS_BUS_DEVICE(&s->r_twi), 0, s->memmap[AW_H3_DEV_R_TWI]); | 369 | } |
125 | + sysbus_connect_irq(SYS_BUS_DEVICE(&s->r_twi), 0, | 370 | + |
126 | + qdev_get_gpio_in(DEVICE(&s->gic), AW_H3_GIC_SPI_R_TWI)); | 371 | + /* |
127 | + | 372 | + * USBs |
128 | /* Unimplemented devices */ | 373 | + */ |
129 | for (i = 0; i < ARRAY_SIZE(unimplemented); i++) { | 374 | for (i = 0; i < FSL_IMX6UL_NUM_USBS; i++) { |
130 | create_unimplemented_device(unimplemented[i].device_name, | 375 | snprintf(name, NAME_SIZE, "usb%d", i); |
376 | object_initialize_child(obj, name, &s->usb[i], TYPE_CHIPIDEA); | ||
377 | } | ||
378 | |||
379 | /* | ||
380 | - * SDHCI | ||
381 | + * SDHCIs | ||
382 | */ | ||
383 | for (i = 0; i < FSL_IMX6UL_NUM_USDHCS; i++) { | ||
384 | snprintf(name, NAME_SIZE, "usdhc%d", i); | ||
385 | @@ -XXX,XX +XXX,XX @@ static void fsl_imx6ul_init(Object *obj) | ||
386 | } | ||
387 | |||
388 | /* | ||
389 | - * Watchdog | ||
390 | + * Watchdogs | ||
391 | */ | ||
392 | for (i = 0; i < FSL_IMX6UL_NUM_WDTS; i++) { | ||
393 | snprintf(name, NAME_SIZE, "wdt%d", i); | ||
394 | @@ -XXX,XX +XXX,XX @@ static void fsl_imx6ul_realize(DeviceState *dev, Error **errp) | ||
395 | * A7MPCORE DAP | ||
396 | */ | ||
397 | create_unimplemented_device("a7mpcore-dap", FSL_IMX6UL_A7MPCORE_DAP_ADDR, | ||
398 | - 0x100000); | ||
399 | + FSL_IMX6UL_A7MPCORE_DAP_SIZE); | ||
400 | |||
401 | /* | ||
402 | - * GPT 1, 2 | ||
403 | + * GPTs | ||
404 | */ | ||
405 | for (i = 0; i < FSL_IMX6UL_NUM_GPTS; i++) { | ||
406 | static const hwaddr FSL_IMX6UL_GPTn_ADDR[FSL_IMX6UL_NUM_GPTS] = { | ||
407 | @@ -XXX,XX +XXX,XX @@ static void fsl_imx6ul_realize(DeviceState *dev, Error **errp) | ||
408 | } | ||
409 | |||
410 | /* | ||
411 | - * EPIT 1, 2 | ||
412 | + * EPITs | ||
413 | */ | ||
414 | for (i = 0; i < FSL_IMX6UL_NUM_EPITS; i++) { | ||
415 | static const hwaddr FSL_IMX6UL_EPITn_ADDR[FSL_IMX6UL_NUM_EPITS] = { | ||
416 | @@ -XXX,XX +XXX,XX @@ static void fsl_imx6ul_realize(DeviceState *dev, Error **errp) | ||
417 | } | ||
418 | |||
419 | /* | ||
420 | - * GPIO | ||
421 | + * GPIOs | ||
422 | */ | ||
423 | for (i = 0; i < FSL_IMX6UL_NUM_GPIOS; i++) { | ||
424 | static const hwaddr FSL_IMX6UL_GPIOn_ADDR[FSL_IMX6UL_NUM_GPIOS] = { | ||
425 | @@ -XXX,XX +XXX,XX @@ static void fsl_imx6ul_realize(DeviceState *dev, Error **errp) | ||
426 | } | ||
427 | |||
428 | /* | ||
429 | - * IOMUXC and IOMUXC_GPR | ||
430 | + * IOMUXC | ||
431 | */ | ||
432 | - for (i = 0; i < 1; i++) { | ||
433 | - static const hwaddr FSL_IMX6UL_IOMUXCn_ADDR[FSL_IMX6UL_NUM_IOMUXCS] = { | ||
434 | - FSL_IMX6UL_IOMUXC_ADDR, | ||
435 | - FSL_IMX6UL_IOMUXC_GPR_ADDR, | ||
436 | - }; | ||
437 | - | ||
438 | - snprintf(name, NAME_SIZE, "iomuxc%d", i); | ||
439 | - create_unimplemented_device(name, FSL_IMX6UL_IOMUXCn_ADDR[i], 0x4000); | ||
440 | - } | ||
441 | + create_unimplemented_device("iomuxc", FSL_IMX6UL_IOMUXC_ADDR, | ||
442 | + FSL_IMX6UL_IOMUXC_SIZE); | ||
443 | + create_unimplemented_device("iomuxc_gpr", FSL_IMX6UL_IOMUXC_GPR_ADDR, | ||
444 | + FSL_IMX6UL_IOMUXC_GPR_SIZE); | ||
445 | |||
446 | /* | ||
447 | * CCM | ||
448 | @@ -XXX,XX +XXX,XX @@ static void fsl_imx6ul_realize(DeviceState *dev, Error **errp) | ||
449 | sysbus_realize(SYS_BUS_DEVICE(&s->gpcv2), &error_abort); | ||
450 | sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpcv2), 0, FSL_IMX6UL_GPC_ADDR); | ||
451 | |||
452 | - /* Initialize all ECSPI */ | ||
453 | + /* | ||
454 | + * ECSPIs | ||
455 | + */ | ||
456 | for (i = 0; i < FSL_IMX6UL_NUM_ECSPIS; i++) { | ||
457 | static const hwaddr FSL_IMX6UL_SPIn_ADDR[FSL_IMX6UL_NUM_ECSPIS] = { | ||
458 | FSL_IMX6UL_ECSPI1_ADDR, | ||
459 | @@ -XXX,XX +XXX,XX @@ static void fsl_imx6ul_realize(DeviceState *dev, Error **errp) | ||
460 | } | ||
461 | |||
462 | /* | ||
463 | - * I2C | ||
464 | + * I2Cs | ||
465 | */ | ||
466 | for (i = 0; i < FSL_IMX6UL_NUM_I2CS; i++) { | ||
467 | static const hwaddr FSL_IMX6UL_I2Cn_ADDR[FSL_IMX6UL_NUM_I2CS] = { | ||
468 | @@ -XXX,XX +XXX,XX @@ static void fsl_imx6ul_realize(DeviceState *dev, Error **errp) | ||
469 | } | ||
470 | |||
471 | /* | ||
472 | - * UART | ||
473 | + * UARTs | ||
474 | */ | ||
475 | for (i = 0; i < FSL_IMX6UL_NUM_UARTS; i++) { | ||
476 | static const hwaddr FSL_IMX6UL_UARTn_ADDR[FSL_IMX6UL_NUM_UARTS] = { | ||
477 | @@ -XXX,XX +XXX,XX @@ static void fsl_imx6ul_realize(DeviceState *dev, Error **errp) | ||
478 | } | ||
479 | |||
480 | /* | ||
481 | - * Ethernet | ||
482 | + * Ethernets | ||
483 | * | ||
484 | * We must use two loops since phy_connected affects the other interface | ||
485 | * and we have to set all properties before calling sysbus_realize(). | ||
486 | @@ -XXX,XX +XXX,XX @@ static void fsl_imx6ul_realize(DeviceState *dev, Error **errp) | ||
487 | FSL_IMX6UL_ENETn_TIMER_IRQ[i])); | ||
488 | } | ||
489 | |||
490 | - /* USB */ | ||
491 | + /* | ||
492 | + * USB PHYs | ||
493 | + */ | ||
494 | for (i = 0; i < FSL_IMX6UL_NUM_USB_PHYS; i++) { | ||
495 | + static const hwaddr | ||
496 | + FSL_IMX6UL_USB_PHYn_ADDR[FSL_IMX6UL_NUM_USB_PHYS] = { | ||
497 | + FSL_IMX6UL_USBPHY1_ADDR, | ||
498 | + FSL_IMX6UL_USBPHY2_ADDR, | ||
499 | + }; | ||
500 | + | ||
501 | sysbus_realize(SYS_BUS_DEVICE(&s->usbphy[i]), &error_abort); | ||
502 | sysbus_mmio_map(SYS_BUS_DEVICE(&s->usbphy[i]), 0, | ||
503 | - FSL_IMX6UL_USBPHY1_ADDR + i * 0x1000); | ||
504 | + FSL_IMX6UL_USB_PHYn_ADDR[i]); | ||
505 | } | ||
506 | |||
507 | + /* | ||
508 | + * USBs | ||
509 | + */ | ||
510 | for (i = 0; i < FSL_IMX6UL_NUM_USBS; i++) { | ||
511 | + static const hwaddr FSL_IMX6UL_USB02_USBn_ADDR[FSL_IMX6UL_NUM_USBS] = { | ||
512 | + FSL_IMX6UL_USBO2_USB1_ADDR, | ||
513 | + FSL_IMX6UL_USBO2_USB2_ADDR, | ||
514 | + }; | ||
515 | + | ||
516 | static const int FSL_IMX6UL_USBn_IRQ[] = { | ||
517 | FSL_IMX6UL_USB1_IRQ, | ||
518 | FSL_IMX6UL_USB2_IRQ, | ||
519 | }; | ||
520 | + | ||
521 | sysbus_realize(SYS_BUS_DEVICE(&s->usb[i]), &error_abort); | ||
522 | sysbus_mmio_map(SYS_BUS_DEVICE(&s->usb[i]), 0, | ||
523 | - FSL_IMX6UL_USBO2_USB_ADDR + i * 0x200); | ||
524 | + FSL_IMX6UL_USB02_USBn_ADDR[i]); | ||
525 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->usb[i]), 0, | ||
526 | qdev_get_gpio_in(DEVICE(&s->a7mpcore), | ||
527 | FSL_IMX6UL_USBn_IRQ[i])); | ||
528 | } | ||
529 | |||
530 | /* | ||
531 | - * USDHC | ||
532 | + * USDHCs | ||
533 | */ | ||
534 | for (i = 0; i < FSL_IMX6UL_NUM_USDHCS; i++) { | ||
535 | static const hwaddr FSL_IMX6UL_USDHCn_ADDR[FSL_IMX6UL_NUM_USDHCS] = { | ||
536 | @@ -XXX,XX +XXX,XX @@ static void fsl_imx6ul_realize(DeviceState *dev, Error **errp) | ||
537 | sysbus_mmio_map(SYS_BUS_DEVICE(&s->snvs), 0, FSL_IMX6UL_SNVS_HP_ADDR); | ||
538 | |||
539 | /* | ||
540 | - * Watchdog | ||
541 | + * Watchdogs | ||
542 | */ | ||
543 | for (i = 0; i < FSL_IMX6UL_NUM_WDTS; i++) { | ||
544 | static const hwaddr FSL_IMX6UL_WDOGn_ADDR[FSL_IMX6UL_NUM_WDTS] = { | ||
545 | @@ -XXX,XX +XXX,XX @@ static void fsl_imx6ul_realize(DeviceState *dev, Error **errp) | ||
546 | FSL_IMX6UL_WDOG2_ADDR, | ||
547 | FSL_IMX6UL_WDOG3_ADDR, | ||
548 | }; | ||
549 | + | ||
550 | static const int FSL_IMX6UL_WDOGn_IRQ[FSL_IMX6UL_NUM_WDTS] = { | ||
551 | FSL_IMX6UL_WDOG1_IRQ, | ||
552 | FSL_IMX6UL_WDOG2_IRQ, | ||
553 | @@ -XXX,XX +XXX,XX @@ static void fsl_imx6ul_realize(DeviceState *dev, Error **errp) | ||
554 | /* | ||
555 | * SDMA | ||
556 | */ | ||
557 | - create_unimplemented_device("sdma", FSL_IMX6UL_SDMA_ADDR, 0x4000); | ||
558 | + create_unimplemented_device("sdma", FSL_IMX6UL_SDMA_ADDR, | ||
559 | + FSL_IMX6UL_SDMA_SIZE); | ||
560 | |||
561 | /* | ||
562 | - * SAI (Audio SSI (Synchronous Serial Interface)) | ||
563 | + * SAIs (Audio SSI (Synchronous Serial Interface)) | ||
564 | */ | ||
565 | - create_unimplemented_device("sai1", FSL_IMX6UL_SAI1_ADDR, 0x4000); | ||
566 | - create_unimplemented_device("sai2", FSL_IMX6UL_SAI2_ADDR, 0x4000); | ||
567 | - create_unimplemented_device("sai3", FSL_IMX6UL_SAI3_ADDR, 0x4000); | ||
568 | + for (i = 0; i < FSL_IMX6UL_NUM_SAIS; i++) { | ||
569 | + static const hwaddr FSL_IMX6UL_SAIn_ADDR[FSL_IMX6UL_NUM_SAIS] = { | ||
570 | + FSL_IMX6UL_SAI1_ADDR, | ||
571 | + FSL_IMX6UL_SAI2_ADDR, | ||
572 | + FSL_IMX6UL_SAI3_ADDR, | ||
573 | + }; | ||
574 | + | ||
575 | + snprintf(name, NAME_SIZE, "sai%d", i); | ||
576 | + create_unimplemented_device(name, FSL_IMX6UL_SAIn_ADDR[i], | ||
577 | + FSL_IMX6UL_SAIn_SIZE); | ||
578 | + } | ||
579 | |||
580 | /* | ||
581 | - * PWM | ||
582 | + * PWMs | ||
583 | */ | ||
584 | - create_unimplemented_device("pwm1", FSL_IMX6UL_PWM1_ADDR, 0x4000); | ||
585 | - create_unimplemented_device("pwm2", FSL_IMX6UL_PWM2_ADDR, 0x4000); | ||
586 | - create_unimplemented_device("pwm3", FSL_IMX6UL_PWM3_ADDR, 0x4000); | ||
587 | - create_unimplemented_device("pwm4", FSL_IMX6UL_PWM4_ADDR, 0x4000); | ||
588 | + for (i = 0; i < FSL_IMX6UL_NUM_PWMS; i++) { | ||
589 | + static const hwaddr FSL_IMX6UL_PWMn_ADDR[FSL_IMX6UL_NUM_PWMS] = { | ||
590 | + FSL_IMX6UL_PWM1_ADDR, | ||
591 | + FSL_IMX6UL_PWM2_ADDR, | ||
592 | + FSL_IMX6UL_PWM3_ADDR, | ||
593 | + FSL_IMX6UL_PWM4_ADDR, | ||
594 | + }; | ||
595 | + | ||
596 | + snprintf(name, NAME_SIZE, "pwm%d", i); | ||
597 | + create_unimplemented_device(name, FSL_IMX6UL_PWMn_ADDR[i], | ||
598 | + FSL_IMX6UL_PWMn_SIZE); | ||
599 | + } | ||
600 | |||
601 | /* | ||
602 | * Audio ASRC (asynchronous sample rate converter) | ||
603 | */ | ||
604 | - create_unimplemented_device("asrc", FSL_IMX6UL_ASRC_ADDR, 0x4000); | ||
605 | + create_unimplemented_device("asrc", FSL_IMX6UL_ASRC_ADDR, | ||
606 | + FSL_IMX6UL_ASRC_SIZE); | ||
607 | |||
608 | /* | ||
609 | - * CAN | ||
610 | + * CANs | ||
611 | */ | ||
612 | - create_unimplemented_device("can1", FSL_IMX6UL_CAN1_ADDR, 0x4000); | ||
613 | - create_unimplemented_device("can2", FSL_IMX6UL_CAN2_ADDR, 0x4000); | ||
614 | + for (i = 0; i < FSL_IMX6UL_NUM_CANS; i++) { | ||
615 | + static const hwaddr FSL_IMX6UL_CANn_ADDR[FSL_IMX6UL_NUM_CANS] = { | ||
616 | + FSL_IMX6UL_CAN1_ADDR, | ||
617 | + FSL_IMX6UL_CAN2_ADDR, | ||
618 | + }; | ||
619 | + | ||
620 | + snprintf(name, NAME_SIZE, "can%d", i); | ||
621 | + create_unimplemented_device(name, FSL_IMX6UL_CANn_ADDR[i], | ||
622 | + FSL_IMX6UL_CANn_SIZE); | ||
623 | + } | ||
624 | |||
625 | /* | ||
626 | * APHB_DMA | ||
627 | @@ -XXX,XX +XXX,XX @@ static void fsl_imx6ul_realize(DeviceState *dev, Error **errp) | ||
628 | }; | ||
629 | |||
630 | snprintf(name, NAME_SIZE, "adc%d", i); | ||
631 | - create_unimplemented_device(name, FSL_IMX6UL_ADCn_ADDR[i], 0x4000); | ||
632 | + create_unimplemented_device(name, FSL_IMX6UL_ADCn_ADDR[i], | ||
633 | + FSL_IMX6UL_ADCn_SIZE); | ||
634 | } | ||
635 | |||
636 | /* | ||
637 | * LCD | ||
638 | */ | ||
639 | - create_unimplemented_device("lcdif", FSL_IMX6UL_LCDIF_ADDR, 0x4000); | ||
640 | + create_unimplemented_device("lcdif", FSL_IMX6UL_LCDIF_ADDR, | ||
641 | + FSL_IMX6UL_LCDIF_SIZE); | ||
642 | |||
643 | /* | ||
644 | * ROM memory | ||
131 | -- | 645 | -- |
132 | 2.34.1 | 646 | 2.34.1 | diff view generated by jsdifflib |
1 | From: Richard Henderson <richard.henderson@linaro.org> | 1 | From: Jean-Christophe Dubois <jcd@tribudubois.net> |
---|---|---|---|
2 | 2 | ||
3 | This will make the function usable between SVE and SME. | 3 | * Add TZASC as unimplemented device. |
4 | - Allow bare metal application to access this (unimplemented) device | ||
5 | * Add CSU as unimplemented device. | ||
6 | - Allow bare metal application to access this (unimplemented) device | ||
7 | * Add 4 missing PWM devices | ||
4 | 8 | ||
5 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | 9 | Signed-off-by: Jean-Christophe Dubois <jcd@tribudubois.net> |
6 | Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> | 10 | Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> |
7 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | 11 | Message-id: 59e4dc56e14eccfefd379275ec19048dff9c10b3.1692964892.git.jcd@tribudubois.net |
8 | Message-id: 20230227213329.793795-9-richard.henderson@linaro.org | ||
9 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 12 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
10 | --- | 13 | --- |
11 | target/arm/gdbstub64.c | 28 ++++++++++++++-------------- | 14 | include/hw/arm/fsl-imx6ul.h | 2 +- |
12 | 1 file changed, 14 insertions(+), 14 deletions(-) | 15 | hw/arm/fsl-imx6ul.c | 16 ++++++++++++++++ |
16 | 2 files changed, 17 insertions(+), 1 deletion(-) | ||
13 | 17 | ||
14 | diff --git a/target/arm/gdbstub64.c b/target/arm/gdbstub64.c | 18 | diff --git a/include/hw/arm/fsl-imx6ul.h b/include/hw/arm/fsl-imx6ul.h |
15 | index XXXXXXX..XXXXXXX 100644 | 19 | index XXXXXXX..XXXXXXX 100644 |
16 | --- a/target/arm/gdbstub64.c | 20 | --- a/include/hw/arm/fsl-imx6ul.h |
17 | +++ b/target/arm/gdbstub64.c | 21 | +++ b/include/hw/arm/fsl-imx6ul.h |
18 | @@ -XXX,XX +XXX,XX @@ int aarch64_gdb_set_sve_reg(CPUARMState *env, uint8_t *buf, int reg) | 22 | @@ -XXX,XX +XXX,XX @@ enum FslIMX6ULConfiguration { |
19 | return 0; | 23 | FSL_IMX6UL_NUM_USBS = 2, |
20 | } | 24 | FSL_IMX6UL_NUM_SAIS = 3, |
21 | 25 | FSL_IMX6UL_NUM_CANS = 2, | |
22 | -static void output_vector_union_type(GString *s, int reg_width) | 26 | - FSL_IMX6UL_NUM_PWMS = 4, |
23 | +static void output_vector_union_type(GString *s, int reg_width, | 27 | + FSL_IMX6UL_NUM_PWMS = 8, |
24 | + const char *name) | 28 | }; |
25 | { | 29 | |
26 | struct TypeSize { | 30 | struct FslIMX6ULState { |
27 | const char *gdb_type; | 31 | diff --git a/hw/arm/fsl-imx6ul.c b/hw/arm/fsl-imx6ul.c |
28 | @@ -XXX,XX +XXX,XX @@ static void output_vector_union_type(GString *s, int reg_width) | 32 | index XXXXXXX..XXXXXXX 100644 |
29 | }; | 33 | --- a/hw/arm/fsl-imx6ul.c |
30 | 34 | +++ b/hw/arm/fsl-imx6ul.c | |
31 | static const char suf[] = { 'q', 'd', 's', 'h', 'b' }; | 35 | @@ -XXX,XX +XXX,XX @@ static void fsl_imx6ul_realize(DeviceState *dev, Error **errp) |
32 | - | 36 | FSL_IMX6UL_PWM2_ADDR, |
33 | - g_autoptr(GString) ts = g_string_new(""); | 37 | FSL_IMX6UL_PWM3_ADDR, |
34 | int i, j, bits; | 38 | FSL_IMX6UL_PWM4_ADDR, |
35 | 39 | + FSL_IMX6UL_PWM5_ADDR, | |
36 | /* First define types and totals in a whole VL */ | 40 | + FSL_IMX6UL_PWM6_ADDR, |
37 | for (i = 0; i < ARRAY_SIZE(vec_lanes); i++) { | 41 | + FSL_IMX6UL_PWM7_ADDR, |
38 | - int count = reg_width / vec_lanes[i].size; | 42 | + FSL_IMX6UL_PWM8_ADDR, |
39 | - g_string_printf(ts, "svev%c%c", vec_lanes[i].sz, vec_lanes[i].suffix); | 43 | }; |
40 | g_string_append_printf(s, | 44 | |
41 | - "<vector id=\"%s\" type=\"%s\" count=\"%d\"/>", | 45 | snprintf(name, NAME_SIZE, "pwm%d", i); |
42 | - ts->str, vec_lanes[i].gdb_type, count); | 46 | @@ -XXX,XX +XXX,XX @@ static void fsl_imx6ul_realize(DeviceState *dev, Error **errp) |
43 | + "<vector id=\"%s%c%c\" type=\"%s\" count=\"%d\"/>", | 47 | create_unimplemented_device("lcdif", FSL_IMX6UL_LCDIF_ADDR, |
44 | + name, vec_lanes[i].sz, vec_lanes[i].suffix, | 48 | FSL_IMX6UL_LCDIF_SIZE); |
45 | + vec_lanes[i].gdb_type, reg_width / vec_lanes[i].size); | 49 | |
46 | } | 50 | + /* |
51 | + * CSU | ||
52 | + */ | ||
53 | + create_unimplemented_device("csu", FSL_IMX6UL_CSU_ADDR, | ||
54 | + FSL_IMX6UL_CSU_SIZE); | ||
55 | + | ||
56 | + /* | ||
57 | + * TZASC | ||
58 | + */ | ||
59 | + create_unimplemented_device("tzasc", FSL_IMX6UL_TZASC_ADDR, | ||
60 | + FSL_IMX6UL_TZASC_SIZE); | ||
47 | + | 61 | + |
48 | /* | 62 | /* |
49 | * Now define a union for each size group containing unsigned and | 63 | * ROM memory |
50 | * signed and potentially float versions of each size from 128 to | ||
51 | * 8 bits. | ||
52 | */ | 64 | */ |
53 | for (bits = 128, i = 0; bits >= 8; bits /= 2, i++) { | ||
54 | - g_string_append_printf(s, "<union id=\"svevn%c\">", suf[i]); | ||
55 | + g_string_append_printf(s, "<union id=\"%sn%c\">", name, suf[i]); | ||
56 | for (j = 0; j < ARRAY_SIZE(vec_lanes); j++) { | ||
57 | if (vec_lanes[j].size == bits) { | ||
58 | - g_string_append_printf(s, "<field name=\"%c\" type=\"svev%c%c\"/>", | ||
59 | - vec_lanes[j].suffix, | ||
60 | + g_string_append_printf(s, "<field name=\"%c\" type=\"%s%c%c\"/>", | ||
61 | + vec_lanes[j].suffix, name, | ||
62 | vec_lanes[j].sz, vec_lanes[j].suffix); | ||
63 | } | ||
64 | } | ||
65 | g_string_append(s, "</union>"); | ||
66 | } | ||
67 | + | ||
68 | /* And now the final union of unions */ | ||
69 | - g_string_append(s, "<union id=\"svev\">"); | ||
70 | + g_string_append_printf(s, "<union id=\"%s\">", name); | ||
71 | for (bits = 128, i = 0; bits >= 8; bits /= 2, i++) { | ||
72 | - g_string_append_printf(s, "<field name=\"%c\" type=\"svevn%c\"/>", | ||
73 | - suf[i], suf[i]); | ||
74 | + g_string_append_printf(s, "<field name=\"%c\" type=\"%sn%c\"/>", | ||
75 | + suf[i], name, suf[i]); | ||
76 | } | ||
77 | g_string_append(s, "</union>"); | ||
78 | } | ||
79 | @@ -XXX,XX +XXX,XX @@ int arm_gen_dynamic_svereg_xml(CPUState *cs, int orig_base_reg) | ||
80 | g_string_append_printf(s, "<feature name=\"org.gnu.gdb.aarch64.sve\">"); | ||
81 | |||
82 | /* Create the vector union type. */ | ||
83 | - output_vector_union_type(s, reg_width); | ||
84 | + output_vector_union_type(s, reg_width, "svev"); | ||
85 | |||
86 | /* Create the predicate vector type. */ | ||
87 | g_string_append_printf(s, | ||
88 | -- | 65 | -- |
89 | 2.34.1 | 66 | 2.34.1 |
90 | 67 | ||
91 | 68 | diff view generated by jsdifflib |
1 | From: qianfan Zhao <qianfanguijin@163.com> | 1 | From: Jean-Christophe Dubois <jcd@tribudubois.net> |
---|---|---|---|
2 | 2 | ||
3 | TWI_CNTR_INT_FLAG is W1C(write 1 to clear and write 0 has non-effect) | 3 | * Add Addr and size definition for all i.MX7 devices in i.MX7 header file. |
4 | register on SUN6i based SoCs, we should lower interrupt when the guest | 4 | * Use those newly defined named constants whenever possible. |
5 | set this bit. | 5 | * Standardize the way we init a familly of unimplemented devices |
6 | - SAI | ||
7 | - PWM | ||
8 | - CAN | ||
9 | * Add/rework few comments | ||
6 | 10 | ||
7 | The linux kernel will hang in irq handler(mv64xxx_i2c_intr) if no | 11 | Signed-off-by: Jean-Christophe Dubois <jcd@tribudubois.net> |
8 | device connected on the i2c bus, next is the trace log: | 12 | Message-id: 59e195d33e4d486a8d131392acd46633c8c10ed7.1692964892.git.jcd@tribudubois.net |
9 | |||
10 | allwinner_i2c_write write CNTR(0x0c): 0xc4 A_ACK BUS_EN INT_EN | ||
11 | allwinner_i2c_write write CNTR(0x0c): 0xcc A_ACK INT_FLAG BUS_EN INT_EN | ||
12 | allwinner_i2c_read read CNTR(0x0c): 0xcc A_ACK INT_FLAG BUS_EN INT_EN | ||
13 | allwinner_i2c_read read STAT(0x10): 0x20 STAT_M_ADDR_WR_NACK | ||
14 | allwinner_i2c_write write CNTR(0x0c): 0x54 A_ACK M_STP BUS_EN | ||
15 | allwinner_i2c_write write CNTR(0x0c): 0x4c A_ACK INT_FLAG BUS_EN | ||
16 | allwinner_i2c_read read CNTR(0x0c): 0x4c A_ACK INT_FLAG BUS_EN | ||
17 | allwinner_i2c_read read STAT(0x10): 0xf8 STAT_IDLE | ||
18 | allwinner_i2c_write write CNTR(0x0c): 0x54 A_ACK M_STP BUS_EN | ||
19 | allwinner_i2c_write write CNTR(0x0c): 0x4c A_ACK INT_FLAG BUS_EN | ||
20 | allwinner_i2c_read read CNTR(0x0c): 0x4c A_ACK INT_FLAG BUS_EN | ||
21 | allwinner_i2c_read read STAT(0x10): 0xf8 STAT_IDLE | ||
22 | ... | ||
23 | |||
24 | Fix it. | ||
25 | |||
26 | Signed-off-by: qianfan Zhao <qianfanguijin@163.com> | ||
27 | Reviewed-by: Strahinja Jankovic <strahinja.p.jankovic@gmail.com> | ||
28 | Tested-by: Strahinja Jankovic <strahinja.p.jankovic@gmail.com> | ||
29 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | 13 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> |
30 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 14 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
31 | --- | 15 | --- |
32 | include/hw/i2c/allwinner-i2c.h | 6 ++++++ | 16 | include/hw/arm/fsl-imx7.h | 330 ++++++++++++++++++++++++++++---------- |
33 | hw/i2c/allwinner-i2c.c | 26 ++++++++++++++++++++++++-- | 17 | hw/arm/fsl-imx7.c | 130 ++++++++++----- |
34 | 2 files changed, 30 insertions(+), 2 deletions(-) | 18 | 2 files changed, 335 insertions(+), 125 deletions(-) |
35 | 19 | ||
36 | diff --git a/include/hw/i2c/allwinner-i2c.h b/include/hw/i2c/allwinner-i2c.h | 20 | diff --git a/include/hw/arm/fsl-imx7.h b/include/hw/arm/fsl-imx7.h |
37 | index XXXXXXX..XXXXXXX 100644 | 21 | index XXXXXXX..XXXXXXX 100644 |
38 | --- a/include/hw/i2c/allwinner-i2c.h | 22 | --- a/include/hw/arm/fsl-imx7.h |
39 | +++ b/include/hw/i2c/allwinner-i2c.h | 23 | +++ b/include/hw/arm/fsl-imx7.h |
40 | @@ -XXX,XX +XXX,XX @@ | 24 | @@ -XXX,XX +XXX,XX @@ |
25 | #include "hw/misc/imx7_ccm.h" | ||
26 | #include "hw/misc/imx7_snvs.h" | ||
27 | #include "hw/misc/imx7_gpr.h" | ||
28 | -#include "hw/misc/imx6_src.h" | ||
29 | #include "hw/watchdog/wdt_imx2.h" | ||
30 | #include "hw/gpio/imx_gpio.h" | ||
31 | #include "hw/char/imx_serial.h" | ||
32 | @@ -XXX,XX +XXX,XX @@ | ||
33 | #include "hw/usb/chipidea.h" | ||
34 | #include "cpu.h" | ||
41 | #include "qom/object.h" | 35 | #include "qom/object.h" |
42 | 36 | +#include "qemu/units.h" | |
43 | #define TYPE_AW_I2C "allwinner.i2c" | 37 | |
44 | + | 38 | #define TYPE_FSL_IMX7 "fsl-imx7" |
45 | +/** Allwinner I2C sun6i family and newer (A31, H2+, H3, etc) */ | 39 | OBJECT_DECLARE_SIMPLE_TYPE(FslIMX7State, FSL_IMX7) |
46 | +#define TYPE_AW_I2C_SUN6I TYPE_AW_I2C "-sun6i" | 40 | @@ -XXX,XX +XXX,XX @@ enum FslIMX7Configuration { |
47 | + | 41 | FSL_IMX7_NUM_ECSPIS = 4, |
48 | OBJECT_DECLARE_SIMPLE_TYPE(AWI2CState, AW_I2C) | 42 | FSL_IMX7_NUM_USBS = 3, |
49 | 43 | FSL_IMX7_NUM_ADCS = 2, | |
50 | #define AW_I2C_MEM_SIZE 0x24 | 44 | + FSL_IMX7_NUM_SAIS = 3, |
51 | @@ -XXX,XX +XXX,XX @@ struct AWI2CState { | 45 | + FSL_IMX7_NUM_CANS = 2, |
52 | uint8_t srst; | 46 | + FSL_IMX7_NUM_PWMS = 4, |
53 | uint8_t efr; | ||
54 | uint8_t lcr; | ||
55 | + | ||
56 | + bool irq_clear_inverted; | ||
57 | }; | 47 | }; |
58 | 48 | ||
59 | #endif /* ALLWINNER_I2C_H */ | 49 | struct FslIMX7State { |
60 | diff --git a/hw/i2c/allwinner-i2c.c b/hw/i2c/allwinner-i2c.c | 50 | @@ -XXX,XX +XXX,XX @@ struct FslIMX7State { |
51 | |||
52 | enum FslIMX7MemoryMap { | ||
53 | FSL_IMX7_MMDC_ADDR = 0x80000000, | ||
54 | - FSL_IMX7_MMDC_SIZE = 2 * 1024 * 1024 * 1024UL, | ||
55 | + FSL_IMX7_MMDC_SIZE = (2 * GiB), | ||
56 | |||
57 | - FSL_IMX7_GPIO1_ADDR = 0x30200000, | ||
58 | - FSL_IMX7_GPIO2_ADDR = 0x30210000, | ||
59 | - FSL_IMX7_GPIO3_ADDR = 0x30220000, | ||
60 | - FSL_IMX7_GPIO4_ADDR = 0x30230000, | ||
61 | - FSL_IMX7_GPIO5_ADDR = 0x30240000, | ||
62 | - FSL_IMX7_GPIO6_ADDR = 0x30250000, | ||
63 | - FSL_IMX7_GPIO7_ADDR = 0x30260000, | ||
64 | + FSL_IMX7_QSPI1_MEM_ADDR = 0x60000000, | ||
65 | + FSL_IMX7_QSPI1_MEM_SIZE = (256 * MiB), | ||
66 | |||
67 | - FSL_IMX7_IOMUXC_LPSR_GPR_ADDR = 0x30270000, | ||
68 | + FSL_IMX7_PCIE1_MEM_ADDR = 0x40000000, | ||
69 | + FSL_IMX7_PCIE1_MEM_SIZE = (256 * MiB), | ||
70 | |||
71 | - FSL_IMX7_WDOG1_ADDR = 0x30280000, | ||
72 | - FSL_IMX7_WDOG2_ADDR = 0x30290000, | ||
73 | - FSL_IMX7_WDOG3_ADDR = 0x302A0000, | ||
74 | - FSL_IMX7_WDOG4_ADDR = 0x302B0000, | ||
75 | + FSL_IMX7_QSPI1_RX_BUF_ADDR = 0x34000000, | ||
76 | + FSL_IMX7_QSPI1_RX_BUF_SIZE = (32 * MiB), | ||
77 | |||
78 | - FSL_IMX7_IOMUXC_LPSR_ADDR = 0x302C0000, | ||
79 | + /* PCIe Peripherals */ | ||
80 | + FSL_IMX7_PCIE_REG_ADDR = 0x33800000, | ||
81 | |||
82 | - FSL_IMX7_GPT1_ADDR = 0x302D0000, | ||
83 | - FSL_IMX7_GPT2_ADDR = 0x302E0000, | ||
84 | - FSL_IMX7_GPT3_ADDR = 0x302F0000, | ||
85 | - FSL_IMX7_GPT4_ADDR = 0x30300000, | ||
86 | + /* MMAP Peripherals */ | ||
87 | + FSL_IMX7_DMA_APBH_ADDR = 0x33000000, | ||
88 | + FSL_IMX7_DMA_APBH_SIZE = 0x8000, | ||
89 | |||
90 | - FSL_IMX7_IOMUXC_ADDR = 0x30330000, | ||
91 | - FSL_IMX7_IOMUXC_GPR_ADDR = 0x30340000, | ||
92 | - FSL_IMX7_IOMUXCn_SIZE = 0x1000, | ||
93 | + /* GPV configuration */ | ||
94 | + FSL_IMX7_GPV6_ADDR = 0x32600000, | ||
95 | + FSL_IMX7_GPV5_ADDR = 0x32500000, | ||
96 | + FSL_IMX7_GPV4_ADDR = 0x32400000, | ||
97 | + FSL_IMX7_GPV3_ADDR = 0x32300000, | ||
98 | + FSL_IMX7_GPV2_ADDR = 0x32200000, | ||
99 | + FSL_IMX7_GPV1_ADDR = 0x32100000, | ||
100 | + FSL_IMX7_GPV0_ADDR = 0x32000000, | ||
101 | + FSL_IMX7_GPVn_SIZE = (1 * MiB), | ||
102 | |||
103 | - FSL_IMX7_OCOTP_ADDR = 0x30350000, | ||
104 | - FSL_IMX7_OCOTP_SIZE = 0x10000, | ||
105 | + /* Arm Peripherals */ | ||
106 | + FSL_IMX7_A7MPCORE_ADDR = 0x31000000, | ||
107 | |||
108 | - FSL_IMX7_ANALOG_ADDR = 0x30360000, | ||
109 | - FSL_IMX7_SNVS_ADDR = 0x30370000, | ||
110 | - FSL_IMX7_CCM_ADDR = 0x30380000, | ||
111 | + /* AIPS-3 Begin */ | ||
112 | |||
113 | - FSL_IMX7_SRC_ADDR = 0x30390000, | ||
114 | - FSL_IMX7_SRC_SIZE = 0x1000, | ||
115 | + FSL_IMX7_ENET2_ADDR = 0x30BF0000, | ||
116 | + FSL_IMX7_ENET1_ADDR = 0x30BE0000, | ||
117 | |||
118 | - FSL_IMX7_ADC1_ADDR = 0x30610000, | ||
119 | - FSL_IMX7_ADC2_ADDR = 0x30620000, | ||
120 | - FSL_IMX7_ADCn_SIZE = 0x1000, | ||
121 | + FSL_IMX7_SDMA_ADDR = 0x30BD0000, | ||
122 | + FSL_IMX7_SDMA_SIZE = (4 * KiB), | ||
123 | |||
124 | - FSL_IMX7_PWM1_ADDR = 0x30660000, | ||
125 | - FSL_IMX7_PWM2_ADDR = 0x30670000, | ||
126 | - FSL_IMX7_PWM3_ADDR = 0x30680000, | ||
127 | - FSL_IMX7_PWM4_ADDR = 0x30690000, | ||
128 | - FSL_IMX7_PWMn_SIZE = 0x10000, | ||
129 | + FSL_IMX7_EIM_ADDR = 0x30BC0000, | ||
130 | + FSL_IMX7_EIM_SIZE = (4 * KiB), | ||
131 | |||
132 | - FSL_IMX7_PCIE_PHY_ADDR = 0x306D0000, | ||
133 | - FSL_IMX7_PCIE_PHY_SIZE = 0x10000, | ||
134 | + FSL_IMX7_QSPI_ADDR = 0x30BB0000, | ||
135 | + FSL_IMX7_QSPI_SIZE = 0x8000, | ||
136 | |||
137 | - FSL_IMX7_GPC_ADDR = 0x303A0000, | ||
138 | + FSL_IMX7_SIM2_ADDR = 0x30BA0000, | ||
139 | + FSL_IMX7_SIM1_ADDR = 0x30B90000, | ||
140 | + FSL_IMX7_SIMn_SIZE = (4 * KiB), | ||
141 | + | ||
142 | + FSL_IMX7_USDHC3_ADDR = 0x30B60000, | ||
143 | + FSL_IMX7_USDHC2_ADDR = 0x30B50000, | ||
144 | + FSL_IMX7_USDHC1_ADDR = 0x30B40000, | ||
145 | + | ||
146 | + FSL_IMX7_USB3_ADDR = 0x30B30000, | ||
147 | + FSL_IMX7_USBMISC3_ADDR = 0x30B30200, | ||
148 | + FSL_IMX7_USB2_ADDR = 0x30B20000, | ||
149 | + FSL_IMX7_USBMISC2_ADDR = 0x30B20200, | ||
150 | + FSL_IMX7_USB1_ADDR = 0x30B10000, | ||
151 | + FSL_IMX7_USBMISC1_ADDR = 0x30B10200, | ||
152 | + FSL_IMX7_USBMISCn_SIZE = 0x200, | ||
153 | + | ||
154 | + FSL_IMX7_USB_PL301_ADDR = 0x30AD0000, | ||
155 | + FSL_IMX7_USB_PL301_SIZE = (64 * KiB), | ||
156 | + | ||
157 | + FSL_IMX7_SEMAPHORE_HS_ADDR = 0x30AC0000, | ||
158 | + FSL_IMX7_SEMAPHORE_HS_SIZE = (64 * KiB), | ||
159 | + | ||
160 | + FSL_IMX7_MUB_ADDR = 0x30AB0000, | ||
161 | + FSL_IMX7_MUA_ADDR = 0x30AA0000, | ||
162 | + FSL_IMX7_MUn_SIZE = (KiB), | ||
163 | + | ||
164 | + FSL_IMX7_UART7_ADDR = 0x30A90000, | ||
165 | + FSL_IMX7_UART6_ADDR = 0x30A80000, | ||
166 | + FSL_IMX7_UART5_ADDR = 0x30A70000, | ||
167 | + FSL_IMX7_UART4_ADDR = 0x30A60000, | ||
168 | + | ||
169 | + FSL_IMX7_I2C4_ADDR = 0x30A50000, | ||
170 | + FSL_IMX7_I2C3_ADDR = 0x30A40000, | ||
171 | + FSL_IMX7_I2C2_ADDR = 0x30A30000, | ||
172 | + FSL_IMX7_I2C1_ADDR = 0x30A20000, | ||
173 | + | ||
174 | + FSL_IMX7_CAN2_ADDR = 0x30A10000, | ||
175 | + FSL_IMX7_CAN1_ADDR = 0x30A00000, | ||
176 | + FSL_IMX7_CANn_SIZE = (4 * KiB), | ||
177 | + | ||
178 | + FSL_IMX7_AIPS3_CONF_ADDR = 0x309F0000, | ||
179 | + FSL_IMX7_AIPS3_CONF_SIZE = (64 * KiB), | ||
180 | |||
181 | FSL_IMX7_CAAM_ADDR = 0x30900000, | ||
182 | - FSL_IMX7_CAAM_SIZE = 0x40000, | ||
183 | + FSL_IMX7_CAAM_SIZE = (256 * KiB), | ||
184 | |||
185 | - FSL_IMX7_CAN1_ADDR = 0x30A00000, | ||
186 | - FSL_IMX7_CAN2_ADDR = 0x30A10000, | ||
187 | - FSL_IMX7_CANn_SIZE = 0x10000, | ||
188 | + FSL_IMX7_SPBA_ADDR = 0x308F0000, | ||
189 | + FSL_IMX7_SPBA_SIZE = (4 * KiB), | ||
190 | |||
191 | - FSL_IMX7_I2C1_ADDR = 0x30A20000, | ||
192 | - FSL_IMX7_I2C2_ADDR = 0x30A30000, | ||
193 | - FSL_IMX7_I2C3_ADDR = 0x30A40000, | ||
194 | - FSL_IMX7_I2C4_ADDR = 0x30A50000, | ||
195 | + FSL_IMX7_SAI3_ADDR = 0x308C0000, | ||
196 | + FSL_IMX7_SAI2_ADDR = 0x308B0000, | ||
197 | + FSL_IMX7_SAI1_ADDR = 0x308A0000, | ||
198 | + FSL_IMX7_SAIn_SIZE = (4 * KiB), | ||
199 | |||
200 | - FSL_IMX7_ECSPI1_ADDR = 0x30820000, | ||
201 | - FSL_IMX7_ECSPI2_ADDR = 0x30830000, | ||
202 | - FSL_IMX7_ECSPI3_ADDR = 0x30840000, | ||
203 | - FSL_IMX7_ECSPI4_ADDR = 0x30630000, | ||
204 | - | ||
205 | - FSL_IMX7_LCDIF_ADDR = 0x30730000, | ||
206 | - FSL_IMX7_LCDIF_SIZE = 0x1000, | ||
207 | - | ||
208 | - FSL_IMX7_UART1_ADDR = 0x30860000, | ||
209 | + FSL_IMX7_UART3_ADDR = 0x30880000, | ||
210 | /* | ||
211 | * Some versions of the reference manual claim that UART2 is @ | ||
212 | * 0x30870000, but experiments with HW + DT files in upstream | ||
213 | @@ -XXX,XX +XXX,XX @@ enum FslIMX7MemoryMap { | ||
214 | * actually located @ 0x30890000 | ||
215 | */ | ||
216 | FSL_IMX7_UART2_ADDR = 0x30890000, | ||
217 | - FSL_IMX7_UART3_ADDR = 0x30880000, | ||
218 | - FSL_IMX7_UART4_ADDR = 0x30A60000, | ||
219 | - FSL_IMX7_UART5_ADDR = 0x30A70000, | ||
220 | - FSL_IMX7_UART6_ADDR = 0x30A80000, | ||
221 | - FSL_IMX7_UART7_ADDR = 0x30A90000, | ||
222 | + FSL_IMX7_UART1_ADDR = 0x30860000, | ||
223 | |||
224 | - FSL_IMX7_SAI1_ADDR = 0x308A0000, | ||
225 | - FSL_IMX7_SAI2_ADDR = 0x308B0000, | ||
226 | - FSL_IMX7_SAI3_ADDR = 0x308C0000, | ||
227 | - FSL_IMX7_SAIn_SIZE = 0x10000, | ||
228 | + FSL_IMX7_ECSPI3_ADDR = 0x30840000, | ||
229 | + FSL_IMX7_ECSPI2_ADDR = 0x30830000, | ||
230 | + FSL_IMX7_ECSPI1_ADDR = 0x30820000, | ||
231 | + FSL_IMX7_ECSPIn_SIZE = (4 * KiB), | ||
232 | |||
233 | - FSL_IMX7_ENET1_ADDR = 0x30BE0000, | ||
234 | - FSL_IMX7_ENET2_ADDR = 0x30BF0000, | ||
235 | + /* AIPS-3 End */ | ||
236 | |||
237 | - FSL_IMX7_USB1_ADDR = 0x30B10000, | ||
238 | - FSL_IMX7_USBMISC1_ADDR = 0x30B10200, | ||
239 | - FSL_IMX7_USB2_ADDR = 0x30B20000, | ||
240 | - FSL_IMX7_USBMISC2_ADDR = 0x30B20200, | ||
241 | - FSL_IMX7_USB3_ADDR = 0x30B30000, | ||
242 | - FSL_IMX7_USBMISC3_ADDR = 0x30B30200, | ||
243 | - FSL_IMX7_USBMISCn_SIZE = 0x200, | ||
244 | + /* AIPS-2 Begin */ | ||
245 | |||
246 | - FSL_IMX7_USDHC1_ADDR = 0x30B40000, | ||
247 | - FSL_IMX7_USDHC2_ADDR = 0x30B50000, | ||
248 | - FSL_IMX7_USDHC3_ADDR = 0x30B60000, | ||
249 | + FSL_IMX7_AXI_DEBUG_MON_ADDR = 0x307E0000, | ||
250 | + FSL_IMX7_AXI_DEBUG_MON_SIZE = (64 * KiB), | ||
251 | |||
252 | - FSL_IMX7_SDMA_ADDR = 0x30BD0000, | ||
253 | - FSL_IMX7_SDMA_SIZE = 0x1000, | ||
254 | + FSL_IMX7_PERFMON2_ADDR = 0x307D0000, | ||
255 | + FSL_IMX7_PERFMON1_ADDR = 0x307C0000, | ||
256 | + FSL_IMX7_PERFMONn_SIZE = (64 * KiB), | ||
257 | + | ||
258 | + FSL_IMX7_DDRC_ADDR = 0x307A0000, | ||
259 | + FSL_IMX7_DDRC_SIZE = (4 * KiB), | ||
260 | + | ||
261 | + FSL_IMX7_DDRC_PHY_ADDR = 0x30790000, | ||
262 | + FSL_IMX7_DDRC_PHY_SIZE = (4 * KiB), | ||
263 | + | ||
264 | + FSL_IMX7_TZASC_ADDR = 0x30780000, | ||
265 | + FSL_IMX7_TZASC_SIZE = (64 * KiB), | ||
266 | + | ||
267 | + FSL_IMX7_MIPI_DSI_ADDR = 0x30760000, | ||
268 | + FSL_IMX7_MIPI_DSI_SIZE = (4 * KiB), | ||
269 | + | ||
270 | + FSL_IMX7_MIPI_CSI_ADDR = 0x30750000, | ||
271 | + FSL_IMX7_MIPI_CSI_SIZE = 0x4000, | ||
272 | + | ||
273 | + FSL_IMX7_LCDIF_ADDR = 0x30730000, | ||
274 | + FSL_IMX7_LCDIF_SIZE = 0x8000, | ||
275 | + | ||
276 | + FSL_IMX7_CSI_ADDR = 0x30710000, | ||
277 | + FSL_IMX7_CSI_SIZE = (4 * KiB), | ||
278 | + | ||
279 | + FSL_IMX7_PXP_ADDR = 0x30700000, | ||
280 | + FSL_IMX7_PXP_SIZE = 0x4000, | ||
281 | + | ||
282 | + FSL_IMX7_EPDC_ADDR = 0x306F0000, | ||
283 | + FSL_IMX7_EPDC_SIZE = (4 * KiB), | ||
284 | + | ||
285 | + FSL_IMX7_PCIE_PHY_ADDR = 0x306D0000, | ||
286 | + FSL_IMX7_PCIE_PHY_SIZE = (4 * KiB), | ||
287 | + | ||
288 | + FSL_IMX7_SYSCNT_CTRL_ADDR = 0x306C0000, | ||
289 | + FSL_IMX7_SYSCNT_CMP_ADDR = 0x306B0000, | ||
290 | + FSL_IMX7_SYSCNT_RD_ADDR = 0x306A0000, | ||
291 | + | ||
292 | + FSL_IMX7_PWM4_ADDR = 0x30690000, | ||
293 | + FSL_IMX7_PWM3_ADDR = 0x30680000, | ||
294 | + FSL_IMX7_PWM2_ADDR = 0x30670000, | ||
295 | + FSL_IMX7_PWM1_ADDR = 0x30660000, | ||
296 | + FSL_IMX7_PWMn_SIZE = (4 * KiB), | ||
297 | + | ||
298 | + FSL_IMX7_FlEXTIMER2_ADDR = 0x30650000, | ||
299 | + FSL_IMX7_FlEXTIMER1_ADDR = 0x30640000, | ||
300 | + FSL_IMX7_FLEXTIMERn_SIZE = (4 * KiB), | ||
301 | + | ||
302 | + FSL_IMX7_ECSPI4_ADDR = 0x30630000, | ||
303 | + | ||
304 | + FSL_IMX7_ADC2_ADDR = 0x30620000, | ||
305 | + FSL_IMX7_ADC1_ADDR = 0x30610000, | ||
306 | + FSL_IMX7_ADCn_SIZE = (4 * KiB), | ||
307 | + | ||
308 | + FSL_IMX7_AIPS2_CONF_ADDR = 0x305F0000, | ||
309 | + FSL_IMX7_AIPS2_CONF_SIZE = (64 * KiB), | ||
310 | + | ||
311 | + /* AIPS-2 End */ | ||
312 | + | ||
313 | + /* AIPS-1 Begin */ | ||
314 | + | ||
315 | + FSL_IMX7_CSU_ADDR = 0x303E0000, | ||
316 | + FSL_IMX7_CSU_SIZE = (64 * KiB), | ||
317 | + | ||
318 | + FSL_IMX7_RDC_ADDR = 0x303D0000, | ||
319 | + FSL_IMX7_RDC_SIZE = (4 * KiB), | ||
320 | + | ||
321 | + FSL_IMX7_SEMAPHORE2_ADDR = 0x303C0000, | ||
322 | + FSL_IMX7_SEMAPHORE1_ADDR = 0x303B0000, | ||
323 | + FSL_IMX7_SEMAPHOREn_SIZE = (4 * KiB), | ||
324 | + | ||
325 | + FSL_IMX7_GPC_ADDR = 0x303A0000, | ||
326 | + | ||
327 | + FSL_IMX7_SRC_ADDR = 0x30390000, | ||
328 | + FSL_IMX7_SRC_SIZE = (4 * KiB), | ||
329 | + | ||
330 | + FSL_IMX7_CCM_ADDR = 0x30380000, | ||
331 | + | ||
332 | + FSL_IMX7_SNVS_HP_ADDR = 0x30370000, | ||
333 | + | ||
334 | + FSL_IMX7_ANALOG_ADDR = 0x30360000, | ||
335 | + | ||
336 | + FSL_IMX7_OCOTP_ADDR = 0x30350000, | ||
337 | + FSL_IMX7_OCOTP_SIZE = 0x10000, | ||
338 | + | ||
339 | + FSL_IMX7_IOMUXC_GPR_ADDR = 0x30340000, | ||
340 | + FSL_IMX7_IOMUXC_GPR_SIZE = (4 * KiB), | ||
341 | + | ||
342 | + FSL_IMX7_IOMUXC_ADDR = 0x30330000, | ||
343 | + FSL_IMX7_IOMUXC_SIZE = (4 * KiB), | ||
344 | + | ||
345 | + FSL_IMX7_KPP_ADDR = 0x30320000, | ||
346 | + FSL_IMX7_KPP_SIZE = (4 * KiB), | ||
347 | + | ||
348 | + FSL_IMX7_ROMCP_ADDR = 0x30310000, | ||
349 | + FSL_IMX7_ROMCP_SIZE = (4 * KiB), | ||
350 | + | ||
351 | + FSL_IMX7_GPT4_ADDR = 0x30300000, | ||
352 | + FSL_IMX7_GPT3_ADDR = 0x302F0000, | ||
353 | + FSL_IMX7_GPT2_ADDR = 0x302E0000, | ||
354 | + FSL_IMX7_GPT1_ADDR = 0x302D0000, | ||
355 | + | ||
356 | + FSL_IMX7_IOMUXC_LPSR_ADDR = 0x302C0000, | ||
357 | + FSL_IMX7_IOMUXC_LPSR_SIZE = (4 * KiB), | ||
358 | + | ||
359 | + FSL_IMX7_WDOG4_ADDR = 0x302B0000, | ||
360 | + FSL_IMX7_WDOG3_ADDR = 0x302A0000, | ||
361 | + FSL_IMX7_WDOG2_ADDR = 0x30290000, | ||
362 | + FSL_IMX7_WDOG1_ADDR = 0x30280000, | ||
363 | + | ||
364 | + FSL_IMX7_IOMUXC_LPSR_GPR_ADDR = 0x30270000, | ||
365 | + | ||
366 | + FSL_IMX7_GPIO7_ADDR = 0x30260000, | ||
367 | + FSL_IMX7_GPIO6_ADDR = 0x30250000, | ||
368 | + FSL_IMX7_GPIO5_ADDR = 0x30240000, | ||
369 | + FSL_IMX7_GPIO4_ADDR = 0x30230000, | ||
370 | + FSL_IMX7_GPIO3_ADDR = 0x30220000, | ||
371 | + FSL_IMX7_GPIO2_ADDR = 0x30210000, | ||
372 | + FSL_IMX7_GPIO1_ADDR = 0x30200000, | ||
373 | + | ||
374 | + FSL_IMX7_AIPS1_CONF_ADDR = 0x301F0000, | ||
375 | + FSL_IMX7_AIPS1_CONF_SIZE = (64 * KiB), | ||
376 | |||
377 | - FSL_IMX7_A7MPCORE_ADDR = 0x31000000, | ||
378 | FSL_IMX7_A7MPCORE_DAP_ADDR = 0x30000000, | ||
379 | + FSL_IMX7_A7MPCORE_DAP_SIZE = (1 * MiB), | ||
380 | |||
381 | - FSL_IMX7_PCIE_REG_ADDR = 0x33800000, | ||
382 | - FSL_IMX7_PCIE_REG_SIZE = 16 * 1024, | ||
383 | + /* AIPS-1 End */ | ||
384 | |||
385 | - FSL_IMX7_GPR_ADDR = 0x30340000, | ||
386 | + FSL_IMX7_EIM_CS0_ADDR = 0x28000000, | ||
387 | + FSL_IMX7_EIM_CS0_SIZE = (128 * MiB), | ||
388 | |||
389 | - FSL_IMX7_DMA_APBH_ADDR = 0x33000000, | ||
390 | - FSL_IMX7_DMA_APBH_SIZE = 0x2000, | ||
391 | + FSL_IMX7_OCRAM_PXP_ADDR = 0x00940000, | ||
392 | + FSL_IMX7_OCRAM_PXP_SIZE = (32 * KiB), | ||
393 | + | ||
394 | + FSL_IMX7_OCRAM_EPDC_ADDR = 0x00920000, | ||
395 | + FSL_IMX7_OCRAM_EPDC_SIZE = (128 * KiB), | ||
396 | + | ||
397 | + FSL_IMX7_OCRAM_MEM_ADDR = 0x00900000, | ||
398 | + FSL_IMX7_OCRAM_MEM_SIZE = (128 * KiB), | ||
399 | + | ||
400 | + FSL_IMX7_TCMU_ADDR = 0x00800000, | ||
401 | + FSL_IMX7_TCMU_SIZE = (32 * KiB), | ||
402 | + | ||
403 | + FSL_IMX7_TCML_ADDR = 0x007F8000, | ||
404 | + FSL_IMX7_TCML_SIZE = (32 * KiB), | ||
405 | + | ||
406 | + FSL_IMX7_OCRAM_S_ADDR = 0x00180000, | ||
407 | + FSL_IMX7_OCRAM_S_SIZE = (32 * KiB), | ||
408 | + | ||
409 | + FSL_IMX7_CAAM_MEM_ADDR = 0x00100000, | ||
410 | + FSL_IMX7_CAAM_MEM_SIZE = (32 * KiB), | ||
411 | + | ||
412 | + FSL_IMX7_ROM_ADDR = 0x00000000, | ||
413 | + FSL_IMX7_ROM_SIZE = (96 * KiB), | ||
414 | }; | ||
415 | |||
416 | enum FslIMX7IRQs { | ||
417 | diff --git a/hw/arm/fsl-imx7.c b/hw/arm/fsl-imx7.c | ||
61 | index XXXXXXX..XXXXXXX 100644 | 418 | index XXXXXXX..XXXXXXX 100644 |
62 | --- a/hw/i2c/allwinner-i2c.c | 419 | --- a/hw/arm/fsl-imx7.c |
63 | +++ b/hw/i2c/allwinner-i2c.c | 420 | +++ b/hw/arm/fsl-imx7.c |
64 | @@ -XXX,XX +XXX,XX @@ static void allwinner_i2c_write(void *opaque, hwaddr offset, | 421 | @@ -XXX,XX +XXX,XX @@ static void fsl_imx7_init(Object *obj) |
65 | s->stat = STAT_FROM_STA(STAT_IDLE); | 422 | char name[NAME_SIZE]; |
66 | s->cntr &= ~TWI_CNTR_M_STP; | 423 | int i; |
67 | } | 424 | |
68 | - if ((s->cntr & TWI_CNTR_INT_FLAG) == 0) { | 425 | + /* |
69 | - /* Interrupt flag cleared */ | 426 | + * CPUs |
70 | + | 427 | + */ |
71 | + if (!s->irq_clear_inverted && !(s->cntr & TWI_CNTR_INT_FLAG)) { | 428 | for (i = 0; i < MIN(ms->smp.cpus, FSL_IMX7_NUM_CPUS); i++) { |
72 | + /* Write 0 to clear this flag */ | 429 | snprintf(name, NAME_SIZE, "cpu%d", i); |
73 | + qemu_irq_lower(s->irq); | 430 | object_initialize_child(obj, name, &s->cpu[i], |
74 | + } else if (s->irq_clear_inverted && (s->cntr & TWI_CNTR_INT_FLAG)) { | 431 | @@ -XXX,XX +XXX,XX @@ static void fsl_imx7_init(Object *obj) |
75 | + /* Write 1 to clear this flag */ | 432 | TYPE_A15MPCORE_PRIV); |
76 | + s->cntr &= ~TWI_CNTR_INT_FLAG; | 433 | |
77 | qemu_irq_lower(s->irq); | 434 | /* |
78 | } | 435 | - * GPIOs 1 to 7 |
79 | + | 436 | + * GPIOs |
80 | if ((s->cntr & TWI_CNTR_A_ACK) == 0) { | 437 | */ |
81 | if (STAT_TO_STA(s->stat) == STAT_M_DATA_RX_ACK) { | 438 | for (i = 0; i < FSL_IMX7_NUM_GPIOS; i++) { |
82 | s->stat = STAT_FROM_STA(STAT_M_DATA_RX_NACK); | 439 | snprintf(name, NAME_SIZE, "gpio%d", i); |
83 | @@ -XXX,XX +XXX,XX @@ static const TypeInfo allwinner_i2c_type_info = { | 440 | @@ -XXX,XX +XXX,XX @@ static void fsl_imx7_init(Object *obj) |
84 | .class_init = allwinner_i2c_class_init, | 441 | } |
85 | }; | 442 | |
86 | 443 | /* | |
87 | +static void allwinner_i2c_sun6i_init(Object *obj) | 444 | - * GPT1, 2, 3, 4 |
88 | +{ | 445 | + * GPTs |
89 | + AWI2CState *s = AW_I2C(obj); | 446 | */ |
90 | + | 447 | for (i = 0; i < FSL_IMX7_NUM_GPTS; i++) { |
91 | + s->irq_clear_inverted = true; | 448 | snprintf(name, NAME_SIZE, "gpt%d", i); |
92 | +} | 449 | @@ -XXX,XX +XXX,XX @@ static void fsl_imx7_init(Object *obj) |
93 | + | 450 | */ |
94 | +static const TypeInfo allwinner_i2c_sun6i_type_info = { | 451 | object_initialize_child(obj, "gpcv2", &s->gpcv2, TYPE_IMX_GPCV2); |
95 | + .name = TYPE_AW_I2C_SUN6I, | 452 | |
96 | + .parent = TYPE_SYS_BUS_DEVICE, | 453 | + /* |
97 | + .instance_size = sizeof(AWI2CState), | 454 | + * ECSPIs |
98 | + .instance_init = allwinner_i2c_sun6i_init, | 455 | + */ |
99 | + .class_init = allwinner_i2c_class_init, | 456 | for (i = 0; i < FSL_IMX7_NUM_ECSPIS; i++) { |
100 | +}; | 457 | snprintf(name, NAME_SIZE, "spi%d", i + 1); |
101 | + | 458 | object_initialize_child(obj, name, &s->spi[i], TYPE_IMX_SPI); |
102 | static void allwinner_i2c_register_types(void) | 459 | } |
103 | { | 460 | |
104 | type_register_static(&allwinner_i2c_type_info); | 461 | - |
105 | + type_register_static(&allwinner_i2c_sun6i_type_info); | 462 | + /* |
463 | + * I2Cs | ||
464 | + */ | ||
465 | for (i = 0; i < FSL_IMX7_NUM_I2CS; i++) { | ||
466 | snprintf(name, NAME_SIZE, "i2c%d", i + 1); | ||
467 | object_initialize_child(obj, name, &s->i2c[i], TYPE_IMX_I2C); | ||
468 | } | ||
469 | |||
470 | /* | ||
471 | - * UART | ||
472 | + * UARTs | ||
473 | */ | ||
474 | for (i = 0; i < FSL_IMX7_NUM_UARTS; i++) { | ||
475 | snprintf(name, NAME_SIZE, "uart%d", i); | ||
476 | @@ -XXX,XX +XXX,XX @@ static void fsl_imx7_init(Object *obj) | ||
477 | } | ||
478 | |||
479 | /* | ||
480 | - * Ethernet | ||
481 | + * Ethernets | ||
482 | */ | ||
483 | for (i = 0; i < FSL_IMX7_NUM_ETHS; i++) { | ||
484 | snprintf(name, NAME_SIZE, "eth%d", i); | ||
485 | @@ -XXX,XX +XXX,XX @@ static void fsl_imx7_init(Object *obj) | ||
486 | } | ||
487 | |||
488 | /* | ||
489 | - * SDHCI | ||
490 | + * SDHCIs | ||
491 | */ | ||
492 | for (i = 0; i < FSL_IMX7_NUM_USDHCS; i++) { | ||
493 | snprintf(name, NAME_SIZE, "usdhc%d", i); | ||
494 | @@ -XXX,XX +XXX,XX @@ static void fsl_imx7_init(Object *obj) | ||
495 | object_initialize_child(obj, "snvs", &s->snvs, TYPE_IMX7_SNVS); | ||
496 | |||
497 | /* | ||
498 | - * Watchdog | ||
499 | + * Watchdogs | ||
500 | */ | ||
501 | for (i = 0; i < FSL_IMX7_NUM_WDTS; i++) { | ||
502 | snprintf(name, NAME_SIZE, "wdt%d", i); | ||
503 | @@ -XXX,XX +XXX,XX @@ static void fsl_imx7_init(Object *obj) | ||
504 | */ | ||
505 | object_initialize_child(obj, "gpr", &s->gpr, TYPE_IMX7_GPR); | ||
506 | |||
507 | + /* | ||
508 | + * PCIE | ||
509 | + */ | ||
510 | object_initialize_child(obj, "pcie", &s->pcie, TYPE_DESIGNWARE_PCIE_HOST); | ||
511 | |||
512 | + /* | ||
513 | + * USBs | ||
514 | + */ | ||
515 | for (i = 0; i < FSL_IMX7_NUM_USBS; i++) { | ||
516 | snprintf(name, NAME_SIZE, "usb%d", i); | ||
517 | object_initialize_child(obj, name, &s->usb[i], TYPE_CHIPIDEA); | ||
518 | @@ -XXX,XX +XXX,XX @@ static void fsl_imx7_realize(DeviceState *dev, Error **errp) | ||
519 | return; | ||
520 | } | ||
521 | |||
522 | + /* | ||
523 | + * CPUs | ||
524 | + */ | ||
525 | for (i = 0; i < smp_cpus; i++) { | ||
526 | o = OBJECT(&s->cpu[i]); | ||
527 | |||
528 | @@ -XXX,XX +XXX,XX @@ static void fsl_imx7_realize(DeviceState *dev, Error **errp) | ||
529 | * A7MPCORE DAP | ||
530 | */ | ||
531 | create_unimplemented_device("a7mpcore-dap", FSL_IMX7_A7MPCORE_DAP_ADDR, | ||
532 | - 0x100000); | ||
533 | + FSL_IMX7_A7MPCORE_DAP_SIZE); | ||
534 | |||
535 | /* | ||
536 | - * GPT1, 2, 3, 4 | ||
537 | + * GPTs | ||
538 | */ | ||
539 | for (i = 0; i < FSL_IMX7_NUM_GPTS; i++) { | ||
540 | static const hwaddr FSL_IMX7_GPTn_ADDR[FSL_IMX7_NUM_GPTS] = { | ||
541 | @@ -XXX,XX +XXX,XX @@ static void fsl_imx7_realize(DeviceState *dev, Error **errp) | ||
542 | FSL_IMX7_GPTn_IRQ[i])); | ||
543 | } | ||
544 | |||
545 | + /* | ||
546 | + * GPIOs | ||
547 | + */ | ||
548 | for (i = 0; i < FSL_IMX7_NUM_GPIOS; i++) { | ||
549 | static const hwaddr FSL_IMX7_GPIOn_ADDR[FSL_IMX7_NUM_GPIOS] = { | ||
550 | FSL_IMX7_GPIO1_ADDR, | ||
551 | @@ -XXX,XX +XXX,XX @@ static void fsl_imx7_realize(DeviceState *dev, Error **errp) | ||
552 | /* | ||
553 | * IOMUXC and IOMUXC_LPSR | ||
554 | */ | ||
555 | - for (i = 0; i < FSL_IMX7_NUM_IOMUXCS; i++) { | ||
556 | - static const hwaddr FSL_IMX7_IOMUXCn_ADDR[FSL_IMX7_NUM_IOMUXCS] = { | ||
557 | - FSL_IMX7_IOMUXC_ADDR, | ||
558 | - FSL_IMX7_IOMUXC_LPSR_ADDR, | ||
559 | - }; | ||
560 | - | ||
561 | - snprintf(name, NAME_SIZE, "iomuxc%d", i); | ||
562 | - create_unimplemented_device(name, FSL_IMX7_IOMUXCn_ADDR[i], | ||
563 | - FSL_IMX7_IOMUXCn_SIZE); | ||
564 | - } | ||
565 | + create_unimplemented_device("iomuxc", FSL_IMX7_IOMUXC_ADDR, | ||
566 | + FSL_IMX7_IOMUXC_SIZE); | ||
567 | + create_unimplemented_device("iomuxc_lspr", FSL_IMX7_IOMUXC_LPSR_ADDR, | ||
568 | + FSL_IMX7_IOMUXC_LPSR_SIZE); | ||
569 | |||
570 | /* | ||
571 | * CCM | ||
572 | @@ -XXX,XX +XXX,XX @@ static void fsl_imx7_realize(DeviceState *dev, Error **errp) | ||
573 | sysbus_realize(SYS_BUS_DEVICE(&s->gpcv2), &error_abort); | ||
574 | sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpcv2), 0, FSL_IMX7_GPC_ADDR); | ||
575 | |||
576 | - /* Initialize all ECSPI */ | ||
577 | + /* | ||
578 | + * ECSPIs | ||
579 | + */ | ||
580 | for (i = 0; i < FSL_IMX7_NUM_ECSPIS; i++) { | ||
581 | static const hwaddr FSL_IMX7_SPIn_ADDR[FSL_IMX7_NUM_ECSPIS] = { | ||
582 | FSL_IMX7_ECSPI1_ADDR, | ||
583 | @@ -XXX,XX +XXX,XX @@ static void fsl_imx7_realize(DeviceState *dev, Error **errp) | ||
584 | FSL_IMX7_SPIn_IRQ[i])); | ||
585 | } | ||
586 | |||
587 | + /* | ||
588 | + * I2Cs | ||
589 | + */ | ||
590 | for (i = 0; i < FSL_IMX7_NUM_I2CS; i++) { | ||
591 | static const hwaddr FSL_IMX7_I2Cn_ADDR[FSL_IMX7_NUM_I2CS] = { | ||
592 | FSL_IMX7_I2C1_ADDR, | ||
593 | @@ -XXX,XX +XXX,XX @@ static void fsl_imx7_realize(DeviceState *dev, Error **errp) | ||
594 | } | ||
595 | |||
596 | /* | ||
597 | - * UART | ||
598 | + * UARTs | ||
599 | */ | ||
600 | for (i = 0; i < FSL_IMX7_NUM_UARTS; i++) { | ||
601 | static const hwaddr FSL_IMX7_UARTn_ADDR[FSL_IMX7_NUM_UARTS] = { | ||
602 | @@ -XXX,XX +XXX,XX @@ static void fsl_imx7_realize(DeviceState *dev, Error **errp) | ||
603 | } | ||
604 | |||
605 | /* | ||
606 | - * Ethernet | ||
607 | + * Ethernets | ||
608 | * | ||
609 | * We must use two loops since phy_connected affects the other interface | ||
610 | * and we have to set all properties before calling sysbus_realize(). | ||
611 | @@ -XXX,XX +XXX,XX @@ static void fsl_imx7_realize(DeviceState *dev, Error **errp) | ||
612 | } | ||
613 | |||
614 | /* | ||
615 | - * USDHC | ||
616 | + * USDHCs | ||
617 | */ | ||
618 | for (i = 0; i < FSL_IMX7_NUM_USDHCS; i++) { | ||
619 | static const hwaddr FSL_IMX7_USDHCn_ADDR[FSL_IMX7_NUM_USDHCS] = { | ||
620 | @@ -XXX,XX +XXX,XX @@ static void fsl_imx7_realize(DeviceState *dev, Error **errp) | ||
621 | * SNVS | ||
622 | */ | ||
623 | sysbus_realize(SYS_BUS_DEVICE(&s->snvs), &error_abort); | ||
624 | - sysbus_mmio_map(SYS_BUS_DEVICE(&s->snvs), 0, FSL_IMX7_SNVS_ADDR); | ||
625 | + sysbus_mmio_map(SYS_BUS_DEVICE(&s->snvs), 0, FSL_IMX7_SNVS_HP_ADDR); | ||
626 | |||
627 | /* | ||
628 | * SRC | ||
629 | @@ -XXX,XX +XXX,XX @@ static void fsl_imx7_realize(DeviceState *dev, Error **errp) | ||
630 | create_unimplemented_device("src", FSL_IMX7_SRC_ADDR, FSL_IMX7_SRC_SIZE); | ||
631 | |||
632 | /* | ||
633 | - * Watchdog | ||
634 | + * Watchdogs | ||
635 | */ | ||
636 | for (i = 0; i < FSL_IMX7_NUM_WDTS; i++) { | ||
637 | static const hwaddr FSL_IMX7_WDOGn_ADDR[FSL_IMX7_NUM_WDTS] = { | ||
638 | @@ -XXX,XX +XXX,XX @@ static void fsl_imx7_realize(DeviceState *dev, Error **errp) | ||
639 | create_unimplemented_device("caam", FSL_IMX7_CAAM_ADDR, FSL_IMX7_CAAM_SIZE); | ||
640 | |||
641 | /* | ||
642 | - * PWM | ||
643 | + * PWMs | ||
644 | */ | ||
645 | - create_unimplemented_device("pwm1", FSL_IMX7_PWM1_ADDR, FSL_IMX7_PWMn_SIZE); | ||
646 | - create_unimplemented_device("pwm2", FSL_IMX7_PWM2_ADDR, FSL_IMX7_PWMn_SIZE); | ||
647 | - create_unimplemented_device("pwm3", FSL_IMX7_PWM3_ADDR, FSL_IMX7_PWMn_SIZE); | ||
648 | - create_unimplemented_device("pwm4", FSL_IMX7_PWM4_ADDR, FSL_IMX7_PWMn_SIZE); | ||
649 | + for (i = 0; i < FSL_IMX7_NUM_PWMS; i++) { | ||
650 | + static const hwaddr FSL_IMX7_PWMn_ADDR[FSL_IMX7_NUM_PWMS] = { | ||
651 | + FSL_IMX7_PWM1_ADDR, | ||
652 | + FSL_IMX7_PWM2_ADDR, | ||
653 | + FSL_IMX7_PWM3_ADDR, | ||
654 | + FSL_IMX7_PWM4_ADDR, | ||
655 | + }; | ||
656 | + | ||
657 | + snprintf(name, NAME_SIZE, "pwm%d", i); | ||
658 | + create_unimplemented_device(name, FSL_IMX7_PWMn_ADDR[i], | ||
659 | + FSL_IMX7_PWMn_SIZE); | ||
660 | + } | ||
661 | |||
662 | /* | ||
663 | - * CAN | ||
664 | + * CANs | ||
665 | */ | ||
666 | - create_unimplemented_device("can1", FSL_IMX7_CAN1_ADDR, FSL_IMX7_CANn_SIZE); | ||
667 | - create_unimplemented_device("can2", FSL_IMX7_CAN2_ADDR, FSL_IMX7_CANn_SIZE); | ||
668 | + for (i = 0; i < FSL_IMX7_NUM_CANS; i++) { | ||
669 | + static const hwaddr FSL_IMX7_CANn_ADDR[FSL_IMX7_NUM_CANS] = { | ||
670 | + FSL_IMX7_CAN1_ADDR, | ||
671 | + FSL_IMX7_CAN2_ADDR, | ||
672 | + }; | ||
673 | + | ||
674 | + snprintf(name, NAME_SIZE, "can%d", i); | ||
675 | + create_unimplemented_device(name, FSL_IMX7_CANn_ADDR[i], | ||
676 | + FSL_IMX7_CANn_SIZE); | ||
677 | + } | ||
678 | |||
679 | /* | ||
680 | - * SAI (Audio SSI (Synchronous Serial Interface)) | ||
681 | + * SAIs (Audio SSI (Synchronous Serial Interface)) | ||
682 | */ | ||
683 | - create_unimplemented_device("sai1", FSL_IMX7_SAI1_ADDR, FSL_IMX7_SAIn_SIZE); | ||
684 | - create_unimplemented_device("sai2", FSL_IMX7_SAI2_ADDR, FSL_IMX7_SAIn_SIZE); | ||
685 | - create_unimplemented_device("sai2", FSL_IMX7_SAI3_ADDR, FSL_IMX7_SAIn_SIZE); | ||
686 | + for (i = 0; i < FSL_IMX7_NUM_SAIS; i++) { | ||
687 | + static const hwaddr FSL_IMX7_SAIn_ADDR[FSL_IMX7_NUM_SAIS] = { | ||
688 | + FSL_IMX7_SAI1_ADDR, | ||
689 | + FSL_IMX7_SAI2_ADDR, | ||
690 | + FSL_IMX7_SAI3_ADDR, | ||
691 | + }; | ||
692 | + | ||
693 | + snprintf(name, NAME_SIZE, "sai%d", i); | ||
694 | + create_unimplemented_device(name, FSL_IMX7_SAIn_ADDR[i], | ||
695 | + FSL_IMX7_SAIn_SIZE); | ||
696 | + } | ||
697 | |||
698 | /* | ||
699 | * OCOTP | ||
700 | @@ -XXX,XX +XXX,XX @@ static void fsl_imx7_realize(DeviceState *dev, Error **errp) | ||
701 | create_unimplemented_device("ocotp", FSL_IMX7_OCOTP_ADDR, | ||
702 | FSL_IMX7_OCOTP_SIZE); | ||
703 | |||
704 | + /* | ||
705 | + * GPR | ||
706 | + */ | ||
707 | sysbus_realize(SYS_BUS_DEVICE(&s->gpr), &error_abort); | ||
708 | - sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpr), 0, FSL_IMX7_GPR_ADDR); | ||
709 | + sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpr), 0, FSL_IMX7_IOMUXC_GPR_ADDR); | ||
710 | |||
711 | + /* | ||
712 | + * PCIE | ||
713 | + */ | ||
714 | sysbus_realize(SYS_BUS_DEVICE(&s->pcie), &error_abort); | ||
715 | sysbus_mmio_map(SYS_BUS_DEVICE(&s->pcie), 0, FSL_IMX7_PCIE_REG_ADDR); | ||
716 | |||
717 | @@ -XXX,XX +XXX,XX @@ static void fsl_imx7_realize(DeviceState *dev, Error **errp) | ||
718 | irq = qdev_get_gpio_in(DEVICE(&s->a7mpcore), FSL_IMX7_PCI_INTD_IRQ); | ||
719 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->pcie), 3, irq); | ||
720 | |||
721 | - | ||
722 | + /* | ||
723 | + * USBs | ||
724 | + */ | ||
725 | for (i = 0; i < FSL_IMX7_NUM_USBS; i++) { | ||
726 | static const hwaddr FSL_IMX7_USBMISCn_ADDR[FSL_IMX7_NUM_USBS] = { | ||
727 | FSL_IMX7_USBMISC1_ADDR, | ||
728 | @@ -XXX,XX +XXX,XX @@ static void fsl_imx7_realize(DeviceState *dev, Error **errp) | ||
729 | */ | ||
730 | create_unimplemented_device("pcie-phy", FSL_IMX7_PCIE_PHY_ADDR, | ||
731 | FSL_IMX7_PCIE_PHY_SIZE); | ||
732 | + | ||
106 | } | 733 | } |
107 | 734 | ||
108 | type_init(allwinner_i2c_register_types) | 735 | static Property fsl_imx7_properties[] = { |
109 | -- | 736 | -- |
110 | 2.34.1 | 737 | 2.34.1 | diff view generated by jsdifflib |
1 | From: Richard Henderson <richard.henderson@linaro.org> | 1 | From: Jean-Christophe Dubois <jcd@tribudubois.net> |
---|---|---|---|
2 | 2 | ||
3 | This function is not used outside gdbstub.c. | 3 | * Add TZASC as unimplemented device. |
4 | - Allow bare metal application to access this (unimplemented) device | ||
5 | * Add CSU as unimplemented device. | ||
6 | - Allow bare metal application to access this (unimplemented) device | ||
7 | * Add various memory segments | ||
8 | - OCRAM | ||
9 | - OCRAM EPDC | ||
10 | - OCRAM PXP | ||
11 | - OCRAM S | ||
12 | - ROM | ||
13 | - CAAM | ||
4 | 14 | ||
5 | Reviewed-by: Fabiano Rosas <farosas@suse.de> | 15 | Signed-off-by: Jean-Christophe Dubois <jcd@tribudubois.net> |
6 | Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> | 16 | Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> |
7 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | 17 | Message-id: f887a3483996ba06d40bd62ffdfb0ecf68621987.1692964892.git.jcd@tribudubois.net |
8 | Message-id: 20230227213329.793795-3-richard.henderson@linaro.org | ||
9 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 18 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
10 | --- | 19 | --- |
11 | target/arm/cpu.h | 1 - | 20 | include/hw/arm/fsl-imx7.h | 7 +++++ |
12 | target/arm/gdbstub.c | 2 +- | 21 | hw/arm/fsl-imx7.c | 63 +++++++++++++++++++++++++++++++++++++++ |
13 | 2 files changed, 1 insertion(+), 2 deletions(-) | 22 | 2 files changed, 70 insertions(+) |
14 | 23 | ||
15 | diff --git a/target/arm/cpu.h b/target/arm/cpu.h | 24 | diff --git a/include/hw/arm/fsl-imx7.h b/include/hw/arm/fsl-imx7.h |
16 | index XXXXXXX..XXXXXXX 100644 | 25 | index XXXXXXX..XXXXXXX 100644 |
17 | --- a/target/arm/cpu.h | 26 | --- a/include/hw/arm/fsl-imx7.h |
18 | +++ b/target/arm/cpu.h | 27 | +++ b/include/hw/arm/fsl-imx7.h |
19 | @@ -XXX,XX +XXX,XX @@ int arm_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); | 28 | @@ -XXX,XX +XXX,XX @@ struct FslIMX7State { |
20 | * Helpers to dynamically generates XML descriptions of the sysregs | 29 | IMX7GPRState gpr; |
21 | * and SVE registers. Returns the number of registers in each set. | 30 | ChipideaState usb[FSL_IMX7_NUM_USBS]; |
22 | */ | 31 | DesignwarePCIEHost pcie; |
23 | -int arm_gen_dynamic_sysreg_xml(CPUState *cpu, int base_reg); | 32 | + MemoryRegion rom; |
24 | int arm_gen_dynamic_svereg_xml(CPUState *cpu, int base_reg); | 33 | + MemoryRegion caam; |
25 | 34 | + MemoryRegion ocram; | |
26 | /* Returns the dynamically generated XML for the gdb stub. | 35 | + MemoryRegion ocram_epdc; |
27 | diff --git a/target/arm/gdbstub.c b/target/arm/gdbstub.c | 36 | + MemoryRegion ocram_pxp; |
37 | + MemoryRegion ocram_s; | ||
38 | + | ||
39 | uint32_t phy_num[FSL_IMX7_NUM_ETHS]; | ||
40 | bool phy_connected[FSL_IMX7_NUM_ETHS]; | ||
41 | }; | ||
42 | diff --git a/hw/arm/fsl-imx7.c b/hw/arm/fsl-imx7.c | ||
28 | index XXXXXXX..XXXXXXX 100644 | 43 | index XXXXXXX..XXXXXXX 100644 |
29 | --- a/target/arm/gdbstub.c | 44 | --- a/hw/arm/fsl-imx7.c |
30 | +++ b/target/arm/gdbstub.c | 45 | +++ b/hw/arm/fsl-imx7.c |
31 | @@ -XXX,XX +XXX,XX @@ static void arm_register_sysreg_for_xml(gpointer key, gpointer value, | 46 | @@ -XXX,XX +XXX,XX @@ static void fsl_imx7_realize(DeviceState *dev, Error **errp) |
32 | } | 47 | create_unimplemented_device("pcie-phy", FSL_IMX7_PCIE_PHY_ADDR, |
48 | FSL_IMX7_PCIE_PHY_SIZE); | ||
49 | |||
50 | + /* | ||
51 | + * CSU | ||
52 | + */ | ||
53 | + create_unimplemented_device("csu", FSL_IMX7_CSU_ADDR, | ||
54 | + FSL_IMX7_CSU_SIZE); | ||
55 | + | ||
56 | + /* | ||
57 | + * TZASC | ||
58 | + */ | ||
59 | + create_unimplemented_device("tzasc", FSL_IMX7_TZASC_ADDR, | ||
60 | + FSL_IMX7_TZASC_SIZE); | ||
61 | + | ||
62 | + /* | ||
63 | + * OCRAM memory | ||
64 | + */ | ||
65 | + memory_region_init_ram(&s->ocram, NULL, "imx7.ocram", | ||
66 | + FSL_IMX7_OCRAM_MEM_SIZE, | ||
67 | + &error_abort); | ||
68 | + memory_region_add_subregion(get_system_memory(), FSL_IMX7_OCRAM_MEM_ADDR, | ||
69 | + &s->ocram); | ||
70 | + | ||
71 | + /* | ||
72 | + * OCRAM EPDC memory | ||
73 | + */ | ||
74 | + memory_region_init_ram(&s->ocram_epdc, NULL, "imx7.ocram_epdc", | ||
75 | + FSL_IMX7_OCRAM_EPDC_SIZE, | ||
76 | + &error_abort); | ||
77 | + memory_region_add_subregion(get_system_memory(), FSL_IMX7_OCRAM_EPDC_ADDR, | ||
78 | + &s->ocram_epdc); | ||
79 | + | ||
80 | + /* | ||
81 | + * OCRAM PXP memory | ||
82 | + */ | ||
83 | + memory_region_init_ram(&s->ocram_pxp, NULL, "imx7.ocram_pxp", | ||
84 | + FSL_IMX7_OCRAM_PXP_SIZE, | ||
85 | + &error_abort); | ||
86 | + memory_region_add_subregion(get_system_memory(), FSL_IMX7_OCRAM_PXP_ADDR, | ||
87 | + &s->ocram_pxp); | ||
88 | + | ||
89 | + /* | ||
90 | + * OCRAM_S memory | ||
91 | + */ | ||
92 | + memory_region_init_ram(&s->ocram_s, NULL, "imx7.ocram_s", | ||
93 | + FSL_IMX7_OCRAM_S_SIZE, | ||
94 | + &error_abort); | ||
95 | + memory_region_add_subregion(get_system_memory(), FSL_IMX7_OCRAM_S_ADDR, | ||
96 | + &s->ocram_s); | ||
97 | + | ||
98 | + /* | ||
99 | + * ROM memory | ||
100 | + */ | ||
101 | + memory_region_init_rom(&s->rom, OBJECT(dev), "imx7.rom", | ||
102 | + FSL_IMX7_ROM_SIZE, &error_abort); | ||
103 | + memory_region_add_subregion(get_system_memory(), FSL_IMX7_ROM_ADDR, | ||
104 | + &s->rom); | ||
105 | + | ||
106 | + /* | ||
107 | + * CAAM memory | ||
108 | + */ | ||
109 | + memory_region_init_rom(&s->caam, OBJECT(dev), "imx7.caam", | ||
110 | + FSL_IMX7_CAAM_MEM_SIZE, &error_abort); | ||
111 | + memory_region_add_subregion(get_system_memory(), FSL_IMX7_CAAM_MEM_ADDR, | ||
112 | + &s->caam); | ||
33 | } | 113 | } |
34 | 114 | ||
35 | -int arm_gen_dynamic_sysreg_xml(CPUState *cs, int base_reg) | 115 | static Property fsl_imx7_properties[] = { |
36 | +static int arm_gen_dynamic_sysreg_xml(CPUState *cs, int base_reg) | ||
37 | { | ||
38 | ARMCPU *cpu = ARM_CPU(cs); | ||
39 | GString *s = g_string_new(NULL); | ||
40 | -- | 116 | -- |
41 | 2.34.1 | 117 | 2.34.1 |
42 | 118 | ||
43 | 119 | diff view generated by jsdifflib |
1 | From: Richard Henderson <richard.henderson@linaro.org> | 1 | From: Jean-Christophe Dubois <jcd@tribudubois.net> |
---|---|---|---|
2 | 2 | ||
3 | The extension is primarily defined by the Linux kernel NT_ARM_PAC_MASK | 3 | The SRC device is normally used to start the secondary CPU. |
4 | ptrace register set. | 4 | |
5 | 5 | When running Linux directly, QEMU is emulating a PSCI interface that UBOOT | |
6 | The original gdb feature consists of two masks, data and code, which are | 6 | is installing at boot time and therefore the fact that the SRC device is |
7 | used to mask out the authentication code within a pointer. Following | 7 | unimplemented is hidden as Qemu respond directly to PSCI requets without |
8 | discussion with Luis Machado, add two more masks in order to support | 8 | using the SRC device. |
9 | pointers within the high half of the address space (i.e. TTBR1 vs TTBR0). | 9 | |
10 | 10 | But if you try to run a more bare metal application (maybe uboot itself), | |
11 | Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1105 | 11 | then it is not possible to start the secondary CPU as the SRC is an |
12 | unimplemented device. | ||
13 | |||
14 | This patch adds the ability to start the secondary CPU through the SRC | ||
15 | device so that you can use this feature in bare metal applications. | ||
16 | |||
17 | Signed-off-by: Jean-Christophe Dubois <jcd@tribudubois.net> | ||
12 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | 18 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> |
13 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | 19 | Message-id: ce9a0162defd2acee5dc7f8a674743de0cded569.1692964892.git.jcd@tribudubois.net |
14 | Message-id: 20230227213329.793795-12-richard.henderson@linaro.org | ||
15 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 20 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
16 | --- | 21 | --- |
17 | configs/targets/aarch64-linux-user.mak | 2 +- | 22 | include/hw/arm/fsl-imx7.h | 3 +- |
18 | configs/targets/aarch64-softmmu.mak | 2 +- | 23 | include/hw/misc/imx7_src.h | 66 +++++++++ |
19 | configs/targets/aarch64_be-linux-user.mak | 2 +- | 24 | hw/arm/fsl-imx7.c | 8 +- |
20 | target/arm/internals.h | 2 ++ | 25 | hw/misc/imx7_src.c | 276 +++++++++++++++++++++++++++++++++++++ |
21 | target/arm/gdbstub.c | 5 ++++ | 26 | hw/misc/meson.build | 1 + |
22 | target/arm/gdbstub64.c | 34 +++++++++++++++++++++++ | 27 | hw/misc/trace-events | 4 + |
23 | gdb-xml/aarch64-pauth.xml | 15 ++++++++++ | 28 | 6 files changed, 356 insertions(+), 2 deletions(-) |
24 | 7 files changed, 59 insertions(+), 3 deletions(-) | 29 | create mode 100644 include/hw/misc/imx7_src.h |
25 | create mode 100644 gdb-xml/aarch64-pauth.xml | 30 | create mode 100644 hw/misc/imx7_src.c |
26 | 31 | ||
27 | diff --git a/configs/targets/aarch64-linux-user.mak b/configs/targets/aarch64-linux-user.mak | 32 | diff --git a/include/hw/arm/fsl-imx7.h b/include/hw/arm/fsl-imx7.h |
28 | index XXXXXXX..XXXXXXX 100644 | 33 | index XXXXXXX..XXXXXXX 100644 |
29 | --- a/configs/targets/aarch64-linux-user.mak | 34 | --- a/include/hw/arm/fsl-imx7.h |
30 | +++ b/configs/targets/aarch64-linux-user.mak | 35 | +++ b/include/hw/arm/fsl-imx7.h |
31 | @@ -XXX,XX +XXX,XX @@ | 36 | @@ -XXX,XX +XXX,XX @@ |
32 | TARGET_ARCH=aarch64 | 37 | #include "hw/misc/imx7_ccm.h" |
33 | TARGET_BASE_ARCH=arm | 38 | #include "hw/misc/imx7_snvs.h" |
34 | -TARGET_XML_FILES= gdb-xml/aarch64-core.xml gdb-xml/aarch64-fpu.xml | 39 | #include "hw/misc/imx7_gpr.h" |
35 | +TARGET_XML_FILES= gdb-xml/aarch64-core.xml gdb-xml/aarch64-fpu.xml gdb-xml/aarch64-pauth.xml | 40 | +#include "hw/misc/imx7_src.h" |
36 | TARGET_HAS_BFLT=y | 41 | #include "hw/watchdog/wdt_imx2.h" |
37 | CONFIG_SEMIHOSTING=y | 42 | #include "hw/gpio/imx_gpio.h" |
38 | CONFIG_ARM_COMPATIBLE_SEMIHOSTING=y | 43 | #include "hw/char/imx_serial.h" |
39 | diff --git a/configs/targets/aarch64-softmmu.mak b/configs/targets/aarch64-softmmu.mak | 44 | @@ -XXX,XX +XXX,XX @@ struct FslIMX7State { |
40 | index XXXXXXX..XXXXXXX 100644 | 45 | IMX7CCMState ccm; |
41 | --- a/configs/targets/aarch64-softmmu.mak | 46 | IMX7AnalogState analog; |
42 | +++ b/configs/targets/aarch64-softmmu.mak | 47 | IMX7SNVSState snvs; |
43 | @@ -XXX,XX +XXX,XX @@ | 48 | + IMX7SRCState src; |
44 | TARGET_ARCH=aarch64 | 49 | IMXGPCv2State gpcv2; |
45 | TARGET_BASE_ARCH=arm | 50 | IMXSPIState spi[FSL_IMX7_NUM_ECSPIS]; |
46 | TARGET_SUPPORTS_MTTCG=y | 51 | IMXI2CState i2c[FSL_IMX7_NUM_I2CS]; |
47 | -TARGET_XML_FILES= gdb-xml/aarch64-core.xml gdb-xml/aarch64-fpu.xml gdb-xml/arm-core.xml gdb-xml/arm-vfp.xml gdb-xml/arm-vfp3.xml gdb-xml/arm-vfp-sysregs.xml gdb-xml/arm-neon.xml gdb-xml/arm-m-profile.xml gdb-xml/arm-m-profile-mve.xml | 52 | @@ -XXX,XX +XXX,XX @@ enum FslIMX7MemoryMap { |
48 | +TARGET_XML_FILES= gdb-xml/aarch64-core.xml gdb-xml/aarch64-fpu.xml gdb-xml/arm-core.xml gdb-xml/arm-vfp.xml gdb-xml/arm-vfp3.xml gdb-xml/arm-vfp-sysregs.xml gdb-xml/arm-neon.xml gdb-xml/arm-m-profile.xml gdb-xml/arm-m-profile-mve.xml gdb-xml/aarch64-pauth.xml | 53 | FSL_IMX7_GPC_ADDR = 0x303A0000, |
49 | TARGET_NEED_FDT=y | 54 | |
50 | diff --git a/configs/targets/aarch64_be-linux-user.mak b/configs/targets/aarch64_be-linux-user.mak | 55 | FSL_IMX7_SRC_ADDR = 0x30390000, |
51 | index XXXXXXX..XXXXXXX 100644 | 56 | - FSL_IMX7_SRC_SIZE = (4 * KiB), |
52 | --- a/configs/targets/aarch64_be-linux-user.mak | 57 | |
53 | +++ b/configs/targets/aarch64_be-linux-user.mak | 58 | FSL_IMX7_CCM_ADDR = 0x30380000, |
54 | @@ -XXX,XX +XXX,XX @@ | 59 | |
55 | TARGET_ARCH=aarch64 | 60 | diff --git a/include/hw/misc/imx7_src.h b/include/hw/misc/imx7_src.h |
56 | TARGET_BASE_ARCH=arm | ||
57 | TARGET_BIG_ENDIAN=y | ||
58 | -TARGET_XML_FILES= gdb-xml/aarch64-core.xml gdb-xml/aarch64-fpu.xml | ||
59 | +TARGET_XML_FILES= gdb-xml/aarch64-core.xml gdb-xml/aarch64-fpu.xml gdb-xml/aarch64-pauth.xml | ||
60 | TARGET_HAS_BFLT=y | ||
61 | CONFIG_SEMIHOSTING=y | ||
62 | CONFIG_ARM_COMPATIBLE_SEMIHOSTING=y | ||
63 | diff --git a/target/arm/internals.h b/target/arm/internals.h | ||
64 | index XXXXXXX..XXXXXXX 100644 | ||
65 | --- a/target/arm/internals.h | ||
66 | +++ b/target/arm/internals.h | ||
67 | @@ -XXX,XX +XXX,XX @@ int aarch64_gdb_get_sve_reg(CPUARMState *env, GByteArray *buf, int reg); | ||
68 | int aarch64_gdb_set_sve_reg(CPUARMState *env, uint8_t *buf, int reg); | ||
69 | int aarch64_gdb_get_fpu_reg(CPUARMState *env, GByteArray *buf, int reg); | ||
70 | int aarch64_gdb_set_fpu_reg(CPUARMState *env, uint8_t *buf, int reg); | ||
71 | +int aarch64_gdb_get_pauth_reg(CPUARMState *env, GByteArray *buf, int reg); | ||
72 | +int aarch64_gdb_set_pauth_reg(CPUARMState *env, uint8_t *buf, int reg); | ||
73 | void arm_cpu_sve_finalize(ARMCPU *cpu, Error **errp); | ||
74 | void arm_cpu_sme_finalize(ARMCPU *cpu, Error **errp); | ||
75 | void arm_cpu_pauth_finalize(ARMCPU *cpu, Error **errp); | ||
76 | diff --git a/target/arm/gdbstub.c b/target/arm/gdbstub.c | ||
77 | index XXXXXXX..XXXXXXX 100644 | ||
78 | --- a/target/arm/gdbstub.c | ||
79 | +++ b/target/arm/gdbstub.c | ||
80 | @@ -XXX,XX +XXX,XX @@ void arm_cpu_register_gdb_regs_for_features(ARMCPU *cpu) | ||
81 | aarch64_gdb_set_fpu_reg, | ||
82 | 34, "aarch64-fpu.xml", 0); | ||
83 | } | ||
84 | + if (isar_feature_aa64_pauth(&cpu->isar)) { | ||
85 | + gdb_register_coprocessor(cs, aarch64_gdb_get_pauth_reg, | ||
86 | + aarch64_gdb_set_pauth_reg, | ||
87 | + 4, "aarch64-pauth.xml", 0); | ||
88 | + } | ||
89 | #endif | ||
90 | } else { | ||
91 | if (arm_feature(env, ARM_FEATURE_NEON)) { | ||
92 | diff --git a/target/arm/gdbstub64.c b/target/arm/gdbstub64.c | ||
93 | index XXXXXXX..XXXXXXX 100644 | ||
94 | --- a/target/arm/gdbstub64.c | ||
95 | +++ b/target/arm/gdbstub64.c | ||
96 | @@ -XXX,XX +XXX,XX @@ int aarch64_gdb_set_sve_reg(CPUARMState *env, uint8_t *buf, int reg) | ||
97 | return 0; | ||
98 | } | ||
99 | |||
100 | +int aarch64_gdb_get_pauth_reg(CPUARMState *env, GByteArray *buf, int reg) | ||
101 | +{ | ||
102 | + switch (reg) { | ||
103 | + case 0: /* pauth_dmask */ | ||
104 | + case 1: /* pauth_cmask */ | ||
105 | + case 2: /* pauth_dmask_high */ | ||
106 | + case 3: /* pauth_cmask_high */ | ||
107 | + /* | ||
108 | + * Note that older versions of this feature only contained | ||
109 | + * pauth_{d,c}mask, for use with Linux user processes, and | ||
110 | + * thus exclusively in the low half of the address space. | ||
111 | + * | ||
112 | + * To support system mode, and to debug kernels, two new regs | ||
113 | + * were added to cover the high half of the address space. | ||
114 | + * For the purpose of pauth_ptr_mask, we can use any well-formed | ||
115 | + * address within the address space half -- here, 0 and -1. | ||
116 | + */ | ||
117 | + { | ||
118 | + bool is_data = !(reg & 1); | ||
119 | + bool is_high = reg & 2; | ||
120 | + uint64_t mask = pauth_ptr_mask(env, -is_high, is_data); | ||
121 | + return gdb_get_reg64(buf, mask); | ||
122 | + } | ||
123 | + default: | ||
124 | + return 0; | ||
125 | + } | ||
126 | +} | ||
127 | + | ||
128 | +int aarch64_gdb_set_pauth_reg(CPUARMState *env, uint8_t *buf, int reg) | ||
129 | +{ | ||
130 | + /* All pseudo registers are read-only. */ | ||
131 | + return 0; | ||
132 | +} | ||
133 | + | ||
134 | static void output_vector_union_type(GString *s, int reg_width, | ||
135 | const char *name) | ||
136 | { | ||
137 | diff --git a/gdb-xml/aarch64-pauth.xml b/gdb-xml/aarch64-pauth.xml | ||
138 | new file mode 100644 | 61 | new file mode 100644 |
139 | index XXXXXXX..XXXXXXX | 62 | index XXXXXXX..XXXXXXX |
140 | --- /dev/null | 63 | --- /dev/null |
141 | +++ b/gdb-xml/aarch64-pauth.xml | 64 | +++ b/include/hw/misc/imx7_src.h |
142 | @@ -XXX,XX +XXX,XX @@ | 65 | @@ -XXX,XX +XXX,XX @@ |
143 | +<?xml version="1.0"?> | 66 | +/* |
144 | +<!-- Copyright (C) 2018-2022 Free Software Foundation, Inc. | 67 | + * IMX7 System Reset Controller |
145 | + | 68 | + * |
146 | + Copying and distribution of this file, with or without modification, | 69 | + * Copyright (C) 2023 Jean-Christophe Dubois <jcd@tribudubois.net> |
147 | + are permitted in any medium without royalty provided the copyright | 70 | + * |
148 | + notice and this notice are preserved. --> | 71 | + * This work is licensed under the terms of the GNU GPL, version 2 or later. |
149 | + | 72 | + * See the COPYING file in the top-level directory. |
150 | +<!DOCTYPE feature SYSTEM "gdb-target.dtd"> | 73 | + */ |
151 | +<feature name="org.gnu.gdb.aarch64.pauth"> | 74 | + |
152 | + <reg name="pauth_dmask" bitsize="64"/> | 75 | +#ifndef IMX7_SRC_H |
153 | + <reg name="pauth_cmask" bitsize="64"/> | 76 | +#define IMX7_SRC_H |
154 | + <reg name="pauth_dmask_high" bitsize="64"/> | 77 | + |
155 | + <reg name="pauth_cmask_high" bitsize="64"/> | 78 | +#include "hw/sysbus.h" |
156 | +</feature> | 79 | +#include "qemu/bitops.h" |
157 | + | 80 | +#include "qom/object.h" |
81 | + | ||
82 | +#define SRC_SCR 0 | ||
83 | +#define SRC_A7RCR0 1 | ||
84 | +#define SRC_A7RCR1 2 | ||
85 | +#define SRC_M4RCR 3 | ||
86 | +#define SRC_ERCR 5 | ||
87 | +#define SRC_HSICPHY_RCR 7 | ||
88 | +#define SRC_USBOPHY1_RCR 8 | ||
89 | +#define SRC_USBOPHY2_RCR 9 | ||
90 | +#define SRC_MPIPHY_RCR 10 | ||
91 | +#define SRC_PCIEPHY_RCR 11 | ||
92 | +#define SRC_SBMR1 22 | ||
93 | +#define SRC_SRSR 23 | ||
94 | +#define SRC_SISR 26 | ||
95 | +#define SRC_SIMR 27 | ||
96 | +#define SRC_SBMR2 28 | ||
97 | +#define SRC_GPR1 29 | ||
98 | +#define SRC_GPR2 30 | ||
99 | +#define SRC_GPR3 31 | ||
100 | +#define SRC_GPR4 32 | ||
101 | +#define SRC_GPR5 33 | ||
102 | +#define SRC_GPR6 34 | ||
103 | +#define SRC_GPR7 35 | ||
104 | +#define SRC_GPR8 36 | ||
105 | +#define SRC_GPR9 37 | ||
106 | +#define SRC_GPR10 38 | ||
107 | +#define SRC_MAX 39 | ||
108 | + | ||
109 | +/* SRC_A7SCR1 */ | ||
110 | +#define R_CORE1_ENABLE_SHIFT 1 | ||
111 | +#define R_CORE1_ENABLE_LENGTH 1 | ||
112 | +/* SRC_A7SCR0 */ | ||
113 | +#define R_CORE1_RST_SHIFT 5 | ||
114 | +#define R_CORE1_RST_LENGTH 1 | ||
115 | +#define R_CORE0_RST_SHIFT 4 | ||
116 | +#define R_CORE0_RST_LENGTH 1 | ||
117 | + | ||
118 | +#define TYPE_IMX7_SRC "imx7.src" | ||
119 | +OBJECT_DECLARE_SIMPLE_TYPE(IMX7SRCState, IMX7_SRC) | ||
120 | + | ||
121 | +struct IMX7SRCState { | ||
122 | + /* <private> */ | ||
123 | + SysBusDevice parent_obj; | ||
124 | + | ||
125 | + /* <public> */ | ||
126 | + MemoryRegion iomem; | ||
127 | + | ||
128 | + uint32_t regs[SRC_MAX]; | ||
129 | +}; | ||
130 | + | ||
131 | +#endif /* IMX7_SRC_H */ | ||
132 | diff --git a/hw/arm/fsl-imx7.c b/hw/arm/fsl-imx7.c | ||
133 | index XXXXXXX..XXXXXXX 100644 | ||
134 | --- a/hw/arm/fsl-imx7.c | ||
135 | +++ b/hw/arm/fsl-imx7.c | ||
136 | @@ -XXX,XX +XXX,XX @@ static void fsl_imx7_init(Object *obj) | ||
137 | */ | ||
138 | object_initialize_child(obj, "gpcv2", &s->gpcv2, TYPE_IMX_GPCV2); | ||
139 | |||
140 | + /* | ||
141 | + * SRC | ||
142 | + */ | ||
143 | + object_initialize_child(obj, "src", &s->src, TYPE_IMX7_SRC); | ||
144 | + | ||
145 | /* | ||
146 | * ECSPIs | ||
147 | */ | ||
148 | @@ -XXX,XX +XXX,XX @@ static void fsl_imx7_realize(DeviceState *dev, Error **errp) | ||
149 | /* | ||
150 | * SRC | ||
151 | */ | ||
152 | - create_unimplemented_device("src", FSL_IMX7_SRC_ADDR, FSL_IMX7_SRC_SIZE); | ||
153 | + sysbus_realize(SYS_BUS_DEVICE(&s->src), &error_abort); | ||
154 | + sysbus_mmio_map(SYS_BUS_DEVICE(&s->src), 0, FSL_IMX7_SRC_ADDR); | ||
155 | |||
156 | /* | ||
157 | * Watchdogs | ||
158 | diff --git a/hw/misc/imx7_src.c b/hw/misc/imx7_src.c | ||
159 | new file mode 100644 | ||
160 | index XXXXXXX..XXXXXXX | ||
161 | --- /dev/null | ||
162 | +++ b/hw/misc/imx7_src.c | ||
163 | @@ -XXX,XX +XXX,XX @@ | ||
164 | +/* | ||
165 | + * IMX7 System Reset Controller | ||
166 | + * | ||
167 | + * Copyright (c) 2023 Jean-Christophe Dubois <jcd@tribudubois.net> | ||
168 | + * | ||
169 | + * This work is licensed under the terms of the GNU GPL, version 2 or later. | ||
170 | + * See the COPYING file in the top-level directory. | ||
171 | + * | ||
172 | + */ | ||
173 | + | ||
174 | +#include "qemu/osdep.h" | ||
175 | +#include "hw/misc/imx7_src.h" | ||
176 | +#include "migration/vmstate.h" | ||
177 | +#include "qemu/bitops.h" | ||
178 | +#include "qemu/log.h" | ||
179 | +#include "qemu/main-loop.h" | ||
180 | +#include "qemu/module.h" | ||
181 | +#include "target/arm/arm-powerctl.h" | ||
182 | +#include "hw/core/cpu.h" | ||
183 | +#include "hw/registerfields.h" | ||
184 | + | ||
185 | +#include "trace.h" | ||
186 | + | ||
187 | +static const char *imx7_src_reg_name(uint32_t reg) | ||
188 | +{ | ||
189 | + static char unknown[20]; | ||
190 | + | ||
191 | + switch (reg) { | ||
192 | + case SRC_SCR: | ||
193 | + return "SRC_SCR"; | ||
194 | + case SRC_A7RCR0: | ||
195 | + return "SRC_A7RCR0"; | ||
196 | + case SRC_A7RCR1: | ||
197 | + return "SRC_A7RCR1"; | ||
198 | + case SRC_M4RCR: | ||
199 | + return "SRC_M4RCR"; | ||
200 | + case SRC_ERCR: | ||
201 | + return "SRC_ERCR"; | ||
202 | + case SRC_HSICPHY_RCR: | ||
203 | + return "SRC_HSICPHY_RCR"; | ||
204 | + case SRC_USBOPHY1_RCR: | ||
205 | + return "SRC_USBOPHY1_RCR"; | ||
206 | + case SRC_USBOPHY2_RCR: | ||
207 | + return "SRC_USBOPHY2_RCR"; | ||
208 | + case SRC_PCIEPHY_RCR: | ||
209 | + return "SRC_PCIEPHY_RCR"; | ||
210 | + case SRC_SBMR1: | ||
211 | + return "SRC_SBMR1"; | ||
212 | + case SRC_SRSR: | ||
213 | + return "SRC_SRSR"; | ||
214 | + case SRC_SISR: | ||
215 | + return "SRC_SISR"; | ||
216 | + case SRC_SIMR: | ||
217 | + return "SRC_SIMR"; | ||
218 | + case SRC_SBMR2: | ||
219 | + return "SRC_SBMR2"; | ||
220 | + case SRC_GPR1: | ||
221 | + return "SRC_GPR1"; | ||
222 | + case SRC_GPR2: | ||
223 | + return "SRC_GPR2"; | ||
224 | + case SRC_GPR3: | ||
225 | + return "SRC_GPR3"; | ||
226 | + case SRC_GPR4: | ||
227 | + return "SRC_GPR4"; | ||
228 | + case SRC_GPR5: | ||
229 | + return "SRC_GPR5"; | ||
230 | + case SRC_GPR6: | ||
231 | + return "SRC_GPR6"; | ||
232 | + case SRC_GPR7: | ||
233 | + return "SRC_GPR7"; | ||
234 | + case SRC_GPR8: | ||
235 | + return "SRC_GPR8"; | ||
236 | + case SRC_GPR9: | ||
237 | + return "SRC_GPR9"; | ||
238 | + case SRC_GPR10: | ||
239 | + return "SRC_GPR10"; | ||
240 | + default: | ||
241 | + sprintf(unknown, "%u ?", reg); | ||
242 | + return unknown; | ||
243 | + } | ||
244 | +} | ||
245 | + | ||
246 | +static const VMStateDescription vmstate_imx7_src = { | ||
247 | + .name = TYPE_IMX7_SRC, | ||
248 | + .version_id = 1, | ||
249 | + .minimum_version_id = 1, | ||
250 | + .fields = (VMStateField[]) { | ||
251 | + VMSTATE_UINT32_ARRAY(regs, IMX7SRCState, SRC_MAX), | ||
252 | + VMSTATE_END_OF_LIST() | ||
253 | + }, | ||
254 | +}; | ||
255 | + | ||
256 | +static void imx7_src_reset(DeviceState *dev) | ||
257 | +{ | ||
258 | + IMX7SRCState *s = IMX7_SRC(dev); | ||
259 | + | ||
260 | + memset(s->regs, 0, sizeof(s->regs)); | ||
261 | + | ||
262 | + /* Set reset values */ | ||
263 | + s->regs[SRC_SCR] = 0xA0; | ||
264 | + s->regs[SRC_SRSR] = 0x1; | ||
265 | + s->regs[SRC_SIMR] = 0x1F; | ||
266 | +} | ||
267 | + | ||
268 | +static uint64_t imx7_src_read(void *opaque, hwaddr offset, unsigned size) | ||
269 | +{ | ||
270 | + uint32_t value = 0; | ||
271 | + IMX7SRCState *s = (IMX7SRCState *)opaque; | ||
272 | + uint32_t index = offset >> 2; | ||
273 | + | ||
274 | + if (index < SRC_MAX) { | ||
275 | + value = s->regs[index]; | ||
276 | + } else { | ||
277 | + qemu_log_mask(LOG_GUEST_ERROR, "[%s]%s: Bad register at offset 0x%" | ||
278 | + HWADDR_PRIx "\n", TYPE_IMX7_SRC, __func__, offset); | ||
279 | + } | ||
280 | + | ||
281 | + trace_imx7_src_read(imx7_src_reg_name(index), value); | ||
282 | + | ||
283 | + return value; | ||
284 | +} | ||
285 | + | ||
286 | + | ||
287 | +/* | ||
288 | + * The reset is asynchronous so we need to defer clearing the reset | ||
289 | + * bit until the work is completed. | ||
290 | + */ | ||
291 | + | ||
292 | +struct SRCSCRResetInfo { | ||
293 | + IMX7SRCState *s; | ||
294 | + uint32_t reset_bit; | ||
295 | +}; | ||
296 | + | ||
297 | +static void imx7_clear_reset_bit(CPUState *cpu, run_on_cpu_data data) | ||
298 | +{ | ||
299 | + struct SRCSCRResetInfo *ri = data.host_ptr; | ||
300 | + IMX7SRCState *s = ri->s; | ||
301 | + | ||
302 | + assert(qemu_mutex_iothread_locked()); | ||
303 | + | ||
304 | + s->regs[SRC_A7RCR0] = deposit32(s->regs[SRC_A7RCR0], ri->reset_bit, 1, 0); | ||
305 | + | ||
306 | + trace_imx7_src_write(imx7_src_reg_name(SRC_A7RCR0), s->regs[SRC_A7RCR0]); | ||
307 | + | ||
308 | + g_free(ri); | ||
309 | +} | ||
310 | + | ||
311 | +static void imx7_defer_clear_reset_bit(uint32_t cpuid, | ||
312 | + IMX7SRCState *s, | ||
313 | + uint32_t reset_shift) | ||
314 | +{ | ||
315 | + struct SRCSCRResetInfo *ri; | ||
316 | + CPUState *cpu = arm_get_cpu_by_id(cpuid); | ||
317 | + | ||
318 | + if (!cpu) { | ||
319 | + return; | ||
320 | + } | ||
321 | + | ||
322 | + ri = g_new(struct SRCSCRResetInfo, 1); | ||
323 | + ri->s = s; | ||
324 | + ri->reset_bit = reset_shift; | ||
325 | + | ||
326 | + async_run_on_cpu(cpu, imx7_clear_reset_bit, RUN_ON_CPU_HOST_PTR(ri)); | ||
327 | +} | ||
328 | + | ||
329 | + | ||
330 | +static void imx7_src_write(void *opaque, hwaddr offset, uint64_t value, | ||
331 | + unsigned size) | ||
332 | +{ | ||
333 | + IMX7SRCState *s = (IMX7SRCState *)opaque; | ||
334 | + uint32_t index = offset >> 2; | ||
335 | + long unsigned int change_mask; | ||
336 | + uint32_t current_value = value; | ||
337 | + | ||
338 | + if (index >= SRC_MAX) { | ||
339 | + qemu_log_mask(LOG_GUEST_ERROR, "[%s]%s: Bad register at offset 0x%" | ||
340 | + HWADDR_PRIx "\n", TYPE_IMX7_SRC, __func__, offset); | ||
341 | + return; | ||
342 | + } | ||
343 | + | ||
344 | + trace_imx7_src_write(imx7_src_reg_name(SRC_A7RCR0), s->regs[SRC_A7RCR0]); | ||
345 | + | ||
346 | + change_mask = s->regs[index] ^ (uint32_t)current_value; | ||
347 | + | ||
348 | + switch (index) { | ||
349 | + case SRC_A7RCR0: | ||
350 | + if (FIELD_EX32(change_mask, CORE0, RST)) { | ||
351 | + arm_reset_cpu(0); | ||
352 | + imx7_defer_clear_reset_bit(0, s, R_CORE0_RST_SHIFT); | ||
353 | + } | ||
354 | + if (FIELD_EX32(change_mask, CORE1, RST)) { | ||
355 | + arm_reset_cpu(1); | ||
356 | + imx7_defer_clear_reset_bit(1, s, R_CORE1_RST_SHIFT); | ||
357 | + } | ||
358 | + s->regs[index] = current_value; | ||
359 | + break; | ||
360 | + case SRC_A7RCR1: | ||
361 | + /* | ||
362 | + * On real hardware when the system reset controller starts a | ||
363 | + * secondary CPU it runs through some boot ROM code which reads | ||
364 | + * the SRC_GPRX registers controlling the start address and branches | ||
365 | + * to it. | ||
366 | + * Here we are taking a short cut and branching directly to the | ||
367 | + * requested address (we don't want to run the boot ROM code inside | ||
368 | + * QEMU) | ||
369 | + */ | ||
370 | + if (FIELD_EX32(change_mask, CORE1, ENABLE)) { | ||
371 | + if (FIELD_EX32(current_value, CORE1, ENABLE)) { | ||
372 | + /* CORE 1 is brought up */ | ||
373 | + arm_set_cpu_on(1, s->regs[SRC_GPR3], s->regs[SRC_GPR4], | ||
374 | + 3, false); | ||
375 | + } else { | ||
376 | + /* CORE 1 is shut down */ | ||
377 | + arm_set_cpu_off(1); | ||
378 | + } | ||
379 | + /* We clear the reset bits as the processor changed state */ | ||
380 | + imx7_defer_clear_reset_bit(1, s, R_CORE1_RST_SHIFT); | ||
381 | + clear_bit(R_CORE1_RST_SHIFT, &change_mask); | ||
382 | + } | ||
383 | + s->regs[index] = current_value; | ||
384 | + break; | ||
385 | + default: | ||
386 | + s->regs[index] = current_value; | ||
387 | + break; | ||
388 | + } | ||
389 | +} | ||
390 | + | ||
391 | +static const struct MemoryRegionOps imx7_src_ops = { | ||
392 | + .read = imx7_src_read, | ||
393 | + .write = imx7_src_write, | ||
394 | + .endianness = DEVICE_NATIVE_ENDIAN, | ||
395 | + .valid = { | ||
396 | + /* | ||
397 | + * Our device would not work correctly if the guest was doing | ||
398 | + * unaligned access. This might not be a limitation on the real | ||
399 | + * device but in practice there is no reason for a guest to access | ||
400 | + * this device unaligned. | ||
401 | + */ | ||
402 | + .min_access_size = 4, | ||
403 | + .max_access_size = 4, | ||
404 | + .unaligned = false, | ||
405 | + }, | ||
406 | +}; | ||
407 | + | ||
408 | +static void imx7_src_realize(DeviceState *dev, Error **errp) | ||
409 | +{ | ||
410 | + IMX7SRCState *s = IMX7_SRC(dev); | ||
411 | + | ||
412 | + memory_region_init_io(&s->iomem, OBJECT(dev), &imx7_src_ops, s, | ||
413 | + TYPE_IMX7_SRC, 0x1000); | ||
414 | + sysbus_init_mmio(SYS_BUS_DEVICE(dev), &s->iomem); | ||
415 | +} | ||
416 | + | ||
417 | +static void imx7_src_class_init(ObjectClass *klass, void *data) | ||
418 | +{ | ||
419 | + DeviceClass *dc = DEVICE_CLASS(klass); | ||
420 | + | ||
421 | + dc->realize = imx7_src_realize; | ||
422 | + dc->reset = imx7_src_reset; | ||
423 | + dc->vmsd = &vmstate_imx7_src; | ||
424 | + dc->desc = "i.MX6 System Reset Controller"; | ||
425 | +} | ||
426 | + | ||
427 | +static const TypeInfo imx7_src_info = { | ||
428 | + .name = TYPE_IMX7_SRC, | ||
429 | + .parent = TYPE_SYS_BUS_DEVICE, | ||
430 | + .instance_size = sizeof(IMX7SRCState), | ||
431 | + .class_init = imx7_src_class_init, | ||
432 | +}; | ||
433 | + | ||
434 | +static void imx7_src_register_types(void) | ||
435 | +{ | ||
436 | + type_register_static(&imx7_src_info); | ||
437 | +} | ||
438 | + | ||
439 | +type_init(imx7_src_register_types) | ||
440 | diff --git a/hw/misc/meson.build b/hw/misc/meson.build | ||
441 | index XXXXXXX..XXXXXXX 100644 | ||
442 | --- a/hw/misc/meson.build | ||
443 | +++ b/hw/misc/meson.build | ||
444 | @@ -XXX,XX +XXX,XX @@ system_ss.add(when: 'CONFIG_IMX', if_true: files( | ||
445 | 'imx6_src.c', | ||
446 | 'imx6ul_ccm.c', | ||
447 | 'imx7_ccm.c', | ||
448 | + 'imx7_src.c', | ||
449 | 'imx7_gpr.c', | ||
450 | 'imx7_snvs.c', | ||
451 | 'imx_ccm.c', | ||
452 | diff --git a/hw/misc/trace-events b/hw/misc/trace-events | ||
453 | index XXXXXXX..XXXXXXX 100644 | ||
454 | --- a/hw/misc/trace-events | ||
455 | +++ b/hw/misc/trace-events | ||
456 | @@ -XXX,XX +XXX,XX @@ ccm_clock_freq(uint32_t clock, uint32_t freq) "(Clock = %d) = %d" | ||
457 | ccm_read_reg(const char *reg_name, uint32_t value) "reg[%s] <= 0x%" PRIx32 | ||
458 | ccm_write_reg(const char *reg_name, uint32_t value) "reg[%s] => 0x%" PRIx32 | ||
459 | |||
460 | +# imx7_src.c | ||
461 | +imx7_src_read(const char *reg_name, uint32_t value) "reg[%s] => 0x%" PRIx32 | ||
462 | +imx7_src_write(const char *reg_name, uint32_t value) "reg[%s] <= 0x%" PRIx32 | ||
463 | + | ||
464 | # iotkit-sysinfo.c | ||
465 | iotkit_sysinfo_read(uint64_t offset, uint64_t data, unsigned size) "IoTKit SysInfo read: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %u" | ||
466 | iotkit_sysinfo_write(uint64_t offset, uint64_t data, unsigned size) "IoTKit SysInfo write: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %u" | ||
158 | -- | 467 | -- |
159 | 2.34.1 | 468 | 2.34.1 | diff view generated by jsdifflib |
New patch | |||
---|---|---|---|
1 | The architecture requires (R_TYTWB) that an attempt to return from EL3 | ||
2 | when SCR_EL3.{NSE,NS} are {1,0} is an illegal exception return. (This | ||
3 | enforces that the CPU can't ever be executing below EL3 with the | ||
4 | NSE,NS bits indicating an invalid security state.) | ||
1 | 5 | ||
6 | We were missing this check; add it. | ||
7 | |||
8 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
9 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
10 | Message-id: 20230807150618.101357-1-peter.maydell@linaro.org | ||
11 | --- | ||
12 | target/arm/tcg/helper-a64.c | 9 +++++++++ | ||
13 | 1 file changed, 9 insertions(+) | ||
14 | |||
15 | diff --git a/target/arm/tcg/helper-a64.c b/target/arm/tcg/helper-a64.c | ||
16 | index XXXXXXX..XXXXXXX 100644 | ||
17 | --- a/target/arm/tcg/helper-a64.c | ||
18 | +++ b/target/arm/tcg/helper-a64.c | ||
19 | @@ -XXX,XX +XXX,XX @@ void HELPER(exception_return)(CPUARMState *env, uint64_t new_pc) | ||
20 | spsr &= ~PSTATE_SS; | ||
21 | } | ||
22 | |||
23 | + /* | ||
24 | + * FEAT_RME forbids return from EL3 with an invalid security state. | ||
25 | + * We don't need an explicit check for FEAT_RME here because we enforce | ||
26 | + * in scr_write() that you can't set the NSE bit without it. | ||
27 | + */ | ||
28 | + if (cur_el == 3 && (env->cp15.scr_el3 & (SCR_NS | SCR_NSE)) == SCR_NSE) { | ||
29 | + goto illegal_return; | ||
30 | + } | ||
31 | + | ||
32 | new_el = el_from_spsr(spsr); | ||
33 | if (new_el == -1) { | ||
34 | goto illegal_return; | ||
35 | -- | ||
36 | 2.34.1 | diff view generated by jsdifflib |
New patch | |||
---|---|---|---|
1 | In the m48t59 device we almost always use 64-bit arithmetic when | ||
2 | dealing with time_t deltas. The one exception is in set_alarm(), | ||
3 | which currently uses a plain 'int' to hold the difference between two | ||
4 | time_t values. Switch to int64_t instead to avoid any possible | ||
5 | overflow issues. | ||
1 | 6 | ||
7 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
8 | Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> | ||
9 | --- | ||
10 | hw/rtc/m48t59.c | 2 +- | ||
11 | 1 file changed, 1 insertion(+), 1 deletion(-) | ||
12 | |||
13 | diff --git a/hw/rtc/m48t59.c b/hw/rtc/m48t59.c | ||
14 | index XXXXXXX..XXXXXXX 100644 | ||
15 | --- a/hw/rtc/m48t59.c | ||
16 | +++ b/hw/rtc/m48t59.c | ||
17 | @@ -XXX,XX +XXX,XX @@ static void alarm_cb (void *opaque) | ||
18 | |||
19 | static void set_alarm(M48t59State *NVRAM) | ||
20 | { | ||
21 | - int diff; | ||
22 | + int64_t diff; | ||
23 | if (NVRAM->alrm_timer != NULL) { | ||
24 | timer_del(NVRAM->alrm_timer); | ||
25 | diff = qemu_timedate_diff(&NVRAM->alarm) - NVRAM->time_offset; | ||
26 | -- | ||
27 | 2.34.1 | ||
28 | |||
29 | diff view generated by jsdifflib |
1 | From: Ard Biesheuvel <ardb@kernel.org> | 1 | In the twl92230 device, use int64_t for the two state fields |
---|---|---|---|
2 | sec_offset and alm_sec, because we set these to values that | ||
3 | are either time_t or differences between two time_t values. | ||
2 | 4 | ||
3 | Fedora 39 will ship its arm64 kernels in the new generic EFI zboot | 5 | These fields aren't saved in vmstate anywhere, so we can |
4 | format, using gzip compression for the payload. | 6 | safely widen them. |
5 | 7 | ||
6 | For doing EFI boot in QEMU, this is completely transparent, as the | 8 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
7 | firmware or bootloader will take care of this. However, for direct | 9 | Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> |
8 | kernel boot without firmware, we will lose the ability to boot such | 10 | --- |
9 | distro kernels unless we deal with the new format directly. | 11 | hw/rtc/twl92230.c | 4 ++-- |
12 | 1 file changed, 2 insertions(+), 2 deletions(-) | ||
10 | 13 | ||
11 | EFI zboot images contain metadata in the header regarding the placement | 14 | diff --git a/hw/rtc/twl92230.c b/hw/rtc/twl92230.c |
12 | of the compressed payload inside the image, and the type of compression | ||
13 | used. This means we can wire up the existing gzip support without too | ||
14 | much hassle, by parsing the header and grabbing the payload from inside | ||
15 | the loaded zboot image. | ||
16 | |||
17 | Cc: Peter Maydell <peter.maydell@linaro.org> | ||
18 | Cc: Alex Bennée <alex.bennee@linaro.org> | ||
19 | Cc: Richard Henderson <richard.henderson@linaro.org> | ||
20 | Cc: Philippe Mathieu-Daudé <f4bug@amsat.org> | ||
21 | Signed-off-by: Ard Biesheuvel <ardb@kernel.org> | ||
22 | Message-id: 20230303160109.3626966-1-ardb@kernel.org | ||
23 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
24 | [PMM: tweaked comment formatting, fixed checkpatch nits] | ||
25 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
26 | --- | ||
27 | include/hw/loader.h | 19 ++++++++++ | ||
28 | hw/arm/boot.c | 6 +++ | ||
29 | hw/core/loader.c | 91 +++++++++++++++++++++++++++++++++++++++++++++ | ||
30 | 3 files changed, 116 insertions(+) | ||
31 | |||
32 | diff --git a/include/hw/loader.h b/include/hw/loader.h | ||
33 | index XXXXXXX..XXXXXXX 100644 | 15 | index XXXXXXX..XXXXXXX 100644 |
34 | --- a/include/hw/loader.h | 16 | --- a/hw/rtc/twl92230.c |
35 | +++ b/include/hw/loader.h | 17 | +++ b/hw/rtc/twl92230.c |
36 | @@ -XXX,XX +XXX,XX @@ ssize_t load_image_gzipped_buffer(const char *filename, uint64_t max_sz, | 18 | @@ -XXX,XX +XXX,XX @@ struct MenelausState { |
37 | uint8_t **buffer); | 19 | struct tm tm; |
38 | ssize_t load_image_gzipped(const char *filename, hwaddr addr, uint64_t max_sz); | 20 | struct tm new; |
39 | 21 | struct tm alm; | |
40 | +/** | 22 | - int sec_offset; |
41 | + * unpack_efi_zboot_image: | 23 | - int alm_sec; |
42 | + * @buffer: pointer to a variable holding the address of a buffer containing the | 24 | + int64_t sec_offset; |
43 | + * image | 25 | + int64_t alm_sec; |
44 | + * @size: pointer to a variable holding the size of the buffer | 26 | int next_comp; |
45 | + * | 27 | } rtc; |
46 | + * Check whether the buffer contains a EFI zboot image, and if it does, extract | 28 | uint16_t rtc_next_vmstate; |
47 | + * the compressed payload and decompress it into a new buffer. If successful, | ||
48 | + * the old buffer is freed, and the *buffer and size variables pointed to by the | ||
49 | + * function arguments are updated to refer to the newly populated buffer. | ||
50 | + * | ||
51 | + * Returns 0 if the image could not be identified as a EFI zboot image. | ||
52 | + * Returns -1 if the buffer contents were identified as a EFI zboot image, but | ||
53 | + * unpacking failed for any reason. | ||
54 | + * Returns the size of the decompressed payload if decompression was performed | ||
55 | + * successfully. | ||
56 | + */ | ||
57 | +ssize_t unpack_efi_zboot_image(uint8_t **buffer, int *size); | ||
58 | + | ||
59 | #define ELF_LOAD_FAILED -1 | ||
60 | #define ELF_LOAD_NOT_ELF -2 | ||
61 | #define ELF_LOAD_WRONG_ARCH -3 | ||
62 | diff --git a/hw/arm/boot.c b/hw/arm/boot.c | ||
63 | index XXXXXXX..XXXXXXX 100644 | ||
64 | --- a/hw/arm/boot.c | ||
65 | +++ b/hw/arm/boot.c | ||
66 | @@ -XXX,XX +XXX,XX @@ static uint64_t load_aarch64_image(const char *filename, hwaddr mem_base, | ||
67 | return -1; | ||
68 | } | ||
69 | size = len; | ||
70 | + | ||
71 | + /* Unpack the image if it is a EFI zboot image */ | ||
72 | + if (unpack_efi_zboot_image(&buffer, &size) < 0) { | ||
73 | + g_free(buffer); | ||
74 | + return -1; | ||
75 | + } | ||
76 | } | ||
77 | |||
78 | /* check the arm64 magic header value -- very old kernels may not have it */ | ||
79 | diff --git a/hw/core/loader.c b/hw/core/loader.c | ||
80 | index XXXXXXX..XXXXXXX 100644 | ||
81 | --- a/hw/core/loader.c | ||
82 | +++ b/hw/core/loader.c | ||
83 | @@ -XXX,XX +XXX,XX @@ ssize_t load_image_gzipped(const char *filename, hwaddr addr, uint64_t max_sz) | ||
84 | return bytes; | ||
85 | } | ||
86 | |||
87 | +/* The PE/COFF MS-DOS stub magic number */ | ||
88 | +#define EFI_PE_MSDOS_MAGIC "MZ" | ||
89 | + | ||
90 | +/* | ||
91 | + * The Linux header magic number for a EFI PE/COFF | ||
92 | + * image targetting an unspecified architecture. | ||
93 | + */ | ||
94 | +#define EFI_PE_LINUX_MAGIC "\xcd\x23\x82\x81" | ||
95 | + | ||
96 | +/* | ||
97 | + * Bootable Linux kernel images may be packaged as EFI zboot images, which are | ||
98 | + * self-decompressing executables when loaded via EFI. The compressed payload | ||
99 | + * can also be extracted from the image and decompressed by a non-EFI loader. | ||
100 | + * | ||
101 | + * The de facto specification for this format is at the following URL: | ||
102 | + * | ||
103 | + * https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/drivers/firmware/efi/libstub/zboot-header.S | ||
104 | + * | ||
105 | + * This definition is based on Linux upstream commit 29636a5ce87beba. | ||
106 | + */ | ||
107 | +struct linux_efi_zboot_header { | ||
108 | + uint8_t msdos_magic[2]; /* PE/COFF 'MZ' magic number */ | ||
109 | + uint8_t reserved0[2]; | ||
110 | + uint8_t zimg[4]; /* "zimg" for Linux EFI zboot images */ | ||
111 | + uint32_t payload_offset; /* LE offset to compressed payload */ | ||
112 | + uint32_t payload_size; /* LE size of the compressed payload */ | ||
113 | + uint8_t reserved1[8]; | ||
114 | + char compression_type[32]; /* Compression type, NUL terminated */ | ||
115 | + uint8_t linux_magic[4]; /* Linux header magic */ | ||
116 | + uint32_t pe_header_offset; /* LE offset to the PE header */ | ||
117 | +}; | ||
118 | + | ||
119 | +/* | ||
120 | + * Check whether *buffer points to a Linux EFI zboot image in memory. | ||
121 | + * | ||
122 | + * If it does, attempt to decompress it to a new buffer, and free the old one. | ||
123 | + * If any of this fails, return an error to the caller. | ||
124 | + * | ||
125 | + * If the image is not a Linux EFI zboot image, do nothing and return success. | ||
126 | + */ | ||
127 | +ssize_t unpack_efi_zboot_image(uint8_t **buffer, int *size) | ||
128 | +{ | ||
129 | + const struct linux_efi_zboot_header *header; | ||
130 | + uint8_t *data = NULL; | ||
131 | + int ploff, plsize; | ||
132 | + ssize_t bytes; | ||
133 | + | ||
134 | + /* ignore if this is too small to be a EFI zboot image */ | ||
135 | + if (*size < sizeof(*header)) { | ||
136 | + return 0; | ||
137 | + } | ||
138 | + | ||
139 | + header = (struct linux_efi_zboot_header *)*buffer; | ||
140 | + | ||
141 | + /* ignore if this is not a Linux EFI zboot image */ | ||
142 | + if (memcmp(&header->msdos_magic, EFI_PE_MSDOS_MAGIC, 2) != 0 || | ||
143 | + memcmp(&header->zimg, "zimg", 4) != 0 || | ||
144 | + memcmp(&header->linux_magic, EFI_PE_LINUX_MAGIC, 4) != 0) { | ||
145 | + return 0; | ||
146 | + } | ||
147 | + | ||
148 | + if (strcmp(header->compression_type, "gzip") != 0) { | ||
149 | + fprintf(stderr, | ||
150 | + "unable to handle EFI zboot image with \"%.*s\" compression\n", | ||
151 | + (int)sizeof(header->compression_type) - 1, | ||
152 | + header->compression_type); | ||
153 | + return -1; | ||
154 | + } | ||
155 | + | ||
156 | + ploff = ldl_le_p(&header->payload_offset); | ||
157 | + plsize = ldl_le_p(&header->payload_size); | ||
158 | + | ||
159 | + if (ploff < 0 || plsize < 0 || ploff + plsize > *size) { | ||
160 | + fprintf(stderr, "unable to handle corrupt EFI zboot image\n"); | ||
161 | + return -1; | ||
162 | + } | ||
163 | + | ||
164 | + data = g_malloc(LOAD_IMAGE_MAX_GUNZIP_BYTES); | ||
165 | + bytes = gunzip(data, LOAD_IMAGE_MAX_GUNZIP_BYTES, *buffer + ploff, plsize); | ||
166 | + if (bytes < 0) { | ||
167 | + fprintf(stderr, "failed to decompress EFI zboot image\n"); | ||
168 | + g_free(data); | ||
169 | + return -1; | ||
170 | + } | ||
171 | + | ||
172 | + g_free(*buffer); | ||
173 | + *buffer = g_realloc(data, bytes); | ||
174 | + *size = bytes; | ||
175 | + return bytes; | ||
176 | +} | ||
177 | + | ||
178 | /* | ||
179 | * Functions for reboot-persistent memory regions. | ||
180 | * - used for vga bios and option roms. | ||
181 | -- | 29 | -- |
182 | 2.34.1 | 30 | 2.34.1 |
183 | 31 | ||
184 | 32 | diff view generated by jsdifflib |
1 | From: Richard Henderson <richard.henderson@linaro.org> | 1 | In the aspeed_rtc device we store a difference between two time_t |
---|---|---|---|
2 | values in an 'int'. This is not really correct when time_t could | ||
3 | be 64 bits. Enlarge the field to 'int64_t'. | ||
2 | 4 | ||
3 | Reviewed-by: Fabiano Rosas <farosas@suse.de> | 5 | This is a migration compatibility break for the aspeed boards. |
4 | Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> | 6 | While we are changing the vmstate, remove the accidental |
5 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | 7 | duplicate of the offset field. |
6 | Message-id: 20230227213329.793795-7-richard.henderson@linaro.org | 8 | |
7 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 9 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
10 | Reviewed-by: Cédric Le Goater <clg@kaod.org> | ||
8 | --- | 11 | --- |
9 | target/arm/gdbstub64.c | 5 +++-- | 12 | include/hw/rtc/aspeed_rtc.h | 2 +- |
10 | 1 file changed, 3 insertions(+), 2 deletions(-) | 13 | hw/rtc/aspeed_rtc.c | 5 ++--- |
14 | 2 files changed, 3 insertions(+), 4 deletions(-) | ||
11 | 15 | ||
12 | diff --git a/target/arm/gdbstub64.c b/target/arm/gdbstub64.c | 16 | diff --git a/include/hw/rtc/aspeed_rtc.h b/include/hw/rtc/aspeed_rtc.h |
13 | index XXXXXXX..XXXXXXX 100644 | 17 | index XXXXXXX..XXXXXXX 100644 |
14 | --- a/target/arm/gdbstub64.c | 18 | --- a/include/hw/rtc/aspeed_rtc.h |
15 | +++ b/target/arm/gdbstub64.c | 19 | +++ b/include/hw/rtc/aspeed_rtc.h |
16 | @@ -XXX,XX +XXX,XX @@ int arm_gen_dynamic_svereg_xml(CPUState *cs, int orig_base_reg) | 20 | @@ -XXX,XX +XXX,XX @@ struct AspeedRtcState { |
17 | GString *s = g_string_new(NULL); | 21 | qemu_irq irq; |
18 | DynamicGDBXMLInfo *info = &cpu->dyn_svereg_xml; | 22 | |
19 | int reg_width = cpu->sve_max_vq * 128; | 23 | uint32_t reg[0x18]; |
20 | + int pred_width = cpu->sve_max_vq * 16; | 24 | - int offset; |
21 | int base_reg = orig_base_reg; | 25 | + int64_t offset; |
22 | int i; | 26 | |
23 | 27 | }; | |
24 | @@ -XXX,XX +XXX,XX @@ int arm_gen_dynamic_svereg_xml(CPUState *cs, int orig_base_reg) | 28 | |
25 | g_string_append_printf(s, | 29 | diff --git a/hw/rtc/aspeed_rtc.c b/hw/rtc/aspeed_rtc.c |
26 | "<reg name=\"p%d\" bitsize=\"%d\"" | 30 | index XXXXXXX..XXXXXXX 100644 |
27 | " regnum=\"%d\" type=\"svep\"/>", | 31 | --- a/hw/rtc/aspeed_rtc.c |
28 | - i, cpu->sve_max_vq * 16, base_reg++); | 32 | +++ b/hw/rtc/aspeed_rtc.c |
29 | + i, pred_width, base_reg++); | 33 | @@ -XXX,XX +XXX,XX @@ static const MemoryRegionOps aspeed_rtc_ops = { |
34 | |||
35 | static const VMStateDescription vmstate_aspeed_rtc = { | ||
36 | .name = TYPE_ASPEED_RTC, | ||
37 | - .version_id = 1, | ||
38 | + .version_id = 2, | ||
39 | .fields = (VMStateField[]) { | ||
40 | VMSTATE_UINT32_ARRAY(reg, AspeedRtcState, 0x18), | ||
41 | - VMSTATE_INT32(offset, AspeedRtcState), | ||
42 | - VMSTATE_INT32(offset, AspeedRtcState), | ||
43 | + VMSTATE_INT64(offset, AspeedRtcState), | ||
44 | VMSTATE_END_OF_LIST() | ||
30 | } | 45 | } |
31 | g_string_append_printf(s, | 46 | }; |
32 | "<reg name=\"ffr\" bitsize=\"%d\"" | ||
33 | " regnum=\"%d\" group=\"vector\"" | ||
34 | " type=\"svep\"/>", | ||
35 | - cpu->sve_max_vq * 16, base_reg++); | ||
36 | + pred_width, base_reg++); | ||
37 | |||
38 | /* Define the vector length pseudo-register. */ | ||
39 | g_string_append_printf(s, | ||
40 | -- | 47 | -- |
41 | 2.34.1 | 48 | 2.34.1 |
42 | 49 | ||
43 | 50 | diff view generated by jsdifflib |
1 | From: Richard Henderson <richard.henderson@linaro.org> | 1 | The functions qemu_get_timedate() and qemu_timedate_diff() take |
---|---|---|---|
2 | and return a time offset as an integer. Coverity points out that | ||
3 | means that when an RTC device implementation holds an offset | ||
4 | as a time_t, as the m48t59 does, the time_t will get truncated. | ||
5 | (CID 1507157, 1517772). | ||
2 | 6 | ||
3 | Make the form of the function names between fp and sve the same: | 7 | The functions work with time_t internally, so make them use that type |
4 | - arm_gdb_*_svereg -> aarch64_gdb_*_sve_reg. | 8 | in their APIs. |
5 | - aarch64_fpu_gdb_*_reg -> aarch64_gdb_*_fpu_reg. | ||
6 | 9 | ||
7 | Reviewed-by: Fabiano Rosas <farosas@suse.de> | 10 | Note that this won't help any Y2038 issues where either the device |
11 | model itself is keeping the offset in a 32-bit integer, or where the | ||
12 | hardware under emulation has Y2038 or other rollover problems. If we | ||
13 | missed any cases of the former then hopefully Coverity will warn us | ||
14 | about them since after this patch we'd be truncating a time_t in | ||
15 | assignments from qemu_timedate_diff().) | ||
16 | |||
17 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
8 | Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> | 18 | Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> |
9 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | ||
10 | Message-id: 20230227213329.793795-2-richard.henderson@linaro.org | ||
11 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
12 | --- | 19 | --- |
13 | target/arm/internals.h | 8 ++++---- | 20 | include/sysemu/rtc.h | 4 ++-- |
14 | target/arm/gdbstub.c | 9 +++++---- | 21 | softmmu/rtc.c | 4 ++-- |
15 | target/arm/gdbstub64.c | 8 ++++---- | 22 | 2 files changed, 4 insertions(+), 4 deletions(-) |
16 | 3 files changed, 13 insertions(+), 12 deletions(-) | ||
17 | 23 | ||
18 | diff --git a/target/arm/internals.h b/target/arm/internals.h | 24 | diff --git a/include/sysemu/rtc.h b/include/sysemu/rtc.h |
19 | index XXXXXXX..XXXXXXX 100644 | 25 | index XXXXXXX..XXXXXXX 100644 |
20 | --- a/target/arm/internals.h | 26 | --- a/include/sysemu/rtc.h |
21 | +++ b/target/arm/internals.h | 27 | +++ b/include/sysemu/rtc.h |
22 | @@ -XXX,XX +XXX,XX @@ static inline uint64_t pmu_counter_mask(CPUARMState *env) | 28 | @@ -XXX,XX +XXX,XX @@ |
29 | * The behaviour of the clock whose value this function returns will | ||
30 | * depend on the -rtc command line option passed by the user. | ||
31 | */ | ||
32 | -void qemu_get_timedate(struct tm *tm, int offset); | ||
33 | +void qemu_get_timedate(struct tm *tm, time_t offset); | ||
34 | |||
35 | /** | ||
36 | * qemu_timedate_diff: Return difference between a struct tm and the RTC | ||
37 | @@ -XXX,XX +XXX,XX @@ void qemu_get_timedate(struct tm *tm, int offset); | ||
38 | * a timestamp one hour further ahead than the current RTC time | ||
39 | * then this function will return 3600. | ||
40 | */ | ||
41 | -int qemu_timedate_diff(struct tm *tm); | ||
42 | +time_t qemu_timedate_diff(struct tm *tm); | ||
43 | |||
44 | #endif | ||
45 | diff --git a/softmmu/rtc.c b/softmmu/rtc.c | ||
46 | index XXXXXXX..XXXXXXX 100644 | ||
47 | --- a/softmmu/rtc.c | ||
48 | +++ b/softmmu/rtc.c | ||
49 | @@ -XXX,XX +XXX,XX @@ static time_t qemu_ref_timedate(QEMUClockType clock) | ||
50 | return value; | ||
23 | } | 51 | } |
24 | 52 | ||
25 | #ifdef TARGET_AARCH64 | 53 | -void qemu_get_timedate(struct tm *tm, int offset) |
26 | -int arm_gdb_get_svereg(CPUARMState *env, GByteArray *buf, int reg); | 54 | +void qemu_get_timedate(struct tm *tm, time_t offset) |
27 | -int arm_gdb_set_svereg(CPUARMState *env, uint8_t *buf, int reg); | ||
28 | -int aarch64_fpu_gdb_get_reg(CPUARMState *env, GByteArray *buf, int reg); | ||
29 | -int aarch64_fpu_gdb_set_reg(CPUARMState *env, uint8_t *buf, int reg); | ||
30 | +int aarch64_gdb_get_sve_reg(CPUARMState *env, GByteArray *buf, int reg); | ||
31 | +int aarch64_gdb_set_sve_reg(CPUARMState *env, uint8_t *buf, int reg); | ||
32 | +int aarch64_gdb_get_fpu_reg(CPUARMState *env, GByteArray *buf, int reg); | ||
33 | +int aarch64_gdb_set_fpu_reg(CPUARMState *env, uint8_t *buf, int reg); | ||
34 | void arm_cpu_sve_finalize(ARMCPU *cpu, Error **errp); | ||
35 | void arm_cpu_sme_finalize(ARMCPU *cpu, Error **errp); | ||
36 | void arm_cpu_pauth_finalize(ARMCPU *cpu, Error **errp); | ||
37 | diff --git a/target/arm/gdbstub.c b/target/arm/gdbstub.c | ||
38 | index XXXXXXX..XXXXXXX 100644 | ||
39 | --- a/target/arm/gdbstub.c | ||
40 | +++ b/target/arm/gdbstub.c | ||
41 | @@ -XXX,XX +XXX,XX @@ void arm_cpu_register_gdb_regs_for_features(ARMCPU *cpu) | ||
42 | */ | ||
43 | #ifdef TARGET_AARCH64 | ||
44 | if (isar_feature_aa64_sve(&cpu->isar)) { | ||
45 | - gdb_register_coprocessor(cs, arm_gdb_get_svereg, arm_gdb_set_svereg, | ||
46 | - arm_gen_dynamic_svereg_xml(cs, cs->gdb_num_regs), | ||
47 | + int nreg = arm_gen_dynamic_svereg_xml(cs, cs->gdb_num_regs); | ||
48 | + gdb_register_coprocessor(cs, aarch64_gdb_get_sve_reg, | ||
49 | + aarch64_gdb_set_sve_reg, nreg, | ||
50 | "sve-registers.xml", 0); | ||
51 | } else { | ||
52 | - gdb_register_coprocessor(cs, aarch64_fpu_gdb_get_reg, | ||
53 | - aarch64_fpu_gdb_set_reg, | ||
54 | + gdb_register_coprocessor(cs, aarch64_gdb_get_fpu_reg, | ||
55 | + aarch64_gdb_set_fpu_reg, | ||
56 | 34, "aarch64-fpu.xml", 0); | ||
57 | } | ||
58 | #endif | ||
59 | diff --git a/target/arm/gdbstub64.c b/target/arm/gdbstub64.c | ||
60 | index XXXXXXX..XXXXXXX 100644 | ||
61 | --- a/target/arm/gdbstub64.c | ||
62 | +++ b/target/arm/gdbstub64.c | ||
63 | @@ -XXX,XX +XXX,XX @@ int aarch64_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n) | ||
64 | return 0; | ||
65 | } | ||
66 | |||
67 | -int aarch64_fpu_gdb_get_reg(CPUARMState *env, GByteArray *buf, int reg) | ||
68 | +int aarch64_gdb_get_fpu_reg(CPUARMState *env, GByteArray *buf, int reg) | ||
69 | { | 55 | { |
70 | switch (reg) { | 56 | time_t ti = qemu_ref_timedate(rtc_clock); |
71 | case 0 ... 31: | 57 | |
72 | @@ -XXX,XX +XXX,XX @@ int aarch64_fpu_gdb_get_reg(CPUARMState *env, GByteArray *buf, int reg) | 58 | @@ -XXX,XX +XXX,XX @@ void qemu_get_timedate(struct tm *tm, int offset) |
73 | } | 59 | } |
74 | } | 60 | } |
75 | 61 | ||
76 | -int aarch64_fpu_gdb_set_reg(CPUARMState *env, uint8_t *buf, int reg) | 62 | -int qemu_timedate_diff(struct tm *tm) |
77 | +int aarch64_gdb_set_fpu_reg(CPUARMState *env, uint8_t *buf, int reg) | 63 | +time_t qemu_timedate_diff(struct tm *tm) |
78 | { | 64 | { |
79 | switch (reg) { | 65 | time_t seconds; |
80 | case 0 ... 31: | ||
81 | @@ -XXX,XX +XXX,XX @@ int aarch64_fpu_gdb_set_reg(CPUARMState *env, uint8_t *buf, int reg) | ||
82 | } | ||
83 | } | ||
84 | |||
85 | -int arm_gdb_get_svereg(CPUARMState *env, GByteArray *buf, int reg) | ||
86 | +int aarch64_gdb_get_sve_reg(CPUARMState *env, GByteArray *buf, int reg) | ||
87 | { | ||
88 | ARMCPU *cpu = env_archcpu(env); | ||
89 | |||
90 | @@ -XXX,XX +XXX,XX @@ int arm_gdb_get_svereg(CPUARMState *env, GByteArray *buf, int reg) | ||
91 | return 0; | ||
92 | } | ||
93 | |||
94 | -int arm_gdb_set_svereg(CPUARMState *env, uint8_t *buf, int reg) | ||
95 | +int aarch64_gdb_set_sve_reg(CPUARMState *env, uint8_t *buf, int reg) | ||
96 | { | ||
97 | ARMCPU *cpu = env_archcpu(env); | ||
98 | 66 | ||
99 | -- | 67 | -- |
100 | 2.34.1 | 68 | 2.34.1 |
101 | 69 | ||
102 | 70 | diff view generated by jsdifflib |
1 | From: Richard Henderson <richard.henderson@linaro.org> | 1 | Where architecturally one ARM_FEATURE_X flag implies another |
---|---|---|---|
2 | 2 | ARM_FEATURE_Y, we allow the CPU init function to only set X, and then | |
3 | Integrate neighboring code from get_phys_addr_lpae which computed | 3 | set Y for it. Currently we do this in two places -- we set a few |
4 | starting level, as it is easier to validate when doing both at the | 4 | flags in arm_cpu_post_init() because we need them to decide which |
5 | same time. Mirror the checks at the start of AArch{64,32}.S2Walk, | 5 | properties to create on the CPU object, and then we do the rest in |
6 | especially S2InvalidSL and S2InconsistentSL. | 6 | arm_cpu_realizefn(). However, this is fragile, because it's easy to |
7 | 7 | add a new property and not notice that this means that an X-implies-Y | |
8 | This reverts 49ba115bb74, which was incorrect -- there is nothing | 8 | check now has to move from realize to post-init. |
9 | in the ARM pseudocode that depends on TxSZ, i.e. outputsize; the | 9 | |
10 | pseudocode is consistent in referencing PAMax. | 10 | As a specific example, the pmsav7-dregion property is conditional |
11 | 11 | on ARM_FEATURE_PMSA && ARM_FEATURE_V7, which means it won't appear | |
12 | Fixes: 49ba115bb74 ("target/arm: Pass outputsize down to check_s2_mmu_setup") | 12 | on the Cortex-M33 and -M55, because they set ARM_FEATURE_V8 and |
13 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | 13 | rely on V8-implies-V7, which doesn't happen until the realizefn. |
14 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | 14 | |
15 | Message-id: 20230227225832.816605-5-richard.henderson@linaro.org | 15 | Move all of these X-implies-Y checks into a new function, which |
16 | we call at the top of arm_cpu_post_init(), so the feature bits | ||
17 | are available at that point. | ||
18 | |||
19 | This does now give us the reverse issue, that if there's a feature | ||
20 | bit which is enabled or disabled by the setting of a property then | ||
21 | then X-implies-Y features that are dependent on that property need to | ||
22 | be in realize, not in this new function. But the only one of those | ||
23 | is the "EL3 implies VBAR" which is already in the right place, so | ||
24 | putting things this way round seems better to me. | ||
25 | |||
16 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 26 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
27 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
28 | Message-id: 20230724174335.2150499-2-peter.maydell@linaro.org | ||
17 | --- | 29 | --- |
18 | target/arm/ptw.c | 173 ++++++++++++++++++++++++++--------------------- | 30 | target/arm/cpu.c | 179 +++++++++++++++++++++++++---------------------- |
19 | 1 file changed, 97 insertions(+), 76 deletions(-) | 31 | 1 file changed, 97 insertions(+), 82 deletions(-) |
20 | 32 | ||
21 | diff --git a/target/arm/ptw.c b/target/arm/ptw.c | 33 | diff --git a/target/arm/cpu.c b/target/arm/cpu.c |
22 | index XXXXXXX..XXXXXXX 100644 | 34 | index XXXXXXX..XXXXXXX 100644 |
23 | --- a/target/arm/ptw.c | 35 | --- a/target/arm/cpu.c |
24 | +++ b/target/arm/ptw.c | 36 | +++ b/target/arm/cpu.c |
25 | @@ -XXX,XX +XXX,XX @@ static ARMVAParameters aa32_va_parameters(CPUARMState *env, uint32_t va, | 37 | @@ -XXX,XX +XXX,XX @@ unsigned int gt_cntfrq_period_ns(ARMCPU *cpu) |
26 | * check_s2_mmu_setup | 38 | NANOSECONDS_PER_SECOND / cpu->gt_cntfrq_hz : 1; |
27 | * @cpu: ARMCPU | 39 | } |
28 | * @is_aa64: True if the translation regime is in AArch64 state | 40 | |
29 | - * @startlevel: Suggested starting level | 41 | +static void arm_cpu_propagate_feature_implications(ARMCPU *cpu) |
30 | - * @inputsize: Bitsize of IPAs | 42 | +{ |
31 | + * @tcr: VTCR_EL2 or VSTCR_EL2 | 43 | + CPUARMState *env = &cpu->env; |
32 | + * @ds: Effective value of TCR.DS. | 44 | + bool no_aa32 = false; |
33 | + * @iasize: Bitsize of IPAs | 45 | + |
34 | * @stride: Page-table stride (See the ARM ARM) | 46 | + /* |
35 | * | 47 | + * Some features automatically imply others: set the feature |
36 | - * Returns true if the suggested S2 translation parameters are OK and | 48 | + * bits explicitly for these cases. |
37 | - * false otherwise. | 49 | + */ |
38 | + * Decode the starting level of the S2 lookup, returning INT_MIN if | 50 | + |
39 | + * the configuration is invalid. | 51 | + if (arm_feature(env, ARM_FEATURE_M)) { |
40 | */ | 52 | + set_feature(env, ARM_FEATURE_PMSA); |
41 | -static bool check_s2_mmu_setup(ARMCPU *cpu, bool is_aa64, int level, | 53 | + } |
42 | - int inputsize, int stride, int outputsize) | 54 | + |
43 | +static int check_s2_mmu_setup(ARMCPU *cpu, bool is_aa64, uint64_t tcr, | 55 | + if (arm_feature(env, ARM_FEATURE_V8)) { |
44 | + bool ds, int iasize, int stride) | 56 | + if (arm_feature(env, ARM_FEATURE_M)) { |
57 | + set_feature(env, ARM_FEATURE_V7); | ||
58 | + } else { | ||
59 | + set_feature(env, ARM_FEATURE_V7VE); | ||
60 | + } | ||
61 | + } | ||
62 | + | ||
63 | + /* | ||
64 | + * There exist AArch64 cpus without AArch32 support. When KVM | ||
65 | + * queries ID_ISAR0_EL1 on such a host, the value is UNKNOWN. | ||
66 | + * Similarly, we cannot check ID_AA64PFR0 without AArch64 support. | ||
67 | + * As a general principle, we also do not make ID register | ||
68 | + * consistency checks anywhere unless using TCG, because only | ||
69 | + * for TCG would a consistency-check failure be a QEMU bug. | ||
70 | + */ | ||
71 | + if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) { | ||
72 | + no_aa32 = !cpu_isar_feature(aa64_aa32, cpu); | ||
73 | + } | ||
74 | + | ||
75 | + if (arm_feature(env, ARM_FEATURE_V7VE)) { | ||
76 | + /* | ||
77 | + * v7 Virtualization Extensions. In real hardware this implies | ||
78 | + * EL2 and also the presence of the Security Extensions. | ||
79 | + * For QEMU, for backwards-compatibility we implement some | ||
80 | + * CPUs or CPU configs which have no actual EL2 or EL3 but do | ||
81 | + * include the various other features that V7VE implies. | ||
82 | + * Presence of EL2 itself is ARM_FEATURE_EL2, and of the | ||
83 | + * Security Extensions is ARM_FEATURE_EL3. | ||
84 | + */ | ||
85 | + assert(!tcg_enabled() || no_aa32 || | ||
86 | + cpu_isar_feature(aa32_arm_div, cpu)); | ||
87 | + set_feature(env, ARM_FEATURE_LPAE); | ||
88 | + set_feature(env, ARM_FEATURE_V7); | ||
89 | + } | ||
90 | + if (arm_feature(env, ARM_FEATURE_V7)) { | ||
91 | + set_feature(env, ARM_FEATURE_VAPA); | ||
92 | + set_feature(env, ARM_FEATURE_THUMB2); | ||
93 | + set_feature(env, ARM_FEATURE_MPIDR); | ||
94 | + if (!arm_feature(env, ARM_FEATURE_M)) { | ||
95 | + set_feature(env, ARM_FEATURE_V6K); | ||
96 | + } else { | ||
97 | + set_feature(env, ARM_FEATURE_V6); | ||
98 | + } | ||
99 | + | ||
100 | + /* | ||
101 | + * Always define VBAR for V7 CPUs even if it doesn't exist in | ||
102 | + * non-EL3 configs. This is needed by some legacy boards. | ||
103 | + */ | ||
104 | + set_feature(env, ARM_FEATURE_VBAR); | ||
105 | + } | ||
106 | + if (arm_feature(env, ARM_FEATURE_V6K)) { | ||
107 | + set_feature(env, ARM_FEATURE_V6); | ||
108 | + set_feature(env, ARM_FEATURE_MVFR); | ||
109 | + } | ||
110 | + if (arm_feature(env, ARM_FEATURE_V6)) { | ||
111 | + set_feature(env, ARM_FEATURE_V5); | ||
112 | + if (!arm_feature(env, ARM_FEATURE_M)) { | ||
113 | + assert(!tcg_enabled() || no_aa32 || | ||
114 | + cpu_isar_feature(aa32_jazelle, cpu)); | ||
115 | + set_feature(env, ARM_FEATURE_AUXCR); | ||
116 | + } | ||
117 | + } | ||
118 | + if (arm_feature(env, ARM_FEATURE_V5)) { | ||
119 | + set_feature(env, ARM_FEATURE_V4T); | ||
120 | + } | ||
121 | + if (arm_feature(env, ARM_FEATURE_LPAE)) { | ||
122 | + set_feature(env, ARM_FEATURE_V7MP); | ||
123 | + } | ||
124 | + if (arm_feature(env, ARM_FEATURE_CBAR_RO)) { | ||
125 | + set_feature(env, ARM_FEATURE_CBAR); | ||
126 | + } | ||
127 | + if (arm_feature(env, ARM_FEATURE_THUMB2) && | ||
128 | + !arm_feature(env, ARM_FEATURE_M)) { | ||
129 | + set_feature(env, ARM_FEATURE_THUMB_DSP); | ||
130 | + } | ||
131 | +} | ||
132 | + | ||
133 | void arm_cpu_post_init(Object *obj) | ||
45 | { | 134 | { |
46 | - const int grainsize = stride + 3; | 135 | ARMCPU *cpu = ARM_CPU(obj); |
47 | - int startsizecheck; | 136 | |
137 | - /* M profile implies PMSA. We have to do this here rather than | ||
138 | - * in realize with the other feature-implication checks because | ||
139 | - * we look at the PMSA bit to see if we should add some properties. | ||
140 | + /* | ||
141 | + * Some features imply others. Figure this out now, because we | ||
142 | + * are going to look at the feature bits in deciding which | ||
143 | + * properties to add. | ||
144 | */ | ||
145 | - if (arm_feature(&cpu->env, ARM_FEATURE_M)) { | ||
146 | - set_feature(&cpu->env, ARM_FEATURE_PMSA); | ||
147 | - } | ||
148 | + arm_cpu_propagate_feature_implications(cpu); | ||
149 | |||
150 | if (arm_feature(&cpu->env, ARM_FEATURE_CBAR) || | ||
151 | arm_feature(&cpu->env, ARM_FEATURE_CBAR_RO)) { | ||
152 | @@ -XXX,XX +XXX,XX @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp) | ||
153 | CPUARMState *env = &cpu->env; | ||
154 | int pagebits; | ||
155 | Error *local_err = NULL; | ||
156 | - bool no_aa32 = false; | ||
157 | |||
158 | /* Use pc-relative instructions in system-mode */ | ||
159 | #ifndef CONFIG_USER_ONLY | ||
160 | @@ -XXX,XX +XXX,XX @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp) | ||
161 | cpu->isar.id_isar3 = u; | ||
162 | } | ||
163 | |||
164 | - /* Some features automatically imply others: */ | ||
165 | - if (arm_feature(env, ARM_FEATURE_V8)) { | ||
166 | - if (arm_feature(env, ARM_FEATURE_M)) { | ||
167 | - set_feature(env, ARM_FEATURE_V7); | ||
168 | - } else { | ||
169 | - set_feature(env, ARM_FEATURE_V7VE); | ||
170 | - } | ||
171 | - } | ||
48 | - | 172 | - |
49 | - /* | 173 | - /* |
50 | - * Negative levels are usually not allowed... | 174 | - * There exist AArch64 cpus without AArch32 support. When KVM |
51 | - * Except for FEAT_LPA2, 4k page table, 52-bit address space, which | 175 | - * queries ID_ISAR0_EL1 on such a host, the value is UNKNOWN. |
52 | - * begins with level -1. Note that previous feature tests will have | 176 | - * Similarly, we cannot check ID_AA64PFR0 without AArch64 support. |
53 | - * eliminated this combination if it is not enabled. | 177 | - * As a general principle, we also do not make ID register |
178 | - * consistency checks anywhere unless using TCG, because only | ||
179 | - * for TCG would a consistency-check failure be a QEMU bug. | ||
54 | - */ | 180 | - */ |
55 | - if (level < (inputsize == 52 && stride == 9 ? -1 : 0)) { | 181 | - if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) { |
56 | - return false; | 182 | - no_aa32 = !cpu_isar_feature(aa64_aa32, cpu); |
57 | - } | 183 | - } |
58 | - | 184 | - |
59 | - startsizecheck = inputsize - ((3 - level) * stride + grainsize); | 185 | - if (arm_feature(env, ARM_FEATURE_V7VE)) { |
60 | - if (startsizecheck < 1 || startsizecheck > stride + 4) { | 186 | - /* v7 Virtualization Extensions. In real hardware this implies |
61 | - return false; | 187 | - * EL2 and also the presence of the Security Extensions. |
62 | - } | 188 | - * For QEMU, for backwards-compatibility we implement some |
63 | + int sl0, sl2, startlevel, granulebits, levels; | 189 | - * CPUs or CPU configs which have no actual EL2 or EL3 but do |
64 | + int s1_min_iasize, s1_max_iasize; | 190 | - * include the various other features that V7VE implies. |
65 | 191 | - * Presence of EL2 itself is ARM_FEATURE_EL2, and of the | |
66 | + sl0 = extract32(tcr, 6, 2); | 192 | - * Security Extensions is ARM_FEATURE_EL3. |
67 | if (is_aa64) { | ||
68 | + /* | ||
69 | + * AArch64.S2InvalidTxSZ: While we checked tsz_oob near the top of | ||
70 | + * get_phys_addr_lpae, that used aa64_va_parameters which apply | ||
71 | + * to aarch64. If Stage1 is aarch32, the min_txsz is larger. | ||
72 | + * See AArch64.S2MinTxSZ, where min_tsz is 24, translated to | ||
73 | + * inputsize is 64 - 24 = 40. | ||
74 | + */ | ||
75 | + if (iasize < 40 && !arm_el_is_aa64(&cpu->env, 1)) { | ||
76 | + goto fail; | ||
77 | + } | ||
78 | + | ||
79 | + /* | ||
80 | + * AArch64.S2InvalidSL: Interpretation of SL depends on the page size, | ||
81 | + * so interleave AArch64.S2StartLevel. | ||
82 | + */ | ||
83 | switch (stride) { | ||
84 | - case 13: /* 64KB Pages. */ | ||
85 | - if (level == 0 || (level == 1 && outputsize <= 42)) { | ||
86 | - return false; | ||
87 | + case 9: /* 4KB */ | ||
88 | + /* SL2 is RES0 unless DS=1 & 4KB granule. */ | ||
89 | + sl2 = extract64(tcr, 33, 1); | ||
90 | + if (ds && sl2) { | ||
91 | + if (sl0 != 0) { | ||
92 | + goto fail; | ||
93 | + } | ||
94 | + startlevel = -1; | ||
95 | + } else { | ||
96 | + startlevel = 2 - sl0; | ||
97 | + switch (sl0) { | ||
98 | + case 2: | ||
99 | + if (arm_pamax(cpu) < 44) { | ||
100 | + goto fail; | ||
101 | + } | ||
102 | + break; | ||
103 | + case 3: | ||
104 | + if (!cpu_isar_feature(aa64_st, cpu)) { | ||
105 | + goto fail; | ||
106 | + } | ||
107 | + startlevel = 3; | ||
108 | + break; | ||
109 | + } | ||
110 | } | ||
111 | break; | ||
112 | - case 11: /* 16KB Pages. */ | ||
113 | - if (level == 0 || (level == 1 && outputsize <= 40)) { | ||
114 | - return false; | ||
115 | + case 11: /* 16KB */ | ||
116 | + switch (sl0) { | ||
117 | + case 2: | ||
118 | + if (arm_pamax(cpu) < 42) { | ||
119 | + goto fail; | ||
120 | + } | ||
121 | + break; | ||
122 | + case 3: | ||
123 | + if (!ds) { | ||
124 | + goto fail; | ||
125 | + } | ||
126 | + break; | ||
127 | } | ||
128 | + startlevel = 3 - sl0; | ||
129 | break; | ||
130 | - case 9: /* 4KB Pages. */ | ||
131 | - if (level == 0 && outputsize <= 42) { | ||
132 | - return false; | ||
133 | + case 13: /* 64KB */ | ||
134 | + switch (sl0) { | ||
135 | + case 2: | ||
136 | + if (arm_pamax(cpu) < 44) { | ||
137 | + goto fail; | ||
138 | + } | ||
139 | + break; | ||
140 | + case 3: | ||
141 | + goto fail; | ||
142 | } | ||
143 | + startlevel = 3 - sl0; | ||
144 | break; | ||
145 | default: | ||
146 | g_assert_not_reached(); | ||
147 | } | ||
148 | - | ||
149 | - /* Inputsize checks. */ | ||
150 | - if (inputsize > outputsize && | ||
151 | - (arm_el_is_aa64(&cpu->env, 1) || inputsize > 40)) { | ||
152 | - /* This is CONSTRAINED UNPREDICTABLE and we choose to fault. */ | ||
153 | - return false; | ||
154 | - } | ||
155 | } else { | ||
156 | - /* AArch32 only supports 4KB pages. Assert on that. */ | ||
157 | + /* | ||
158 | + * Things are simpler for AArch32 EL2, with only 4k pages. | ||
159 | + * There is no separate S2InvalidSL function, but AArch32.S2Walk | ||
160 | + * begins with walkparms.sl0 in {'1x'}. | ||
161 | + */ | ||
162 | assert(stride == 9); | ||
163 | - | ||
164 | - if (level == 0) { | ||
165 | - return false; | ||
166 | + if (sl0 >= 2) { | ||
167 | + goto fail; | ||
168 | } | ||
169 | + startlevel = 2 - sl0; | ||
170 | } | ||
171 | - return true; | ||
172 | + | ||
173 | + /* AArch{64,32}.S2InconsistentSL are functionally equivalent. */ | ||
174 | + levels = 3 - startlevel; | ||
175 | + granulebits = stride + 3; | ||
176 | + | ||
177 | + s1_min_iasize = levels * stride + granulebits + 1; | ||
178 | + s1_max_iasize = s1_min_iasize + (stride - 1) + 4; | ||
179 | + | ||
180 | + if (iasize >= s1_min_iasize && iasize <= s1_max_iasize) { | ||
181 | + return startlevel; | ||
182 | + } | ||
183 | + | ||
184 | + fail: | ||
185 | + return INT_MIN; | ||
186 | } | ||
187 | |||
188 | /** | ||
189 | @@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_lpae(CPUARMState *env, S1Translate *ptw, | ||
190 | */ | ||
191 | level = 4 - (inputsize - 4) / stride; | ||
192 | } else { | ||
193 | - /* | ||
194 | - * For stage 2 translations the starting level is specified by the | ||
195 | - * VTCR_EL2.SL0 field (whose interpretation depends on the page size) | ||
196 | - */ | 193 | - */ |
197 | - uint32_t sl0 = extract32(tcr, 6, 2); | 194 | - assert(!tcg_enabled() || no_aa32 || |
198 | - uint32_t sl2 = extract64(tcr, 33, 1); | 195 | - cpu_isar_feature(aa32_arm_div, cpu)); |
199 | - int32_t startlevel; | 196 | - set_feature(env, ARM_FEATURE_LPAE); |
200 | - bool ok; | 197 | - set_feature(env, ARM_FEATURE_V7); |
201 | - | 198 | - } |
202 | - /* SL2 is RES0 unless DS=1 & 4kb granule. */ | 199 | - if (arm_feature(env, ARM_FEATURE_V7)) { |
203 | - if (param.ds && stride == 9 && sl2) { | 200 | - set_feature(env, ARM_FEATURE_VAPA); |
204 | - if (sl0 != 0) { | 201 | - set_feature(env, ARM_FEATURE_THUMB2); |
205 | - level = 0; | 202 | - set_feature(env, ARM_FEATURE_MPIDR); |
206 | - goto do_translation_fault; | 203 | - if (!arm_feature(env, ARM_FEATURE_M)) { |
207 | - } | 204 | - set_feature(env, ARM_FEATURE_V6K); |
208 | - startlevel = -1; | ||
209 | - } else if (!aarch64 || stride == 9) { | ||
210 | - /* AArch32 or 4KB pages */ | ||
211 | - startlevel = 2 - sl0; | ||
212 | - | ||
213 | - if (cpu_isar_feature(aa64_st, cpu)) { | ||
214 | - startlevel &= 3; | ||
215 | - } | ||
216 | - } else { | 205 | - } else { |
217 | - /* 16KB or 64KB pages */ | 206 | - set_feature(env, ARM_FEATURE_V6); |
218 | - startlevel = 3 - sl0; | ||
219 | - } | 207 | - } |
220 | - | 208 | - |
221 | - /* Check that the starting level is valid. */ | 209 | - /* Always define VBAR for V7 CPUs even if it doesn't exist in |
222 | - ok = check_s2_mmu_setup(cpu, aarch64, startlevel, | 210 | - * non-EL3 configs. This is needed by some legacy boards. |
223 | - inputsize, stride, outputsize); | 211 | - */ |
224 | - if (!ok) { | 212 | - set_feature(env, ARM_FEATURE_VBAR); |
225 | + int startlevel = check_s2_mmu_setup(cpu, aarch64, tcr, param.ds, | 213 | - } |
226 | + inputsize, stride); | 214 | - if (arm_feature(env, ARM_FEATURE_V6K)) { |
227 | + if (startlevel == INT_MIN) { | 215 | - set_feature(env, ARM_FEATURE_V6); |
228 | + level = 0; | 216 | - set_feature(env, ARM_FEATURE_MVFR); |
229 | goto do_translation_fault; | 217 | - } |
230 | } | 218 | - if (arm_feature(env, ARM_FEATURE_V6)) { |
231 | level = startlevel; | 219 | - set_feature(env, ARM_FEATURE_V5); |
220 | - if (!arm_feature(env, ARM_FEATURE_M)) { | ||
221 | - assert(!tcg_enabled() || no_aa32 || | ||
222 | - cpu_isar_feature(aa32_jazelle, cpu)); | ||
223 | - set_feature(env, ARM_FEATURE_AUXCR); | ||
224 | - } | ||
225 | - } | ||
226 | - if (arm_feature(env, ARM_FEATURE_V5)) { | ||
227 | - set_feature(env, ARM_FEATURE_V4T); | ||
228 | - } | ||
229 | - if (arm_feature(env, ARM_FEATURE_LPAE)) { | ||
230 | - set_feature(env, ARM_FEATURE_V7MP); | ||
231 | - } | ||
232 | - if (arm_feature(env, ARM_FEATURE_CBAR_RO)) { | ||
233 | - set_feature(env, ARM_FEATURE_CBAR); | ||
234 | - } | ||
235 | - if (arm_feature(env, ARM_FEATURE_THUMB2) && | ||
236 | - !arm_feature(env, ARM_FEATURE_M)) { | ||
237 | - set_feature(env, ARM_FEATURE_THUMB_DSP); | ||
238 | - } | ||
239 | |||
240 | /* | ||
241 | * We rely on no XScale CPU having VFP so we can use the same bits in the | ||
232 | -- | 242 | -- |
233 | 2.34.1 | 243 | 2.34.1 | diff view generated by jsdifflib |
1 | From: David Reiss <dreiss@meta.com> | 1 | M-profile CPUs generally allow configuration of the number of MPU |
---|---|---|---|
2 | regions that they have. We don't currently model this, so our | ||
3 | implementations of some of the board models provide CPUs with the | ||
4 | wrong number of regions. RTOSes like Zephyr that hardcode the | ||
5 | expected number of regions may therefore not run on the model if they | ||
6 | are set up to run on real hardware. | ||
2 | 7 | ||
3 | Allow the function to be used outside of m_helper.c. | 8 | Add properties mpu-ns-regions and mpu-s-regions to the ARMV7M object, |
4 | Move to be outside of ifndef CONFIG_USER_ONLY block. | 9 | matching the ability of hardware to configure the number of Secure |
5 | Rename from get_v7m_sp_ptr. | 10 | and NonSecure regions separately. Our actual CPU implementation |
11 | doesn't currently support that, and it happens that none of the MPS | ||
12 | boards we model set the number of regions differently for Secure vs | ||
13 | NonSecure, so we provide an interface to the boards and SoCs that | ||
14 | won't need to change if we ever do add that functionality in future, | ||
15 | but make it an error to configure the two properties to different | ||
16 | values. | ||
6 | 17 | ||
7 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | 18 | (The property name on the CPU is the somewhat misnamed-for-M-profile |
19 | "pmsav7-dregion", so we don't follow that naming convention for | ||
20 | the properties here. The TRM doesn't say what the CPU configuration | ||
21 | variable names are, so we pick something, and follow the lowercase | ||
22 | convention we already have for properties here.) | ||
23 | |||
24 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
8 | Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> | 25 | Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> |
9 | Signed-off-by: David Reiss <dreiss@meta.com> | 26 | Message-id: 20230724174335.2150499-3-peter.maydell@linaro.org |
10 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | ||
11 | Message-id: 20230227213329.793795-14-richard.henderson@linaro.org | ||
12 | [rth: Split out of a larger patch] | ||
13 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | ||
14 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
15 | --- | 27 | --- |
16 | target/arm/internals.h | 10 +++++ | 28 | include/hw/arm/armv7m.h | 8 ++++++++ |
17 | target/arm/tcg/m_helper.c | 84 +++++++++++++++++++-------------------- | 29 | hw/arm/armv7m.c | 21 +++++++++++++++++++++ |
18 | 2 files changed, 51 insertions(+), 43 deletions(-) | 30 | 2 files changed, 29 insertions(+) |
19 | 31 | ||
20 | diff --git a/target/arm/internals.h b/target/arm/internals.h | 32 | diff --git a/include/hw/arm/armv7m.h b/include/hw/arm/armv7m.h |
21 | index XXXXXXX..XXXXXXX 100644 | 33 | index XXXXXXX..XXXXXXX 100644 |
22 | --- a/target/arm/internals.h | 34 | --- a/include/hw/arm/armv7m.h |
23 | +++ b/target/arm/internals.h | 35 | +++ b/include/hw/arm/armv7m.h |
24 | @@ -XXX,XX +XXX,XX @@ void arm_cpu_lpa2_finalize(ARMCPU *cpu, Error **errp); | 36 | @@ -XXX,XX +XXX,XX @@ OBJECT_DECLARE_SIMPLE_TYPE(ARMv7MState, ARMV7M) |
25 | /* Read the CONTROL register as the MRS instruction would. */ | 37 | * + Property "vfp": enable VFP (forwarded to CPU object) |
26 | uint32_t arm_v7m_mrs_control(CPUARMState *env, uint32_t secure); | 38 | * + Property "dsp": enable DSP (forwarded to CPU object) |
27 | 39 | * + Property "enable-bitband": expose bitbanded IO | |
28 | +/* | 40 | + * + Property "mpu-ns-regions": number of Non-Secure MPU regions (forwarded |
29 | + * Return a pointer to the location where we currently store the | 41 | + * to CPU object pmsav7-dregion property; default is whatever the default |
30 | + * stack pointer for the requested security state and thread mode. | 42 | + * for the CPU is) |
31 | + * This pointer will become invalid if the CPU state is updated | 43 | + * + Property "mpu-s-regions": number of Secure MPU regions (default is |
32 | + * such that the stack pointers are switched around (eg changing | 44 | + * whatever the default for the CPU is; must currently be set to the same |
33 | + * the SPSEL control bit). | 45 | + * value as mpu-ns-regions if the CPU implements the Security Extension) |
34 | + */ | 46 | * + Clock input "refclk" is the external reference clock for the systick timers |
35 | +uint32_t *arm_v7m_get_sp_ptr(CPUARMState *env, bool secure, | 47 | * + Clock input "cpuclk" is the main CPU clock |
36 | + bool threadmode, bool spsel); | 48 | */ |
37 | + | 49 | @@ -XXX,XX +XXX,XX @@ struct ARMv7MState { |
38 | #ifdef CONFIG_USER_ONLY | 50 | Object *idau; |
39 | static inline void define_cortex_a72_a57_a53_cp_reginfo(ARMCPU *cpu) { } | 51 | uint32_t init_svtor; |
40 | #else | 52 | uint32_t init_nsvtor; |
41 | diff --git a/target/arm/tcg/m_helper.c b/target/arm/tcg/m_helper.c | 53 | + uint32_t mpu_ns_regions; |
54 | + uint32_t mpu_s_regions; | ||
55 | bool enable_bitband; | ||
56 | bool start_powered_off; | ||
57 | bool vfp; | ||
58 | diff --git a/hw/arm/armv7m.c b/hw/arm/armv7m.c | ||
42 | index XXXXXXX..XXXXXXX 100644 | 59 | index XXXXXXX..XXXXXXX 100644 |
43 | --- a/target/arm/tcg/m_helper.c | 60 | --- a/hw/arm/armv7m.c |
44 | +++ b/target/arm/tcg/m_helper.c | 61 | +++ b/hw/arm/armv7m.c |
45 | @@ -XXX,XX +XXX,XX @@ void HELPER(v7m_blxns)(CPUARMState *env, uint32_t dest) | 62 | @@ -XXX,XX +XXX,XX @@ static void armv7m_realize(DeviceState *dev, Error **errp) |
46 | arm_rebuild_hflags(env); | 63 | } |
47 | } | 64 | } |
48 | 65 | ||
49 | -static uint32_t *get_v7m_sp_ptr(CPUARMState *env, bool secure, bool threadmode, | ||
50 | - bool spsel) | ||
51 | -{ | ||
52 | - /* | ||
53 | - * Return a pointer to the location where we currently store the | ||
54 | - * stack pointer for the requested security state and thread mode. | ||
55 | - * This pointer will become invalid if the CPU state is updated | ||
56 | - * such that the stack pointers are switched around (eg changing | ||
57 | - * the SPSEL control bit). | ||
58 | - * Compare the v8M ARM ARM pseudocode LookUpSP_with_security_mode(). | ||
59 | - * Unlike that pseudocode, we require the caller to pass us in the | ||
60 | - * SPSEL control bit value; this is because we also use this | ||
61 | - * function in handling of pushing of the callee-saves registers | ||
62 | - * part of the v8M stack frame (pseudocode PushCalleeStack()), | ||
63 | - * and in the tailchain codepath the SPSEL bit comes from the exception | ||
64 | - * return magic LR value from the previous exception. The pseudocode | ||
65 | - * opencodes the stack-selection in PushCalleeStack(), but we prefer | ||
66 | - * to make this utility function generic enough to do the job. | ||
67 | - */ | ||
68 | - bool want_psp = threadmode && spsel; | ||
69 | - | ||
70 | - if (secure == env->v7m.secure) { | ||
71 | - if (want_psp == v7m_using_psp(env)) { | ||
72 | - return &env->regs[13]; | ||
73 | - } else { | ||
74 | - return &env->v7m.other_sp; | ||
75 | - } | ||
76 | - } else { | ||
77 | - if (want_psp) { | ||
78 | - return &env->v7m.other_ss_psp; | ||
79 | - } else { | ||
80 | - return &env->v7m.other_ss_msp; | ||
81 | - } | ||
82 | - } | ||
83 | -} | ||
84 | - | ||
85 | static bool arm_v7m_load_vector(ARMCPU *cpu, int exc, bool targets_secure, | ||
86 | uint32_t *pvec) | ||
87 | { | ||
88 | @@ -XXX,XX +XXX,XX @@ static bool v7m_push_callee_stack(ARMCPU *cpu, uint32_t lr, bool dotailchain, | ||
89 | !mode; | ||
90 | |||
91 | mmu_idx = arm_v7m_mmu_idx_for_secstate_and_priv(env, M_REG_S, priv); | ||
92 | - frame_sp_p = get_v7m_sp_ptr(env, M_REG_S, mode, | ||
93 | - lr & R_V7M_EXCRET_SPSEL_MASK); | ||
94 | + frame_sp_p = arm_v7m_get_sp_ptr(env, M_REG_S, mode, | ||
95 | + lr & R_V7M_EXCRET_SPSEL_MASK); | ||
96 | want_psp = mode && (lr & R_V7M_EXCRET_SPSEL_MASK); | ||
97 | if (want_psp) { | ||
98 | limit = env->v7m.psplim[M_REG_S]; | ||
99 | @@ -XXX,XX +XXX,XX @@ static void do_v7m_exception_exit(ARMCPU *cpu) | ||
100 | * use 'frame_sp_p' after we do something that makes it invalid. | ||
101 | */ | ||
102 | bool spsel = env->v7m.control[return_to_secure] & R_V7M_CONTROL_SPSEL_MASK; | ||
103 | - uint32_t *frame_sp_p = get_v7m_sp_ptr(env, | ||
104 | - return_to_secure, | ||
105 | - !return_to_handler, | ||
106 | - spsel); | ||
107 | + uint32_t *frame_sp_p = arm_v7m_get_sp_ptr(env, return_to_secure, | ||
108 | + !return_to_handler, spsel); | ||
109 | uint32_t frameptr = *frame_sp_p; | ||
110 | bool pop_ok = true; | ||
111 | ARMMMUIdx mmu_idx; | ||
112 | @@ -XXX,XX +XXX,XX @@ static bool do_v7m_function_return(ARMCPU *cpu) | ||
113 | threadmode = !arm_v7m_is_handler_mode(env); | ||
114 | spsel = env->v7m.control[M_REG_S] & R_V7M_CONTROL_SPSEL_MASK; | ||
115 | |||
116 | - frame_sp_p = get_v7m_sp_ptr(env, true, threadmode, spsel); | ||
117 | + frame_sp_p = arm_v7m_get_sp_ptr(env, true, threadmode, spsel); | ||
118 | frameptr = *frame_sp_p; | ||
119 | |||
120 | /* | ||
121 | @@ -XXX,XX +XXX,XX @@ uint32_t HELPER(v7m_tt)(CPUARMState *env, uint32_t addr, uint32_t op) | ||
122 | } | ||
123 | |||
124 | #endif /* !CONFIG_USER_ONLY */ | ||
125 | + | ||
126 | +uint32_t *arm_v7m_get_sp_ptr(CPUARMState *env, bool secure, bool threadmode, | ||
127 | + bool spsel) | ||
128 | +{ | ||
129 | + /* | 66 | + /* |
130 | + * Return a pointer to the location where we currently store the | 67 | + * Real M-profile hardware can be configured with a different number of |
131 | + * stack pointer for the requested security state and thread mode. | 68 | + * MPU regions for Secure vs NonSecure. QEMU's CPU implementation doesn't |
132 | + * This pointer will become invalid if the CPU state is updated | 69 | + * support that yet, so catch attempts to select that. |
133 | + * such that the stack pointers are switched around (eg changing | ||
134 | + * the SPSEL control bit). | ||
135 | + * Compare the v8M ARM ARM pseudocode LookUpSP_with_security_mode(). | ||
136 | + * Unlike that pseudocode, we require the caller to pass us in the | ||
137 | + * SPSEL control bit value; this is because we also use this | ||
138 | + * function in handling of pushing of the callee-saves registers | ||
139 | + * part of the v8M stack frame (pseudocode PushCalleeStack()), | ||
140 | + * and in the tailchain codepath the SPSEL bit comes from the exception | ||
141 | + * return magic LR value from the previous exception. The pseudocode | ||
142 | + * opencodes the stack-selection in PushCalleeStack(), but we prefer | ||
143 | + * to make this utility function generic enough to do the job. | ||
144 | + */ | 70 | + */ |
145 | + bool want_psp = threadmode && spsel; | 71 | + if (arm_feature(&s->cpu->env, ARM_FEATURE_M_SECURITY) && |
146 | + | 72 | + s->mpu_ns_regions != s->mpu_s_regions) { |
147 | + if (secure == env->v7m.secure) { | 73 | + error_setg(errp, |
148 | + if (want_psp == v7m_using_psp(env)) { | 74 | + "mpu-ns-regions and mpu-s-regions properties must have the same value"); |
149 | + return &env->regs[13]; | 75 | + return; |
150 | + } else { | 76 | + } |
151 | + return &env->v7m.other_sp; | 77 | + if (s->mpu_ns_regions != UINT_MAX && |
152 | + } | 78 | + object_property_find(OBJECT(s->cpu), "pmsav7-dregion")) { |
153 | + } else { | 79 | + if (!object_property_set_uint(OBJECT(s->cpu), "pmsav7-dregion", |
154 | + if (want_psp) { | 80 | + s->mpu_ns_regions, errp)) { |
155 | + return &env->v7m.other_ss_psp; | 81 | + return; |
156 | + } else { | ||
157 | + return &env->v7m.other_ss_msp; | ||
158 | + } | 82 | + } |
159 | + } | 83 | + } |
160 | +} | 84 | + |
85 | /* | ||
86 | * Tell the CPU where the NVIC is; it will fail realize if it doesn't | ||
87 | * have one. Similarly, tell the NVIC where its CPU is. | ||
88 | @@ -XXX,XX +XXX,XX @@ static Property armv7m_properties[] = { | ||
89 | false), | ||
90 | DEFINE_PROP_BOOL("vfp", ARMv7MState, vfp, true), | ||
91 | DEFINE_PROP_BOOL("dsp", ARMv7MState, dsp, true), | ||
92 | + DEFINE_PROP_UINT32("mpu-ns-regions", ARMv7MState, mpu_ns_regions, UINT_MAX), | ||
93 | + DEFINE_PROP_UINT32("mpu-s-regions", ARMv7MState, mpu_s_regions, UINT_MAX), | ||
94 | DEFINE_PROP_END_OF_LIST(), | ||
95 | }; | ||
96 | |||
161 | -- | 97 | -- |
162 | 2.34.1 | 98 | 2.34.1 |
163 | 99 | ||
164 | 100 | diff view generated by jsdifflib |
1 | From: David Reiss <dreiss@meta.com> | 1 | The IoTKit, SSE200 and SSE300 all default to 8 MPU regions. The |
---|---|---|---|
2 | 2 | MPS2/MPS3 FPGA images don't override these except in the case of | |
3 | Allow the function to be used outside of m_helper.c. | 3 | AN547, which uses 16 MPU regions. |
4 | Rename with an "arm_" prefix. | 4 | |
5 | 5 | Define properties on the ARMSSE object for the MPU regions (using the | |
6 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | 6 | same names as the documented RTL configuration settings, and |
7 | following the pattern we already have for this device of using | ||
8 | all-caps names as the RTL does), and set them in the board code. | ||
9 | |||
10 | We don't actually need to override the default except on AN547, | ||
11 | but it's simpler code to have the board code set them always | ||
12 | rather than tracking which board subtypes want to set them to | ||
13 | a non-default value separately from what that value is. | ||
14 | |||
15 | Tho overall effect is that for mps2-an505, mps2-an521 and mps3-an524 | ||
16 | we now correctly use 8 MPU regions, while mps3-an547 stays at its | ||
17 | current 16 regions. | ||
18 | |||
19 | It's possible some guest code wrongly depended on the previous | ||
20 | incorrectly modeled number of memory regions. (Such guest code | ||
21 | should ideally check the number of regions via the MPU_TYPE | ||
22 | register.) The old behaviour can be obtained with additional | ||
23 | -global arguments to QEMU: | ||
24 | |||
25 | For mps2-an521 and mps2-an524: | ||
26 | -global sse-200.CPU0_MPU_NS=16 -global sse-200.CPU0_MPU_S=16 -global sse-200.CPU1_MPU_NS=16 -global sse-200.CPU1_MPU_S=16 | ||
27 | |||
28 | For mps2-an505: | ||
29 | -global sse-200.CPU0_MPU_NS=16 -global sse-200.CPU0_MPU_S=16 | ||
30 | |||
31 | NB that the way the implementation allows this use of -global | ||
32 | is slightly fragile: if the board code explicitly sets the | ||
33 | properties on the sse-200 object, this overrides the -global | ||
34 | command line option. So we rely on: | ||
35 | - the boards that need fixing all happen to use the SSE defaults | ||
36 | - we can write the board code to only set the property if it | ||
37 | is different from the default, rather than having all boards | ||
38 | explicitly set the property | ||
39 | - the board that does need to use a non-default value happens | ||
40 | to need to set it to the same value (16) we previously used | ||
41 | This works, but there are some kinds of refactoring of the | ||
42 | mps2-tz.c code that would break the support for -global here. | ||
43 | |||
44 | Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1772 | ||
45 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
46 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
7 | Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> | 47 | Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> |
8 | Signed-off-by: David Reiss <dreiss@meta.com> | 48 | Message-id: 20230724174335.2150499-4-peter.maydell@linaro.org |
9 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | ||
10 | Message-id: 20230227213329.793795-13-richard.henderson@linaro.org | ||
11 | [rth: Split out of a larger patch] | ||
12 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | ||
13 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
14 | --- | 49 | --- |
15 | target/arm/internals.h | 3 +++ | 50 | include/hw/arm/armsse.h | 5 +++++ |
16 | target/arm/tcg/m_helper.c | 6 +++--- | 51 | hw/arm/armsse.c | 16 ++++++++++++++++ |
17 | 2 files changed, 6 insertions(+), 3 deletions(-) | 52 | hw/arm/mps2-tz.c | 29 +++++++++++++++++++++++++++++ |
18 | 53 | 3 files changed, 50 insertions(+) | |
19 | diff --git a/target/arm/internals.h b/target/arm/internals.h | 54 | |
55 | diff --git a/include/hw/arm/armsse.h b/include/hw/arm/armsse.h | ||
20 | index XXXXXXX..XXXXXXX 100644 | 56 | index XXXXXXX..XXXXXXX 100644 |
21 | --- a/target/arm/internals.h | 57 | --- a/include/hw/arm/armsse.h |
22 | +++ b/target/arm/internals.h | 58 | +++ b/include/hw/arm/armsse.h |
23 | @@ -XXX,XX +XXX,XX @@ void arm_cpu_pauth_finalize(ARMCPU *cpu, Error **errp); | 59 | @@ -XXX,XX +XXX,XX @@ |
24 | void arm_cpu_lpa2_finalize(ARMCPU *cpu, Error **errp); | 60 | * (matching the hardware) is that for CPU0 in an IoTKit and CPU1 in an |
61 | * SSE-200 both are present; CPU0 in an SSE-200 has neither. | ||
62 | * Since the IoTKit has only one CPU, it does not have the CPU1_* properties. | ||
63 | + * + QOM properties "CPU0_MPU_NS", "CPU0_MPU_S", "CPU1_MPU_NS" and "CPU1_MPU_S" | ||
64 | + * which set the number of MPU regions on the CPUs. If there is only one | ||
65 | + * CPU the CPU1 properties are not present. | ||
66 | * + Named GPIO inputs "EXP_IRQ" 0..n are the expansion interrupts for CPU 0, | ||
67 | * which are wired to its NVIC lines 32 .. n+32 | ||
68 | * + Named GPIO inputs "EXP_CPU1_IRQ" 0..n are the expansion interrupts for | ||
69 | @@ -XXX,XX +XXX,XX @@ struct ARMSSE { | ||
70 | uint32_t exp_numirq; | ||
71 | uint32_t sram_addr_width; | ||
72 | uint32_t init_svtor; | ||
73 | + uint32_t cpu_mpu_ns[SSE_MAX_CPUS]; | ||
74 | + uint32_t cpu_mpu_s[SSE_MAX_CPUS]; | ||
75 | bool cpu_fpu[SSE_MAX_CPUS]; | ||
76 | bool cpu_dsp[SSE_MAX_CPUS]; | ||
77 | }; | ||
78 | diff --git a/hw/arm/armsse.c b/hw/arm/armsse.c | ||
79 | index XXXXXXX..XXXXXXX 100644 | ||
80 | --- a/hw/arm/armsse.c | ||
81 | +++ b/hw/arm/armsse.c | ||
82 | @@ -XXX,XX +XXX,XX @@ static Property iotkit_properties[] = { | ||
83 | DEFINE_PROP_UINT32("init-svtor", ARMSSE, init_svtor, 0x10000000), | ||
84 | DEFINE_PROP_BOOL("CPU0_FPU", ARMSSE, cpu_fpu[0], true), | ||
85 | DEFINE_PROP_BOOL("CPU0_DSP", ARMSSE, cpu_dsp[0], true), | ||
86 | + DEFINE_PROP_UINT32("CPU0_MPU_NS", ARMSSE, cpu_mpu_ns[0], 8), | ||
87 | + DEFINE_PROP_UINT32("CPU0_MPU_S", ARMSSE, cpu_mpu_s[0], 8), | ||
88 | DEFINE_PROP_END_OF_LIST() | ||
89 | }; | ||
90 | |||
91 | @@ -XXX,XX +XXX,XX @@ static Property sse200_properties[] = { | ||
92 | DEFINE_PROP_BOOL("CPU0_DSP", ARMSSE, cpu_dsp[0], false), | ||
93 | DEFINE_PROP_BOOL("CPU1_FPU", ARMSSE, cpu_fpu[1], true), | ||
94 | DEFINE_PROP_BOOL("CPU1_DSP", ARMSSE, cpu_dsp[1], true), | ||
95 | + DEFINE_PROP_UINT32("CPU0_MPU_NS", ARMSSE, cpu_mpu_ns[0], 8), | ||
96 | + DEFINE_PROP_UINT32("CPU0_MPU_S", ARMSSE, cpu_mpu_s[0], 8), | ||
97 | + DEFINE_PROP_UINT32("CPU1_MPU_NS", ARMSSE, cpu_mpu_ns[1], 8), | ||
98 | + DEFINE_PROP_UINT32("CPU1_MPU_S", ARMSSE, cpu_mpu_s[1], 8), | ||
99 | DEFINE_PROP_END_OF_LIST() | ||
100 | }; | ||
101 | |||
102 | @@ -XXX,XX +XXX,XX @@ static Property sse300_properties[] = { | ||
103 | DEFINE_PROP_UINT32("init-svtor", ARMSSE, init_svtor, 0x10000000), | ||
104 | DEFINE_PROP_BOOL("CPU0_FPU", ARMSSE, cpu_fpu[0], true), | ||
105 | DEFINE_PROP_BOOL("CPU0_DSP", ARMSSE, cpu_dsp[0], true), | ||
106 | + DEFINE_PROP_UINT32("CPU0_MPU_NS", ARMSSE, cpu_mpu_ns[0], 8), | ||
107 | + DEFINE_PROP_UINT32("CPU0_MPU_S", ARMSSE, cpu_mpu_s[0], 8), | ||
108 | DEFINE_PROP_END_OF_LIST() | ||
109 | }; | ||
110 | |||
111 | @@ -XXX,XX +XXX,XX @@ static void armsse_realize(DeviceState *dev, Error **errp) | ||
112 | return; | ||
113 | } | ||
114 | } | ||
115 | + if (!object_property_set_uint(cpuobj, "mpu-ns-regions", | ||
116 | + s->cpu_mpu_ns[i], errp)) { | ||
117 | + return; | ||
118 | + } | ||
119 | + if (!object_property_set_uint(cpuobj, "mpu-s-regions", | ||
120 | + s->cpu_mpu_s[i], errp)) { | ||
121 | + return; | ||
122 | + } | ||
123 | |||
124 | if (i > 0) { | ||
125 | memory_region_add_subregion_overlap(&s->cpu_container[i], 0, | ||
126 | diff --git a/hw/arm/mps2-tz.c b/hw/arm/mps2-tz.c | ||
127 | index XXXXXXX..XXXXXXX 100644 | ||
128 | --- a/hw/arm/mps2-tz.c | ||
129 | +++ b/hw/arm/mps2-tz.c | ||
130 | @@ -XXX,XX +XXX,XX @@ struct MPS2TZMachineClass { | ||
131 | int uart_overflow_irq; /* number of the combined UART overflow IRQ */ | ||
132 | uint32_t init_svtor; /* init-svtor setting for SSE */ | ||
133 | uint32_t sram_addr_width; /* SRAM_ADDR_WIDTH setting for SSE */ | ||
134 | + uint32_t cpu0_mpu_ns; /* CPU0_MPU_NS setting for SSE */ | ||
135 | + uint32_t cpu0_mpu_s; /* CPU0_MPU_S setting for SSE */ | ||
136 | + uint32_t cpu1_mpu_ns; /* CPU1_MPU_NS setting for SSE */ | ||
137 | + uint32_t cpu1_mpu_s; /* CPU1_MPU_S setting for SSE */ | ||
138 | const RAMInfo *raminfo; | ||
139 | const char *armsse_type; | ||
140 | uint32_t boot_ram_size; /* size of ram at address 0; 0 == find in raminfo */ | ||
141 | @@ -XXX,XX +XXX,XX @@ OBJECT_DECLARE_TYPE(MPS2TZMachineState, MPS2TZMachineClass, MPS2TZ_MACHINE) | ||
142 | #define MPS3_DDR_SIZE (2 * GiB) | ||
25 | #endif | 143 | #endif |
26 | 144 | ||
27 | +/* Read the CONTROL register as the MRS instruction would. */ | 145 | +/* For cpu{0,1}_mpu_{ns,s}, means "leave at SSE's default value" */ |
28 | +uint32_t arm_v7m_mrs_control(CPUARMState *env, uint32_t secure); | 146 | +#define MPU_REGION_DEFAULT UINT32_MAX |
29 | + | 147 | + |
30 | #ifdef CONFIG_USER_ONLY | 148 | static const uint32_t an505_oscclk[] = { |
31 | static inline void define_cortex_a72_a57_a53_cp_reginfo(ARMCPU *cpu) { } | 149 | 40000000, |
32 | #else | 150 | 24580000, |
33 | diff --git a/target/arm/tcg/m_helper.c b/target/arm/tcg/m_helper.c | 151 | @@ -XXX,XX +XXX,XX @@ static void mps2tz_common_init(MachineState *machine) |
34 | index XXXXXXX..XXXXXXX 100644 | 152 | OBJECT(system_memory), &error_abort); |
35 | --- a/target/arm/tcg/m_helper.c | 153 | qdev_prop_set_uint32(iotkitdev, "EXP_NUMIRQ", mmc->numirq); |
36 | +++ b/target/arm/tcg/m_helper.c | 154 | qdev_prop_set_uint32(iotkitdev, "init-svtor", mmc->init_svtor); |
37 | @@ -XXX,XX +XXX,XX @@ static uint32_t v7m_mrs_xpsr(CPUARMState *env, uint32_t reg, unsigned el) | 155 | + if (mmc->cpu0_mpu_ns != MPU_REGION_DEFAULT) { |
38 | return xpsr_read(env) & mask; | 156 | + qdev_prop_set_uint32(iotkitdev, "CPU0_MPU_NS", mmc->cpu0_mpu_ns); |
157 | + } | ||
158 | + if (mmc->cpu0_mpu_s != MPU_REGION_DEFAULT) { | ||
159 | + qdev_prop_set_uint32(iotkitdev, "CPU0_MPU_S", mmc->cpu0_mpu_s); | ||
160 | + } | ||
161 | + if (object_property_find(OBJECT(iotkitdev), "CPU1_MPU_NS")) { | ||
162 | + if (mmc->cpu1_mpu_ns != MPU_REGION_DEFAULT) { | ||
163 | + qdev_prop_set_uint32(iotkitdev, "CPU1_MPU_NS", mmc->cpu1_mpu_ns); | ||
164 | + } | ||
165 | + if (mmc->cpu1_mpu_s != MPU_REGION_DEFAULT) { | ||
166 | + qdev_prop_set_uint32(iotkitdev, "CPU1_MPU_S", mmc->cpu1_mpu_s); | ||
167 | + } | ||
168 | + } | ||
169 | qdev_prop_set_uint32(iotkitdev, "SRAM_ADDR_WIDTH", mmc->sram_addr_width); | ||
170 | qdev_connect_clock_in(iotkitdev, "MAINCLK", mms->sysclk); | ||
171 | qdev_connect_clock_in(iotkitdev, "S32KCLK", mms->s32kclk); | ||
172 | @@ -XXX,XX +XXX,XX @@ static void mps2tz_class_init(ObjectClass *oc, void *data) | ||
173 | { | ||
174 | MachineClass *mc = MACHINE_CLASS(oc); | ||
175 | IDAUInterfaceClass *iic = IDAU_INTERFACE_CLASS(oc); | ||
176 | + MPS2TZMachineClass *mmc = MPS2TZ_MACHINE_CLASS(oc); | ||
177 | |||
178 | mc->init = mps2tz_common_init; | ||
179 | mc->reset = mps2_machine_reset; | ||
180 | iic->check = mps2_tz_idau_check; | ||
181 | + | ||
182 | + /* Most machines leave these at the SSE defaults */ | ||
183 | + mmc->cpu0_mpu_ns = MPU_REGION_DEFAULT; | ||
184 | + mmc->cpu0_mpu_s = MPU_REGION_DEFAULT; | ||
185 | + mmc->cpu1_mpu_ns = MPU_REGION_DEFAULT; | ||
186 | + mmc->cpu1_mpu_s = MPU_REGION_DEFAULT; | ||
39 | } | 187 | } |
40 | 188 | ||
41 | -static uint32_t v7m_mrs_control(CPUARMState *env, uint32_t secure) | 189 | static void mps2tz_set_default_ram_info(MPS2TZMachineClass *mmc) |
42 | +uint32_t arm_v7m_mrs_control(CPUARMState *env, uint32_t secure) | 190 | @@ -XXX,XX +XXX,XX @@ static void mps3tz_an547_class_init(ObjectClass *oc, void *data) |
43 | { | 191 | mmc->numirq = 96; |
44 | uint32_t value = env->v7m.control[secure]; | 192 | mmc->uart_overflow_irq = 48; |
45 | 193 | mmc->init_svtor = 0x00000000; | |
46 | @@ -XXX,XX +XXX,XX @@ uint32_t HELPER(v7m_mrs)(CPUARMState *env, uint32_t reg) | 194 | + mmc->cpu0_mpu_s = mmc->cpu0_mpu_ns = 16; |
47 | case 0 ... 7: /* xPSR sub-fields */ | 195 | mmc->sram_addr_width = 21; |
48 | return v7m_mrs_xpsr(env, reg, 0); | 196 | mmc->raminfo = an547_raminfo; |
49 | case 20: /* CONTROL */ | 197 | mmc->armsse_type = TYPE_SSE300; |
50 | - return v7m_mrs_control(env, 0); | ||
51 | + return arm_v7m_mrs_control(env, 0); | ||
52 | default: | ||
53 | /* Unprivileged reads others as zero. */ | ||
54 | return 0; | ||
55 | @@ -XXX,XX +XXX,XX @@ uint32_t HELPER(v7m_mrs)(CPUARMState *env, uint32_t reg) | ||
56 | case 0 ... 7: /* xPSR sub-fields */ | ||
57 | return v7m_mrs_xpsr(env, reg, el); | ||
58 | case 20: /* CONTROL */ | ||
59 | - return v7m_mrs_control(env, env->v7m.secure); | ||
60 | + return arm_v7m_mrs_control(env, env->v7m.secure); | ||
61 | case 0x94: /* CONTROL_NS */ | ||
62 | /* | ||
63 | * We have to handle this here because unprivileged Secure code | ||
64 | -- | 198 | -- |
65 | 2.34.1 | 199 | 2.34.1 |
66 | 200 | ||
67 | 201 | diff view generated by jsdifflib |