Currently a Risc-V platform cannot realizes multiple CPUs with non contiguous
hart IDs because the APLIC, IMSIC and ACLINT emulation code uses the
contiguous logical CPU ID to fetch per CPU state.

This patchset implements cpu_by_arch_id for Risc-V to get the CPU state
by hart ID which may be sparse instead of the contigous logical CPU id.

Mayuresh Chitale (2):
  target/riscv: cpu: Implement get_arch_id callback
  hw: intc: Use cpu_by_arch_id to fetch CPU state

 hw/intc/riscv_aclint.c | 16 ++++++++--------
 hw/intc/riscv_aplic.c  |  4 ++--
 hw/intc/riscv_imsic.c  |  6 +++---
 target/riscv/cpu.c     |  8 ++++++++
 4 files changed, 21 insertions(+), 13 deletions(-)

-- 
2.34.1

On Thu, 02 Mar 2023 22:50:53 PST (-0800), mchitale@ventanamicro.com wrote:
> Currently a Risc-V platform cannot realizes multiple CPUs with non contiguous
> hart IDs because the APLIC, IMSIC and ACLINT emulation code uses the
> contiguous logical CPU ID to fetch per CPU state.
>
> This patchset implements cpu_by_arch_id for Risc-V to get the CPU state
> by hart ID which may be sparse instead of the contigous logical CPU id.
>
> Mayuresh Chitale (2):
>   target/riscv: cpu: Implement get_arch_id callback
>   hw: intc: Use cpu_by_arch_id to fetch CPU state
>
>  hw/intc/riscv_aclint.c | 16 ++++++++--------
>  hw/intc/riscv_aplic.c  |  4 ++--
>  hw/intc/riscv_imsic.c  |  6 +++---
>  target/riscv/cpu.c     |  8 ++++++++
>  4 files changed, 21 insertions(+), 13 deletions(-)

Thanks, these are queue up on riscv-to-apply.next.