From nobody Tue May 7 19:18:05 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1677826369; cv=none; d=zohomail.com; s=zohoarc; b=RLc+VBu7vdGgl29zxagkIxrCIWTWiFUojEjdn3fIr+uZPxZ7zOMbcNiOePoK14SLjRWQbwDZ8W/W8qu2TA1oamINSOy+yLbN/0gDrQbY9FajYG0XHbDhwipDvKSDAQ9pnziLmNW02znSE/FWI1eCzZnExuqmUvRn04Tk+eyppkU= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1677826369; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=sgOOI7JfbiaxIsYqyFar1QsOwyv72kWWDEfoe6yhldw=; b=JofKnyYUS8Xbfvl7KvcODl8c8avIihXZ2Tjrf6gb9eCGPPN+zgsGG2OpTepsA+OVZCJxniWVvGQyAQkdr4dxv0j9F9hjoC3PKVgQG/82nlpscR05hJfFDrHwcemOjZQINvw/6xBAlmldzc+CgwWc/X18UTw1pLEjwfZdJXZPlRQ= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1677826368985498.72214137938624; Thu, 2 Mar 2023 22:52:48 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pXzGA-00030j-H8; Fri, 03 Mar 2023 01:51:18 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pXzG4-0002zQ-FA for qemu-devel@nongnu.org; Fri, 03 Mar 2023 01:51:13 -0500 Received: from mail-oa1-x2e.google.com ([2001:4860:4864:20::2e]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pXzG1-0001yU-4P for qemu-devel@nongnu.org; Fri, 03 Mar 2023 01:51:12 -0500 Received: by mail-oa1-x2e.google.com with SMTP id 586e51a60fabf-1720433ba75so2005926fac.5 for ; Thu, 02 Mar 2023 22:51:07 -0800 (PST) Received: from mchitale-vm.. ([103.97.165.210]) by smtp.googlemail.com with ESMTPSA id t4-20020a056870e74400b0017293fa734asm675414oak.48.2023.03.02.22.51.03 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 02 Mar 2023 22:51:05 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1677826266; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=sgOOI7JfbiaxIsYqyFar1QsOwyv72kWWDEfoe6yhldw=; b=pLnjIhSZA0+gfcKA6DQSFRY595IFkQ8gG/O50ZmohHMR5Mog7B0BEZaq+2XrqmyIW5 ciVBvssHub9ZDeLUyOKVM97b6kg4/kj5v976v8+F5o0x30xu18Ya5YiDXwkz0YvJZMJI /DOeS2ohDq+lssG6P5rBm0pjNmu+vZfjzpfqfH57JnZ755XXpZNWkyHeArLWciQm1suB DmuOK1KqGUU+jOQ4GBDRMUvZ043RtarAO3Qu+cIjT6FcXj6/BFCS5xwsYc1fjhiJYKu2 el19/VZVRwJhcYZ7qNV9iP8giPlbk7nzykfx2GlyDKcQcNcoESFKlN1jwb9/nlr/4FK6 pCkw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1677826266; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=sgOOI7JfbiaxIsYqyFar1QsOwyv72kWWDEfoe6yhldw=; b=CaeoSMtdh7mPgB5F3MaTJakHJrNfCwM5NBdHXRkqaPZIiymwsmc6lCCGINilxMo5se F4EKe06vWP3nsL9rkECSahba0Rvs5PRDz5gi+STcwJdFY7aAlfF1ElmJBdCSYd5E6V1h 10jaE5fR9vimFq4pOdfyOfXw1URVNdAqn8gElahREoYCIx9hgswmWzoIblgkS00hj3Ui n9KgdCLYuCP8qI/cj1C8og07wmUNpWGtU6icao9a+w7s70743AXTqplMuycpFYioiqG1 J00GIk8NlmUNR3PuvecvOG6zwrQH8kYS7bEnf2SdBwKRmJsj0zXoRDMX8Duo45ADG+VH a+pg== X-Gm-Message-State: AO0yUKUe4ZafHnSeAeXVT60iECfPq2ioDjaDMqP9vph+TS3IqzKS/xZe jfY3324ugHKQOeR9lyimzzIbZalgIqMhnQJHxQ0= X-Google-Smtp-Source: AK7set+jnO+0EBZ+z30zj2mkbRaHh9mCH9X/TipVhClMQbr24O2R4gMnSTqS2XGaerLITswYu2yClA== X-Received: by 2002:a05:6870:b61b:b0:172:3d65:2e2f with SMTP id cm27-20020a056870b61b00b001723d652e2fmr545067oab.14.1677826266111; Thu, 02 Mar 2023 22:51:06 -0800 (PST) From: Mayuresh Chitale To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Cc: Mayuresh Chitale , alistair.francis@wdc.com, Anup Patel Subject: [PATCH 1/2] target/riscv: cpu: Implement get_arch_id callback Date: Fri, 3 Mar 2023 12:20:54 +0530 Message-Id: <20230303065055.915652-2-mchitale@ventanamicro.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230303065055.915652-1-mchitale@ventanamicro.com> References: <20230303065055.915652-1-mchitale@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2001:4860:4864:20::2e; envelope-from=mchitale@ventanamicro.com; helo=mail-oa1-x2e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ventanamicro.com) X-ZM-MESSAGEID: 1677826371064100011 Content-Type: text/plain; charset="utf-8" Implement the callback for getting the architecture-dependent CPU ID ie mhartid. Signed-off-by: Mayuresh Chitale Signed-off-by: Anup Patel Reviewed-by: Daniel Henrique Barboza --- target/riscv/cpu.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 0dd2f0c753..467d8467a3 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -1243,6 +1243,13 @@ static const char *riscv_gdb_get_dynamic_xml(CPUStat= e *cs, const char *xmlname) } =20 #ifndef CONFIG_USER_ONLY +static int64_t riscv_get_arch_id(CPUState *cs) +{ + RISCVCPU *cpu =3D RISCV_CPU(cs); + + return cpu->env.mhartid; +} + #include "hw/core/sysemu-cpu-ops.h" =20 static const struct SysemuCPUOps riscv_sysemu_ops =3D { @@ -1297,6 +1304,7 @@ static void riscv_cpu_class_init(ObjectClass *c, void= *data) cc->disas_set_info =3D riscv_cpu_disas_set_info; #ifndef CONFIG_USER_ONLY cc->sysemu_ops =3D &riscv_sysemu_ops; + cc->get_arch_id =3D riscv_get_arch_id; #endif cc->gdb_arch_name =3D riscv_gdb_arch_name; cc->gdb_get_dynamic_xml =3D riscv_gdb_get_dynamic_xml; --=20 2.34.1 From nobody Tue May 7 19:18:05 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1677826368; cv=none; d=zohomail.com; s=zohoarc; b=PwZ4DDC/r/eCwP3YIPTtEOfqK3I6p7kBMfrZ/hsN7JcnZJYTRqSGeKFrOwRwKV14Apa61484/qgUKJaZ/iL7hrPf3nr7ByOjvx3WmeHxB8o1k7NxLKNj9+L4X0A//OlDdEz80WzMHHS/UGDjsUcWeBa0KVCrbVVwNstybO2M1tY= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1677826368; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=lZQ2ngJ4sFZYmlYtgi8mO9F5kyakeh7gT4w82Q7qixg=; b=LIsmpkThdFr3UuGdvVWIfbb4HXlb2sjuV4+NPRzEGtvw+yyqzEZ62aAt1nmdKY2/khs3LvTW6iGtaCdjDld/bDDfZPxIbuMLFjcQJ39Hdxzz0uHgZQQvlJ6aCwJJigEiZVgHPgbEbW0fOars9OkbBIUOzqGbXrEzvbXqZPcfV9M= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1677826368134132.28501505246197; Thu, 2 Mar 2023 22:52:48 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pXzGP-00032P-Fn; Fri, 03 Mar 2023 01:51:35 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pXzG4-0002zO-5b for qemu-devel@nongnu.org; Fri, 03 Mar 2023 01:51:13 -0500 Received: from mail-oa1-x2d.google.com ([2001:4860:4864:20::2d]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pXzG2-0001yH-2A for qemu-devel@nongnu.org; Fri, 03 Mar 2023 01:51:11 -0500 Received: by mail-oa1-x2d.google.com with SMTP id 586e51a60fabf-173435e0ec4so1950056fac.12 for ; Thu, 02 Mar 2023 22:51:09 -0800 (PST) Received: from mchitale-vm.. ([103.97.165.210]) by smtp.googlemail.com with ESMTPSA id t4-20020a056870e74400b0017293fa734asm675414oak.48.2023.03.02.22.51.06 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 02 Mar 2023 22:51:08 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1677826269; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=lZQ2ngJ4sFZYmlYtgi8mO9F5kyakeh7gT4w82Q7qixg=; b=F8Mzyz1gnhNaYjMkSQRaxCbKMCUHKVwUyXo521GQnflHmI2HMk9BI2zz9aofFZYc7R PkR6JhyB4AFCUQGem+KYylCfaCX8EU73KLpEw/P9IQroB11nrBn4sZTJ7la35EMgqj2F /UxZBSqtPA2NRIpnjE1JLpWqne/NCw1ikN+BKwsGtpzk0t6lOFuwiUmHXunWRf4v7qLM S4ZgN0NA5jnRrUeEZiH4lwlNC0vvt4hb5jkt7NM/8kjBasOwYZvgORR1ykTOsz4pp0YR 02M1ryRTCXHjkLvfnT7SjRraRHDaA+YFDDFxIi+lJqiQLttIWtoxHeI+a/JA7dsdZ5iA WFQg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1677826269; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=lZQ2ngJ4sFZYmlYtgi8mO9F5kyakeh7gT4w82Q7qixg=; b=axM/VwlOXo/gs/4fVcdAYHb+PeaRiWFxvcwg566J/xFBXSeg2FtzsruPybWeXvRK7j Zy0hh2C8Tez6ae70HKQ36G6Num6j6JJJM5jIRTkGMfLoIr3Ux/z6/WX7rvCmDewXqDqy W3FfEyIDpIMPX3j+b6xCCkhao0HTq+is/PlAZVm1mTflsrE3Zu0gveFYRDFGfFJnTmvp AyVPksKKYzpF6WqyGJVNCR/rxWffI42zsrpgiUgFfLSk+3kA1QjDWxQQum7yw2YA+LOs kz/0mfy+5Qv3l1gEyhYNabdsbQ4MUKssJbZAlYRNm++lxM93PHGHOOEpw63hyz07nd0P yoWA== X-Gm-Message-State: AO0yUKVjDDAayMU8nIHi7nCYGenwDNjtOCXKUUe4uYUGGpTXvTjCwa2U AZtk+2VaCnyq2rtUP0NXZGgiOzne/Lp9IWL7YzU= X-Google-Smtp-Source: AK7set8xKUQH1oFYk9k2Oa++6pUOSv5t/kSzC0GKa3jcgjax8ICToUxKJCk+XyHwmwgAOBJ5CE4SPw== X-Received: by 2002:a05:6870:a687:b0:176:261c:d8a6 with SMTP id i7-20020a056870a68700b00176261cd8a6mr305595oam.6.1677826269132; Thu, 02 Mar 2023 22:51:09 -0800 (PST) From: Mayuresh Chitale To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Cc: Mayuresh Chitale , alistair.francis@wdc.com, Anup Patel Subject: [PATCH 2/2] hw: intc: Use cpu_by_arch_id to fetch CPU state Date: Fri, 3 Mar 2023 12:20:55 +0530 Message-Id: <20230303065055.915652-3-mchitale@ventanamicro.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230303065055.915652-1-mchitale@ventanamicro.com> References: <20230303065055.915652-1-mchitale@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2001:4860:4864:20::2d; envelope-from=mchitale@ventanamicro.com; helo=mail-oa1-x2d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ventanamicro.com) X-ZM-MESSAGEID: 1677826368981100005 Content-Type: text/plain; charset="utf-8" Qemu_get_cpu uses the logical CPU id assigned during init to fetch the CPU state. However APLIC, IMSIC and ACLINT contain registers and states which are specific to physical hart Ids. The hart Ids in any given system might be sparse and hence calls to qemu_get_cpu need to be replaced by cpu_by_arch_id which performs lookup based on the sparse physical hart IDs. Signed-off-by: Mayuresh Chitale Signed-off-by: Anup Patel Reviewed-by: Daniel Henrique Barboza --- hw/intc/riscv_aclint.c | 16 ++++++++-------- hw/intc/riscv_aplic.c | 4 ++-- hw/intc/riscv_imsic.c | 6 +++--- 3 files changed, 13 insertions(+), 13 deletions(-) diff --git a/hw/intc/riscv_aclint.c b/hw/intc/riscv_aclint.c index eee04643cb..b466a6abaf 100644 --- a/hw/intc/riscv_aclint.c +++ b/hw/intc/riscv_aclint.c @@ -130,7 +130,7 @@ static uint64_t riscv_aclint_mtimer_read(void *opaque, = hwaddr addr, addr < (mtimer->timecmp_base + (mtimer->num_harts << 3))) { size_t hartid =3D mtimer->hartid_base + ((addr - mtimer->timecmp_base) >> 3); - CPUState *cpu =3D qemu_get_cpu(hartid); + CPUState *cpu =3D cpu_by_arch_id(hartid); CPURISCVState *env =3D cpu ? cpu->env_ptr : NULL; if (!env) { qemu_log_mask(LOG_GUEST_ERROR, @@ -173,7 +173,7 @@ static void riscv_aclint_mtimer_write(void *opaque, hwa= ddr addr, addr < (mtimer->timecmp_base + (mtimer->num_harts << 3))) { size_t hartid =3D mtimer->hartid_base + ((addr - mtimer->timecmp_base) >> 3); - CPUState *cpu =3D qemu_get_cpu(hartid); + CPUState *cpu =3D cpu_by_arch_id(hartid); CPURISCVState *env =3D cpu ? cpu->env_ptr : NULL; if (!env) { qemu_log_mask(LOG_GUEST_ERROR, @@ -231,7 +231,7 @@ static void riscv_aclint_mtimer_write(void *opaque, hwa= ddr addr, =20 /* Check if timer interrupt is triggered for each hart. */ for (i =3D 0; i < mtimer->num_harts; i++) { - CPUState *cpu =3D qemu_get_cpu(mtimer->hartid_base + i); + CPUState *cpu =3D cpu_by_arch_id(mtimer->hartid_base + i); CPURISCVState *env =3D cpu ? cpu->env_ptr : NULL; if (!env) { continue; @@ -292,7 +292,7 @@ static void riscv_aclint_mtimer_realize(DeviceState *de= v, Error **errp) s->timecmp =3D g_new0(uint64_t, s->num_harts); /* Claim timer interrupt bits */ for (i =3D 0; i < s->num_harts; i++) { - RISCVCPU *cpu =3D RISCV_CPU(qemu_get_cpu(s->hartid_base + i)); + RISCVCPU *cpu =3D RISCV_CPU(cpu_by_arch_id(s->hartid_base + i)); if (riscv_cpu_claim_interrupts(cpu, MIP_MTIP) < 0) { error_report("MTIP already claimed"); exit(1); @@ -372,7 +372,7 @@ DeviceState *riscv_aclint_mtimer_create(hwaddr addr, hw= addr size, sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, addr); =20 for (i =3D 0; i < num_harts; i++) { - CPUState *cpu =3D qemu_get_cpu(hartid_base + i); + CPUState *cpu =3D cpu_by_arch_id(hartid_base + i); RISCVCPU *rvcpu =3D RISCV_CPU(cpu); CPURISCVState *env =3D cpu ? cpu->env_ptr : NULL; riscv_aclint_mtimer_callback *cb =3D @@ -407,7 +407,7 @@ static uint64_t riscv_aclint_swi_read(void *opaque, hwa= ddr addr, =20 if (addr < (swi->num_harts << 2)) { size_t hartid =3D swi->hartid_base + (addr >> 2); - CPUState *cpu =3D qemu_get_cpu(hartid); + CPUState *cpu =3D cpu_by_arch_id(hartid); CPURISCVState *env =3D cpu ? cpu->env_ptr : NULL; if (!env) { qemu_log_mask(LOG_GUEST_ERROR, @@ -430,7 +430,7 @@ static void riscv_aclint_swi_write(void *opaque, hwaddr= addr, uint64_t value, =20 if (addr < (swi->num_harts << 2)) { size_t hartid =3D swi->hartid_base + (addr >> 2); - CPUState *cpu =3D qemu_get_cpu(hartid); + CPUState *cpu =3D cpu_by_arch_id(hartid); CPURISCVState *env =3D cpu ? cpu->env_ptr : NULL; if (!env) { qemu_log_mask(LOG_GUEST_ERROR, @@ -545,7 +545,7 @@ DeviceState *riscv_aclint_swi_create(hwaddr addr, uint3= 2_t hartid_base, sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, addr); =20 for (i =3D 0; i < num_harts; i++) { - CPUState *cpu =3D qemu_get_cpu(hartid_base + i); + CPUState *cpu =3D cpu_by_arch_id(hartid_base + i); RISCVCPU *rvcpu =3D RISCV_CPU(cpu); =20 qdev_connect_gpio_out(dev, i, diff --git a/hw/intc/riscv_aplic.c b/hw/intc/riscv_aplic.c index cfd007e629..cd7efc4ad4 100644 --- a/hw/intc/riscv_aplic.c +++ b/hw/intc/riscv_aplic.c @@ -833,7 +833,7 @@ static void riscv_aplic_realize(DeviceState *dev, Error= **errp) =20 /* Claim the CPU interrupt to be triggered by this APLIC */ for (i =3D 0; i < aplic->num_harts; i++) { - RISCVCPU *cpu =3D RISCV_CPU(qemu_get_cpu(aplic->hartid_base + = i)); + RISCVCPU *cpu =3D RISCV_CPU(cpu_by_arch_id(aplic->hartid_base = + i)); if (riscv_cpu_claim_interrupts(cpu, (aplic->mmode) ? MIP_MEIP : MIP_SEIP) < 0) { error_report("%s already claimed", @@ -966,7 +966,7 @@ DeviceState *riscv_aplic_create(hwaddr addr, hwaddr siz= e, =20 if (!msimode) { for (i =3D 0; i < num_harts; i++) { - CPUState *cpu =3D qemu_get_cpu(hartid_base + i); + CPUState *cpu =3D cpu_by_arch_id(hartid_base + i); =20 qdev_connect_gpio_out_named(dev, NULL, i, qdev_get_gpio_in(DEVICE(cpu), diff --git a/hw/intc/riscv_imsic.c b/hw/intc/riscv_imsic.c index 4d4d5b50ca..fea3385b51 100644 --- a/hw/intc/riscv_imsic.c +++ b/hw/intc/riscv_imsic.c @@ -316,8 +316,8 @@ static const MemoryRegionOps riscv_imsic_ops =3D { static void riscv_imsic_realize(DeviceState *dev, Error **errp) { RISCVIMSICState *imsic =3D RISCV_IMSIC(dev); - RISCVCPU *rcpu =3D RISCV_CPU(qemu_get_cpu(imsic->hartid)); - CPUState *cpu =3D qemu_get_cpu(imsic->hartid); + RISCVCPU *rcpu =3D RISCV_CPU(cpu_by_arch_id(imsic->hartid)); + CPUState *cpu =3D cpu_by_arch_id(imsic->hartid); CPURISCVState *env =3D cpu ? cpu->env_ptr : NULL; =20 imsic->num_eistate =3D imsic->num_pages * imsic->num_irqs; @@ -413,7 +413,7 @@ DeviceState *riscv_imsic_create(hwaddr addr, uint32_t h= artid, bool mmode, uint32_t num_pages, uint32_t num_ids) { DeviceState *dev =3D qdev_new(TYPE_RISCV_IMSIC); - CPUState *cpu =3D qemu_get_cpu(hartid); + CPUState *cpu =3D cpu_by_arch_id(hartid); uint32_t i; =20 assert(!(addr & (IMSIC_MMIO_PAGE_SZ - 1))); --=20 2.34.1