ARM CPUs fetch instructions in little-endian.
smpboot[] encoded instructions are written in little-endian.
This is fine on little-endian host, but on big-endian ones
the smpboot[] array ends swapped. Use the const_le32()
macro so the instructions are always in little-endian in the
smpboot[] array.
Fixes: 9bb6d14081 ("aspeed: Add boot stub for smp booting")
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
hw/arm/aspeed.c | 28 ++++++++++++++--------------
1 file changed, 14 insertions(+), 14 deletions(-)
diff --git a/hw/arm/aspeed.c b/hw/arm/aspeed.c
index 55f114ef72..adff9a0d73 100644
--- a/hw/arm/aspeed.c
+++ b/hw/arm/aspeed.c
@@ -194,22 +194,22 @@ static void aspeed_write_smpboot(ARMCPU *cpu,
* r1 = AST_SMP_MBOX_FIELD_ENTRY
* r0 = AST_SMP_MBOX_FIELD_GOSIGN
*/
- 0xee100fb0, /* mrc p15, 0, r0, c0, c0, 5 */
- 0xe21000ff, /* ands r0, r0, #255 */
- 0xe59f201c, /* ldr r2, [pc, #28] */
- 0xe1822000, /* orr r2, r2, r0 */
+ const_le32(0xee100fb0), /* mrc p15, 0, r0, c0, c0, 5 */
+ const_le32(0xe21000ff), /* ands r0, r0, #255 */
+ const_le32(0xe59f201c), /* ldr r2, [pc, #28] */
+ const_le32(0xe1822000), /* orr r2, r2, r0 */
- 0xe59f1018, /* ldr r1, [pc, #24] */
- 0xe59f0018, /* ldr r0, [pc, #24] */
+ const_le32(0xe59f1018), /* ldr r1, [pc, #24] */
+ const_le32(0xe59f0018), /* ldr r0, [pc, #24] */
- 0xe320f002, /* wfe */
- 0xe5904000, /* ldr r4, [r0] */
- 0xe1520004, /* cmp r2, r4 */
- 0x1afffffb, /* bne <wfe> */
- 0xe591f000, /* ldr pc, [r1] */
- AST_SMP_MBOX_GOSIGN,
- AST_SMP_MBOX_FIELD_ENTRY,
- AST_SMP_MBOX_FIELD_GOSIGN,
+ const_le32(0xe320f002), /* wfe */
+ const_le32(0xe5904000), /* ldr r4, [r0] */
+ const_le32(0xe1520004), /* cmp r2, r4 */
+ const_le32(0x1afffffb), /* bne <wfe> */
+ const_le32(0xe591f000), /* ldr pc, [r1] */
+ const_le32(AST_SMP_MBOX_GOSIGN),
+ const_le32(AST_SMP_MBOX_FIELD_ENTRY),
+ const_le32(AST_SMP_MBOX_FIELD_GOSIGN)
};
rom_add_blob_fixed("aspeed.smpboot", poll_mailbox_ready,
--
2.38.1
On Thu, 22 Dec 2022 at 21:56, Philippe Mathieu-Daudé <philmd@linaro.org> wrote:
>
> ARM CPUs fetch instructions in little-endian.
>
> smpboot[] encoded instructions are written in little-endian.
> This is fine on little-endian host, but on big-endian ones
> the smpboot[] array ends swapped. Use the const_le32()
> macro so the instructions are always in little-endian in the
> smpboot[] array.
>
> Fixes: 9bb6d14081 ("aspeed: Add boot stub for smp booting")
> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
> ---
> hw/arm/aspeed.c | 28 ++++++++++++++--------------
> 1 file changed, 14 insertions(+), 14 deletions(-)
>
> diff --git a/hw/arm/aspeed.c b/hw/arm/aspeed.c
> index 55f114ef72..adff9a0d73 100644
> --- a/hw/arm/aspeed.c
> +++ b/hw/arm/aspeed.c
> @@ -194,22 +194,22 @@ static void aspeed_write_smpboot(ARMCPU *cpu,
> * r1 = AST_SMP_MBOX_FIELD_ENTRY
> * r0 = AST_SMP_MBOX_FIELD_GOSIGN
> */
> - 0xee100fb0, /* mrc p15, 0, r0, c0, c0, 5 */
> - 0xe21000ff, /* ands r0, r0, #255 */
> - 0xe59f201c, /* ldr r2, [pc, #28] */
> - 0xe1822000, /* orr r2, r2, r0 */
> + const_le32(0xee100fb0), /* mrc p15, 0, r0, c0, c0, 5 */
> + const_le32(0xe21000ff), /* ands r0, r0, #255 */
> + const_le32(0xe59f201c), /* ldr r2, [pc, #28] */
> + const_le32(0xe1822000), /* orr r2, r2, r0 */
>
> - 0xe59f1018, /* ldr r1, [pc, #24] */
> - 0xe59f0018, /* ldr r0, [pc, #24] */
> + const_le32(0xe59f1018), /* ldr r1, [pc, #24] */
> + const_le32(0xe59f0018), /* ldr r0, [pc, #24] */
>
> - 0xe320f002, /* wfe */
> - 0xe5904000, /* ldr r4, [r0] */
> - 0xe1520004, /* cmp r2, r4 */
> - 0x1afffffb, /* bne <wfe> */
> - 0xe591f000, /* ldr pc, [r1] */
> - AST_SMP_MBOX_GOSIGN,
> - AST_SMP_MBOX_FIELD_ENTRY,
> - AST_SMP_MBOX_FIELD_GOSIGN,
> + const_le32(0xe320f002), /* wfe */
> + const_le32(0xe5904000), /* ldr r4, [r0] */
> + const_le32(0xe1520004), /* cmp r2, r4 */
> + const_le32(0x1afffffb), /* bne <wfe> */
> + const_le32(0xe591f000), /* ldr pc, [r1] */
> + const_le32(AST_SMP_MBOX_GOSIGN),
> + const_le32(AST_SMP_MBOX_FIELD_ENTRY),
> + const_le32(AST_SMP_MBOX_FIELD_GOSIGN)
> };
>
> rom_add_blob_fixed("aspeed.smpboot", poll_mailbox_ready,
Can we use the write_bootloader() function, which handles the
endianness question correctly and is how other boards do the
"put a little lump of code into the guest" job ?
thanks
-- PMM
On 1/3/23 18:33, Peter Maydell wrote:
> On Thu, 22 Dec 2022 at 21:56, Philippe Mathieu-Daudé <philmd@linaro.org> wrote:
>>
>> ARM CPUs fetch instructions in little-endian.
>>
>> smpboot[] encoded instructions are written in little-endian.
>> This is fine on little-endian host, but on big-endian ones
>> the smpboot[] array ends swapped. Use the const_le32()
>> macro so the instructions are always in little-endian in the
>> smpboot[] array.
>>
>> Fixes: 9bb6d14081 ("aspeed: Add boot stub for smp booting")
>> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
>> ---
>> hw/arm/aspeed.c | 28 ++++++++++++++--------------
>> 1 file changed, 14 insertions(+), 14 deletions(-)
>>
>> diff --git a/hw/arm/aspeed.c b/hw/arm/aspeed.c
>> index 55f114ef72..adff9a0d73 100644
>> --- a/hw/arm/aspeed.c
>> +++ b/hw/arm/aspeed.c
>> @@ -194,22 +194,22 @@ static void aspeed_write_smpboot(ARMCPU *cpu,
>> * r1 = AST_SMP_MBOX_FIELD_ENTRY
>> * r0 = AST_SMP_MBOX_FIELD_GOSIGN
>> */
>> - 0xee100fb0, /* mrc p15, 0, r0, c0, c0, 5 */
>> - 0xe21000ff, /* ands r0, r0, #255 */
>> - 0xe59f201c, /* ldr r2, [pc, #28] */
>> - 0xe1822000, /* orr r2, r2, r0 */
>> + const_le32(0xee100fb0), /* mrc p15, 0, r0, c0, c0, 5 */
>> + const_le32(0xe21000ff), /* ands r0, r0, #255 */
>> + const_le32(0xe59f201c), /* ldr r2, [pc, #28] */
>> + const_le32(0xe1822000), /* orr r2, r2, r0 */
>>
>> - 0xe59f1018, /* ldr r1, [pc, #24] */
>> - 0xe59f0018, /* ldr r0, [pc, #24] */
>> + const_le32(0xe59f1018), /* ldr r1, [pc, #24] */
>> + const_le32(0xe59f0018), /* ldr r0, [pc, #24] */
>>
>> - 0xe320f002, /* wfe */
>> - 0xe5904000, /* ldr r4, [r0] */
>> - 0xe1520004, /* cmp r2, r4 */
>> - 0x1afffffb, /* bne <wfe> */
>> - 0xe591f000, /* ldr pc, [r1] */
>> - AST_SMP_MBOX_GOSIGN,
>> - AST_SMP_MBOX_FIELD_ENTRY,
>> - AST_SMP_MBOX_FIELD_GOSIGN,
>> + const_le32(0xe320f002), /* wfe */
>> + const_le32(0xe5904000), /* ldr r4, [r0] */
>> + const_le32(0xe1520004), /* cmp r2, r4 */
>> + const_le32(0x1afffffb), /* bne <wfe> */
>> + const_le32(0xe591f000), /* ldr pc, [r1] */
>> + const_le32(AST_SMP_MBOX_GOSIGN),
>> + const_le32(AST_SMP_MBOX_FIELD_ENTRY),
>> + const_le32(AST_SMP_MBOX_FIELD_GOSIGN)
>> };
>>
>> rom_add_blob_fixed("aspeed.smpboot", poll_mailbox_ready,
>
> Can we use the write_bootloader() function, which handles the
> endianness question correctly and is how other boards do the
> "put a little lump of code into the guest" job ?
Yes. See below.
May be we could change write_bootloader a little to handle an empty
fixupcontext.
Thanks,
C.
From 671d43faa7e14b896855403feb0afd777350cb0a Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= <clg@kaod.org>
Date: Wed, 4 Jan 2023 09:30:28 +0100
Subject: [PATCH] hw/arm/boot: Export write_bootloader for Aspeed machines
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit
AST2600 Aspeed machines have an home made boot loader for secondaries.
Instead, use the internal ARM boot loader.
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
include/hw/arm/boot.h | 24 ++++++++++++++++++++++++
hw/arm/aspeed.c | 42 ++++++++++++++++++++++--------------------
hw/arm/boot.c | 34 +++++++---------------------------
3 files changed, 53 insertions(+), 47 deletions(-)
diff --git a/include/hw/arm/boot.h b/include/hw/arm/boot.h
index f18cc3064f..23edd0d31b 100644
--- a/include/hw/arm/boot.h
+++ b/include/hw/arm/boot.h
@@ -183,4 +183,28 @@ void arm_write_secure_board_setup_dummy_smc(ARMCPU *cpu,
const struct arm_boot_info *info,
hwaddr mvbar_addr);
+typedef enum {
+ FIXUP_NONE = 0, /* do nothing */
+ FIXUP_TERMINATOR, /* end of insns */
+ FIXUP_BOARDID, /* overwrite with board ID number */
+ FIXUP_BOARD_SETUP, /* overwrite with board specific setup code address */
+ FIXUP_ARGPTR_LO, /* overwrite with pointer to kernel args */
+ FIXUP_ARGPTR_HI, /* overwrite with pointer to kernel args (high half) */
+ FIXUP_ENTRYPOINT_LO, /* overwrite with kernel entry point */
+ FIXUP_ENTRYPOINT_HI, /* overwrite with kernel entry point (high half) */
+ FIXUP_GIC_CPU_IF, /* overwrite with GIC CPU interface address */
+ FIXUP_BOOTREG, /* overwrite with boot register address */
+ FIXUP_DSB, /* overwrite with correct DSB insn for cpu */
+ FIXUP_MAX,
+} FixupType;
+
+typedef struct ARMInsnFixup {
+ uint32_t insn;
+ FixupType fixup;
+} ARMInsnFixup;
+
+void arm_write_bootloader(const char *name, hwaddr addr,
+ const ARMInsnFixup *insns, uint32_t *fixupcontext,
+ AddressSpace *as);
+
#endif /* HW_ARM_BOOT_H */
diff --git a/hw/arm/aspeed.c b/hw/arm/aspeed.c
index 9c60575cb8..311c0091ca 100644
--- a/hw/arm/aspeed.c
+++ b/hw/arm/aspeed.c
@@ -201,33 +201,35 @@ struct AspeedMachineState {
static void aspeed_write_smpboot(ARMCPU *cpu,
const struct arm_boot_info *info)
{
- static const uint32_t poll_mailbox_ready[] = {
+ AddressSpace *as = arm_boot_address_space(cpu, info);
+ static const ARMInsnFixup poll_mailbox_ready[] = {
/*
* r2 = per-cpu go sign value
* r1 = AST_SMP_MBOX_FIELD_ENTRY
* r0 = AST_SMP_MBOX_FIELD_GOSIGN
*/
- 0xee100fb0, /* mrc p15, 0, r0, c0, c0, 5 */
- 0xe21000ff, /* ands r0, r0, #255 */
- 0xe59f201c, /* ldr r2, [pc, #28] */
- 0xe1822000, /* orr r2, r2, r0 */
-
- 0xe59f1018, /* ldr r1, [pc, #24] */
- 0xe59f0018, /* ldr r0, [pc, #24] */
-
- 0xe320f002, /* wfe */
- 0xe5904000, /* ldr r4, [r0] */
- 0xe1520004, /* cmp r2, r4 */
- 0x1afffffb, /* bne <wfe> */
- 0xe591f000, /* ldr pc, [r1] */
- AST_SMP_MBOX_GOSIGN,
- AST_SMP_MBOX_FIELD_ENTRY,
- AST_SMP_MBOX_FIELD_GOSIGN,
+ { 0xee100fb0 }, /* mrc p15, 0, r0, c0, c0, 5 */
+ { 0xe21000ff }, /* ands r0, r0, #255 */
+ { 0xe59f201c }, /* ldr r2, [pc, #28] */
+ { 0xe1822000 }, /* orr r2, r2, r0 */
+
+ { 0xe59f1018 }, /* ldr r1, [pc, #24] */
+ { 0xe59f0018 }, /* ldr r0, [pc, #24] */
+
+ { 0xe320f002 }, /* wfe */
+ { 0xe5904000 }, /* ldr r4, [r0] */
+ { 0xe1520004 }, /* cmp r2, r4 */
+ { 0x1afffffb }, /* bne <wfe> */
+ { 0xe591f000 }, /* ldr pc, [r1] */
+ { AST_SMP_MBOX_GOSIGN },
+ { AST_SMP_MBOX_FIELD_ENTRY },
+ { AST_SMP_MBOX_FIELD_GOSIGN },
+ { 0, FIXUP_TERMINATOR }
};
+ uint32_t fixupcontext[FIXUP_MAX] = { 0 };
- rom_add_blob_fixed("aspeed.smpboot", poll_mailbox_ready,
- sizeof(poll_mailbox_ready),
- info->smp_loader_start);
+ arm_write_bootloader("aspeed.smpboot", info->smp_loader_start,
+ poll_mailbox_ready, fixupcontext, as);
}
static void aspeed_reset_secondary(ARMCPU *cpu,
diff --git a/hw/arm/boot.c b/hw/arm/boot.c
index 3d7d11f782..ed6fd7c77f 100644
--- a/hw/arm/boot.c
+++ b/hw/arm/boot.c
@@ -59,26 +59,6 @@ AddressSpace *arm_boot_address_space(ARMCPU *cpu,
return cpu_get_address_space(cs, asidx);
}
-typedef enum {
- FIXUP_NONE = 0, /* do nothing */
- FIXUP_TERMINATOR, /* end of insns */
- FIXUP_BOARDID, /* overwrite with board ID number */
- FIXUP_BOARD_SETUP, /* overwrite with board specific setup code address */
- FIXUP_ARGPTR_LO, /* overwrite with pointer to kernel args */
- FIXUP_ARGPTR_HI, /* overwrite with pointer to kernel args (high half) */
- FIXUP_ENTRYPOINT_LO, /* overwrite with kernel entry point */
- FIXUP_ENTRYPOINT_HI, /* overwrite with kernel entry point (high half) */
- FIXUP_GIC_CPU_IF, /* overwrite with GIC CPU interface address */
- FIXUP_BOOTREG, /* overwrite with boot register address */
- FIXUP_DSB, /* overwrite with correct DSB insn for cpu */
- FIXUP_MAX,
-} FixupType;
-
-typedef struct ARMInsnFixup {
- uint32_t insn;
- FixupType fixup;
-} ARMInsnFixup;
-
static const ARMInsnFixup bootloader_aarch64[] = {
{ 0x580000c0 }, /* ldr x0, arg ; Load the lower 32-bits of DTB */
{ 0xaa1f03e1 }, /* mov x1, xzr */
@@ -149,9 +129,9 @@ static const ARMInsnFixup smpboot[] = {
{ 0, FIXUP_TERMINATOR }
};
-static void write_bootloader(const char *name, hwaddr addr,
- const ARMInsnFixup *insns, uint32_t *fixupcontext,
- AddressSpace *as)
+void arm_write_bootloader(const char *name, hwaddr addr,
+ const ARMInsnFixup *insns, uint32_t *fixupcontext,
+ AddressSpace *as)
{
/* Fix up the specified bootloader fragment and write it into
* guest memory using rom_add_blob_fixed(). fixupcontext is
@@ -213,8 +193,8 @@ static void default_write_secondary(ARMCPU *cpu,
fixupcontext[FIXUP_DSB] = CP15_DSB_INSN;
}
- write_bootloader("smpboot", info->smp_loader_start,
- smpboot, fixupcontext, as);
+ arm_write_bootloader("smpboot", info->smp_loader_start,
+ smpboot, fixupcontext, as);
}
void arm_write_secure_board_setup_dummy_smc(ARMCPU *cpu,
@@ -1173,8 +1153,8 @@ static void arm_setup_direct_kernel_boot(ARMCPU *cpu,
fixupcontext[FIXUP_ENTRYPOINT_LO] = entry;
fixupcontext[FIXUP_ENTRYPOINT_HI] = entry >> 32;
- write_bootloader("bootloader", info->loader_start,
- primary_loader, fixupcontext, as);
+ arm_write_bootloader("bootloader", info->loader_start,
+ primary_loader, fixupcontext, as);
if (info->write_board_setup) {
info->write_board_setup(cpu, info);
--
2.38.1
Hi Cédric, On 4/1/23 09:43, Cédric Le Goater wrote: > On 1/3/23 18:33, Peter Maydell wrote: >> Can we use the write_bootloader() function, which handles the >> endianness question correctly and is how other boards do the >> "put a little lump of code into the guest" job ? > > Yes. See below. > > May be we could change write_bootloader a little to handle an empty > fixupcontext. > > Thanks, > > C. > > From 671d43faa7e14b896855403feb0afd777350cb0a Mon Sep 17 00:00:00 2001 > From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= <clg@kaod.org> > Date: Wed, 4 Jan 2023 09:30:28 +0100 > Subject: [PATCH] hw/arm/boot: Export write_bootloader for Aspeed machines > MIME-Version: 1.0 > Content-Type: text/plain; charset=UTF-8 > Content-Transfer-Encoding: 8bit > > AST2600 Aspeed machines have an home made boot loader for secondaries. > Instead, use the internal ARM boot loader. > > Signed-off-by: Cédric Le Goater <clg@kaod.org> > --- > include/hw/arm/boot.h | 24 ++++++++++++++++++++++++ > hw/arm/aspeed.c | 42 ++++++++++++++++++++++-------------------- > hw/arm/boot.c | 34 +++++++--------------------------- > 3 files changed, 53 insertions(+), 47 deletions(-) [...] I'm getting: Applying: hw/arm/boot: Export write_bootloader for Aspeed machines error: patch failed: include/hw/arm/boot.h:183 error: include/hw/arm/boot.h: patch does not apply error: patch failed: hw/arm/aspeed.c:201 error: hw/arm/aspeed.c: patch does not apply error: patch failed: hw/arm/boot.c:59 error: hw/arm/boot.c: patch does not apply Patch failed at 0001 hw/arm/boot: Export write_bootloader for Aspeed machines hint: Use 'git am --show-current-patch=diff' to see the failed patch When you have resolved this problem, run "git am --continue". If you prefer to skip this patch, run "git am --skip" instead. To restore the original branch and stop patching, run "git am --abort". What is your base commit? Can you post a normal patch? Thanks, Phil.
On 1/4/23 23:35, Philippe Mathieu-Daudé wrote:
> Hi Cédric,
>
> On 4/1/23 09:43, Cédric Le Goater wrote:
>> On 1/3/23 18:33, Peter Maydell wrote:
>
>>> Can we use the write_bootloader() function, which handles the
>>> endianness question correctly and is how other boards do the
>>> "put a little lump of code into the guest" job ?
>>
>> Yes. See below.
>>
>> May be we could change write_bootloader a little to handle an empty
>> fixupcontext.
>>
>> Thanks,
>>
>> C.
>>
>> From 671d43faa7e14b896855403feb0afd777350cb0a Mon Sep 17 00:00:00 2001
>> From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= <clg@kaod.org>
>> Date: Wed, 4 Jan 2023 09:30:28 +0100
>> Subject: [PATCH] hw/arm/boot: Export write_bootloader for Aspeed machines
>> MIME-Version: 1.0
>> Content-Type: text/plain; charset=UTF-8
>> Content-Transfer-Encoding: 8bit
>>
>> AST2600 Aspeed machines have an home made boot loader for secondaries.
>> Instead, use the internal ARM boot loader.
>>
>> Signed-off-by: Cédric Le Goater <clg@kaod.org>
>> ---
>> include/hw/arm/boot.h | 24 ++++++++++++++++++++++++
>> hw/arm/aspeed.c | 42 ++++++++++++++++++++++--------------------
>> hw/arm/boot.c | 34 +++++++---------------------------
>> 3 files changed, 53 insertions(+), 47 deletions(-)
> [...]
>
> I'm getting:
>
> Applying: hw/arm/boot: Export write_bootloader for Aspeed machines
> error: patch failed: include/hw/arm/boot.h:183
> error: include/hw/arm/boot.h: patch does not apply
> error: patch failed: hw/arm/aspeed.c:201
> error: hw/arm/aspeed.c: patch does not apply
> error: patch failed: hw/arm/boot.c:59
> error: hw/arm/boot.c: patch does not apply
> Patch failed at 0001 hw/arm/boot: Export write_bootloader for Aspeed machines
> hint: Use 'git am --show-current-patch=diff' to see the failed patch
> When you have resolved this problem, run "git am --continue".
> If you prefer to skip this patch, run "git am --skip" instead.
> To restore the original branch and stop patching, run "git am --abort".
>
> What is your base commit?
It applies on 222059a0fc ("Merge tag 'pull-ppc-20221221' of
https://gitlab.com/danielhb/qemu into staging")
> Can you post a normal patch?
Sure.
C.
On 12/22/22 22:55, Philippe Mathieu-Daudé wrote:
> ARM CPUs fetch instructions in little-endian.
>
> smpboot[] encoded instructions are written in little-endian.
> This is fine on little-endian host, but on big-endian ones
> the smpboot[] array ends swapped. Use the const_le32()
> macro so the instructions are always in little-endian in the
> smpboot[] array.
>
> Fixes: 9bb6d14081 ("aspeed: Add boot stub for smp booting")
> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
> ---
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Thanks,
C.
> hw/arm/aspeed.c | 28 ++++++++++++++--------------
> 1 file changed, 14 insertions(+), 14 deletions(-)
>
> diff --git a/hw/arm/aspeed.c b/hw/arm/aspeed.c
> index 55f114ef72..adff9a0d73 100644
> --- a/hw/arm/aspeed.c
> +++ b/hw/arm/aspeed.c
> @@ -194,22 +194,22 @@ static void aspeed_write_smpboot(ARMCPU *cpu,
> * r1 = AST_SMP_MBOX_FIELD_ENTRY
> * r0 = AST_SMP_MBOX_FIELD_GOSIGN
> */
> - 0xee100fb0, /* mrc p15, 0, r0, c0, c0, 5 */
> - 0xe21000ff, /* ands r0, r0, #255 */
> - 0xe59f201c, /* ldr r2, [pc, #28] */
> - 0xe1822000, /* orr r2, r2, r0 */
> + const_le32(0xee100fb0), /* mrc p15, 0, r0, c0, c0, 5 */
> + const_le32(0xe21000ff), /* ands r0, r0, #255 */
> + const_le32(0xe59f201c), /* ldr r2, [pc, #28] */
> + const_le32(0xe1822000), /* orr r2, r2, r0 */
>
> - 0xe59f1018, /* ldr r1, [pc, #24] */
> - 0xe59f0018, /* ldr r0, [pc, #24] */
> + const_le32(0xe59f1018), /* ldr r1, [pc, #24] */
> + const_le32(0xe59f0018), /* ldr r0, [pc, #24] */
>
> - 0xe320f002, /* wfe */
> - 0xe5904000, /* ldr r4, [r0] */
> - 0xe1520004, /* cmp r2, r4 */
> - 0x1afffffb, /* bne <wfe> */
> - 0xe591f000, /* ldr pc, [r1] */
> - AST_SMP_MBOX_GOSIGN,
> - AST_SMP_MBOX_FIELD_ENTRY,
> - AST_SMP_MBOX_FIELD_GOSIGN,
> + const_le32(0xe320f002), /* wfe */
> + const_le32(0xe5904000), /* ldr r4, [r0] */
> + const_le32(0xe1520004), /* cmp r2, r4 */
> + const_le32(0x1afffffb), /* bne <wfe> */
> + const_le32(0xe591f000), /* ldr pc, [r1] */
> + const_le32(AST_SMP_MBOX_GOSIGN),
> + const_le32(AST_SMP_MBOX_FIELD_ENTRY),
> + const_le32(AST_SMP_MBOX_FIELD_GOSIGN)
> };
>
> rom_add_blob_fixed("aspeed.smpboot", poll_mailbox_ready,
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