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Iglesias" , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , Alistair Francis , qemu-arm@nongnu.org, Tyrone Ting Subject: [PATCH 1/6] hw/arm/aspeed: Fix smpboot[] on big-endian hosts Date: Thu, 22 Dec 2022 22:55:44 +0100 Message-Id: <20221222215549.86872-2-philmd@linaro.org> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20221222215549.86872-1-philmd@linaro.org> References: <20221222215549.86872-1-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::62c; envelope-from=philmd@linaro.org; helo=mail-ej1-x62c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1671746305777100001 ARM CPUs fetch instructions in little-endian. smpboot[] encoded instructions are written in little-endian. This is fine on little-endian host, but on big-endian ones the smpboot[] array ends swapped. Use the const_le32() macro so the instructions are always in little-endian in the smpboot[] array. Fixes: 9bb6d14081 ("aspeed: Add boot stub for smp booting") Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: C=C3=A9dric Le Goater --- hw/arm/aspeed.c | 28 ++++++++++++++-------------- 1 file changed, 14 insertions(+), 14 deletions(-) diff --git a/hw/arm/aspeed.c b/hw/arm/aspeed.c index 55f114ef72..adff9a0d73 100644 --- a/hw/arm/aspeed.c +++ b/hw/arm/aspeed.c @@ -194,22 +194,22 @@ static void aspeed_write_smpboot(ARMCPU *cpu, * r1 =3D AST_SMP_MBOX_FIELD_ENTRY * r0 =3D AST_SMP_MBOX_FIELD_GOSIGN */ - 0xee100fb0, /* mrc p15, 0, r0, c0, c0, 5 */ - 0xe21000ff, /* ands r0, r0, #255 */ - 0xe59f201c, /* ldr r2, [pc, #28] */ - 0xe1822000, /* orr r2, r2, r0 */ + const_le32(0xee100fb0), /* mrc p15, 0, r0, c0, c0, 5 */ + const_le32(0xe21000ff), /* ands r0, r0, #255 */ + const_le32(0xe59f201c), /* ldr r2, [pc, #28] */ + const_le32(0xe1822000), /* orr r2, r2, r0 */ =20 - 0xe59f1018, /* ldr r1, [pc, #24] */ - 0xe59f0018, /* ldr r0, [pc, #24] */ + const_le32(0xe59f1018), /* ldr r1, [pc, #24] */ + const_le32(0xe59f0018), /* ldr r0, [pc, #24] */ =20 - 0xe320f002, /* wfe */ - 0xe5904000, /* ldr r4, [r0] */ - 0xe1520004, /* cmp r2, r4 */ - 0x1afffffb, /* bne */ - 0xe591f000, /* ldr pc, [r1] */ - AST_SMP_MBOX_GOSIGN, - AST_SMP_MBOX_FIELD_ENTRY, - AST_SMP_MBOX_FIELD_GOSIGN, + const_le32(0xe320f002), /* wfe */ + const_le32(0xe5904000), /* ldr r4, [r0] */ + const_le32(0xe1520004), /* cmp r2, r4 */ + const_le32(0x1afffffb), /* bne */ + const_le32(0xe591f000), /* ldr pc, [r1] */ + const_le32(AST_SMP_MBOX_GOSIGN), + const_le32(AST_SMP_MBOX_FIELD_ENTRY), + const_le32(AST_SMP_MBOX_FIELD_GOSIGN) }; =20 rom_add_blob_fixed("aspeed.smpboot", poll_mailbox_ready, --=20 2.38.1