Series comparison

-[PULL 00/10] riscv-to-apply queue
+[PULL 00/28] riscv-to-apply queue
-From: Alistair Francis <alistair.francis@wdc.com>
+The following changes since commit ad10b4badc1dd5b28305f9b9f1168cf0aa3ae946:
-The following changes since commit 2ba341b3694cf3cff7b8a1df4cc765900d5c4f60:
+  Merge tag 'pull-error-2024-05-27' of https://repo.or.cz/qemu/armbru into staging (2024-05-27 06:40:42 -0700)
   Merge tag 'kraxel-20221013-pull-request' of https://gitlab.com/kraxel/qemu into staging (2022-10-13 13:55:53 -0400)
 are available in the Git repository at:
-  https://github.com/alistair23/qemu.git tags/pull-riscv-to-apply-20221014
+  https://github.com/alistair23/qemu.git tags/pull-riscv-to-apply-20240528
-for you to fetch changes up to 47566421f029b0a489b63f8195b3ff944e017056:
+for you to fetch changes up to 1806da76cb81088ea026ca3441551782b850e393:
-  target/riscv: pmp: Fixup TLB size calculation (2022-10-14 14:36:19 +1000)
+  target/riscv: raise an exception when CSRRS/CSRRC writes a read-only CSR (2024-05-28 12:20:27 +1000)
 ----------------------------------------------------------------
-Third RISC-V PR for QEMU 7.2
+RISC-V PR for 9.1
-* Update qtest comment
+* APLICs add child earlier than realize
-* Fix coverity issue with Ibex SPI
+* Fix exposure of Zkr
-* Move load_image_to_fw_cfg() to common location
+* Raise exceptions on wrs.nto
-* Enable booting S-mode firmware from pflash on virt machine
+* Implement SBI debug console (DBCN) calls for KVM
-* Add disas support for vector instructions
+* Support 64-bit addresses for initrd
-* Priority level fixes for PLIC
+* Change RISCV_EXCP_SEMIHOST exception number to 63
-* Fixup TLB size calculation when using PMP
+* Tolerate KVM disable ext errors
 * Set tval in breakpoints
 * Add support for Zve32x extension
 * Add support for Zve64x extension
 * Relax vector register check in RISCV gdbstub
 * Fix the element agnostic Vector function problem
 * Fix Zvkb extension config
 * Implement dynamic establishment of custom decoder
 * Add th.sxstatus CSR emulation
 * Fix Zvfhmin checking for vfwcvt.f.f.v and vfncvt.f.f.w instructions
 * Check single width operator for vector fp widen instructions
 * Check single width operator for vfncvt.rod.f.f.w
 * Remove redudant SEW checking for vector fp narrow/widen instructions
 * Prioritize pmp errors in raise_mmu_exception()
 * Do not set mtval2 for non guest-page faults
 * Remove experimental prefix from "B" extension
 * Fixup CBO extension register calculation
 * Fix the hart bit setting of AIA
 * Fix reg_width in ricsv_gen_dynamic_vector_feature()
 * Decode all of the pmpcfg and pmpaddr CSRs
 * Raise an exception when CSRRS/CSRRC writes a read-only CSR
 ----------------------------------------------------------------
-Alistair Francis (1):
+Alexei Filippov (1):
-      target/riscv: pmp: Fixup TLB size calculation
+      target/riscv: do not set mtval2 for non guest-page faults
-Bin Meng (1):
+Alistair Francis (2):
-      hw/riscv: Update comment for qtest check in riscv_find_firmware()
+      target/riscv: rvzicbo: Fixup CBO extension register calculation
       disas/riscv: Decode all of the pmpcfg and pmpaddr CSRs
-Jim Shu (2):
+Andrew Jones (2):
-      hw/intc: sifive_plic: fix hard-coded max priority level
+      target/riscv/kvm: Fix exposure of Zkr
-      hw/intc: sifive_plic: change interrupt priority register to WARL field
+      target/riscv: Raise exceptions on wrs.nto
-Sunil V L (3):
+Cheng Yang (1):
-      hw/arm, loongarch: Move load_image_to_fw_cfg() to common location
+      hw/riscv/boot.c: Support 64-bit address for initrd
       hw/riscv: virt: Move create_fw_cfg() prior to loading kernel
       hw/riscv: virt: Enable booting S-mode firmware from pflash
-Wilfred Mallawa (2):
+Christoph Müllner (1):
-      hw/ssi: ibex_spi: fixup coverity issue
+      riscv: thead: Add th.sxstatus CSR emulation
       hw/ssi: ibex_spi: fixup/add rw1c functionality
-Yang Liu (1):
+Clément Léger (1):
-      disas/riscv.c: rvv: Add disas support for vector instructions
+      target/riscv: change RISCV_EXCP_SEMIHOST exception number to 63
- include/hw/nvram/fw_cfg.h      |   21 +
+Daniel Henrique Barboza (6):
- include/hw/riscv/boot.h        |    1 +
+      target/riscv/kvm: implement SBI debug console (DBCN) calls
- include/hw/ssi/ibex_spi_host.h |    4 +-
+      target/riscv/kvm: tolerate KVM disable ext errors
- disas/riscv.c                  | 1432 +++++++++++++++++++++++++++++++++++++++-
+      target/riscv/debug: set tval=pc in breakpoint exceptions
- hw/arm/boot.c                  |   49 --
+      trans_privileged.c.inc: set (m|s)tval on ebreak breakpoint
- hw/intc/sifive_plic.c          |   25 +-
+      target/riscv: prioritize pmp errors in raise_mmu_exception()
- hw/loongarch/virt.c            |   33 -
+      riscv, gdbstub.c: fix reg_width in ricsv_gen_dynamic_vector_feature()
- hw/nvram/fw_cfg.c              |   32 +
- hw/riscv/boot.c                |   33 +-
+Huang Tao (2):
- hw/riscv/virt.c                |   32 +-
+      target/riscv: Fix the element agnostic function problem
- hw/ssi/ibex_spi_host.c         |  166 +++--
+      target/riscv: Implement dynamic establishment of custom decoder
- target/riscv/pmp.c             |   12 +
-files changed, 1675 insertions(+), 165 deletions(-)
+Jason Chien (3):
       target/riscv: Add support for Zve32x extension
       target/riscv: Add support for Zve64x extension
       target/riscv: Relax vector register check in RISCV gdbstub
 Max Chou (4):
       target/riscv: rvv: Fix Zvfhmin checking for vfwcvt.f.f.v and vfncvt.f.f.w instructions
       target/riscv: rvv: Check single width operator for vector fp widen instructions
       target/riscv: rvv: Check single width operator for vfncvt.rod.f.f.w
       target/riscv: rvv: Remove redudant SEW checking for vector fp narrow/widen instructions
 Rob Bradford (1):
       target/riscv: Remove experimental prefix from "B" extension
 Yangyu Chen (1):
       target/riscv/cpu.c: fix Zvkb extension config
 Yong-Xuan Wang (1):
       target/riscv/kvm.c: Fix the hart bit setting of AIA
 Yu-Ming Chang (1):
       target/riscv: raise an exception when CSRRS/CSRRC writes a read-only CSR
 yang.zhang (1):
       hw/intc/riscv_aplic: APLICs should add child earlier than realize
  MAINTAINERS                                    |   1 +
  target/riscv/cpu.h                             |  11 ++
  target/riscv/cpu_bits.h                        |   2 +-
  target/riscv/cpu_cfg.h                         |   2 +
  target/riscv/helper.h                          |   1 +
  target/riscv/sbi_ecall_interface.h             |  17 +++
  target/riscv/tcg/tcg-cpu.h                     |  15 +++
  disas/riscv.c                                  |  65 +++++++++-
  hw/intc/riscv_aplic.c                          |   8 +-
  hw/riscv/boot.c                                |   4 +-
  target/riscv/cpu.c                             |  10 +-
  target/riscv/cpu_helper.c                      |  37 +++---
  target/riscv/csr.c                             |  71 +++++++++--
  target/riscv/debug.c                           |   3 +
  target/riscv/gdbstub.c                         |   8 +-
  target/riscv/kvm/kvm-cpu.c                     | 157 ++++++++++++++++++++++++-
  target/riscv/op_helper.c                       |  17 ++-
  target/riscv/tcg/tcg-cpu.c                     |  50 +++++---
  target/riscv/th_csr.c                          |  79 +++++++++++++
  target/riscv/translate.c                       |  31 +++--
  target/riscv/vector_internals.c                |  22 ++++
  target/riscv/insn_trans/trans_privileged.c.inc |   2 +
  target/riscv/insn_trans/trans_rvv.c.inc        |  46 +++++---
  target/riscv/insn_trans/trans_rvzawrs.c.inc    |  29 +++--
  target/riscv/insn_trans/trans_rvzicbo.c.inc    |  16 ++-
  target/riscv/meson.build                       |   1 +
 files changed, 596 insertions(+), 109 deletions(-)
  create mode 100644 target/riscv/th_csr.c

-New patch
+[PULL 01/28] hw/intc/riscv_aplic: APLICs should add child earlier than realize
+From: "yang.zhang" <yang.zhang@hexintek.com>
+Since only root APLICs can have hw IRQ lines, aplic->parent should
+be initialized first.
+Fixes: e8f79343cf ("hw/intc: Add RISC-V AIA APLIC device emulation")
+Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
+Signed-off-by: yang.zhang <yang.zhang@hexintek.com>
+Cc: qemu-stable <qemu-stable@nongnu.org>
+Message-ID: <20240409014445.278-1-gaoshanliukou@163.com>
+Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
+---
+ hw/intc/riscv_aplic.c | 8 ++++----
+file changed, 4 insertions(+), 4 deletions(-)
+diff --git a/hw/intc/riscv_aplic.c b/hw/intc/riscv_aplic.c
+index XXXXXXX..XXXXXXX 100644
+--- a/hw/intc/riscv_aplic.c
++++ b/hw/intc/riscv_aplic.c
+@@ -XXX,XX +XXX,XX @@ DeviceState *riscv_aplic_create(hwaddr addr, hwaddr size,
+     qdev_prop_set_bit(dev, "msimode", msimode);
+     qdev_prop_set_bit(dev, "mmode", mmode);
++    if (parent) {
++        riscv_aplic_add_child(parent, dev);
++    }
++
+     sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
+     if (!is_kvm_aia(msimode)) {
+         sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, addr);
+     }
+-    if (parent) {
+-        riscv_aplic_add_child(parent, dev);
+-    }
+-
+     if (!msimode) {
+         for (i = 0; i < num_harts; i++) {
+             CPUState *cpu = cpu_by_arch_id(hartid_base + i);
+--
+.45.1

-New patch
+[PULL 02/28] target/riscv/kvm: Fix exposure of Zkr
+From: Andrew Jones <ajones@ventanamicro.com>
+The Zkr extension may only be exposed to KVM guests if the VMM
+implements the SEED CSR. Use the same implementation as TCG.
+Without this patch, running with a KVM which does not forward the
+SEED CSR access to QEMU will result in an ILL exception being
+injected into the guest (this results in Linux guests crashing on
+boot). And, when running with a KVM which does forward the access,
+QEMU will crash, since QEMU doesn't know what to do with the exit.
+Fixes: 3108e2f1c69d ("target/riscv/kvm: update KVM exts to Linux 6.8")
+Signed-off-by: Andrew Jones <ajones@ventanamicro.com>
+Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
+Cc: qemu-stable <qemu-stable@nongnu.org>
+Message-ID: <20240422134605.534207-2-ajones@ventanamicro.com>
+Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
+---
+ target/riscv/cpu.h         |  3 +++
+ target/riscv/csr.c         | 18 ++++++++++++++----
+ target/riscv/kvm/kvm-cpu.c | 25 +++++++++++++++++++++++++
+files changed, 42 insertions(+), 4 deletions(-)
+diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
+index XXXXXXX..XXXXXXX 100644
+--- a/target/riscv/cpu.h
++++ b/target/riscv/cpu.h
+@@ -XXX,XX +XXX,XX @@ void riscv_set_csr_ops(int csrno, riscv_csr_operations *ops);
+ void riscv_cpu_register_gdb_regs_for_features(CPUState *cs);
++target_ulong riscv_new_csr_seed(target_ulong new_value,
++                                target_ulong write_mask);
++
+ uint8_t satp_mode_max_from_map(uint32_t map);
+ const char *satp_mode_str(uint8_t satp_mode, bool is_32_bit);
+diff --git a/target/riscv/csr.c b/target/riscv/csr.c
+index XXXXXXX..XXXXXXX 100644
+--- a/target/riscv/csr.c
++++ b/target/riscv/csr.c
+@@ -XXX,XX +XXX,XX @@ static RISCVException write_upmbase(CPURISCVState *env, int csrno,
+ #endif
+ /* Crypto Extension */
+-static RISCVException rmw_seed(CPURISCVState *env, int csrno,
+-                               target_ulong *ret_value,
+-                               target_ulong new_value,
+-                               target_ulong write_mask)
++target_ulong riscv_new_csr_seed(target_ulong new_value,
++                                target_ulong write_mask)
+ {
+     uint16_t random_v;
+     Error *random_e = NULL;
+@@ -XXX,XX +XXX,XX @@ static RISCVException rmw_seed(CPURISCVState *env, int csrno,
+         rval = random_v | SEED_OPST_ES16;
+     }
++    return rval;
++}
++
++static RISCVException rmw_seed(CPURISCVState *env, int csrno,
++                               target_ulong *ret_value,
++                               target_ulong new_value,
++                               target_ulong write_mask)
++{
++    target_ulong rval;
++
++    rval = riscv_new_csr_seed(new_value, write_mask);
++
+     if (ret_value) {
+         *ret_value = rval;
+     }
+diff --git a/target/riscv/kvm/kvm-cpu.c b/target/riscv/kvm/kvm-cpu.c
+index XXXXXXX..XXXXXXX 100644
+--- a/target/riscv/kvm/kvm-cpu.c
++++ b/target/riscv/kvm/kvm-cpu.c
+@@ -XXX,XX +XXX,XX @@ static int kvm_riscv_handle_sbi(CPUState *cs, struct kvm_run *run)
+     return ret;
+ }
++static int kvm_riscv_handle_csr(CPUState *cs, struct kvm_run *run)
++{
++    target_ulong csr_num = run->riscv_csr.csr_num;
++    target_ulong new_value = run->riscv_csr.new_value;
++    target_ulong write_mask = run->riscv_csr.write_mask;
++    int ret = 0;
++
++    switch (csr_num) {
++    case CSR_SEED:
++        run->riscv_csr.ret_value = riscv_new_csr_seed(new_value, write_mask);
++        break;
++    default:
++        qemu_log_mask(LOG_UNIMP,
++                      "%s: un-handled CSR EXIT for CSR %lx\n",
++                      __func__, csr_num);
++        ret = -1;
++        break;
++    }
++
++    return ret;
++}
++
+ int kvm_arch_handle_exit(CPUState *cs, struct kvm_run *run)
+ {
+     int ret = 0;
+@@ -XXX,XX +XXX,XX @@ int kvm_arch_handle_exit(CPUState *cs, struct kvm_run *run)
+     case KVM_EXIT_RISCV_SBI:
+         ret = kvm_riscv_handle_sbi(cs, run);
+         break;
++    case KVM_EXIT_RISCV_CSR:
++        ret = kvm_riscv_handle_csr(cs, run);
++        break;
+     default:
+         qemu_log_mask(LOG_UNIMP, "%s: un-handled exit reason %d\n",
+                       __func__, run->exit_reason);
+--
+.45.1

-[PULL 06/10] hw/riscv: virt: Enable booting S-mode firmware from pflash
+[PULL 03/28] target/riscv: Raise exceptions on wrs.nto
-From: Sunil V L <sunilvl@ventanamicro.com>
+From: Andrew Jones <ajones@ventanamicro.com>
-To boot S-mode firmware payload like EDK2 from persistent
+Implementing wrs.nto to always just return is consistent with the
-flash storage, qemu needs to pass the flash address as the
+specification, as the instruction is permitted to terminate the
-next_addr in fw_dynamic_info to the opensbi.
+stall for any reason, but it's not useful for virtualization, where
 we'd like the guest to trap to the hypervisor in order to allow
 scheduling of the lock holding VCPU. Change to always immediately
 raise exceptions when the appropriate conditions are present,
 otherwise continue to just return. Note, immediately raising
 exceptions is also consistent with the specification since the
 time limit that should expire prior to the exception is
 implementation-specific.
-When both -kernel and -pflash options are provided in command line,
+Signed-off-by: Andrew Jones <ajones@ventanamicro.com>
-the kernel (and initrd if -initrd) will be copied to fw_cfg table.
+Reviewed-by: Christoph Müllner <christoph.muellner@vrull.eu>
-The S-mode FW will load the kernel/initrd from fw_cfg table.
+Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
 If only pflash is given but not -kernel, then it is the job of
 of the S-mode firmware to locate and load the kernel.
 In either case, update the kernel_entry with the flash address
 so that the opensbi can jump to the entry point of the S-mode
 firmware.
 Signed-off-by: Sunil V L <sunilvl@ventanamicro.com>
 Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
 Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
-Message-Id: <20221004092351.18209-4-sunilvl@ventanamicro.com>
+Message-ID: <20240424142808.62936-2-ajones@ventanamicro.com>
 Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
 ---
- include/hw/riscv/boot.h |  1 +
+ target/riscv/helper.h                       |  1 +
- hw/riscv/boot.c         | 29 +++++++++++++++++++++++++++++
+ target/riscv/op_helper.c                    | 11 ++++++++
- hw/riscv/virt.c         | 18 +++++++++++++++++-
+ target/riscv/insn_trans/trans_rvzawrs.c.inc | 29 ++++++++++++++-------
-files changed, 47 insertions(+), 1 deletion(-)
+files changed, 32 insertions(+), 9 deletions(-)
-diff --git a/include/hw/riscv/boot.h b/include/hw/riscv/boot.h
+diff --git a/target/riscv/helper.h b/target/riscv/helper.h
 index XXXXXXX..XXXXXXX 100644
---- a/include/hw/riscv/boot.h
+--- a/target/riscv/helper.h
-+++ b/include/hw/riscv/boot.h
++++ b/target/riscv/helper.h
-@@ -XXX,XX +XXX,XX @@ void riscv_rom_copy_firmware_info(MachineState *machine, hwaddr rom_base,
+@@ -XXX,XX +XXX,XX @@ DEF_HELPER_6(csrrw_i128, tl, env, int, tl, tl, tl, tl)
-                                   uint32_t reset_vec_size,
+ DEF_HELPER_1(sret, tl, env)
-                                   uint64_t kernel_entry);
+ DEF_HELPER_1(mret, tl, env)
- void riscv_setup_direct_kernel(hwaddr kernel_addr, hwaddr fdt_addr);
+ DEF_HELPER_1(wfi, void, env)
-+void riscv_setup_firmware_boot(MachineState *machine);
++DEF_HELPER_1(wrs_nto, void, env)
+ DEF_HELPER_1(tlb_flush, void, env)
- #endif /* RISCV_BOOT_H */
+ DEF_HELPER_1(tlb_flush_all, void, env)
-diff --git a/hw/riscv/boot.c b/hw/riscv/boot.c
+ /* Native Debug */
 diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c
 index XXXXXXX..XXXXXXX 100644
---- a/hw/riscv/boot.c
+--- a/target/riscv/op_helper.c
-+++ b/hw/riscv/boot.c
++++ b/target/riscv/op_helper.c
-@@ -XXX,XX +XXX,XX @@ void riscv_setup_direct_kernel(hwaddr kernel_addr, hwaddr fdt_addr)
+@@ -XXX,XX +XXX,XX @@ void helper_wfi(CPURISCVState *env)
          riscv_cpu->env.fdt_addr = fdt_addr;
      }
  }
-+
-+void riscv_setup_firmware_boot(MachineState *machine)
++void helper_wrs_nto(CPURISCVState *env)
 +{
-+    if (machine->kernel_filename) {
++    if (env->virt_enabled && (env->priv == PRV_S || env->priv == PRV_U) &&
-+        FWCfgState *fw_cfg;
++        get_field(env->hstatus, HSTATUS_VTW) &&
-+        fw_cfg = fw_cfg_find();
++        !get_field(env->mstatus, MSTATUS_TW)) {
-+
++        riscv_raise_exception(env, RISCV_EXCP_VIRT_INSTRUCTION_FAULT, GETPC());
-+        assert(fw_cfg);
++    } else if (env->priv != PRV_M && get_field(env->mstatus, MSTATUS_TW)) {
-+        /*
++        riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC());
 +         * Expose the kernel, the command line, and the initrd in fw_cfg.
 +         * We don't process them here at all, it's all left to the
 +         * firmware.
 +         */
 +        load_image_to_fw_cfg(fw_cfg,
 +                             FW_CFG_KERNEL_SIZE, FW_CFG_KERNEL_DATA,
 +                             machine->kernel_filename,
 +                             true);
 +        load_image_to_fw_cfg(fw_cfg,
 +                             FW_CFG_INITRD_SIZE, FW_CFG_INITRD_DATA,
 +                             machine->initrd_filename, false);
 +
 +        if (machine->kernel_cmdline) {
 +            fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_SIZE,
 +                           strlen(machine->kernel_cmdline) + 1);
 +            fw_cfg_add_string(fw_cfg, FW_CFG_CMDLINE_DATA,
 +                              machine->kernel_cmdline);
 +        }
 +    }
 +}
-diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
++
  void helper_tlb_flush(CPURISCVState *env)
  {
      CPUState *cs = env_cpu(env);
 diff --git a/target/riscv/insn_trans/trans_rvzawrs.c.inc b/target/riscv/insn_trans/trans_rvzawrs.c.inc
 index XXXXXXX..XXXXXXX 100644
---- a/hw/riscv/virt.c
+--- a/target/riscv/insn_trans/trans_rvzawrs.c.inc
-+++ b/hw/riscv/virt.c
++++ b/target/riscv/insn_trans/trans_rvzawrs.c.inc
-@@ -XXX,XX +XXX,XX @@ static void virt_machine_done(Notifier *notifier, void *data)
+@@ -XXX,XX +XXX,XX @@
-     s->fw_cfg = create_fw_cfg(machine);
+  * this program.  If not, see <http://www.gnu.org/licenses/>.
-     rom_set_fw(s->fw_cfg);
+  */
--    if (machine->kernel_filename) {
+-static bool trans_wrs(DisasContext *ctx)
-+    if (drive_get(IF_PFLASH, 0, 1)) {
++static bool trans_wrs_sto(DisasContext *ctx, arg_wrs_sto *a)
-+        /*
+ {
-+         * S-mode FW like EDK2 will be kept in second plash (unit 1).
+     if (!ctx->cfg_ptr->ext_zawrs) {
-+         * When both kernel, initrd and pflash options are provided in the
+         return false;
-+         * command line, the kernel and initrd will be copied to the fw_cfg
+@@ -XXX,XX +XXX,XX @@ static bool trans_wrs(DisasContext *ctx)
-+         * table and opensbi will jump to the flash address which is the
+     return true;
-+         * entry point of S-mode FW. It is the job of the S-mode FW to load
+ }
-+         * the kernel and initrd using fw_cfg table.
-+         *
+-#define GEN_TRANS_WRS(insn)                                     \
-+         * If only pflash is given but not -kernel, then it is the job of
+-static bool trans_ ## insn(DisasContext *ctx, arg_ ## insn *a)  \
-+         * of the S-mode firmware to locate and load the kernel.
+-{                                                               \
-+         * In either case, the next_addr for opensbi will be the flash address.
+-    (void)a;                                                    \
-+         */
+-    return trans_wrs(ctx);                                      \
-+        riscv_setup_firmware_boot(machine);
+-}
-+        kernel_entry = virt_memmap[VIRT_FLASH].base +
++static bool trans_wrs_nto(DisasContext *ctx, arg_wrs_nto *a)
-+                       virt_memmap[VIRT_FLASH].size / 2;
++{
-+    } else if (machine->kernel_filename) {
++    if (!ctx->cfg_ptr->ext_zawrs) {
-         kernel_start_addr = riscv_calc_kernel_start_addr(&s->soc[0],
++        return false;
-                                                          firmware_end_addr);
++    }
 -GEN_TRANS_WRS(wrs_nto)
 -GEN_TRANS_WRS(wrs_sto)
 +    /*
 +     * Depending on the mode of execution, mstatus.TW and hstatus.VTW, wrs.nto
 +     * should raise an exception when the implementation-specific bounded time
 +     * limit has expired. Our time limit is zero, so we either return
 +     * immediately, as does our implementation of wrs.sto, or raise an
 +     * exception, as handled by the wrs.nto helper.
 +     */
 +#ifndef CONFIG_USER_ONLY
 +    gen_helper_wrs_nto(tcg_env);
 +#endif
 +
 +    /* We only get here when helper_wrs_nto() doesn't raise an exception. */
 +    return trans_wrs_sto(ctx, NULL);
 +}
 --
-.37.3
+.45.1

-New patch
+[PULL 04/28] target/riscv/kvm: implement SBI debug console (DBCN) calls
+From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
 SBI defines a Debug Console extension "DBCN" that will, in time, replace
 the legacy console putchar and getchar SBI extensions.
 The appeal of the DBCN extension is that it allows multiple bytes to be
 read/written in the SBI console in a single SBI call.
 As far as KVM goes, the DBCN calls are forwarded by an in-kernel KVM
 module to userspace. But this will only happens if the KVM module
 actually supports this SBI extension and we activate it.
 We'll check for DBCN support during init time, checking if get-reg-list
 is advertising KVM_RISCV_SBI_EXT_DBCN. In that case, we'll enable it via
 kvm_set_one_reg() during kvm_arch_init_vcpu().
 Finally, change kvm_riscv_handle_sbi() to handle the incoming calls for
 SBI_EXT_DBCN, reading and writing as required.
 A simple KVM guest with 'earlycon=sbi', running in an emulated RISC-V
 host, takes around 20 seconds to boot without using DBCN. With this
 patch we're taking around 14 seconds to boot due to the speed-up in the
 terminal output.  There's no change in boot time if the guest isn't
 using earlycon.
 Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
 Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
 Message-ID: <20240425155012.581366-1-dbarboza@ventanamicro.com>
 Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
 ---
  target/riscv/sbi_ecall_interface.h |  17 +++++
  target/riscv/kvm/kvm-cpu.c         | 111 +++++++++++++++++++++++++++++
 files changed, 128 insertions(+)
 diff --git a/target/riscv/sbi_ecall_interface.h b/target/riscv/sbi_ecall_interface.h
 index XXXXXXX..XXXXXXX 100644
 --- a/target/riscv/sbi_ecall_interface.h
 +++ b/target/riscv/sbi_ecall_interface.h
@@ -XXX,XX +XXX,XX @@
  /* clang-format off */
 +#define SBI_SUCCESS                      0
 +#define SBI_ERR_FAILED                  -1
 +#define SBI_ERR_NOT_SUPPORTED           -2
 +#define SBI_ERR_INVALID_PARAM           -3
 +#define SBI_ERR_DENIED                  -4
 +#define SBI_ERR_INVALID_ADDRESS         -5
 +#define SBI_ERR_ALREADY_AVAILABLE       -6
 +#define SBI_ERR_ALREADY_STARTED         -7
 +#define SBI_ERR_ALREADY_STOPPED         -8
 +#define SBI_ERR_NO_SHMEM                -9
 +
  /* SBI Extension IDs */
  #define SBI_EXT_0_1_SET_TIMER           0x0
  #define SBI_EXT_0_1_CONSOLE_PUTCHAR     0x1
@@ -XXX,XX +XXX,XX @@
  #define SBI_EXT_IPI                     0x735049
  #define SBI_EXT_RFENCE                  0x52464E43
  #define SBI_EXT_HSM                     0x48534D
 +#define SBI_EXT_DBCN                    0x4442434E
  /* SBI function IDs for BASE extension */
  #define SBI_EXT_BASE_GET_SPEC_VERSION   0x0
@@ -XXX,XX +XXX,XX @@
  #define SBI_EXT_HSM_HART_STOP           0x1
  #define SBI_EXT_HSM_HART_GET_STATUS     0x2
 +/* SBI function IDs for DBCN extension */
 +#define SBI_EXT_DBCN_CONSOLE_WRITE      0x0
 +#define SBI_EXT_DBCN_CONSOLE_READ       0x1
 +#define SBI_EXT_DBCN_CONSOLE_WRITE_BYTE 0x2
 +
  #define SBI_HSM_HART_STATUS_STARTED     0x0
  #define SBI_HSM_HART_STATUS_STOPPED     0x1
  #define SBI_HSM_HART_STATUS_START_PENDING   0x2
 diff --git a/target/riscv/kvm/kvm-cpu.c b/target/riscv/kvm/kvm-cpu.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/riscv/kvm/kvm-cpu.c
 +++ b/target/riscv/kvm/kvm-cpu.c
@@ -XXX,XX +XXX,XX @@ static KVMCPUConfig kvm_v_vlenb = {
                     KVM_REG_RISCV_VECTOR_CSR_REG(vlenb)
  };
 +static KVMCPUConfig kvm_sbi_dbcn = {
 +    .name = "sbi_dbcn",
 +    .kvm_reg_id = KVM_REG_RISCV | KVM_REG_SIZE_U64 |
 +                  KVM_REG_RISCV_SBI_EXT | KVM_RISCV_SBI_EXT_DBCN
 +};
 +
  static void kvm_riscv_update_cpu_cfg_isa_ext(RISCVCPU *cpu, CPUState *cs)
  {
      CPURISCVState *env = &cpu->env;
@@ -XXX,XX +XXX,XX @@ static int uint64_cmp(const void *a, const void *b)
      return 0;
  }
 +static void kvm_riscv_check_sbi_dbcn_support(RISCVCPU *cpu,
 +                                             KVMScratchCPU *kvmcpu,
 +                                             struct kvm_reg_list *reglist)
 +{
 +    struct kvm_reg_list *reg_search;
 +
 +    reg_search = bsearch(&kvm_sbi_dbcn.kvm_reg_id, reglist->reg, reglist->n,
 +                         sizeof(uint64_t), uint64_cmp);
 +
 +    if (reg_search) {
 +        kvm_sbi_dbcn.supported = true;
 +    }
 +}
 +
  static void kvm_riscv_read_vlenb(RISCVCPU *cpu, KVMScratchCPU *kvmcpu,
                                   struct kvm_reg_list *reglist)
  {
@@ -XXX,XX +XXX,XX @@ static void kvm_riscv_init_multiext_cfg(RISCVCPU *cpu, KVMScratchCPU *kvmcpu)
      if (riscv_has_ext(&cpu->env, RVV)) {
          kvm_riscv_read_vlenb(cpu, kvmcpu, reglist);
      }
 +
 +    kvm_riscv_check_sbi_dbcn_support(cpu, kvmcpu, reglist);
  }
  static void riscv_init_kvm_registers(Object *cpu_obj)
@@ -XXX,XX +XXX,XX @@ static int kvm_vcpu_set_machine_ids(RISCVCPU *cpu, CPUState *cs)
      return ret;
  }
 +static int kvm_vcpu_enable_sbi_dbcn(RISCVCPU *cpu, CPUState *cs)
 +{
 +    target_ulong reg = 1;
 +
 +    if (!kvm_sbi_dbcn.supported) {
 +        return 0;
 +    }
 +
 +    return kvm_set_one_reg(cs, kvm_sbi_dbcn.kvm_reg_id, &reg);
 +}
 +
  int kvm_arch_init_vcpu(CPUState *cs)
  {
      int ret = 0;
@@ -XXX,XX +XXX,XX @@ int kvm_arch_init_vcpu(CPUState *cs)
      kvm_riscv_update_cpu_misa_ext(cpu, cs);
      kvm_riscv_update_cpu_cfg_isa_ext(cpu, cs);
 +    ret = kvm_vcpu_enable_sbi_dbcn(cpu, cs);
 +
      return ret;
  }
@@ -XXX,XX +XXX,XX @@ bool kvm_arch_stop_on_emulation_error(CPUState *cs)
      return true;
  }
 +static void kvm_riscv_handle_sbi_dbcn(CPUState *cs, struct kvm_run *run)
 +{
 +    g_autofree uint8_t *buf = NULL;
 +    RISCVCPU *cpu = RISCV_CPU(cs);
 +    target_ulong num_bytes;
 +    uint64_t addr;
 +    unsigned char ch;
 +    int ret;
 +
 +    switch (run->riscv_sbi.function_id) {
 +    case SBI_EXT_DBCN_CONSOLE_READ:
 +    case SBI_EXT_DBCN_CONSOLE_WRITE:
 +        num_bytes = run->riscv_sbi.args[0];
 +
 +        if (num_bytes == 0) {
 +            run->riscv_sbi.ret[0] = SBI_SUCCESS;
 +            run->riscv_sbi.ret[1] = 0;
 +            break;
 +        }
 +
 +        addr = run->riscv_sbi.args[1];
 +
 +        /*
 +         * Handle the case where a 32 bit CPU is running in a
 +         * 64 bit addressing env.
 +         */
 +        if (riscv_cpu_mxl(&cpu->env) == MXL_RV32) {
 +            addr |= (uint64_t)run->riscv_sbi.args[2] << 32;
 +        }
 +
 +        buf = g_malloc0(num_bytes);
 +
 +        if (run->riscv_sbi.function_id == SBI_EXT_DBCN_CONSOLE_READ) {
 +            ret = qemu_chr_fe_read_all(serial_hd(0)->be, buf, num_bytes);
 +            if (ret < 0) {
 +                error_report("SBI_EXT_DBCN_CONSOLE_READ: error when "
 +                             "reading chardev");
 +                exit(1);
 +            }
 +
 +            cpu_physical_memory_write(addr, buf, ret);
 +        } else {
 +            cpu_physical_memory_read(addr, buf, num_bytes);
 +
 +            ret = qemu_chr_fe_write_all(serial_hd(0)->be, buf, num_bytes);
 +            if (ret < 0) {
 +                error_report("SBI_EXT_DBCN_CONSOLE_WRITE: error when "
 +                             "writing chardev");
 +                exit(1);
 +            }
 +        }
 +
 +        run->riscv_sbi.ret[0] = SBI_SUCCESS;
 +        run->riscv_sbi.ret[1] = ret;
 +        break;
 +    case SBI_EXT_DBCN_CONSOLE_WRITE_BYTE:
 +        ch = run->riscv_sbi.args[0];
 +        ret = qemu_chr_fe_write(serial_hd(0)->be, &ch, sizeof(ch));
 +
 +        if (ret < 0) {
 +            error_report("SBI_EXT_DBCN_CONSOLE_WRITE_BYTE: error when "
 +                         "writing chardev");
 +            exit(1);
 +        }
 +
 +        run->riscv_sbi.ret[0] = SBI_SUCCESS;
 +        run->riscv_sbi.ret[1] = 0;
 +        break;
 +    default:
 +        run->riscv_sbi.ret[0] = SBI_ERR_NOT_SUPPORTED;
 +    }
 +}
 +
  static int kvm_riscv_handle_sbi(CPUState *cs, struct kvm_run *run)
  {
      int ret = 0;
@@ -XXX,XX +XXX,XX @@ static int kvm_riscv_handle_sbi(CPUState *cs, struct kvm_run *run)
          }
          ret = 0;
          break;
 +    case SBI_EXT_DBCN:
 +        kvm_riscv_handle_sbi_dbcn(cs, run);
 +        break;
      default:
          qemu_log_mask(LOG_UNIMP,
                        "%s: un-handled SBI EXIT, specific reasons is %lu\n",
 --
 .45.1

-[PULL 01/10] hw/riscv: Update comment for qtest check in riscv_find_firmware()
+[PULL 05/28] hw/riscv/boot.c: Support 64-bit address for initrd
-From: Bin Meng <bmeng.cn@gmail.com>
+From: Cheng Yang <yangcheng.work@foxmail.com>
-Since commit 4211fc553234 ("roms/opensbi: Remove ELF images"), the
+Use qemu_fdt_setprop_u64() instead of qemu_fdt_setprop_cell()
-comment for qtest check in riscv_find_firmware() is out of date.
+to set the address of initrd in FDT to support 64-bit address.
 Update it to reflect the latest status.
-Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
+Signed-off-by: Cheng Yang <yangcheng.work@foxmail.com>
 Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
-Message-Id: <BN7PR08MB435525C92550BAC5467BE672BF219@BN7PR08MB4355.namprd08.prod.outlook.com>
+Message-ID: <tencent_A4482251DD0890F312758FA6B33F60815609@qq.com>
 Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
 ---
  hw/riscv/boot.c | 4 ++--
 file changed, 2 insertions(+), 2 deletions(-)
 diff --git a/hw/riscv/boot.c b/hw/riscv/boot.c
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/riscv/boot.c
 +++ b/hw/riscv/boot.c
-@@ -XXX,XX +XXX,XX @@ char *riscv_find_firmware(const char *firmware_filename)
+@@ -XXX,XX +XXX,XX @@ static void riscv_load_initrd(MachineState *machine, uint64_t kernel_entry)
-     if (filename == NULL) {
+     /* Some RISC-V machines (e.g. opentitan) don't have a fdt. */
-         if (!qtest_enabled()) {
+     if (fdt) {
-             /*
+         end = start + size;
--             * We only ship plain binary bios images in the QEMU source.
+-        qemu_fdt_setprop_cell(fdt, "/chosen", "linux,initrd-start", start);
--             * With Spike machine that uses ELF images as the default bios,
+-        qemu_fdt_setprop_cell(fdt, "/chosen", "linux,initrd-end", end);
-+             * We only ship OpenSBI binary bios images in the QEMU source.
++        qemu_fdt_setprop_u64(fdt, "/chosen", "linux,initrd-start", start);
-+             * For machines that use images other than the default bios,
++        qemu_fdt_setprop_u64(fdt, "/chosen", "linux,initrd-end", end);
-              * running QEMU test will complain hence let's suppress the error
+     }
-              * report for QEMU testing.
+ }
-              */
 --
-.37.3
+.45.1

-New patch
+[PULL 06/28] target/riscv: change RISCV_EXCP_SEMIHOST exception number to 63
+From: Clément Léger <cleger@rivosinc.com>
+The current semihost exception number (16) is a reserved number (range
+[16-17]). The upcoming double trap specification uses that number for
+the double trap exception. Since the privileged spec (Table 22) defines
+ranges for custom uses change the semihosting exception number to 63
+which belongs to the range [48-63] in order to avoid any future
+collisions with reserved exception.
+Signed-off-by: Clément Léger <cleger@rivosinc.com>
+Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
+Message-ID: <20240422135840.1959967-1-cleger@rivosinc.com>
+Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
+---
+ target/riscv/cpu_bits.h | 2 +-
+file changed, 1 insertion(+), 1 deletion(-)
+diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
+index XXXXXXX..XXXXXXX 100644
+--- a/target/riscv/cpu_bits.h
++++ b/target/riscv/cpu_bits.h
+@@ -XXX,XX +XXX,XX @@ typedef enum RISCVException {
+     RISCV_EXCP_INST_PAGE_FAULT = 0xc, /* since: priv-1.10.0 */
+     RISCV_EXCP_LOAD_PAGE_FAULT = 0xd, /* since: priv-1.10.0 */
+     RISCV_EXCP_STORE_PAGE_FAULT = 0xf, /* since: priv-1.10.0 */
+-    RISCV_EXCP_SEMIHOST = 0x10,
+     RISCV_EXCP_INST_GUEST_PAGE_FAULT = 0x14,
+     RISCV_EXCP_LOAD_GUEST_ACCESS_FAULT = 0x15,
+     RISCV_EXCP_VIRT_INSTRUCTION_FAULT = 0x16,
+     RISCV_EXCP_STORE_GUEST_AMO_ACCESS_FAULT = 0x17,
++    RISCV_EXCP_SEMIHOST = 0x3f,
+ } RISCVException;
+ #define RISCV_EXCP_INT_FLAG                0x80000000
+--
+.45.1

-New patch
+[PULL 07/28] target/riscv/kvm: tolerate KVM disable ext errors
+From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
+Running a KVM guest using a 6.9-rc3 kernel, in a 6.8 host that has zkr
+enabled, will fail with a kernel oops SIGILL right at the start. The
+reason is that we can't expose zkr without implementing the SEED CSR.
+Disabling zkr in the guest would be a workaround, but if the KVM doesn't
+allow it we'll error out and never boot.
+In hindsight this is too strict. If we keep proceeding, despite not
+disabling the extension in the KVM vcpu, we'll not add the extension in
+the riscv,isa. The guest kernel will be unaware of the extension, i.e.
+it doesn't matter if the KVM vcpu has it enabled underneath or not. So
+it's ok to keep booting in this case.
+Change our current logic to not error out if we fail to disable an
+extension in kvm_set_one_reg(), but show a warning and keep booting. It
+is important to throw a warning because we must make the user aware that
+the extension is still available in the vcpu, meaning that an
+ill-behaved guest can ignore the riscv,isa settings and  use the
+extension.
+The case we're handling happens with an EINVAL error code. If we fail to
+disable the extension in KVM for any other reason, error out.
+We'll also keep erroring out when we fail to enable an extension in KVM,
+since adding the extension in riscv,isa at this point will cause a guest
+malfunction because the extension isn't enabled in the vcpu.
+Suggested-by: Andrew Jones <ajones@ventanamicro.com>
+Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
+Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
+Cc: qemu-stable <qemu-stable@nongnu.org>
+Message-ID: <20240422171425.333037-2-dbarboza@ventanamicro.com>
+Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
+---
+ target/riscv/kvm/kvm-cpu.c | 12 ++++++++----
+file changed, 8 insertions(+), 4 deletions(-)
+diff --git a/target/riscv/kvm/kvm-cpu.c b/target/riscv/kvm/kvm-cpu.c
+index XXXXXXX..XXXXXXX 100644
+--- a/target/riscv/kvm/kvm-cpu.c
++++ b/target/riscv/kvm/kvm-cpu.c
+@@ -XXX,XX +XXX,XX @@ static void kvm_riscv_update_cpu_cfg_isa_ext(RISCVCPU *cpu, CPUState *cs)
+         reg = kvm_cpu_cfg_get(cpu, multi_ext_cfg);
+         ret = kvm_set_one_reg(cs, id, &reg);
+         if (ret != 0) {
+-            error_report("Unable to %s extension %s in KVM, error %d",
+-                         reg ? "enable" : "disable",
+-                         multi_ext_cfg->name, ret);
+-            exit(EXIT_FAILURE);
++            if (!reg && ret == -EINVAL) {
++                warn_report("KVM cannot disable extension %s",
++                            multi_ext_cfg->name);
++            } else {
++                error_report("Unable to enable extension %s in KVM, error %d",
++                             multi_ext_cfg->name, ret);
++                exit(EXIT_FAILURE);
++            }
+         }
+     }
+ }
+--
+.45.1

-New patch
+[PULL 08/28] target/riscv/debug: set tval=pc in breakpoint exceptions
+From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
+We're not setting (s/m)tval when triggering breakpoints of type 2
+(mcontrol) and 6 (mcontrol6). According to the debug spec section
+.7.12, "Match Control Type 6":
+"The Privileged Spec says that breakpoint exceptions that occur on
+instruction fetches, loads, or stores update the tval CSR with either
+zero or the faulting virtual address. The faulting virtual address for
+an mcontrol6 trigger with action = 0 is the address being accessed and
+which caused that trigger to fire."
+A similar text is also found in the Debug spec section 5.7.11 w.r.t.
+mcontrol.
+Note that what we're doing ATM is not violating the spec, but it's
+simple enough to set mtval/stval and it makes life easier for any
+software that relies on this info.
+Given that we always use action = 0, save the faulting address for the
+mcontrol and mcontrol6 trigger breakpoints into env->badaddr, which is
+used as as scratch area for traps with address information. 'tval' is
+then set during riscv_cpu_do_interrupt().
+Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
+Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
+Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
+Message-ID: <20240416230437.1869024-2-dbarboza@ventanamicro.com>
+Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
+---
+ target/riscv/cpu_helper.c | 1 +
+ target/riscv/debug.c      | 3 +++
+files changed, 4 insertions(+)
+diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
+index XXXXXXX..XXXXXXX 100644
+--- a/target/riscv/cpu_helper.c
++++ b/target/riscv/cpu_helper.c
+@@ -XXX,XX +XXX,XX @@ void riscv_cpu_do_interrupt(CPUState *cs)
+             tval = env->bins;
+             break;
+         case RISCV_EXCP_BREAKPOINT:
++            tval = env->badaddr;
+             if (cs->watchpoint_hit) {
+                 tval = cs->watchpoint_hit->hitaddr;
+                 cs->watchpoint_hit = NULL;
+diff --git a/target/riscv/debug.c b/target/riscv/debug.c
+index XXXXXXX..XXXXXXX 100644
+--- a/target/riscv/debug.c
++++ b/target/riscv/debug.c
+@@ -XXX,XX +XXX,XX @@ bool riscv_cpu_debug_check_breakpoint(CPUState *cs)
+                 if ((ctrl & TYPE2_EXEC) && (bp->pc == pc)) {
+                     /* check U/S/M bit against current privilege level */
+                     if ((ctrl >> 3) & BIT(env->priv)) {
++                        env->badaddr = pc;
+                         return true;
+                     }
+                 }
+@@ -XXX,XX +XXX,XX @@ bool riscv_cpu_debug_check_breakpoint(CPUState *cs)
+                     if (env->virt_enabled) {
+                         /* check VU/VS bit against current privilege level */
+                         if ((ctrl >> 23) & BIT(env->priv)) {
++                            env->badaddr = pc;
+                             return true;
+                         }
+                     } else {
+                         /* check U/S/M bit against current privilege level */
+                         if ((ctrl >> 3) & BIT(env->priv)) {
++                            env->badaddr = pc;
+                             return true;
+                         }
+                     }
+--
+.45.1

-New patch
+[PULL 09/28] trans_privileged.c.inc: set (m|s)tval on ebreak breakpoint
+From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
+Privileged spec section 4.1.9 mentions:
+"When a trap is taken into S-mode, stval is written with
+exception-specific information to assist software in handling the trap.
+(...)
+If stval is written with a nonzero value when a breakpoint,
+address-misaligned, access-fault, or page-fault exception occurs on an
+instruction fetch, load, or store, then stval will contain the faulting
+virtual address."
+A similar text is found for mtval in section 3.1.16.
+Setting mtval/stval in this scenario is optional, but some softwares read
+these regs when handling ebreaks.
+Write 'badaddr' in all ebreak breakpoints to write the appropriate
+'tval' during riscv_do_cpu_interrrupt().
+Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
+Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
+Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
+Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
+Message-ID: <20240416230437.1869024-3-dbarboza@ventanamicro.com>
+Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
+---
+ target/riscv/insn_trans/trans_privileged.c.inc | 2 ++
+file changed, 2 insertions(+)
+diff --git a/target/riscv/insn_trans/trans_privileged.c.inc b/target/riscv/insn_trans/trans_privileged.c.inc
+index XXXXXXX..XXXXXXX 100644
+--- a/target/riscv/insn_trans/trans_privileged.c.inc
++++ b/target/riscv/insn_trans/trans_privileged.c.inc
+@@ -XXX,XX +XXX,XX @@ static bool trans_ebreak(DisasContext *ctx, arg_ebreak *a)
+     if (pre == 0x01f01013 && ebreak == 0x00100073 && post == 0x40705013) {
+         generate_exception(ctx, RISCV_EXCP_SEMIHOST);
+     } else {
++        tcg_gen_st_tl(tcg_constant_tl(ebreak_addr), tcg_env,
++                      offsetof(CPURISCVState, badaddr));
+         generate_exception(ctx, RISCV_EXCP_BREAKPOINT);
+     }
+     return true;
+--
+.45.1

-[PULL 10/10] target/riscv: pmp: Fixup TLB size calculation
+[PULL 10/28] target/riscv: Add support for Zve32x extension
-From: Alistair Francis <alistair.francis@wdc.com>
+From: Jason Chien <jason.chien@sifive.com>
-Since commit 4047368938f6 "accel/tcg: Introduce tlb_set_page_full" we
+Add support for Zve32x extension and replace some checks for Zve32f with
-have been seeing this assert
+Zve32x, since Zve32f depends on Zve32x.
-    ../accel/tcg/cputlb.c:1294: tlb_set_page_with_attrs: Assertion `is_power_of_2(size)' failed.
+Signed-off-by: Jason Chien <jason.chien@sifive.com>
 Reviewed-by: Frank Chang <frank.chang@sifive.com>
 Reviewed-by: Max Chou <max.chou@sifive.com>
 Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
 Message-ID: <20240328022343.6871-2-jason.chien@sifive.com>
 Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
 ---
  target/riscv/cpu_cfg.h                  |  1 +
  target/riscv/cpu.c                      |  2 ++
  target/riscv/cpu_helper.c               |  2 +-
  target/riscv/csr.c                      |  2 +-
  target/riscv/tcg/tcg-cpu.c              | 16 ++++++++--------
  target/riscv/insn_trans/trans_rvv.c.inc |  4 ++--
 files changed, 15 insertions(+), 12 deletions(-)
-When running Tock on the OpenTitan machine.
+diff --git a/target/riscv/cpu_cfg.h b/target/riscv/cpu_cfg.h
 The issue is that pmp_get_tlb_size() would return a TLB size that wasn't
 a power of 2. The size was also smaller then TARGET_PAGE_SIZE.
 This patch ensures that any TLB size less then TARGET_PAGE_SIZE is
 rounded down to 1 to ensure it's a valid size.
 Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
 Reviewed-by: LIU Zhiwei<zhiwei_liu@linux.alibaba.com>
 Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
 Message-id: 20221012011449.506928-1-alistair.francis@opensource.wdc.com
 Message-Id: <20221012011449.506928-1-alistair.francis@opensource.wdc.com>
 ---
  target/riscv/pmp.c | 12 ++++++++++++
 file changed, 12 insertions(+)
 diff --git a/target/riscv/pmp.c b/target/riscv/pmp.c
 index XXXXXXX..XXXXXXX 100644
---- a/target/riscv/pmp.c
+--- a/target/riscv/cpu_cfg.h
-+++ b/target/riscv/pmp.c
++++ b/target/riscv/cpu_cfg.h
-@@ -XXX,XX +XXX,XX @@ bool pmp_is_range_in_tlb(CPURISCVState *env, hwaddr tlb_sa,
+@@ -XXX,XX +XXX,XX @@ struct RISCVCPUConfig {
      bool ext_zhinx;
      bool ext_zhinxmin;
      bool ext_zve32f;
 +    bool ext_zve32x;
      bool ext_zve64f;
      bool ext_zve64d;
      bool ext_zvbb;
 diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/riscv/cpu.c
 +++ b/target/riscv/cpu.c
@@ -XXX,XX +XXX,XX @@ const RISCVIsaExtData isa_edata_arr[] = {
      ISA_EXT_DATA_ENTRY(zvbb, PRIV_VERSION_1_12_0, ext_zvbb),
      ISA_EXT_DATA_ENTRY(zvbc, PRIV_VERSION_1_12_0, ext_zvbc),
      ISA_EXT_DATA_ENTRY(zve32f, PRIV_VERSION_1_10_0, ext_zve32f),
 +    ISA_EXT_DATA_ENTRY(zve32x, PRIV_VERSION_1_10_0, ext_zve32x),
      ISA_EXT_DATA_ENTRY(zve64f, PRIV_VERSION_1_10_0, ext_zve64f),
      ISA_EXT_DATA_ENTRY(zve64d, PRIV_VERSION_1_10_0, ext_zve64d),
      ISA_EXT_DATA_ENTRY(zvfbfmin, PRIV_VERSION_1_12_0, ext_zvfbfmin),
@@ -XXX,XX +XXX,XX @@ const RISCVCPUMultiExtConfig riscv_cpu_extensions[] = {
      MULTI_EXT_CFG_BOOL("zfh", ext_zfh, false),
      MULTI_EXT_CFG_BOOL("zfhmin", ext_zfhmin, false),
      MULTI_EXT_CFG_BOOL("zve32f", ext_zve32f, false),
 +    MULTI_EXT_CFG_BOOL("zve32x", ext_zve32x, false),
      MULTI_EXT_CFG_BOOL("zve64f", ext_zve64f, false),
      MULTI_EXT_CFG_BOOL("zve64d", ext_zve64d, false),
      MULTI_EXT_CFG_BOOL("zvfbfmin", ext_zvfbfmin, false),
 diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/riscv/cpu_helper.c
 +++ b/target/riscv/cpu_helper.c
@@ -XXX,XX +XXX,XX @@ void cpu_get_tb_cpu_state(CPURISCVState *env, vaddr *pc,
      *pc = env->xl == MXL_RV32 ? env->pc & UINT32_MAX : env->pc;
      *cs_base = 0;
 -    if (cpu->cfg.ext_zve32f) {
 +    if (cpu->cfg.ext_zve32x) {
          /*
           * If env->vl equals to VLMAX, we can use generic vector operation
           * expanders (GVEC) to accerlate the vector operations.
 diff --git a/target/riscv/csr.c b/target/riscv/csr.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/riscv/csr.c
 +++ b/target/riscv/csr.c
@@ -XXX,XX +XXX,XX @@ static RISCVException fs(CPURISCVState *env, int csrno)
  static RISCVException vs(CPURISCVState *env, int csrno)
  {
 -    if (riscv_cpu_cfg(env)->ext_zve32f) {
 +    if (riscv_cpu_cfg(env)->ext_zve32x) {
  #if !defined(CONFIG_USER_ONLY)
          if (!env->debugger && !riscv_cpu_vector_enabled(env)) {
              return RISCV_EXCP_ILLEGAL_INST;
 diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/riscv/tcg/tcg-cpu.c
 +++ b/target/riscv/tcg/tcg-cpu.c
@@ -XXX,XX +XXX,XX @@ void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp)
          return;
      }
-     if (*tlb_size != 0) {
+-    if (cpu->cfg.ext_zve32f && !riscv_has_ext(env, RVF)) {
-+        /*
+-        error_setg(errp, "Zve32f/Zve64f extensions require F extension");
-+         * At this point we have a tlb_size that is the smallest possible size
+-        return;
-+         * That fits within a TARGET_PAGE_SIZE and the PMP region.
++    /* The Zve32f extension depends on the Zve32x extension */
-+         *
++    if (cpu->cfg.ext_zve32f) {
-+         * If the size is less then TARGET_PAGE_SIZE we drop the size to 1.
++        if (!riscv_has_ext(env, RVF)) {
-+         * This means the result isn't cached in the TLB and is only used for
++            error_setg(errp, "Zve32f/Zve64f extensions require F extension");
-+         * a single translation.
++            return;
 +         */
 +        if (*tlb_size < TARGET_PAGE_SIZE) {
 +            *tlb_size = 1;
 +        }
-+
++        cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zve32x), true);
          return true;
      }
+     if (cpu->cfg.ext_zvfh) {
+@@ -XXX,XX +XXX,XX @@ void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp)
+         cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zvbc), true);
+     }
+-    /*
+-     * In principle Zve*x would also suffice here, were they supported
+-     * in qemu
+-     */
+     if ((cpu->cfg.ext_zvbb || cpu->cfg.ext_zvkb || cpu->cfg.ext_zvkg ||
+          cpu->cfg.ext_zvkned || cpu->cfg.ext_zvknha || cpu->cfg.ext_zvksed ||
+-         cpu->cfg.ext_zvksh) && !cpu->cfg.ext_zve32f) {
++         cpu->cfg.ext_zvksh) && !cpu->cfg.ext_zve32x) {
+         error_setg(errp,
+                    "Vector crypto extensions require V or Zve* extensions");
+         return;
+diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc
+index XXXXXXX..XXXXXXX 100644
+--- a/target/riscv/insn_trans/trans_rvv.c.inc
++++ b/target/riscv/insn_trans/trans_rvv.c.inc
+@@ -XXX,XX +XXX,XX @@ static bool do_vsetvl(DisasContext *s, int rd, int rs1, TCGv s2)
+ {
+     TCGv s1, dst;
+-    if (!require_rvv(s) || !s->cfg_ptr->ext_zve32f) {
++    if (!require_rvv(s) || !s->cfg_ptr->ext_zve32x) {
+         return false;
+     }
+@@ -XXX,XX +XXX,XX @@ static bool do_vsetivli(DisasContext *s, int rd, TCGv s1, TCGv s2)
+ {
+     TCGv dst;
+-    if (!require_rvv(s) || !s->cfg_ptr->ext_zve32f) {
++    if (!require_rvv(s) || !s->cfg_ptr->ext_zve32x) {
+         return false;
+     }
 --
-.37.3
+.45.1

-[PULL 05/10] hw/riscv: virt: Move create_fw_cfg() prior to loading kernel
+[PULL 11/28] target/riscv: Add support for Zve64x extension
-From: Sunil V L <sunilvl@ventanamicro.com>
+From: Jason Chien <jason.chien@sifive.com>
-To enable both -kernel and -pflash options, the fw_cfg needs to be
+Add support for Zve64x extension. Enabling Zve64f enables Zve64x and
-created prior to loading the kernel.
+enabling Zve64x enables Zve32x according to their dependency.
-Signed-off-by: Sunil V L <sunilvl@ventanamicro.com>
+Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2107
-Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
+Signed-off-by: Jason Chien <jason.chien@sifive.com>
-Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
+Reviewed-by: Frank Chang <frank.chang@sifive.com>
-Message-Id: <20221004092351.18209-3-sunilvl@ventanamicro.com>
+Reviewed-by: Max Chou <max.chou@sifive.com>
 Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
 Message-ID: <20240328022343.6871-3-jason.chien@sifive.com>
 Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
 ---
- hw/riscv/virt.c | 14 +++++++-------
+ target/riscv/cpu_cfg.h     |  1 +
-file changed, 7 insertions(+), 7 deletions(-)
+ target/riscv/cpu.c         |  2 ++
  target/riscv/tcg/tcg-cpu.c | 17 +++++++++++------
 files changed, 14 insertions(+), 6 deletions(-)
-diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
+diff --git a/target/riscv/cpu_cfg.h b/target/riscv/cpu_cfg.h
 index XXXXXXX..XXXXXXX 100644
---- a/hw/riscv/virt.c
+--- a/target/riscv/cpu_cfg.h
-+++ b/hw/riscv/virt.c
++++ b/target/riscv/cpu_cfg.h
-@@ -XXX,XX +XXX,XX @@ static void virt_machine_done(Notifier *notifier, void *data)
+@@ -XXX,XX +XXX,XX @@ struct RISCVCPUConfig {
-                                     RISCV64_BIOS_BIN, start_addr, NULL);
+     bool ext_zve32x;
      bool ext_zve64f;
      bool ext_zve64d;
 +    bool ext_zve64x;
      bool ext_zvbb;
      bool ext_zvbc;
      bool ext_zvkb;
 diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/riscv/cpu.c
 +++ b/target/riscv/cpu.c
@@ -XXX,XX +XXX,XX @@ const RISCVIsaExtData isa_edata_arr[] = {
      ISA_EXT_DATA_ENTRY(zve32x, PRIV_VERSION_1_10_0, ext_zve32x),
      ISA_EXT_DATA_ENTRY(zve64f, PRIV_VERSION_1_10_0, ext_zve64f),
      ISA_EXT_DATA_ENTRY(zve64d, PRIV_VERSION_1_10_0, ext_zve64d),
 +    ISA_EXT_DATA_ENTRY(zve64x, PRIV_VERSION_1_10_0, ext_zve64x),
      ISA_EXT_DATA_ENTRY(zvfbfmin, PRIV_VERSION_1_12_0, ext_zvfbfmin),
      ISA_EXT_DATA_ENTRY(zvfbfwma, PRIV_VERSION_1_12_0, ext_zvfbfwma),
      ISA_EXT_DATA_ENTRY(zvfh, PRIV_VERSION_1_12_0, ext_zvfh),
@@ -XXX,XX +XXX,XX @@ const RISCVCPUMultiExtConfig riscv_cpu_extensions[] = {
      MULTI_EXT_CFG_BOOL("zve32x", ext_zve32x, false),
      MULTI_EXT_CFG_BOOL("zve64f", ext_zve64f, false),
      MULTI_EXT_CFG_BOOL("zve64d", ext_zve64d, false),
 +    MULTI_EXT_CFG_BOOL("zve64x", ext_zve64x, false),
      MULTI_EXT_CFG_BOOL("zvfbfmin", ext_zvfbfmin, false),
      MULTI_EXT_CFG_BOOL("zvfbfwma", ext_zvfbfwma, false),
      MULTI_EXT_CFG_BOOL("zvfh", ext_zvfh, false),
 diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/riscv/tcg/tcg-cpu.c
 +++ b/target/riscv/tcg/tcg-cpu.c
@@ -XXX,XX +XXX,XX @@ void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp)
      /* The Zve64d extension depends on the Zve64f extension */
      if (cpu->cfg.ext_zve64d) {
 +        if (!riscv_has_ext(env, RVD)) {
 +            error_setg(errp, "Zve64d/V extensions require D extension");
 +            return;
 +        }
          cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zve64f), true);
      }
-+    /*
+-    /* The Zve64f extension depends on the Zve32f extension */
-+     * Init fw_cfg.  Must be done before riscv_load_fdt, otherwise the device
++    /* The Zve64f extension depends on the Zve64x and Zve32f extensions */
-+     * tree cannot be altered and we get FDT_ERR_NOSPACE.
+     if (cpu->cfg.ext_zve64f) {
-+     */
++        cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zve64x), true);
-+    s->fw_cfg = create_fw_cfg(machine);
+         cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zve32f), true);
 +    rom_set_fw(s->fw_cfg);
 +
      if (machine->kernel_filename) {
          kernel_start_addr = riscv_calc_kernel_start_addr(&s->soc[0],
                                                           firmware_end_addr);
@@ -XXX,XX +XXX,XX @@ static void virt_machine_done(Notifier *notifier, void *data)
          start_addr = virt_memmap[VIRT_FLASH].base;
      }
--    /*
+-    if (cpu->cfg.ext_zve64d && !riscv_has_ext(env, RVD)) {
--     * Init fw_cfg.  Must be done before riscv_load_fdt, otherwise the device
+-        error_setg(errp, "Zve64d/V extensions require D extension");
--     * tree cannot be altered and we get FDT_ERR_NOSPACE.
+-        return;
--     */
++    /* The Zve64x extension depends on the Zve32x extension */
--    s->fw_cfg = create_fw_cfg(machine);
++    if (cpu->cfg.ext_zve64x) {
--    rom_set_fw(s->fw_cfg);
++        cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zve32x), true);
--
+     }
-     /* Compute the fdt load address in dram */
-     fdt_load_addr = riscv_load_fdt(memmap[VIRT_DRAM].base,
+     /* The Zve32f extension depends on the Zve32x extension */
-                                    machine->ram_size, machine->fdt);
+@@ -XXX,XX +XXX,XX @@ void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp)
          return;
      }
 -    if ((cpu->cfg.ext_zvbc || cpu->cfg.ext_zvknhb) && !cpu->cfg.ext_zve64f) {
 +    if ((cpu->cfg.ext_zvbc || cpu->cfg.ext_zvknhb) && !cpu->cfg.ext_zve64x) {
          error_setg(
              errp,
 -            "Zvbc and Zvknhb extensions require V or Zve64{f,d} extensions");
 +            "Zvbc and Zvknhb extensions require V or Zve64x extensions");
          return;
      }
 --
-.37.3
+.45.1

-New patch
+[PULL 12/28] target/riscv: Relax vector register check in RISCV gdbstub
+From: Jason Chien <jason.chien@sifive.com>
+In current implementation, the gdbstub allows reading vector registers
+only if V extension is supported. However, all vector extensions and
+vector crypto extensions have the vector registers and they all depend
+on Zve32x. The gdbstub should check for Zve32x instead.
+Signed-off-by: Jason Chien <jason.chien@sifive.com>
+Reviewed-by: Frank Chang <frank.chang@sifive.com>
+Reviewed-by: Max Chou <max.chou@sifive.com>
+Message-ID: <20240328022343.6871-4-jason.chien@sifive.com>
+Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
+---
+ target/riscv/gdbstub.c | 2 +-
+file changed, 1 insertion(+), 1 deletion(-)
+diff --git a/target/riscv/gdbstub.c b/target/riscv/gdbstub.c
+index XXXXXXX..XXXXXXX 100644
+--- a/target/riscv/gdbstub.c
++++ b/target/riscv/gdbstub.c
+@@ -XXX,XX +XXX,XX @@ void riscv_cpu_register_gdb_regs_for_features(CPUState *cs)
+                                  gdb_find_static_feature("riscv-32bit-fpu.xml"),
+);
+     }
+-    if (env->misa_ext & RVV) {
++    if (cpu->cfg.ext_zve32x) {
+         gdb_register_coprocessor(cs, riscv_gdb_get_vector,
+                                  riscv_gdb_set_vector,
+                                  ricsv_gen_dynamic_vector_feature(cs, cs->gdb_num_regs),
+--
+.45.1

-New patch
+[PULL 13/28] target/riscv: Fix the element agnostic function problem
+From: Huang Tao <eric.huang@linux.alibaba.com>
+In RVV and vcrypto instructions, the masked and tail elements are set to 1s
+using vext_set_elems_1s function if the vma/vta bit is set. It is the element
+agnostic policy.
+However, this function can't deal the big endian situation. This patch fixes
+the problem by adding handling of such case.
+Signed-off-by: Huang Tao <eric.huang@linux.alibaba.com>
+Suggested-by: Richard Henderson <richard.henderson@linaro.org>
+Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
+Cc: qemu-stable <qemu-stable@nongnu.org>
+Message-ID: <20240325021654.6594-1-eric.huang@linux.alibaba.com>
+Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
+---
+ target/riscv/vector_internals.c | 22 ++++++++++++++++++++++
+file changed, 22 insertions(+)
+diff --git a/target/riscv/vector_internals.c b/target/riscv/vector_internals.c
+index XXXXXXX..XXXXXXX 100644
+--- a/target/riscv/vector_internals.c
++++ b/target/riscv/vector_internals.c
+@@ -XXX,XX +XXX,XX @@ void vext_set_elems_1s(void *base, uint32_t is_agnostic, uint32_t cnt,
+     if (tot - cnt == 0) {
+         return ;
+     }
++
++    if (HOST_BIG_ENDIAN) {
++        /*
++         * Deal the situation when the elements are insdie
++         * only one uint64 block including setting the
++         * masked-off element.
++         */
++        if (((tot - 1) ^ cnt) < 8) {
++            memset(base + H1(tot - 1), -1, tot - cnt);
++            return;
++        }
++        /*
++         * Otherwise, at least cross two uint64_t blocks.
++         * Set first unaligned block.
++         */
++        if (cnt % 8 != 0) {
++            uint32_t j = ROUND_UP(cnt, 8);
++            memset(base + H1(j - 1), -1, j - cnt);
++            cnt = j;
++        }
++        /* Set other 64bit aligend blocks */
++    }
+     memset(base + cnt, -1, tot - cnt);
+ }
+--
+.45.1

-New patch
+[PULL 14/28] target/riscv/cpu.c: fix Zvkb extension config
+From: Yangyu Chen <cyy@cyyself.name>
+This code has a typo that writes zvkb to zvkg, causing users can't
+enable zvkb through the config. This patch gets this fixed.
+Signed-off-by: Yangyu Chen <cyy@cyyself.name>
+Fixes: ea61ef7097d0 ("target/riscv: Move vector crypto extensions to riscv_cpu_extensions")
+Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
+Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
+Reviewed-by: Max Chou <max.chou@sifive.com>
+Reviewed-by:  Weiwei Li <liwei1518@gmail.com>
+Message-ID: <tencent_7E34EEF0F90B9A68BF38BEE09EC6D4877C0A@qq.com>
+Cc: qemu-stable <qemu-stable@nongnu.org>
+Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
+---
+ target/riscv/cpu.c | 2 +-
+file changed, 1 insertion(+), 1 deletion(-)
+diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
+index XXXXXXX..XXXXXXX 100644
+--- a/target/riscv/cpu.c
++++ b/target/riscv/cpu.c
+@@ -XXX,XX +XXX,XX @@ const RISCVCPUMultiExtConfig riscv_cpu_extensions[] = {
+     /* Vector cryptography extensions */
+     MULTI_EXT_CFG_BOOL("zvbb", ext_zvbb, false),
+     MULTI_EXT_CFG_BOOL("zvbc", ext_zvbc, false),
+-    MULTI_EXT_CFG_BOOL("zvkb", ext_zvkg, false),
++    MULTI_EXT_CFG_BOOL("zvkb", ext_zvkb, false),
+     MULTI_EXT_CFG_BOOL("zvkg", ext_zvkg, false),
+     MULTI_EXT_CFG_BOOL("zvkned", ext_zvkned, false),
+     MULTI_EXT_CFG_BOOL("zvknha", ext_zvknha, false),
+--
+.45.1

-New patch
+[PULL 15/28] target/riscv: Implement dynamic establishment of custom decoder
+From: Huang Tao <eric.huang@linux.alibaba.com>
+In this patch, we modify the decoder to be a freely composable data
+structure instead of a hardcoded one. It can be dynamically builded up
+according to the extensions.
+This approach has several benefits:
+. Provides support for heterogeneous cpu architectures. As we add decoder in
+   RISCVCPU, each cpu can have their own decoder, and the decoders can be
+   different due to cpu's features.
+. Improve the decoding efficiency. We run the guard_func to see if the decoder
+   can be added to the dynamic_decoder when building up the decoder. Therefore,
+   there is no need to run the guard_func when decoding each instruction. It can
+   improve the decoding efficiency
+. For vendor or dynamic cpus, it allows them to customize their own decoder
+   functions to improve decoding efficiency, especially when vendor-defined
+   instruction sets increase. Because of dynamic building up, it can skip the other
+   decoder guard functions when decoding.
+. Pre patch for allowing adding a vendor decoder before decode_insn32() with minimal
+   overhead for users that don't need this particular vendor decoder.
+Signed-off-by: Huang Tao <eric.huang@linux.alibaba.com>
+Suggested-by: Christoph Muellner <christoph.muellner@vrull.eu>
+Co-authored-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
+Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
+Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
+Message-ID: <20240506023607.29544-1-eric.huang@linux.alibaba.com>
+Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
+---
+ target/riscv/cpu.h         |  1 +
+ target/riscv/tcg/tcg-cpu.h | 15 +++++++++++++++
+ target/riscv/cpu.c         |  1 +
+ target/riscv/tcg/tcg-cpu.c | 15 +++++++++++++++
+ target/riscv/translate.c   | 31 +++++++++++++++----------------
+files changed, 47 insertions(+), 16 deletions(-)
+diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
+index XXXXXXX..XXXXXXX 100644
+--- a/target/riscv/cpu.h
++++ b/target/riscv/cpu.h
+@@ -XXX,XX +XXX,XX @@ struct ArchCPU {
+     uint32_t pmu_avail_ctrs;
+     /* Mapping of events to counters */
+     GHashTable *pmu_event_ctr_map;
++    const GPtrArray *decoders;
+ };
+ /**
+diff --git a/target/riscv/tcg/tcg-cpu.h b/target/riscv/tcg/tcg-cpu.h
+index XXXXXXX..XXXXXXX 100644
+--- a/target/riscv/tcg/tcg-cpu.h
++++ b/target/riscv/tcg/tcg-cpu.h
+@@ -XXX,XX +XXX,XX @@ void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp);
+ void riscv_tcg_cpu_finalize_features(RISCVCPU *cpu, Error **errp);
+ bool riscv_cpu_tcg_compatible(RISCVCPU *cpu);
++struct DisasContext;
++struct RISCVCPUConfig;
++typedef struct RISCVDecoder {
++    bool (*guard_func)(const struct RISCVCPUConfig *);
++    bool (*riscv_cpu_decode_fn)(struct DisasContext *, uint32_t);
++} RISCVDecoder;
++
++typedef bool (*riscv_cpu_decode_fn)(struct DisasContext *, uint32_t);
++
++extern const size_t decoder_table_size;
++
++extern const RISCVDecoder decoder_table[];
++
++void riscv_tcg_cpu_finalize_dynamic_decoder(RISCVCPU *cpu);
++
+ #endif
+diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
+index XXXXXXX..XXXXXXX 100644
+--- a/target/riscv/cpu.c
++++ b/target/riscv/cpu.c
+@@ -XXX,XX +XXX,XX @@ void riscv_cpu_finalize_features(RISCVCPU *cpu, Error **errp)
+             error_propagate(errp, local_err);
+             return;
+         }
++        riscv_tcg_cpu_finalize_dynamic_decoder(cpu);
+     } else if (kvm_enabled()) {
+         riscv_kvm_cpu_finalize_features(cpu, &local_err);
+         if (local_err != NULL) {
+diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c
+index XXXXXXX..XXXXXXX 100644
+--- a/target/riscv/tcg/tcg-cpu.c
++++ b/target/riscv/tcg/tcg-cpu.c
+@@ -XXX,XX +XXX,XX @@ void riscv_tcg_cpu_finalize_features(RISCVCPU *cpu, Error **errp)
+     }
+ }
++void riscv_tcg_cpu_finalize_dynamic_decoder(RISCVCPU *cpu)
++{
++    GPtrArray *dynamic_decoders;
++    dynamic_decoders = g_ptr_array_sized_new(decoder_table_size);
++    for (size_t i = 0; i < decoder_table_size; ++i) {
++        if (decoder_table[i].guard_func &&
++            decoder_table[i].guard_func(&cpu->cfg)) {
++            g_ptr_array_add(dynamic_decoders,
++                            (gpointer)decoder_table[i].riscv_cpu_decode_fn);
++        }
++    }
++
++    cpu->decoders = dynamic_decoders;
++}
++
+ bool riscv_cpu_tcg_compatible(RISCVCPU *cpu)
+ {
+     return object_dynamic_cast(OBJECT(cpu), TYPE_RISCV_CPU_HOST) == NULL;
+diff --git a/target/riscv/translate.c b/target/riscv/translate.c
+index XXXXXXX..XXXXXXX 100644
+--- a/target/riscv/translate.c
++++ b/target/riscv/translate.c
+@@ -XXX,XX +XXX,XX @@
+ #include "exec/helper-info.c.inc"
+ #undef  HELPER_H
++#include "tcg/tcg-cpu.h"
++
+ /* global register indices */
+ static TCGv cpu_gpr[32], cpu_gprh[32], cpu_pc, cpu_vl, cpu_vstart;
+ static TCGv_i64 cpu_fpr[32]; /* assume F and D extensions */
+@@ -XXX,XX +XXX,XX @@ typedef struct DisasContext {
+     /* FRM is known to contain a valid value. */
+     bool frm_valid;
+     bool insn_start_updated;
++    const GPtrArray *decoders;
+ } DisasContext;
+ static inline bool has_ext(DisasContext *ctx, uint32_t ext)
+@@ -XXX,XX +XXX,XX @@ static inline int insn_len(uint16_t first_word)
+     return (first_word & 3) == 3 ? 4 : 2;
+ }
++const RISCVDecoder decoder_table[] = {
++    { always_true_p, decode_insn32 },
++    { has_xthead_p, decode_xthead},
++    { has_XVentanaCondOps_p, decode_XVentanaCodeOps},
++};
++
++const size_t decoder_table_size = ARRAY_SIZE(decoder_table);
++
+ static void decode_opc(CPURISCVState *env, DisasContext *ctx, uint16_t opcode)
+ {
+-    /*
+-     * A table with predicate (i.e., guard) functions and decoder functions
+-     * that are tested in-order until a decoder matches onto the opcode.
+-     */
+-    static const struct {
+-        bool (*guard_func)(const RISCVCPUConfig *);
+-        bool (*decode_func)(DisasContext *, uint32_t);
+-    } decoders[] = {
+-        { always_true_p,  decode_insn32 },
+-        { has_xthead_p, decode_xthead },
+-        { has_XVentanaCondOps_p,  decode_XVentanaCodeOps },
+-    };
+-
+     ctx->virt_inst_excp = false;
+     ctx->cur_insn_len = insn_len(opcode);
+     /* Check for compressed insn */
+@@ -XXX,XX +XXX,XX @@ static void decode_opc(CPURISCVState *env, DisasContext *ctx, uint16_t opcode)
+                                              ctx->base.pc_next + 2));
+         ctx->opcode = opcode32;
+-        for (size_t i = 0; i < ARRAY_SIZE(decoders); ++i) {
+-            if (decoders[i].guard_func(ctx->cfg_ptr) &&
+-                decoders[i].decode_func(ctx, opcode32)) {
++        for (guint i = 0; i < ctx->decoders->len; ++i) {
++            riscv_cpu_decode_fn func = g_ptr_array_index(ctx->decoders, i);
++            if (func(ctx, opcode32)) {
+                 return;
+             }
+         }
+@@ -XXX,XX +XXX,XX @@ static void riscv_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs)
+     ctx->itrigger = FIELD_EX32(tb_flags, TB_FLAGS, ITRIGGER);
+     ctx->zero = tcg_constant_tl(0);
+     ctx->virt_inst_excp = false;
++    ctx->decoders = cpu->decoders;
+ }
+ static void riscv_tr_tb_start(DisasContextBase *db, CPUState *cpu)
+--
+.45.1

-New patch
+[PULL 16/28] riscv: thead: Add th.sxstatus CSR emulation
+From: Christoph Müllner <christoph.muellner@vrull.eu>
+The th.sxstatus CSR can be used to identify available custom extension
+on T-Head CPUs. The CSR is documented here:
+  https://github.com/T-head-Semi/thead-extension-spec/blob/master/xtheadsxstatus.adoc
+An important property of this patch is, that the th.sxstatus MAEE field
+is not set (indicating that XTheadMae is not available).
+XTheadMae is a memory attribute extension (similar to Svpbmt) which is
+implemented in many T-Head CPUs (C906, C910, etc.) and utilizes bits
+in PTEs that are marked as reserved. QEMU maintainers prefer to not
+implement XTheadMae, so we need give kernels a mechanism to identify
+if XTheadMae is available in a system or not. And this patch introduces
+this mechanism in QEMU in a way that's compatible with real HW
+(i.e., probing the th.sxstatus.MAEE bit).
+Further context can be found on the list:
+https://lists.gnu.org/archive/html/qemu-devel/2024-02/msg00775.html
+Reviewed-by: LIU Zhiwei <zhiwe_liu@linux.alibaba.com>
+Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
+Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
+Message-ID: <20240429073656.2486732-1-christoph.muellner@vrull.eu>
+Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
+---
+ MAINTAINERS              |  1 +
+ target/riscv/cpu.h       |  3 ++
+ target/riscv/cpu.c       |  1 +
+ target/riscv/th_csr.c    | 79 ++++++++++++++++++++++++++++++++++++++++
+ target/riscv/meson.build |  1 +
+files changed, 85 insertions(+)
+ create mode 100644 target/riscv/th_csr.c
+diff --git a/MAINTAINERS b/MAINTAINERS
+index XXXXXXX..XXXXXXX 100644
+--- a/MAINTAINERS
++++ b/MAINTAINERS
+@@ -XXX,XX +XXX,XX @@ L: qemu-riscv@nongnu.org
+ S: Supported
+ F: target/riscv/insn_trans/trans_xthead.c.inc
+ F: target/riscv/xthead*.decode
++F: target/riscv/th_*
+ F: disas/riscv-xthead*
+ RISC-V XVentanaCondOps extension
+diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
+index XXXXXXX..XXXXXXX 100644
+--- a/target/riscv/cpu.h
++++ b/target/riscv/cpu.h
+@@ -XXX,XX +XXX,XX @@ target_ulong riscv_new_csr_seed(target_ulong new_value,
+ uint8_t satp_mode_max_from_map(uint32_t map);
+ const char *satp_mode_str(uint8_t satp_mode, bool is_32_bit);
++/* Implemented in th_csr.c */
++void th_register_custom_csrs(RISCVCPU *cpu);
++
+ #endif /* RISCV_CPU_H */
+diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
+index XXXXXXX..XXXXXXX 100644
+--- a/target/riscv/cpu.c
++++ b/target/riscv/cpu.c
+@@ -XXX,XX +XXX,XX @@ static void rv64_thead_c906_cpu_init(Object *obj)
+     cpu->cfg.mvendorid = THEAD_VENDOR_ID;
+ #ifndef CONFIG_USER_ONLY
+     set_satp_mode_max_supported(cpu, VM_1_10_SV39);
++    th_register_custom_csrs(cpu);
+ #endif
+     /* inherited from parent obj via riscv_cpu_init() */
+diff --git a/target/riscv/th_csr.c b/target/riscv/th_csr.c
+new file mode 100644
+index XXXXXXX..XXXXXXX
+--- /dev/null
++++ b/target/riscv/th_csr.c
+@@ -XXX,XX +XXX,XX @@
++/*
++ * T-Head-specific CSRs.
++ *
++ * Copyright (c) 2024 VRULL GmbH
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms and conditions of the GNU General Public License,
++ * version 2 or later, as published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
++ * more details.
++ *
++ * You should have received a copy of the GNU General Public License along with
++ * this program.  If not, see <http://www.gnu.org/licenses/>.
++ */
++
++#include "qemu/osdep.h"
++#include "cpu.h"
++#include "cpu_vendorid.h"
++
++#define CSR_TH_SXSTATUS 0x5c0
++
++/* TH_SXSTATUS bits */
++#define TH_SXSTATUS_UCME        BIT(16)
++#define TH_SXSTATUS_MAEE        BIT(21)
++#define TH_SXSTATUS_THEADISAEE  BIT(22)
++
++typedef struct {
++    int csrno;
++    int (*insertion_test)(RISCVCPU *cpu);
++    riscv_csr_operations csr_ops;
++} riscv_csr;
++
++static RISCVException smode(CPURISCVState *env, int csrno)
++{
++    if (riscv_has_ext(env, RVS)) {
++        return RISCV_EXCP_NONE;
++    }
++
++    return RISCV_EXCP_ILLEGAL_INST;
++}
++
++static int test_thead_mvendorid(RISCVCPU *cpu)
++{
++    if (cpu->cfg.mvendorid != THEAD_VENDOR_ID) {
++        return -1;
++    }
++
++    return 0;
++}
++
++static RISCVException read_th_sxstatus(CPURISCVState *env, int csrno,
++                                       target_ulong *val)
++{
++    /* We don't set MAEE here, because QEMU does not implement MAEE. */
++    *val = TH_SXSTATUS_UCME | TH_SXSTATUS_THEADISAEE;
++    return RISCV_EXCP_NONE;
++}
++
++static riscv_csr th_csr_list[] = {
++    {
++        .csrno = CSR_TH_SXSTATUS,
++        .insertion_test = test_thead_mvendorid,
++        .csr_ops = { "th.sxstatus", smode, read_th_sxstatus }
++    }
++};
++
++void th_register_custom_csrs(RISCVCPU *cpu)
++{
++    for (size_t i = 0; i < ARRAY_SIZE(th_csr_list); i++) {
++        int csrno = th_csr_list[i].csrno;
++        riscv_csr_operations *csr_ops = &th_csr_list[i].csr_ops;
++        if (!th_csr_list[i].insertion_test(cpu)) {
++            riscv_set_csr_ops(csrno, csr_ops);
++        }
++    }
++}
+diff --git a/target/riscv/meson.build b/target/riscv/meson.build
+index XXXXXXX..XXXXXXX 100644
+--- a/target/riscv/meson.build
++++ b/target/riscv/meson.build
+@@ -XXX,XX +XXX,XX @@ riscv_system_ss.add(files(
+   'monitor.c',
+   'machine.c',
+   'pmu.c',
++  'th_csr.c',
+   'time_helper.c',
+   'riscv-qmp-cmds.c',
+ ))
+--
+.45.1

-New patch
+[PULL 17/28] target/riscv: rvv: Fix Zvfhmin checking for vfwcvt.f.f.v and vfncvt.f.f.w instructions
+From: Max Chou <max.chou@sifive.com>
+According v spec 18.4, only the vfwcvt.f.f.v and vfncvt.f.f.w
+instructions will be affected by Zvfhmin extension.
+And the vfwcvt.f.f.v and vfncvt.f.f.w instructions only support the
+conversions of
+* From 1*SEW(16/32) to 2*SEW(32/64)
+* From 2*SEW(32/64) to 1*SEW(16/32)
+Signed-off-by: Max Chou <max.chou@sifive.com>
+Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
+Cc: qemu-stable <qemu-stable@nongnu.org>
+Message-ID: <20240322092600.1198921-2-max.chou@sifive.com>
+Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
+---
+ target/riscv/insn_trans/trans_rvv.c.inc | 20 ++++++++++++++++++--
+file changed, 18 insertions(+), 2 deletions(-)
+diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc
+index XXXXXXX..XXXXXXX 100644
+--- a/target/riscv/insn_trans/trans_rvv.c.inc
++++ b/target/riscv/insn_trans/trans_rvv.c.inc
+@@ -XXX,XX +XXX,XX @@ static bool require_rvf(DisasContext *s)
+     }
+ }
++static bool require_rvfmin(DisasContext *s)
++{
++    if (s->mstatus_fs == EXT_STATUS_DISABLED) {
++        return false;
++    }
++
++    switch (s->sew) {
++    case MO_16:
++        return s->cfg_ptr->ext_zvfhmin;
++    case MO_32:
++        return s->cfg_ptr->ext_zve32f;
++    default:
++        return false;
++    }
++}
++
+ static bool require_scale_rvf(DisasContext *s)
+ {
+     if (s->mstatus_fs == EXT_STATUS_DISABLED) {
+@@ -XXX,XX +XXX,XX @@ static bool require_scale_rvfmin(DisasContext *s)
+     }
+     switch (s->sew) {
+-    case MO_8:
+-        return s->cfg_ptr->ext_zvfhmin;
+     case MO_16:
+         return s->cfg_ptr->ext_zve32f;
+     case MO_32:
+@@ -XXX,XX +XXX,XX @@ static bool opxfv_widen_check(DisasContext *s, arg_rmr *a)
+ static bool opffv_widen_check(DisasContext *s, arg_rmr *a)
+ {
+     return opfv_widen_check(s, a) &&
++           require_rvfmin(s) &&
+            require_scale_rvfmin(s) &&
+            (s->sew != MO_8);
+ }
+@@ -XXX,XX +XXX,XX @@ static bool opfxv_narrow_check(DisasContext *s, arg_rmr *a)
+ static bool opffv_narrow_check(DisasContext *s, arg_rmr *a)
+ {
+     return opfv_narrow_check(s, a) &&
++           require_rvfmin(s) &&
+            require_scale_rvfmin(s) &&
+            (s->sew != MO_8);
+ }
+--
+.45.1

-New patch
+[PULL 18/28] target/riscv: rvv: Check single width operator for vector fp widen instructions
+From: Max Chou <max.chou@sifive.com>
+The require_scale_rvf function only checks the double width operator for
+the vector floating point widen instructions, so most of the widen
+checking functions need to add require_rvf for single width operator.
+The vfwcvt.f.x.v and vfwcvt.f.xu.v instructions convert single width
+integer to double width float, so the opfxv_widen_check function doesn’t
+need require_rvf for the single width operator(integer).
+Signed-off-by: Max Chou <max.chou@sifive.com>
+Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
+Cc: qemu-stable <qemu-stable@nongnu.org>
+Message-ID: <20240322092600.1198921-3-max.chou@sifive.com>
+Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
+---
+ target/riscv/insn_trans/trans_rvv.c.inc | 5 +++++
+file changed, 5 insertions(+)
+diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc
+index XXXXXXX..XXXXXXX 100644
+--- a/target/riscv/insn_trans/trans_rvv.c.inc
++++ b/target/riscv/insn_trans/trans_rvv.c.inc
+@@ -XXX,XX +XXX,XX @@ GEN_OPFVF_TRANS(vfrsub_vf,  opfvf_check)
+ static bool opfvv_widen_check(DisasContext *s, arg_rmrr *a)
+ {
+     return require_rvv(s) &&
++           require_rvf(s) &&
+            require_scale_rvf(s) &&
+            (s->sew != MO_8) &&
+            vext_check_isa_ill(s) &&
+@@ -XXX,XX +XXX,XX @@ GEN_OPFVV_WIDEN_TRANS(vfwsub_vv, opfvv_widen_check)
+ static bool opfvf_widen_check(DisasContext *s, arg_rmrr *a)
+ {
+     return require_rvv(s) &&
++           require_rvf(s) &&
+            require_scale_rvf(s) &&
+            (s->sew != MO_8) &&
+            vext_check_isa_ill(s) &&
+@@ -XXX,XX +XXX,XX @@ GEN_OPFVF_WIDEN_TRANS(vfwsub_vf)
+ static bool opfwv_widen_check(DisasContext *s, arg_rmrr *a)
+ {
+     return require_rvv(s) &&
++           require_rvf(s) &&
+            require_scale_rvf(s) &&
+            (s->sew != MO_8) &&
+            vext_check_isa_ill(s) &&
+@@ -XXX,XX +XXX,XX @@ GEN_OPFWV_WIDEN_TRANS(vfwsub_wv)
+ static bool opfwf_widen_check(DisasContext *s, arg_rmrr *a)
+ {
+     return require_rvv(s) &&
++           require_rvf(s) &&
+            require_scale_rvf(s) &&
+            (s->sew != MO_8) &&
+            vext_check_isa_ill(s) &&
+@@ -XXX,XX +XXX,XX @@ GEN_OPFVV_TRANS(vfredmin_vs, freduction_check)
+ static bool freduction_widen_check(DisasContext *s, arg_rmrr *a)
+ {
+     return reduction_widen_check(s, a) &&
++           require_rvf(s) &&
+            require_scale_rvf(s) &&
+            (s->sew != MO_8);
+ }
+--
+.45.1

-New patch
+[PULL 19/28] target/riscv: rvv: Check single width operator for vfncvt.rod.f.f.w
+From: Max Chou <max.chou@sifive.com>
+The opfv_narrow_check needs to check the single width float operator by
+require_rvf.
+Signed-off-by: Max Chou <max.chou@sifive.com>
+Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
+Cc: qemu-stable <qemu-stable@nongnu.org>
+Message-ID: <20240322092600.1198921-4-max.chou@sifive.com>
+Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
+---
+ target/riscv/insn_trans/trans_rvv.c.inc | 1 +
+file changed, 1 insertion(+)
+diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc
+index XXXXXXX..XXXXXXX 100644
+--- a/target/riscv/insn_trans/trans_rvv.c.inc
++++ b/target/riscv/insn_trans/trans_rvv.c.inc
+@@ -XXX,XX +XXX,XX @@ static bool opffv_narrow_check(DisasContext *s, arg_rmr *a)
+ static bool opffv_rod_narrow_check(DisasContext *s, arg_rmr *a)
+ {
+     return opfv_narrow_check(s, a) &&
++           require_rvf(s) &&
+            require_scale_rvf(s) &&
+            (s->sew != MO_8);
+ }
+--
+.45.1

-New patch
+[PULL 20/28] target/riscv: rvv: Remove redudant SEW checking for vector fp narrow/widen instructions
+From: Max Chou <max.chou@sifive.com>
+If the checking functions check both the single and double width
+operators at the same time, then the single width operator checking
+functions (require_rvf[min]) will check whether the SEW is 8.
+Signed-off-by: Max Chou <max.chou@sifive.com>
+Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
+Cc: qemu-stable <qemu-stable@nongnu.org>
+Message-ID: <20240322092600.1198921-5-max.chou@sifive.com>
+Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
+---
+ target/riscv/insn_trans/trans_rvv.c.inc | 16 ++++------------
+file changed, 4 insertions(+), 12 deletions(-)
+diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc
+index XXXXXXX..XXXXXXX 100644
+--- a/target/riscv/insn_trans/trans_rvv.c.inc
++++ b/target/riscv/insn_trans/trans_rvv.c.inc
+@@ -XXX,XX +XXX,XX @@ static bool opfvv_widen_check(DisasContext *s, arg_rmrr *a)
+     return require_rvv(s) &&
+            require_rvf(s) &&
+            require_scale_rvf(s) &&
+-           (s->sew != MO_8) &&
+            vext_check_isa_ill(s) &&
+            vext_check_dss(s, a->rd, a->rs1, a->rs2, a->vm);
+ }
+@@ -XXX,XX +XXX,XX @@ static bool opfvf_widen_check(DisasContext *s, arg_rmrr *a)
+     return require_rvv(s) &&
+            require_rvf(s) &&
+            require_scale_rvf(s) &&
+-           (s->sew != MO_8) &&
+            vext_check_isa_ill(s) &&
+            vext_check_ds(s, a->rd, a->rs2, a->vm);
+ }
+@@ -XXX,XX +XXX,XX @@ static bool opfwv_widen_check(DisasContext *s, arg_rmrr *a)
+     return require_rvv(s) &&
+            require_rvf(s) &&
+            require_scale_rvf(s) &&
+-           (s->sew != MO_8) &&
+            vext_check_isa_ill(s) &&
+            vext_check_dds(s, a->rd, a->rs1, a->rs2, a->vm);
+ }
+@@ -XXX,XX +XXX,XX @@ static bool opfwf_widen_check(DisasContext *s, arg_rmrr *a)
+     return require_rvv(s) &&
+            require_rvf(s) &&
+            require_scale_rvf(s) &&
+-           (s->sew != MO_8) &&
+            vext_check_isa_ill(s) &&
+            vext_check_dd(s, a->rd, a->rs2, a->vm);
+ }
+@@ -XXX,XX +XXX,XX @@ static bool opffv_widen_check(DisasContext *s, arg_rmr *a)
+ {
+     return opfv_widen_check(s, a) &&
+            require_rvfmin(s) &&
+-           require_scale_rvfmin(s) &&
+-           (s->sew != MO_8);
++           require_scale_rvfmin(s);
+ }
+ #define GEN_OPFV_WIDEN_TRANS(NAME, CHECK, HELPER, FRM)             \
+@@ -XXX,XX +XXX,XX @@ static bool opffv_narrow_check(DisasContext *s, arg_rmr *a)
+ {
+     return opfv_narrow_check(s, a) &&
+            require_rvfmin(s) &&
+-           require_scale_rvfmin(s) &&
+-           (s->sew != MO_8);
++           require_scale_rvfmin(s);
+ }
+ static bool opffv_rod_narrow_check(DisasContext *s, arg_rmr *a)
+ {
+     return opfv_narrow_check(s, a) &&
+            require_rvf(s) &&
+-           require_scale_rvf(s) &&
+-           (s->sew != MO_8);
++           require_scale_rvf(s);
+ }
+ #define GEN_OPFV_NARROW_TRANS(NAME, CHECK, HELPER, FRM)            \
+@@ -XXX,XX +XXX,XX @@ static bool freduction_widen_check(DisasContext *s, arg_rmrr *a)
+ {
+     return reduction_widen_check(s, a) &&
+            require_rvf(s) &&
+-           require_scale_rvf(s) &&
+-           (s->sew != MO_8);
++           require_scale_rvf(s);
+ }
+ GEN_OPFVV_WIDEN_TRANS(vfwredusum_vs, freduction_widen_check)
+--
+.45.1

-New patch
+[PULL 21/28] target/riscv: prioritize pmp errors in raise_mmu_exception()
+From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
+raise_mmu_exception(), as is today, is prioritizing guest page faults by
+checking first if virt_enabled && !first_stage, and then considering the
+regular inst/load/store faults.
+There's no mention in the spec about guest page fault being a higher
+priority that PMP faults. In fact, privileged spec section 3.7.1 says:
+"Attempting to fetch an instruction from a PMP region that does not have
+execute permissions raises an instruction access-fault exception.
+Attempting to execute a load or load-reserved instruction which accesses
+a physical address within a PMP region without read permissions raises a
+load access-fault exception. Attempting to execute a store,
+store-conditional, or AMO instruction which accesses a physical address
+within a PMP region without write permissions raises a store
+access-fault exception."
+So, in fact, we're doing it wrong - PMP faults should always be thrown,
+regardless of also being a first or second stage fault.
+The way riscv_cpu_tlb_fill() and get_physical_address() work is
+adequate: a TRANSLATE_PMP_FAIL error is immediately reported and
+reflected in the 'pmp_violation' flag. What we need is to change
+raise_mmu_exception() to prioritize it.
+Reported-by: Joseph Chan <jchan@ventanamicro.com>
+Fixes: 82d53adfbb ("target/riscv/cpu_helper.c: Invalid exception on MMU translation stage")
+Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
+Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
+Message-ID: <20240413105929.7030-1-alexei.filippov@syntacore.com>
+Cc: qemu-stable <qemu-stable@nongnu.org>
+Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
+---
+ target/riscv/cpu_helper.c | 22 ++++++++++++----------
+file changed, 12 insertions(+), 10 deletions(-)
+diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
+index XXXXXXX..XXXXXXX 100644
+--- a/target/riscv/cpu_helper.c
++++ b/target/riscv/cpu_helper.c
+@@ -XXX,XX +XXX,XX @@ static void raise_mmu_exception(CPURISCVState *env, target_ulong address,
+     switch (access_type) {
+     case MMU_INST_FETCH:
+-        if (env->virt_enabled && !first_stage) {
++        if (pmp_violation) {
++            cs->exception_index = RISCV_EXCP_INST_ACCESS_FAULT;
++        } else if (env->virt_enabled && !first_stage) {
+             cs->exception_index = RISCV_EXCP_INST_GUEST_PAGE_FAULT;
+         } else {
+-            cs->exception_index = pmp_violation ?
+-                RISCV_EXCP_INST_ACCESS_FAULT : RISCV_EXCP_INST_PAGE_FAULT;
++            cs->exception_index = RISCV_EXCP_INST_PAGE_FAULT;
+         }
+         break;
+     case MMU_DATA_LOAD:
+-        if (two_stage && !first_stage) {
++        if (pmp_violation) {
++            cs->exception_index = RISCV_EXCP_LOAD_ACCESS_FAULT;
++        } else if (two_stage && !first_stage) {
+             cs->exception_index = RISCV_EXCP_LOAD_GUEST_ACCESS_FAULT;
+         } else {
+-            cs->exception_index = pmp_violation ?
+-                RISCV_EXCP_LOAD_ACCESS_FAULT : RISCV_EXCP_LOAD_PAGE_FAULT;
++            cs->exception_index = RISCV_EXCP_LOAD_PAGE_FAULT;
+         }
+         break;
+     case MMU_DATA_STORE:
+-        if (two_stage && !first_stage) {
++        if (pmp_violation) {
++            cs->exception_index = RISCV_EXCP_STORE_AMO_ACCESS_FAULT;
++        } else if (two_stage && !first_stage) {
+             cs->exception_index = RISCV_EXCP_STORE_GUEST_AMO_ACCESS_FAULT;
+         } else {
+-            cs->exception_index = pmp_violation ?
+-                RISCV_EXCP_STORE_AMO_ACCESS_FAULT :
+-                RISCV_EXCP_STORE_PAGE_FAULT;
++            cs->exception_index = RISCV_EXCP_STORE_PAGE_FAULT;
+         }
+         break;
+     default:
+--
+.45.1

-New patch
+[PULL 22/28] target/riscv: do not set mtval2 for non guest-page faults
+From: Alexei Filippov <alexei.filippov@syntacore.com>
+Previous patch fixed the PMP priority in raise_mmu_exception() but we're still
+setting mtval2 incorrectly. In riscv_cpu_tlb_fill(), after pmp check in 2 stage
+translation part, mtval2 will be set in case of successes 2 stage translation but
+failed pmp check.
+In this case we gonna set mtval2 via env->guest_phys_fault_addr in context of
+riscv_cpu_tlb_fill(), as this was a guest-page-fault, but it didn't and mtval2
+should be zero, according to RISCV privileged spec sect. 9.4.4: When a guest
+page-fault is taken into M-mode, mtval2 is written with either zero or guest
+physical address that faulted, shifted by 2 bits. *For other traps, mtval2
+is set to zero...*
+Signed-off-by: Alexei Filippov <alexei.filippov@syntacore.com>
+Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
+Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
+Message-ID: <20240503103052.6819-1-alexei.filippov@syntacore.com>
+Cc: qemu-stable <qemu-stable@nongnu.org>
+Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
+---
+ target/riscv/cpu_helper.c | 12 ++++++------
+file changed, 6 insertions(+), 6 deletions(-)
+diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
+index XXXXXXX..XXXXXXX 100644
+--- a/target/riscv/cpu_helper.c
++++ b/target/riscv/cpu_helper.c
+@@ -XXX,XX +XXX,XX @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
+                               __func__, pa, ret, prot_pmp, tlb_size);
+                 prot &= prot_pmp;
+-            }
+-
+-            if (ret != TRANSLATE_SUCCESS) {
++            } else {
+                 /*
+                  * Guest physical address translation failed, this is a HS
+                  * level exception
+                  */
+                 first_stage_error = false;
+-                env->guest_phys_fault_addr = (im_address |
+-                                              (address &
+-                                               (TARGET_PAGE_SIZE - 1))) >> 2;
++                if (ret != TRANSLATE_PMP_FAIL) {
++                    env->guest_phys_fault_addr = (im_address |
++                                                  (address &
++                                                   (TARGET_PAGE_SIZE - 1))) >> 2;
++                }
+             }
+         }
+     } else {
+--
+.45.1

-[PULL 09/10] hw/intc: sifive_plic: change interrupt priority register to WARL field
+[PULL 23/28] target/riscv: Remove experimental prefix from "B" extension
-From: Jim Shu <jim.shu@sifive.com>
+From: Rob Bradford <rbradford@rivosinc.com>
-PLIC spec [1] requires interrupt source priority registers are WARL
+This extension has now been ratified:
-field and the number of supported priority is power-of-2 to simplify SW
+https://jira.riscv.org/browse/RVS-2006 so the "x-" prefix can be
-discovery.
+removed.
-Existing QEMU RISC-V machine (e.g. shakti_c) don't strictly follow PLIC
+Since this is now a ratified extension add it to the list of extensions
-spec, whose number of supported priority is not power-of-2. Just change
+included in the "max" CPU variant.
 each bit of interrupt priority register to WARL field when the number of
 supported priority is power-of-2.
-[1] https://github.com/riscv/riscv-plic-spec/blob/master/riscv-plic.adoc#interrupt-priorities
+Signed-off-by: Rob Bradford <rbradford@rivosinc.com>
+Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
-Signed-off-by: Jim Shu <jim.shu@sifive.com>
+Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
-Reviewed-by: Clément Chigot <chigot@adacore.com>
+Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
-Acked-by: Alistair Francis <alistair.francis@wdc.com>
+Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
-Message-Id: <20221003041440.2320-3-jim.shu@sifive.com>
+Message-ID: <20240514110217.22516-1-rbradford@rivosinc.com>
 Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
 ---
- hw/intc/sifive_plic.c | 21 +++++++++++++++++++--
+ target/riscv/cpu.c         | 2 +-
-file changed, 19 insertions(+), 2 deletions(-)
+ target/riscv/tcg/tcg-cpu.c | 2 +-
 files changed, 2 insertions(+), 2 deletions(-)
-diff --git a/hw/intc/sifive_plic.c b/hw/intc/sifive_plic.c
+diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
 index XXXXXXX..XXXXXXX 100644
---- a/hw/intc/sifive_plic.c
+--- a/target/riscv/cpu.c
-+++ b/hw/intc/sifive_plic.c
++++ b/target/riscv/cpu.c
-@@ -XXX,XX +XXX,XX @@ static void sifive_plic_write(void *opaque, hwaddr addr, uint64_t value,
+@@ -XXX,XX +XXX,XX @@ static const MISAExtInfo misa_ext_info_arr[] = {
-     if (addr_between(addr, plic->priority_base, plic->num_sources << 2)) {
+     MISA_EXT_INFO(RVJ, "x-j", "Dynamic translated languages"),
-         uint32_t irq = ((addr - plic->priority_base) >> 2) + 1;
+     MISA_EXT_INFO(RVV, "v", "Vector operations"),
+     MISA_EXT_INFO(RVG, "g", "General purpose (IMAFD_Zicsr_Zifencei)"),
--        if (value <= plic->num_priorities) {
+-    MISA_EXT_INFO(RVB, "x-b", "Bit manipulation (Zba_Zbb_Zbs)")
-+        if (((plic->num_priorities + 1) & plic->num_priorities) == 0) {
++    MISA_EXT_INFO(RVB, "b", "Bit manipulation (Zba_Zbb_Zbs)")
-+            /*
+ };
-+             * if "num_priorities + 1" is power-of-2, make each register bit of
-+             * interrupt priority WARL (Write-Any-Read-Legal). Just filter
+ static void riscv_cpu_validate_misa_mxl(RISCVCPUClass *mcc)
-+             * out the access to unsupported priority bits.
+diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c
-+             */
+index XXXXXXX..XXXXXXX 100644
-+            plic->source_priority[irq] = value % (plic->num_priorities + 1);
+--- a/target/riscv/tcg/tcg-cpu.c
-+            sifive_plic_update(plic);
++++ b/target/riscv/tcg/tcg-cpu.c
-+        } else if (value <= plic->num_priorities) {
+@@ -XXX,XX +XXX,XX @@ static void riscv_init_max_cpu_extensions(Object *obj)
-             plic->source_priority[irq] = value;
+     const RISCVCPUMultiExtConfig *prop;
-             sifive_plic_update(plic);
-         }
+     /* Enable RVG, RVJ and RVV that are disabled by default */
-@@ -XXX,XX +XXX,XX @@ static void sifive_plic_write(void *opaque, hwaddr addr, uint64_t value,
+-    riscv_cpu_set_misa_ext(env, env->misa_ext | RVG | RVJ | RVV);
-         uint32_t contextid = (addr & (plic->context_stride - 1));
++    riscv_cpu_set_misa_ext(env, env->misa_ext | RVB | RVG | RVJ | RVV);
-         if (contextid == 0) {
+     for (prop = riscv_cpu_extensions; prop && prop->name; prop++) {
--            if (value <= plic->num_priorities) {
+         isa_ext_update_enabled(cpu, prop->offset, true);
 +            if (((plic->num_priorities + 1) & plic->num_priorities) == 0) {
 +                /*
 +                 * if "num_priorities + 1" is power-of-2, each register bit of
 +                 * interrupt priority is WARL (Write-Any-Read-Legal). Just
 +                 * filter out the access to unsupported priority bits.
 +                 */
 +                plic->target_priority[addrid] = value %
 +                                                (plic->num_priorities + 1);
 +                sifive_plic_update(plic);
 +            } else if (value <= plic->num_priorities) {
                  plic->target_priority[addrid] = value;
                  sifive_plic_update(plic);
              }
 --
-.37.3
+.45.1

-[PULL 02/10] hw/ssi: ibex_spi: fixup coverity issue
+[PULL 24/28] target/riscv: rvzicbo: Fixup CBO extension register calculation
-From: Wilfred Mallawa <wilfred.mallawa@wdc.com>
+From: Alistair Francis <alistair23@gmail.com>
-This patch addresses the coverity issues specified in [1],
+When running the instruction
 as suggested, `FIELD_DP32()`/`FIELD_EX32()` macros have been
 implemented to clean up the code.
-[1] https://www.mail-archive.com/qemu-devel@nongnu.org/msg887713.html
+```
     cbo.flush 0(x0)
 ```
-Fixes: Coverity CID 1488107
+QEMU would segfault.
-Signed-off-by: Wilfred Mallawa <wilfred.mallawa@wdc.com>
+The issue was in cpu_gpr[a->rs1] as QEMU does not have cpu_gpr[0]
-Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
+allocated.
-Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
-Message-Id: <20220930033241.206581-2-wilfred.mallawa@opensource.wdc.com>
+In order to fix this let's use the existing get_address()
 helper. This also has the benefit of performing pointer mask
 calculations on the address specified in rs1.
 The pointer masking specificiation specifically states:
 """
 Cache Management Operations: All instructions in Zicbom, Zicbop and Zicboz
 """
 So this is the correct behaviour and we previously have been incorrectly
 not masking the address.
 Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
 Reported-by: Fabian Thomas <fabian.thomas@cispa.de>
 Fixes: e05da09b7cfd ("target/riscv: implement Zicbom extension")
 Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
 Cc: qemu-stable <qemu-stable@nongnu.org>
 Message-ID: <20240514023910.301766-1-alistair.francis@wdc.com>
 Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
 ---
- hw/ssi/ibex_spi_host.c | 132 +++++++++++++++++++++--------------------
+ target/riscv/insn_trans/trans_rvzicbo.c.inc | 16 ++++++++++++----
-file changed, 68 insertions(+), 64 deletions(-)
+file changed, 12 insertions(+), 4 deletions(-)
-diff --git a/hw/ssi/ibex_spi_host.c b/hw/ssi/ibex_spi_host.c
+diff --git a/target/riscv/insn_trans/trans_rvzicbo.c.inc b/target/riscv/insn_trans/trans_rvzicbo.c.inc
 index XXXXXXX..XXXXXXX 100644
---- a/hw/ssi/ibex_spi_host.c
+--- a/target/riscv/insn_trans/trans_rvzicbo.c.inc
-+++ b/hw/ssi/ibex_spi_host.c
++++ b/target/riscv/insn_trans/trans_rvzicbo.c.inc
-@@ -XXX,XX +XXX,XX @@ static inline uint8_t div4_round_up(uint8_t dividend)
+@@ -XXX,XX +XXX,XX @@
+ static bool trans_cbo_clean(DisasContext *ctx, arg_cbo_clean *a)
  static void ibex_spi_rxfifo_reset(IbexSPIHostState *s)
  {
-+    uint32_t data = s->regs[IBEX_SPI_HOST_STATUS];
+     REQUIRE_ZICBOM(ctx);
-     /* Empty the RX FIFO and assert RXEMPTY */
+-    gen_helper_cbo_clean_flush(tcg_env, cpu_gpr[a->rs1]);
-     fifo8_reset(&s->rx_fifo);
++    TCGv src = get_address(ctx, a->rs1, 0);
--    s->regs[IBEX_SPI_HOST_STATUS] &= ~R_STATUS_RXFULL_MASK;
++
--    s->regs[IBEX_SPI_HOST_STATUS] |= R_STATUS_RXEMPTY_MASK;
++    gen_helper_cbo_clean_flush(tcg_env, src);
-+    data = FIELD_DP32(data, STATUS, RXFULL, 0);
+     return true;
 +    data = FIELD_DP32(data, STATUS, RXEMPTY, 1);
 +    s->regs[IBEX_SPI_HOST_STATUS] = data;
  }
- static void ibex_spi_txfifo_reset(IbexSPIHostState *s)
+ static bool trans_cbo_flush(DisasContext *ctx, arg_cbo_flush *a)
  {
-+    uint32_t data = s->regs[IBEX_SPI_HOST_STATUS];
+     REQUIRE_ZICBOM(ctx);
-     /* Empty the TX FIFO and assert TXEMPTY */
+-    gen_helper_cbo_clean_flush(tcg_env, cpu_gpr[a->rs1]);
-     fifo8_reset(&s->tx_fifo);
++    TCGv src = get_address(ctx, a->rs1, 0);
--    s->regs[IBEX_SPI_HOST_STATUS] &= ~R_STATUS_TXFULL_MASK;
++
--    s->regs[IBEX_SPI_HOST_STATUS] |= R_STATUS_TXEMPTY_MASK;
++    gen_helper_cbo_clean_flush(tcg_env, src);
-+    data = FIELD_DP32(data, STATUS, TXFULL, 0);
+     return true;
 +    data = FIELD_DP32(data, STATUS, TXEMPTY, 1);
 +    s->regs[IBEX_SPI_HOST_STATUS] = data;
  }
- static void ibex_spi_host_reset(DeviceState *dev)
+ static bool trans_cbo_inval(DisasContext *ctx, arg_cbo_inval *a)
@@ -XXX,XX +XXX,XX @@ static void ibex_spi_host_reset(DeviceState *dev)
   */
  static void ibex_spi_host_irq(IbexSPIHostState *s)
  {
--    bool error_en = s->regs[IBEX_SPI_HOST_INTR_ENABLE]
+     REQUIRE_ZICBOM(ctx);
--                    & R_INTR_ENABLE_ERROR_MASK;
+-    gen_helper_cbo_inval(tcg_env, cpu_gpr[a->rs1]);
--    bool event_en = s->regs[IBEX_SPI_HOST_INTR_ENABLE]
++    TCGv src = get_address(ctx, a->rs1, 0);
 -                    & R_INTR_ENABLE_SPI_EVENT_MASK;
 -    bool err_pending = s->regs[IBEX_SPI_HOST_INTR_STATE]
 -                        & R_INTR_STATE_ERROR_MASK;
 -    bool status_pending = s->regs[IBEX_SPI_HOST_INTR_STATE]
 -                        & R_INTR_STATE_SPI_EVENT_MASK;
 +    uint32_t intr_test_reg = s->regs[IBEX_SPI_HOST_INTR_TEST];
 +    uint32_t intr_en_reg = s->regs[IBEX_SPI_HOST_INTR_ENABLE];
 +    uint32_t intr_state_reg = s->regs[IBEX_SPI_HOST_INTR_STATE];
 +
-+    uint32_t err_en_reg = s->regs[IBEX_SPI_HOST_ERROR_ENABLE];
++    gen_helper_cbo_inval(tcg_env, src);
-+    uint32_t event_en_reg = s->regs[IBEX_SPI_HOST_EVENT_ENABLE];
+     return true;
-+    uint32_t err_status_reg = s->regs[IBEX_SPI_HOST_ERROR_STATUS];
+ }
-+    uint32_t status_reg = s->regs[IBEX_SPI_HOST_STATUS];
  static bool trans_cbo_zero(DisasContext *ctx, arg_cbo_zero *a)
  {
      REQUIRE_ZICBOZ(ctx);
 -    gen_helper_cbo_zero(tcg_env, cpu_gpr[a->rs1]);
 +    TCGv src = get_address(ctx, a->rs1, 0);
 +
-+
++    gen_helper_cbo_zero(tcg_env, src);
-+    bool error_en = FIELD_EX32(intr_en_reg, INTR_ENABLE, ERROR);
+     return true;
 +    bool event_en = FIELD_EX32(intr_en_reg, INTR_ENABLE, SPI_EVENT);
 +    bool err_pending = FIELD_EX32(intr_state_reg, INTR_STATE, ERROR);
 +    bool status_pending = FIELD_EX32(intr_state_reg, INTR_STATE, SPI_EVENT);
 +
      int err_irq = 0, event_irq = 0;
      /* Error IRQ enabled and Error IRQ Cleared */
      if (error_en && !err_pending) {
          /* Event enabled, Interrupt Test Error */
 -        if (s->regs[IBEX_SPI_HOST_INTR_TEST] & R_INTR_TEST_ERROR_MASK) {
 +        if (FIELD_EX32(intr_test_reg, INTR_TEST,  ERROR)) {
              err_irq = 1;
 -        } else if ((s->regs[IBEX_SPI_HOST_ERROR_ENABLE]
 -                    &  R_ERROR_ENABLE_CMDBUSY_MASK) &&
 -                    s->regs[IBEX_SPI_HOST_ERROR_STATUS]
 -                    & R_ERROR_STATUS_CMDBUSY_MASK) {
 +        } else if (FIELD_EX32(err_en_reg, ERROR_ENABLE,  CMDBUSY) &&
 +                   FIELD_EX32(err_status_reg, ERROR_STATUS,  CMDBUSY)) {
              /* Wrote to COMMAND when not READY */
              err_irq = 1;
 -        } else if ((s->regs[IBEX_SPI_HOST_ERROR_ENABLE]
 -                    &  R_ERROR_ENABLE_CMDINVAL_MASK) &&
 -                    s->regs[IBEX_SPI_HOST_ERROR_STATUS]
 -                    & R_ERROR_STATUS_CMDINVAL_MASK) {
 +        } else if (FIELD_EX32(err_en_reg, ERROR_ENABLE,  CMDINVAL)  &&
 +                   FIELD_EX32(err_status_reg, ERROR_STATUS,  CMDINVAL)) {
              /* Invalid command segment */
              err_irq = 1;
 -        } else if ((s->regs[IBEX_SPI_HOST_ERROR_ENABLE]
 -                    & R_ERROR_ENABLE_CSIDINVAL_MASK) &&
 -                    s->regs[IBEX_SPI_HOST_ERROR_STATUS]
 -                    & R_ERROR_STATUS_CSIDINVAL_MASK) {
 +        } else if (FIELD_EX32(err_en_reg, ERROR_ENABLE,  CSIDINVAL) &&
 +                   FIELD_EX32(err_status_reg, ERROR_STATUS,  CSIDINVAL)) {
              /* Invalid value for CSID */
              err_irq = 1;
          }
@@ -XXX,XX +XXX,XX @@ static void ibex_spi_host_irq(IbexSPIHostState *s)
      /* Event IRQ Enabled and Event IRQ Cleared */
      if (event_en && !status_pending) {
 -        if (s->regs[IBEX_SPI_HOST_INTR_TEST] & R_INTR_TEST_SPI_EVENT_MASK) {
 +        if (FIELD_EX32(intr_test_reg, INTR_STATE,  SPI_EVENT)) {
              /* Event enabled, Interrupt Test Event */
              event_irq = 1;
 -        } else if ((s->regs[IBEX_SPI_HOST_EVENT_ENABLE]
 -                    & R_EVENT_ENABLE_READY_MASK) &&
 -                    (s->regs[IBEX_SPI_HOST_STATUS] & R_STATUS_READY_MASK)) {
 +        } else if (FIELD_EX32(event_en_reg, EVENT_ENABLE,  READY) &&
 +                   FIELD_EX32(status_reg, STATUS, READY)) {
              /* SPI Host ready for next command */
              event_irq = 1;
 -        } else if ((s->regs[IBEX_SPI_HOST_EVENT_ENABLE]
 -                    & R_EVENT_ENABLE_TXEMPTY_MASK) &&
 -                    (s->regs[IBEX_SPI_HOST_STATUS] & R_STATUS_TXEMPTY_MASK)) {
 +        } else if (FIELD_EX32(event_en_reg, EVENT_ENABLE,  TXEMPTY) &&
 +                   FIELD_EX32(status_reg, STATUS,  TXEMPTY)) {
              /* SPI TXEMPTY, TXFIFO drained */
              event_irq = 1;
 -        } else if ((s->regs[IBEX_SPI_HOST_EVENT_ENABLE]
 -                    & R_EVENT_ENABLE_RXFULL_MASK) &&
 -                    (s->regs[IBEX_SPI_HOST_STATUS] & R_STATUS_RXFULL_MASK)) {
 +        } else if (FIELD_EX32(event_en_reg, EVENT_ENABLE,  RXFULL) &&
 +                   FIELD_EX32(status_reg, STATUS,  RXFULL)) {
              /* SPI RXFULL, RXFIFO  full */
              event_irq = 1;
          }
@@ -XXX,XX +XXX,XX @@ static void ibex_spi_host_irq(IbexSPIHostState *s)
  static void ibex_spi_host_transfer(IbexSPIHostState *s)
  {
 -    uint32_t rx, tx;
 +    uint32_t rx, tx, data;
      /* Get num of one byte transfers */
 -    uint8_t segment_len = ((s->regs[IBEX_SPI_HOST_COMMAND] & R_COMMAND_LEN_MASK)
 -                          >> R_COMMAND_LEN_SHIFT);
 +    uint8_t segment_len = FIELD_EX32(s->regs[IBEX_SPI_HOST_COMMAND],
 +                                     COMMAND,  LEN);
 +
      while (segment_len > 0) {
          if (fifo8_is_empty(&s->tx_fifo)) {
              /* Assert Stall */
@@ -XXX,XX +XXX,XX @@ static void ibex_spi_host_transfer(IbexSPIHostState *s)
          --segment_len;
      }
 +    data = s->regs[IBEX_SPI_HOST_STATUS];
      /* Assert Ready */
 -    s->regs[IBEX_SPI_HOST_STATUS] |= R_STATUS_READY_MASK;
 +    data = FIELD_DP32(data, STATUS, READY, 1);
      /* Set RXQD */
 -    s->regs[IBEX_SPI_HOST_STATUS] &= ~R_STATUS_RXQD_MASK;
 -    s->regs[IBEX_SPI_HOST_STATUS] |= (R_STATUS_RXQD_MASK
 -                                    & div4_round_up(segment_len));
 +    data = FIELD_DP32(data, STATUS, RXQD, div4_round_up(segment_len));
      /* Set TXQD */
 -    s->regs[IBEX_SPI_HOST_STATUS] &= ~R_STATUS_TXQD_MASK;
 -    s->regs[IBEX_SPI_HOST_STATUS] |= (fifo8_num_used(&s->tx_fifo) / 4)
 -                                    & R_STATUS_TXQD_MASK;
 +    data = FIELD_DP32(data, STATUS, TXQD, fifo8_num_used(&s->tx_fifo) / 4);
      /* Clear TXFULL */
 -    s->regs[IBEX_SPI_HOST_STATUS] &= ~R_STATUS_TXFULL_MASK;
 -    /* Assert TXEMPTY and drop remaining bytes that exceed segment_len */
 -    ibex_spi_txfifo_reset(s);
 +    data = FIELD_DP32(data, STATUS, TXFULL, 0);
      /* Reset RXEMPTY */
 -    s->regs[IBEX_SPI_HOST_STATUS] &= ~R_STATUS_RXEMPTY_MASK;
 +    data = FIELD_DP32(data, STATUS, RXEMPTY, 0);
 +    /* Update register status */
 +    s->regs[IBEX_SPI_HOST_STATUS] = data;
 +    /* Drop remaining bytes that exceed segment_len */
 +    ibex_spi_txfifo_reset(s);
      ibex_spi_host_irq(s);
  }
-@@ -XXX,XX +XXX,XX @@ static void ibex_spi_host_write(void *opaque, hwaddr addr,
- {
-     IbexSPIHostState *s = opaque;
-     uint32_t val32 = val64;
--    uint32_t shift_mask = 0xff;
-+    uint32_t shift_mask = 0xff, status = 0;
-     uint8_t txqd_len;
-     trace_ibex_spi_host_write(addr, size, val64);
-@@ -XXX,XX +XXX,XX @@ static void ibex_spi_host_write(void *opaque, hwaddr addr,
-         s->regs[addr] = val32;
-         /* STALL, IP not enabled */
--        if (!(s->regs[IBEX_SPI_HOST_CONTROL] & R_CONTROL_SPIEN_MASK)) {
-+        if (!(FIELD_EX32(s->regs[IBEX_SPI_HOST_CONTROL],
-+                         CONTROL, SPIEN))) {
-             return;
-         }
-         /* SPI not ready, IRQ Error */
--        if (!(s->regs[IBEX_SPI_HOST_STATUS] & R_STATUS_READY_MASK)) {
-+        if (!(FIELD_EX32(s->regs[IBEX_SPI_HOST_STATUS],
-+                         STATUS, READY))) {
-             s->regs[IBEX_SPI_HOST_ERROR_STATUS] |= R_ERROR_STATUS_CMDBUSY_MASK;
-             ibex_spi_host_irq(s);
-             return;
-         }
-+
-         /* Assert Not Ready */
-         s->regs[IBEX_SPI_HOST_STATUS] &= ~R_STATUS_READY_MASK;
--        if (((val32 & R_COMMAND_DIRECTION_MASK) >> R_COMMAND_DIRECTION_SHIFT)
--            != BIDIRECTIONAL_TRANSFER) {
--                qemu_log_mask(LOG_UNIMP,
-+        if (FIELD_EX32(val32, COMMAND, DIRECTION) != BIDIRECTIONAL_TRANSFER) {
-+            qemu_log_mask(LOG_UNIMP,
-                           "%s: Rx Only/Tx Only are not supported\n", __func__);
-         }
-@@ -XXX,XX +XXX,XX @@ static void ibex_spi_host_write(void *opaque, hwaddr addr,
-                 return;
-             }
-             /* Byte ordering is set by the IP */
--            if ((s->regs[IBEX_SPI_HOST_STATUS] &
--                R_STATUS_BYTEORDER_MASK) == 0) {
-+            status = s->regs[IBEX_SPI_HOST_STATUS];
-+            if (FIELD_EX32(status, STATUS, BYTEORDER) == 0) {
-                 /* LE: LSB transmitted first (default for ibex processor) */
-                 shift_mask = 0xff << (i * 8);
-             } else {
-@@ -XXX,XX +XXX,XX @@ static void ibex_spi_host_write(void *opaque, hwaddr addr,
-             fifo8_push(&s->tx_fifo, (val32 & shift_mask) >> (i * 8));
-         }
--
-+        status = s->regs[IBEX_SPI_HOST_STATUS];
-         /* Reset TXEMPTY */
--        s->regs[IBEX_SPI_HOST_STATUS] &= ~R_STATUS_TXEMPTY_MASK;
-+        status = FIELD_DP32(status, STATUS, TXEMPTY, 0);
-         /* Update TXQD */
--        txqd_len = (s->regs[IBEX_SPI_HOST_STATUS] &
--                    R_STATUS_TXQD_MASK) >> R_STATUS_TXQD_SHIFT;
-+        txqd_len = FIELD_EX32(status, STATUS, TXQD);
-         /* Partial bytes (size < 4) are padded, in words. */
-         txqd_len += 1;
--        s->regs[IBEX_SPI_HOST_STATUS] &= ~R_STATUS_TXQD_MASK;
--        s->regs[IBEX_SPI_HOST_STATUS] |= txqd_len;
-+        status = FIELD_DP32(status, STATUS, TXQD, txqd_len);
-         /* Assert Ready */
--        s->regs[IBEX_SPI_HOST_STATUS] |= R_STATUS_READY_MASK;
-+        status = FIELD_DP32(status, STATUS, READY, 1);
-+        /* Update register status */
-+        s->regs[IBEX_SPI_HOST_STATUS] = status;
-         break;
-     case IBEX_SPI_HOST_ERROR_ENABLE:
-         s->regs[addr] = val32;
 --
-.37.3
+.45.1

-[PULL 08/10] hw/intc: sifive_plic: fix hard-coded max priority level
+[PULL 25/28] target/riscv/kvm.c: Fix the hart bit setting of AIA
-From: Jim Shu <jim.shu@sifive.com>
+From: Yong-Xuan Wang <yongxuan.wang@sifive.com>
-The maximum priority level is hard-coded when writing to interrupt
+In AIA spec, each hart (or each hart within a group) has a unique hart
-priority register. However, when writing to priority threshold register,
+number to locate the memory pages of interrupt files in the address
-the maximum priority level is from num_priorities Property which is
+space. The number of bits required to represent any hart number is equal
-configured by platform.
+to ceil(log2(hmax + 1)), where hmax is the largest hart number among
 groups.
-Also change interrupt priority register to use num_priorities Property
+However, if the largest hart number among groups is a power of 2, QEMU
-in maximum priority level.
+will pass an inaccurate hart-index-bit setting to Linux. For example, when
 the guest OS has 4 harts, only ceil(log2(3 + 1)) = 2 bits are sufficient
 to represent 4 harts, but we passes 3 to Linux. The code needs to be
 updated to ensure accurate hart-index-bit settings.
-Signed-off-by: Emmanuel Blot <emmanuel.blot@sifive.com>
+Additionally, a Linux patch[1] is necessary to correctly recover the hart
-Signed-off-by: Jim Shu <jim.shu@sifive.com>
+index when the guest OS has only 1 hart, where the hart-index-bit is 0.
-Reviewed-by: Frank Chang <frank.chang@sifive.com>
-Acked-by: Alistair Francis <alistair.francis@wdc.com>
+[1] https://lore.kernel.org/lkml/20240415064905.25184-1-yongxuan.wang@sifive.com/t/
-Message-Id: <20221003041440.2320-2-jim.shu@sifive.com>
 Signed-off-by: Yong-Xuan Wang <yongxuan.wang@sifive.com>
 Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
 Cc: qemu-stable <qemu-stable@nongnu.org>
 Message-ID: <20240515091129.28116-1-yongxuan.wang@sifive.com>
 Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
 ---
- hw/intc/sifive_plic.c | 6 ++++--
+ target/riscv/kvm/kvm-cpu.c | 9 ++++++++-
-file changed, 4 insertions(+), 2 deletions(-)
+file changed, 8 insertions(+), 1 deletion(-)
-diff --git a/hw/intc/sifive_plic.c b/hw/intc/sifive_plic.c
+diff --git a/target/riscv/kvm/kvm-cpu.c b/target/riscv/kvm/kvm-cpu.c
 index XXXXXXX..XXXXXXX 100644
---- a/hw/intc/sifive_plic.c
+--- a/target/riscv/kvm/kvm-cpu.c
-+++ b/hw/intc/sifive_plic.c
++++ b/target/riscv/kvm/kvm-cpu.c
-@@ -XXX,XX +XXX,XX @@ static void sifive_plic_write(void *opaque, hwaddr addr, uint64_t value,
+@@ -XXX,XX +XXX,XX @@ void kvm_riscv_aia_create(MachineState *machine, uint64_t group_shift,
-     if (addr_between(addr, plic->priority_base, plic->num_sources << 2)) {
+         }
-         uint32_t irq = ((addr - plic->priority_base) >> 2) + 1;
+     }
--        plic->source_priority[irq] = value & 7;
+-    hart_bits = find_last_bit(&max_hart_per_socket, BITS_PER_LONG) + 1;
--        sifive_plic_update(plic);
++
-+        if (value <= plic->num_priorities) {
++    if (max_hart_per_socket > 1) {
-+            plic->source_priority[irq] = value;
++        max_hart_per_socket--;
-+            sifive_plic_update(plic);
++        hart_bits = find_last_bit(&max_hart_per_socket, BITS_PER_LONG) + 1;
-+        }
++    } else {
-     } else if (addr_between(addr, plic->pending_base,
++        hart_bits = 0;
-                             plic->num_sources >> 3)) {
++    }
-         qemu_log_mask(LOG_GUEST_ERROR,
++
      ret = kvm_device_access(aia_fd, KVM_DEV_RISCV_AIA_GRP_CONFIG,
                              KVM_DEV_RISCV_AIA_CONFIG_HART_BITS,
                              &hart_bits, true, NULL);
 --
-.37.3
+.45.1

-[PULL 03/10] hw/ssi: ibex_spi: fixup/add rw1c functionality
+[PULL 26/28] riscv, gdbstub.c: fix reg_width in ricsv_gen_dynamic_vector_feature()
-From: Wilfred Mallawa <wilfred.mallawa@wdc.com>
+From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
-This patch adds the `rw1c` functionality to the respective
+Commit 33a24910ae changed 'reg_width' to use 'vlenb', i.e. vector length
-registers. The status fields are cleared when the respective
+in bytes, when in this context we want 'reg_width' as the length in
-field is set.
+bits.
-Signed-off-by: Wilfred Mallawa <wilfred.mallawa@wdc.com>
+Fix 'reg_width' back to the value in bits like 7cb59921c05a
 ("target/riscv/gdbstub.c: use 'vlenb' instead of shifting 'vlen'") set
 beforehand.
 While we're at it, rename 'reg_width' to 'bitsize' to provide a bit more
 clarity about what the variable represents. 'bitsize' is also used in
 riscv_gen_dynamic_csr_feature() with the same purpose, i.e. as an input to
 gdb_feature_builder_append_reg().
 Cc: Akihiko Odaki <akihiko.odaki@daynix.com>
 Cc: Alex Bennée <alex.bennee@linaro.org>
 Reported-by: Robin Dapp <rdapp.gcc@gmail.com>
 Fixes: 33a24910ae ("target/riscv: Use GDBFeature for dynamic XML")
 Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
 Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
 Acked-by: Alex Bennée <alex.bennee@linaro.org>
 Reviewed-by: Akihiko Odaki <akihiko.odaki@daynix.com>
 Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
-Message-Id: <20220930033241.206581-3-wilfred.mallawa@opensource.wdc.com>
+Cc: qemu-stable <qemu-stable@nongnu.org>
 Message-ID: <20240517203054.880861-2-dbarboza@ventanamicro.com>
 Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
 ---
- include/hw/ssi/ibex_spi_host.h |  4 ++--
+ target/riscv/gdbstub.c | 6 +++---
- hw/ssi/ibex_spi_host.c         | 36 +++++++++++++++++++++++++++++++---
+file changed, 3 insertions(+), 3 deletions(-)
 files changed, 35 insertions(+), 5 deletions(-)
-diff --git a/include/hw/ssi/ibex_spi_host.h b/include/hw/ssi/ibex_spi_host.h
+diff --git a/target/riscv/gdbstub.c b/target/riscv/gdbstub.c
 index XXXXXXX..XXXXXXX 100644
---- a/include/hw/ssi/ibex_spi_host.h
+--- a/target/riscv/gdbstub.c
-+++ b/include/hw/ssi/ibex_spi_host.h
++++ b/target/riscv/gdbstub.c
-@@ -XXX,XX +XXX,XX @@
+@@ -XXX,XX +XXX,XX @@ static GDBFeature *riscv_gen_dynamic_csr_feature(CPUState *cs, int base_reg)
-     OBJECT_CHECK(IbexSPIHostState, (obj), TYPE_IBEX_SPI_HOST)
+ static GDBFeature *ricsv_gen_dynamic_vector_feature(CPUState *cs, int base_reg)
  /* SPI Registers */
 -#define IBEX_SPI_HOST_INTR_STATE         (0x00 / 4)  /* rw */
 +#define IBEX_SPI_HOST_INTR_STATE         (0x00 / 4)  /* rw1c */
  #define IBEX_SPI_HOST_INTR_ENABLE        (0x04 / 4)  /* rw */
  #define IBEX_SPI_HOST_INTR_TEST          (0x08 / 4)  /* wo */
  #define IBEX_SPI_HOST_ALERT_TEST         (0x0c / 4)  /* wo */
@@ -XXX,XX +XXX,XX @@
  #define IBEX_SPI_HOST_TXDATA             (0x28 / 4)
  #define IBEX_SPI_HOST_ERROR_ENABLE       (0x2c / 4)  /* rw */
 -#define IBEX_SPI_HOST_ERROR_STATUS       (0x30 / 4)  /* rw */
 +#define IBEX_SPI_HOST_ERROR_STATUS       (0x30 / 4)  /* rw1c */
  #define IBEX_SPI_HOST_EVENT_ENABLE       (0x34 / 4)  /* rw */
  /* FIFO Len in Bytes */
 diff --git a/hw/ssi/ibex_spi_host.c b/hw/ssi/ibex_spi_host.c
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/ssi/ibex_spi_host.c
 +++ b/hw/ssi/ibex_spi_host.c
@@ -XXX,XX +XXX,XX @@ static void ibex_spi_host_write(void *opaque, hwaddr addr,
  {
-     IbexSPIHostState *s = opaque;
+     RISCVCPU *cpu = RISCV_CPU(cs);
-     uint32_t val32 = val64;
+-    int reg_width = cpu->cfg.vlenb;
--    uint32_t shift_mask = 0xff, status = 0;
++    int bitsize = cpu->cfg.vlenb << 3;
-+    uint32_t shift_mask = 0xff, status = 0, data = 0;
+     GDBFeatureBuilder builder;
-     uint8_t txqd_len;
+     int i;
-     trace_ibex_spi_host_write(addr, size, val64);
+@@ -XXX,XX +XXX,XX @@ static GDBFeature *ricsv_gen_dynamic_vector_feature(CPUState *cs, int base_reg)
-@@ -XXX,XX +XXX,XX @@ static void ibex_spi_host_write(void *opaque, hwaddr addr,
+     /* First define types and totals in a whole VL */
-     switch (addr) {
+     for (i = 0; i < ARRAY_SIZE(vec_lanes); i++) {
-     /* Skipping any R/O registers */
+-        int count = reg_width / vec_lanes[i].size;
--    case IBEX_SPI_HOST_INTR_STATE...IBEX_SPI_HOST_INTR_ENABLE:
++        int count = bitsize / vec_lanes[i].size;
-+    case IBEX_SPI_HOST_INTR_STATE:
+         gdb_feature_builder_append_tag(
-+        /* rw1c status register */
+             &builder, "<vector id=\"%s\" type=\"%s\" count=\"%d\"/>",
-+        if (FIELD_EX32(val32, INTR_STATE, ERROR)) {
+             vec_lanes[i].id, vec_lanes[i].gdb_type, count);
-+            data = FIELD_DP32(data, INTR_STATE, ERROR, 0);
+@@ -XXX,XX +XXX,XX @@ static GDBFeature *ricsv_gen_dynamic_vector_feature(CPUState *cs, int base_reg)
-+        }
+     /* Define vector registers */
-+        if (FIELD_EX32(val32, INTR_STATE, SPI_EVENT)) {
+     for (i = 0; i < 32; i++) {
-+            data = FIELD_DP32(data, INTR_STATE, SPI_EVENT, 0);
+         gdb_feature_builder_append_reg(&builder, g_strdup_printf("v%d", i),
-+        }
+-                                       reg_width, i, "riscv_vector", "vector");
-+        s->regs[addr] = data;
++                                       bitsize, i, "riscv_vector", "vector");
-+        break;
+     }
-+    case IBEX_SPI_HOST_INTR_ENABLE:
-         s->regs[addr] = val32;
+     gdb_feature_builder_end(&builder);
          break;
      case IBEX_SPI_HOST_INTR_TEST:
@@ -XXX,XX +XXX,XX @@ static void ibex_spi_host_write(void *opaque, hwaddr addr,
       *  When an error occurs, the corresponding bit must be cleared
       *  here before issuing any further commands
       */
 -        s->regs[addr] = val32;
 +        status = s->regs[addr];
 +        /* rw1c status register */
 +        if (FIELD_EX32(val32, ERROR_STATUS, CMDBUSY)) {
 +            status = FIELD_DP32(status, ERROR_STATUS, CMDBUSY, 0);
 +        }
 +        if (FIELD_EX32(val32, ERROR_STATUS, OVERFLOW)) {
 +            status = FIELD_DP32(status, ERROR_STATUS, OVERFLOW, 0);
 +        }
 +        if (FIELD_EX32(val32, ERROR_STATUS, UNDERFLOW)) {
 +            status = FIELD_DP32(status, ERROR_STATUS, UNDERFLOW, 0);
 +        }
 +        if (FIELD_EX32(val32, ERROR_STATUS, CMDINVAL)) {
 +            status = FIELD_DP32(status, ERROR_STATUS, CMDINVAL, 0);
 +        }
 +        if (FIELD_EX32(val32, ERROR_STATUS, CSIDINVAL)) {
 +            status = FIELD_DP32(status, ERROR_STATUS, CSIDINVAL, 0);
 +        }
 +        if (FIELD_EX32(val32, ERROR_STATUS, ACCESSINVAL)) {
 +            status = FIELD_DP32(status, ERROR_STATUS, ACCESSINVAL, 0);
 +        }
 +        s->regs[addr] = status;
          break;
      case IBEX_SPI_HOST_EVENT_ENABLE:
      /* Controls which classes of SPI events raise an interrupt. */
 --
-.37.3
+.45.1

-[PULL 07/10] disas/riscv.c: rvv: Add disas support for vector instructions
+[PULL 27/28] disas/riscv: Decode all of the pmpcfg and pmpaddr CSRs
-From: Yang Liu <liuyang22@iscas.ac.cn>
+From: Alistair Francis <alistair23@gmail.com>
-Tested with https://github.com/ksco/rvv-decoder-tests
+Previously we only listed a single pmpcfg CSR and the first 16 pmpaddr
 CSRs. This patch fixes this to list all 16 pmpcfg and all 64 pmpaddr
 CSRs are part of the disassembly.
-Expected checkpatch errors for consistency and brevity reasons:
+Reported-by: Eric DeVolder <eric_devolder@yahoo.com>
+Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
-ERROR: line over 90 characters
+Fixes: ea10325917 ("RISC-V Disassembler")
-ERROR: trailing statements should be on next line
+Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
-ERROR: braces {} are necessary for all arms of this statement
+Cc: qemu-stable <qemu-stable@nongnu.org>
+Message-ID: <20240514051615.330979-1-alistair.francis@wdc.com>
 Signed-off-by: Yang Liu <liuyang22@iscas.ac.cn>
 Acked-by: Alistair Francis <alistair.francis@wdc.com>
 Message-Id: <20220928051842.16207-1-liuyang22@iscas.ac.cn>
 Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
 ---
- disas/riscv.c | 1432 ++++++++++++++++++++++++++++++++++++++++++++++++-
+ disas/riscv.c | 65 ++++++++++++++++++++++++++++++++++++++++++++++++++-
-file changed, 1430 insertions(+), 2 deletions(-)
+file changed, 64 insertions(+), 1 deletion(-)
 diff --git a/disas/riscv.c b/disas/riscv.c
 index XXXXXXX..XXXXXXX 100644
 --- a/disas/riscv.c
 +++ b/disas/riscv.c
-@@ -XXX,XX +XXX,XX @@ typedef enum {
-     rv_codec_css_sqsp,
-     rv_codec_k_bs,
-     rv_codec_k_rnum,
-+    rv_codec_v_r,
-+    rv_codec_v_ldst,
-+    rv_codec_v_i,
-+    rv_codec_vsetvli,
-+    rv_codec_vsetivli,
- } rv_codec;
- typedef enum {
-@@ -XXX,XX +XXX,XX @@ typedef enum {
-     rv_op_zip = 396,
-     rv_op_xperm4 = 397,
-     rv_op_xperm8 = 398,
-+    rv_op_vle8_v = 399,
-+    rv_op_vle16_v = 400,
-+    rv_op_vle32_v = 401,
-+    rv_op_vle64_v = 402,
-+    rv_op_vse8_v = 403,
-+    rv_op_vse16_v = 404,
-+    rv_op_vse32_v = 405,
-+    rv_op_vse64_v = 406,
-+    rv_op_vlm_v = 407,
-+    rv_op_vsm_v = 408,
-+    rv_op_vlse8_v = 409,
-+    rv_op_vlse16_v = 410,
-+    rv_op_vlse32_v = 411,
-+    rv_op_vlse64_v = 412,
-+    rv_op_vsse8_v = 413,
-+    rv_op_vsse16_v = 414,
-+    rv_op_vsse32_v = 415,
-+    rv_op_vsse64_v = 416,
-+    rv_op_vluxei8_v = 417,
-+    rv_op_vluxei16_v = 418,
-+    rv_op_vluxei32_v = 419,
-+    rv_op_vluxei64_v = 420,
-+    rv_op_vloxei8_v = 421,
-+    rv_op_vloxei16_v = 422,
-+    rv_op_vloxei32_v = 423,
-+    rv_op_vloxei64_v = 424,
-+    rv_op_vsuxei8_v = 425,
-+    rv_op_vsuxei16_v = 426,
-+    rv_op_vsuxei32_v = 427,
-+    rv_op_vsuxei64_v = 428,
-+    rv_op_vsoxei8_v = 429,
-+    rv_op_vsoxei16_v = 430,
-+    rv_op_vsoxei32_v = 431,
-+    rv_op_vsoxei64_v = 432,
-+    rv_op_vle8ff_v = 433,
-+    rv_op_vle16ff_v = 434,
-+    rv_op_vle32ff_v = 435,
-+    rv_op_vle64ff_v = 436,
-+    rv_op_vl1re8_v = 437,
-+    rv_op_vl1re16_v = 438,
-+    rv_op_vl1re32_v = 439,
-+    rv_op_vl1re64_v = 440,
-+    rv_op_vl2re8_v = 441,
-+    rv_op_vl2re16_v = 442,
-+    rv_op_vl2re32_v = 443,
-+    rv_op_vl2re64_v = 444,
-+    rv_op_vl4re8_v = 445,
-+    rv_op_vl4re16_v = 446,
-+    rv_op_vl4re32_v = 447,
-+    rv_op_vl4re64_v = 448,
-+    rv_op_vl8re8_v = 449,
-+    rv_op_vl8re16_v = 450,
-+    rv_op_vl8re32_v = 451,
-+    rv_op_vl8re64_v = 452,
-+    rv_op_vs1r_v = 453,
-+    rv_op_vs2r_v = 454,
-+    rv_op_vs4r_v = 455,
-+    rv_op_vs8r_v = 456,
-+    rv_op_vadd_vv = 457,
-+    rv_op_vadd_vx = 458,
-+    rv_op_vadd_vi = 459,
-+    rv_op_vsub_vv = 460,
-+    rv_op_vsub_vx = 461,
-+    rv_op_vrsub_vx = 462,
-+    rv_op_vrsub_vi = 463,
-+    rv_op_vwaddu_vv = 464,
-+    rv_op_vwaddu_vx = 465,
-+    rv_op_vwadd_vv = 466,
-+    rv_op_vwadd_vx = 467,
-+    rv_op_vwsubu_vv = 468,
-+    rv_op_vwsubu_vx = 469,
-+    rv_op_vwsub_vv = 470,
-+    rv_op_vwsub_vx = 471,
-+    rv_op_vwaddu_wv = 472,
-+    rv_op_vwaddu_wx = 473,
-+    rv_op_vwadd_wv = 474,
-+    rv_op_vwadd_wx = 475,
-+    rv_op_vwsubu_wv = 476,
-+    rv_op_vwsubu_wx = 477,
-+    rv_op_vwsub_wv = 478,
-+    rv_op_vwsub_wx = 479,
-+    rv_op_vadc_vvm = 480,
-+    rv_op_vadc_vxm = 481,
-+    rv_op_vadc_vim = 482,
-+    rv_op_vmadc_vvm = 483,
-+    rv_op_vmadc_vxm = 484,
-+    rv_op_vmadc_vim = 485,
-+    rv_op_vsbc_vvm = 486,
-+    rv_op_vsbc_vxm = 487,
-+    rv_op_vmsbc_vvm = 488,
-+    rv_op_vmsbc_vxm = 489,
-+    rv_op_vand_vv = 490,
-+    rv_op_vand_vx = 491,
-+    rv_op_vand_vi = 492,
-+    rv_op_vor_vv = 493,
-+    rv_op_vor_vx = 494,
-+    rv_op_vor_vi = 495,
-+    rv_op_vxor_vv = 496,
-+    rv_op_vxor_vx = 497,
-+    rv_op_vxor_vi = 498,
-+    rv_op_vsll_vv = 499,
-+    rv_op_vsll_vx = 500,
-+    rv_op_vsll_vi = 501,
-+    rv_op_vsrl_vv = 502,
-+    rv_op_vsrl_vx = 503,
-+    rv_op_vsrl_vi = 504,
-+    rv_op_vsra_vv = 505,
-+    rv_op_vsra_vx = 506,
-+    rv_op_vsra_vi = 507,
-+    rv_op_vnsrl_wv = 508,
-+    rv_op_vnsrl_wx = 509,
-+    rv_op_vnsrl_wi = 510,
-+    rv_op_vnsra_wv = 511,
-+    rv_op_vnsra_wx = 512,
-+    rv_op_vnsra_wi = 513,
-+    rv_op_vmseq_vv = 514,
-+    rv_op_vmseq_vx = 515,
-+    rv_op_vmseq_vi = 516,
-+    rv_op_vmsne_vv = 517,
-+    rv_op_vmsne_vx = 518,
-+    rv_op_vmsne_vi = 519,
-+    rv_op_vmsltu_vv = 520,
-+    rv_op_vmsltu_vx = 521,
-+    rv_op_vmslt_vv = 522,
-+    rv_op_vmslt_vx = 523,
-+    rv_op_vmsleu_vv = 524,
-+    rv_op_vmsleu_vx = 525,
-+    rv_op_vmsleu_vi = 526,
-+    rv_op_vmsle_vv = 527,
-+    rv_op_vmsle_vx = 528,
-+    rv_op_vmsle_vi = 529,
-+    rv_op_vmsgtu_vx = 530,
-+    rv_op_vmsgtu_vi = 531,
-+    rv_op_vmsgt_vx = 532,
-+    rv_op_vmsgt_vi = 533,
-+    rv_op_vminu_vv = 534,
-+    rv_op_vminu_vx = 535,
-+    rv_op_vmin_vv = 536,
-+    rv_op_vmin_vx = 537,
-+    rv_op_vmaxu_vv = 538,
-+    rv_op_vmaxu_vx = 539,
-+    rv_op_vmax_vv = 540,
-+    rv_op_vmax_vx = 541,
-+    rv_op_vmul_vv = 542,
-+    rv_op_vmul_vx = 543,
-+    rv_op_vmulh_vv = 544,
-+    rv_op_vmulh_vx = 545,
-+    rv_op_vmulhu_vv = 546,
-+    rv_op_vmulhu_vx = 547,
-+    rv_op_vmulhsu_vv = 548,
-+    rv_op_vmulhsu_vx = 549,
-+    rv_op_vdivu_vv = 550,
-+    rv_op_vdivu_vx = 551,
-+    rv_op_vdiv_vv = 552,
-+    rv_op_vdiv_vx = 553,
-+    rv_op_vremu_vv = 554,
-+    rv_op_vremu_vx = 555,
-+    rv_op_vrem_vv = 556,
-+    rv_op_vrem_vx = 557,
-+    rv_op_vwmulu_vv = 558,
-+    rv_op_vwmulu_vx = 559,
-+    rv_op_vwmulsu_vv = 560,
-+    rv_op_vwmulsu_vx = 561,
-+    rv_op_vwmul_vv = 562,
-+    rv_op_vwmul_vx = 563,
-+    rv_op_vmacc_vv = 564,
-+    rv_op_vmacc_vx = 565,
-+    rv_op_vnmsac_vv = 566,
-+    rv_op_vnmsac_vx = 567,
-+    rv_op_vmadd_vv = 568,
-+    rv_op_vmadd_vx = 569,
-+    rv_op_vnmsub_vv = 570,
-+    rv_op_vnmsub_vx = 571,
-+    rv_op_vwmaccu_vv = 572,
-+    rv_op_vwmaccu_vx = 573,
-+    rv_op_vwmacc_vv = 574,
-+    rv_op_vwmacc_vx = 575,
-+    rv_op_vwmaccsu_vv = 576,
-+    rv_op_vwmaccsu_vx = 577,
-+    rv_op_vwmaccus_vx = 578,
-+    rv_op_vmv_v_v = 579,
-+    rv_op_vmv_v_x = 580,
-+    rv_op_vmv_v_i = 581,
-+    rv_op_vmerge_vvm = 582,
-+    rv_op_vmerge_vxm = 583,
-+    rv_op_vmerge_vim = 584,
-+    rv_op_vsaddu_vv = 585,
-+    rv_op_vsaddu_vx = 586,
-+    rv_op_vsaddu_vi = 587,
-+    rv_op_vsadd_vv = 588,
-+    rv_op_vsadd_vx = 589,
-+    rv_op_vsadd_vi = 590,
-+    rv_op_vssubu_vv = 591,
-+    rv_op_vssubu_vx = 592,
-+    rv_op_vssub_vv = 593,
-+    rv_op_vssub_vx = 594,
-+    rv_op_vaadd_vv = 595,
-+    rv_op_vaadd_vx = 596,
-+    rv_op_vaaddu_vv = 597,
-+    rv_op_vaaddu_vx = 598,
-+    rv_op_vasub_vv = 599,
-+    rv_op_vasub_vx = 600,
-+    rv_op_vasubu_vv = 601,
-+    rv_op_vasubu_vx = 602,
-+    rv_op_vsmul_vv = 603,
-+    rv_op_vsmul_vx = 604,
-+    rv_op_vssrl_vv = 605,
-+    rv_op_vssrl_vx = 606,
-+    rv_op_vssrl_vi = 607,
-+    rv_op_vssra_vv = 608,
-+    rv_op_vssra_vx = 609,
-+    rv_op_vssra_vi = 610,
-+    rv_op_vnclipu_wv = 611,
-+    rv_op_vnclipu_wx = 612,
-+    rv_op_vnclipu_wi = 613,
-+    rv_op_vnclip_wv = 614,
-+    rv_op_vnclip_wx = 615,
-+    rv_op_vnclip_wi = 616,
-+    rv_op_vfadd_vv = 617,
-+    rv_op_vfadd_vf = 618,
-+    rv_op_vfsub_vv = 619,
-+    rv_op_vfsub_vf = 620,
-+    rv_op_vfrsub_vf = 621,
-+    rv_op_vfwadd_vv = 622,
-+    rv_op_vfwadd_vf = 623,
-+    rv_op_vfwadd_wv = 624,
-+    rv_op_vfwadd_wf = 625,
-+    rv_op_vfwsub_vv = 626,
-+    rv_op_vfwsub_vf = 627,
-+    rv_op_vfwsub_wv = 628,
-+    rv_op_vfwsub_wf = 629,
-+    rv_op_vfmul_vv = 630,
-+    rv_op_vfmul_vf = 631,
-+    rv_op_vfdiv_vv = 632,
-+    rv_op_vfdiv_vf = 633,
-+    rv_op_vfrdiv_vf = 634,
-+    rv_op_vfwmul_vv = 635,
-+    rv_op_vfwmul_vf = 636,
-+    rv_op_vfmacc_vv = 637,
-+    rv_op_vfmacc_vf = 638,
-+    rv_op_vfnmacc_vv = 639,
-+    rv_op_vfnmacc_vf = 640,
-+    rv_op_vfmsac_vv = 641,
-+    rv_op_vfmsac_vf = 642,
-+    rv_op_vfnmsac_vv = 643,
-+    rv_op_vfnmsac_vf = 644,
-+    rv_op_vfmadd_vv = 645,
-+    rv_op_vfmadd_vf = 646,
-+    rv_op_vfnmadd_vv = 647,
-+    rv_op_vfnmadd_vf = 648,
-+    rv_op_vfmsub_vv = 649,
-+    rv_op_vfmsub_vf = 650,
-+    rv_op_vfnmsub_vv = 651,
-+    rv_op_vfnmsub_vf = 652,
-+    rv_op_vfwmacc_vv = 653,
-+    rv_op_vfwmacc_vf = 654,
-+    rv_op_vfwnmacc_vv = 655,
-+    rv_op_vfwnmacc_vf = 656,
-+    rv_op_vfwmsac_vv = 657,
-+    rv_op_vfwmsac_vf = 658,
-+    rv_op_vfwnmsac_vv = 659,
-+    rv_op_vfwnmsac_vf = 660,
-+    rv_op_vfsqrt_v = 661,
-+    rv_op_vfrsqrt7_v = 662,
-+    rv_op_vfrec7_v = 663,
-+    rv_op_vfmin_vv = 664,
-+    rv_op_vfmin_vf = 665,
-+    rv_op_vfmax_vv = 666,
-+    rv_op_vfmax_vf = 667,
-+    rv_op_vfsgnj_vv = 668,
-+    rv_op_vfsgnj_vf = 669,
-+    rv_op_vfsgnjn_vv = 670,
-+    rv_op_vfsgnjn_vf = 671,
-+    rv_op_vfsgnjx_vv = 672,
-+    rv_op_vfsgnjx_vf = 673,
-+    rv_op_vfslide1up_vf = 674,
-+    rv_op_vfslide1down_vf = 675,
-+    rv_op_vmfeq_vv = 676,
-+    rv_op_vmfeq_vf = 677,
-+    rv_op_vmfne_vv = 678,
-+    rv_op_vmfne_vf = 679,
-+    rv_op_vmflt_vv = 680,
-+    rv_op_vmflt_vf = 681,
-+    rv_op_vmfle_vv = 682,
-+    rv_op_vmfle_vf = 683,
-+    rv_op_vmfgt_vf = 684,
-+    rv_op_vmfge_vf = 685,
-+    rv_op_vfclass_v = 686,
-+    rv_op_vfmerge_vfm = 687,
-+    rv_op_vfmv_v_f = 688,
-+    rv_op_vfcvt_xu_f_v = 689,
-+    rv_op_vfcvt_x_f_v = 690,
-+    rv_op_vfcvt_f_xu_v = 691,
-+    rv_op_vfcvt_f_x_v = 692,
-+    rv_op_vfcvt_rtz_xu_f_v = 693,
-+    rv_op_vfcvt_rtz_x_f_v = 694,
-+    rv_op_vfwcvt_xu_f_v = 695,
-+    rv_op_vfwcvt_x_f_v = 696,
-+    rv_op_vfwcvt_f_xu_v = 697,
-+    rv_op_vfwcvt_f_x_v = 698,
-+    rv_op_vfwcvt_f_f_v = 699,
-+    rv_op_vfwcvt_rtz_xu_f_v = 700,
-+    rv_op_vfwcvt_rtz_x_f_v = 701,
-+    rv_op_vfncvt_xu_f_w = 702,
-+    rv_op_vfncvt_x_f_w = 703,
-+    rv_op_vfncvt_f_xu_w = 704,
-+    rv_op_vfncvt_f_x_w = 705,
-+    rv_op_vfncvt_f_f_w = 706,
-+    rv_op_vfncvt_rod_f_f_w = 707,
-+    rv_op_vfncvt_rtz_xu_f_w = 708,
-+    rv_op_vfncvt_rtz_x_f_w = 709,
-+    rv_op_vredsum_vs = 710,
-+    rv_op_vredand_vs = 711,
-+    rv_op_vredor_vs = 712,
-+    rv_op_vredxor_vs = 713,
-+    rv_op_vredminu_vs = 714,
-+    rv_op_vredmin_vs = 715,
-+    rv_op_vredmaxu_vs = 716,
-+    rv_op_vredmax_vs = 717,
-+    rv_op_vwredsumu_vs = 718,
-+    rv_op_vwredsum_vs = 719,
-+    rv_op_vfredusum_vs = 720,
-+    rv_op_vfredosum_vs = 721,
-+    rv_op_vfredmin_vs = 722,
-+    rv_op_vfredmax_vs = 723,
-+    rv_op_vfwredusum_vs = 724,
-+    rv_op_vfwredosum_vs = 725,
-+    rv_op_vmand_mm = 726,
-+    rv_op_vmnand_mm = 727,
-+    rv_op_vmandn_mm = 728,
-+    rv_op_vmxor_mm = 729,
-+    rv_op_vmor_mm = 730,
-+    rv_op_vmnor_mm = 731,
-+    rv_op_vmorn_mm = 732,
-+    rv_op_vmxnor_mm = 733,
-+    rv_op_vcpop_m = 734,
-+    rv_op_vfirst_m = 735,
-+    rv_op_vmsbf_m = 736,
-+    rv_op_vmsif_m = 737,
-+    rv_op_vmsof_m = 738,
-+    rv_op_viota_m = 739,
-+    rv_op_vid_v = 740,
-+    rv_op_vmv_x_s = 741,
-+    rv_op_vmv_s_x = 742,
-+    rv_op_vfmv_f_s = 743,
-+    rv_op_vfmv_s_f = 744,
-+    rv_op_vslideup_vx = 745,
-+    rv_op_vslideup_vi = 746,
-+    rv_op_vslide1up_vx = 747,
-+    rv_op_vslidedown_vx = 748,
-+    rv_op_vslidedown_vi = 749,
-+    rv_op_vslide1down_vx = 750,
-+    rv_op_vrgather_vv = 751,
-+    rv_op_vrgatherei16_vv = 752,
-+    rv_op_vrgather_vx = 753,
-+    rv_op_vrgather_vi = 754,
-+    rv_op_vcompress_vm = 755,
-+    rv_op_vmv1r_v = 756,
-+    rv_op_vmv2r_v = 757,
-+    rv_op_vmv4r_v = 758,
-+    rv_op_vmv8r_v = 759,
-+    rv_op_vzext_vf2 = 760,
-+    rv_op_vzext_vf4 = 761,
-+    rv_op_vzext_vf8 = 762,
-+    rv_op_vsext_vf2 = 763,
-+    rv_op_vsext_vf4 = 764,
-+    rv_op_vsext_vf8 = 765,
-+    rv_op_vsetvli = 766,
-+    rv_op_vsetivli = 767,
-+    rv_op_vsetvl = 768,
- } rv_op;
- /* structures */
-@@ -XXX,XX +XXX,XX @@ typedef struct {
-     uint8_t   rl;
-     uint8_t   bs;
-     uint8_t   rnum;
-+    uint8_t   vm;
-+    uint32_t  vzimm;
- } rv_decode;
- typedef struct {
-@@ -XXX,XX +XXX,XX @@ static const char rv_freg_name_sym[32][5] = {
-     "fs8",  "fs9",  "fs10", "fs11", "ft8",  "ft9",  "ft10", "ft11",
- };
-+static const char rv_vreg_name_sym[32][4] = {
-+    "v0",  "v1",  "v2",  "v3",  "v4",  "v5",  "v6",  "v7",
-+    "v8",  "v9",  "v10", "v11", "v12", "v13", "v14", "v15",
-+    "v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23",
-+    "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31"
-+};
-+
- /* instruction formats */
- #define rv_fmt_none                   "O\t"
-@@ -XXX,XX +XXX,XX @@ static const char rv_freg_name_sym[32][5] = {
- #define rv_fmt_rs2_offset             "O\t2,o"
- #define rv_fmt_rs1_rs2_bs             "O\t1,2,b"
- #define rv_fmt_rd_rs1_rnum            "O\t0,1,n"
-+#define rv_fmt_ldst_vd_rs1_vm         "O\tD,(1)m"
-+#define rv_fmt_ldst_vd_rs1_rs2_vm     "O\tD,(1),2m"
-+#define rv_fmt_ldst_vd_rs1_vs2_vm     "O\tD,(1),Fm"
-+#define rv_fmt_vd_vs2_vs1             "O\tD,F,E"
-+#define rv_fmt_vd_vs2_vs1_vl          "O\tD,F,El"
-+#define rv_fmt_vd_vs2_vs1_vm          "O\tD,F,Em"
-+#define rv_fmt_vd_vs2_rs1_vl          "O\tD,F,1l"
-+#define rv_fmt_vd_vs2_fs1_vl          "O\tD,F,4l"
-+#define rv_fmt_vd_vs2_rs1_vm          "O\tD,F,1m"
-+#define rv_fmt_vd_vs2_fs1_vm          "O\tD,F,4m"
-+#define rv_fmt_vd_vs2_imm_vl          "O\tD,F,il"
-+#define rv_fmt_vd_vs2_imm_vm          "O\tD,F,im"
-+#define rv_fmt_vd_vs2_uimm_vm         "O\tD,F,um"
-+#define rv_fmt_vd_vs1_vs2_vm          "O\tD,E,Fm"
-+#define rv_fmt_vd_rs1_vs2_vm          "O\tD,1,Fm"
-+#define rv_fmt_vd_fs1_vs2_vm          "O\tD,4,Fm"
-+#define rv_fmt_vd_vs1                 "O\tD,E"
-+#define rv_fmt_vd_rs1                 "O\tD,1"
-+#define rv_fmt_vd_fs1                 "O\tD,4"
-+#define rv_fmt_vd_imm                 "O\tD,i"
-+#define rv_fmt_vd_vs2                 "O\tD,F"
-+#define rv_fmt_vd_vs2_vm              "O\tD,Fm"
-+#define rv_fmt_rd_vs2_vm              "O\t0,Fm"
-+#define rv_fmt_rd_vs2                 "O\t0,F"
-+#define rv_fmt_fd_vs2                 "O\t3,F"
-+#define rv_fmt_vd_vm                  "O\tDm"
-+#define rv_fmt_vsetvli                "O\t0,1,v"
-+#define rv_fmt_vsetivli               "O\t0,u,v"
- /* pseudo-instruction constraints */
-@@ -XXX,XX +XXX,XX @@ const rv_opcode_data opcode_data[] = {
-     { "unzip", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
-     { "zip", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
-     { "xperm4", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
--    { "xperm8", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 }
-+    { "xperm8", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
-+    { "vle8.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, rv_op_vle8_v, rv_op_vle8_v, 0 },
-+    { "vle16.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, rv_op_vle16_v, rv_op_vle16_v, 0 },
-+    { "vle32.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, rv_op_vle32_v, rv_op_vle32_v, 0 },
-+    { "vle64.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, rv_op_vle64_v, rv_op_vle64_v, 0 },
-+    { "vse8.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, rv_op_vse8_v, rv_op_vse8_v, 0 },
-+    { "vse16.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, rv_op_vse16_v, rv_op_vse16_v, 0 },
-+    { "vse32.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, rv_op_vse32_v, rv_op_vse32_v, 0 },
-+    { "vse64.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, rv_op_vse64_v, rv_op_vse64_v, 0 },
-+    { "vlm.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, rv_op_vlm_v, rv_op_vlm_v, 0 },
-+    { "vsm.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, rv_op_vsm_v, rv_op_vsm_v, 0 },
-+    { "vlse8.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_rs2_vm, NULL, rv_op_vlse8_v, rv_op_vlse8_v, 0 },
-+    { "vlse16.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_rs2_vm, NULL, rv_op_vlse16_v, rv_op_vlse16_v, 0 },
-+    { "vlse32.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_rs2_vm, NULL, rv_op_vlse32_v, rv_op_vlse32_v, 0 },
-+    { "vlse64.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_rs2_vm, NULL, rv_op_vlse64_v, rv_op_vlse64_v, 0 },
-+    { "vsse8.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_rs2_vm, NULL, rv_op_vsse8_v, rv_op_vsse8_v, 0 },
-+    { "vsse16.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_rs2_vm, NULL, rv_op_vsse16_v, rv_op_vsse16_v, 0 },
-+    { "vsse32.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_rs2_vm, NULL, rv_op_vsse32_v, rv_op_vsse32_v, 0 },
-+    { "vsse64.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_rs2_vm, NULL, rv_op_vsse64_v, rv_op_vsse64_v, 0 },
-+    { "vluxei8.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_vs2_vm, NULL, rv_op_vluxei8_v, rv_op_vluxei8_v, 0 },
-+    { "vluxei16.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_vs2_vm, NULL, rv_op_vluxei16_v, rv_op_vluxei16_v, 0 },
-+    { "vluxei32.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_vs2_vm, NULL, rv_op_vluxei32_v, rv_op_vluxei32_v, 0 },
-+    { "vluxei64.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_vs2_vm, NULL, rv_op_vluxei64_v, rv_op_vluxei64_v, 0 },
-+    { "vloxei8.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_vs2_vm, NULL, rv_op_vloxei8_v, rv_op_vloxei8_v, 0 },
-+    { "vloxei16.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_vs2_vm, NULL, rv_op_vloxei16_v, rv_op_vloxei16_v, 0 },
-+    { "vloxei32.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_vs2_vm, NULL, rv_op_vloxei32_v, rv_op_vloxei32_v, 0 },
-+    { "vloxei64.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_vs2_vm, NULL, rv_op_vloxei64_v, rv_op_vloxei64_v, 0 },
-+    { "vsuxei8.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_vs2_vm, NULL, rv_op_vsuxei8_v, rv_op_vsuxei8_v, 0 },
-+    { "vsuxei16.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_vs2_vm, NULL, rv_op_vsuxei16_v, rv_op_vsuxei16_v, 0 },
-+    { "vsuxei32.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_vs2_vm, NULL, rv_op_vsuxei32_v, rv_op_vsuxei32_v, 0 },
-+    { "vsuxei64.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_vs2_vm, NULL, rv_op_vsuxei64_v, rv_op_vsuxei64_v, 0 },
-+    { "vsoxei8.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_vs2_vm, NULL, rv_op_vsoxei8_v, rv_op_vsoxei8_v, 0 },
-+    { "vsoxei16.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_vs2_vm, NULL, rv_op_vsoxei16_v, rv_op_vsoxei16_v, 0 },
-+    { "vsoxei32.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_vs2_vm, NULL, rv_op_vsoxei32_v, rv_op_vsoxei32_v, 0 },
-+    { "vsoxei64.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_vs2_vm, NULL, rv_op_vsoxei64_v, rv_op_vsoxei64_v, 0 },
-+    { "vle8ff.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, rv_op_vle8ff_v, rv_op_vle8ff_v, 0 },
-+    { "vle16ff.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, rv_op_vle16ff_v, rv_op_vle16ff_v, 0 },
-+    { "vle32ff.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, rv_op_vle32ff_v, rv_op_vle32ff_v, 0 },
-+    { "vle64ff.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, rv_op_vle64ff_v, rv_op_vle64ff_v, 0 },
-+    { "vl1re8.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, rv_op_vl1re8_v, rv_op_vl1re8_v, 0 },
-+    { "vl1re16.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, rv_op_vl1re16_v, rv_op_vl1re16_v, 0 },
-+    { "vl1re32.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, rv_op_vl1re32_v, rv_op_vl1re32_v, 0 },
-+    { "vl1re64.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, rv_op_vl1re64_v, rv_op_vl1re64_v, 0 },
-+    { "vl2re8.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, rv_op_vl2re8_v, rv_op_vl2re8_v, 0 },
-+    { "vl2re16.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, rv_op_vl2re16_v, rv_op_vl2re16_v, 0 },
-+    { "vl2re32.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, rv_op_vl2re32_v, rv_op_vl2re32_v, 0 },
-+    { "vl2re64.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, rv_op_vl2re64_v, rv_op_vl2re64_v, 0 },
-+    { "vl4re8.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, rv_op_vl4re8_v, rv_op_vl4re8_v, 0 },
-+    { "vl4re16.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, rv_op_vl4re16_v, rv_op_vl4re16_v, 0 },
-+    { "vl4re32.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, rv_op_vl4re32_v, rv_op_vl4re32_v, 0 },
-+    { "vl4re64.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, rv_op_vl4re64_v, rv_op_vl4re64_v, 0 },
-+    { "vl8re8.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, rv_op_vl8re8_v, rv_op_vl8re8_v, 0 },
-+    { "vl8re16.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, rv_op_vl8re16_v, rv_op_vl8re16_v, 0 },
-+    { "vl8re32.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, rv_op_vl8re32_v, rv_op_vl8re32_v, 0 },
-+    { "vl8re64.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, rv_op_vl8re64_v, rv_op_vl8re64_v, 0 },
-+    { "vs1r.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, rv_op_vs1r_v, rv_op_vs1r_v, 0 },
-+    { "vs2r.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, rv_op_vs2r_v, rv_op_vs2r_v, 0 },
-+    { "vs4r.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, rv_op_vs4r_v, rv_op_vs4r_v, 0 },
-+    { "vs8r.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, rv_op_vs8r_v, rv_op_vs8r_v, 0 },
-+    { "vadd.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vadd_vv, rv_op_vadd_vv, 0 },
-+    { "vadd.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, rv_op_vadd_vx, rv_op_vadd_vx, 0 },
-+    { "vadd.vi", rv_codec_v_i, rv_fmt_vd_vs2_imm_vm, NULL, rv_op_vadd_vi, rv_op_vadd_vi, 0 },
-+    { "vsub.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vsub_vv, rv_op_vsub_vv, 0 },
-+    { "vsub.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, rv_op_vsub_vx, rv_op_vsub_vx, 0 },
-+    { "vrsub.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, rv_op_vrsub_vx, rv_op_vrsub_vx, 0 },
-+    { "vrsub.vi", rv_codec_v_i, rv_fmt_vd_vs2_imm_vm, NULL, rv_op_vrsub_vi, rv_op_vrsub_vi, 0 },
-+    { "vwaddu.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vwaddu_vv, rv_op_vwaddu_vv, 0 },
-+    { "vwaddu.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, rv_op_vwaddu_vx, rv_op_vwaddu_vx, 0 },
-+    { "vwadd.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vwadd_vv, rv_op_vwadd_vv, 0 },
-+    { "vwadd.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, rv_op_vwadd_vx, rv_op_vwadd_vx, 0 },
-+    { "vwsubu.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vwsubu_vv, rv_op_vwsubu_vv, 0 },
-+    { "vwsubu.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, rv_op_vwsubu_vx, rv_op_vwsubu_vx, 0 },
-+    { "vwsub.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vwsub_vv, rv_op_vwsub_vv, 0 },
-+    { "vwsub.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, rv_op_vwsub_vx, rv_op_vwsub_vx, 0 },
-+    { "vwaddu.wv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vwaddu_wv, rv_op_vwaddu_wv, 0 },
-+    { "vwaddu.wx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, rv_op_vwaddu_wx, rv_op_vwaddu_wx, 0 },
-+    { "vwadd.wv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vwadd_wv, rv_op_vwadd_wv, 0 },
-+    { "vwadd.wx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, rv_op_vwadd_wx, rv_op_vwadd_wx, 0 },
-+    { "vwsubu.wv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vwsubu_wv, rv_op_vwsubu_wv, 0 },
-+    { "vwsubu.wx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, rv_op_vwsubu_wx, rv_op_vwsubu_wx, 0 },
-+    { "vwsub.wv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vwsub_wv, rv_op_vwsub_wv, 0 },
-+    { "vwsub.wx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, rv_op_vwsub_wx, rv_op_vwsub_wx, 0 },
-+    { "vadc.vvm", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vl, NULL, rv_op_vadc_vvm, rv_op_vadc_vvm, 0 },
-+    { "vadc.vxm", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vl, NULL, rv_op_vadc_vxm, rv_op_vadc_vxm, 0 },
-+    { "vadc.vim", rv_codec_v_i, rv_fmt_vd_vs2_imm_vl, NULL, rv_op_vadc_vim, rv_op_vadc_vim, 0 },
-+    { "vmadc.vvm", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vl, NULL, rv_op_vmadc_vvm, rv_op_vmadc_vvm, 0 },
-+    { "vmadc.vxm", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vl, NULL, rv_op_vmadc_vxm, rv_op_vmadc_vxm, 0 },
-+    { "vmadc.vim", rv_codec_v_i, rv_fmt_vd_vs2_imm_vl, NULL, rv_op_vmadc_vim, rv_op_vmadc_vim, 0 },
-+    { "vsbc.vvm", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vl, NULL, rv_op_vsbc_vvm, rv_op_vsbc_vvm, 0 },
-+    { "vsbc.vxm", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vl, NULL, rv_op_vsbc_vxm, rv_op_vsbc_vxm, 0 },
-+    { "vmsbc.vvm", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vl, NULL, rv_op_vmsbc_vvm, rv_op_vmsbc_vvm, 0 },
-+    { "vmsbc.vxm", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vl, NULL, rv_op_vmsbc_vxm, rv_op_vmsbc_vxm, 0 },
-+    { "vand.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vand_vv, rv_op_vand_vv, 0 },
-+    { "vand.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, rv_op_vand_vx, rv_op_vand_vx, 0 },
-+    { "vand.vi", rv_codec_v_i, rv_fmt_vd_vs2_imm_vm, NULL, rv_op_vand_vi, rv_op_vand_vi, 0 },
-+    { "vor.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vor_vv, rv_op_vor_vv, 0 },
-+    { "vor.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, rv_op_vor_vx, rv_op_vor_vx, 0 },
-+    { "vor.vi", rv_codec_v_i, rv_fmt_vd_vs2_imm_vm, NULL, rv_op_vor_vi, rv_op_vor_vi, 0 },
-+    { "vxor.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vxor_vv, rv_op_vxor_vv, 0 },
-+    { "vxor.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, rv_op_vxor_vx, rv_op_vxor_vx, 0 },
-+    { "vxor.vi", rv_codec_v_i, rv_fmt_vd_vs2_imm_vm, NULL, rv_op_vxor_vi, rv_op_vxor_vi, 0 },
-+    { "vsll.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vsll_vv, rv_op_vsll_vv, 0 },
-+    { "vsll.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, rv_op_vsll_vx, rv_op_vsll_vx, 0 },
-+    { "vsll.vi", rv_codec_v_i, rv_fmt_vd_vs2_uimm_vm, NULL, rv_op_vsll_vi, rv_op_vsll_vi, 0 },
-+    { "vsrl.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vsrl_vv, rv_op_vsrl_vv, 0 },
-+    { "vsrl.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, rv_op_vsrl_vx, rv_op_vsrl_vx, 0 },
-+    { "vsrl.vi", rv_codec_v_i, rv_fmt_vd_vs2_uimm_vm, NULL, rv_op_vsrl_vi, rv_op_vsrl_vi, 0 },
-+    { "vsra.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vsra_vv, rv_op_vsra_vv, 0 },
-+    { "vsra.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, rv_op_vsra_vx, rv_op_vsra_vx, 0 },
-+    { "vsra.vi", rv_codec_v_i, rv_fmt_vd_vs2_uimm_vm, NULL, rv_op_vsra_vi, rv_op_vsra_vi, 0 },
-+    { "vnsrl.wv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vnsrl_wv, rv_op_vnsrl_wv, 0 },
-+    { "vnsrl.wx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, rv_op_vnsrl_wx, rv_op_vnsrl_wx, 0 },
-+    { "vnsrl.wi", rv_codec_v_i, rv_fmt_vd_vs2_uimm_vm, NULL, rv_op_vnsrl_wi, rv_op_vnsrl_wi, 0 },
-+    { "vnsra.wv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vnsra_wv, rv_op_vnsra_wv, 0 },
-+    { "vnsra.wx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, rv_op_vnsra_wx, rv_op_vnsra_wx, 0 },
-+    { "vnsra.wi", rv_codec_v_i, rv_fmt_vd_vs2_uimm_vm, NULL, rv_op_vnsra_wi, rv_op_vnsra_wi, 0 },
-+    { "vmseq.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vmseq_vv, rv_op_vmseq_vv, 0 },
-+    { "vmseq.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, rv_op_vmseq_vx, rv_op_vmseq_vx, 0 },
-+    { "vmseq.vi", rv_codec_v_i, rv_fmt_vd_vs2_imm_vm, NULL, rv_op_vmseq_vi, rv_op_vmseq_vi, 0 },
-+    { "vmsne.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vmsne_vv, rv_op_vmsne_vv, 0 },
-+    { "vmsne.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, rv_op_vmsne_vx, rv_op_vmsne_vx, 0 },
-+    { "vmsne.vi", rv_codec_v_i, rv_fmt_vd_vs2_imm_vm, NULL, rv_op_vmsne_vi, rv_op_vmsne_vi, 0 },
-+    { "vmsltu.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vmsltu_vv, rv_op_vmsltu_vv, 0 },
-+    { "vmsltu.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, rv_op_vmsltu_vx, rv_op_vmsltu_vx, 0 },
-+    { "vmslt.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vmslt_vv, rv_op_vmslt_vv, 0 },
-+    { "vmslt.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, rv_op_vmslt_vx, rv_op_vmslt_vx, 0 },
-+    { "vmsleu.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vmsleu_vv, rv_op_vmsleu_vv, 0 },
-+    { "vmsleu.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, rv_op_vmsleu_vx, rv_op_vmsleu_vx, 0 },
-+    { "vmsleu.vi", rv_codec_v_i, rv_fmt_vd_vs2_imm_vm, NULL, rv_op_vmsleu_vi, rv_op_vmsleu_vi, 0 },
-+    { "vmsle.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vmsle_vv, rv_op_vmsle_vv, 0 },
-+    { "vmsle.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, rv_op_vmsle_vx, rv_op_vmsle_vx, 0 },
-+    { "vmsle.vi", rv_codec_v_i, rv_fmt_vd_vs2_imm_vm, NULL, rv_op_vmsle_vi, rv_op_vmsle_vi, 0 },
-+    { "vmsgtu.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, rv_op_vmsgtu_vx, rv_op_vmsgtu_vx, 0 },
-+    { "vmsgtu.vi", rv_codec_v_i, rv_fmt_vd_vs2_imm_vm, NULL, rv_op_vmsgtu_vi, rv_op_vmsgtu_vi, 0 },
-+    { "vmsgt.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, rv_op_vmsgt_vx, rv_op_vmsgt_vx, 0 },
-+    { "vmsgt.vi", rv_codec_v_i, rv_fmt_vd_vs2_imm_vm, NULL, rv_op_vmsgt_vi, rv_op_vmsgt_vi, 0 },
-+    { "vminu.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vminu_vv, rv_op_vminu_vv, 0 },
-+    { "vminu.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, rv_op_vminu_vx, rv_op_vminu_vx, 0 },
-+    { "vmin.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vmin_vv, rv_op_vmin_vv, 0 },
-+    { "vmin.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, rv_op_vmin_vx, rv_op_vmin_vx, 0 },
-+    { "vmaxu.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vmaxu_vv, rv_op_vmaxu_vv, 0 },
-+    { "vmaxu.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, rv_op_vmaxu_vx, rv_op_vmaxu_vx, 0 },
-+    { "vmax.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vmax_vv, rv_op_vmax_vv, 0 },
-+    { "vmax.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, rv_op_vmax_vx, rv_op_vmax_vx, 0 },
-+    { "vmul.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vmul_vv, rv_op_vmul_vv, 0 },
-+    { "vmul.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, rv_op_vmul_vx, rv_op_vmul_vx, 0 },
-+    { "vmulh.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vmulh_vv, rv_op_vmulh_vv, 0 },
-+    { "vmulh.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, rv_op_vmulh_vx, rv_op_vmulh_vx, 0 },
-+    { "vmulhu.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vmulhu_vv, rv_op_vmulhu_vv, 0 },
-+    { "vmulhu.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, rv_op_vmulhu_vx, rv_op_vmulhu_vx, 0 },
-+    { "vmulhsu.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vmulhsu_vv, rv_op_vmulhsu_vv, 0 },
-+    { "vmulhsu.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, rv_op_vmulhsu_vx, rv_op_vmulhsu_vx, 0 },
-+    { "vdivu.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vdivu_vv, rv_op_vdivu_vv, 0 },
-+    { "vdivu.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, rv_op_vdivu_vx, rv_op_vdivu_vx, 0 },
-+    { "vdiv.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vdiv_vv, rv_op_vdiv_vv, 0 },
-+    { "vdiv.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, rv_op_vdiv_vx, rv_op_vdiv_vx, 0 },
-+    { "vremu.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vremu_vv, rv_op_vremu_vv, 0 },
-+    { "vremu.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, rv_op_vremu_vx, rv_op_vremu_vx, 0 },
-+    { "vrem.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vrem_vv, rv_op_vrem_vv, 0 },
-+    { "vrem.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, rv_op_vrem_vx, rv_op_vrem_vx, 0 },
-+    { "vwmulu.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vwmulu_vv, rv_op_vwmulu_vv, 0 },
-+    { "vwmulu.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, rv_op_vwmulu_vx, rv_op_vwmulu_vx, 0 },
-+    { "vwmulsu.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vwmulsu_vv, rv_op_vwmulsu_vv, 0 },
-+    { "vwmulsu.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, rv_op_vwmulsu_vx, rv_op_vwmulsu_vx, 0 },
-+    { "vwmul.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vwmul_vv, rv_op_vwmul_vv, 0 },
-+    { "vwmul.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, rv_op_vwmul_vx, rv_op_vwmul_vx, 0 },
-+    { "vmacc.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm, NULL, rv_op_vmacc_vv, rv_op_vmacc_vv, 0 },
-+    { "vmacc.vx", rv_codec_v_r, rv_fmt_vd_rs1_vs2_vm, NULL, rv_op_vmacc_vx, rv_op_vmacc_vx, 0 },
-+    { "vnmsac.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm, NULL, rv_op_vnmsac_vv, rv_op_vnmsac_vv, 0 },
-+    { "vnmsac.vx", rv_codec_v_r, rv_fmt_vd_rs1_vs2_vm, NULL, rv_op_vnmsac_vx, rv_op_vnmsac_vx, 0 },
-+    { "vmadd.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm, NULL, rv_op_vmadd_vv, rv_op_vmadd_vv, 0 },
-+    { "vmadd.vx", rv_codec_v_r, rv_fmt_vd_rs1_vs2_vm, NULL, rv_op_vmadd_vx, rv_op_vmadd_vx, 0 },
-+    { "vnmsub.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm, NULL, rv_op_vnmsub_vv, rv_op_vnmsub_vv, 0 },
-+    { "vnmsub.vx", rv_codec_v_r, rv_fmt_vd_rs1_vs2_vm, NULL, rv_op_vnmsub_vx, rv_op_vnmsub_vx, 0 },
-+    { "vwmaccu.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm, NULL, rv_op_vwmaccu_vv, rv_op_vwmaccu_vv, 0 },
-+    { "vwmaccu.vx", rv_codec_v_r, rv_fmt_vd_rs1_vs2_vm, NULL, rv_op_vwmaccu_vx, rv_op_vwmaccu_vx, 0 },
-+    { "vwmacc.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm, NULL, rv_op_vwmacc_vv, rv_op_vwmacc_vv, 0 },
-+    { "vwmacc.vx", rv_codec_v_r, rv_fmt_vd_rs1_vs2_vm, NULL, rv_op_vwmacc_vx, rv_op_vwmacc_vx, 0 },
-+    { "vwmaccsu.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm, NULL, rv_op_vwmaccsu_vv, rv_op_vwmaccsu_vv, 0 },
-+    { "vwmaccsu.vx", rv_codec_v_r, rv_fmt_vd_rs1_vs2_vm, NULL, rv_op_vwmaccsu_vx, rv_op_vwmaccsu_vx, 0 },
-+    { "vwmaccus.vx", rv_codec_v_r, rv_fmt_vd_rs1_vs2_vm, NULL, rv_op_vwmaccus_vx, rv_op_vwmaccus_vx, 0 },
-+    { "vmv.v.v", rv_codec_v_r, rv_fmt_vd_vs1, NULL, rv_op_vmv_v_v, rv_op_vmv_v_v, 0 },
-+    { "vmv.v.x", rv_codec_v_r, rv_fmt_vd_rs1, NULL, rv_op_vmv_v_x, rv_op_vmv_v_x, 0 },
-+    { "vmv.v.i", rv_codec_v_i, rv_fmt_vd_imm, NULL, rv_op_vmv_v_i, rv_op_vmv_v_i, 0 },
-+    { "vmerge.vvm", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vl, NULL, rv_op_vmerge_vvm, rv_op_vmerge_vvm, 0 },
-+    { "vmerge.vxm", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vl, NULL, rv_op_vmerge_vxm, rv_op_vmerge_vxm, 0 },
-+    { "vmerge.vim", rv_codec_v_i, rv_fmt_vd_vs2_imm_vl, NULL, rv_op_vmerge_vim, rv_op_vmerge_vim, 0 },
-+    { "vsaddu.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vsaddu_vv, rv_op_vsaddu_vv, 0 },
-+    { "vsaddu.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, rv_op_vsaddu_vx, rv_op_vsaddu_vx, 0 },
-+    { "vsaddu.vi", rv_codec_v_i, rv_fmt_vd_vs2_imm_vm, NULL, rv_op_vsaddu_vi, rv_op_vsaddu_vi, 0 },
-+    { "vsadd.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vsadd_vv, rv_op_vsadd_vv, 0 },
-+    { "vsadd.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, rv_op_vsadd_vx, rv_op_vsadd_vx, 0 },
-+    { "vsadd.vi", rv_codec_v_i, rv_fmt_vd_vs2_imm_vm, NULL, rv_op_vsadd_vi, rv_op_vsadd_vi, 0 },
-+    { "vssubu.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vssubu_vv, rv_op_vssubu_vv, 0 },
-+    { "vssubu.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, rv_op_vssubu_vx, rv_op_vssubu_vx, 0 },
-+    { "vssub.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vssub_vv, rv_op_vssub_vv, 0 },
-+    { "vssub.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, rv_op_vssub_vx, rv_op_vssub_vx, 0 },
-+    { "vaadd.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vaadd_vv, rv_op_vaadd_vv, 0 },
-+    { "vaadd.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, rv_op_vaadd_vx, rv_op_vaadd_vx, 0 },
-+    { "vaaddu.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vaaddu_vv, rv_op_vaaddu_vv, 0 },
-+    { "vaaddu.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, rv_op_vaaddu_vx, rv_op_vaaddu_vx, 0 },
-+    { "vasub.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vasub_vv, rv_op_vasub_vv, 0 },
-+    { "vasub.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, rv_op_vasub_vx, rv_op_vasub_vx, 0 },
-+    { "vasubu.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vasubu_vv, rv_op_vasubu_vv, 0 },
-+    { "vasubu.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, rv_op_vasubu_vx, rv_op_vasubu_vx, 0 },
-+    { "vsmul.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vsmul_vv, rv_op_vsmul_vv, 0 },
-+    { "vsmul.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, rv_op_vsmul_vx, rv_op_vsmul_vx, 0 },
-+    { "vssrl.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vssrl_vv, rv_op_vssrl_vv, 0 },
-+    { "vssrl.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, rv_op_vssrl_vx, rv_op_vssrl_vx, 0 },
-+    { "vssrl.vi", rv_codec_v_i, rv_fmt_vd_vs2_uimm_vm, NULL, rv_op_vssrl_vi, rv_op_vssrl_vi, 0 },
-+    { "vssra.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vssra_vv, rv_op_vssra_vv, 0 },
-+    { "vssra.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, rv_op_vssra_vx, rv_op_vssra_vx, 0 },
-+    { "vssra.vi", rv_codec_v_i, rv_fmt_vd_vs2_uimm_vm, NULL, rv_op_vssra_vi, rv_op_vssra_vi, 0 },
-+    { "vnclipu.wv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vnclipu_wv, rv_op_vnclipu_wv, 0 },
-+    { "vnclipu.wx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, rv_op_vnclipu_wx, rv_op_vnclipu_wx, 0 },
-+    { "vnclipu.wi", rv_codec_v_i, rv_fmt_vd_vs2_uimm_vm, NULL, rv_op_vnclipu_wi, rv_op_vnclipu_wi, 0 },
-+    { "vnclip.wv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vnclip_wv, rv_op_vnclip_wv, 0 },
-+    { "vnclip.wx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, rv_op_vnclip_wx, rv_op_vnclip_wx, 0 },
-+    { "vnclip.wi", rv_codec_v_i, rv_fmt_vd_vs2_uimm_vm, NULL, rv_op_vnclip_wi, rv_op_vnclip_wi, 0 },
-+    { "vfadd.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vfadd_vv, rv_op_vfadd_vv, 0 },
-+    { "vfadd.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm, NULL, rv_op_vfadd_vf, rv_op_vfadd_vf, 0 },
-+    { "vfsub.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vfsub_vv, rv_op_vfsub_vv, 0 },
-+    { "vfsub.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm, NULL, rv_op_vfsub_vf, rv_op_vfsub_vf, 0 },
-+    { "vfrsub.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm, NULL, rv_op_vfrsub_vf, rv_op_vfrsub_vf, 0 },
-+    { "vfwadd.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vfwadd_vv, rv_op_vfwadd_vv, 0 },
-+    { "vfwadd.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm, NULL, rv_op_vfwadd_vf, rv_op_vfwadd_vf, 0 },
-+    { "vfwadd.wv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vfwadd_wv, rv_op_vfwadd_wv, 0 },
-+    { "vfwadd.wf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm, NULL, rv_op_vfwadd_wf, rv_op_vfwadd_wf, 0 },
-+    { "vfwsub.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vfwsub_vv, rv_op_vfwsub_vv, 0 },
-+    { "vfwsub.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm, NULL, rv_op_vfwsub_vf, rv_op_vfwsub_vf, 0 },
-+    { "vfwsub.wv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vfwsub_wv, rv_op_vfwsub_wv, 0 },
-+    { "vfwsub.wf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm, NULL, rv_op_vfwsub_wf, rv_op_vfwsub_wf, 0 },
-+    { "vfmul.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vfmul_vv, rv_op_vfmul_vv, 0 },
-+    { "vfmul.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm, NULL, rv_op_vfmul_vf, rv_op_vfmul_vf, 0 },
-+    { "vfdiv.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vfdiv_vv, rv_op_vfdiv_vv, 0 },
-+    { "vfdiv.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm, NULL, rv_op_vfdiv_vf, rv_op_vfdiv_vf, 0 },
-+    { "vfrdiv.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm, NULL, rv_op_vfrdiv_vf, rv_op_vfrdiv_vf, 0 },
-+    { "vfwmul.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vfwmul_vv, rv_op_vfwmul_vv, 0 },
-+    { "vfwmul.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm, NULL, rv_op_vfwmul_vf, rv_op_vfwmul_vf, 0 },
-+    { "vfmacc.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm, NULL, rv_op_vfmacc_vv, rv_op_vfmacc_vv, 0 },
-+    { "vfmacc.vf", rv_codec_v_r, rv_fmt_vd_fs1_vs2_vm, NULL, rv_op_vfmacc_vf, rv_op_vfmacc_vf, 0 },
-+    { "vfnmacc.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm, NULL, rv_op_vfnmacc_vv, rv_op_vfnmacc_vv, 0 },
-+    { "vfnmacc.vf", rv_codec_v_r, rv_fmt_vd_fs1_vs2_vm, NULL, rv_op_vfnmacc_vf, rv_op_vfnmacc_vf, 0 },
-+    { "vfmsac.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm, NULL, rv_op_vfmsac_vv, rv_op_vfmsac_vv, 0 },
-+    { "vfmsac.vf", rv_codec_v_r, rv_fmt_vd_fs1_vs2_vm, NULL, rv_op_vfmsac_vf, rv_op_vfmsac_vf, 0 },
-+    { "vfnmsac.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm, NULL, rv_op_vfnmsac_vv, rv_op_vfnmsac_vv, 0 },
-+    { "vfnmsac.vf", rv_codec_v_r, rv_fmt_vd_fs1_vs2_vm, NULL, rv_op_vfnmsac_vf, rv_op_vfnmsac_vf, 0 },
-+    { "vfmadd.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm, NULL, rv_op_vfmadd_vv, rv_op_vfmadd_vv, 0 },
-+    { "vfmadd.vf", rv_codec_v_r, rv_fmt_vd_fs1_vs2_vm, NULL, rv_op_vfmadd_vf, rv_op_vfmadd_vf, 0 },
-+    { "vfnmadd.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm, NULL, rv_op_vfnmadd_vv, rv_op_vfnmadd_vv, 0 },
-+    { "vfnmadd.vf", rv_codec_v_r, rv_fmt_vd_fs1_vs2_vm, NULL, rv_op_vfnmadd_vf, rv_op_vfnmadd_vf, 0 },
-+    { "vfmsub.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm, NULL, rv_op_vfmsub_vv, rv_op_vfmsub_vv, 0 },
-+    { "vfmsub.vf", rv_codec_v_r, rv_fmt_vd_fs1_vs2_vm, NULL, rv_op_vfmsub_vf, rv_op_vfmsub_vf, 0 },
-+    { "vfnmsub.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm, NULL, rv_op_vfnmsub_vv, rv_op_vfnmsub_vv, 0 },
-+    { "vfnmsub.vf", rv_codec_v_r, rv_fmt_vd_fs1_vs2_vm, NULL, rv_op_vfnmsub_vf, rv_op_vfnmsub_vf, 0 },
-+    { "vfwmacc.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm, NULL, rv_op_vfwmacc_vv, rv_op_vfwmacc_vv, 0 },
-+    { "vfwmacc.vf", rv_codec_v_r, rv_fmt_vd_fs1_vs2_vm, NULL, rv_op_vfwmacc_vf, rv_op_vfwmacc_vf, 0 },
-+    { "vfwnmacc.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm, NULL, rv_op_vfwnmacc_vv, rv_op_vfwnmacc_vv, 0 },
-+    { "vfwnmacc.vf", rv_codec_v_r, rv_fmt_vd_fs1_vs2_vm, NULL, rv_op_vfwnmacc_vf, rv_op_vfwnmacc_vf, 0 },
-+    { "vfwmsac.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm, NULL, rv_op_vfwmsac_vv, rv_op_vfwmsac_vv, 0 },
-+    { "vfwmsac.vf", rv_codec_v_r, rv_fmt_vd_fs1_vs2_vm, NULL, rv_op_vfwmsac_vf, rv_op_vfwmsac_vf, 0 },
-+    { "vfwnmsac.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm, NULL, rv_op_vfwnmsac_vv, rv_op_vfwnmsac_vv, 0 },
-+    { "vfwnmsac.vf", rv_codec_v_r, rv_fmt_vd_fs1_vs2_vm, NULL, rv_op_vfwnmsac_vf, rv_op_vfwnmsac_vf, 0 },
-+    { "vfsqrt.v", rv_codec_v_r, rv_fmt_vd_vs2, NULL, rv_op_vfsqrt_v, rv_op_vfsqrt_v, 0 },
-+    { "vfrsqrt7.v", rv_codec_v_r, rv_fmt_vd_vs2, NULL, rv_op_vfrsqrt7_v, rv_op_vfrsqrt7_v, 0 },
-+    { "vfrec7.v", rv_codec_v_r, rv_fmt_vd_vs2, NULL, rv_op_vfrec7_v, rv_op_vfrec7_v, 0 },
-+    { "vfmin.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vfmin_vv, rv_op_vfmin_vv, 0 },
-+    { "vfmin.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm, NULL, rv_op_vfmin_vf, rv_op_vfmin_vf, 0 },
-+    { "vfmax.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vfmax_vv, rv_op_vfmax_vv, 0 },
-+    { "vfmax.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm, NULL, rv_op_vfmax_vf, rv_op_vfmax_vf, 0 },
-+    { "vfsgnj.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vfsgnj_vv, rv_op_vfsgnj_vv, 0 },
-+    { "vfsgnj.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm, NULL, rv_op_vfsgnj_vf, rv_op_vfsgnj_vf, 0 },
-+    { "vfsgnjn.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vfsgnjn_vv, rv_op_vfsgnjn_vv, 0 },
-+    { "vfsgnjn.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm, NULL, rv_op_vfsgnjn_vf, rv_op_vfsgnjn_vf, 0 },
-+    { "vfsgnjx.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vfsgnjx_vv, rv_op_vfsgnjx_vv, 0 },
-+    { "vfsgnjx.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm, NULL, rv_op_vfsgnjx_vf, rv_op_vfsgnjx_vf, 0 },
-+    { "vfslide1up.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm, NULL, rv_op_vfslide1up_vf, rv_op_vfslide1up_vf, 0 },
-+    { "vfslide1down.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm, NULL, rv_op_vfslide1down_vf, rv_op_vfslide1down_vf, 0 },
-+    { "vmfeq.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vmfeq_vv, rv_op_vmfeq_vv, 0 },
-+    { "vmfeq.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm, NULL, rv_op_vmfeq_vf, rv_op_vmfeq_vf, 0 },
-+    { "vmfne.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vmfne_vv, rv_op_vmfne_vv, 0 },
-+    { "vmfne.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm, NULL, rv_op_vmfne_vf, rv_op_vmfne_vf, 0 },
-+    { "vmflt.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vmflt_vv, rv_op_vmflt_vv, 0 },
-+    { "vmflt.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm, NULL, rv_op_vmflt_vf, rv_op_vmflt_vf, 0 },
-+    { "vmfle.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vmfle_vv, rv_op_vmfle_vv, 0 },
-+    { "vmfle.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm, NULL, rv_op_vmfle_vf, rv_op_vmfle_vf, 0 },
-+    { "vmfgt.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm, NULL, rv_op_vmfgt_vf, rv_op_vmfgt_vf, 0 },
-+    { "vmfge.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm, NULL, rv_op_vmfge_vf, rv_op_vmfge_vf, 0 },
-+    { "vfclass.v", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, rv_op_vfclass_v, rv_op_vfclass_v, 0 },
-+    { "vfmerge.vfm", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vl, NULL, rv_op_vfmerge_vfm, rv_op_vfmerge_vfm, 0 },
-+    { "vfmv.v.f", rv_codec_v_r, rv_fmt_vd_fs1, NULL, rv_op_vfmv_v_f, rv_op_vfmv_v_f, 0 },
-+    { "vfcvt.xu.f.v", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, rv_op_vfcvt_xu_f_v, rv_op_vfcvt_xu_f_v, 0 },
-+    { "vfcvt.x.f.v", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, rv_op_vfcvt_x_f_v, rv_op_vfcvt_x_f_v, 0 },
-+    { "vfcvt.f.xu.v", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, rv_op_vfcvt_f_xu_v, rv_op_vfcvt_f_xu_v, 0 },
-+    { "vfcvt.f.x.v", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, rv_op_vfcvt_f_x_v, rv_op_vfcvt_f_x_v, 0 },
-+    { "vfcvt.rtz.xu.f.v", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, rv_op_vfcvt_rtz_xu_f_v, rv_op_vfcvt_rtz_xu_f_v, 0 },
-+    { "vfcvt.rtz.x.f.v", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, rv_op_vfcvt_rtz_x_f_v, rv_op_vfcvt_rtz_x_f_v, 0 },
-+    { "vfwcvt.xu.f.v", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, rv_op_vfwcvt_xu_f_v, rv_op_vfwcvt_xu_f_v, 0 },
-+    { "vfwcvt.x.f.v", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, rv_op_vfwcvt_x_f_v, rv_op_vfwcvt_x_f_v, 0 },
-+    { "vfwcvt.f.xu.v", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, rv_op_vfwcvt_f_xu_v, rv_op_vfwcvt_f_xu_v, 0 },
-+    { "vfwcvt.f.x.v", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, rv_op_vfwcvt_f_x_v, rv_op_vfwcvt_f_x_v, 0 },
-+    { "vfwcvt.f.f.v", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, rv_op_vfwcvt_f_f_v, rv_op_vfwcvt_f_f_v, 0 },
-+    { "vfwcvt.rtz.xu.f.v", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, rv_op_vfwcvt_rtz_xu_f_v, rv_op_vfwcvt_rtz_xu_f_v, 0 },
-+    { "vfwcvt.rtz.x.f.v", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, rv_op_vfwcvt_rtz_x_f_v, rv_op_vfwcvt_rtz_x_f_v, 0 },
-+    { "vfncvt.xu.f.w", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, rv_op_vfncvt_xu_f_w, rv_op_vfncvt_xu_f_w, 0 },
-+    { "vfncvt.x.f.w", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, rv_op_vfncvt_x_f_w, rv_op_vfncvt_x_f_w, 0 },
-+    { "vfncvt.f.xu.w", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, rv_op_vfncvt_f_xu_w, rv_op_vfncvt_f_xu_w, 0 },
-+    { "vfncvt.f.x.w", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, rv_op_vfncvt_f_x_w, rv_op_vfncvt_f_x_w, 0 },
-+    { "vfncvt.f.f.w", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, rv_op_vfncvt_f_f_w, rv_op_vfncvt_f_f_w, 0 },
-+    { "vfncvt.rod.f.f.w", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, rv_op_vfncvt_rod_f_f_w, rv_op_vfncvt_rod_f_f_w, 0 },
-+    { "vfncvt.rtz.xu.f.w", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, rv_op_vfncvt_rtz_xu_f_w, rv_op_vfncvt_rtz_xu_f_w, 0 },
-+    { "vfncvt.rtz.x.f.w", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, rv_op_vfncvt_rtz_x_f_w, rv_op_vfncvt_rtz_x_f_w, 0 },
-+    { "vredsum.vs", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vredsum_vs, rv_op_vredsum_vs, 0 },
-+    { "vredand.vs", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vredand_vs, rv_op_vredand_vs, 0 },
-+    { "vredor.vs", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vredor_vs, rv_op_vredor_vs, 0 },
-+    { "vredxor.vs", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vredxor_vs, rv_op_vredxor_vs, 0 },
-+    { "vredminu.vs", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vredminu_vs, rv_op_vredminu_vs, 0 },
-+    { "vredmin.vs", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vredmin_vs, rv_op_vredmin_vs, 0 },
-+    { "vredmaxu.vs", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vredmaxu_vs, rv_op_vredmaxu_vs, 0 },
-+    { "vredmax.vs", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vredmax_vs, rv_op_vredmax_vs, 0 },
-+    { "vwredsumu.vs", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vwredsumu_vs, rv_op_vwredsumu_vs, 0 },
-+    { "vwredsum.vs", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vwredsum_vs, rv_op_vwredsum_vs, 0 },
-+    { "vfredusum.vs", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vfredusum_vs, rv_op_vfredusum_vs, 0 },
-+    { "vfredosum.vs", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vfredosum_vs, rv_op_vfredosum_vs, 0 },
-+    { "vfredmin.vs", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vfredmin_vs, rv_op_vfredmin_vs, 0 },
-+    { "vfredmax.vs", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vfredmax_vs, rv_op_vfredmax_vs, 0 },
-+    { "vfwredusum.vs", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vfwredusum_vs, rv_op_vfwredusum_vs, 0 },
-+    { "vfwredosum.vs", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vfwredosum_vs, rv_op_vfwredosum_vs, 0 },
-+    { "vmand.mm", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vmand_mm, rv_op_vmand_mm, 0 },
-+    { "vmnand.mm", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vmnand_mm, rv_op_vmnand_mm, 0 },
-+    { "vmandn.mm", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vmandn_mm, rv_op_vmandn_mm, 0 },
-+    { "vmxor.mm", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vmxor_mm, rv_op_vmxor_mm, 0 },
-+    { "vmor.mm", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vmor_mm, rv_op_vmor_mm, 0 },
-+    { "vmnor.mm", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vmnor_mm, rv_op_vmnor_mm, 0 },
-+    { "vmorn.mm", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vmorn_mm, rv_op_vmorn_mm, 0 },
-+    { "vmxnor.mm", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vmxnor_mm, rv_op_vmxnor_mm, 0 },
-+    { "vcpop.m", rv_codec_v_r, rv_fmt_rd_vs2_vm, NULL, rv_op_vcpop_m, rv_op_vcpop_m, 0 },
-+    { "vfirst.m", rv_codec_v_r, rv_fmt_rd_vs2_vm, NULL, rv_op_vfirst_m, rv_op_vfirst_m, 0 },
-+    { "vmsbf.m", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, rv_op_vmsbf_m, rv_op_vmsbf_m, 0 },
-+    { "vmsif.m", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, rv_op_vmsif_m, rv_op_vmsif_m, 0 },
-+    { "vmsof.m", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, rv_op_vmsof_m, rv_op_vmsof_m, 0 },
-+    { "viota.m", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, rv_op_viota_m, rv_op_viota_m, 0 },
-+    { "vid.v", rv_codec_v_r, rv_fmt_vd_vm, NULL, rv_op_vid_v, rv_op_vid_v, 0 },
-+    { "vmv.x.s", rv_codec_v_r, rv_fmt_rd_vs2, NULL, rv_op_vmv_x_s, rv_op_vmv_x_s, 0 },
-+    { "vmv.s.x", rv_codec_v_r, rv_fmt_vd_rs1, NULL, rv_op_vmv_s_x, rv_op_vmv_s_x, 0 },
-+    { "vfmv.f.s", rv_codec_v_r, rv_fmt_fd_vs2, NULL, rv_op_vfmv_f_s, rv_op_vfmv_f_s, 0 },
-+    { "vfmv.s.f", rv_codec_v_r, rv_fmt_vd_fs1, NULL, rv_op_vfmv_s_f, rv_op_vfmv_s_f, 0 },
-+    { "vslideup.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, rv_op_vslideup_vx, rv_op_vslideup_vx, 0 },
-+    { "vslideup.vi", rv_codec_v_i, rv_fmt_vd_vs2_uimm_vm, NULL, rv_op_vslideup_vi, rv_op_vslideup_vi, 0 },
-+    { "vslide1up.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, rv_op_vslide1up_vx, rv_op_vslide1up_vx, 0 },
-+    { "vslidedown.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, rv_op_vslidedown_vx, rv_op_vslidedown_vx, 0 },
-+    { "vslidedown.vi", rv_codec_v_i, rv_fmt_vd_vs2_uimm_vm, NULL, rv_op_vslidedown_vi, rv_op_vslidedown_vi, 0 },
-+    { "vslide1down.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, rv_op_vslide1down_vx, rv_op_vslide1down_vx, 0 },
-+    { "vrgather.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vrgather_vv, rv_op_vrgather_vv, 0 },
-+    { "vrgatherei16.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vrgatherei16_vv, rv_op_vrgatherei16_vv, 0 },
-+    { "vrgather.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, rv_op_vrgather_vx, rv_op_vrgather_vx, 0 },
-+    { "vrgather.vi", rv_codec_v_i, rv_fmt_vd_vs2_uimm_vm, NULL, rv_op_vrgather_vi, rv_op_vrgather_vi, 0 },
-+    { "vcompress.vm", rv_codec_v_r, rv_fmt_vd_vs2_vs1, NULL, rv_op_vcompress_vm, rv_op_vcompress_vm, 0 },
-+    { "vmv1r.v", rv_codec_v_r, rv_fmt_vd_vs2, NULL, rv_op_vmv1r_v, rv_op_vmv1r_v, 0 },
-+    { "vmv2r.v", rv_codec_v_r, rv_fmt_vd_vs2, NULL, rv_op_vmv2r_v, rv_op_vmv2r_v, 0 },
-+    { "vmv4r.v", rv_codec_v_r, rv_fmt_vd_vs2, NULL, rv_op_vmv4r_v, rv_op_vmv4r_v, 0 },
-+    { "vmv8r.v", rv_codec_v_r, rv_fmt_vd_vs2, NULL, rv_op_vmv8r_v, rv_op_vmv8r_v, 0 },
-+    { "vzext.vf2", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, rv_op_vzext_vf2, rv_op_vzext_vf2, 0 },
-+    { "vzext.vf4", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, rv_op_vzext_vf4, rv_op_vzext_vf4, 0 },
-+    { "vzext.vf8", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, rv_op_vzext_vf8, rv_op_vzext_vf8, 0 },
-+    { "vsext.vf2", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, rv_op_vsext_vf2, rv_op_vsext_vf2, 0 },
-+    { "vsext.vf4", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, rv_op_vsext_vf4, rv_op_vsext_vf4, 0 },
-+    { "vsext.vf8", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, rv_op_vsext_vf8, rv_op_vsext_vf8, 0 },
-+    { "vsetvli", rv_codec_vsetvli, rv_fmt_vsetvli, NULL, rv_op_vsetvli, rv_op_vsetvli, 0 },
-+    { "vsetivli", rv_codec_vsetivli, rv_fmt_vsetivli, NULL, rv_op_vsetivli, rv_op_vsetivli, 0 },
-+    { "vsetvl", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, rv_op_vsetvl, rv_op_vsetvl, 0 }
- };
- /* CSR names */
 @@ -XXX,XX +XXX,XX @@ static const char *csr_name(int csrno)
-     case 0x0003: return "fcsr";
+     case 0x0383: return "mibound";
-     case 0x0004: return "uie";
+     case 0x0384: return "mdbase";
-     case 0x0005: return "utvec";
+     case 0x0385: return "mdbound";
-+    case 0x0008: return "vstart";
+-    case 0x03a0: return "pmpcfg3";
-+    case 0x0009: return "vxsat";
++    case 0x03a0: return "pmpcfg0";
-+    case 0x000a: return "vxrm";
++    case 0x03a1: return "pmpcfg1";
-+    case 0x000f: return "vcsr";
++    case 0x03a2: return "pmpcfg2";
-     case 0x0015: return "seed";
++    case 0x03a3: return "pmpcfg3";
-     case 0x0040: return "uscratch";
++    case 0x03a4: return "pmpcfg4";
-     case 0x0041: return "uepc";
++    case 0x03a5: return "pmpcfg5";
 +    case 0x03a6: return "pmpcfg6";
 +    case 0x03a7: return "pmpcfg7";
 +    case 0x03a8: return "pmpcfg8";
 +    case 0x03a9: return "pmpcfg9";
 +    case 0x03aa: return "pmpcfg10";
 +    case 0x03ab: return "pmpcfg11";
 +    case 0x03ac: return "pmpcfg12";
 +    case 0x03ad: return "pmpcfg13";
 +    case 0x03ae: return "pmpcfg14";
 +    case 0x03af: return "pmpcfg15";
      case 0x03b0: return "pmpaddr0";
      case 0x03b1: return "pmpaddr1";
      case 0x03b2: return "pmpaddr2";
 @@ -XXX,XX +XXX,XX @@ static const char *csr_name(int csrno)
-     case 0x0c00: return "cycle";
+     case 0x03bd: return "pmpaddr13";
-     case 0x0c01: return "time";
+     case 0x03be: return "pmpaddr14";
-     case 0x0c02: return "instret";
+     case 0x03bf: return "pmpaddr15";
-+    case 0x0c20: return "vl";
++    case 0x03c0: return "pmpaddr16";
-+    case 0x0c21: return "vtype";
++    case 0x03c1: return "pmpaddr17";
-+    case 0x0c22: return "vlenb";
++    case 0x03c2: return "pmpaddr18";
-     case 0x0c80: return "cycleh";
++    case 0x03c3: return "pmpaddr19";
-     case 0x0c81: return "timeh";
++    case 0x03c4: return "pmpaddr20";
-     case 0x0c82: return "instreth";
++    case 0x03c5: return "pmpaddr21";
-@@ -XXX,XX +XXX,XX @@ static void decode_inst_opcode(rv_decode *dec, rv_isa isa)
++    case 0x03c6: return "pmpaddr22";
-             break;
++    case 0x03c7: return "pmpaddr23";
-         case 1:
++    case 0x03c8: return "pmpaddr24";
-             switch (((inst >> 12) & 0b111)) {
++    case 0x03c9: return "pmpaddr25";
-+            case 0:
++    case 0x03ca: return "pmpaddr26";
-+                switch (((inst >> 20) & 0b111111111111)) {
++    case 0x03cb: return "pmpaddr27";
-+                case 40: op = rv_op_vl1re8_v; break;
++    case 0x03cc: return "pmpaddr28";
-+                case 552: op = rv_op_vl2re8_v; break;
++    case 0x03cd: return "pmpaddr29";
-+                case 1576: op = rv_op_vl4re8_v; break;
++    case 0x03ce: return "pmpaddr30";
-+                case 3624: op = rv_op_vl8re8_v; break;
++    case 0x03cf: return "pmpaddr31";
-+                }
++    case 0x03d0: return "pmpaddr32";
-+                switch (((inst >> 26) & 0b111)) {
++    case 0x03d1: return "pmpaddr33";
-+                case 0:
++    case 0x03d2: return "pmpaddr34";
-+                    switch (((inst >> 20) & 0b11111)) {
++    case 0x03d3: return "pmpaddr35";
-+                    case 0: op = rv_op_vle8_v; break;
++    case 0x03d4: return "pmpaddr36";
-+                    case 11: op = rv_op_vlm_v; break;
++    case 0x03d5: return "pmpaddr37";
-+                    case 16: op = rv_op_vle8ff_v; break;
++    case 0x03d6: return "pmpaddr38";
-+                    }
++    case 0x03d7: return "pmpaddr39";
-+                    break;
++    case 0x03d8: return "pmpaddr40";
-+                case 1: op = rv_op_vluxei8_v; break;
++    case 0x03d9: return "pmpaddr41";
-+                case 2: op = rv_op_vlse8_v; break;
++    case 0x03da: return "pmpaddr42";
-+                case 3: op = rv_op_vloxei8_v; break;
++    case 0x03db: return "pmpaddr43";
-+                }
++    case 0x03dc: return "pmpaddr44";
-+                break;
++    case 0x03dd: return "pmpaddr45";
-             case 2: op = rv_op_flw; break;
++    case 0x03de: return "pmpaddr46";
-             case 3: op = rv_op_fld; break;
++    case 0x03df: return "pmpaddr47";
-             case 4: op = rv_op_flq; break;
++    case 0x03e0: return "pmpaddr48";
-+            case 5:
++    case 0x03e1: return "pmpaddr49";
-+                switch (((inst >> 20) & 0b111111111111)) {
++    case 0x03e2: return "pmpaddr50";
-+                case 40: op = rv_op_vl1re16_v; break;
++    case 0x03e3: return "pmpaddr51";
-+                case 552: op = rv_op_vl2re16_v; break;
++    case 0x03e4: return "pmpaddr52";
-+                case 1576: op = rv_op_vl4re16_v; break;
++    case 0x03e5: return "pmpaddr53";
-+                case 3624: op = rv_op_vl8re16_v; break;
++    case 0x03e6: return "pmpaddr54";
-+                }
++    case 0x03e7: return "pmpaddr55";
-+                switch (((inst >> 26) & 0b111)) {
++    case 0x03e8: return "pmpaddr56";
-+                case 0:
++    case 0x03e9: return "pmpaddr57";
-+                    switch (((inst >> 20) & 0b11111)) {
++    case 0x03ea: return "pmpaddr58";
-+                    case 0: op = rv_op_vle16_v; break;
++    case 0x03eb: return "pmpaddr59";
-+                    case 16: op = rv_op_vle16ff_v; break;
++    case 0x03ec: return "pmpaddr60";
-+                    }
++    case 0x03ed: return "pmpaddr61";
-+                    break;
++    case 0x03ee: return "pmpaddr62";
-+                case 1: op = rv_op_vluxei16_v; break;
++    case 0x03ef: return "pmpaddr63";
-+                case 2: op = rv_op_vlse16_v; break;
+     case 0x0780: return "mtohost";
-+                case 3: op = rv_op_vloxei16_v; break;
+     case 0x0781: return "mfromhost";
-+                }
+     case 0x0782: return "mreset";
 +                break;
 +            case 6:
 +                switch (((inst >> 20) & 0b111111111111)) {
 +                case 40: op = rv_op_vl1re32_v; break;
 +                case 552: op = rv_op_vl2re32_v; break;
 +                case 1576: op = rv_op_vl4re32_v; break;
 +                case 3624: op = rv_op_vl8re32_v; break;
 +                }
 +                switch (((inst >> 26) & 0b111)) {
 +                case 0:
 +                    switch (((inst >> 20) & 0b11111)) {
 +                    case 0: op = rv_op_vle32_v; break;
 +                    case 16: op = rv_op_vle32ff_v; break;
 +                    }
 +                    break;
 +                case 1: op = rv_op_vluxei32_v; break;
 +                case 2: op = rv_op_vlse32_v; break;
 +                case 3: op = rv_op_vloxei32_v; break;
 +                }
 +                break;
 +            case 7:
 +                switch (((inst >> 20) & 0b111111111111)) {
 +                case 40: op = rv_op_vl1re64_v; break;
 +                case 552: op = rv_op_vl2re64_v; break;
 +                case 1576: op = rv_op_vl4re64_v; break;
 +                case 3624: op = rv_op_vl8re64_v; break;
 +                }
 +                switch (((inst >> 26) & 0b111)) {
 +                case 0:
 +                    switch (((inst >> 20) & 0b11111)) {
 +                    case 0: op = rv_op_vle64_v; break;
 +                    case 16: op = rv_op_vle64ff_v; break;
 +                    }
 +                    break;
 +                case 1: op = rv_op_vluxei64_v; break;
 +                case 2: op = rv_op_vlse64_v; break;
 +                case 3: op = rv_op_vloxei64_v; break;
 +                }
 +                break;
              }
              break;
          case 3:
@@ -XXX,XX +XXX,XX @@ static void decode_inst_opcode(rv_decode *dec, rv_isa isa)
              break;
          case 9:
              switch (((inst >> 12) & 0b111)) {
 +            case 0:
 +                switch (((inst >> 20) & 0b111111111111)) {
 +                case 40: op = rv_op_vs1r_v; break;
 +                case 552: op = rv_op_vs2r_v; break;
 +                case 1576: op = rv_op_vs4r_v; break;
 +                case 3624: op = rv_op_vs8r_v; break;
 +                }
 +                switch (((inst >> 26) & 0b111)) {
 +                case 0:
 +                    switch (((inst >> 20) & 0b11111)) {
 +                    case 0: op = rv_op_vse8_v; break;
 +                    case 11: op = rv_op_vsm_v; break;
 +                    }
 +                    break;
 +                case 1: op = rv_op_vsuxei8_v; break;
 +                case 2: op = rv_op_vsse8_v; break;
 +                case 3: op = rv_op_vsoxei8_v; break;
 +                }
 +                break;
              case 2: op = rv_op_fsw; break;
              case 3: op = rv_op_fsd; break;
              case 4: op = rv_op_fsq; break;
 +            case 5:
 +                switch (((inst >> 26) & 0b111)) {
 +                case 0:
 +                    switch (((inst >> 20) & 0b11111)) {
 +                    case 0: op = rv_op_vse16_v; break;
 +                    }
 +                    break;
 +                case 1: op = rv_op_vsuxei16_v; break;
 +                case 2: op = rv_op_vsse16_v; break;
 +                case 3: op = rv_op_vsoxei16_v; break;
 +                }
 +                break;
 +            case 6:
 +                switch (((inst >> 26) & 0b111)) {
 +                case 0:
 +                    switch (((inst >> 20) & 0b11111)) {
 +                    case 0: op = rv_op_vse32_v; break;
 +                    }
 +                    break;
 +                case 1: op = rv_op_vsuxei32_v; break;
 +                case 2: op = rv_op_vsse32_v; break;
 +                case 3: op = rv_op_vsoxei32_v; break;
 +                }
 +                break;
 +            case 7:
 +                switch (((inst >> 26) & 0b111)) {
 +                case 0:
 +                    switch (((inst >> 20) & 0b11111)) {
 +                    case 0: op = rv_op_vse64_v; break;
 +                    }
 +                    break;
 +                case 1: op = rv_op_vsuxei64_v; break;
 +                case 2: op = rv_op_vsse64_v; break;
 +                case 3: op = rv_op_vsoxei64_v; break;
 +                }
 +                break;
              }
              break;
          case 11:
@@ -XXX,XX +XXX,XX @@ static void decode_inst_opcode(rv_decode *dec, rv_isa isa)
                  break;
              }
              break;
 +        case 21:
 +            switch (((inst >> 12) & 0b111)) {
 +            case 0:
 +                switch (((inst >> 26) & 0b111111)) {
 +                case 0: op = rv_op_vadd_vv; break;
 +                case 2: op = rv_op_vsub_vv; break;
 +                case 4: op = rv_op_vminu_vv; break;
 +                case 5: op = rv_op_vmin_vv; break;
 +                case 6: op = rv_op_vmaxu_vv; break;
 +                case 7: op = rv_op_vmax_vv; break;
 +                case 9: op = rv_op_vand_vv; break;
 +                case 10: op = rv_op_vor_vv; break;
 +                case 11: op = rv_op_vxor_vv; break;
 +                case 12: op = rv_op_vrgather_vv; break;
 +                case 14: op = rv_op_vrgatherei16_vv; break;
 +                case 16: if (((inst >> 25) & 1) == 0) op = rv_op_vadc_vvm; break;
 +                case 17: op = rv_op_vmadc_vvm; break;
 +                case 18: if (((inst >> 25) & 1) == 0) op = rv_op_vsbc_vvm; break;
 +                case 19: op = rv_op_vmsbc_vvm; break;
 +                case 23:
 +                    if (((inst >> 20) & 0b111111) == 32)
 +                        op = rv_op_vmv_v_v;
 +                    else if (((inst >> 25) & 1) == 0)
 +                        op = rv_op_vmerge_vvm;
 +                    break;
 +                case 24: op = rv_op_vmseq_vv; break;
 +                case 25: op = rv_op_vmsne_vv; break;
 +                case 26: op = rv_op_vmsltu_vv; break;
 +                case 27: op = rv_op_vmslt_vv; break;
 +                case 28: op = rv_op_vmsleu_vv; break;
 +                case 29: op = rv_op_vmsle_vv; break;
 +                case 32: op = rv_op_vsaddu_vv; break;
 +                case 33: op = rv_op_vsadd_vv; break;
 +                case 34: op = rv_op_vssubu_vv; break;
 +                case 35: op = rv_op_vssub_vv; break;
 +                case 37: op = rv_op_vsll_vv; break;
 +                case 39: op = rv_op_vsmul_vv; break;
 +                case 40: op = rv_op_vsrl_vv; break;
 +                case 41: op = rv_op_vsra_vv; break;
 +                case 42: op = rv_op_vssrl_vv; break;
 +                case 43: op = rv_op_vssra_vv; break;
 +                case 44: op = rv_op_vnsrl_wv; break;
 +                case 45: op = rv_op_vnsra_wv; break;
 +                case 46: op = rv_op_vnclipu_wv; break;
 +                case 47: op = rv_op_vnclip_wv; break;
 +                case 48: op = rv_op_vwredsumu_vs; break;
 +                case 49: op = rv_op_vwredsum_vs; break;
 +                }
 +                break;
 +            case 1:
 +                switch (((inst >> 26) & 0b111111)) {
 +                case 0: op = rv_op_vfadd_vv; break;
 +                case 1: op = rv_op_vfredusum_vs; break;
 +                case 2: op = rv_op_vfsub_vv; break;
 +                case 3: op = rv_op_vfredosum_vs; break;
 +                case 4: op = rv_op_vfmin_vv; break;
 +                case 5: op = rv_op_vfredmin_vs; break;
 +                case 6: op = rv_op_vfmax_vv; break;
 +                case 7: op = rv_op_vfredmax_vs; break;
 +                case 8: op = rv_op_vfsgnj_vv; break;
 +                case 9: op = rv_op_vfsgnjn_vv; break;
 +                case 10: op = rv_op_vfsgnjx_vv; break;
 +                case 16:
 +                    switch (((inst >> 15) & 0b11111)) {
 +                    case 0: if ((inst >> 25) & 1) op = rv_op_vfmv_f_s; break;
 +                    }
 +                    break;
 +                case 18:
 +                    switch (((inst >> 15) & 0b11111)) {
 +                    case 0: op = rv_op_vfcvt_xu_f_v; break;
 +                    case 1: op = rv_op_vfcvt_x_f_v; break;
 +                    case 2: op = rv_op_vfcvt_f_xu_v; break;
 +                    case 3: op = rv_op_vfcvt_f_x_v; break;
 +                    case 6: op = rv_op_vfcvt_rtz_xu_f_v; break;
 +                    case 7: op = rv_op_vfcvt_rtz_x_f_v; break;
 +                    case 8: op = rv_op_vfwcvt_xu_f_v; break;
 +                    case 9: op = rv_op_vfwcvt_x_f_v; break;
 +                    case 10: op = rv_op_vfwcvt_f_xu_v; break;
 +                    case 11: op = rv_op_vfwcvt_f_x_v; break;
 +                    case 12: op = rv_op_vfwcvt_f_f_v; break;
 +                    case 14: op = rv_op_vfwcvt_rtz_xu_f_v; break;
 +                    case 15: op = rv_op_vfwcvt_rtz_x_f_v; break;
 +                    case 16: op = rv_op_vfncvt_xu_f_w; break;
 +                    case 17: op = rv_op_vfncvt_x_f_w; break;
 +                    case 18: op = rv_op_vfncvt_f_xu_w; break;
 +                    case 19: op = rv_op_vfncvt_f_x_w; break;
 +                    case 20: op = rv_op_vfncvt_f_f_w; break;
 +                    case 21: op = rv_op_vfncvt_rod_f_f_w; break;
 +                    case 22: op = rv_op_vfncvt_rtz_xu_f_w; break;
 +                    case 23: op = rv_op_vfncvt_rtz_x_f_w; break;
 +                    }
 +                    break;
 +                case 19:
 +                    switch (((inst >> 15) & 0b11111)) {
 +                    case 0: op = rv_op_vfsqrt_v; break;
 +                    case 4: op = rv_op_vfrsqrt7_v; break;
 +                    case 5: op = rv_op_vfrec7_v; break;
 +                    case 16: op = rv_op_vfclass_v; break;
 +                    }
 +                    break;
 +                case 24: op = rv_op_vmfeq_vv; break;
 +                case 25: op = rv_op_vmfle_vv; break;
 +                case 27: op = rv_op_vmflt_vv; break;
 +                case 28: op = rv_op_vmfne_vv; break;
 +                case 32: op = rv_op_vfdiv_vv; break;
 +                case 36: op = rv_op_vfmul_vv; break;
 +                case 40: op = rv_op_vfmadd_vv; break;
 +                case 41: op = rv_op_vfnmadd_vv; break;
 +                case 42: op = rv_op_vfmsub_vv; break;
 +                case 43: op = rv_op_vfnmsub_vv; break;
 +                case 44: op = rv_op_vfmacc_vv; break;
 +                case 45: op = rv_op_vfnmacc_vv; break;
 +                case 46: op = rv_op_vfmsac_vv; break;
 +                case 47: op = rv_op_vfnmsac_vv; break;
 +                case 48: op = rv_op_vfwadd_vv; break;
 +                case 49: op = rv_op_vfwredusum_vs; break;
 +                case 50: op = rv_op_vfwsub_vv; break;
 +                case 51: op = rv_op_vfwredosum_vs; break;
 +                case 52: op = rv_op_vfwadd_wv; break;
 +                case 54: op = rv_op_vfwsub_wv; break;
 +                case 56: op = rv_op_vfwmul_vv; break;
 +                case 60: op = rv_op_vfwmacc_vv; break;
 +                case 61: op = rv_op_vfwnmacc_vv; break;
 +                case 62: op = rv_op_vfwmsac_vv; break;
 +                case 63: op = rv_op_vfwnmsac_vv; break;
 +                }
 +                break;
 +            case 2:
 +                switch (((inst >> 26) & 0b111111)) {
 +                case 0: op = rv_op_vredsum_vs; break;
 +                case 1: op = rv_op_vredand_vs; break;
 +                case 2: op = rv_op_vredor_vs; break;
 +                case 3: op = rv_op_vredxor_vs; break;
 +                case 4: op = rv_op_vredminu_vs; break;
 +                case 5: op = rv_op_vredmin_vs; break;
 +                case 6: op = rv_op_vredmaxu_vs; break;
 +                case 7: op = rv_op_vredmax_vs; break;
 +                case 8: op = rv_op_vaaddu_vv; break;
 +                case 9: op = rv_op_vaadd_vv; break;
 +                case 10: op = rv_op_vasubu_vv; break;
 +                case 11: op = rv_op_vasub_vv; break;
 +                case 16:
 +                    switch (((inst >> 15) & 0b11111)) {
 +                    case 0: if ((inst >> 25) & 1) op = rv_op_vmv_x_s; break;
 +                    case 16: op = rv_op_vcpop_m; break;
 +                    case 17: op = rv_op_vfirst_m; break;
 +                    }
 +                    break;
 +                case 18:
 +                    switch (((inst >> 15) & 0b11111)) {
 +                    case 2: op = rv_op_vzext_vf8; break;
 +                    case 3: op = rv_op_vsext_vf8; break;
 +                    case 4: op = rv_op_vzext_vf4; break;
 +                    case 5: op = rv_op_vsext_vf4; break;
 +                    case 6: op = rv_op_vzext_vf2; break;
 +                    case 7: op = rv_op_vsext_vf2; break;
 +                    }
 +                    break;
 +                case 20:
 +                    switch (((inst >> 15) & 0b11111)) {
 +                    case 1: op = rv_op_vmsbf_m;  break;
 +                    case 2: op = rv_op_vmsof_m; break;
 +                    case 3: op = rv_op_vmsif_m; break;
 +                    case 16: op = rv_op_viota_m; break;
 +                    case 17: if (((inst >> 20) & 0b11111) == 0) op = rv_op_vid_v; break;
 +                    }
 +                    break;
 +                case 23: if ((inst >> 25) & 1) op = rv_op_vcompress_vm; break;
 +                case 24: if ((inst >> 25) & 1) op = rv_op_vmandn_mm; break;
 +                case 25: if ((inst >> 25) & 1) op = rv_op_vmand_mm; break;
 +                case 26: if ((inst >> 25) & 1) op = rv_op_vmor_mm; break;
 +                case 27: if ((inst >> 25) & 1) op = rv_op_vmxor_mm; break;
 +                case 28: if ((inst >> 25) & 1) op = rv_op_vmorn_mm; break;
 +                case 29: if ((inst >> 25) & 1) op = rv_op_vmnand_mm; break;
 +                case 30: if ((inst >> 25) & 1) op = rv_op_vmnor_mm; break;
 +                case 31: if ((inst >> 25) & 1) op = rv_op_vmxnor_mm; break;
 +                case 32: op = rv_op_vdivu_vv; break;
 +                case 33: op = rv_op_vdiv_vv; break;
 +                case 34: op = rv_op_vremu_vv; break;
 +                case 35: op = rv_op_vrem_vv; break;
 +                case 36: op = rv_op_vmulhu_vv; break;
 +                case 37: op = rv_op_vmul_vv; break;
 +                case 38: op = rv_op_vmulhsu_vv; break;
 +                case 39: op = rv_op_vmulh_vv; break;
 +                case 41: op = rv_op_vmadd_vv; break;
 +                case 43: op = rv_op_vnmsub_vv; break;
 +                case 45: op = rv_op_vmacc_vv; break;
 +                case 47: op = rv_op_vnmsac_vv; break;
 +                case 48: op = rv_op_vwaddu_vv; break;
 +                case 49: op = rv_op_vwadd_vv; break;
 +                case 50: op = rv_op_vwsubu_vv; break;
 +                case 51: op = rv_op_vwsub_vv; break;
 +                case 52: op = rv_op_vwaddu_wv; break;
 +                case 53: op = rv_op_vwadd_wv; break;
 +                case 54: op = rv_op_vwsubu_wv; break;
 +                case 55: op = rv_op_vwsub_wv; break;
 +                case 56: op = rv_op_vwmulu_vv; break;
 +                case 58: op = rv_op_vwmulsu_vv; break;
 +                case 59: op = rv_op_vwmul_vv; break;
 +                case 60: op = rv_op_vwmaccu_vv; break;
 +                case 61: op = rv_op_vwmacc_vv; break;
 +                case 63: op = rv_op_vwmaccsu_vv; break;
 +                }
 +                break;
 +            case 3:
 +                switch (((inst >> 26) & 0b111111)) {
 +                case 0: op = rv_op_vadd_vi; break;
 +                case 3: op = rv_op_vrsub_vi; break;
 +                case 9: op = rv_op_vand_vi; break;
 +                case 10: op = rv_op_vor_vi; break;
 +                case 11: op = rv_op_vxor_vi; break;
 +                case 12: op = rv_op_vrgather_vi; break;
 +                case 14: op = rv_op_vslideup_vi; break;
 +                case 15: op = rv_op_vslidedown_vi; break;
 +                case 16: if (((inst >> 25) & 1) == 0) op = rv_op_vadc_vim; break;
 +                case 17: op = rv_op_vmadc_vim; break;
 +                case 23:
 +                    if (((inst >> 20) & 0b111111) == 32)
 +                        op = rv_op_vmv_v_i;
 +                    else if (((inst >> 25) & 1) == 0)
 +                        op = rv_op_vmerge_vim;
 +                    break;
 +                case 24: op = rv_op_vmseq_vi; break;
 +                case 25: op = rv_op_vmsne_vi; break;
 +                case 28: op = rv_op_vmsleu_vi; break;
 +                case 29: op = rv_op_vmsle_vi; break;
 +                case 30: op = rv_op_vmsgtu_vi; break;
 +                case 31: op = rv_op_vmsgt_vi; break;
 +                case 32: op = rv_op_vsaddu_vi; break;
 +                case 33: op = rv_op_vsadd_vi; break;
 +                case 37: op = rv_op_vsll_vi; break;
 +                case 39:
 +                    switch (((inst >> 15) & 0b11111)) {
 +                    case 0: op = rv_op_vmv1r_v; break;
 +                    case 1: op = rv_op_vmv2r_v; break;
 +                    case 3: op = rv_op_vmv4r_v; break;
 +                    case 7: op = rv_op_vmv8r_v; break;
 +                    }
 +                    break;
 +                case 40: op = rv_op_vsrl_vi; break;
 +                case 41: op = rv_op_vsra_vi; break;
 +                case 42: op = rv_op_vssrl_vi; break;
 +                case 43: op = rv_op_vssra_vi; break;
 +                case 44: op = rv_op_vnsrl_wi; break;
 +                case 45: op = rv_op_vnsra_wi; break;
 +                case 46: op = rv_op_vnclipu_wi; break;
 +                case 47: op = rv_op_vnclip_wi; break;
 +                }
 +                break;
 +            case 4:
 +                switch (((inst >> 26) & 0b111111)) {
 +                case 0: op = rv_op_vadd_vx; break;
 +                case 2: op = rv_op_vsub_vx; break;
 +                case 3: op = rv_op_vrsub_vx; break;
 +                case 4: op = rv_op_vminu_vx; break;
 +                case 5: op = rv_op_vmin_vx; break;
 +                case 6: op = rv_op_vmaxu_vx; break;
 +                case 7: op = rv_op_vmax_vx; break;
 +                case 9: op = rv_op_vand_vx; break;
 +                case 10: op = rv_op_vor_vx; break;
 +                case 11: op = rv_op_vxor_vx; break;
 +                case 12: op = rv_op_vrgather_vx; break;
 +                case 14: op = rv_op_vslideup_vx; break;
 +                case 15: op = rv_op_vslidedown_vx; break;
 +                case 16: if (((inst >> 25) & 1) == 0) op = rv_op_vadc_vxm; break;
 +                case 17: op = rv_op_vmadc_vxm; break;
 +                case 18: if (((inst >> 25) & 1) == 0) op = rv_op_vsbc_vxm; break;
 +                case 19: op = rv_op_vmsbc_vxm; break;
 +                case 23:
 +                    if (((inst >> 20) & 0b111111) == 32)
 +                        op = rv_op_vmv_v_x;
 +                    else if (((inst >> 25) & 1) == 0)
 +                        op = rv_op_vmerge_vxm;
 +                    break;
 +                case 24: op = rv_op_vmseq_vx; break;
 +                case 25: op = rv_op_vmsne_vx; break;
 +                case 26: op = rv_op_vmsltu_vx; break;
 +                case 27: op = rv_op_vmslt_vx; break;
 +                case 28: op = rv_op_vmsleu_vx; break;
 +                case 29: op = rv_op_vmsle_vx; break;
 +                case 30: op = rv_op_vmsgtu_vx; break;
 +                case 31: op = rv_op_vmsgt_vx; break;
 +                case 32: op = rv_op_vsaddu_vx; break;
 +                case 33: op = rv_op_vsadd_vx; break;
 +                case 34: op = rv_op_vssubu_vx; break;
 +                case 35: op = rv_op_vssub_vx; break;
 +                case 37: op = rv_op_vsll_vx; break;
 +                case 39: op = rv_op_vsmul_vx; break;
 +                case 40: op = rv_op_vsrl_vx; break;
 +                case 41: op = rv_op_vsra_vx; break;
 +                case 42: op = rv_op_vssrl_vx; break;
 +                case 43: op = rv_op_vssra_vx; break;
 +                case 44: op = rv_op_vnsrl_wx; break;
 +                case 45: op = rv_op_vnsra_wx; break;
 +                case 46: op = rv_op_vnclipu_wx; break;
 +                case 47: op = rv_op_vnclip_wx; break;
 +                }
 +                break;
 +            case 5:
 +                switch (((inst >> 26) & 0b111111)) {
 +                case 0: op = rv_op_vfadd_vf; break;
 +                case 2: op = rv_op_vfsub_vf; break;
 +                case 4: op = rv_op_vfmin_vf; break;
 +                case 6: op = rv_op_vfmax_vf; break;
 +                case 8: op = rv_op_vfsgnj_vf; break;
 +                case 9: op = rv_op_vfsgnjn_vf; break;
 +                case 10: op = rv_op_vfsgnjx_vf; break;
 +                case 14: op = rv_op_vfslide1up_vf; break;
 +                case 15: op = rv_op_vfslide1down_vf; break;
 +                case 16:
 +                    switch (((inst >> 20) & 0b11111)) {
 +                    case 0: if ((inst >> 25) & 1) op = rv_op_vfmv_s_f; break;
 +                    }
 +                    break;
 +                case 23:
 +                    if (((inst >> 25) & 1) == 0)
 +                        op = rv_op_vfmerge_vfm;
 +                    else if (((inst >> 20) & 0b111111) == 32)
 +                        op = rv_op_vfmv_v_f;
 +                    break;
 +                case 24: op = rv_op_vmfeq_vf; break;
 +                case 25: op = rv_op_vmfle_vf; break;
 +                case 27: op = rv_op_vmflt_vf; break;
 +                case 28: op = rv_op_vmfne_vf; break;
 +                case 29: op = rv_op_vmfgt_vf; break;
 +                case 31: op = rv_op_vmfge_vf; break;
 +                case 32: op = rv_op_vfdiv_vf; break;
 +                case 33: op = rv_op_vfrdiv_vf; break;
 +                case 36: op = rv_op_vfmul_vf; break;
 +                case 39: op = rv_op_vfrsub_vf; break;
 +                case 40: op = rv_op_vfmadd_vf; break;
 +                case 41: op = rv_op_vfnmadd_vf; break;
 +                case 42: op = rv_op_vfmsub_vf; break;
 +                case 43: op = rv_op_vfnmsub_vf; break;
 +                case 44: op = rv_op_vfmacc_vf; break;
 +                case 45: op = rv_op_vfnmacc_vf; break;
 +                case 46: op = rv_op_vfmsac_vf; break;
 +                case 47: op = rv_op_vfnmsac_vf; break;
 +                case 48: op = rv_op_vfwadd_vf; break;
 +                case 50: op = rv_op_vfwsub_vf; break;
 +                case 52: op = rv_op_vfwadd_wf; break;
 +                case 54: op = rv_op_vfwsub_wf; break;
 +                case 56: op = rv_op_vfwmul_vf; break;
 +                case 60: op = rv_op_vfwmacc_vf; break;
 +                case 61: op = rv_op_vfwnmacc_vf; break;
 +                case 62: op = rv_op_vfwmsac_vf; break;
 +                case 63: op = rv_op_vfwnmsac_vf; break;
 +                }
 +                break;
 +            case 6:
 +                switch (((inst >> 26) & 0b111111)) {
 +                case 8: op = rv_op_vaaddu_vx; break;
 +                case 9: op = rv_op_vaadd_vx; break;
 +                case 10: op = rv_op_vasubu_vx; break;
 +                case 11: op = rv_op_vasub_vx; break;
 +                case 14: op = rv_op_vslide1up_vx; break;
 +                case 15: op = rv_op_vslide1down_vx; break;
 +                case 16:
 +                    switch (((inst >> 20) & 0b11111)) {
 +                    case 0: if ((inst >> 25) & 1) op = rv_op_vmv_s_x; break;
 +                    }
 +                    break;
 +                case 32: op = rv_op_vdivu_vx; break;
 +                case 33: op = rv_op_vdiv_vx; break;
 +                case 34: op = rv_op_vremu_vx; break;
 +                case 35: op = rv_op_vrem_vx; break;
 +                case 36: op = rv_op_vmulhu_vx; break;
 +                case 37: op = rv_op_vmul_vx; break;
 +                case 38: op = rv_op_vmulhsu_vx; break;
 +                case 39: op = rv_op_vmulh_vx; break;
 +                case 41: op = rv_op_vmadd_vx; break;
 +                case 43: op = rv_op_vnmsub_vx; break;
 +                case 45: op = rv_op_vmacc_vx; break;
 +                case 47: op = rv_op_vnmsac_vx; break;
 +                case 48: op = rv_op_vwaddu_vx; break;
 +                case 49: op = rv_op_vwadd_vx; break;
 +                case 50: op = rv_op_vwsubu_vx; break;
 +                case 51: op = rv_op_vwsub_vx; break;
 +                case 52: op = rv_op_vwaddu_wx; break;
 +                case 53: op = rv_op_vwadd_wx; break;
 +                case 54: op = rv_op_vwsubu_wx; break;
 +                case 55: op = rv_op_vwsub_wx; break;
 +                case 56: op = rv_op_vwmulu_vx; break;
 +                case 58: op = rv_op_vwmulsu_vx; break;
 +                case 59: op = rv_op_vwmul_vx; break;
 +                case 60: op = rv_op_vwmaccu_vx; break;
 +                case 61: op = rv_op_vwmacc_vx; break;
 +                case 62: op = rv_op_vwmaccus_vx; break;
 +                case 63: op = rv_op_vwmaccsu_vx; break;
 +                }
 +                break;
 +            case 7:
 +                if (((inst >> 31) & 1) == 0) {
 +                    op = rv_op_vsetvli;
 +                } else if ((inst >> 30) & 1) {
 +                    op = rv_op_vsetivli;
 +                } else if (((inst >> 25) & 0b11111) == 0) {
 +                    op = rv_op_vsetvl;
 +                }
 +                break;
 +            }
 +            break;
          case 22:
              switch (((inst >> 12) & 0b111)) {
              case 0: op = rv_op_addid; break;
@@ -XXX,XX +XXX,XX @@ static uint32_t operand_cimmq(rv_inst inst)
          ((inst << 57) >> 62) << 6;
  }
 +static uint32_t operand_vimm(rv_inst inst)
 +{
 +    return (int64_t)(inst << 44) >> 59;
 +}
 +
 +static uint32_t operand_vzimm11(rv_inst inst)
 +{
 +    return (inst << 33) >> 53;
 +}
 +
 +static uint32_t operand_vzimm10(rv_inst inst)
 +{
 +    return (inst << 34) >> 54;
 +}
 +
  static uint32_t operand_bs(rv_inst inst)
  {
      return (inst << 32) >> 62;
@@ -XXX,XX +XXX,XX @@ static uint32_t operand_rnum(rv_inst inst)
      return (inst << 40) >> 60;
  }
 +static uint32_t operand_vm(rv_inst inst)
 +{
 +    return (inst << 38) >> 63;
 +}
 +
  /* decode operands */
  static void decode_inst_operands(rv_decode *dec, rv_isa isa)
@@ -XXX,XX +XXX,XX @@ static void decode_inst_operands(rv_decode *dec, rv_isa isa)
          dec->rs1 = operand_rs1(inst);
          dec->rnum = operand_rnum(inst);
          break;
 +    case rv_codec_v_r:
 +        dec->rd = operand_rd(inst);
 +        dec->rs1 = operand_rs1(inst);
 +        dec->rs2 = operand_rs2(inst);
 +        dec->vm = operand_vm(inst);
 +        break;
 +    case rv_codec_v_ldst:
 +        dec->rd = operand_rd(inst);
 +        dec->rs1 = operand_rs1(inst);
 +        dec->vm = operand_vm(inst);
 +        break;
 +    case rv_codec_v_i:
 +        dec->rd = operand_rd(inst);
 +        dec->rs2 = operand_rs2(inst);
 +        dec->imm = operand_vimm(inst);
 +        dec->vm = operand_vm(inst);
 +        break;
 +    case rv_codec_vsetvli:
 +        dec->rd = operand_rd(inst);
 +        dec->rs1 = operand_rs1(inst);
 +        dec->vzimm = operand_vzimm11(inst);
 +        break;
 +    case rv_codec_vsetivli:
 +        dec->rd = operand_rd(inst);
 +        dec->imm = operand_vimm(inst);
 +        dec->vzimm = operand_vzimm10(inst);
 +        break;
      };
  }
@@ -XXX,XX +XXX,XX @@ static void format_inst(char *buf, size_t buflen, size_t tab, rv_decode *dec)
              snprintf(tmp, sizeof(tmp), "%d", dec->imm);
              append(buf, tmp, buflen);
              break;
 +        case 'u':
 +            snprintf(tmp, sizeof(tmp), "%u", ((uint32_t)dec->imm & 0b11111));
 +            append(buf, tmp, buflen);
 +            break;
          case 'o':
              snprintf(tmp, sizeof(tmp), "%d", dec->imm);
              append(buf, tmp, buflen);
@@ -XXX,XX +XXX,XX @@ static void format_inst(char *buf, size_t buflen, size_t tab, rv_decode *dec)
                  append(buf, ".rl", buflen);
              }
              break;
 +        case 'l':
 +            append(buf, ",v0", buflen);
 +            break;
 +        case 'm':
 +            if (dec->vm == 0) {
 +                append(buf, ",v0.t", buflen);
 +            }
 +            break;
 +        case 'D':
 +            append(buf, rv_vreg_name_sym[dec->rd], buflen);
 +            break;
 +        case 'E':
 +            append(buf, rv_vreg_name_sym[dec->rs1], buflen);
 +            break;
 +        case 'F':
 +            append(buf, rv_vreg_name_sym[dec->rs2], buflen);
 +            break;
 +        case 'G':
 +            append(buf, rv_vreg_name_sym[dec->rs3], buflen);
 +            break;
 +        case 'v': {
 +            char nbuf[32] = {0};
 +            const int sew = 1 << (((dec->vzimm >> 3) & 0b111) + 3);
 +            sprintf(nbuf, "%d", sew);
 +            const int lmul = dec->vzimm & 0b11;
 +            const int flmul = (dec->vzimm >> 2) & 1;
 +            const char *vta = (dec->vzimm >> 6) & 1 ? "ta" : "tu";
 +            const char *vma = (dec->vzimm >> 7) & 1 ? "ma" : "mu";
 +            append(buf, "e", buflen);
 +            append(buf, nbuf, buflen);
 +            append(buf, ",m", buflen);
 +            if (flmul) {
 +                switch (lmul) {
 +                case 3:
 +                    sprintf(nbuf, "f2");
 +                    break;
 +                case 2:
 +                    sprintf(nbuf, "f4");
 +                    break;
 +                case 1:
 +                    sprintf(nbuf, "f8");
 +                break;
 +                }
 +                append(buf, nbuf, buflen);
 +            } else {
 +                sprintf(nbuf, "%d", 1 << lmul);
 +                append(buf, nbuf, buflen);
 +            }
 +            append(buf, ",", buflen);
 +            append(buf, vta, buflen);
 +            append(buf, ",", buflen);
 +            append(buf, vma, buflen);
 +            break;
 +        }
          default:
              break;
          }
@@ -XXX,XX +XXX,XX @@ disasm_inst(char *buf, size_t buflen, rv_isa isa, uint64_t pc, rv_inst inst)
      decode_inst_operands(&dec, isa);
      decode_inst_decompress(&dec, isa);
      decode_inst_lift_pseudo(&dec);
 -    format_inst(buf, buflen, 16, &dec);
 +    format_inst(buf, buflen, 24, &dec);
  }
  #define INST_FMT_2 "%04" PRIx64 "              "
 --
-.37.3
+.45.1

-[PULL 04/10] hw/arm, loongarch: Move load_image_to_fw_cfg() to common location
+[PULL 28/28] target/riscv: raise an exception when CSRRS/CSRRC writes a read-only CSR
-From: Sunil V L <sunilvl@ventanamicro.com>
+From: Yu-Ming Chang <yumin686@andestech.com>
-load_image_to_fw_cfg() is duplicated by both arm and loongarch. The same
+Both CSRRS and CSRRC always read the addressed CSR and cause any read side
-function will be required by riscv too. So, it's time to refactor and
+effects regardless of rs1 and rd fields. Note that if rs1 specifies a register
-move this function to a common path.
+holding a zero value other than x0, the instruction will still attempt to write
 the unmodified value back to the CSR and will cause any attendant side effects.
-Signed-off-by: Sunil V L <sunilvl@ventanamicro.com>
+So if CSRRS or CSRRC tries to write a read-only CSR with rs1 which specifies
-Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
+a register holding a zero value, an illegal instruction exception should be
 raised.
 Signed-off-by: Yu-Ming Chang <yumin686@andestech.com>
 Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
-Reviewed-by: Song Gao <gaosong@loongson.cn>
+Message-ID: <20240403070823.80897-1-yumin686@andestech.com>
 Message-Id: <20221004092351.18209-2-sunilvl@ventanamicro.com>
 Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
 ---
- include/hw/nvram/fw_cfg.h | 21 +++++++++++++++++
+ target/riscv/cpu.h       |  4 ++++
- hw/arm/boot.c             | 49 ---------------------------------------
+ target/riscv/csr.c       | 51 ++++++++++++++++++++++++++++++++++++----
- hw/loongarch/virt.c       | 33 --------------------------
+ target/riscv/op_helper.c |  6 ++---
- hw/nvram/fw_cfg.c         | 32 +++++++++++++++++++++++++
+files changed, 53 insertions(+), 8 deletions(-)
 files changed, 53 insertions(+), 82 deletions(-)
-diff --git a/include/hw/nvram/fw_cfg.h b/include/hw/nvram/fw_cfg.h
+diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
 index XXXXXXX..XXXXXXX 100644
---- a/include/hw/nvram/fw_cfg.h
+--- a/target/riscv/cpu.h
-+++ b/include/hw/nvram/fw_cfg.h
++++ b/target/riscv/cpu.h
-@@ -XXX,XX +XXX,XX @@ bool fw_cfg_dma_enabled(void *opaque);
+@@ -XXX,XX +XXX,XX @@ void cpu_get_tb_cpu_state(CPURISCVState *env, vaddr *pc,
-  */
+ void riscv_cpu_update_mask(CPURISCVState *env);
- const char *fw_cfg_arch_key_name(uint16_t key);
+ bool riscv_cpu_is_32bit(RISCVCPU *cpu);
-+/**
++RISCVException riscv_csrr(CPURISCVState *env, int csrno,
-+ * load_image_to_fw_cfg() - Load an image file into an fw_cfg entry identified
++                          target_ulong *ret_value);
-+ *                          by key.
+ RISCVException riscv_csrrw(CPURISCVState *env, int csrno,
-+ * @fw_cfg:         The firmware config instance to store the data in.
+                            target_ulong *ret_value,
-+ * @size_key:       The firmware config key to store the size of the loaded
+                            target_ulong new_value, target_ulong write_mask);
-+ *                  data under, with fw_cfg_add_i32().
+@@ -XXX,XX +XXX,XX @@ typedef RISCVException (*riscv_csr_op_fn)(CPURISCVState *env, int csrno,
-+ * @data_key:       The firmware config key to store the loaded data under,
+                                           target_ulong new_value,
-+ *                  with fw_cfg_add_bytes().
+                                           target_ulong write_mask);
-+ * @image_name:     The name of the image file to load. If it is NULL, the
-+ *                  function returns without doing anything.
++RISCVException riscv_csrr_i128(CPURISCVState *env, int csrno,
-+ * @try_decompress: Whether the image should be decompressed (gunzipped) before
++                               Int128 *ret_value);
-+ *                  adding it to fw_cfg. If decompression fails, the image is
+ RISCVException riscv_csrrw_i128(CPURISCVState *env, int csrno,
-+ *                  loaded as-is.
+                                 Int128 *ret_value,
-+ *
+                                 Int128 new_value, Int128 write_mask);
-+ * In case of failure, the function prints an error message to stderr and the
+diff --git a/target/riscv/csr.c b/target/riscv/csr.c
 + * process exits with status 1.
 + */
 +void load_image_to_fw_cfg(FWCfgState *fw_cfg, uint16_t size_key,
 +                          uint16_t data_key, const char *image_name,
 +                          bool try_decompress);
 +
  #endif
 diff --git a/hw/arm/boot.c b/hw/arm/boot.c
 index XXXXXXX..XXXXXXX 100644
---- a/hw/arm/boot.c
+--- a/target/riscv/csr.c
-+++ b/hw/arm/boot.c
++++ b/target/riscv/csr.c
-@@ -XXX,XX +XXX,XX @@ static void do_cpu_reset(void *opaque)
+@@ -XXX,XX +XXX,XX @@ static RISCVException rmw_seed(CPURISCVState *env, int csrno,
  static inline RISCVException riscv_csrrw_check(CPURISCVState *env,
                                                 int csrno,
 -                                               bool write_mask)
 +                                               bool write)
  {
      /* check privileges and return RISCV_EXCP_ILLEGAL_INST if check fails */
      bool read_only = get_field(csrno, 0xC00) == 3;
@@ -XXX,XX +XXX,XX @@ static inline RISCVException riscv_csrrw_check(CPURISCVState *env,
      }
+     /* read / write check */
+-    if (write_mask && read_only) {
++    if (write && read_only) {
+         return RISCV_EXCP_ILLEGAL_INST;
+     }
+@@ -XXX,XX +XXX,XX @@ static RISCVException riscv_csrrw_do64(CPURISCVState *env, int csrno,
+     return RISCV_EXCP_NONE;
  }
--/**
++RISCVException riscv_csrr(CPURISCVState *env, int csrno,
-- * load_image_to_fw_cfg() - Load an image file into an fw_cfg entry identified
++                           target_ulong *ret_value)
 - *                          by key.
 - * @fw_cfg:         The firmware config instance to store the data in.
 - * @size_key:       The firmware config key to store the size of the loaded
 - *                  data under, with fw_cfg_add_i32().
 - * @data_key:       The firmware config key to store the loaded data under,
 - *                  with fw_cfg_add_bytes().
 - * @image_name:     The name of the image file to load. If it is NULL, the
 - *                  function returns without doing anything.
 - * @try_decompress: Whether the image should be decompressed (gunzipped) before
 - *                  adding it to fw_cfg. If decompression fails, the image is
 - *                  loaded as-is.
 - *
 - * In case of failure, the function prints an error message to stderr and the
 - * process exits with status 1.
 - */
 -static void load_image_to_fw_cfg(FWCfgState *fw_cfg, uint16_t size_key,
 -                                 uint16_t data_key, const char *image_name,
 -                                 bool try_decompress)
 -{
 -    size_t size = -1;
 -    uint8_t *data;
 -
 -    if (image_name == NULL) {
 -        return;
 -    }
 -
 -    if (try_decompress) {
 -        size = load_image_gzipped_buffer(image_name,
 -                                         LOAD_IMAGE_MAX_GUNZIP_BYTES, &data);
 -    }
 -
 -    if (size == (size_t)-1) {
 -        gchar *contents;
 -        gsize length;
 -
 -        if (!g_file_get_contents(image_name, &contents, &length, NULL)) {
 -            error_report("failed to load \"%s\"", image_name);
 -            exit(1);
 -        }
 -        size = length;
 -        data = (uint8_t *)contents;
 -    }
 -
 -    fw_cfg_add_i32(fw_cfg, size_key, size);
 -    fw_cfg_add_bytes(fw_cfg, data_key, data, size);
 -}
 -
  static int do_arm_linux_init(Object *obj, void *opaque)
  {
      if (object_dynamic_cast(obj, TYPE_ARM_LINUX_BOOT_IF)) {
 diff --git a/hw/loongarch/virt.c b/hw/loongarch/virt.c
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/loongarch/virt.c
 +++ b/hw/loongarch/virt.c
@@ -XXX,XX +XXX,XX @@ static void reset_load_elf(void *opaque)
      }
  }
 -/* Load an image file into an fw_cfg entry identified by key. */
 -static void load_image_to_fw_cfg(FWCfgState *fw_cfg, uint16_t size_key,
 -                                 uint16_t data_key, const char *image_name,
 -                                 bool try_decompress)
 -{
 -    size_t size = -1;
 -    uint8_t *data;
 -
 -    if (image_name == NULL) {
 -        return;
 -    }
 -
 -    if (try_decompress) {
 -        size = load_image_gzipped_buffer(image_name,
 -                                         LOAD_IMAGE_MAX_GUNZIP_BYTES, &data);
 -    }
 -
 -    if (size == (size_t)-1) {
 -        gchar *contents;
 -        gsize length;
 -
 -        if (!g_file_get_contents(image_name, &contents, &length, NULL)) {
 -            error_report("failed to load \"%s\"", image_name);
 -            exit(1);
 -        }
 -        size = length;
 -        data = (uint8_t *)contents;
 -    }
 -
 -    fw_cfg_add_i32(fw_cfg, size_key, size);
 -    fw_cfg_add_bytes(fw_cfg, data_key, data, size);
 -}
 -
  static void fw_cfg_add_kernel_info(FWCfgState *fw_cfg)
  {
      /*
 diff --git a/hw/nvram/fw_cfg.c b/hw/nvram/fw_cfg.c
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/nvram/fw_cfg.c
 +++ b/hw/nvram/fw_cfg.c
@@ -XXX,XX +XXX,XX @@
  #include "qapi/error.h"
  #include "hw/acpi/aml-build.h"
  #include "hw/pci/pci_bus.h"
 +#include "hw/loader.h"
  #define FW_CFG_FILE_SLOTS_DFLT 0x20
@@ -XXX,XX +XXX,XX @@ FWCfgState *fw_cfg_find(void)
      return FW_CFG(object_resolve_path_type("", TYPE_FW_CFG, NULL));
  }
 +void load_image_to_fw_cfg(FWCfgState *fw_cfg, uint16_t size_key,
 +                          uint16_t data_key, const char *image_name,
 +                          bool try_decompress)
 +{
-+    size_t size = -1;
++    RISCVException ret = riscv_csrrw_check(env, csrno, false);
-+    uint8_t *data;
++    if (ret != RISCV_EXCP_NONE) {
-+
++        return ret;
 +    if (image_name == NULL) {
 +        return;
 +    }
 +
-+    if (try_decompress) {
++    return riscv_csrrw_do64(env, csrno, ret_value, 0, 0);
-+        size = load_image_gzipped_buffer(image_name,
++}
-+                                         LOAD_IMAGE_MAX_GUNZIP_BYTES, &data);
++
  RISCVException riscv_csrrw(CPURISCVState *env, int csrno,
                             target_ulong *ret_value,
                             target_ulong new_value, target_ulong write_mask)
  {
 -    RISCVException ret = riscv_csrrw_check(env, csrno, write_mask);
 +    RISCVException ret = riscv_csrrw_check(env, csrno, true);
      if (ret != RISCV_EXCP_NONE) {
          return ret;
      }
@@ -XXX,XX +XXX,XX @@ static RISCVException riscv_csrrw_do128(CPURISCVState *env, int csrno,
      return RISCV_EXCP_NONE;
  }
 +RISCVException riscv_csrr_i128(CPURISCVState *env, int csrno,
 +                               Int128 *ret_value)
 +{
 +    RISCVException ret;
 +
 +    ret = riscv_csrrw_check(env, csrno, false);
 +    if (ret != RISCV_EXCP_NONE) {
 +        return ret;
 +    }
 +
-+    if (size == (size_t)-1) {
++    if (csr_ops[csrno].read128) {
-+        gchar *contents;
++        return riscv_csrrw_do128(env, csrno, ret_value,
-+        gsize length;
++                                 int128_zero(), int128_zero());
 +
 +        if (!g_file_get_contents(image_name, &contents, &length, NULL)) {
 +            error_report("failed to load \"%s\"", image_name);
 +            exit(1);
 +        }
 +        size = length;
 +        data = (uint8_t *)contents;
 +    }
 +
-+    fw_cfg_add_i32(fw_cfg, size_key, size);
++    /*
-+    fw_cfg_add_bytes(fw_cfg, data_key, data, size);
++     * Fall back to 64-bit version for now, if the 128-bit alternative isn't
 +     * at all defined.
 +     * Note, some CSRs don't need to extend to MXLEN (64 upper bits non
 +     * significant), for those, this fallback is correctly handling the
 +     * accesses
 +     */
 +    target_ulong old_value;
 +    ret = riscv_csrrw_do64(env, csrno, &old_value,
 +                           (target_ulong)0,
 +                           (target_ulong)0);
 +    if (ret == RISCV_EXCP_NONE && ret_value) {
 +        *ret_value = int128_make64(old_value);
 +    }
 +    return ret;
 +}
++
- static void fw_cfg_class_init(ObjectClass *klass, void *data)
+ RISCVException riscv_csrrw_i128(CPURISCVState *env, int csrno,
                                  Int128 *ret_value,
                                  Int128 new_value, Int128 write_mask)
  {
+     RISCVException ret;
+-    ret = riscv_csrrw_check(env, csrno, int128_nz(write_mask));
++    ret = riscv_csrrw_check(env, csrno, true);
+     if (ret != RISCV_EXCP_NONE) {
+         return ret;
+     }
+diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c
+index XXXXXXX..XXXXXXX 100644
+--- a/target/riscv/op_helper.c
++++ b/target/riscv/op_helper.c
+@@ -XXX,XX +XXX,XX @@ target_ulong helper_csrr(CPURISCVState *env, int csr)
+     }
+     target_ulong val = 0;
+-    RISCVException ret = riscv_csrrw(env, csr, &val, 0, 0);
++    RISCVException ret = riscv_csrr(env, csr, &val);
+     if (ret != RISCV_EXCP_NONE) {
+         riscv_raise_exception(env, ret, GETPC());
+@@ -XXX,XX +XXX,XX @@ target_ulong helper_csrrw(CPURISCVState *env, int csr,
+ target_ulong helper_csrr_i128(CPURISCVState *env, int csr)
+ {
+     Int128 rv = int128_zero();
+-    RISCVException ret = riscv_csrrw_i128(env, csr, &rv,
+-                                          int128_zero(),
+-                                          int128_zero());
++    RISCVException ret = riscv_csrr_i128(env, csr, &rv);
+     if (ret != RISCV_EXCP_NONE) {
+         riscv_raise_exception(env, ret, GETPC());
 --
-.37.3
+.45.1

From: Alistair Francis <alistair.francis@wdc.com>

The following changes since commit 2ba341b3694cf3cff7b8a1df4cc765900d5c4f60:

Merge tag 'kraxel-20221013-pull-request' of https://gitlab.com/kraxel/qemu into staging (2022-10-13 13:55:53 -0400)

are available in the Git repository at:

https://github.com/alistair23/qemu.git tags/pull-riscv-to-apply-20221014

for you to fetch changes up to 47566421f029b0a489b63f8195b3ff944e017056:

target/riscv: pmp: Fixup TLB size calculation (2022-10-14 14:36:19 +1000)

----------------------------------------------------------------
Third RISC-V PR for QEMU 7.2

* Update qtest comment
* Fix coverity issue with Ibex SPI
* Move load_image_to_fw_cfg() to common location
* Enable booting S-mode firmware from pflash on virt machine
* Add disas support for vector instructions
* Priority level fixes for PLIC
* Fixup TLB size calculation when using PMP

----------------------------------------------------------------
Alistair Francis (1):
      target/riscv: pmp: Fixup TLB size calculation

Bin Meng (1):
      hw/riscv: Update comment for qtest check in riscv_find_firmware()

Jim Shu (2):
      hw/intc: sifive_plic: fix hard-coded max priority level
      hw/intc: sifive_plic: change interrupt priority register to WARL field

Sunil V L (3):
      hw/arm, loongarch: Move load_image_to_fw_cfg() to common location
      hw/riscv: virt: Move create_fw_cfg() prior to loading kernel
      hw/riscv: virt: Enable booting S-mode firmware from pflash

Wilfred Mallawa (2):
      hw/ssi: ibex_spi: fixup coverity issue
      hw/ssi: ibex_spi: fixup/add rw1c functionality

Yang Liu (1):
      disas/riscv.c: rvv: Add disas support for vector instructions

From: Bin Meng <bmeng.cn@gmail.com>

Since commit 4211fc553234 ("roms/opensbi: Remove ELF images"), the
comment for qtest check in riscv_find_firmware() is out of date.
Update it to reflect the latest status.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <BN7PR08MB435525C92550BAC5467BE672BF219@BN7PR08MB4355.namprd08.prod.outlook.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 hw/riscv/boot.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/hw/riscv/boot.c b/hw/riscv/boot.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/riscv/boot.c
+++ b/hw/riscv/boot.c
@@ -XXX,XX +XXX,XX @@ char *riscv_find_firmware(const char *firmware_filename)
     if (filename == NULL) {
         if (!qtest_enabled()) {
             /*
-             * We only ship plain binary bios images in the QEMU source.
-             * With Spike machine that uses ELF images as the default bios,
+             * We only ship OpenSBI binary bios images in the QEMU source.
+             * For machines that use images other than the default bios,
              * running QEMU test will complain hence let's suppress the error
              * report for QEMU testing.
              */
-- 
2.37.3

From: Wilfred Mallawa <wilfred.mallawa@wdc.com>

This patch addresses the coverity issues specified in [1],
as suggested, `FIELD_DP32()`/`FIELD_EX32()` macros have been
implemented to clean up the code.

[1] https://www.mail-archive.com/qemu-devel@nongnu.org/msg887713.html

Fixes: Coverity CID 1488107

Signed-off-by: Wilfred Mallawa <wilfred.mallawa@wdc.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Message-Id: <20220930033241.206581-2-wilfred.mallawa@opensource.wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 hw/ssi/ibex_spi_host.c | 132 +++++++++++++++++++++--------------------
 1 file changed, 68 insertions(+), 64 deletions(-)

diff --git a/hw/ssi/ibex_spi_host.c b/hw/ssi/ibex_spi_host.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/ssi/ibex_spi_host.c
+++ b/hw/ssi/ibex_spi_host.c
@@ -XXX,XX +XXX,XX @@ static inline uint8_t div4_round_up(uint8_t dividend)
 
 static void ibex_spi_rxfifo_reset(IbexSPIHostState *s)
 {
+    uint32_t data = s->regs[IBEX_SPI_HOST_STATUS];
     /* Empty the RX FIFO and assert RXEMPTY */
     fifo8_reset(&s->rx_fifo);
-    s->regs[IBEX_SPI_HOST_STATUS] &= ~R_STATUS_RXFULL_MASK;
-    s->regs[IBEX_SPI_HOST_STATUS] |= R_STATUS_RXEMPTY_MASK;
+    data = FIELD_DP32(data, STATUS, RXFULL, 0);
+    data = FIELD_DP32(data, STATUS, RXEMPTY, 1);
+    s->regs[IBEX_SPI_HOST_STATUS] = data;
 }
 
 static void ibex_spi_txfifo_reset(IbexSPIHostState *s)
 {
+    uint32_t data = s->regs[IBEX_SPI_HOST_STATUS];
     /* Empty the TX FIFO and assert TXEMPTY */
     fifo8_reset(&s->tx_fifo);
-    s->regs[IBEX_SPI_HOST_STATUS] &= ~R_STATUS_TXFULL_MASK;
-    s->regs[IBEX_SPI_HOST_STATUS] |= R_STATUS_TXEMPTY_MASK;
+    data = FIELD_DP32(data, STATUS, TXFULL, 0);
+    data = FIELD_DP32(data, STATUS, TXEMPTY, 1);
+    s->regs[IBEX_SPI_HOST_STATUS] = data;
 }
 
 static void ibex_spi_host_reset(DeviceState *dev)
@@ -XXX,XX +XXX,XX @@ static void ibex_spi_host_reset(DeviceState *dev)
  */
 static void ibex_spi_host_irq(IbexSPIHostState *s)
 {
-    bool error_en = s->regs[IBEX_SPI_HOST_INTR_ENABLE]
-                    & R_INTR_ENABLE_ERROR_MASK;
-    bool event_en = s->regs[IBEX_SPI_HOST_INTR_ENABLE]
-                    & R_INTR_ENABLE_SPI_EVENT_MASK;
-    bool err_pending = s->regs[IBEX_SPI_HOST_INTR_STATE]
-                        & R_INTR_STATE_ERROR_MASK;
-    bool status_pending = s->regs[IBEX_SPI_HOST_INTR_STATE]
-                        & R_INTR_STATE_SPI_EVENT_MASK;
+    uint32_t intr_test_reg = s->regs[IBEX_SPI_HOST_INTR_TEST];
+    uint32_t intr_en_reg = s->regs[IBEX_SPI_HOST_INTR_ENABLE];
+    uint32_t intr_state_reg = s->regs[IBEX_SPI_HOST_INTR_STATE];
+
+    uint32_t err_en_reg = s->regs[IBEX_SPI_HOST_ERROR_ENABLE];
+    uint32_t event_en_reg = s->regs[IBEX_SPI_HOST_EVENT_ENABLE];
+    uint32_t err_status_reg = s->regs[IBEX_SPI_HOST_ERROR_STATUS];
+    uint32_t status_reg = s->regs[IBEX_SPI_HOST_STATUS];
+
+
+    bool error_en = FIELD_EX32(intr_en_reg, INTR_ENABLE, ERROR);
+    bool event_en = FIELD_EX32(intr_en_reg, INTR_ENABLE, SPI_EVENT);
+    bool err_pending = FIELD_EX32(intr_state_reg, INTR_STATE, ERROR);
+    bool status_pending = FIELD_EX32(intr_state_reg, INTR_STATE, SPI_EVENT);
+
     int err_irq = 0, event_irq = 0;
 
     /* Error IRQ enabled and Error IRQ Cleared */
     if (error_en && !err_pending) {
         /* Event enabled, Interrupt Test Error */
-        if (s->regs[IBEX_SPI_HOST_INTR_TEST] & R_INTR_TEST_ERROR_MASK) {
+        if (FIELD_EX32(intr_test_reg, INTR_TEST,  ERROR)) {
             err_irq = 1;
-        } else if ((s->regs[IBEX_SPI_HOST_ERROR_ENABLE]
-                    &  R_ERROR_ENABLE_CMDBUSY_MASK) &&
-                    s->regs[IBEX_SPI_HOST_ERROR_STATUS]
-                    & R_ERROR_STATUS_CMDBUSY_MASK) {
+        } else if (FIELD_EX32(err_en_reg, ERROR_ENABLE,  CMDBUSY) &&
+                   FIELD_EX32(err_status_reg, ERROR_STATUS,  CMDBUSY)) {
             /* Wrote to COMMAND when not READY */
             err_irq = 1;
-        } else if ((s->regs[IBEX_SPI_HOST_ERROR_ENABLE]
-                    &  R_ERROR_ENABLE_CMDINVAL_MASK) &&
-                    s->regs[IBEX_SPI_HOST_ERROR_STATUS]
-                    & R_ERROR_STATUS_CMDINVAL_MASK) {
+        } else if (FIELD_EX32(err_en_reg, ERROR_ENABLE,  CMDINVAL)  &&
+                   FIELD_EX32(err_status_reg, ERROR_STATUS,  CMDINVAL)) {
             /* Invalid command segment */
             err_irq = 1;
-        } else if ((s->regs[IBEX_SPI_HOST_ERROR_ENABLE]
-                    & R_ERROR_ENABLE_CSIDINVAL_MASK) &&
-                    s->regs[IBEX_SPI_HOST_ERROR_STATUS]
-                    & R_ERROR_STATUS_CSIDINVAL_MASK) {
+        } else if (FIELD_EX32(err_en_reg, ERROR_ENABLE,  CSIDINVAL) &&
+                   FIELD_EX32(err_status_reg, ERROR_STATUS,  CSIDINVAL)) {
             /* Invalid value for CSID */
             err_irq = 1;
         }
@@ -XXX,XX +XXX,XX @@ static void ibex_spi_host_irq(IbexSPIHostState *s)
 
     /* Event IRQ Enabled and Event IRQ Cleared */
     if (event_en && !status_pending) {
-        if (s->regs[IBEX_SPI_HOST_INTR_TEST] & R_INTR_TEST_SPI_EVENT_MASK) {
+        if (FIELD_EX32(intr_test_reg, INTR_STATE,  SPI_EVENT)) {
             /* Event enabled, Interrupt Test Event */
             event_irq = 1;
-        } else if ((s->regs[IBEX_SPI_HOST_EVENT_ENABLE]
-                    & R_EVENT_ENABLE_READY_MASK) &&
-                    (s->regs[IBEX_SPI_HOST_STATUS] & R_STATUS_READY_MASK)) {
+        } else if (FIELD_EX32(event_en_reg, EVENT_ENABLE,  READY) &&
+                   FIELD_EX32(status_reg, STATUS, READY)) {
             /* SPI Host ready for next command */
             event_irq = 1;
-        } else if ((s->regs[IBEX_SPI_HOST_EVENT_ENABLE]
-                    & R_EVENT_ENABLE_TXEMPTY_MASK) &&
-                    (s->regs[IBEX_SPI_HOST_STATUS] & R_STATUS_TXEMPTY_MASK)) {
+        } else if (FIELD_EX32(event_en_reg, EVENT_ENABLE,  TXEMPTY) &&
+                   FIELD_EX32(status_reg, STATUS,  TXEMPTY)) {
             /* SPI TXEMPTY, TXFIFO drained */
             event_irq = 1;
-        } else if ((s->regs[IBEX_SPI_HOST_EVENT_ENABLE]
-                    & R_EVENT_ENABLE_RXFULL_MASK) &&
-                    (s->regs[IBEX_SPI_HOST_STATUS] & R_STATUS_RXFULL_MASK)) {
+        } else if (FIELD_EX32(event_en_reg, EVENT_ENABLE,  RXFULL) &&
+                   FIELD_EX32(status_reg, STATUS,  RXFULL)) {
             /* SPI RXFULL, RXFIFO  full */
             event_irq = 1;
         }
@@ -XXX,XX +XXX,XX @@ static void ibex_spi_host_irq(IbexSPIHostState *s)
 
 static void ibex_spi_host_transfer(IbexSPIHostState *s)
 {
-    uint32_t rx, tx;
+    uint32_t rx, tx, data;
     /* Get num of one byte transfers */
-    uint8_t segment_len = ((s->regs[IBEX_SPI_HOST_COMMAND] & R_COMMAND_LEN_MASK)
-                          >> R_COMMAND_LEN_SHIFT);
+    uint8_t segment_len = FIELD_EX32(s->regs[IBEX_SPI_HOST_COMMAND],
+                                     COMMAND,  LEN);
+
     while (segment_len > 0) {
         if (fifo8_is_empty(&s->tx_fifo)) {
             /* Assert Stall */
@@ -XXX,XX +XXX,XX @@ static void ibex_spi_host_transfer(IbexSPIHostState *s)
         --segment_len;
     }
 
+    data = s->regs[IBEX_SPI_HOST_STATUS];
     /* Assert Ready */
-    s->regs[IBEX_SPI_HOST_STATUS] |= R_STATUS_READY_MASK;
+    data = FIELD_DP32(data, STATUS, READY, 1);
     /* Set RXQD */
-    s->regs[IBEX_SPI_HOST_STATUS] &= ~R_STATUS_RXQD_MASK;
-    s->regs[IBEX_SPI_HOST_STATUS] |= (R_STATUS_RXQD_MASK
-                                    & div4_round_up(segment_len));
+    data = FIELD_DP32(data, STATUS, RXQD, div4_round_up(segment_len));
     /* Set TXQD */
-    s->regs[IBEX_SPI_HOST_STATUS] &= ~R_STATUS_TXQD_MASK;
-    s->regs[IBEX_SPI_HOST_STATUS] |= (fifo8_num_used(&s->tx_fifo) / 4)
-                                    & R_STATUS_TXQD_MASK;
+    data = FIELD_DP32(data, STATUS, TXQD, fifo8_num_used(&s->tx_fifo) / 4);
     /* Clear TXFULL */
-    s->regs[IBEX_SPI_HOST_STATUS] &= ~R_STATUS_TXFULL_MASK;
-    /* Assert TXEMPTY and drop remaining bytes that exceed segment_len */
-    ibex_spi_txfifo_reset(s);
+    data = FIELD_DP32(data, STATUS, TXFULL, 0);
     /* Reset RXEMPTY */
-    s->regs[IBEX_SPI_HOST_STATUS] &= ~R_STATUS_RXEMPTY_MASK;
+    data = FIELD_DP32(data, STATUS, RXEMPTY, 0);
+    /* Update register status */
+    s->regs[IBEX_SPI_HOST_STATUS] = data;
+    /* Drop remaining bytes that exceed segment_len */
+    ibex_spi_txfifo_reset(s);
 
     ibex_spi_host_irq(s);
 }
@@ -XXX,XX +XXX,XX @@ static void ibex_spi_host_write(void *opaque, hwaddr addr,
 {
     IbexSPIHostState *s = opaque;
     uint32_t val32 = val64;
-    uint32_t shift_mask = 0xff;
+    uint32_t shift_mask = 0xff, status = 0;
     uint8_t txqd_len;
 
     trace_ibex_spi_host_write(addr, size, val64);
@@ -XXX,XX +XXX,XX @@ static void ibex_spi_host_write(void *opaque, hwaddr addr,
         s->regs[addr] = val32;
 
         /* STALL, IP not enabled */
-        if (!(s->regs[IBEX_SPI_HOST_CONTROL] & R_CONTROL_SPIEN_MASK)) {
+        if (!(FIELD_EX32(s->regs[IBEX_SPI_HOST_CONTROL],
+                         CONTROL, SPIEN))) {
             return;
         }
 
         /* SPI not ready, IRQ Error */
-        if (!(s->regs[IBEX_SPI_HOST_STATUS] & R_STATUS_READY_MASK)) {
+        if (!(FIELD_EX32(s->regs[IBEX_SPI_HOST_STATUS],
+                         STATUS, READY))) {
             s->regs[IBEX_SPI_HOST_ERROR_STATUS] |= R_ERROR_STATUS_CMDBUSY_MASK;
             ibex_spi_host_irq(s);
             return;
         }
+
         /* Assert Not Ready */
         s->regs[IBEX_SPI_HOST_STATUS] &= ~R_STATUS_READY_MASK;
 
-        if (((val32 & R_COMMAND_DIRECTION_MASK) >> R_COMMAND_DIRECTION_SHIFT)
-            != BIDIRECTIONAL_TRANSFER) {
-                qemu_log_mask(LOG_UNIMP,
+        if (FIELD_EX32(val32, COMMAND, DIRECTION) != BIDIRECTIONAL_TRANSFER) {
+            qemu_log_mask(LOG_UNIMP,
                           "%s: Rx Only/Tx Only are not supported\n", __func__);
         }
 
@@ -XXX,XX +XXX,XX @@ static void ibex_spi_host_write(void *opaque, hwaddr addr,
                 return;
             }
             /* Byte ordering is set by the IP */
-            if ((s->regs[IBEX_SPI_HOST_STATUS] &
-                R_STATUS_BYTEORDER_MASK) == 0) {
+            status = s->regs[IBEX_SPI_HOST_STATUS];
+            if (FIELD_EX32(status, STATUS, BYTEORDER) == 0) {
                 /* LE: LSB transmitted first (default for ibex processor) */
                 shift_mask = 0xff << (i * 8);
             } else {
@@ -XXX,XX +XXX,XX @@ static void ibex_spi_host_write(void *opaque, hwaddr addr,
 
             fifo8_push(&s->tx_fifo, (val32 & shift_mask) >> (i * 8));
         }
-
+        status = s->regs[IBEX_SPI_HOST_STATUS];
         /* Reset TXEMPTY */
-        s->regs[IBEX_SPI_HOST_STATUS] &= ~R_STATUS_TXEMPTY_MASK;
+        status = FIELD_DP32(status, STATUS, TXEMPTY, 0);
         /* Update TXQD */
-        txqd_len = (s->regs[IBEX_SPI_HOST_STATUS] &
-                    R_STATUS_TXQD_MASK) >> R_STATUS_TXQD_SHIFT;
+        txqd_len = FIELD_EX32(status, STATUS, TXQD);
         /* Partial bytes (size < 4) are padded, in words. */
         txqd_len += 1;
-        s->regs[IBEX_SPI_HOST_STATUS] &= ~R_STATUS_TXQD_MASK;
-        s->regs[IBEX_SPI_HOST_STATUS] |= txqd_len;
+        status = FIELD_DP32(status, STATUS, TXQD, txqd_len);
         /* Assert Ready */
-        s->regs[IBEX_SPI_HOST_STATUS] |= R_STATUS_READY_MASK;
+        status = FIELD_DP32(status, STATUS, READY, 1);
+        /* Update register status */
+        s->regs[IBEX_SPI_HOST_STATUS] = status;
         break;
     case IBEX_SPI_HOST_ERROR_ENABLE:
         s->regs[addr] = val32;
-- 
2.37.3

From: Wilfred Mallawa <wilfred.mallawa@wdc.com>

This patch adds the `rw1c` functionality to the respective
registers. The status fields are cleared when the respective
field is set.

Signed-off-by: Wilfred Mallawa <wilfred.mallawa@wdc.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20220930033241.206581-3-wilfred.mallawa@opensource.wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 include/hw/ssi/ibex_spi_host.h |  4 ++--
 hw/ssi/ibex_spi_host.c         | 36 +++++++++++++++++++++++++++++++---
 2 files changed, 35 insertions(+), 5 deletions(-)

diff --git a/include/hw/ssi/ibex_spi_host.h b/include/hw/ssi/ibex_spi_host.h
index XXXXXXX..XXXXXXX 100644
--- a/include/hw/ssi/ibex_spi_host.h
+++ b/include/hw/ssi/ibex_spi_host.h
@@ -XXX,XX +XXX,XX @@
     OBJECT_CHECK(IbexSPIHostState, (obj), TYPE_IBEX_SPI_HOST)
 
 /* SPI Registers */
-#define IBEX_SPI_HOST_INTR_STATE         (0x00 / 4)  /* rw */
+#define IBEX_SPI_HOST_INTR_STATE         (0x00 / 4)  /* rw1c */
 #define IBEX_SPI_HOST_INTR_ENABLE        (0x04 / 4)  /* rw */
 #define IBEX_SPI_HOST_INTR_TEST          (0x08 / 4)  /* wo */
 #define IBEX_SPI_HOST_ALERT_TEST         (0x0c / 4)  /* wo */
@@ -XXX,XX +XXX,XX @@
 #define IBEX_SPI_HOST_TXDATA             (0x28 / 4)
 
 #define IBEX_SPI_HOST_ERROR_ENABLE       (0x2c / 4)  /* rw */
-#define IBEX_SPI_HOST_ERROR_STATUS       (0x30 / 4)  /* rw */
+#define IBEX_SPI_HOST_ERROR_STATUS       (0x30 / 4)  /* rw1c */
 #define IBEX_SPI_HOST_EVENT_ENABLE       (0x34 / 4)  /* rw */
 
 /* FIFO Len in Bytes */
diff --git a/hw/ssi/ibex_spi_host.c b/hw/ssi/ibex_spi_host.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/ssi/ibex_spi_host.c
+++ b/hw/ssi/ibex_spi_host.c
@@ -XXX,XX +XXX,XX @@ static void ibex_spi_host_write(void *opaque, hwaddr addr,
 {
     IbexSPIHostState *s = opaque;
     uint32_t val32 = val64;
-    uint32_t shift_mask = 0xff, status = 0;
+    uint32_t shift_mask = 0xff, status = 0, data = 0;
     uint8_t txqd_len;
 
     trace_ibex_spi_host_write(addr, size, val64);
@@ -XXX,XX +XXX,XX @@ static void ibex_spi_host_write(void *opaque, hwaddr addr,
 
     switch (addr) {
     /* Skipping any R/O registers */
-    case IBEX_SPI_HOST_INTR_STATE...IBEX_SPI_HOST_INTR_ENABLE:
+    case IBEX_SPI_HOST_INTR_STATE:
+        /* rw1c status register */
+        if (FIELD_EX32(val32, INTR_STATE, ERROR)) {
+            data = FIELD_DP32(data, INTR_STATE, ERROR, 0);
+        }
+        if (FIELD_EX32(val32, INTR_STATE, SPI_EVENT)) {
+            data = FIELD_DP32(data, INTR_STATE, SPI_EVENT, 0);
+        }
+        s->regs[addr] = data;
+        break;
+    case IBEX_SPI_HOST_INTR_ENABLE:
         s->regs[addr] = val32;
         break;
     case IBEX_SPI_HOST_INTR_TEST:
@@ -XXX,XX +XXX,XX @@ static void ibex_spi_host_write(void *opaque, hwaddr addr,
      *  When an error occurs, the corresponding bit must be cleared
      *  here before issuing any further commands
      */
-        s->regs[addr] = val32;
+        status = s->regs[addr];
+        /* rw1c status register */
+        if (FIELD_EX32(val32, ERROR_STATUS, CMDBUSY)) {
+            status = FIELD_DP32(status, ERROR_STATUS, CMDBUSY, 0);
+        }
+        if (FIELD_EX32(val32, ERROR_STATUS, OVERFLOW)) {
+            status = FIELD_DP32(status, ERROR_STATUS, OVERFLOW, 0);
+        }
+        if (FIELD_EX32(val32, ERROR_STATUS, UNDERFLOW)) {
+            status = FIELD_DP32(status, ERROR_STATUS, UNDERFLOW, 0);
+        }
+        if (FIELD_EX32(val32, ERROR_STATUS, CMDINVAL)) {
+            status = FIELD_DP32(status, ERROR_STATUS, CMDINVAL, 0);
+        }
+        if (FIELD_EX32(val32, ERROR_STATUS, CSIDINVAL)) {
+            status = FIELD_DP32(status, ERROR_STATUS, CSIDINVAL, 0);
+        }
+        if (FIELD_EX32(val32, ERROR_STATUS, ACCESSINVAL)) {
+            status = FIELD_DP32(status, ERROR_STATUS, ACCESSINVAL, 0);
+        }
+        s->regs[addr] = status;
         break;
     case IBEX_SPI_HOST_EVENT_ENABLE:
     /* Controls which classes of SPI events raise an interrupt. */
-- 
2.37.3

From: Sunil V L <sunilvl@ventanamicro.com>

load_image_to_fw_cfg() is duplicated by both arm and loongarch. The same
function will be required by riscv too. So, it's time to refactor and
move this function to a common path.

Signed-off-by: Sunil V L <sunilvl@ventanamicro.com>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Song Gao <gaosong@loongson.cn>
Message-Id: <20221004092351.18209-2-sunilvl@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 include/hw/nvram/fw_cfg.h | 21 +++++++++++++++++
 hw/arm/boot.c             | 49 ---------------------------------------
 hw/loongarch/virt.c       | 33 --------------------------
 hw/nvram/fw_cfg.c         | 32 +++++++++++++++++++++++++
 4 files changed, 53 insertions(+), 82 deletions(-)

diff --git a/include/hw/nvram/fw_cfg.h b/include/hw/nvram/fw_cfg.h
index XXXXXXX..XXXXXXX 100644
--- a/include/hw/nvram/fw_cfg.h
+++ b/include/hw/nvram/fw_cfg.h
@@ -XXX,XX +XXX,XX @@ bool fw_cfg_dma_enabled(void *opaque);
  */
 const char *fw_cfg_arch_key_name(uint16_t key);
 
+/**
+ * load_image_to_fw_cfg() - Load an image file into an fw_cfg entry identified
+ *                          by key.
+ * @fw_cfg:         The firmware config instance to store the data in.
+ * @size_key:       The firmware config key to store the size of the loaded
+ *                  data under, with fw_cfg_add_i32().
+ * @data_key:       The firmware config key to store the loaded data under,
+ *                  with fw_cfg_add_bytes().
+ * @image_name:     The name of the image file to load. If it is NULL, the
+ *                  function returns without doing anything.
+ * @try_decompress: Whether the image should be decompressed (gunzipped) before
+ *                  adding it to fw_cfg. If decompression fails, the image is
+ *                  loaded as-is.
+ *
+ * In case of failure, the function prints an error message to stderr and the
+ * process exits with status 1.
+ */
+void load_image_to_fw_cfg(FWCfgState *fw_cfg, uint16_t size_key,
+                          uint16_t data_key, const char *image_name,
+                          bool try_decompress);
+
 #endif
diff --git a/hw/arm/boot.c b/hw/arm/boot.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/boot.c
+++ b/hw/arm/boot.c
@@ -XXX,XX +XXX,XX @@ static void do_cpu_reset(void *opaque)
     }
 }
 
-/**
- * load_image_to_fw_cfg() - Load an image file into an fw_cfg entry identified
- *                          by key.
- * @fw_cfg:         The firmware config instance to store the data in.
- * @size_key:       The firmware config key to store the size of the loaded
- *                  data under, with fw_cfg_add_i32().
- * @data_key:       The firmware config key to store the loaded data under,
- *                  with fw_cfg_add_bytes().
- * @image_name:     The name of the image file to load. If it is NULL, the
- *                  function returns without doing anything.
- * @try_decompress: Whether the image should be decompressed (gunzipped) before
- *                  adding it to fw_cfg. If decompression fails, the image is
- *                  loaded as-is.
- *
- * In case of failure, the function prints an error message to stderr and the
- * process exits with status 1.
- */
-static void load_image_to_fw_cfg(FWCfgState *fw_cfg, uint16_t size_key,
-                                 uint16_t data_key, const char *image_name,
-                                 bool try_decompress)
-{
-    size_t size = -1;
-    uint8_t *data;
-
-    if (image_name == NULL) {
-        return;
-    }
-
-    if (try_decompress) {
-        size = load_image_gzipped_buffer(image_name,
-                                         LOAD_IMAGE_MAX_GUNZIP_BYTES, &data);
-    }
-
-    if (size == (size_t)-1) {
-        gchar *contents;
-        gsize length;
-
-        if (!g_file_get_contents(image_name, &contents, &length, NULL)) {
-            error_report("failed to load \"%s\"", image_name);
-            exit(1);
-        }
-        size = length;
-        data = (uint8_t *)contents;
-    }
-
-    fw_cfg_add_i32(fw_cfg, size_key, size);
-    fw_cfg_add_bytes(fw_cfg, data_key, data, size);
-}
-
 static int do_arm_linux_init(Object *obj, void *opaque)
 {
     if (object_dynamic_cast(obj, TYPE_ARM_LINUX_BOOT_IF)) {
diff --git a/hw/loongarch/virt.c b/hw/loongarch/virt.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/loongarch/virt.c
+++ b/hw/loongarch/virt.c
@@ -XXX,XX +XXX,XX @@ static void reset_load_elf(void *opaque)
     }
 }
 
-/* Load an image file into an fw_cfg entry identified by key. */
-static void load_image_to_fw_cfg(FWCfgState *fw_cfg, uint16_t size_key,
-                                 uint16_t data_key, const char *image_name,
-                                 bool try_decompress)
-{
-    size_t size = -1;
-    uint8_t *data;
-
-    if (image_name == NULL) {
-        return;
-    }
-
-    if (try_decompress) {
-        size = load_image_gzipped_buffer(image_name,
-                                         LOAD_IMAGE_MAX_GUNZIP_BYTES, &data);
-    }
-
-    if (size == (size_t)-1) {
-        gchar *contents;
-        gsize length;
-
-        if (!g_file_get_contents(image_name, &contents, &length, NULL)) {
-            error_report("failed to load \"%s\"", image_name);
-            exit(1);
-        }
-        size = length;
-        data = (uint8_t *)contents;
-    }
-
-    fw_cfg_add_i32(fw_cfg, size_key, size);
-    fw_cfg_add_bytes(fw_cfg, data_key, data, size);
-}
-
 static void fw_cfg_add_kernel_info(FWCfgState *fw_cfg)
 {
     /*
diff --git a/hw/nvram/fw_cfg.c b/hw/nvram/fw_cfg.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/nvram/fw_cfg.c
+++ b/hw/nvram/fw_cfg.c
@@ -XXX,XX +XXX,XX @@
 #include "qapi/error.h"
 #include "hw/acpi/aml-build.h"
 #include "hw/pci/pci_bus.h"
+#include "hw/loader.h"
 
 #define FW_CFG_FILE_SLOTS_DFLT 0x20
 
@@ -XXX,XX +XXX,XX @@ FWCfgState *fw_cfg_find(void)
     return FW_CFG(object_resolve_path_type("", TYPE_FW_CFG, NULL));
 }
 
+void load_image_to_fw_cfg(FWCfgState *fw_cfg, uint16_t size_key,
+                          uint16_t data_key, const char *image_name,
+                          bool try_decompress)
+{
+    size_t size = -1;
+    uint8_t *data;
+
+    if (image_name == NULL) {
+        return;
+    }
+
+    if (try_decompress) {
+        size = load_image_gzipped_buffer(image_name,
+                                         LOAD_IMAGE_MAX_GUNZIP_BYTES, &data);
+    }
+
+    if (size == (size_t)-1) {
+        gchar *contents;
+        gsize length;
+
+        if (!g_file_get_contents(image_name, &contents, &length, NULL)) {
+            error_report("failed to load \"%s\"", image_name);
+            exit(1);
+        }
+        size = length;
+        data = (uint8_t *)contents;
+    }
+
+    fw_cfg_add_i32(fw_cfg, size_key, size);
+    fw_cfg_add_bytes(fw_cfg, data_key, data, size);
+}
 
 static void fw_cfg_class_init(ObjectClass *klass, void *data)
 {
-- 
2.37.3

From: Sunil V L <sunilvl@ventanamicro.com>

To enable both -kernel and -pflash options, the fw_cfg needs to be
created prior to loading the kernel.

Signed-off-by: Sunil V L <sunilvl@ventanamicro.com>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20221004092351.18209-3-sunilvl@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 hw/riscv/virt.c | 14 +++++++-------
 1 file changed, 7 insertions(+), 7 deletions(-)

diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/riscv/virt.c
+++ b/hw/riscv/virt.c
@@ -XXX,XX +XXX,XX @@ static void virt_machine_done(Notifier *notifier, void *data)
                                     RISCV64_BIOS_BIN, start_addr, NULL);
     }
 
+    /*
+     * Init fw_cfg.  Must be done before riscv_load_fdt, otherwise the device
+     * tree cannot be altered and we get FDT_ERR_NOSPACE.
+     */
+    s->fw_cfg = create_fw_cfg(machine);
+    rom_set_fw(s->fw_cfg);
+
     if (machine->kernel_filename) {
         kernel_start_addr = riscv_calc_kernel_start_addr(&s->soc[0],
                                                          firmware_end_addr);
@@ -XXX,XX +XXX,XX @@ static void virt_machine_done(Notifier *notifier, void *data)
         start_addr = virt_memmap[VIRT_FLASH].base;
     }
 
-    /*
-     * Init fw_cfg.  Must be done before riscv_load_fdt, otherwise the device
-     * tree cannot be altered and we get FDT_ERR_NOSPACE.
-     */
-    s->fw_cfg = create_fw_cfg(machine);
-    rom_set_fw(s->fw_cfg);
-
     /* Compute the fdt load address in dram */
     fdt_load_addr = riscv_load_fdt(memmap[VIRT_DRAM].base,
                                    machine->ram_size, machine->fdt);
-- 
2.37.3

From: Sunil V L <sunilvl@ventanamicro.com>

To boot S-mode firmware payload like EDK2 from persistent
flash storage, qemu needs to pass the flash address as the
next_addr in fw_dynamic_info to the opensbi.

When both -kernel and -pflash options are provided in command line,
the kernel (and initrd if -initrd) will be copied to fw_cfg table.
The S-mode FW will load the kernel/initrd from fw_cfg table.

If only pflash is given but not -kernel, then it is the job of
of the S-mode firmware to locate and load the kernel.

In either case, update the kernel_entry with the flash address
so that the opensbi can jump to the entry point of the S-mode
firmware.

Signed-off-by: Sunil V L <sunilvl@ventanamicro.com>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20221004092351.18209-4-sunilvl@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 include/hw/riscv/boot.h |  1 +
 hw/riscv/boot.c         | 29 +++++++++++++++++++++++++++++
 hw/riscv/virt.c         | 18 +++++++++++++++++-
 3 files changed, 47 insertions(+), 1 deletion(-)

diff --git a/include/hw/riscv/boot.h b/include/hw/riscv/boot.h
index XXXXXXX..XXXXXXX 100644
--- a/include/hw/riscv/boot.h
+++ b/include/hw/riscv/boot.h
@@ -XXX,XX +XXX,XX @@ void riscv_rom_copy_firmware_info(MachineState *machine, hwaddr rom_base,
                                   uint32_t reset_vec_size,
                                   uint64_t kernel_entry);
 void riscv_setup_direct_kernel(hwaddr kernel_addr, hwaddr fdt_addr);
+void riscv_setup_firmware_boot(MachineState *machine);
 
 #endif /* RISCV_BOOT_H */
diff --git a/hw/riscv/boot.c b/hw/riscv/boot.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/riscv/boot.c
+++ b/hw/riscv/boot.c
@@ -XXX,XX +XXX,XX @@ void riscv_setup_direct_kernel(hwaddr kernel_addr, hwaddr fdt_addr)
         riscv_cpu->env.fdt_addr = fdt_addr;
     }
 }
+
+void riscv_setup_firmware_boot(MachineState *machine)
+{
+    if (machine->kernel_filename) {
+        FWCfgState *fw_cfg;
+        fw_cfg = fw_cfg_find();
+
+        assert(fw_cfg);
+        /*
+         * Expose the kernel, the command line, and the initrd in fw_cfg.
+         * We don't process them here at all, it's all left to the
+         * firmware.
+         */
+        load_image_to_fw_cfg(fw_cfg,
+                             FW_CFG_KERNEL_SIZE, FW_CFG_KERNEL_DATA,
+                             machine->kernel_filename,
+                             true);
+        load_image_to_fw_cfg(fw_cfg,
+                             FW_CFG_INITRD_SIZE, FW_CFG_INITRD_DATA,
+                             machine->initrd_filename, false);
+
+        if (machine->kernel_cmdline) {
+            fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_SIZE,
+                           strlen(machine->kernel_cmdline) + 1);
+            fw_cfg_add_string(fw_cfg, FW_CFG_CMDLINE_DATA,
+                              machine->kernel_cmdline);
+        }
+    }
+}
diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/riscv/virt.c
+++ b/hw/riscv/virt.c
@@ -XXX,XX +XXX,XX @@ static void virt_machine_done(Notifier *notifier, void *data)
     s->fw_cfg = create_fw_cfg(machine);
     rom_set_fw(s->fw_cfg);
 
-    if (machine->kernel_filename) {
+    if (drive_get(IF_PFLASH, 0, 1)) {
+        /*
+         * S-mode FW like EDK2 will be kept in second plash (unit 1).
+         * When both kernel, initrd and pflash options are provided in the
+         * command line, the kernel and initrd will be copied to the fw_cfg
+         * table and opensbi will jump to the flash address which is the
+         * entry point of S-mode FW. It is the job of the S-mode FW to load
+         * the kernel and initrd using fw_cfg table.
+         *
+         * If only pflash is given but not -kernel, then it is the job of
+         * of the S-mode firmware to locate and load the kernel.
+         * In either case, the next_addr for opensbi will be the flash address.
+         */
+        riscv_setup_firmware_boot(machine);
+        kernel_entry = virt_memmap[VIRT_FLASH].base +
+                       virt_memmap[VIRT_FLASH].size / 2;
+    } else if (machine->kernel_filename) {
         kernel_start_addr = riscv_calc_kernel_start_addr(&s->soc[0],
                                                          firmware_end_addr);
 
-- 
2.37.3

From: Yang Liu <liuyang22@iscas.ac.cn>

Tested with https://github.com/ksco/rvv-decoder-tests

Expected checkpatch errors for consistency and brevity reasons:

ERROR: line over 90 characters
ERROR: trailing statements should be on next line
ERROR: braces {} are necessary for all arms of this statement

Signed-off-by: Yang Liu <liuyang22@iscas.ac.cn>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20220928051842.16207-1-liuyang22@iscas.ac.cn>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 disas/riscv.c | 1432 ++++++++++++++++++++++++++++++++++++++++++++++++-
 1 file changed, 1430 insertions(+), 2 deletions(-)

diff --git a/disas/riscv.c b/disas/riscv.c
index XXXXXXX..XXXXXXX 100644
--- a/disas/riscv.c
+++ b/disas/riscv.c
@@ -XXX,XX +XXX,XX @@ typedef enum {
     rv_codec_css_sqsp,
     rv_codec_k_bs,
     rv_codec_k_rnum,
+    rv_codec_v_r,
+    rv_codec_v_ldst,
+    rv_codec_v_i,
+    rv_codec_vsetvli,
+    rv_codec_vsetivli,
 } rv_codec;
 
 typedef enum {
@@ -XXX,XX +XXX,XX @@ typedef enum {
     rv_op_zip = 396,
     rv_op_xperm4 = 397,
     rv_op_xperm8 = 398,
+    rv_op_vle8_v = 399,
+    rv_op_vle16_v = 400,
+    rv_op_vle32_v = 401,
+    rv_op_vle64_v = 402,
+    rv_op_vse8_v = 403,
+    rv_op_vse16_v = 404,
+    rv_op_vse32_v = 405,
+    rv_op_vse64_v = 406,
+    rv_op_vlm_v = 407,
+    rv_op_vsm_v = 408,
+    rv_op_vlse8_v = 409,
+    rv_op_vlse16_v = 410,
+    rv_op_vlse32_v = 411,
+    rv_op_vlse64_v = 412,
+    rv_op_vsse8_v = 413,
+    rv_op_vsse16_v = 414,
+    rv_op_vsse32_v = 415,
+    rv_op_vsse64_v = 416,
+    rv_op_vluxei8_v = 417,
+    rv_op_vluxei16_v = 418,
+    rv_op_vluxei32_v = 419,
+    rv_op_vluxei64_v = 420,
+    rv_op_vloxei8_v = 421,
+    rv_op_vloxei16_v = 422,
+    rv_op_vloxei32_v = 423,
+    rv_op_vloxei64_v = 424,
+    rv_op_vsuxei8_v = 425,
+    rv_op_vsuxei16_v = 426,
+    rv_op_vsuxei32_v = 427,
+    rv_op_vsuxei64_v = 428,
+    rv_op_vsoxei8_v = 429,
+    rv_op_vsoxei16_v = 430,
+    rv_op_vsoxei32_v = 431,
+    rv_op_vsoxei64_v = 432,
+    rv_op_vle8ff_v = 433,
+    rv_op_vle16ff_v = 434,
+    rv_op_vle32ff_v = 435,
+    rv_op_vle64ff_v = 436,
+    rv_op_vl1re8_v = 437,
+    rv_op_vl1re16_v = 438,
+    rv_op_vl1re32_v = 439,
+    rv_op_vl1re64_v = 440,
+    rv_op_vl2re8_v = 441,
+    rv_op_vl2re16_v = 442,
+    rv_op_vl2re32_v = 443,
+    rv_op_vl2re64_v = 444,
+    rv_op_vl4re8_v = 445,
+    rv_op_vl4re16_v = 446,
+    rv_op_vl4re32_v = 447,
+    rv_op_vl4re64_v = 448,
+    rv_op_vl8re8_v = 449,
+    rv_op_vl8re16_v = 450,
+    rv_op_vl8re32_v = 451,
+    rv_op_vl8re64_v = 452,
+    rv_op_vs1r_v = 453,
+    rv_op_vs2r_v = 454,
+    rv_op_vs4r_v = 455,
+    rv_op_vs8r_v = 456,
+    rv_op_vadd_vv = 457,
+    rv_op_vadd_vx = 458,
+    rv_op_vadd_vi = 459,
+    rv_op_vsub_vv = 460,
+    rv_op_vsub_vx = 461,
+    rv_op_vrsub_vx = 462,
+    rv_op_vrsub_vi = 463,
+    rv_op_vwaddu_vv = 464,
+    rv_op_vwaddu_vx = 465,
+    rv_op_vwadd_vv = 466,
+    rv_op_vwadd_vx = 467,
+    rv_op_vwsubu_vv = 468,
+    rv_op_vwsubu_vx = 469,
+    rv_op_vwsub_vv = 470,
+    rv_op_vwsub_vx = 471,
+    rv_op_vwaddu_wv = 472,
+    rv_op_vwaddu_wx = 473,
+    rv_op_vwadd_wv = 474,
+    rv_op_vwadd_wx = 475,
+    rv_op_vwsubu_wv = 476,
+    rv_op_vwsubu_wx = 477,
+    rv_op_vwsub_wv = 478,
+    rv_op_vwsub_wx = 479,
+    rv_op_vadc_vvm = 480,
+    rv_op_vadc_vxm = 481,
+    rv_op_vadc_vim = 482,
+    rv_op_vmadc_vvm = 483,
+    rv_op_vmadc_vxm = 484,
+    rv_op_vmadc_vim = 485,
+    rv_op_vsbc_vvm = 486,
+    rv_op_vsbc_vxm = 487,
+    rv_op_vmsbc_vvm = 488,
+    rv_op_vmsbc_vxm = 489,
+    rv_op_vand_vv = 490,
+    rv_op_vand_vx = 491,
+    rv_op_vand_vi = 492,
+    rv_op_vor_vv = 493,
+    rv_op_vor_vx = 494,
+    rv_op_vor_vi = 495,
+    rv_op_vxor_vv = 496,
+    rv_op_vxor_vx = 497,
+    rv_op_vxor_vi = 498,
+    rv_op_vsll_vv = 499,
+    rv_op_vsll_vx = 500,
+    rv_op_vsll_vi = 501,
+    rv_op_vsrl_vv = 502,
+    rv_op_vsrl_vx = 503,
+    rv_op_vsrl_vi = 504,
+    rv_op_vsra_vv = 505,
+    rv_op_vsra_vx = 506,
+    rv_op_vsra_vi = 507,
+    rv_op_vnsrl_wv = 508,
+    rv_op_vnsrl_wx = 509,
+    rv_op_vnsrl_wi = 510,
+    rv_op_vnsra_wv = 511,
+    rv_op_vnsra_wx = 512,
+    rv_op_vnsra_wi = 513,
+    rv_op_vmseq_vv = 514,
+    rv_op_vmseq_vx = 515,
+    rv_op_vmseq_vi = 516,
+    rv_op_vmsne_vv = 517,
+    rv_op_vmsne_vx = 518,
+    rv_op_vmsne_vi = 519,
+    rv_op_vmsltu_vv = 520,
+    rv_op_vmsltu_vx = 521,
+    rv_op_vmslt_vv = 522,
+    rv_op_vmslt_vx = 523,
+    rv_op_vmsleu_vv = 524,
+    rv_op_vmsleu_vx = 525,
+    rv_op_vmsleu_vi = 526,
+    rv_op_vmsle_vv = 527,
+    rv_op_vmsle_vx = 528,
+    rv_op_vmsle_vi = 529,
+    rv_op_vmsgtu_vx = 530,
+    rv_op_vmsgtu_vi = 531,
+    rv_op_vmsgt_vx = 532,
+    rv_op_vmsgt_vi = 533,
+    rv_op_vminu_vv = 534,
+    rv_op_vminu_vx = 535,
+    rv_op_vmin_vv = 536,
+    rv_op_vmin_vx = 537,
+    rv_op_vmaxu_vv = 538,
+    rv_op_vmaxu_vx = 539,
+    rv_op_vmax_vv = 540,
+    rv_op_vmax_vx = 541,
+    rv_op_vmul_vv = 542,
+    rv_op_vmul_vx = 543,
+    rv_op_vmulh_vv = 544,
+    rv_op_vmulh_vx = 545,
+    rv_op_vmulhu_vv = 546,
+    rv_op_vmulhu_vx = 547,
+    rv_op_vmulhsu_vv = 548,
+    rv_op_vmulhsu_vx = 549,
+    rv_op_vdivu_vv = 550,
+    rv_op_vdivu_vx = 551,
+    rv_op_vdiv_vv = 552,
+    rv_op_vdiv_vx = 553,
+    rv_op_vremu_vv = 554,
+    rv_op_vremu_vx = 555,
+    rv_op_vrem_vv = 556,
+    rv_op_vrem_vx = 557,
+    rv_op_vwmulu_vv = 558,
+    rv_op_vwmulu_vx = 559,
+    rv_op_vwmulsu_vv = 560,
+    rv_op_vwmulsu_vx = 561,
+    rv_op_vwmul_vv = 562,
+    rv_op_vwmul_vx = 563,
+    rv_op_vmacc_vv = 564,
+    rv_op_vmacc_vx = 565,
+    rv_op_vnmsac_vv = 566,
+    rv_op_vnmsac_vx = 567,
+    rv_op_vmadd_vv = 568,
+    rv_op_vmadd_vx = 569,
+    rv_op_vnmsub_vv = 570,
+    rv_op_vnmsub_vx = 571,
+    rv_op_vwmaccu_vv = 572,
+    rv_op_vwmaccu_vx = 573,
+    rv_op_vwmacc_vv = 574,
+    rv_op_vwmacc_vx = 575,
+    rv_op_vwmaccsu_vv = 576,
+    rv_op_vwmaccsu_vx = 577,
+    rv_op_vwmaccus_vx = 578,
+    rv_op_vmv_v_v = 579,
+    rv_op_vmv_v_x = 580,
+    rv_op_vmv_v_i = 581,
+    rv_op_vmerge_vvm = 582,
+    rv_op_vmerge_vxm = 583,
+    rv_op_vmerge_vim = 584,
+    rv_op_vsaddu_vv = 585,
+    rv_op_vsaddu_vx = 586,
+    rv_op_vsaddu_vi = 587,
+    rv_op_vsadd_vv = 588,
+    rv_op_vsadd_vx = 589,
+    rv_op_vsadd_vi = 590,
+    rv_op_vssubu_vv = 591,
+    rv_op_vssubu_vx = 592,
+    rv_op_vssub_vv = 593,
+    rv_op_vssub_vx = 594,
+    rv_op_vaadd_vv = 595,
+    rv_op_vaadd_vx = 596,
+    rv_op_vaaddu_vv = 597,
+    rv_op_vaaddu_vx = 598,
+    rv_op_vasub_vv = 599,
+    rv_op_vasub_vx = 600,
+    rv_op_vasubu_vv = 601,
+    rv_op_vasubu_vx = 602,
+    rv_op_vsmul_vv = 603,
+    rv_op_vsmul_vx = 604,
+    rv_op_vssrl_vv = 605,
+    rv_op_vssrl_vx = 606,
+    rv_op_vssrl_vi = 607,
+    rv_op_vssra_vv = 608,
+    rv_op_vssra_vx = 609,
+    rv_op_vssra_vi = 610,
+    rv_op_vnclipu_wv = 611,
+    rv_op_vnclipu_wx = 612,
+    rv_op_vnclipu_wi = 613,
+    rv_op_vnclip_wv = 614,
+    rv_op_vnclip_wx = 615,
+    rv_op_vnclip_wi = 616,
+    rv_op_vfadd_vv = 617,
+    rv_op_vfadd_vf = 618,
+    rv_op_vfsub_vv = 619,
+    rv_op_vfsub_vf = 620,
+    rv_op_vfrsub_vf = 621,
+    rv_op_vfwadd_vv = 622,
+    rv_op_vfwadd_vf = 623,
+    rv_op_vfwadd_wv = 624,
+    rv_op_vfwadd_wf = 625,
+    rv_op_vfwsub_vv = 626,
+    rv_op_vfwsub_vf = 627,
+    rv_op_vfwsub_wv = 628,
+    rv_op_vfwsub_wf = 629,
+    rv_op_vfmul_vv = 630,
+    rv_op_vfmul_vf = 631,
+    rv_op_vfdiv_vv = 632,
+    rv_op_vfdiv_vf = 633,
+    rv_op_vfrdiv_vf = 634,
+    rv_op_vfwmul_vv = 635,
+    rv_op_vfwmul_vf = 636,
+    rv_op_vfmacc_vv = 637,
+    rv_op_vfmacc_vf = 638,
+    rv_op_vfnmacc_vv = 639,
+    rv_op_vfnmacc_vf = 640,
+    rv_op_vfmsac_vv = 641,
+    rv_op_vfmsac_vf = 642,
+    rv_op_vfnmsac_vv = 643,
+    rv_op_vfnmsac_vf = 644,
+    rv_op_vfmadd_vv = 645,
+    rv_op_vfmadd_vf = 646,
+    rv_op_vfnmadd_vv = 647,
+    rv_op_vfnmadd_vf = 648,
+    rv_op_vfmsub_vv = 649,
+    rv_op_vfmsub_vf = 650,
+    rv_op_vfnmsub_vv = 651,
+    rv_op_vfnmsub_vf = 652,
+    rv_op_vfwmacc_vv = 653,
+    rv_op_vfwmacc_vf = 654,
+    rv_op_vfwnmacc_vv = 655,
+    rv_op_vfwnmacc_vf = 656,
+    rv_op_vfwmsac_vv = 657,
+    rv_op_vfwmsac_vf = 658,
+    rv_op_vfwnmsac_vv = 659,
+    rv_op_vfwnmsac_vf = 660,
+    rv_op_vfsqrt_v = 661,
+    rv_op_vfrsqrt7_v = 662,
+    rv_op_vfrec7_v = 663,
+    rv_op_vfmin_vv = 664,
+    rv_op_vfmin_vf = 665,
+    rv_op_vfmax_vv = 666,
+    rv_op_vfmax_vf = 667,
+    rv_op_vfsgnj_vv = 668,
+    rv_op_vfsgnj_vf = 669,
+    rv_op_vfsgnjn_vv = 670,
+    rv_op_vfsgnjn_vf = 671,
+    rv_op_vfsgnjx_vv = 672,
+    rv_op_vfsgnjx_vf = 673,
+    rv_op_vfslide1up_vf = 674,
+    rv_op_vfslide1down_vf = 675,
+    rv_op_vmfeq_vv = 676,
+    rv_op_vmfeq_vf = 677,
+    rv_op_vmfne_vv = 678,
+    rv_op_vmfne_vf = 679,
+    rv_op_vmflt_vv = 680,
+    rv_op_vmflt_vf = 681,
+    rv_op_vmfle_vv = 682,
+    rv_op_vmfle_vf = 683,
+    rv_op_vmfgt_vf = 684,
+    rv_op_vmfge_vf = 685,
+    rv_op_vfclass_v = 686,
+    rv_op_vfmerge_vfm = 687,
+    rv_op_vfmv_v_f = 688,
+    rv_op_vfcvt_xu_f_v = 689,
+    rv_op_vfcvt_x_f_v = 690,
+    rv_op_vfcvt_f_xu_v = 691,
+    rv_op_vfcvt_f_x_v = 692,
+    rv_op_vfcvt_rtz_xu_f_v = 693,
+    rv_op_vfcvt_rtz_x_f_v = 694,
+    rv_op_vfwcvt_xu_f_v = 695,
+    rv_op_vfwcvt_x_f_v = 696,
+    rv_op_vfwcvt_f_xu_v = 697,
+    rv_op_vfwcvt_f_x_v = 698,
+    rv_op_vfwcvt_f_f_v = 699,
+    rv_op_vfwcvt_rtz_xu_f_v = 700,
+    rv_op_vfwcvt_rtz_x_f_v = 701,
+    rv_op_vfncvt_xu_f_w = 702,
+    rv_op_vfncvt_x_f_w = 703,
+    rv_op_vfncvt_f_xu_w = 704,
+    rv_op_vfncvt_f_x_w = 705,
+    rv_op_vfncvt_f_f_w = 706,
+    rv_op_vfncvt_rod_f_f_w = 707,
+    rv_op_vfncvt_rtz_xu_f_w = 708,
+    rv_op_vfncvt_rtz_x_f_w = 709,
+    rv_op_vredsum_vs = 710,
+    rv_op_vredand_vs = 711,
+    rv_op_vredor_vs = 712,
+    rv_op_vredxor_vs = 713,
+    rv_op_vredminu_vs = 714,
+    rv_op_vredmin_vs = 715,
+    rv_op_vredmaxu_vs = 716,
+    rv_op_vredmax_vs = 717,
+    rv_op_vwredsumu_vs = 718,
+    rv_op_vwredsum_vs = 719,
+    rv_op_vfredusum_vs = 720,
+    rv_op_vfredosum_vs = 721,
+    rv_op_vfredmin_vs = 722,
+    rv_op_vfredmax_vs = 723,
+    rv_op_vfwredusum_vs = 724,
+    rv_op_vfwredosum_vs = 725,
+    rv_op_vmand_mm = 726,
+    rv_op_vmnand_mm = 727,
+    rv_op_vmandn_mm = 728,
+    rv_op_vmxor_mm = 729,
+    rv_op_vmor_mm = 730,
+    rv_op_vmnor_mm = 731,
+    rv_op_vmorn_mm = 732,
+    rv_op_vmxnor_mm = 733,
+    rv_op_vcpop_m = 734,
+    rv_op_vfirst_m = 735,
+    rv_op_vmsbf_m = 736,
+    rv_op_vmsif_m = 737,
+    rv_op_vmsof_m = 738,
+    rv_op_viota_m = 739,
+    rv_op_vid_v = 740,
+    rv_op_vmv_x_s = 741,
+    rv_op_vmv_s_x = 742,
+    rv_op_vfmv_f_s = 743,
+    rv_op_vfmv_s_f = 744,
+    rv_op_vslideup_vx = 745,
+    rv_op_vslideup_vi = 746,
+    rv_op_vslide1up_vx = 747,
+    rv_op_vslidedown_vx = 748,
+    rv_op_vslidedown_vi = 749,
+    rv_op_vslide1down_vx = 750,
+    rv_op_vrgather_vv = 751,
+    rv_op_vrgatherei16_vv = 752,
+    rv_op_vrgather_vx = 753,
+    rv_op_vrgather_vi = 754,
+    rv_op_vcompress_vm = 755,
+    rv_op_vmv1r_v = 756,
+    rv_op_vmv2r_v = 757,
+    rv_op_vmv4r_v = 758,
+    rv_op_vmv8r_v = 759,
+    rv_op_vzext_vf2 = 760,
+    rv_op_vzext_vf4 = 761,
+    rv_op_vzext_vf8 = 762,
+    rv_op_vsext_vf2 = 763,
+    rv_op_vsext_vf4 = 764,
+    rv_op_vsext_vf8 = 765,
+    rv_op_vsetvli = 766,
+    rv_op_vsetivli = 767,
+    rv_op_vsetvl = 768,
 } rv_op;
 
 /* structures */
@@ -XXX,XX +XXX,XX @@ typedef struct {
     uint8_t   rl;
     uint8_t   bs;
     uint8_t   rnum;
+    uint8_t   vm;
+    uint32_t  vzimm;
 } rv_decode;
 
 typedef struct {
@@ -XXX,XX +XXX,XX @@ static const char rv_freg_name_sym[32][5] = {
     "fs8",  "fs9",  "fs10", "fs11", "ft8",  "ft9",  "ft10", "ft11",
 };
 
+static const char rv_vreg_name_sym[32][4] = {
+    "v0",  "v1",  "v2",  "v3",  "v4",  "v5",  "v6",  "v7",
+    "v8",  "v9",  "v10", "v11", "v12", "v13", "v14", "v15",
+    "v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23",
+    "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31"
+};
+
 /* instruction formats */
 
 #define rv_fmt_none                   "O\t"
@@ -XXX,XX +XXX,XX @@ static const char rv_freg_name_sym[32][5] = {
 #define rv_fmt_rs2_offset             "O\t2,o"
 #define rv_fmt_rs1_rs2_bs             "O\t1,2,b"
 #define rv_fmt_rd_rs1_rnum            "O\t0,1,n"
+#define rv_fmt_ldst_vd_rs1_vm         "O\tD,(1)m"
+#define rv_fmt_ldst_vd_rs1_rs2_vm     "O\tD,(1),2m"
+#define rv_fmt_ldst_vd_rs1_vs2_vm     "O\tD,(1),Fm"
+#define rv_fmt_vd_vs2_vs1             "O\tD,F,E"
+#define rv_fmt_vd_vs2_vs1_vl          "O\tD,F,El"
+#define rv_fmt_vd_vs2_vs1_vm          "O\tD,F,Em"
+#define rv_fmt_vd_vs2_rs1_vl          "O\tD,F,1l"
+#define rv_fmt_vd_vs2_fs1_vl          "O\tD,F,4l"
+#define rv_fmt_vd_vs2_rs1_vm          "O\tD,F,1m"
+#define rv_fmt_vd_vs2_fs1_vm          "O\tD,F,4m"
+#define rv_fmt_vd_vs2_imm_vl          "O\tD,F,il"
+#define rv_fmt_vd_vs2_imm_vm          "O\tD,F,im"
+#define rv_fmt_vd_vs2_uimm_vm         "O\tD,F,um"
+#define rv_fmt_vd_vs1_vs2_vm          "O\tD,E,Fm"
+#define rv_fmt_vd_rs1_vs2_vm          "O\tD,1,Fm"
+#define rv_fmt_vd_fs1_vs2_vm          "O\tD,4,Fm"
+#define rv_fmt_vd_vs1                 "O\tD,E"
+#define rv_fmt_vd_rs1                 "O\tD,1"
+#define rv_fmt_vd_fs1                 "O\tD,4"
+#define rv_fmt_vd_imm                 "O\tD,i"
+#define rv_fmt_vd_vs2                 "O\tD,F"
+#define rv_fmt_vd_vs2_vm              "O\tD,Fm"
+#define rv_fmt_rd_vs2_vm              "O\t0,Fm"
+#define rv_fmt_rd_vs2                 "O\t0,F"
+#define rv_fmt_fd_vs2                 "O\t3,F"
+#define rv_fmt_vd_vm                  "O\tDm"
+#define rv_fmt_vsetvli                "O\t0,1,v"
+#define rv_fmt_vsetivli               "O\t0,u,v"
 
 /* pseudo-instruction constraints */
 
@@ -XXX,XX +XXX,XX @@ const rv_opcode_data opcode_data[] = {
     { "unzip", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
     { "zip", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
     { "xperm4", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
-    { "xperm8", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 }
+    { "xperm8", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
+    { "vle8.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, rv_op_vle8_v, rv_op_vle8_v, 0 },
+    { "vle16.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, rv_op_vle16_v, rv_op_vle16_v, 0 },
+    { "vle32.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, rv_op_vle32_v, rv_op_vle32_v, 0 },
+    { "vle64.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, rv_op_vle64_v, rv_op_vle64_v, 0 },
+    { "vse8.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, rv_op_vse8_v, rv_op_vse8_v, 0 },
+    { "vse16.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, rv_op_vse16_v, rv_op_vse16_v, 0 },
+    { "vse32.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, rv_op_vse32_v, rv_op_vse32_v, 0 },
+    { "vse64.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, rv_op_vse64_v, rv_op_vse64_v, 0 },
+    { "vlm.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, rv_op_vlm_v, rv_op_vlm_v, 0 },
+    { "vsm.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, rv_op_vsm_v, rv_op_vsm_v, 0 },
+    { "vlse8.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_rs2_vm, NULL, rv_op_vlse8_v, rv_op_vlse8_v, 0 },
+    { "vlse16.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_rs2_vm, NULL, rv_op_vlse16_v, rv_op_vlse16_v, 0 },
+    { "vlse32.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_rs2_vm, NULL, rv_op_vlse32_v, rv_op_vlse32_v, 0 },
+    { "vlse64.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_rs2_vm, NULL, rv_op_vlse64_v, rv_op_vlse64_v, 0 },
+    { "vsse8.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_rs2_vm, NULL, rv_op_vsse8_v, rv_op_vsse8_v, 0 },
+    { "vsse16.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_rs2_vm, NULL, rv_op_vsse16_v, rv_op_vsse16_v, 0 },
+    { "vsse32.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_rs2_vm, NULL, rv_op_vsse32_v, rv_op_vsse32_v, 0 },
+    { "vsse64.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_rs2_vm, NULL, rv_op_vsse64_v, rv_op_vsse64_v, 0 },
+    { "vluxei8.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_vs2_vm, NULL, rv_op_vluxei8_v, rv_op_vluxei8_v, 0 },
+    { "vluxei16.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_vs2_vm, NULL, rv_op_vluxei16_v, rv_op_vluxei16_v, 0 },
+    { "vluxei32.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_vs2_vm, NULL, rv_op_vluxei32_v, rv_op_vluxei32_v, 0 },
+    { "vluxei64.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_vs2_vm, NULL, rv_op_vluxei64_v, rv_op_vluxei64_v, 0 },
+    { "vloxei8.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_vs2_vm, NULL, rv_op_vloxei8_v, rv_op_vloxei8_v, 0 },
+    { "vloxei16.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_vs2_vm, NULL, rv_op_vloxei16_v, rv_op_vloxei16_v, 0 },
+    { "vloxei32.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_vs2_vm, NULL, rv_op_vloxei32_v, rv_op_vloxei32_v, 0 },
+    { "vloxei64.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_vs2_vm, NULL, rv_op_vloxei64_v, rv_op_vloxei64_v, 0 },
+    { "vsuxei8.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_vs2_vm, NULL, rv_op_vsuxei8_v, rv_op_vsuxei8_v, 0 },
+    { "vsuxei16.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_vs2_vm, NULL, rv_op_vsuxei16_v, rv_op_vsuxei16_v, 0 },
+    { "vsuxei32.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_vs2_vm, NULL, rv_op_vsuxei32_v, rv_op_vsuxei32_v, 0 },
+    { "vsuxei64.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_vs2_vm, NULL, rv_op_vsuxei64_v, rv_op_vsuxei64_v, 0 },
+    { "vsoxei8.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_vs2_vm, NULL, rv_op_vsoxei8_v, rv_op_vsoxei8_v, 0 },
+    { "vsoxei16.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_vs2_vm, NULL, rv_op_vsoxei16_v, rv_op_vsoxei16_v, 0 },
+    { "vsoxei32.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_vs2_vm, NULL, rv_op_vsoxei32_v, rv_op_vsoxei32_v, 0 },
+    { "vsoxei64.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_vs2_vm, NULL, rv_op_vsoxei64_v, rv_op_vsoxei64_v, 0 },
+    { "vle8ff.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, rv_op_vle8ff_v, rv_op_vle8ff_v, 0 },
+    { "vle16ff.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, rv_op_vle16ff_v, rv_op_vle16ff_v, 0 },
+    { "vle32ff.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, rv_op_vle32ff_v, rv_op_vle32ff_v, 0 },
+    { "vle64ff.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, rv_op_vle64ff_v, rv_op_vle64ff_v, 0 },
+    { "vl1re8.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, rv_op_vl1re8_v, rv_op_vl1re8_v, 0 },
+    { "vl1re16.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, rv_op_vl1re16_v, rv_op_vl1re16_v, 0 },
+    { "vl1re32.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, rv_op_vl1re32_v, rv_op_vl1re32_v, 0 },
+    { "vl1re64.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, rv_op_vl1re64_v, rv_op_vl1re64_v, 0 },
+    { "vl2re8.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, rv_op_vl2re8_v, rv_op_vl2re8_v, 0 },
+    { "vl2re16.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, rv_op_vl2re16_v, rv_op_vl2re16_v, 0 },
+    { "vl2re32.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, rv_op_vl2re32_v, rv_op_vl2re32_v, 0 },
+    { "vl2re64.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, rv_op_vl2re64_v, rv_op_vl2re64_v, 0 },
+    { "vl4re8.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, rv_op_vl4re8_v, rv_op_vl4re8_v, 0 },
+    { "vl4re16.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, rv_op_vl4re16_v, rv_op_vl4re16_v, 0 },
+    { "vl4re32.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, rv_op_vl4re32_v, rv_op_vl4re32_v, 0 },
+    { "vl4re64.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, rv_op_vl4re64_v, rv_op_vl4re64_v, 0 },
+    { "vl8re8.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, rv_op_vl8re8_v, rv_op_vl8re8_v, 0 },
+    { "vl8re16.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, rv_op_vl8re16_v, rv_op_vl8re16_v, 0 },
+    { "vl8re32.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, rv_op_vl8re32_v, rv_op_vl8re32_v, 0 },
+    { "vl8re64.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, rv_op_vl8re64_v, rv_op_vl8re64_v, 0 },
+    { "vs1r.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, rv_op_vs1r_v, rv_op_vs1r_v, 0 },
+    { "vs2r.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, rv_op_vs2r_v, rv_op_vs2r_v, 0 },
+    { "vs4r.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, rv_op_vs4r_v, rv_op_vs4r_v, 0 },
+    { "vs8r.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, rv_op_vs8r_v, rv_op_vs8r_v, 0 },
+    { "vadd.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vadd_vv, rv_op_vadd_vv, 0 },
+    { "vadd.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, rv_op_vadd_vx, rv_op_vadd_vx, 0 },
+    { "vadd.vi", rv_codec_v_i, rv_fmt_vd_vs2_imm_vm, NULL, rv_op_vadd_vi, rv_op_vadd_vi, 0 },
+    { "vsub.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vsub_vv, rv_op_vsub_vv, 0 },
+    { "vsub.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, rv_op_vsub_vx, rv_op_vsub_vx, 0 },
+    { "vrsub.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, rv_op_vrsub_vx, rv_op_vrsub_vx, 0 },
+    { "vrsub.vi", rv_codec_v_i, rv_fmt_vd_vs2_imm_vm, NULL, rv_op_vrsub_vi, rv_op_vrsub_vi, 0 },
+    { "vwaddu.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vwaddu_vv, rv_op_vwaddu_vv, 0 },
+    { "vwaddu.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, rv_op_vwaddu_vx, rv_op_vwaddu_vx, 0 },
+    { "vwadd.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vwadd_vv, rv_op_vwadd_vv, 0 },
+    { "vwadd.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, rv_op_vwadd_vx, rv_op_vwadd_vx, 0 },
+    { "vwsubu.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vwsubu_vv, rv_op_vwsubu_vv, 0 },
+    { "vwsubu.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, rv_op_vwsubu_vx, rv_op_vwsubu_vx, 0 },
+    { "vwsub.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vwsub_vv, rv_op_vwsub_vv, 0 },
+    { "vwsub.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, rv_op_vwsub_vx, rv_op_vwsub_vx, 0 },
+    { "vwaddu.wv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vwaddu_wv, rv_op_vwaddu_wv, 0 },
+    { "vwaddu.wx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, rv_op_vwaddu_wx, rv_op_vwaddu_wx, 0 },
+    { "vwadd.wv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vwadd_wv, rv_op_vwadd_wv, 0 },
+    { "vwadd.wx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, rv_op_vwadd_wx, rv_op_vwadd_wx, 0 },
+    { "vwsubu.wv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vwsubu_wv, rv_op_vwsubu_wv, 0 },
+    { "vwsubu.wx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, rv_op_vwsubu_wx, rv_op_vwsubu_wx, 0 },
+    { "vwsub.wv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vwsub_wv, rv_op_vwsub_wv, 0 },
+    { "vwsub.wx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, rv_op_vwsub_wx, rv_op_vwsub_wx, 0 },
+    { "vadc.vvm", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vl, NULL, rv_op_vadc_vvm, rv_op_vadc_vvm, 0 },
+    { "vadc.vxm", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vl, NULL, rv_op_vadc_vxm, rv_op_vadc_vxm, 0 },
+    { "vadc.vim", rv_codec_v_i, rv_fmt_vd_vs2_imm_vl, NULL, rv_op_vadc_vim, rv_op_vadc_vim, 0 },
+    { "vmadc.vvm", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vl, NULL, rv_op_vmadc_vvm, rv_op_vmadc_vvm, 0 },
+    { "vmadc.vxm", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vl, NULL, rv_op_vmadc_vxm, rv_op_vmadc_vxm, 0 },
+    { "vmadc.vim", rv_codec_v_i, rv_fmt_vd_vs2_imm_vl, NULL, rv_op_vmadc_vim, rv_op_vmadc_vim, 0 },
+    { "vsbc.vvm", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vl, NULL, rv_op_vsbc_vvm, rv_op_vsbc_vvm, 0 },
+    { "vsbc.vxm", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vl, NULL, rv_op_vsbc_vxm, rv_op_vsbc_vxm, 0 },
+    { "vmsbc.vvm", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vl, NULL, rv_op_vmsbc_vvm, rv_op_vmsbc_vvm, 0 },
+    { "vmsbc.vxm", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vl, NULL, rv_op_vmsbc_vxm, rv_op_vmsbc_vxm, 0 },
+    { "vand.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vand_vv, rv_op_vand_vv, 0 },
+    { "vand.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, rv_op_vand_vx, rv_op_vand_vx, 0 },
+    { "vand.vi", rv_codec_v_i, rv_fmt_vd_vs2_imm_vm, NULL, rv_op_vand_vi, rv_op_vand_vi, 0 },
+    { "vor.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vor_vv, rv_op_vor_vv, 0 },
+    { "vor.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, rv_op_vor_vx, rv_op_vor_vx, 0 },
+    { "vor.vi", rv_codec_v_i, rv_fmt_vd_vs2_imm_vm, NULL, rv_op_vor_vi, rv_op_vor_vi, 0 },
+    { "vxor.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vxor_vv, rv_op_vxor_vv, 0 },
+    { "vxor.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, rv_op_vxor_vx, rv_op_vxor_vx, 0 },
+    { "vxor.vi", rv_codec_v_i, rv_fmt_vd_vs2_imm_vm, NULL, rv_op_vxor_vi, rv_op_vxor_vi, 0 },
+    { "vsll.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vsll_vv, rv_op_vsll_vv, 0 },
+    { "vsll.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, rv_op_vsll_vx, rv_op_vsll_vx, 0 },
+    { "vsll.vi", rv_codec_v_i, rv_fmt_vd_vs2_uimm_vm, NULL, rv_op_vsll_vi, rv_op_vsll_vi, 0 },
+    { "vsrl.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vsrl_vv, rv_op_vsrl_vv, 0 },
+    { "vsrl.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, rv_op_vsrl_vx, rv_op_vsrl_vx, 0 },
+    { "vsrl.vi", rv_codec_v_i, rv_fmt_vd_vs2_uimm_vm, NULL, rv_op_vsrl_vi, rv_op_vsrl_vi, 0 },
+    { "vsra.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vsra_vv, rv_op_vsra_vv, 0 },
+    { "vsra.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, rv_op_vsra_vx, rv_op_vsra_vx, 0 },
+    { "vsra.vi", rv_codec_v_i, rv_fmt_vd_vs2_uimm_vm, NULL, rv_op_vsra_vi, rv_op_vsra_vi, 0 },
+    { "vnsrl.wv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vnsrl_wv, rv_op_vnsrl_wv, 0 },
+    { "vnsrl.wx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, rv_op_vnsrl_wx, rv_op_vnsrl_wx, 0 },
+    { "vnsrl.wi", rv_codec_v_i, rv_fmt_vd_vs2_uimm_vm, NULL, rv_op_vnsrl_wi, rv_op_vnsrl_wi, 0 },
+    { "vnsra.wv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vnsra_wv, rv_op_vnsra_wv, 0 },
+    { "vnsra.wx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, rv_op_vnsra_wx, rv_op_vnsra_wx, 0 },
+    { "vnsra.wi", rv_codec_v_i, rv_fmt_vd_vs2_uimm_vm, NULL, rv_op_vnsra_wi, rv_op_vnsra_wi, 0 },
+    { "vmseq.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vmseq_vv, rv_op_vmseq_vv, 0 },
+    { "vmseq.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, rv_op_vmseq_vx, rv_op_vmseq_vx, 0 },
+    { "vmseq.vi", rv_codec_v_i, rv_fmt_vd_vs2_imm_vm, NULL, rv_op_vmseq_vi, rv_op_vmseq_vi, 0 },
+    { "vmsne.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vmsne_vv, rv_op_vmsne_vv, 0 },
+    { "vmsne.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, rv_op_vmsne_vx, rv_op_vmsne_vx, 0 },
+    { "vmsne.vi", rv_codec_v_i, rv_fmt_vd_vs2_imm_vm, NULL, rv_op_vmsne_vi, rv_op_vmsne_vi, 0 },
+    { "vmsltu.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vmsltu_vv, rv_op_vmsltu_vv, 0 },
+    { "vmsltu.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, rv_op_vmsltu_vx, rv_op_vmsltu_vx, 0 },
+    { "vmslt.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vmslt_vv, rv_op_vmslt_vv, 0 },
+    { "vmslt.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, rv_op_vmslt_vx, rv_op_vmslt_vx, 0 },
+    { "vmsleu.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vmsleu_vv, rv_op_vmsleu_vv, 0 },
+    { "vmsleu.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, rv_op_vmsleu_vx, rv_op_vmsleu_vx, 0 },
+    { "vmsleu.vi", rv_codec_v_i, rv_fmt_vd_vs2_imm_vm, NULL, rv_op_vmsleu_vi, rv_op_vmsleu_vi, 0 },
+    { "vmsle.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vmsle_vv, rv_op_vmsle_vv, 0 },
+    { "vmsle.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, rv_op_vmsle_vx, rv_op_vmsle_vx, 0 },
+    { "vmsle.vi", rv_codec_v_i, rv_fmt_vd_vs2_imm_vm, NULL, rv_op_vmsle_vi, rv_op_vmsle_vi, 0 },
+    { "vmsgtu.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, rv_op_vmsgtu_vx, rv_op_vmsgtu_vx, 0 },
+    { "vmsgtu.vi", rv_codec_v_i, rv_fmt_vd_vs2_imm_vm, NULL, rv_op_vmsgtu_vi, rv_op_vmsgtu_vi, 0 },
+    { "vmsgt.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, rv_op_vmsgt_vx, rv_op_vmsgt_vx, 0 },
+    { "vmsgt.vi", rv_codec_v_i, rv_fmt_vd_vs2_imm_vm, NULL, rv_op_vmsgt_vi, rv_op_vmsgt_vi, 0 },
+    { "vminu.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vminu_vv, rv_op_vminu_vv, 0 },
+    { "vminu.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, rv_op_vminu_vx, rv_op_vminu_vx, 0 },
+    { "vmin.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vmin_vv, rv_op_vmin_vv, 0 },
+    { "vmin.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, rv_op_vmin_vx, rv_op_vmin_vx, 0 },
+    { "vmaxu.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vmaxu_vv, rv_op_vmaxu_vv, 0 },
+    { "vmaxu.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, rv_op_vmaxu_vx, rv_op_vmaxu_vx, 0 },
+    { "vmax.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vmax_vv, rv_op_vmax_vv, 0 },
+    { "vmax.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, rv_op_vmax_vx, rv_op_vmax_vx, 0 },
+    { "vmul.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vmul_vv, rv_op_vmul_vv, 0 },
+    { "vmul.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, rv_op_vmul_vx, rv_op_vmul_vx, 0 },
+    { "vmulh.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vmulh_vv, rv_op_vmulh_vv, 0 },
+    { "vmulh.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, rv_op_vmulh_vx, rv_op_vmulh_vx, 0 },
+    { "vmulhu.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vmulhu_vv, rv_op_vmulhu_vv, 0 },
+    { "vmulhu.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, rv_op_vmulhu_vx, rv_op_vmulhu_vx, 0 },
+    { "vmulhsu.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vmulhsu_vv, rv_op_vmulhsu_vv, 0 },
+    { "vmulhsu.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, rv_op_vmulhsu_vx, rv_op_vmulhsu_vx, 0 },
+    { "vdivu.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vdivu_vv, rv_op_vdivu_vv, 0 },
+    { "vdivu.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, rv_op_vdivu_vx, rv_op_vdivu_vx, 0 },
+    { "vdiv.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vdiv_vv, rv_op_vdiv_vv, 0 },
+    { "vdiv.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, rv_op_vdiv_vx, rv_op_vdiv_vx, 0 },
+    { "vremu.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vremu_vv, rv_op_vremu_vv, 0 },
+    { "vremu.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, rv_op_vremu_vx, rv_op_vremu_vx, 0 },
+    { "vrem.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vrem_vv, rv_op_vrem_vv, 0 },
+    { "vrem.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, rv_op_vrem_vx, rv_op_vrem_vx, 0 },
+    { "vwmulu.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vwmulu_vv, rv_op_vwmulu_vv, 0 },
+    { "vwmulu.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, rv_op_vwmulu_vx, rv_op_vwmulu_vx, 0 },
+    { "vwmulsu.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vwmulsu_vv, rv_op_vwmulsu_vv, 0 },
+    { "vwmulsu.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, rv_op_vwmulsu_vx, rv_op_vwmulsu_vx, 0 },
+    { "vwmul.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vwmul_vv, rv_op_vwmul_vv, 0 },
+    { "vwmul.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, rv_op_vwmul_vx, rv_op_vwmul_vx, 0 },
+    { "vmacc.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm, NULL, rv_op_vmacc_vv, rv_op_vmacc_vv, 0 },
+    { "vmacc.vx", rv_codec_v_r, rv_fmt_vd_rs1_vs2_vm, NULL, rv_op_vmacc_vx, rv_op_vmacc_vx, 0 },
+    { "vnmsac.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm, NULL, rv_op_vnmsac_vv, rv_op_vnmsac_vv, 0 },
+    { "vnmsac.vx", rv_codec_v_r, rv_fmt_vd_rs1_vs2_vm, NULL, rv_op_vnmsac_vx, rv_op_vnmsac_vx, 0 },
+    { "vmadd.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm, NULL, rv_op_vmadd_vv, rv_op_vmadd_vv, 0 },
+    { "vmadd.vx", rv_codec_v_r, rv_fmt_vd_rs1_vs2_vm, NULL, rv_op_vmadd_vx, rv_op_vmadd_vx, 0 },
+    { "vnmsub.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm, NULL, rv_op_vnmsub_vv, rv_op_vnmsub_vv, 0 },
+    { "vnmsub.vx", rv_codec_v_r, rv_fmt_vd_rs1_vs2_vm, NULL, rv_op_vnmsub_vx, rv_op_vnmsub_vx, 0 },
+    { "vwmaccu.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm, NULL, rv_op_vwmaccu_vv, rv_op_vwmaccu_vv, 0 },
+    { "vwmaccu.vx", rv_codec_v_r, rv_fmt_vd_rs1_vs2_vm, NULL, rv_op_vwmaccu_vx, rv_op_vwmaccu_vx, 0 },
+    { "vwmacc.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm, NULL, rv_op_vwmacc_vv, rv_op_vwmacc_vv, 0 },
+    { "vwmacc.vx", rv_codec_v_r, rv_fmt_vd_rs1_vs2_vm, NULL, rv_op_vwmacc_vx, rv_op_vwmacc_vx, 0 },
+    { "vwmaccsu.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm, NULL, rv_op_vwmaccsu_vv, rv_op_vwmaccsu_vv, 0 },
+    { "vwmaccsu.vx", rv_codec_v_r, rv_fmt_vd_rs1_vs2_vm, NULL, rv_op_vwmaccsu_vx, rv_op_vwmaccsu_vx, 0 },
+    { "vwmaccus.vx", rv_codec_v_r, rv_fmt_vd_rs1_vs2_vm, NULL, rv_op_vwmaccus_vx, rv_op_vwmaccus_vx, 0 },
+    { "vmv.v.v", rv_codec_v_r, rv_fmt_vd_vs1, NULL, rv_op_vmv_v_v, rv_op_vmv_v_v, 0 },
+    { "vmv.v.x", rv_codec_v_r, rv_fmt_vd_rs1, NULL, rv_op_vmv_v_x, rv_op_vmv_v_x, 0 },
+    { "vmv.v.i", rv_codec_v_i, rv_fmt_vd_imm, NULL, rv_op_vmv_v_i, rv_op_vmv_v_i, 0 },
+    { "vmerge.vvm", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vl, NULL, rv_op_vmerge_vvm, rv_op_vmerge_vvm, 0 },
+    { "vmerge.vxm", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vl, NULL, rv_op_vmerge_vxm, rv_op_vmerge_vxm, 0 },
+    { "vmerge.vim", rv_codec_v_i, rv_fmt_vd_vs2_imm_vl, NULL, rv_op_vmerge_vim, rv_op_vmerge_vim, 0 },
+    { "vsaddu.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vsaddu_vv, rv_op_vsaddu_vv, 0 },
+    { "vsaddu.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, rv_op_vsaddu_vx, rv_op_vsaddu_vx, 0 },
+    { "vsaddu.vi", rv_codec_v_i, rv_fmt_vd_vs2_imm_vm, NULL, rv_op_vsaddu_vi, rv_op_vsaddu_vi, 0 },
+    { "vsadd.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vsadd_vv, rv_op_vsadd_vv, 0 },
+    { "vsadd.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, rv_op_vsadd_vx, rv_op_vsadd_vx, 0 },
+    { "vsadd.vi", rv_codec_v_i, rv_fmt_vd_vs2_imm_vm, NULL, rv_op_vsadd_vi, rv_op_vsadd_vi, 0 },
+    { "vssubu.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vssubu_vv, rv_op_vssubu_vv, 0 },
+    { "vssubu.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, rv_op_vssubu_vx, rv_op_vssubu_vx, 0 },
+    { "vssub.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vssub_vv, rv_op_vssub_vv, 0 },
+    { "vssub.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, rv_op_vssub_vx, rv_op_vssub_vx, 0 },
+    { "vaadd.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vaadd_vv, rv_op_vaadd_vv, 0 },
+    { "vaadd.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, rv_op_vaadd_vx, rv_op_vaadd_vx, 0 },
+    { "vaaddu.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vaaddu_vv, rv_op_vaaddu_vv, 0 },
+    { "vaaddu.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, rv_op_vaaddu_vx, rv_op_vaaddu_vx, 0 },
+    { "vasub.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vasub_vv, rv_op_vasub_vv, 0 },
+    { "vasub.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, rv_op_vasub_vx, rv_op_vasub_vx, 0 },
+    { "vasubu.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vasubu_vv, rv_op_vasubu_vv, 0 },
+    { "vasubu.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, rv_op_vasubu_vx, rv_op_vasubu_vx, 0 },
+    { "vsmul.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vsmul_vv, rv_op_vsmul_vv, 0 },
+    { "vsmul.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, rv_op_vsmul_vx, rv_op_vsmul_vx, 0 },
+    { "vssrl.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vssrl_vv, rv_op_vssrl_vv, 0 },
+    { "vssrl.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, rv_op_vssrl_vx, rv_op_vssrl_vx, 0 },
+    { "vssrl.vi", rv_codec_v_i, rv_fmt_vd_vs2_uimm_vm, NULL, rv_op_vssrl_vi, rv_op_vssrl_vi, 0 },
+    { "vssra.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vssra_vv, rv_op_vssra_vv, 0 },
+    { "vssra.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, rv_op_vssra_vx, rv_op_vssra_vx, 0 },
+    { "vssra.vi", rv_codec_v_i, rv_fmt_vd_vs2_uimm_vm, NULL, rv_op_vssra_vi, rv_op_vssra_vi, 0 },
+    { "vnclipu.wv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vnclipu_wv, rv_op_vnclipu_wv, 0 },
+    { "vnclipu.wx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, rv_op_vnclipu_wx, rv_op_vnclipu_wx, 0 },
+    { "vnclipu.wi", rv_codec_v_i, rv_fmt_vd_vs2_uimm_vm, NULL, rv_op_vnclipu_wi, rv_op_vnclipu_wi, 0 },
+    { "vnclip.wv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vnclip_wv, rv_op_vnclip_wv, 0 },
+    { "vnclip.wx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, rv_op_vnclip_wx, rv_op_vnclip_wx, 0 },
+    { "vnclip.wi", rv_codec_v_i, rv_fmt_vd_vs2_uimm_vm, NULL, rv_op_vnclip_wi, rv_op_vnclip_wi, 0 },
+    { "vfadd.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vfadd_vv, rv_op_vfadd_vv, 0 },
+    { "vfadd.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm, NULL, rv_op_vfadd_vf, rv_op_vfadd_vf, 0 },
+    { "vfsub.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vfsub_vv, rv_op_vfsub_vv, 0 },
+    { "vfsub.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm, NULL, rv_op_vfsub_vf, rv_op_vfsub_vf, 0 },
+    { "vfrsub.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm, NULL, rv_op_vfrsub_vf, rv_op_vfrsub_vf, 0 },
+    { "vfwadd.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vfwadd_vv, rv_op_vfwadd_vv, 0 },
+    { "vfwadd.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm, NULL, rv_op_vfwadd_vf, rv_op_vfwadd_vf, 0 },
+    { "vfwadd.wv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vfwadd_wv, rv_op_vfwadd_wv, 0 },
+    { "vfwadd.wf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm, NULL, rv_op_vfwadd_wf, rv_op_vfwadd_wf, 0 },
+    { "vfwsub.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vfwsub_vv, rv_op_vfwsub_vv, 0 },
+    { "vfwsub.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm, NULL, rv_op_vfwsub_vf, rv_op_vfwsub_vf, 0 },
+    { "vfwsub.wv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vfwsub_wv, rv_op_vfwsub_wv, 0 },
+    { "vfwsub.wf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm, NULL, rv_op_vfwsub_wf, rv_op_vfwsub_wf, 0 },
+    { "vfmul.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vfmul_vv, rv_op_vfmul_vv, 0 },
+    { "vfmul.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm, NULL, rv_op_vfmul_vf, rv_op_vfmul_vf, 0 },
+    { "vfdiv.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vfdiv_vv, rv_op_vfdiv_vv, 0 },
+    { "vfdiv.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm, NULL, rv_op_vfdiv_vf, rv_op_vfdiv_vf, 0 },
+    { "vfrdiv.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm, NULL, rv_op_vfrdiv_vf, rv_op_vfrdiv_vf, 0 },
+    { "vfwmul.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vfwmul_vv, rv_op_vfwmul_vv, 0 },
+    { "vfwmul.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm, NULL, rv_op_vfwmul_vf, rv_op_vfwmul_vf, 0 },
+    { "vfmacc.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm, NULL, rv_op_vfmacc_vv, rv_op_vfmacc_vv, 0 },
+    { "vfmacc.vf", rv_codec_v_r, rv_fmt_vd_fs1_vs2_vm, NULL, rv_op_vfmacc_vf, rv_op_vfmacc_vf, 0 },
+    { "vfnmacc.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm, NULL, rv_op_vfnmacc_vv, rv_op_vfnmacc_vv, 0 },
+    { "vfnmacc.vf", rv_codec_v_r, rv_fmt_vd_fs1_vs2_vm, NULL, rv_op_vfnmacc_vf, rv_op_vfnmacc_vf, 0 },
+    { "vfmsac.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm, NULL, rv_op_vfmsac_vv, rv_op_vfmsac_vv, 0 },
+    { "vfmsac.vf", rv_codec_v_r, rv_fmt_vd_fs1_vs2_vm, NULL, rv_op_vfmsac_vf, rv_op_vfmsac_vf, 0 },
+    { "vfnmsac.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm, NULL, rv_op_vfnmsac_vv, rv_op_vfnmsac_vv, 0 },
+    { "vfnmsac.vf", rv_codec_v_r, rv_fmt_vd_fs1_vs2_vm, NULL, rv_op_vfnmsac_vf, rv_op_vfnmsac_vf, 0 },
+    { "vfmadd.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm, NULL, rv_op_vfmadd_vv, rv_op_vfmadd_vv, 0 },
+    { "vfmadd.vf", rv_codec_v_r, rv_fmt_vd_fs1_vs2_vm, NULL, rv_op_vfmadd_vf, rv_op_vfmadd_vf, 0 },
+    { "vfnmadd.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm, NULL, rv_op_vfnmadd_vv, rv_op_vfnmadd_vv, 0 },
+    { "vfnmadd.vf", rv_codec_v_r, rv_fmt_vd_fs1_vs2_vm, NULL, rv_op_vfnmadd_vf, rv_op_vfnmadd_vf, 0 },
+    { "vfmsub.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm, NULL, rv_op_vfmsub_vv, rv_op_vfmsub_vv, 0 },
+    { "vfmsub.vf", rv_codec_v_r, rv_fmt_vd_fs1_vs2_vm, NULL, rv_op_vfmsub_vf, rv_op_vfmsub_vf, 0 },
+    { "vfnmsub.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm, NULL, rv_op_vfnmsub_vv, rv_op_vfnmsub_vv, 0 },
+    { "vfnmsub.vf", rv_codec_v_r, rv_fmt_vd_fs1_vs2_vm, NULL, rv_op_vfnmsub_vf, rv_op_vfnmsub_vf, 0 },
+    { "vfwmacc.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm, NULL, rv_op_vfwmacc_vv, rv_op_vfwmacc_vv, 0 },
+    { "vfwmacc.vf", rv_codec_v_r, rv_fmt_vd_fs1_vs2_vm, NULL, rv_op_vfwmacc_vf, rv_op_vfwmacc_vf, 0 },
+    { "vfwnmacc.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm, NULL, rv_op_vfwnmacc_vv, rv_op_vfwnmacc_vv, 0 },
+    { "vfwnmacc.vf", rv_codec_v_r, rv_fmt_vd_fs1_vs2_vm, NULL, rv_op_vfwnmacc_vf, rv_op_vfwnmacc_vf, 0 },
+    { "vfwmsac.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm, NULL, rv_op_vfwmsac_vv, rv_op_vfwmsac_vv, 0 },
+    { "vfwmsac.vf", rv_codec_v_r, rv_fmt_vd_fs1_vs2_vm, NULL, rv_op_vfwmsac_vf, rv_op_vfwmsac_vf, 0 },
+    { "vfwnmsac.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm, NULL, rv_op_vfwnmsac_vv, rv_op_vfwnmsac_vv, 0 },
+    { "vfwnmsac.vf", rv_codec_v_r, rv_fmt_vd_fs1_vs2_vm, NULL, rv_op_vfwnmsac_vf, rv_op_vfwnmsac_vf, 0 },
+    { "vfsqrt.v", rv_codec_v_r, rv_fmt_vd_vs2, NULL, rv_op_vfsqrt_v, rv_op_vfsqrt_v, 0 },
+    { "vfrsqrt7.v", rv_codec_v_r, rv_fmt_vd_vs2, NULL, rv_op_vfrsqrt7_v, rv_op_vfrsqrt7_v, 0 },
+    { "vfrec7.v", rv_codec_v_r, rv_fmt_vd_vs2, NULL, rv_op_vfrec7_v, rv_op_vfrec7_v, 0 },
+    { "vfmin.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vfmin_vv, rv_op_vfmin_vv, 0 },
+    { "vfmin.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm, NULL, rv_op_vfmin_vf, rv_op_vfmin_vf, 0 },
+    { "vfmax.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vfmax_vv, rv_op_vfmax_vv, 0 },
+    { "vfmax.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm, NULL, rv_op_vfmax_vf, rv_op_vfmax_vf, 0 },
+    { "vfsgnj.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vfsgnj_vv, rv_op_vfsgnj_vv, 0 },
+    { "vfsgnj.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm, NULL, rv_op_vfsgnj_vf, rv_op_vfsgnj_vf, 0 },
+    { "vfsgnjn.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vfsgnjn_vv, rv_op_vfsgnjn_vv, 0 },
+    { "vfsgnjn.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm, NULL, rv_op_vfsgnjn_vf, rv_op_vfsgnjn_vf, 0 },
+    { "vfsgnjx.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vfsgnjx_vv, rv_op_vfsgnjx_vv, 0 },
+    { "vfsgnjx.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm, NULL, rv_op_vfsgnjx_vf, rv_op_vfsgnjx_vf, 0 },
+    { "vfslide1up.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm, NULL, rv_op_vfslide1up_vf, rv_op_vfslide1up_vf, 0 },
+    { "vfslide1down.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm, NULL, rv_op_vfslide1down_vf, rv_op_vfslide1down_vf, 0 },
+    { "vmfeq.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vmfeq_vv, rv_op_vmfeq_vv, 0 },
+    { "vmfeq.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm, NULL, rv_op_vmfeq_vf, rv_op_vmfeq_vf, 0 },
+    { "vmfne.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vmfne_vv, rv_op_vmfne_vv, 0 },
+    { "vmfne.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm, NULL, rv_op_vmfne_vf, rv_op_vmfne_vf, 0 },
+    { "vmflt.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vmflt_vv, rv_op_vmflt_vv, 0 },
+    { "vmflt.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm, NULL, rv_op_vmflt_vf, rv_op_vmflt_vf, 0 },
+    { "vmfle.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vmfle_vv, rv_op_vmfle_vv, 0 },
+    { "vmfle.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm, NULL, rv_op_vmfle_vf, rv_op_vmfle_vf, 0 },
+    { "vmfgt.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm, NULL, rv_op_vmfgt_vf, rv_op_vmfgt_vf, 0 },
+    { "vmfge.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm, NULL, rv_op_vmfge_vf, rv_op_vmfge_vf, 0 },
+    { "vfclass.v", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, rv_op_vfclass_v, rv_op_vfclass_v, 0 },
+    { "vfmerge.vfm", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vl, NULL, rv_op_vfmerge_vfm, rv_op_vfmerge_vfm, 0 },
+    { "vfmv.v.f", rv_codec_v_r, rv_fmt_vd_fs1, NULL, rv_op_vfmv_v_f, rv_op_vfmv_v_f, 0 },
+    { "vfcvt.xu.f.v", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, rv_op_vfcvt_xu_f_v, rv_op_vfcvt_xu_f_v, 0 },
+    { "vfcvt.x.f.v", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, rv_op_vfcvt_x_f_v, rv_op_vfcvt_x_f_v, 0 },
+    { "vfcvt.f.xu.v", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, rv_op_vfcvt_f_xu_v, rv_op_vfcvt_f_xu_v, 0 },
+    { "vfcvt.f.x.v", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, rv_op_vfcvt_f_x_v, rv_op_vfcvt_f_x_v, 0 },
+    { "vfcvt.rtz.xu.f.v", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, rv_op_vfcvt_rtz_xu_f_v, rv_op_vfcvt_rtz_xu_f_v, 0 },
+    { "vfcvt.rtz.x.f.v", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, rv_op_vfcvt_rtz_x_f_v, rv_op_vfcvt_rtz_x_f_v, 0 },
+    { "vfwcvt.xu.f.v", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, rv_op_vfwcvt_xu_f_v, rv_op_vfwcvt_xu_f_v, 0 },
+    { "vfwcvt.x.f.v", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, rv_op_vfwcvt_x_f_v, rv_op_vfwcvt_x_f_v, 0 },
+    { "vfwcvt.f.xu.v", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, rv_op_vfwcvt_f_xu_v, rv_op_vfwcvt_f_xu_v, 0 },
+    { "vfwcvt.f.x.v", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, rv_op_vfwcvt_f_x_v, rv_op_vfwcvt_f_x_v, 0 },
+    { "vfwcvt.f.f.v", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, rv_op_vfwcvt_f_f_v, rv_op_vfwcvt_f_f_v, 0 },
+    { "vfwcvt.rtz.xu.f.v", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, rv_op_vfwcvt_rtz_xu_f_v, rv_op_vfwcvt_rtz_xu_f_v, 0 },
+    { "vfwcvt.rtz.x.f.v", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, rv_op_vfwcvt_rtz_x_f_v, rv_op_vfwcvt_rtz_x_f_v, 0 },
+    { "vfncvt.xu.f.w", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, rv_op_vfncvt_xu_f_w, rv_op_vfncvt_xu_f_w, 0 },
+    { "vfncvt.x.f.w", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, rv_op_vfncvt_x_f_w, rv_op_vfncvt_x_f_w, 0 },
+    { "vfncvt.f.xu.w", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, rv_op_vfncvt_f_xu_w, rv_op_vfncvt_f_xu_w, 0 },
+    { "vfncvt.f.x.w", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, rv_op_vfncvt_f_x_w, rv_op_vfncvt_f_x_w, 0 },
+    { "vfncvt.f.f.w", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, rv_op_vfncvt_f_f_w, rv_op_vfncvt_f_f_w, 0 },
+    { "vfncvt.rod.f.f.w", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, rv_op_vfncvt_rod_f_f_w, rv_op_vfncvt_rod_f_f_w, 0 },
+    { "vfncvt.rtz.xu.f.w", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, rv_op_vfncvt_rtz_xu_f_w, rv_op_vfncvt_rtz_xu_f_w, 0 },
+    { "vfncvt.rtz.x.f.w", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, rv_op_vfncvt_rtz_x_f_w, rv_op_vfncvt_rtz_x_f_w, 0 },
+    { "vredsum.vs", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vredsum_vs, rv_op_vredsum_vs, 0 },
+    { "vredand.vs", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vredand_vs, rv_op_vredand_vs, 0 },
+    { "vredor.vs", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vredor_vs, rv_op_vredor_vs, 0 },
+    { "vredxor.vs", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vredxor_vs, rv_op_vredxor_vs, 0 },
+    { "vredminu.vs", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vredminu_vs, rv_op_vredminu_vs, 0 },
+    { "vredmin.vs", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vredmin_vs, rv_op_vredmin_vs, 0 },
+    { "vredmaxu.vs", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vredmaxu_vs, rv_op_vredmaxu_vs, 0 },
+    { "vredmax.vs", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vredmax_vs, rv_op_vredmax_vs, 0 },
+    { "vwredsumu.vs", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vwredsumu_vs, rv_op_vwredsumu_vs, 0 },
+    { "vwredsum.vs", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vwredsum_vs, rv_op_vwredsum_vs, 0 },
+    { "vfredusum.vs", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vfredusum_vs, rv_op_vfredusum_vs, 0 },
+    { "vfredosum.vs", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vfredosum_vs, rv_op_vfredosum_vs, 0 },
+    { "vfredmin.vs", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vfredmin_vs, rv_op_vfredmin_vs, 0 },
+    { "vfredmax.vs", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vfredmax_vs, rv_op_vfredmax_vs, 0 },
+    { "vfwredusum.vs", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vfwredusum_vs, rv_op_vfwredusum_vs, 0 },
+    { "vfwredosum.vs", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vfwredosum_vs, rv_op_vfwredosum_vs, 0 },
+    { "vmand.mm", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vmand_mm, rv_op_vmand_mm, 0 },
+    { "vmnand.mm", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vmnand_mm, rv_op_vmnand_mm, 0 },
+    { "vmandn.mm", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vmandn_mm, rv_op_vmandn_mm, 0 },
+    { "vmxor.mm", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vmxor_mm, rv_op_vmxor_mm, 0 },
+    { "vmor.mm", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vmor_mm, rv_op_vmor_mm, 0 },
+    { "vmnor.mm", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vmnor_mm, rv_op_vmnor_mm, 0 },
+    { "vmorn.mm", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vmorn_mm, rv_op_vmorn_mm, 0 },
+    { "vmxnor.mm", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vmxnor_mm, rv_op_vmxnor_mm, 0 },
+    { "vcpop.m", rv_codec_v_r, rv_fmt_rd_vs2_vm, NULL, rv_op_vcpop_m, rv_op_vcpop_m, 0 },
+    { "vfirst.m", rv_codec_v_r, rv_fmt_rd_vs2_vm, NULL, rv_op_vfirst_m, rv_op_vfirst_m, 0 },
+    { "vmsbf.m", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, rv_op_vmsbf_m, rv_op_vmsbf_m, 0 },
+    { "vmsif.m", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, rv_op_vmsif_m, rv_op_vmsif_m, 0 },
+    { "vmsof.m", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, rv_op_vmsof_m, rv_op_vmsof_m, 0 },
+    { "viota.m", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, rv_op_viota_m, rv_op_viota_m, 0 },
+    { "vid.v", rv_codec_v_r, rv_fmt_vd_vm, NULL, rv_op_vid_v, rv_op_vid_v, 0 },
+    { "vmv.x.s", rv_codec_v_r, rv_fmt_rd_vs2, NULL, rv_op_vmv_x_s, rv_op_vmv_x_s, 0 },
+    { "vmv.s.x", rv_codec_v_r, rv_fmt_vd_rs1, NULL, rv_op_vmv_s_x, rv_op_vmv_s_x, 0 },
+    { "vfmv.f.s", rv_codec_v_r, rv_fmt_fd_vs2, NULL, rv_op_vfmv_f_s, rv_op_vfmv_f_s, 0 },
+    { "vfmv.s.f", rv_codec_v_r, rv_fmt_vd_fs1, NULL, rv_op_vfmv_s_f, rv_op_vfmv_s_f, 0 },
+    { "vslideup.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, rv_op_vslideup_vx, rv_op_vslideup_vx, 0 },
+    { "vslideup.vi", rv_codec_v_i, rv_fmt_vd_vs2_uimm_vm, NULL, rv_op_vslideup_vi, rv_op_vslideup_vi, 0 },
+    { "vslide1up.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, rv_op_vslide1up_vx, rv_op_vslide1up_vx, 0 },
+    { "vslidedown.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, rv_op_vslidedown_vx, rv_op_vslidedown_vx, 0 },
+    { "vslidedown.vi", rv_codec_v_i, rv_fmt_vd_vs2_uimm_vm, NULL, rv_op_vslidedown_vi, rv_op_vslidedown_vi, 0 },
+    { "vslide1down.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, rv_op_vslide1down_vx, rv_op_vslide1down_vx, 0 },
+    { "vrgather.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vrgather_vv, rv_op_vrgather_vv, 0 },
+    { "vrgatherei16.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vrgatherei16_vv, rv_op_vrgatherei16_vv, 0 },
+    { "vrgather.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, rv_op_vrgather_vx, rv_op_vrgather_vx, 0 },
+    { "vrgather.vi", rv_codec_v_i, rv_fmt_vd_vs2_uimm_vm, NULL, rv_op_vrgather_vi, rv_op_vrgather_vi, 0 },
+    { "vcompress.vm", rv_codec_v_r, rv_fmt_vd_vs2_vs1, NULL, rv_op_vcompress_vm, rv_op_vcompress_vm, 0 },
+    { "vmv1r.v", rv_codec_v_r, rv_fmt_vd_vs2, NULL, rv_op_vmv1r_v, rv_op_vmv1r_v, 0 },
+    { "vmv2r.v", rv_codec_v_r, rv_fmt_vd_vs2, NULL, rv_op_vmv2r_v, rv_op_vmv2r_v, 0 },
+    { "vmv4r.v", rv_codec_v_r, rv_fmt_vd_vs2, NULL, rv_op_vmv4r_v, rv_op_vmv4r_v, 0 },
+    { "vmv8r.v", rv_codec_v_r, rv_fmt_vd_vs2, NULL, rv_op_vmv8r_v, rv_op_vmv8r_v, 0 },
+    { "vzext.vf2", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, rv_op_vzext_vf2, rv_op_vzext_vf2, 0 },
+    { "vzext.vf4", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, rv_op_vzext_vf4, rv_op_vzext_vf4, 0 },
+    { "vzext.vf8", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, rv_op_vzext_vf8, rv_op_vzext_vf8, 0 },
+    { "vsext.vf2", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, rv_op_vsext_vf2, rv_op_vsext_vf2, 0 },
+    { "vsext.vf4", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, rv_op_vsext_vf4, rv_op_vsext_vf4, 0 },
+    { "vsext.vf8", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, rv_op_vsext_vf8, rv_op_vsext_vf8, 0 },
+    { "vsetvli", rv_codec_vsetvli, rv_fmt_vsetvli, NULL, rv_op_vsetvli, rv_op_vsetvli, 0 },
+    { "vsetivli", rv_codec_vsetivli, rv_fmt_vsetivli, NULL, rv_op_vsetivli, rv_op_vsetivli, 0 },
+    { "vsetvl", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, rv_op_vsetvl, rv_op_vsetvl, 0 }
 };
 
 /* CSR names */
@@ -XXX,XX +XXX,XX @@ static const char *csr_name(int csrno)
     case 0x0003: return "fcsr";
     case 0x0004: return "uie";
     case 0x0005: return "utvec";
+    case 0x0008: return "vstart";
+    case 0x0009: return "vxsat";
+    case 0x000a: return "vxrm";
+    case 0x000f: return "vcsr";
     case 0x0015: return "seed";
     case 0x0040: return "uscratch";
     case 0x0041: return "uepc";
@@ -XXX,XX +XXX,XX @@ static const char *csr_name(int csrno)
     case 0x0c00: return "cycle";
     case 0x0c01: return "time";
     case 0x0c02: return "instret";
+    case 0x0c20: return "vl";
+    case 0x0c21: return "vtype";
+    case 0x0c22: return "vlenb";
     case 0x0c80: return "cycleh";
     case 0x0c81: return "timeh";
     case 0x0c82: return "instreth";
@@ -XXX,XX +XXX,XX @@ static void decode_inst_opcode(rv_decode *dec, rv_isa isa)
             break;
         case 1:
             switch (((inst >> 12) & 0b111)) {
+            case 0:
+                switch (((inst >> 20) & 0b111111111111)) {
+                case 40: op = rv_op_vl1re8_v; break;
+                case 552: op = rv_op_vl2re8_v; break;
+                case 1576: op = rv_op_vl4re8_v; break;
+                case 3624: op = rv_op_vl8re8_v; break;
+                }
+                switch (((inst >> 26) & 0b111)) {
+                case 0:
+                    switch (((inst >> 20) & 0b11111)) {
+                    case 0: op = rv_op_vle8_v; break;
+                    case 11: op = rv_op_vlm_v; break;
+                    case 16: op = rv_op_vle8ff_v; break;
+                    }
+                    break;
+                case 1: op = rv_op_vluxei8_v; break;
+                case 2: op = rv_op_vlse8_v; break;
+                case 3: op = rv_op_vloxei8_v; break;
+                }
+                break;
             case 2: op = rv_op_flw; break;
             case 3: op = rv_op_fld; break;
             case 4: op = rv_op_flq; break;
+            case 5:
+                switch (((inst >> 20) & 0b111111111111)) {
+                case 40: op = rv_op_vl1re16_v; break;
+                case 552: op = rv_op_vl2re16_v; break;
+                case 1576: op = rv_op_vl4re16_v; break;
+                case 3624: op = rv_op_vl8re16_v; break;
+                }
+                switch (((inst >> 26) & 0b111)) {
+                case 0:
+                    switch (((inst >> 20) & 0b11111)) {
+                    case 0: op = rv_op_vle16_v; break;
+                    case 16: op = rv_op_vle16ff_v; break;
+                    }
+                    break;
+                case 1: op = rv_op_vluxei16_v; break;
+                case 2: op = rv_op_vlse16_v; break;
+                case 3: op = rv_op_vloxei16_v; break;
+                }
+                break;
+            case 6:
+                switch (((inst >> 20) & 0b111111111111)) {
+                case 40: op = rv_op_vl1re32_v; break;
+                case 552: op = rv_op_vl2re32_v; break;
+                case 1576: op = rv_op_vl4re32_v; break;
+                case 3624: op = rv_op_vl8re32_v; break;
+                }
+                switch (((inst >> 26) & 0b111)) {
+                case 0:
+                    switch (((inst >> 20) & 0b11111)) {
+                    case 0: op = rv_op_vle32_v; break;
+                    case 16: op = rv_op_vle32ff_v; break;
+                    }
+                    break;
+                case 1: op = rv_op_vluxei32_v; break;
+                case 2: op = rv_op_vlse32_v; break;
+                case 3: op = rv_op_vloxei32_v; break;
+                }
+                break;
+            case 7:
+                switch (((inst >> 20) & 0b111111111111)) {
+                case 40: op = rv_op_vl1re64_v; break;
+                case 552: op = rv_op_vl2re64_v; break;
+                case 1576: op = rv_op_vl4re64_v; break;
+                case 3624: op = rv_op_vl8re64_v; break;
+                }
+                switch (((inst >> 26) & 0b111)) {
+                case 0:
+                    switch (((inst >> 20) & 0b11111)) {
+                    case 0: op = rv_op_vle64_v; break;
+                    case 16: op = rv_op_vle64ff_v; break;
+                    }
+                    break;
+                case 1: op = rv_op_vluxei64_v; break;
+                case 2: op = rv_op_vlse64_v; break;
+                case 3: op = rv_op_vloxei64_v; break;
+                }
+                break;
             }
             break;
         case 3:
@@ -XXX,XX +XXX,XX @@ static void decode_inst_opcode(rv_decode *dec, rv_isa isa)
             break;
         case 9:
             switch (((inst >> 12) & 0b111)) {
+            case 0:
+                switch (((inst >> 20) & 0b111111111111)) {
+                case 40: op = rv_op_vs1r_v; break;
+                case 552: op = rv_op_vs2r_v; break;
+                case 1576: op = rv_op_vs4r_v; break;
+                case 3624: op = rv_op_vs8r_v; break;
+                }
+                switch (((inst >> 26) & 0b111)) {
+                case 0:
+                    switch (((inst >> 20) & 0b11111)) {
+                    case 0: op = rv_op_vse8_v; break;
+                    case 11: op = rv_op_vsm_v; break;
+                    }
+                    break;
+                case 1: op = rv_op_vsuxei8_v; break;
+                case 2: op = rv_op_vsse8_v; break;
+                case 3: op = rv_op_vsoxei8_v; break;
+                }
+                break;
             case 2: op = rv_op_fsw; break;
             case 3: op = rv_op_fsd; break;
             case 4: op = rv_op_fsq; break;
+            case 5:
+                switch (((inst >> 26) & 0b111)) {
+                case 0:
+                    switch (((inst >> 20) & 0b11111)) {
+                    case 0: op = rv_op_vse16_v; break;
+                    }
+                    break;
+                case 1: op = rv_op_vsuxei16_v; break;
+                case 2: op = rv_op_vsse16_v; break;
+                case 3: op = rv_op_vsoxei16_v; break;
+                }
+                break;
+            case 6:
+                switch (((inst >> 26) & 0b111)) {
+                case 0:
+                    switch (((inst >> 20) & 0b11111)) {
+                    case 0: op = rv_op_vse32_v; break;
+                    }
+                    break;
+                case 1: op = rv_op_vsuxei32_v; break;
+                case 2: op = rv_op_vsse32_v; break;
+                case 3: op = rv_op_vsoxei32_v; break;
+                }
+                break;
+            case 7:
+                switch (((inst >> 26) & 0b111)) {
+                case 0:
+                    switch (((inst >> 20) & 0b11111)) {
+                    case 0: op = rv_op_vse64_v; break;
+                    }
+                    break;
+                case 1: op = rv_op_vsuxei64_v; break;
+                case 2: op = rv_op_vsse64_v; break;
+                case 3: op = rv_op_vsoxei64_v; break;
+                }
+                break;
             }
             break;
         case 11:
@@ -XXX,XX +XXX,XX @@ static void decode_inst_opcode(rv_decode *dec, rv_isa isa)
                 break;
             }
             break;
+        case 21:
+            switch (((inst >> 12) & 0b111)) {
+            case 0:
+                switch (((inst >> 26) & 0b111111)) {
+                case 0: op = rv_op_vadd_vv; break;
+                case 2: op = rv_op_vsub_vv; break;
+                case 4: op = rv_op_vminu_vv; break;
+                case 5: op = rv_op_vmin_vv; break;
+                case 6: op = rv_op_vmaxu_vv; break;
+                case 7: op = rv_op_vmax_vv; break;
+                case 9: op = rv_op_vand_vv; break;
+                case 10: op = rv_op_vor_vv; break;
+                case 11: op = rv_op_vxor_vv; break;
+                case 12: op = rv_op_vrgather_vv; break;
+                case 14: op = rv_op_vrgatherei16_vv; break;
+                case 16: if (((inst >> 25) & 1) == 0) op = rv_op_vadc_vvm; break;
+                case 17: op = rv_op_vmadc_vvm; break;
+                case 18: if (((inst >> 25) & 1) == 0) op = rv_op_vsbc_vvm; break;
+                case 19: op = rv_op_vmsbc_vvm; break;
+                case 23:
+                    if (((inst >> 20) & 0b111111) == 32)
+                        op = rv_op_vmv_v_v;
+                    else if (((inst >> 25) & 1) == 0)
+                        op = rv_op_vmerge_vvm;
+                    break;
+                case 24: op = rv_op_vmseq_vv; break;
+                case 25: op = rv_op_vmsne_vv; break;
+                case 26: op = rv_op_vmsltu_vv; break;
+                case 27: op = rv_op_vmslt_vv; break;
+                case 28: op = rv_op_vmsleu_vv; break;
+                case 29: op = rv_op_vmsle_vv; break;
+                case 32: op = rv_op_vsaddu_vv; break;
+                case 33: op = rv_op_vsadd_vv; break;
+                case 34: op = rv_op_vssubu_vv; break;
+                case 35: op = rv_op_vssub_vv; break;
+                case 37: op = rv_op_vsll_vv; break;
+                case 39: op = rv_op_vsmul_vv; break;
+                case 40: op = rv_op_vsrl_vv; break;
+                case 41: op = rv_op_vsra_vv; break;
+                case 42: op = rv_op_vssrl_vv; break;
+                case 43: op = rv_op_vssra_vv; break;
+                case 44: op = rv_op_vnsrl_wv; break;
+                case 45: op = rv_op_vnsra_wv; break;
+                case 46: op = rv_op_vnclipu_wv; break;
+                case 47: op = rv_op_vnclip_wv; break;
+                case 48: op = rv_op_vwredsumu_vs; break;
+                case 49: op = rv_op_vwredsum_vs; break;
+                }
+                break;
+            case 1:
+                switch (((inst >> 26) & 0b111111)) {
+                case 0: op = rv_op_vfadd_vv; break;
+                case 1: op = rv_op_vfredusum_vs; break;
+                case 2: op = rv_op_vfsub_vv; break;
+                case 3: op = rv_op_vfredosum_vs; break;
+                case 4: op = rv_op_vfmin_vv; break;
+                case 5: op = rv_op_vfredmin_vs; break;
+                case 6: op = rv_op_vfmax_vv; break;
+                case 7: op = rv_op_vfredmax_vs; break;
+                case 8: op = rv_op_vfsgnj_vv; break;
+                case 9: op = rv_op_vfsgnjn_vv; break;
+                case 10: op = rv_op_vfsgnjx_vv; break;
+                case 16:
+                    switch (((inst >> 15) & 0b11111)) {
+                    case 0: if ((inst >> 25) & 1) op = rv_op_vfmv_f_s; break;
+                    }
+                    break;
+                case 18:
+                    switch (((inst >> 15) & 0b11111)) {
+                    case 0: op = rv_op_vfcvt_xu_f_v; break;
+                    case 1: op = rv_op_vfcvt_x_f_v; break;
+                    case 2: op = rv_op_vfcvt_f_xu_v; break;
+                    case 3: op = rv_op_vfcvt_f_x_v; break;
+                    case 6: op = rv_op_vfcvt_rtz_xu_f_v; break;
+                    case 7: op = rv_op_vfcvt_rtz_x_f_v; break;
+                    case 8: op = rv_op_vfwcvt_xu_f_v; break;
+                    case 9: op = rv_op_vfwcvt_x_f_v; break;
+                    case 10: op = rv_op_vfwcvt_f_xu_v; break;
+                    case 11: op = rv_op_vfwcvt_f_x_v; break;
+                    case 12: op = rv_op_vfwcvt_f_f_v; break;
+                    case 14: op = rv_op_vfwcvt_rtz_xu_f_v; break;
+                    case 15: op = rv_op_vfwcvt_rtz_x_f_v; break;
+                    case 16: op = rv_op_vfncvt_xu_f_w; break;
+                    case 17: op = rv_op_vfncvt_x_f_w; break;
+                    case 18: op = rv_op_vfncvt_f_xu_w; break;
+                    case 19: op = rv_op_vfncvt_f_x_w; break;
+                    case 20: op = rv_op_vfncvt_f_f_w; break;
+                    case 21: op = rv_op_vfncvt_rod_f_f_w; break;
+                    case 22: op = rv_op_vfncvt_rtz_xu_f_w; break;
+                    case 23: op = rv_op_vfncvt_rtz_x_f_w; break;
+                    }
+                    break;
+                case 19:
+                    switch (((inst >> 15) & 0b11111)) {
+                    case 0: op = rv_op_vfsqrt_v; break;
+                    case 4: op = rv_op_vfrsqrt7_v; break;
+                    case 5: op = rv_op_vfrec7_v; break;
+                    case 16: op = rv_op_vfclass_v; break;
+                    }
+                    break;
+                case 24: op = rv_op_vmfeq_vv; break;
+                case 25: op = rv_op_vmfle_vv; break;
+                case 27: op = rv_op_vmflt_vv; break;
+                case 28: op = rv_op_vmfne_vv; break;
+                case 32: op = rv_op_vfdiv_vv; break;
+                case 36: op = rv_op_vfmul_vv; break;
+                case 40: op = rv_op_vfmadd_vv; break;
+                case 41: op = rv_op_vfnmadd_vv; break;
+                case 42: op = rv_op_vfmsub_vv; break;
+                case 43: op = rv_op_vfnmsub_vv; break;
+                case 44: op = rv_op_vfmacc_vv; break;
+                case 45: op = rv_op_vfnmacc_vv; break;
+                case 46: op = rv_op_vfmsac_vv; break;
+                case 47: op = rv_op_vfnmsac_vv; break;
+                case 48: op = rv_op_vfwadd_vv; break;
+                case 49: op = rv_op_vfwredusum_vs; break;
+                case 50: op = rv_op_vfwsub_vv; break;
+                case 51: op = rv_op_vfwredosum_vs; break;
+                case 52: op = rv_op_vfwadd_wv; break;
+                case 54: op = rv_op_vfwsub_wv; break;
+                case 56: op = rv_op_vfwmul_vv; break;
+                case 60: op = rv_op_vfwmacc_vv; break;
+                case 61: op = rv_op_vfwnmacc_vv; break;
+                case 62: op = rv_op_vfwmsac_vv; break;
+                case 63: op = rv_op_vfwnmsac_vv; break;
+                }
+                break;
+            case 2:
+                switch (((inst >> 26) & 0b111111)) {
+                case 0: op = rv_op_vredsum_vs; break;
+                case 1: op = rv_op_vredand_vs; break;
+                case 2: op = rv_op_vredor_vs; break;
+                case 3: op = rv_op_vredxor_vs; break;
+                case 4: op = rv_op_vredminu_vs; break;
+                case 5: op = rv_op_vredmin_vs; break;
+                case 6: op = rv_op_vredmaxu_vs; break;
+                case 7: op = rv_op_vredmax_vs; break;
+                case 8: op = rv_op_vaaddu_vv; break;
+                case 9: op = rv_op_vaadd_vv; break;
+                case 10: op = rv_op_vasubu_vv; break;
+                case 11: op = rv_op_vasub_vv; break;
+                case 16:
+                    switch (((inst >> 15) & 0b11111)) {
+                    case 0: if ((inst >> 25) & 1) op = rv_op_vmv_x_s; break;
+                    case 16: op = rv_op_vcpop_m; break;
+                    case 17: op = rv_op_vfirst_m; break;
+                    }
+                    break;
+                case 18:
+                    switch (((inst >> 15) & 0b11111)) {
+                    case 2: op = rv_op_vzext_vf8; break;
+                    case 3: op = rv_op_vsext_vf8; break;
+                    case 4: op = rv_op_vzext_vf4; break;
+                    case 5: op = rv_op_vsext_vf4; break;
+                    case 6: op = rv_op_vzext_vf2; break;
+                    case 7: op = rv_op_vsext_vf2; break;
+                    }
+                    break;
+                case 20:
+                    switch (((inst >> 15) & 0b11111)) {
+                    case 1: op = rv_op_vmsbf_m;  break;
+                    case 2: op = rv_op_vmsof_m; break;
+                    case 3: op = rv_op_vmsif_m; break;
+                    case 16: op = rv_op_viota_m; break;
+                    case 17: if (((inst >> 20) & 0b11111) == 0) op = rv_op_vid_v; break;
+                    }
+                    break;
+                case 23: if ((inst >> 25) & 1) op = rv_op_vcompress_vm; break;
+                case 24: if ((inst >> 25) & 1) op = rv_op_vmandn_mm; break;
+                case 25: if ((inst >> 25) & 1) op = rv_op_vmand_mm; break;
+                case 26: if ((inst >> 25) & 1) op = rv_op_vmor_mm; break;
+                case 27: if ((inst >> 25) & 1) op = rv_op_vmxor_mm; break;
+                case 28: if ((inst >> 25) & 1) op = rv_op_vmorn_mm; break;
+                case 29: if ((inst >> 25) & 1) op = rv_op_vmnand_mm; break;
+                case 30: if ((inst >> 25) & 1) op = rv_op_vmnor_mm; break;
+                case 31: if ((inst >> 25) & 1) op = rv_op_vmxnor_mm; break;
+                case 32: op = rv_op_vdivu_vv; break;
+                case 33: op = rv_op_vdiv_vv; break;
+                case 34: op = rv_op_vremu_vv; break;
+                case 35: op = rv_op_vrem_vv; break;
+                case 36: op = rv_op_vmulhu_vv; break;
+                case 37: op = rv_op_vmul_vv; break;
+                case 38: op = rv_op_vmulhsu_vv; break;
+                case 39: op = rv_op_vmulh_vv; break;
+                case 41: op = rv_op_vmadd_vv; break;
+                case 43: op = rv_op_vnmsub_vv; break;
+                case 45: op = rv_op_vmacc_vv; break;
+                case 47: op = rv_op_vnmsac_vv; break;
+                case 48: op = rv_op_vwaddu_vv; break;
+                case 49: op = rv_op_vwadd_vv; break;
+                case 50: op = rv_op_vwsubu_vv; break;
+                case 51: op = rv_op_vwsub_vv; break;
+                case 52: op = rv_op_vwaddu_wv; break;
+                case 53: op = rv_op_vwadd_wv; break;
+                case 54: op = rv_op_vwsubu_wv; break;
+                case 55: op = rv_op_vwsub_wv; break;
+                case 56: op = rv_op_vwmulu_vv; break;
+                case 58: op = rv_op_vwmulsu_vv; break;
+                case 59: op = rv_op_vwmul_vv; break;
+                case 60: op = rv_op_vwmaccu_vv; break;
+                case 61: op = rv_op_vwmacc_vv; break;
+                case 63: op = rv_op_vwmaccsu_vv; break;
+                }
+                break;
+            case 3:
+                switch (((inst >> 26) & 0b111111)) {
+                case 0: op = rv_op_vadd_vi; break;
+                case 3: op = rv_op_vrsub_vi; break;
+                case 9: op = rv_op_vand_vi; break;
+                case 10: op = rv_op_vor_vi; break;
+                case 11: op = rv_op_vxor_vi; break;
+                case 12: op = rv_op_vrgather_vi; break;
+                case 14: op = rv_op_vslideup_vi; break;
+                case 15: op = rv_op_vslidedown_vi; break;
+                case 16: if (((inst >> 25) & 1) == 0) op = rv_op_vadc_vim; break;
+                case 17: op = rv_op_vmadc_vim; break;
+                case 23:
+                    if (((inst >> 20) & 0b111111) == 32)
+                        op = rv_op_vmv_v_i;
+                    else if (((inst >> 25) & 1) == 0)
+                        op = rv_op_vmerge_vim;
+                    break;
+                case 24: op = rv_op_vmseq_vi; break;
+                case 25: op = rv_op_vmsne_vi; break;
+                case 28: op = rv_op_vmsleu_vi; break;
+                case 29: op = rv_op_vmsle_vi; break;
+                case 30: op = rv_op_vmsgtu_vi; break;
+                case 31: op = rv_op_vmsgt_vi; break;
+                case 32: op = rv_op_vsaddu_vi; break;
+                case 33: op = rv_op_vsadd_vi; break;
+                case 37: op = rv_op_vsll_vi; break;
+                case 39:
+                    switch (((inst >> 15) & 0b11111)) {
+                    case 0: op = rv_op_vmv1r_v; break;
+                    case 1: op = rv_op_vmv2r_v; break;
+                    case 3: op = rv_op_vmv4r_v; break;
+                    case 7: op = rv_op_vmv8r_v; break;
+                    }
+                    break;
+                case 40: op = rv_op_vsrl_vi; break;
+                case 41: op = rv_op_vsra_vi; break;
+                case 42: op = rv_op_vssrl_vi; break;
+                case 43: op = rv_op_vssra_vi; break;
+                case 44: op = rv_op_vnsrl_wi; break;
+                case 45: op = rv_op_vnsra_wi; break;
+                case 46: op = rv_op_vnclipu_wi; break;
+                case 47: op = rv_op_vnclip_wi; break;
+                }
+                break;
+            case 4:
+                switch (((inst >> 26) & 0b111111)) {
+                case 0: op = rv_op_vadd_vx; break;
+                case 2: op = rv_op_vsub_vx; break;
+                case 3: op = rv_op_vrsub_vx; break;
+                case 4: op = rv_op_vminu_vx; break;
+                case 5: op = rv_op_vmin_vx; break;
+                case 6: op = rv_op_vmaxu_vx; break;
+                case 7: op = rv_op_vmax_vx; break;
+                case 9: op = rv_op_vand_vx; break;
+                case 10: op = rv_op_vor_vx; break;
+                case 11: op = rv_op_vxor_vx; break;
+                case 12: op = rv_op_vrgather_vx; break;
+                case 14: op = rv_op_vslideup_vx; break;
+                case 15: op = rv_op_vslidedown_vx; break;
+                case 16: if (((inst >> 25) & 1) == 0) op = rv_op_vadc_vxm; break;
+                case 17: op = rv_op_vmadc_vxm; break;
+                case 18: if (((inst >> 25) & 1) == 0) op = rv_op_vsbc_vxm; break;
+                case 19: op = rv_op_vmsbc_vxm; break;
+                case 23:
+                    if (((inst >> 20) & 0b111111) == 32)
+                        op = rv_op_vmv_v_x;
+                    else if (((inst >> 25) & 1) == 0)
+                        op = rv_op_vmerge_vxm;
+                    break;
+                case 24: op = rv_op_vmseq_vx; break;
+                case 25: op = rv_op_vmsne_vx; break;
+                case 26: op = rv_op_vmsltu_vx; break;
+                case 27: op = rv_op_vmslt_vx; break;
+                case 28: op = rv_op_vmsleu_vx; break;
+                case 29: op = rv_op_vmsle_vx; break;
+                case 30: op = rv_op_vmsgtu_vx; break;
+                case 31: op = rv_op_vmsgt_vx; break;
+                case 32: op = rv_op_vsaddu_vx; break;
+                case 33: op = rv_op_vsadd_vx; break;
+                case 34: op = rv_op_vssubu_vx; break;
+                case 35: op = rv_op_vssub_vx; break;
+                case 37: op = rv_op_vsll_vx; break;
+                case 39: op = rv_op_vsmul_vx; break;
+                case 40: op = rv_op_vsrl_vx; break;
+                case 41: op = rv_op_vsra_vx; break;
+                case 42: op = rv_op_vssrl_vx; break;
+                case 43: op = rv_op_vssra_vx; break;
+                case 44: op = rv_op_vnsrl_wx; break;
+                case 45: op = rv_op_vnsra_wx; break;
+                case 46: op = rv_op_vnclipu_wx; break;
+                case 47: op = rv_op_vnclip_wx; break;
+                }
+                break;
+            case 5:
+                switch (((inst >> 26) & 0b111111)) {
+                case 0: op = rv_op_vfadd_vf; break;
+                case 2: op = rv_op_vfsub_vf; break;
+                case 4: op = rv_op_vfmin_vf; break;
+                case 6: op = rv_op_vfmax_vf; break;
+                case 8: op = rv_op_vfsgnj_vf; break;
+                case 9: op = rv_op_vfsgnjn_vf; break;
+                case 10: op = rv_op_vfsgnjx_vf; break;
+                case 14: op = rv_op_vfslide1up_vf; break;
+                case 15: op = rv_op_vfslide1down_vf; break;
+                case 16:
+                    switch (((inst >> 20) & 0b11111)) {
+                    case 0: if ((inst >> 25) & 1) op = rv_op_vfmv_s_f; break;
+                    }
+                    break;
+                case 23:
+                    if (((inst >> 25) & 1) == 0)
+                        op = rv_op_vfmerge_vfm;
+                    else if (((inst >> 20) & 0b111111) == 32)
+                        op = rv_op_vfmv_v_f;
+                    break;
+                case 24: op = rv_op_vmfeq_vf; break;
+                case 25: op = rv_op_vmfle_vf; break;
+                case 27: op = rv_op_vmflt_vf; break;
+                case 28: op = rv_op_vmfne_vf; break;
+                case 29: op = rv_op_vmfgt_vf; break;
+                case 31: op = rv_op_vmfge_vf; break;
+                case 32: op = rv_op_vfdiv_vf; break;
+                case 33: op = rv_op_vfrdiv_vf; break;
+                case 36: op = rv_op_vfmul_vf; break;
+                case 39: op = rv_op_vfrsub_vf; break;
+                case 40: op = rv_op_vfmadd_vf; break;
+                case 41: op = rv_op_vfnmadd_vf; break;
+                case 42: op = rv_op_vfmsub_vf; break;
+                case 43: op = rv_op_vfnmsub_vf; break;
+                case 44: op = rv_op_vfmacc_vf; break;
+                case 45: op = rv_op_vfnmacc_vf; break;
+                case 46: op = rv_op_vfmsac_vf; break;
+                case 47: op = rv_op_vfnmsac_vf; break;
+                case 48: op = rv_op_vfwadd_vf; break;
+                case 50: op = rv_op_vfwsub_vf; break;
+                case 52: op = rv_op_vfwadd_wf; break;
+                case 54: op = rv_op_vfwsub_wf; break;
+                case 56: op = rv_op_vfwmul_vf; break;
+                case 60: op = rv_op_vfwmacc_vf; break;
+                case 61: op = rv_op_vfwnmacc_vf; break;
+                case 62: op = rv_op_vfwmsac_vf; break;
+                case 63: op = rv_op_vfwnmsac_vf; break;
+                }
+                break;
+            case 6:
+                switch (((inst >> 26) & 0b111111)) {
+                case 8: op = rv_op_vaaddu_vx; break;
+                case 9: op = rv_op_vaadd_vx; break;
+                case 10: op = rv_op_vasubu_vx; break;
+                case 11: op = rv_op_vasub_vx; break;
+                case 14: op = rv_op_vslide1up_vx; break;
+                case 15: op = rv_op_vslide1down_vx; break;
+                case 16:
+                    switch (((inst >> 20) & 0b11111)) {
+                    case 0: if ((inst >> 25) & 1) op = rv_op_vmv_s_x; break;
+                    }
+                    break;
+                case 32: op = rv_op_vdivu_vx; break;
+                case 33: op = rv_op_vdiv_vx; break;
+                case 34: op = rv_op_vremu_vx; break;
+                case 35: op = rv_op_vrem_vx; break;
+                case 36: op = rv_op_vmulhu_vx; break;
+                case 37: op = rv_op_vmul_vx; break;
+                case 38: op = rv_op_vmulhsu_vx; break;
+                case 39: op = rv_op_vmulh_vx; break;
+                case 41: op = rv_op_vmadd_vx; break;
+                case 43: op = rv_op_vnmsub_vx; break;
+                case 45: op = rv_op_vmacc_vx; break;
+                case 47: op = rv_op_vnmsac_vx; break;
+                case 48: op = rv_op_vwaddu_vx; break;
+                case 49: op = rv_op_vwadd_vx; break;
+                case 50: op = rv_op_vwsubu_vx; break;
+                case 51: op = rv_op_vwsub_vx; break;
+                case 52: op = rv_op_vwaddu_wx; break;
+                case 53: op = rv_op_vwadd_wx; break;
+                case 54: op = rv_op_vwsubu_wx; break;
+                case 55: op = rv_op_vwsub_wx; break;
+                case 56: op = rv_op_vwmulu_vx; break;
+                case 58: op = rv_op_vwmulsu_vx; break;
+                case 59: op = rv_op_vwmul_vx; break;
+                case 60: op = rv_op_vwmaccu_vx; break;
+                case 61: op = rv_op_vwmacc_vx; break;
+                case 62: op = rv_op_vwmaccus_vx; break;
+                case 63: op = rv_op_vwmaccsu_vx; break;
+                }
+                break;
+            case 7:
+                if (((inst >> 31) & 1) == 0) {
+                    op = rv_op_vsetvli;
+                } else if ((inst >> 30) & 1) {
+                    op = rv_op_vsetivli;
+                } else if (((inst >> 25) & 0b11111) == 0) {
+                    op = rv_op_vsetvl;
+                }
+                break;
+            }
+            break;
         case 22:
             switch (((inst >> 12) & 0b111)) {
             case 0: op = rv_op_addid; break;
@@ -XXX,XX +XXX,XX @@ static uint32_t operand_cimmq(rv_inst inst)
         ((inst << 57) >> 62) << 6;
 }
 
+static uint32_t operand_vimm(rv_inst inst)
+{
+    return (int64_t)(inst << 44) >> 59;
+}
+
+static uint32_t operand_vzimm11(rv_inst inst)
+{
+    return (inst << 33) >> 53;
+}
+
+static uint32_t operand_vzimm10(rv_inst inst)
+{
+    return (inst << 34) >> 54;
+}
+
 static uint32_t operand_bs(rv_inst inst)
 {
     return (inst << 32) >> 62;
@@ -XXX,XX +XXX,XX @@ static uint32_t operand_rnum(rv_inst inst)
     return (inst << 40) >> 60;
 }
 
+static uint32_t operand_vm(rv_inst inst)
+{
+    return (inst << 38) >> 63;
+}
+
 /* decode operands */
 
 static void decode_inst_operands(rv_decode *dec, rv_isa isa)
@@ -XXX,XX +XXX,XX @@ static void decode_inst_operands(rv_decode *dec, rv_isa isa)
         dec->rs1 = operand_rs1(inst);
         dec->rnum = operand_rnum(inst);
         break;
+    case rv_codec_v_r:
+        dec->rd = operand_rd(inst);
+        dec->rs1 = operand_rs1(inst);
+        dec->rs2 = operand_rs2(inst);
+        dec->vm = operand_vm(inst);
+        break;
+    case rv_codec_v_ldst:
+        dec->rd = operand_rd(inst);
+        dec->rs1 = operand_rs1(inst);
+        dec->vm = operand_vm(inst);
+        break;
+    case rv_codec_v_i:
+        dec->rd = operand_rd(inst);
+        dec->rs2 = operand_rs2(inst);
+        dec->imm = operand_vimm(inst);
+        dec->vm = operand_vm(inst);
+        break;
+    case rv_codec_vsetvli:
+        dec->rd = operand_rd(inst);
+        dec->rs1 = operand_rs1(inst);
+        dec->vzimm = operand_vzimm11(inst);
+        break;
+    case rv_codec_vsetivli:
+        dec->rd = operand_rd(inst);
+        dec->imm = operand_vimm(inst);
+        dec->vzimm = operand_vzimm10(inst);
+        break;
     };
 }
 
@@ -XXX,XX +XXX,XX @@ static void format_inst(char *buf, size_t buflen, size_t tab, rv_decode *dec)
             snprintf(tmp, sizeof(tmp), "%d", dec->imm);
             append(buf, tmp, buflen);
             break;
+        case 'u':
+            snprintf(tmp, sizeof(tmp), "%u", ((uint32_t)dec->imm & 0b11111));
+            append(buf, tmp, buflen);
+            break;
         case 'o':
             snprintf(tmp, sizeof(tmp), "%d", dec->imm);
             append(buf, tmp, buflen);
@@ -XXX,XX +XXX,XX @@ static void format_inst(char *buf, size_t buflen, size_t tab, rv_decode *dec)
                 append(buf, ".rl", buflen);
             }
             break;
+        case 'l':
+            append(buf, ",v0", buflen);
+            break;
+        case 'm':
+            if (dec->vm == 0) {
+                append(buf, ",v0.t", buflen);
+            }
+            break;
+        case 'D':
+            append(buf, rv_vreg_name_sym[dec->rd], buflen);
+            break;
+        case 'E':
+            append(buf, rv_vreg_name_sym[dec->rs1], buflen);
+            break;
+        case 'F':
+            append(buf, rv_vreg_name_sym[dec->rs2], buflen);
+            break;
+        case 'G':
+            append(buf, rv_vreg_name_sym[dec->rs3], buflen);
+            break;
+        case 'v': {
+            char nbuf[32] = {0};
+            const int sew = 1 << (((dec->vzimm >> 3) & 0b111) + 3);
+            sprintf(nbuf, "%d", sew);
+            const int lmul = dec->vzimm & 0b11;
+            const int flmul = (dec->vzimm >> 2) & 1;
+            const char *vta = (dec->vzimm >> 6) & 1 ? "ta" : "tu";
+            const char *vma = (dec->vzimm >> 7) & 1 ? "ma" : "mu";
+            append(buf, "e", buflen);
+            append(buf, nbuf, buflen);
+            append(buf, ",m", buflen);
+            if (flmul) {
+                switch (lmul) {
+                case 3:
+                    sprintf(nbuf, "f2");
+                    break;
+                case 2:
+                    sprintf(nbuf, "f4");
+                    break;
+                case 1:
+                    sprintf(nbuf, "f8");
+                break;
+                }
+                append(buf, nbuf, buflen);
+            } else {
+                sprintf(nbuf, "%d", 1 << lmul);
+                append(buf, nbuf, buflen);
+            }
+            append(buf, ",", buflen);
+            append(buf, vta, buflen);
+            append(buf, ",", buflen);
+            append(buf, vma, buflen);
+            break;
+        }
         default:
             break;
         }
@@ -XXX,XX +XXX,XX @@ disasm_inst(char *buf, size_t buflen, rv_isa isa, uint64_t pc, rv_inst inst)
     decode_inst_operands(&dec, isa);
     decode_inst_decompress(&dec, isa);
     decode_inst_lift_pseudo(&dec);
-    format_inst(buf, buflen, 16, &dec);
+    format_inst(buf, buflen, 24, &dec);
 }
 
 #define INST_FMT_2 "%04" PRIx64 "              "
-- 
2.37.3

From: Jim Shu <jim.shu@sifive.com>

The maximum priority level is hard-coded when writing to interrupt
priority register. However, when writing to priority threshold register,
the maximum priority level is from num_priorities Property which is
configured by platform.

Also change interrupt priority register to use num_priorities Property
in maximum priority level.

Signed-off-by: Emmanuel Blot <emmanuel.blot@sifive.com>
Signed-off-by: Jim Shu <jim.shu@sifive.com>
Reviewed-by: Frank Chang <frank.chang@sifive.com>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20221003041440.2320-2-jim.shu@sifive.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 hw/intc/sifive_plic.c | 6 ++++--
 1 file changed, 4 insertions(+), 2 deletions(-)

From: Jim Shu <jim.shu@sifive.com>

PLIC spec [1] requires interrupt source priority registers are WARL
field and the number of supported priority is power-of-2 to simplify SW
discovery.

Existing QEMU RISC-V machine (e.g. shakti_c) don't strictly follow PLIC
spec, whose number of supported priority is not power-of-2. Just change
each bit of interrupt priority register to WARL field when the number of
supported priority is power-of-2.

[1] https://github.com/riscv/riscv-plic-spec/blob/master/riscv-plic.adoc#interrupt-priorities

Signed-off-by: Jim Shu <jim.shu@sifive.com>
Reviewed-by: Clément Chigot <chigot@adacore.com>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20221003041440.2320-3-jim.shu@sifive.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 hw/intc/sifive_plic.c | 21 +++++++++++++++++++--
 1 file changed, 19 insertions(+), 2 deletions(-)

diff --git a/hw/intc/sifive_plic.c b/hw/intc/sifive_plic.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/intc/sifive_plic.c
+++ b/hw/intc/sifive_plic.c
@@ -XXX,XX +XXX,XX @@ static void sifive_plic_write(void *opaque, hwaddr addr, uint64_t value,
     if (addr_between(addr, plic->priority_base, plic->num_sources << 2)) {
         uint32_t irq = ((addr - plic->priority_base) >> 2) + 1;
 
-        if (value <= plic->num_priorities) {
+        if (((plic->num_priorities + 1) & plic->num_priorities) == 0) {
+            /*
+             * if "num_priorities + 1" is power-of-2, make each register bit of
+             * interrupt priority WARL (Write-Any-Read-Legal). Just filter
+             * out the access to unsupported priority bits.
+             */
+            plic->source_priority[irq] = value % (plic->num_priorities + 1);
+            sifive_plic_update(plic);
+        } else if (value <= plic->num_priorities) {
             plic->source_priority[irq] = value;
             sifive_plic_update(plic);
         }
@@ -XXX,XX +XXX,XX @@ static void sifive_plic_write(void *opaque, hwaddr addr, uint64_t value,
         uint32_t contextid = (addr & (plic->context_stride - 1));
 
         if (contextid == 0) {
-            if (value <= plic->num_priorities) {
+            if (((plic->num_priorities + 1) & plic->num_priorities) == 0) {
+                /*
+                 * if "num_priorities + 1" is power-of-2, each register bit of
+                 * interrupt priority is WARL (Write-Any-Read-Legal). Just
+                 * filter out the access to unsupported priority bits.
+                 */
+                plic->target_priority[addrid] = value %
+                                                (plic->num_priorities + 1);
+                sifive_plic_update(plic);
+            } else if (value <= plic->num_priorities) {
                 plic->target_priority[addrid] = value;
                 sifive_plic_update(plic);
             }
-- 
2.37.3

From: Alistair Francis <alistair.francis@wdc.com>

Since commit 4047368938f6 "accel/tcg: Introduce tlb_set_page_full" we
have been seeing this assert

../accel/tcg/cputlb.c:1294: tlb_set_page_with_attrs: Assertion `is_power_of_2(size)' failed.

When running Tock on the OpenTitan machine.

The issue is that pmp_get_tlb_size() would return a TLB size that wasn't
a power of 2. The size was also smaller then TARGET_PAGE_SIZE.

This patch ensures that any TLB size less then TARGET_PAGE_SIZE is
rounded down to 1 to ensure it's a valid size.

Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: LIU Zhiwei<zhiwei_liu@linux.alibaba.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20221012011449.506928-1-alistair.francis@opensource.wdc.com
Message-Id: <20221012011449.506928-1-alistair.francis@opensource.wdc.com>
---
 target/riscv/pmp.c | 12 ++++++++++++
 1 file changed, 12 insertions(+)

diff --git a/target/riscv/pmp.c b/target/riscv/pmp.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/pmp.c
+++ b/target/riscv/pmp.c
@@ -XXX,XX +XXX,XX @@ bool pmp_is_range_in_tlb(CPURISCVState *env, hwaddr tlb_sa,
     }
 
     if (*tlb_size != 0) {
+        /*
+         * At this point we have a tlb_size that is the smallest possible size
+         * That fits within a TARGET_PAGE_SIZE and the PMP region.
+         *
+         * If the size is less then TARGET_PAGE_SIZE we drop the size to 1.
+         * This means the result isn't cached in the TLB and is only used for
+         * a single translation.
+         */
+        if (*tlb_size < TARGET_PAGE_SIZE) {
+            *tlb_size = 1;
+        }
+
         return true;
     }
 
-- 
2.37.3

The following changes since commit ad10b4badc1dd5b28305f9b9f1168cf0aa3ae946:

Merge tag 'pull-error-2024-05-27' of https://repo.or.cz/qemu/armbru into staging (2024-05-27 06:40:42 -0700)

are available in the Git repository at:

https://github.com/alistair23/qemu.git tags/pull-riscv-to-apply-20240528

for you to fetch changes up to 1806da76cb81088ea026ca3441551782b850e393:

target/riscv: raise an exception when CSRRS/CSRRC writes a read-only CSR (2024-05-28 12:20:27 +1000)

----------------------------------------------------------------
RISC-V PR for 9.1

* APLICs add child earlier than realize
* Fix exposure of Zkr
* Raise exceptions on wrs.nto
* Implement SBI debug console (DBCN) calls for KVM
* Support 64-bit addresses for initrd
* Change RISCV_EXCP_SEMIHOST exception number to 63
* Tolerate KVM disable ext errors
* Set tval in breakpoints
* Add support for Zve32x extension
* Add support for Zve64x extension
* Relax vector register check in RISCV gdbstub
* Fix the element agnostic Vector function problem
* Fix Zvkb extension config
* Implement dynamic establishment of custom decoder
* Add th.sxstatus CSR emulation
* Fix Zvfhmin checking for vfwcvt.f.f.v and vfncvt.f.f.w instructions
* Check single width operator for vector fp widen instructions
* Check single width operator for vfncvt.rod.f.f.w
* Remove redudant SEW checking for vector fp narrow/widen instructions
* Prioritize pmp errors in raise_mmu_exception()
* Do not set mtval2 for non guest-page faults
* Remove experimental prefix from "B" extension
* Fixup CBO extension register calculation
* Fix the hart bit setting of AIA
* Fix reg_width in ricsv_gen_dynamic_vector_feature()
* Decode all of the pmpcfg and pmpaddr CSRs
* Raise an exception when CSRRS/CSRRC writes a read-only CSR

----------------------------------------------------------------
Alexei Filippov (1):
      target/riscv: do not set mtval2 for non guest-page faults

Alistair Francis (2):
      target/riscv: rvzicbo: Fixup CBO extension register calculation
      disas/riscv: Decode all of the pmpcfg and pmpaddr CSRs

Andrew Jones (2):
      target/riscv/kvm: Fix exposure of Zkr
      target/riscv: Raise exceptions on wrs.nto

Cheng Yang (1):
      hw/riscv/boot.c: Support 64-bit address for initrd

Christoph Müllner (1):
      riscv: thead: Add th.sxstatus CSR emulation

Clément Léger (1):
      target/riscv: change RISCV_EXCP_SEMIHOST exception number to 63

Daniel Henrique Barboza (6):
      target/riscv/kvm: implement SBI debug console (DBCN) calls
      target/riscv/kvm: tolerate KVM disable ext errors
      target/riscv/debug: set tval=pc in breakpoint exceptions
      trans_privileged.c.inc: set (m|s)tval on ebreak breakpoint
      target/riscv: prioritize pmp errors in raise_mmu_exception()
      riscv, gdbstub.c: fix reg_width in ricsv_gen_dynamic_vector_feature()

Huang Tao (2):
      target/riscv: Fix the element agnostic function problem
      target/riscv: Implement dynamic establishment of custom decoder

Jason Chien (3):
      target/riscv: Add support for Zve32x extension
      target/riscv: Add support for Zve64x extension
      target/riscv: Relax vector register check in RISCV gdbstub

Max Chou (4):
      target/riscv: rvv: Fix Zvfhmin checking for vfwcvt.f.f.v and vfncvt.f.f.w instructions
      target/riscv: rvv: Check single width operator for vector fp widen instructions
      target/riscv: rvv: Check single width operator for vfncvt.rod.f.f.w
      target/riscv: rvv: Remove redudant SEW checking for vector fp narrow/widen instructions

Rob Bradford (1):
      target/riscv: Remove experimental prefix from "B" extension

Yangyu Chen (1):
      target/riscv/cpu.c: fix Zvkb extension config

Yong-Xuan Wang (1):
      target/riscv/kvm.c: Fix the hart bit setting of AIA

Yu-Ming Chang (1):
      target/riscv: raise an exception when CSRRS/CSRRC writes a read-only CSR

yang.zhang (1):
      hw/intc/riscv_aplic: APLICs should add child earlier than realize

From: "yang.zhang" <yang.zhang@hexintek.com>

Since only root APLICs can have hw IRQ lines, aplic->parent should
be initialized first.

Fixes: e8f79343cf ("hw/intc: Add RISC-V AIA APLIC device emulation")
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Signed-off-by: yang.zhang <yang.zhang@hexintek.com>
Cc: qemu-stable <qemu-stable@nongnu.org>
Message-ID: <20240409014445.278-1-gaoshanliukou@163.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 hw/intc/riscv_aplic.c | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/hw/intc/riscv_aplic.c b/hw/intc/riscv_aplic.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/intc/riscv_aplic.c
+++ b/hw/intc/riscv_aplic.c
@@ -XXX,XX +XXX,XX @@ DeviceState *riscv_aplic_create(hwaddr addr, hwaddr size,
     qdev_prop_set_bit(dev, "msimode", msimode);
     qdev_prop_set_bit(dev, "mmode", mmode);
 
+    if (parent) {
+        riscv_aplic_add_child(parent, dev);
+    }
+
     sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
 
     if (!is_kvm_aia(msimode)) {
         sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, addr);
     }
 
-    if (parent) {
-        riscv_aplic_add_child(parent, dev);
-    }
-
     if (!msimode) {
         for (i = 0; i < num_harts; i++) {
             CPUState *cpu = cpu_by_arch_id(hartid_base + i);
-- 
2.45.1

From: Andrew Jones <ajones@ventanamicro.com>

The Zkr extension may only be exposed to KVM guests if the VMM
implements the SEED CSR. Use the same implementation as TCG.

Without this patch, running with a KVM which does not forward the
SEED CSR access to QEMU will result in an ILL exception being
injected into the guest (this results in Linux guests crashing on
boot). And, when running with a KVM which does forward the access,
QEMU will crash, since QEMU doesn't know what to do with the exit.

Fixes: 3108e2f1c69d ("target/riscv/kvm: update KVM exts to Linux 6.8")
Signed-off-by: Andrew Jones <ajones@ventanamicro.com>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Cc: qemu-stable <qemu-stable@nongnu.org>
Message-ID: <20240422134605.534207-2-ajones@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/cpu.h         |  3 +++
 target/riscv/csr.c         | 18 ++++++++++++++----
 target/riscv/kvm/kvm-cpu.c | 25 +++++++++++++++++++++++++
 3 files changed, 42 insertions(+), 4 deletions(-)

diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -XXX,XX +XXX,XX @@ void riscv_set_csr_ops(int csrno, riscv_csr_operations *ops);
 
 void riscv_cpu_register_gdb_regs_for_features(CPUState *cs);
 
+target_ulong riscv_new_csr_seed(target_ulong new_value,
+                                target_ulong write_mask);
+
 uint8_t satp_mode_max_from_map(uint32_t map);
 const char *satp_mode_str(uint8_t satp_mode, bool is_32_bit);
 
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -XXX,XX +XXX,XX @@ static RISCVException write_upmbase(CPURISCVState *env, int csrno,
 #endif
 
 /* Crypto Extension */
-static RISCVException rmw_seed(CPURISCVState *env, int csrno,
-                               target_ulong *ret_value,
-                               target_ulong new_value,
-                               target_ulong write_mask)
+target_ulong riscv_new_csr_seed(target_ulong new_value,
+                                target_ulong write_mask)
 {
     uint16_t random_v;
     Error *random_e = NULL;
@@ -XXX,XX +XXX,XX @@ static RISCVException rmw_seed(CPURISCVState *env, int csrno,
         rval = random_v | SEED_OPST_ES16;
     }
 
+    return rval;
+}
+
+static RISCVException rmw_seed(CPURISCVState *env, int csrno,
+                               target_ulong *ret_value,
+                               target_ulong new_value,
+                               target_ulong write_mask)
+{
+    target_ulong rval;
+
+    rval = riscv_new_csr_seed(new_value, write_mask);
+
     if (ret_value) {
         *ret_value = rval;
     }
diff --git a/target/riscv/kvm/kvm-cpu.c b/target/riscv/kvm/kvm-cpu.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/kvm/kvm-cpu.c
+++ b/target/riscv/kvm/kvm-cpu.c
@@ -XXX,XX +XXX,XX @@ static int kvm_riscv_handle_sbi(CPUState *cs, struct kvm_run *run)
     return ret;
 }
 
+static int kvm_riscv_handle_csr(CPUState *cs, struct kvm_run *run)
+{
+    target_ulong csr_num = run->riscv_csr.csr_num;
+    target_ulong new_value = run->riscv_csr.new_value;
+    target_ulong write_mask = run->riscv_csr.write_mask;
+    int ret = 0;
+
+    switch (csr_num) {
+    case CSR_SEED:
+        run->riscv_csr.ret_value = riscv_new_csr_seed(new_value, write_mask);
+        break;
+    default:
+        qemu_log_mask(LOG_UNIMP,
+                      "%s: un-handled CSR EXIT for CSR %lx\n",
+                      __func__, csr_num);
+        ret = -1;
+        break;
+    }
+
+    return ret;
+}
+
 int kvm_arch_handle_exit(CPUState *cs, struct kvm_run *run)
 {
     int ret = 0;
@@ -XXX,XX +XXX,XX @@ int kvm_arch_handle_exit(CPUState *cs, struct kvm_run *run)
     case KVM_EXIT_RISCV_SBI:
         ret = kvm_riscv_handle_sbi(cs, run);
         break;
+    case KVM_EXIT_RISCV_CSR:
+        ret = kvm_riscv_handle_csr(cs, run);
+        break;
     default:
         qemu_log_mask(LOG_UNIMP, "%s: un-handled exit reason %d\n",
                       __func__, run->exit_reason);
-- 
2.45.1

From: Andrew Jones <ajones@ventanamicro.com>

Implementing wrs.nto to always just return is consistent with the
specification, as the instruction is permitted to terminate the
stall for any reason, but it's not useful for virtualization, where
we'd like the guest to trap to the hypervisor in order to allow
scheduling of the lock holding VCPU. Change to always immediately
raise exceptions when the appropriate conditions are present,
otherwise continue to just return. Note, immediately raising
exceptions is also consistent with the specification since the
time limit that should expire prior to the exception is
implementation-specific.

Signed-off-by: Andrew Jones <ajones@ventanamicro.com>
Reviewed-by: Christoph Müllner <christoph.muellner@vrull.eu>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20240424142808.62936-2-ajones@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/helper.h                       |  1 +
 target/riscv/op_helper.c                    | 11 ++++++++
 target/riscv/insn_trans/trans_rvzawrs.c.inc | 29 ++++++++++++++-------
 3 files changed, 32 insertions(+), 9 deletions(-)

diff --git a/target/riscv/helper.h b/target/riscv/helper.h
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/helper.h
+++ b/target/riscv/helper.h
@@ -XXX,XX +XXX,XX @@ DEF_HELPER_6(csrrw_i128, tl, env, int, tl, tl, tl, tl)
 DEF_HELPER_1(sret, tl, env)
 DEF_HELPER_1(mret, tl, env)
 DEF_HELPER_1(wfi, void, env)
+DEF_HELPER_1(wrs_nto, void, env)
 DEF_HELPER_1(tlb_flush, void, env)
 DEF_HELPER_1(tlb_flush_all, void, env)
 /* Native Debug */
diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/op_helper.c
+++ b/target/riscv/op_helper.c
@@ -XXX,XX +XXX,XX @@ void helper_wfi(CPURISCVState *env)
     }
 }
 
+void helper_wrs_nto(CPURISCVState *env)
+{
+    if (env->virt_enabled && (env->priv == PRV_S || env->priv == PRV_U) &&
+        get_field(env->hstatus, HSTATUS_VTW) &&
+        !get_field(env->mstatus, MSTATUS_TW)) {
+        riscv_raise_exception(env, RISCV_EXCP_VIRT_INSTRUCTION_FAULT, GETPC());
+    } else if (env->priv != PRV_M && get_field(env->mstatus, MSTATUS_TW)) {
+        riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC());
+    }
+}
+
 void helper_tlb_flush(CPURISCVState *env)
 {
     CPUState *cs = env_cpu(env);
diff --git a/target/riscv/insn_trans/trans_rvzawrs.c.inc b/target/riscv/insn_trans/trans_rvzawrs.c.inc
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/insn_trans/trans_rvzawrs.c.inc
+++ b/target/riscv/insn_trans/trans_rvzawrs.c.inc
@@ -XXX,XX +XXX,XX @@
  * this program.  If not, see <http://www.gnu.org/licenses/>.
  */
 
-static bool trans_wrs(DisasContext *ctx)
+static bool trans_wrs_sto(DisasContext *ctx, arg_wrs_sto *a)
 {
     if (!ctx->cfg_ptr->ext_zawrs) {
         return false;
@@ -XXX,XX +XXX,XX @@ static bool trans_wrs(DisasContext *ctx)
     return true;
 }
 
-#define GEN_TRANS_WRS(insn)                                     \
-static bool trans_ ## insn(DisasContext *ctx, arg_ ## insn *a)  \
-{                                                               \
-    (void)a;                                                    \
-    return trans_wrs(ctx);                                      \
-}
+static bool trans_wrs_nto(DisasContext *ctx, arg_wrs_nto *a)
+{
+    if (!ctx->cfg_ptr->ext_zawrs) {
+        return false;
+    }
 
-GEN_TRANS_WRS(wrs_nto)
-GEN_TRANS_WRS(wrs_sto)
+    /*
+     * Depending on the mode of execution, mstatus.TW and hstatus.VTW, wrs.nto
+     * should raise an exception when the implementation-specific bounded time
+     * limit has expired. Our time limit is zero, so we either return
+     * immediately, as does our implementation of wrs.sto, or raise an
+     * exception, as handled by the wrs.nto helper.
+     */
+#ifndef CONFIG_USER_ONLY
+    gen_helper_wrs_nto(tcg_env);
+#endif
+
+    /* We only get here when helper_wrs_nto() doesn't raise an exception. */
+    return trans_wrs_sto(ctx, NULL);
+}
-- 
2.45.1

From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>

SBI defines a Debug Console extension "DBCN" that will, in time, replace
the legacy console putchar and getchar SBI extensions.

The appeal of the DBCN extension is that it allows multiple bytes to be
read/written in the SBI console in a single SBI call.

As far as KVM goes, the DBCN calls are forwarded by an in-kernel KVM
module to userspace. But this will only happens if the KVM module
actually supports this SBI extension and we activate it.

We'll check for DBCN support during init time, checking if get-reg-list
is advertising KVM_RISCV_SBI_EXT_DBCN. In that case, we'll enable it via
kvm_set_one_reg() during kvm_arch_init_vcpu().

Finally, change kvm_riscv_handle_sbi() to handle the incoming calls for
SBI_EXT_DBCN, reading and writing as required.

A simple KVM guest with 'earlycon=sbi', running in an emulated RISC-V
host, takes around 20 seconds to boot without using DBCN. With this
patch we're taking around 14 seconds to boot due to the speed-up in the
terminal output.  There's no change in boot time if the guest isn't
using earlycon.

Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Message-ID: <20240425155012.581366-1-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/sbi_ecall_interface.h |  17 +++++
 target/riscv/kvm/kvm-cpu.c         | 111 +++++++++++++++++++++++++++++
 2 files changed, 128 insertions(+)

diff --git a/target/riscv/sbi_ecall_interface.h b/target/riscv/sbi_ecall_interface.h
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/sbi_ecall_interface.h
+++ b/target/riscv/sbi_ecall_interface.h
@@ -XXX,XX +XXX,XX @@
 
 /* clang-format off */
 
+#define SBI_SUCCESS                      0
+#define SBI_ERR_FAILED                  -1
+#define SBI_ERR_NOT_SUPPORTED           -2
+#define SBI_ERR_INVALID_PARAM           -3
+#define SBI_ERR_DENIED                  -4
+#define SBI_ERR_INVALID_ADDRESS         -5
+#define SBI_ERR_ALREADY_AVAILABLE       -6
+#define SBI_ERR_ALREADY_STARTED         -7
+#define SBI_ERR_ALREADY_STOPPED         -8
+#define SBI_ERR_NO_SHMEM                -9
+
 /* SBI Extension IDs */
 #define SBI_EXT_0_1_SET_TIMER           0x0
 #define SBI_EXT_0_1_CONSOLE_PUTCHAR     0x1
@@ -XXX,XX +XXX,XX @@
 #define SBI_EXT_IPI                     0x735049
 #define SBI_EXT_RFENCE                  0x52464E43
 #define SBI_EXT_HSM                     0x48534D
+#define SBI_EXT_DBCN                    0x4442434E
 
 /* SBI function IDs for BASE extension */
 #define SBI_EXT_BASE_GET_SPEC_VERSION   0x0
@@ -XXX,XX +XXX,XX @@
 #define SBI_EXT_HSM_HART_STOP           0x1
 #define SBI_EXT_HSM_HART_GET_STATUS     0x2
 
+/* SBI function IDs for DBCN extension */
+#define SBI_EXT_DBCN_CONSOLE_WRITE      0x0
+#define SBI_EXT_DBCN_CONSOLE_READ       0x1
+#define SBI_EXT_DBCN_CONSOLE_WRITE_BYTE 0x2
+
 #define SBI_HSM_HART_STATUS_STARTED     0x0
 #define SBI_HSM_HART_STATUS_STOPPED     0x1
 #define SBI_HSM_HART_STATUS_START_PENDING   0x2
diff --git a/target/riscv/kvm/kvm-cpu.c b/target/riscv/kvm/kvm-cpu.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/kvm/kvm-cpu.c
+++ b/target/riscv/kvm/kvm-cpu.c
@@ -XXX,XX +XXX,XX @@ static KVMCPUConfig kvm_v_vlenb = {
                    KVM_REG_RISCV_VECTOR_CSR_REG(vlenb)
 };
 
+static KVMCPUConfig kvm_sbi_dbcn = {
+    .name = "sbi_dbcn",
+    .kvm_reg_id = KVM_REG_RISCV | KVM_REG_SIZE_U64 |
+                  KVM_REG_RISCV_SBI_EXT | KVM_RISCV_SBI_EXT_DBCN
+};
+
 static void kvm_riscv_update_cpu_cfg_isa_ext(RISCVCPU *cpu, CPUState *cs)
 {
     CPURISCVState *env = &cpu->env;
@@ -XXX,XX +XXX,XX @@ static int uint64_cmp(const void *a, const void *b)
     return 0;
 }
 
+static void kvm_riscv_check_sbi_dbcn_support(RISCVCPU *cpu,
+                                             KVMScratchCPU *kvmcpu,
+                                             struct kvm_reg_list *reglist)
+{
+    struct kvm_reg_list *reg_search;
+
+    reg_search = bsearch(&kvm_sbi_dbcn.kvm_reg_id, reglist->reg, reglist->n,
+                         sizeof(uint64_t), uint64_cmp);
+
+    if (reg_search) {
+        kvm_sbi_dbcn.supported = true;
+    }
+}
+
 static void kvm_riscv_read_vlenb(RISCVCPU *cpu, KVMScratchCPU *kvmcpu,
                                  struct kvm_reg_list *reglist)
 {
@@ -XXX,XX +XXX,XX @@ static void kvm_riscv_init_multiext_cfg(RISCVCPU *cpu, KVMScratchCPU *kvmcpu)
     if (riscv_has_ext(&cpu->env, RVV)) {
         kvm_riscv_read_vlenb(cpu, kvmcpu, reglist);
     }
+
+    kvm_riscv_check_sbi_dbcn_support(cpu, kvmcpu, reglist);
 }
 
 static void riscv_init_kvm_registers(Object *cpu_obj)
@@ -XXX,XX +XXX,XX @@ static int kvm_vcpu_set_machine_ids(RISCVCPU *cpu, CPUState *cs)
     return ret;
 }
 
+static int kvm_vcpu_enable_sbi_dbcn(RISCVCPU *cpu, CPUState *cs)
+{
+    target_ulong reg = 1;
+
+    if (!kvm_sbi_dbcn.supported) {
+        return 0;
+    }
+
+    return kvm_set_one_reg(cs, kvm_sbi_dbcn.kvm_reg_id, &reg);
+}
+
 int kvm_arch_init_vcpu(CPUState *cs)
 {
     int ret = 0;
@@ -XXX,XX +XXX,XX @@ int kvm_arch_init_vcpu(CPUState *cs)
     kvm_riscv_update_cpu_misa_ext(cpu, cs);
     kvm_riscv_update_cpu_cfg_isa_ext(cpu, cs);
 
+    ret = kvm_vcpu_enable_sbi_dbcn(cpu, cs);
+
     return ret;
 }
 
@@ -XXX,XX +XXX,XX @@ bool kvm_arch_stop_on_emulation_error(CPUState *cs)
     return true;
 }
 
+static void kvm_riscv_handle_sbi_dbcn(CPUState *cs, struct kvm_run *run)
+{
+    g_autofree uint8_t *buf = NULL;
+    RISCVCPU *cpu = RISCV_CPU(cs);
+    target_ulong num_bytes;
+    uint64_t addr;
+    unsigned char ch;
+    int ret;
+
+    switch (run->riscv_sbi.function_id) {
+    case SBI_EXT_DBCN_CONSOLE_READ:
+    case SBI_EXT_DBCN_CONSOLE_WRITE:
+        num_bytes = run->riscv_sbi.args[0];
+
+        if (num_bytes == 0) {
+            run->riscv_sbi.ret[0] = SBI_SUCCESS;
+            run->riscv_sbi.ret[1] = 0;
+            break;
+        }
+
+        addr = run->riscv_sbi.args[1];
+
+        /*
+         * Handle the case where a 32 bit CPU is running in a
+         * 64 bit addressing env.
+         */
+        if (riscv_cpu_mxl(&cpu->env) == MXL_RV32) {
+            addr |= (uint64_t)run->riscv_sbi.args[2] << 32;
+        }
+
+        buf = g_malloc0(num_bytes);
+
+        if (run->riscv_sbi.function_id == SBI_EXT_DBCN_CONSOLE_READ) {
+            ret = qemu_chr_fe_read_all(serial_hd(0)->be, buf, num_bytes);
+            if (ret < 0) {
+                error_report("SBI_EXT_DBCN_CONSOLE_READ: error when "
+                             "reading chardev");
+                exit(1);
+            }
+
+            cpu_physical_memory_write(addr, buf, ret);
+        } else {
+            cpu_physical_memory_read(addr, buf, num_bytes);
+
+            ret = qemu_chr_fe_write_all(serial_hd(0)->be, buf, num_bytes);
+            if (ret < 0) {
+                error_report("SBI_EXT_DBCN_CONSOLE_WRITE: error when "
+                             "writing chardev");
+                exit(1);
+            }
+        }
+
+        run->riscv_sbi.ret[0] = SBI_SUCCESS;
+        run->riscv_sbi.ret[1] = ret;
+        break;
+    case SBI_EXT_DBCN_CONSOLE_WRITE_BYTE:
+        ch = run->riscv_sbi.args[0];
+        ret = qemu_chr_fe_write(serial_hd(0)->be, &ch, sizeof(ch));
+
+        if (ret < 0) {
+            error_report("SBI_EXT_DBCN_CONSOLE_WRITE_BYTE: error when "
+                         "writing chardev");
+            exit(1);
+        }
+
+        run->riscv_sbi.ret[0] = SBI_SUCCESS;
+        run->riscv_sbi.ret[1] = 0;
+        break;
+    default:
+        run->riscv_sbi.ret[0] = SBI_ERR_NOT_SUPPORTED;
+    }
+}
+
 static int kvm_riscv_handle_sbi(CPUState *cs, struct kvm_run *run)
 {
     int ret = 0;
@@ -XXX,XX +XXX,XX @@ static int kvm_riscv_handle_sbi(CPUState *cs, struct kvm_run *run)
         }
         ret = 0;
         break;
+    case SBI_EXT_DBCN:
+        kvm_riscv_handle_sbi_dbcn(cs, run);
+        break;
     default:
         qemu_log_mask(LOG_UNIMP,
                       "%s: un-handled SBI EXIT, specific reasons is %lu\n",
-- 
2.45.1

From: Cheng Yang <yangcheng.work@foxmail.com>

Use qemu_fdt_setprop_u64() instead of qemu_fdt_setprop_cell()
to set the address of initrd in FDT to support 64-bit address.

Signed-off-by: Cheng Yang <yangcheng.work@foxmail.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <tencent_A4482251DD0890F312758FA6B33F60815609@qq.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 hw/riscv/boot.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/hw/riscv/boot.c b/hw/riscv/boot.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/riscv/boot.c
+++ b/hw/riscv/boot.c
@@ -XXX,XX +XXX,XX @@ static void riscv_load_initrd(MachineState *machine, uint64_t kernel_entry)
     /* Some RISC-V machines (e.g. opentitan) don't have a fdt. */
     if (fdt) {
         end = start + size;
-        qemu_fdt_setprop_cell(fdt, "/chosen", "linux,initrd-start", start);
-        qemu_fdt_setprop_cell(fdt, "/chosen", "linux,initrd-end", end);
+        qemu_fdt_setprop_u64(fdt, "/chosen", "linux,initrd-start", start);
+        qemu_fdt_setprop_u64(fdt, "/chosen", "linux,initrd-end", end);
     }
 }
 
-- 
2.45.1

From: Clément Léger <cleger@rivosinc.com>

The current semihost exception number (16) is a reserved number (range
[16-17]). The upcoming double trap specification uses that number for
the double trap exception. Since the privileged spec (Table 22) defines
ranges for custom uses change the semihosting exception number to 63
which belongs to the range [48-63] in order to avoid any future
collisions with reserved exception.

Signed-off-by: Clément Léger <cleger@rivosinc.com>

Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20240422135840.1959967-1-cleger@rivosinc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/cpu_bits.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu_bits.h
+++ b/target/riscv/cpu_bits.h
@@ -XXX,XX +XXX,XX @@ typedef enum RISCVException {
     RISCV_EXCP_INST_PAGE_FAULT = 0xc, /* since: priv-1.10.0 */
     RISCV_EXCP_LOAD_PAGE_FAULT = 0xd, /* since: priv-1.10.0 */
     RISCV_EXCP_STORE_PAGE_FAULT = 0xf, /* since: priv-1.10.0 */
-    RISCV_EXCP_SEMIHOST = 0x10,
     RISCV_EXCP_INST_GUEST_PAGE_FAULT = 0x14,
     RISCV_EXCP_LOAD_GUEST_ACCESS_FAULT = 0x15,
     RISCV_EXCP_VIRT_INSTRUCTION_FAULT = 0x16,
     RISCV_EXCP_STORE_GUEST_AMO_ACCESS_FAULT = 0x17,
+    RISCV_EXCP_SEMIHOST = 0x3f,
 } RISCVException;
 
 #define RISCV_EXCP_INT_FLAG                0x80000000
-- 
2.45.1

From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>

Running a KVM guest using a 6.9-rc3 kernel, in a 6.8 host that has zkr
enabled, will fail with a kernel oops SIGILL right at the start. The
reason is that we can't expose zkr without implementing the SEED CSR.
Disabling zkr in the guest would be a workaround, but if the KVM doesn't
allow it we'll error out and never boot.

In hindsight this is too strict. If we keep proceeding, despite not
disabling the extension in the KVM vcpu, we'll not add the extension in
the riscv,isa. The guest kernel will be unaware of the extension, i.e.
it doesn't matter if the KVM vcpu has it enabled underneath or not. So
it's ok to keep booting in this case.

Change our current logic to not error out if we fail to disable an
extension in kvm_set_one_reg(), but show a warning and keep booting. It
is important to throw a warning because we must make the user aware that
the extension is still available in the vcpu, meaning that an
ill-behaved guest can ignore the riscv,isa settings and  use the
extension.

The case we're handling happens with an EINVAL error code. If we fail to
disable the extension in KVM for any other reason, error out.

We'll also keep erroring out when we fail to enable an extension in KVM,
since adding the extension in riscv,isa at this point will cause a guest
malfunction because the extension isn't enabled in the vcpu.

Suggested-by: Andrew Jones <ajones@ventanamicro.com>
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Cc: qemu-stable <qemu-stable@nongnu.org>
Message-ID: <20240422171425.333037-2-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/kvm/kvm-cpu.c | 12 ++++++++----
 1 file changed, 8 insertions(+), 4 deletions(-)

diff --git a/target/riscv/kvm/kvm-cpu.c b/target/riscv/kvm/kvm-cpu.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/kvm/kvm-cpu.c
+++ b/target/riscv/kvm/kvm-cpu.c
@@ -XXX,XX +XXX,XX @@ static void kvm_riscv_update_cpu_cfg_isa_ext(RISCVCPU *cpu, CPUState *cs)
         reg = kvm_cpu_cfg_get(cpu, multi_ext_cfg);
         ret = kvm_set_one_reg(cs, id, &reg);
         if (ret != 0) {
-            error_report("Unable to %s extension %s in KVM, error %d",
-                         reg ? "enable" : "disable",
-                         multi_ext_cfg->name, ret);
-            exit(EXIT_FAILURE);
+            if (!reg && ret == -EINVAL) {
+                warn_report("KVM cannot disable extension %s",
+                            multi_ext_cfg->name);
+            } else {
+                error_report("Unable to enable extension %s in KVM, error %d",
+                             multi_ext_cfg->name, ret);
+                exit(EXIT_FAILURE);
+            }
         }
     }
 }
-- 
2.45.1

From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>

We're not setting (s/m)tval when triggering breakpoints of type 2
(mcontrol) and 6 (mcontrol6). According to the debug spec section
5.7.12, "Match Control Type 6":

"The Privileged Spec says that breakpoint exceptions that occur on
instruction fetches, loads, or stores update the tval CSR with either
zero or the faulting virtual address. The faulting virtual address for
an mcontrol6 trigger with action = 0 is the address being accessed and
which caused that trigger to fire."

A similar text is also found in the Debug spec section 5.7.11 w.r.t.
mcontrol.

Note that what we're doing ATM is not violating the spec, but it's
simple enough to set mtval/stval and it makes life easier for any
software that relies on this info.

Given that we always use action = 0, save the faulting address for the
mcontrol and mcontrol6 trigger breakpoints into env->badaddr, which is
used as as scratch area for traps with address information. 'tval' is
then set during riscv_cpu_do_interrupt().

Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Message-ID: <20240416230437.1869024-2-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/cpu_helper.c | 1 +
 target/riscv/debug.c      | 3 +++
 2 files changed, 4 insertions(+)

diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -XXX,XX +XXX,XX @@ void riscv_cpu_do_interrupt(CPUState *cs)
             tval = env->bins;
             break;
         case RISCV_EXCP_BREAKPOINT:
+            tval = env->badaddr;
             if (cs->watchpoint_hit) {
                 tval = cs->watchpoint_hit->hitaddr;
                 cs->watchpoint_hit = NULL;
diff --git a/target/riscv/debug.c b/target/riscv/debug.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/debug.c
+++ b/target/riscv/debug.c
@@ -XXX,XX +XXX,XX @@ bool riscv_cpu_debug_check_breakpoint(CPUState *cs)
                 if ((ctrl & TYPE2_EXEC) && (bp->pc == pc)) {
                     /* check U/S/M bit against current privilege level */
                     if ((ctrl >> 3) & BIT(env->priv)) {
+                        env->badaddr = pc;
                         return true;
                     }
                 }
@@ -XXX,XX +XXX,XX @@ bool riscv_cpu_debug_check_breakpoint(CPUState *cs)
                     if (env->virt_enabled) {
                         /* check VU/VS bit against current privilege level */
                         if ((ctrl >> 23) & BIT(env->priv)) {
+                            env->badaddr = pc;
                             return true;
                         }
                     } else {
                         /* check U/S/M bit against current privilege level */
                         if ((ctrl >> 3) & BIT(env->priv)) {
+                            env->badaddr = pc;
                             return true;
                         }
                     }
-- 
2.45.1

From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>

Privileged spec section 4.1.9 mentions:

"When a trap is taken into S-mode, stval is written with
exception-specific information to assist software in handling the trap.
(...)

If stval is written with a nonzero value when a breakpoint,
address-misaligned, access-fault, or page-fault exception occurs on an
instruction fetch, load, or store, then stval will contain the faulting
virtual address."

A similar text is found for mtval in section 3.1.16.

Setting mtval/stval in this scenario is optional, but some softwares read
these regs when handling ebreaks.

Write 'badaddr' in all ebreak breakpoints to write the appropriate
'tval' during riscv_do_cpu_interrrupt().

Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-ID: <20240416230437.1869024-3-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/insn_trans/trans_privileged.c.inc | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/target/riscv/insn_trans/trans_privileged.c.inc b/target/riscv/insn_trans/trans_privileged.c.inc
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/insn_trans/trans_privileged.c.inc
+++ b/target/riscv/insn_trans/trans_privileged.c.inc
@@ -XXX,XX +XXX,XX @@ static bool trans_ebreak(DisasContext *ctx, arg_ebreak *a)
     if (pre == 0x01f01013 && ebreak == 0x00100073 && post == 0x40705013) {
         generate_exception(ctx, RISCV_EXCP_SEMIHOST);
     } else {
+        tcg_gen_st_tl(tcg_constant_tl(ebreak_addr), tcg_env,
+                      offsetof(CPURISCVState, badaddr));
         generate_exception(ctx, RISCV_EXCP_BREAKPOINT);
     }
     return true;
-- 
2.45.1

From: Jason Chien <jason.chien@sifive.com>

Add support for Zve32x extension and replace some checks for Zve32f with
Zve32x, since Zve32f depends on Zve32x.

Signed-off-by: Jason Chien <jason.chien@sifive.com>
Reviewed-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Max Chou <max.chou@sifive.com>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Message-ID: <20240328022343.6871-2-jason.chien@sifive.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/cpu_cfg.h                  |  1 +
 target/riscv/cpu.c                      |  2 ++
 target/riscv/cpu_helper.c               |  2 +-
 target/riscv/csr.c                      |  2 +-
 target/riscv/tcg/tcg-cpu.c              | 16 ++++++++--------
 target/riscv/insn_trans/trans_rvv.c.inc |  4 ++--
 6 files changed, 15 insertions(+), 12 deletions(-)

diff --git a/target/riscv/cpu_cfg.h b/target/riscv/cpu_cfg.h
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu_cfg.h
+++ b/target/riscv/cpu_cfg.h
@@ -XXX,XX +XXX,XX @@ struct RISCVCPUConfig {
     bool ext_zhinx;
     bool ext_zhinxmin;
     bool ext_zve32f;
+    bool ext_zve32x;
     bool ext_zve64f;
     bool ext_zve64d;
     bool ext_zvbb;
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -XXX,XX +XXX,XX @@ const RISCVIsaExtData isa_edata_arr[] = {
     ISA_EXT_DATA_ENTRY(zvbb, PRIV_VERSION_1_12_0, ext_zvbb),
     ISA_EXT_DATA_ENTRY(zvbc, PRIV_VERSION_1_12_0, ext_zvbc),
     ISA_EXT_DATA_ENTRY(zve32f, PRIV_VERSION_1_10_0, ext_zve32f),
+    ISA_EXT_DATA_ENTRY(zve32x, PRIV_VERSION_1_10_0, ext_zve32x),
     ISA_EXT_DATA_ENTRY(zve64f, PRIV_VERSION_1_10_0, ext_zve64f),
     ISA_EXT_DATA_ENTRY(zve64d, PRIV_VERSION_1_10_0, ext_zve64d),
     ISA_EXT_DATA_ENTRY(zvfbfmin, PRIV_VERSION_1_12_0, ext_zvfbfmin),
@@ -XXX,XX +XXX,XX @@ const RISCVCPUMultiExtConfig riscv_cpu_extensions[] = {
     MULTI_EXT_CFG_BOOL("zfh", ext_zfh, false),
     MULTI_EXT_CFG_BOOL("zfhmin", ext_zfhmin, false),
     MULTI_EXT_CFG_BOOL("zve32f", ext_zve32f, false),
+    MULTI_EXT_CFG_BOOL("zve32x", ext_zve32x, false),
     MULTI_EXT_CFG_BOOL("zve64f", ext_zve64f, false),
     MULTI_EXT_CFG_BOOL("zve64d", ext_zve64d, false),
     MULTI_EXT_CFG_BOOL("zvfbfmin", ext_zvfbfmin, false),
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -XXX,XX +XXX,XX @@ void cpu_get_tb_cpu_state(CPURISCVState *env, vaddr *pc,
     *pc = env->xl == MXL_RV32 ? env->pc & UINT32_MAX : env->pc;
     *cs_base = 0;
 
-    if (cpu->cfg.ext_zve32f) {
+    if (cpu->cfg.ext_zve32x) {
         /*
          * If env->vl equals to VLMAX, we can use generic vector operation
          * expanders (GVEC) to accerlate the vector operations.
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -XXX,XX +XXX,XX @@ static RISCVException fs(CPURISCVState *env, int csrno)
 
 static RISCVException vs(CPURISCVState *env, int csrno)
 {
-    if (riscv_cpu_cfg(env)->ext_zve32f) {
+    if (riscv_cpu_cfg(env)->ext_zve32x) {
 #if !defined(CONFIG_USER_ONLY)
         if (!env->debugger && !riscv_cpu_vector_enabled(env)) {
             return RISCV_EXCP_ILLEGAL_INST;
diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/tcg/tcg-cpu.c
+++ b/target/riscv/tcg/tcg-cpu.c
@@ -XXX,XX +XXX,XX @@ void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp)
         return;
     }
 
-    if (cpu->cfg.ext_zve32f && !riscv_has_ext(env, RVF)) {
-        error_setg(errp, "Zve32f/Zve64f extensions require F extension");
-        return;
+    /* The Zve32f extension depends on the Zve32x extension */
+    if (cpu->cfg.ext_zve32f) {
+        if (!riscv_has_ext(env, RVF)) {
+            error_setg(errp, "Zve32f/Zve64f extensions require F extension");
+            return;
+        }
+        cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zve32x), true);
     }
 
     if (cpu->cfg.ext_zvfh) {
@@ -XXX,XX +XXX,XX @@ void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp)
         cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zvbc), true);
     }
 
-    /*
-     * In principle Zve*x would also suffice here, were they supported
-     * in qemu
-     */
     if ((cpu->cfg.ext_zvbb || cpu->cfg.ext_zvkb || cpu->cfg.ext_zvkg ||
          cpu->cfg.ext_zvkned || cpu->cfg.ext_zvknha || cpu->cfg.ext_zvksed ||
-         cpu->cfg.ext_zvksh) && !cpu->cfg.ext_zve32f) {
+         cpu->cfg.ext_zvksh) && !cpu->cfg.ext_zve32x) {
         error_setg(errp,
                    "Vector crypto extensions require V or Zve* extensions");
         return;
diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/insn_trans/trans_rvv.c.inc
+++ b/target/riscv/insn_trans/trans_rvv.c.inc
@@ -XXX,XX +XXX,XX @@ static bool do_vsetvl(DisasContext *s, int rd, int rs1, TCGv s2)
 {
     TCGv s1, dst;
 
-    if (!require_rvv(s) || !s->cfg_ptr->ext_zve32f) {
+    if (!require_rvv(s) || !s->cfg_ptr->ext_zve32x) {
         return false;
     }
 
@@ -XXX,XX +XXX,XX @@ static bool do_vsetivli(DisasContext *s, int rd, TCGv s1, TCGv s2)
 {
     TCGv dst;
 
-    if (!require_rvv(s) || !s->cfg_ptr->ext_zve32f) {
+    if (!require_rvv(s) || !s->cfg_ptr->ext_zve32x) {
         return false;
     }
 
-- 
2.45.1

From: Jason Chien <jason.chien@sifive.com>

Add support for Zve64x extension. Enabling Zve64f enables Zve64x and
enabling Zve64x enables Zve32x according to their dependency.

Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2107
Signed-off-by: Jason Chien <jason.chien@sifive.com>
Reviewed-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Max Chou <max.chou@sifive.com>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Message-ID: <20240328022343.6871-3-jason.chien@sifive.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/cpu_cfg.h     |  1 +
 target/riscv/cpu.c         |  2 ++
 target/riscv/tcg/tcg-cpu.c | 17 +++++++++++------
 3 files changed, 14 insertions(+), 6 deletions(-)

From: Jason Chien <jason.chien@sifive.com>

In current implementation, the gdbstub allows reading vector registers
only if V extension is supported. However, all vector extensions and
vector crypto extensions have the vector registers and they all depend
on Zve32x. The gdbstub should check for Zve32x instead.

Signed-off-by: Jason Chien <jason.chien@sifive.com>
Reviewed-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Max Chou <max.chou@sifive.com>
Message-ID: <20240328022343.6871-4-jason.chien@sifive.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/gdbstub.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/target/riscv/gdbstub.c b/target/riscv/gdbstub.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/gdbstub.c
+++ b/target/riscv/gdbstub.c
@@ -XXX,XX +XXX,XX @@ void riscv_cpu_register_gdb_regs_for_features(CPUState *cs)
                                  gdb_find_static_feature("riscv-32bit-fpu.xml"),
                                  0);
     }
-    if (env->misa_ext & RVV) {
+    if (cpu->cfg.ext_zve32x) {
         gdb_register_coprocessor(cs, riscv_gdb_get_vector,
                                  riscv_gdb_set_vector,
                                  ricsv_gen_dynamic_vector_feature(cs, cs->gdb_num_regs),
-- 
2.45.1

From: Huang Tao <eric.huang@linux.alibaba.com>

In RVV and vcrypto instructions, the masked and tail elements are set to 1s
using vext_set_elems_1s function if the vma/vta bit is set. It is the element
agnostic policy.

However, this function can't deal the big endian situation. This patch fixes
the problem by adding handling of such case.

Signed-off-by: Huang Tao <eric.huang@linux.alibaba.com>
Suggested-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Cc: qemu-stable <qemu-stable@nongnu.org>
Message-ID: <20240325021654.6594-1-eric.huang@linux.alibaba.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/vector_internals.c | 22 ++++++++++++++++++++++
 1 file changed, 22 insertions(+)

diff --git a/target/riscv/vector_internals.c b/target/riscv/vector_internals.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/vector_internals.c
+++ b/target/riscv/vector_internals.c
@@ -XXX,XX +XXX,XX @@ void vext_set_elems_1s(void *base, uint32_t is_agnostic, uint32_t cnt,
     if (tot - cnt == 0) {
         return ;
     }
+
+    if (HOST_BIG_ENDIAN) {
+        /*
+         * Deal the situation when the elements are insdie
+         * only one uint64 block including setting the
+         * masked-off element.
+         */
+        if (((tot - 1) ^ cnt) < 8) {
+            memset(base + H1(tot - 1), -1, tot - cnt);
+            return;
+        }
+        /*
+         * Otherwise, at least cross two uint64_t blocks.
+         * Set first unaligned block.
+         */
+        if (cnt % 8 != 0) {
+            uint32_t j = ROUND_UP(cnt, 8);
+            memset(base + H1(j - 1), -1, j - cnt);
+            cnt = j;
+        }
+        /* Set other 64bit aligend blocks */
+    }
     memset(base + cnt, -1, tot - cnt);
 }
 
-- 
2.45.1

From: Yangyu Chen <cyy@cyyself.name>

This code has a typo that writes zvkb to zvkg, causing users can't
enable zvkb through the config. This patch gets this fixed.

Signed-off-by: Yangyu Chen <cyy@cyyself.name>
Fixes: ea61ef7097d0 ("target/riscv: Move vector crypto extensions to riscv_cpu_extensions")
Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Max Chou <max.chou@sifive.com>
Reviewed-by:  Weiwei Li <liwei1518@gmail.com>
Message-ID: <tencent_7E34EEF0F90B9A68BF38BEE09EC6D4877C0A@qq.com>
Cc: qemu-stable <qemu-stable@nongnu.org>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/cpu.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -XXX,XX +XXX,XX @@ const RISCVCPUMultiExtConfig riscv_cpu_extensions[] = {
     /* Vector cryptography extensions */
     MULTI_EXT_CFG_BOOL("zvbb", ext_zvbb, false),
     MULTI_EXT_CFG_BOOL("zvbc", ext_zvbc, false),
-    MULTI_EXT_CFG_BOOL("zvkb", ext_zvkg, false),
+    MULTI_EXT_CFG_BOOL("zvkb", ext_zvkb, false),
     MULTI_EXT_CFG_BOOL("zvkg", ext_zvkg, false),
     MULTI_EXT_CFG_BOOL("zvkned", ext_zvkned, false),
     MULTI_EXT_CFG_BOOL("zvknha", ext_zvknha, false),
-- 
2.45.1

From: Huang Tao <eric.huang@linux.alibaba.com>

In this patch, we modify the decoder to be a freely composable data
structure instead of a hardcoded one. It can be dynamically builded up
according to the extensions.
This approach has several benefits:
1. Provides support for heterogeneous cpu architectures. As we add decoder in
   RISCVCPU, each cpu can have their own decoder, and the decoders can be
   different due to cpu's features.
2. Improve the decoding efficiency. We run the guard_func to see if the decoder
   can be added to the dynamic_decoder when building up the decoder. Therefore,
   there is no need to run the guard_func when decoding each instruction. It can
   improve the decoding efficiency
3. For vendor or dynamic cpus, it allows them to customize their own decoder
   functions to improve decoding efficiency, especially when vendor-defined
   instruction sets increase. Because of dynamic building up, it can skip the other
   decoder guard functions when decoding.
4. Pre patch for allowing adding a vendor decoder before decode_insn32() with minimal
   overhead for users that don't need this particular vendor decoder.

Signed-off-by: Huang Tao <eric.huang@linux.alibaba.com>
Suggested-by: Christoph Muellner <christoph.muellner@vrull.eu>
Co-authored-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20240506023607.29544-1-eric.huang@linux.alibaba.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/cpu.h         |  1 +
 target/riscv/tcg/tcg-cpu.h | 15 +++++++++++++++
 target/riscv/cpu.c         |  1 +
 target/riscv/tcg/tcg-cpu.c | 15 +++++++++++++++
 target/riscv/translate.c   | 31 +++++++++++++++----------------
 5 files changed, 47 insertions(+), 16 deletions(-)

diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -XXX,XX +XXX,XX @@ struct ArchCPU {
     uint32_t pmu_avail_ctrs;
     /* Mapping of events to counters */
     GHashTable *pmu_event_ctr_map;
+    const GPtrArray *decoders;
 };
 
 /**
diff --git a/target/riscv/tcg/tcg-cpu.h b/target/riscv/tcg/tcg-cpu.h
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/tcg/tcg-cpu.h
+++ b/target/riscv/tcg/tcg-cpu.h
@@ -XXX,XX +XXX,XX @@ void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp);
 void riscv_tcg_cpu_finalize_features(RISCVCPU *cpu, Error **errp);
 bool riscv_cpu_tcg_compatible(RISCVCPU *cpu);
 
+struct DisasContext;
+struct RISCVCPUConfig;
+typedef struct RISCVDecoder {
+    bool (*guard_func)(const struct RISCVCPUConfig *);
+    bool (*riscv_cpu_decode_fn)(struct DisasContext *, uint32_t);
+} RISCVDecoder;
+
+typedef bool (*riscv_cpu_decode_fn)(struct DisasContext *, uint32_t);
+
+extern const size_t decoder_table_size;
+
+extern const RISCVDecoder decoder_table[];
+
+void riscv_tcg_cpu_finalize_dynamic_decoder(RISCVCPU *cpu);
+
 #endif
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -XXX,XX +XXX,XX @@ void riscv_cpu_finalize_features(RISCVCPU *cpu, Error **errp)
             error_propagate(errp, local_err);
             return;
         }
+        riscv_tcg_cpu_finalize_dynamic_decoder(cpu);
     } else if (kvm_enabled()) {
         riscv_kvm_cpu_finalize_features(cpu, &local_err);
         if (local_err != NULL) {
diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/tcg/tcg-cpu.c
+++ b/target/riscv/tcg/tcg-cpu.c
@@ -XXX,XX +XXX,XX @@ void riscv_tcg_cpu_finalize_features(RISCVCPU *cpu, Error **errp)
     }
 }
 
+void riscv_tcg_cpu_finalize_dynamic_decoder(RISCVCPU *cpu)
+{
+    GPtrArray *dynamic_decoders;
+    dynamic_decoders = g_ptr_array_sized_new(decoder_table_size);
+    for (size_t i = 0; i < decoder_table_size; ++i) {
+        if (decoder_table[i].guard_func &&
+            decoder_table[i].guard_func(&cpu->cfg)) {
+            g_ptr_array_add(dynamic_decoders,
+                            (gpointer)decoder_table[i].riscv_cpu_decode_fn);
+        }
+    }
+
+    cpu->decoders = dynamic_decoders;
+}
+
 bool riscv_cpu_tcg_compatible(RISCVCPU *cpu)
 {
     return object_dynamic_cast(OBJECT(cpu), TYPE_RISCV_CPU_HOST) == NULL;
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -XXX,XX +XXX,XX @@
 #include "exec/helper-info.c.inc"
 #undef  HELPER_H
 
+#include "tcg/tcg-cpu.h"
+
 /* global register indices */
 static TCGv cpu_gpr[32], cpu_gprh[32], cpu_pc, cpu_vl, cpu_vstart;
 static TCGv_i64 cpu_fpr[32]; /* assume F and D extensions */
@@ -XXX,XX +XXX,XX @@ typedef struct DisasContext {
     /* FRM is known to contain a valid value. */
     bool frm_valid;
     bool insn_start_updated;
+    const GPtrArray *decoders;
 } DisasContext;
 
 static inline bool has_ext(DisasContext *ctx, uint32_t ext)
@@ -XXX,XX +XXX,XX @@ static inline int insn_len(uint16_t first_word)
     return (first_word & 3) == 3 ? 4 : 2;
 }
 
+const RISCVDecoder decoder_table[] = {
+    { always_true_p, decode_insn32 },
+    { has_xthead_p, decode_xthead},
+    { has_XVentanaCondOps_p, decode_XVentanaCodeOps},
+};
+
+const size_t decoder_table_size = ARRAY_SIZE(decoder_table);
+
 static void decode_opc(CPURISCVState *env, DisasContext *ctx, uint16_t opcode)
 {
-    /*
-     * A table with predicate (i.e., guard) functions and decoder functions
-     * that are tested in-order until a decoder matches onto the opcode.
-     */
-    static const struct {
-        bool (*guard_func)(const RISCVCPUConfig *);
-        bool (*decode_func)(DisasContext *, uint32_t);
-    } decoders[] = {
-        { always_true_p,  decode_insn32 },
-        { has_xthead_p, decode_xthead },
-        { has_XVentanaCondOps_p,  decode_XVentanaCodeOps },
-    };
-
     ctx->virt_inst_excp = false;
     ctx->cur_insn_len = insn_len(opcode);
     /* Check for compressed insn */
@@ -XXX,XX +XXX,XX @@ static void decode_opc(CPURISCVState *env, DisasContext *ctx, uint16_t opcode)
                                              ctx->base.pc_next + 2));
         ctx->opcode = opcode32;
 
-        for (size_t i = 0; i < ARRAY_SIZE(decoders); ++i) {
-            if (decoders[i].guard_func(ctx->cfg_ptr) &&
-                decoders[i].decode_func(ctx, opcode32)) {
+        for (guint i = 0; i < ctx->decoders->len; ++i) {
+            riscv_cpu_decode_fn func = g_ptr_array_index(ctx->decoders, i);
+            if (func(ctx, opcode32)) {
                 return;
             }
         }
@@ -XXX,XX +XXX,XX @@ static void riscv_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs)
     ctx->itrigger = FIELD_EX32(tb_flags, TB_FLAGS, ITRIGGER);
     ctx->zero = tcg_constant_tl(0);
     ctx->virt_inst_excp = false;
+    ctx->decoders = cpu->decoders;
 }
 
 static void riscv_tr_tb_start(DisasContextBase *db, CPUState *cpu)
-- 
2.45.1

From: Christoph Müllner <christoph.muellner@vrull.eu>

The th.sxstatus CSR can be used to identify available custom extension
on T-Head CPUs. The CSR is documented here:
  https://github.com/T-head-Semi/thead-extension-spec/blob/master/xtheadsxstatus.adoc

An important property of this patch is, that the th.sxstatus MAEE field
is not set (indicating that XTheadMae is not available).
XTheadMae is a memory attribute extension (similar to Svpbmt) which is
implemented in many T-Head CPUs (C906, C910, etc.) and utilizes bits
in PTEs that are marked as reserved. QEMU maintainers prefer to not
implement XTheadMae, so we need give kernels a mechanism to identify
if XTheadMae is available in a system or not. And this patch introduces
this mechanism in QEMU in a way that's compatible with real HW
(i.e., probing the th.sxstatus.MAEE bit).

Further context can be found on the list:
https://lists.gnu.org/archive/html/qemu-devel/2024-02/msg00775.html

Reviewed-by: LIU Zhiwei <zhiwe_liu@linux.alibaba.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
Message-ID: <20240429073656.2486732-1-christoph.muellner@vrull.eu>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 MAINTAINERS              |  1 +
 target/riscv/cpu.h       |  3 ++
 target/riscv/cpu.c       |  1 +
 target/riscv/th_csr.c    | 79 ++++++++++++++++++++++++++++++++++++++++
 target/riscv/meson.build |  1 +
 5 files changed, 85 insertions(+)
 create mode 100644 target/riscv/th_csr.c

diff --git a/MAINTAINERS b/MAINTAINERS
index XXXXXXX..XXXXXXX 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -XXX,XX +XXX,XX @@ L: qemu-riscv@nongnu.org
 S: Supported
 F: target/riscv/insn_trans/trans_xthead.c.inc
 F: target/riscv/xthead*.decode
+F: target/riscv/th_*
 F: disas/riscv-xthead*
 
 RISC-V XVentanaCondOps extension
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -XXX,XX +XXX,XX @@ target_ulong riscv_new_csr_seed(target_ulong new_value,
 uint8_t satp_mode_max_from_map(uint32_t map);
 const char *satp_mode_str(uint8_t satp_mode, bool is_32_bit);
 
+/* Implemented in th_csr.c */
+void th_register_custom_csrs(RISCVCPU *cpu);
+
 #endif /* RISCV_CPU_H */
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -XXX,XX +XXX,XX @@ static void rv64_thead_c906_cpu_init(Object *obj)
     cpu->cfg.mvendorid = THEAD_VENDOR_ID;
 #ifndef CONFIG_USER_ONLY
     set_satp_mode_max_supported(cpu, VM_1_10_SV39);
+    th_register_custom_csrs(cpu);
 #endif
 
     /* inherited from parent obj via riscv_cpu_init() */
diff --git a/target/riscv/th_csr.c b/target/riscv/th_csr.c
new file mode 100644
index XXXXXXX..XXXXXXX
--- /dev/null
+++ b/target/riscv/th_csr.c
@@ -XXX,XX +XXX,XX @@
+/*
+ * T-Head-specific CSRs.
+ *
+ * Copyright (c) 2024 VRULL GmbH
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2 or later, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include "qemu/osdep.h"
+#include "cpu.h"
+#include "cpu_vendorid.h"
+
+#define CSR_TH_SXSTATUS 0x5c0
+
+/* TH_SXSTATUS bits */
+#define TH_SXSTATUS_UCME        BIT(16)
+#define TH_SXSTATUS_MAEE        BIT(21)
+#define TH_SXSTATUS_THEADISAEE  BIT(22)
+
+typedef struct {
+    int csrno;
+    int (*insertion_test)(RISCVCPU *cpu);
+    riscv_csr_operations csr_ops;
+} riscv_csr;
+
+static RISCVException smode(CPURISCVState *env, int csrno)
+{
+    if (riscv_has_ext(env, RVS)) {
+        return RISCV_EXCP_NONE;
+    }
+
+    return RISCV_EXCP_ILLEGAL_INST;
+}
+
+static int test_thead_mvendorid(RISCVCPU *cpu)
+{
+    if (cpu->cfg.mvendorid != THEAD_VENDOR_ID) {
+        return -1;
+    }
+
+    return 0;
+}
+
+static RISCVException read_th_sxstatus(CPURISCVState *env, int csrno,
+                                       target_ulong *val)
+{
+    /* We don't set MAEE here, because QEMU does not implement MAEE. */
+    *val = TH_SXSTATUS_UCME | TH_SXSTATUS_THEADISAEE;
+    return RISCV_EXCP_NONE;
+}
+
+static riscv_csr th_csr_list[] = {
+    {
+        .csrno = CSR_TH_SXSTATUS,
+        .insertion_test = test_thead_mvendorid,
+        .csr_ops = { "th.sxstatus", smode, read_th_sxstatus }
+    }
+};
+
+void th_register_custom_csrs(RISCVCPU *cpu)
+{
+    for (size_t i = 0; i < ARRAY_SIZE(th_csr_list); i++) {
+        int csrno = th_csr_list[i].csrno;
+        riscv_csr_operations *csr_ops = &th_csr_list[i].csr_ops;
+        if (!th_csr_list[i].insertion_test(cpu)) {
+            riscv_set_csr_ops(csrno, csr_ops);
+        }
+    }
+}
diff --git a/target/riscv/meson.build b/target/riscv/meson.build
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/meson.build
+++ b/target/riscv/meson.build
@@ -XXX,XX +XXX,XX @@ riscv_system_ss.add(files(
   'monitor.c',
   'machine.c',
   'pmu.c',
+  'th_csr.c',
   'time_helper.c',
   'riscv-qmp-cmds.c',
 ))
-- 
2.45.1

From: Max Chou <max.chou@sifive.com>

According v spec 18.4, only the vfwcvt.f.f.v and vfncvt.f.f.w
instructions will be affected by Zvfhmin extension.
And the vfwcvt.f.f.v and vfncvt.f.f.w instructions only support the
conversions of

* From 1*SEW(16/32) to 2*SEW(32/64)
* From 2*SEW(32/64) to 1*SEW(16/32)

Signed-off-by: Max Chou <max.chou@sifive.com>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Cc: qemu-stable <qemu-stable@nongnu.org>
Message-ID: <20240322092600.1198921-2-max.chou@sifive.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/insn_trans/trans_rvv.c.inc | 20 ++++++++++++++++++--
 1 file changed, 18 insertions(+), 2 deletions(-)

From: Max Chou <max.chou@sifive.com>

The require_scale_rvf function only checks the double width operator for
the vector floating point widen instructions, so most of the widen
checking functions need to add require_rvf for single width operator.

The vfwcvt.f.x.v and vfwcvt.f.xu.v instructions convert single width
integer to double width float, so the opfxv_widen_check function doesn’t
need require_rvf for the single width operator(integer).

Signed-off-by: Max Chou <max.chou@sifive.com>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Cc: qemu-stable <qemu-stable@nongnu.org>
Message-ID: <20240322092600.1198921-3-max.chou@sifive.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/insn_trans/trans_rvv.c.inc | 5 +++++
 1 file changed, 5 insertions(+)

From: Max Chou <max.chou@sifive.com>

If the checking functions check both the single and double width
operators at the same time, then the single width operator checking
functions (require_rvf[min]) will check whether the SEW is 8.

Signed-off-by: Max Chou <max.chou@sifive.com>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Cc: qemu-stable <qemu-stable@nongnu.org>
Message-ID: <20240322092600.1198921-5-max.chou@sifive.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/insn_trans/trans_rvv.c.inc | 16 ++++------------
 1 file changed, 4 insertions(+), 12 deletions(-)

diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/insn_trans/trans_rvv.c.inc
+++ b/target/riscv/insn_trans/trans_rvv.c.inc
@@ -XXX,XX +XXX,XX @@ static bool opfvv_widen_check(DisasContext *s, arg_rmrr *a)
     return require_rvv(s) &&
            require_rvf(s) &&
            require_scale_rvf(s) &&
-           (s->sew != MO_8) &&
            vext_check_isa_ill(s) &&
            vext_check_dss(s, a->rd, a->rs1, a->rs2, a->vm);
 }
@@ -XXX,XX +XXX,XX @@ static bool opfvf_widen_check(DisasContext *s, arg_rmrr *a)
     return require_rvv(s) &&
            require_rvf(s) &&
            require_scale_rvf(s) &&
-           (s->sew != MO_8) &&
            vext_check_isa_ill(s) &&
            vext_check_ds(s, a->rd, a->rs2, a->vm);
 }
@@ -XXX,XX +XXX,XX @@ static bool opfwv_widen_check(DisasContext *s, arg_rmrr *a)
     return require_rvv(s) &&
            require_rvf(s) &&
            require_scale_rvf(s) &&
-           (s->sew != MO_8) &&
            vext_check_isa_ill(s) &&
            vext_check_dds(s, a->rd, a->rs1, a->rs2, a->vm);
 }
@@ -XXX,XX +XXX,XX @@ static bool opfwf_widen_check(DisasContext *s, arg_rmrr *a)
     return require_rvv(s) &&
            require_rvf(s) &&
            require_scale_rvf(s) &&
-           (s->sew != MO_8) &&
            vext_check_isa_ill(s) &&
            vext_check_dd(s, a->rd, a->rs2, a->vm);
 }
@@ -XXX,XX +XXX,XX @@ static bool opffv_widen_check(DisasContext *s, arg_rmr *a)
 {
     return opfv_widen_check(s, a) &&
            require_rvfmin(s) &&
-           require_scale_rvfmin(s) &&
-           (s->sew != MO_8);
+           require_scale_rvfmin(s);
 }
 
 #define GEN_OPFV_WIDEN_TRANS(NAME, CHECK, HELPER, FRM)             \
@@ -XXX,XX +XXX,XX @@ static bool opffv_narrow_check(DisasContext *s, arg_rmr *a)
 {
     return opfv_narrow_check(s, a) &&
            require_rvfmin(s) &&
-           require_scale_rvfmin(s) &&
-           (s->sew != MO_8);
+           require_scale_rvfmin(s);
 }
 
 static bool opffv_rod_narrow_check(DisasContext *s, arg_rmr *a)
 {
     return opfv_narrow_check(s, a) &&
            require_rvf(s) &&
-           require_scale_rvf(s) &&
-           (s->sew != MO_8);
+           require_scale_rvf(s);
 }
 
 #define GEN_OPFV_NARROW_TRANS(NAME, CHECK, HELPER, FRM)            \
@@ -XXX,XX +XXX,XX @@ static bool freduction_widen_check(DisasContext *s, arg_rmrr *a)
 {
     return reduction_widen_check(s, a) &&
            require_rvf(s) &&
-           require_scale_rvf(s) &&
-           (s->sew != MO_8);
+           require_scale_rvf(s);
 }
 
 GEN_OPFVV_WIDEN_TRANS(vfwredusum_vs, freduction_widen_check)
-- 
2.45.1

From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>

raise_mmu_exception(), as is today, is prioritizing guest page faults by
checking first if virt_enabled && !first_stage, and then considering the
regular inst/load/store faults.

There's no mention in the spec about guest page fault being a higher
priority that PMP faults. In fact, privileged spec section 3.7.1 says:

"Attempting to fetch an instruction from a PMP region that does not have
execute permissions raises an instruction access-fault exception.
Attempting to execute a load or load-reserved instruction which accesses
a physical address within a PMP region without read permissions raises a
load access-fault exception. Attempting to execute a store,
store-conditional, or AMO instruction which accesses a physical address
within a PMP region without write permissions raises a store
access-fault exception."

So, in fact, we're doing it wrong - PMP faults should always be thrown,
regardless of also being a first or second stage fault.

The way riscv_cpu_tlb_fill() and get_physical_address() work is
adequate: a TRANSLATE_PMP_FAIL error is immediately reported and
reflected in the 'pmp_violation' flag. What we need is to change
raise_mmu_exception() to prioritize it.

Reported-by: Joseph Chan <jchan@ventanamicro.com>
Fixes: 82d53adfbb ("target/riscv/cpu_helper.c: Invalid exception on MMU translation stage")
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20240413105929.7030-1-alexei.filippov@syntacore.com>
Cc: qemu-stable <qemu-stable@nongnu.org>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/cpu_helper.c | 22 ++++++++++++----------
 1 file changed, 12 insertions(+), 10 deletions(-)

diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -XXX,XX +XXX,XX @@ static void raise_mmu_exception(CPURISCVState *env, target_ulong address,
 
     switch (access_type) {
     case MMU_INST_FETCH:
-        if (env->virt_enabled && !first_stage) {
+        if (pmp_violation) {
+            cs->exception_index = RISCV_EXCP_INST_ACCESS_FAULT;
+        } else if (env->virt_enabled && !first_stage) {
             cs->exception_index = RISCV_EXCP_INST_GUEST_PAGE_FAULT;
         } else {
-            cs->exception_index = pmp_violation ?
-                RISCV_EXCP_INST_ACCESS_FAULT : RISCV_EXCP_INST_PAGE_FAULT;
+            cs->exception_index = RISCV_EXCP_INST_PAGE_FAULT;
         }
         break;
     case MMU_DATA_LOAD:
-        if (two_stage && !first_stage) {
+        if (pmp_violation) {
+            cs->exception_index = RISCV_EXCP_LOAD_ACCESS_FAULT;
+        } else if (two_stage && !first_stage) {
             cs->exception_index = RISCV_EXCP_LOAD_GUEST_ACCESS_FAULT;
         } else {
-            cs->exception_index = pmp_violation ?
-                RISCV_EXCP_LOAD_ACCESS_FAULT : RISCV_EXCP_LOAD_PAGE_FAULT;
+            cs->exception_index = RISCV_EXCP_LOAD_PAGE_FAULT;
         }
         break;
     case MMU_DATA_STORE:
-        if (two_stage && !first_stage) {
+        if (pmp_violation) {
+            cs->exception_index = RISCV_EXCP_STORE_AMO_ACCESS_FAULT;
+        } else if (two_stage && !first_stage) {
             cs->exception_index = RISCV_EXCP_STORE_GUEST_AMO_ACCESS_FAULT;
         } else {
-            cs->exception_index = pmp_violation ?
-                RISCV_EXCP_STORE_AMO_ACCESS_FAULT :
-                RISCV_EXCP_STORE_PAGE_FAULT;
+            cs->exception_index = RISCV_EXCP_STORE_PAGE_FAULT;
         }
         break;
     default:
-- 
2.45.1

From: Alexei Filippov <alexei.filippov@syntacore.com>

Previous patch fixed the PMP priority in raise_mmu_exception() but we're still
setting mtval2 incorrectly. In riscv_cpu_tlb_fill(), after pmp check in 2 stage
translation part, mtval2 will be set in case of successes 2 stage translation but
failed pmp check.

In this case we gonna set mtval2 via env->guest_phys_fault_addr in context of
riscv_cpu_tlb_fill(), as this was a guest-page-fault, but it didn't and mtval2
should be zero, according to RISCV privileged spec sect. 9.4.4: When a guest
page-fault is taken into M-mode, mtval2 is written with either zero or guest
physical address that faulted, shifted by 2 bits. *For other traps, mtval2
is set to zero...*

Signed-off-by: Alexei Filippov <alexei.filippov@syntacore.com>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20240503103052.6819-1-alexei.filippov@syntacore.com>
Cc: qemu-stable <qemu-stable@nongnu.org>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/cpu_helper.c | 12 ++++++------
 1 file changed, 6 insertions(+), 6 deletions(-)

diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -XXX,XX +XXX,XX @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
                               __func__, pa, ret, prot_pmp, tlb_size);
 
                 prot &= prot_pmp;
-            }
-
-            if (ret != TRANSLATE_SUCCESS) {
+            } else {
                 /*
                  * Guest physical address translation failed, this is a HS
                  * level exception
                  */
                 first_stage_error = false;
-                env->guest_phys_fault_addr = (im_address |
-                                              (address &
-                                               (TARGET_PAGE_SIZE - 1))) >> 2;
+                if (ret != TRANSLATE_PMP_FAIL) {
+                    env->guest_phys_fault_addr = (im_address |
+                                                  (address &
+                                                   (TARGET_PAGE_SIZE - 1))) >> 2;
+                }
             }
         }
     } else {
-- 
2.45.1

From: Rob Bradford <rbradford@rivosinc.com>

This extension has now been ratified:
https://jira.riscv.org/browse/RVS-2006 so the "x-" prefix can be
removed.

Since this is now a ratified extension add it to the list of extensions
included in the "max" CPU variant.

Signed-off-by: Rob Bradford <rbradford@rivosinc.com>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Message-ID: <20240514110217.22516-1-rbradford@rivosinc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/cpu.c         | 2 +-
 target/riscv/tcg/tcg-cpu.c | 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -XXX,XX +XXX,XX @@ static const MISAExtInfo misa_ext_info_arr[] = {
     MISA_EXT_INFO(RVJ, "x-j", "Dynamic translated languages"),
     MISA_EXT_INFO(RVV, "v", "Vector operations"),
     MISA_EXT_INFO(RVG, "g", "General purpose (IMAFD_Zicsr_Zifencei)"),
-    MISA_EXT_INFO(RVB, "x-b", "Bit manipulation (Zba_Zbb_Zbs)")
+    MISA_EXT_INFO(RVB, "b", "Bit manipulation (Zba_Zbb_Zbs)")
 };
 
 static void riscv_cpu_validate_misa_mxl(RISCVCPUClass *mcc)
diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/tcg/tcg-cpu.c
+++ b/target/riscv/tcg/tcg-cpu.c
@@ -XXX,XX +XXX,XX @@ static void riscv_init_max_cpu_extensions(Object *obj)
     const RISCVCPUMultiExtConfig *prop;
 
     /* Enable RVG, RVJ and RVV that are disabled by default */
-    riscv_cpu_set_misa_ext(env, env->misa_ext | RVG | RVJ | RVV);
+    riscv_cpu_set_misa_ext(env, env->misa_ext | RVB | RVG | RVJ | RVV);
 
     for (prop = riscv_cpu_extensions; prop && prop->name; prop++) {
         isa_ext_update_enabled(cpu, prop->offset, true);
-- 
2.45.1

From: Alistair Francis <alistair23@gmail.com>

When running the instruction

```
    cbo.flush 0(x0)
```

QEMU would segfault.

The issue was in cpu_gpr[a->rs1] as QEMU does not have cpu_gpr[0]
allocated.

In order to fix this let's use the existing get_address()
helper. This also has the benefit of performing pointer mask
calculations on the address specified in rs1.

The pointer masking specificiation specifically states:

"""
Cache Management Operations: All instructions in Zicbom, Zicbop and Zicboz
"""

So this is the correct behaviour and we previously have been incorrectly
not masking the address.

Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reported-by: Fabian Thomas <fabian.thomas@cispa.de>
Fixes: e05da09b7cfd ("target/riscv: implement Zicbom extension")
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Cc: qemu-stable <qemu-stable@nongnu.org>
Message-ID: <20240514023910.301766-1-alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/insn_trans/trans_rvzicbo.c.inc | 16 ++++++++++++----
 1 file changed, 12 insertions(+), 4 deletions(-)

diff --git a/target/riscv/insn_trans/trans_rvzicbo.c.inc b/target/riscv/insn_trans/trans_rvzicbo.c.inc
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/insn_trans/trans_rvzicbo.c.inc
+++ b/target/riscv/insn_trans/trans_rvzicbo.c.inc
@@ -XXX,XX +XXX,XX @@
 static bool trans_cbo_clean(DisasContext *ctx, arg_cbo_clean *a)
 {
     REQUIRE_ZICBOM(ctx);
-    gen_helper_cbo_clean_flush(tcg_env, cpu_gpr[a->rs1]);
+    TCGv src = get_address(ctx, a->rs1, 0);
+
+    gen_helper_cbo_clean_flush(tcg_env, src);
     return true;
 }
 
 static bool trans_cbo_flush(DisasContext *ctx, arg_cbo_flush *a)
 {
     REQUIRE_ZICBOM(ctx);
-    gen_helper_cbo_clean_flush(tcg_env, cpu_gpr[a->rs1]);
+    TCGv src = get_address(ctx, a->rs1, 0);
+
+    gen_helper_cbo_clean_flush(tcg_env, src);
     return true;
 }
 
 static bool trans_cbo_inval(DisasContext *ctx, arg_cbo_inval *a)
 {
     REQUIRE_ZICBOM(ctx);
-    gen_helper_cbo_inval(tcg_env, cpu_gpr[a->rs1]);
+    TCGv src = get_address(ctx, a->rs1, 0);
+
+    gen_helper_cbo_inval(tcg_env, src);
     return true;
 }
 
 static bool trans_cbo_zero(DisasContext *ctx, arg_cbo_zero *a)
 {
     REQUIRE_ZICBOZ(ctx);
-    gen_helper_cbo_zero(tcg_env, cpu_gpr[a->rs1]);
+    TCGv src = get_address(ctx, a->rs1, 0);
+
+    gen_helper_cbo_zero(tcg_env, src);
     return true;
 }
-- 
2.45.1

From: Yong-Xuan Wang <yongxuan.wang@sifive.com>

In AIA spec, each hart (or each hart within a group) has a unique hart
number to locate the memory pages of interrupt files in the address
space. The number of bits required to represent any hart number is equal
to ceil(log2(hmax + 1)), where hmax is the largest hart number among
groups.

However, if the largest hart number among groups is a power of 2, QEMU
will pass an inaccurate hart-index-bit setting to Linux. For example, when
the guest OS has 4 harts, only ceil(log2(3 + 1)) = 2 bits are sufficient
to represent 4 harts, but we passes 3 to Linux. The code needs to be
updated to ensure accurate hart-index-bit settings.

Additionally, a Linux patch[1] is necessary to correctly recover the hart
index when the guest OS has only 1 hart, where the hart-index-bit is 0.

[1] https://lore.kernel.org/lkml/20240415064905.25184-1-yongxuan.wang@sifive.com/t/

Signed-off-by: Yong-Xuan Wang <yongxuan.wang@sifive.com>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Cc: qemu-stable <qemu-stable@nongnu.org>
Message-ID: <20240515091129.28116-1-yongxuan.wang@sifive.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/kvm/kvm-cpu.c | 9 ++++++++-
 1 file changed, 8 insertions(+), 1 deletion(-)

diff --git a/target/riscv/kvm/kvm-cpu.c b/target/riscv/kvm/kvm-cpu.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/kvm/kvm-cpu.c
+++ b/target/riscv/kvm/kvm-cpu.c
@@ -XXX,XX +XXX,XX @@ void kvm_riscv_aia_create(MachineState *machine, uint64_t group_shift,
         }
     }
 
-    hart_bits = find_last_bit(&max_hart_per_socket, BITS_PER_LONG) + 1;
+
+    if (max_hart_per_socket > 1) {
+        max_hart_per_socket--;
+        hart_bits = find_last_bit(&max_hart_per_socket, BITS_PER_LONG) + 1;
+    } else {
+        hart_bits = 0;
+    }
+
     ret = kvm_device_access(aia_fd, KVM_DEV_RISCV_AIA_GRP_CONFIG,
                             KVM_DEV_RISCV_AIA_CONFIG_HART_BITS,
                             &hart_bits, true, NULL);
-- 
2.45.1

From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>

Commit 33a24910ae changed 'reg_width' to use 'vlenb', i.e. vector length
in bytes, when in this context we want 'reg_width' as the length in
bits.

Fix 'reg_width' back to the value in bits like 7cb59921c05a
("target/riscv/gdbstub.c: use 'vlenb' instead of shifting 'vlen'") set
beforehand.

While we're at it, rename 'reg_width' to 'bitsize' to provide a bit more
clarity about what the variable represents. 'bitsize' is also used in
riscv_gen_dynamic_csr_feature() with the same purpose, i.e. as an input to
gdb_feature_builder_append_reg().

Cc: Akihiko Odaki <akihiko.odaki@daynix.com>
Cc: Alex Bennée <alex.bennee@linaro.org>
Reported-by: Robin Dapp <rdapp.gcc@gmail.com>
Fixes: 33a24910ae ("target/riscv: Use GDBFeature for dynamic XML")
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Acked-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Akihiko Odaki <akihiko.odaki@daynix.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Cc: qemu-stable <qemu-stable@nongnu.org>
Message-ID: <20240517203054.880861-2-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/gdbstub.c | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/target/riscv/gdbstub.c b/target/riscv/gdbstub.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/gdbstub.c
+++ b/target/riscv/gdbstub.c
@@ -XXX,XX +XXX,XX @@ static GDBFeature *riscv_gen_dynamic_csr_feature(CPUState *cs, int base_reg)
 static GDBFeature *ricsv_gen_dynamic_vector_feature(CPUState *cs, int base_reg)
 {
     RISCVCPU *cpu = RISCV_CPU(cs);
-    int reg_width = cpu->cfg.vlenb;
+    int bitsize = cpu->cfg.vlenb << 3;
     GDBFeatureBuilder builder;
     int i;
 
@@ -XXX,XX +XXX,XX @@ static GDBFeature *ricsv_gen_dynamic_vector_feature(CPUState *cs, int base_reg)
 
     /* First define types and totals in a whole VL */
     for (i = 0; i < ARRAY_SIZE(vec_lanes); i++) {
-        int count = reg_width / vec_lanes[i].size;
+        int count = bitsize / vec_lanes[i].size;
         gdb_feature_builder_append_tag(
             &builder, "<vector id=\"%s\" type=\"%s\" count=\"%d\"/>",
             vec_lanes[i].id, vec_lanes[i].gdb_type, count);
@@ -XXX,XX +XXX,XX @@ static GDBFeature *ricsv_gen_dynamic_vector_feature(CPUState *cs, int base_reg)
     /* Define vector registers */
     for (i = 0; i < 32; i++) {
         gdb_feature_builder_append_reg(&builder, g_strdup_printf("v%d", i),
-                                       reg_width, i, "riscv_vector", "vector");
+                                       bitsize, i, "riscv_vector", "vector");
     }
 
     gdb_feature_builder_end(&builder);
-- 
2.45.1

From: Alistair Francis <alistair23@gmail.com>

Previously we only listed a single pmpcfg CSR and the first 16 pmpaddr
CSRs. This patch fixes this to list all 16 pmpcfg and all 64 pmpaddr
CSRs are part of the disassembly.

Reported-by: Eric DeVolder <eric_devolder@yahoo.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Fixes: ea10325917 ("RISC-V Disassembler")
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Cc: qemu-stable <qemu-stable@nongnu.org>
Message-ID: <20240514051615.330979-1-alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 disas/riscv.c | 65 ++++++++++++++++++++++++++++++++++++++++++++++++++-
 1 file changed, 64 insertions(+), 1 deletion(-)

diff --git a/disas/riscv.c b/disas/riscv.c
index XXXXXXX..XXXXXXX 100644
--- a/disas/riscv.c
+++ b/disas/riscv.c
@@ -XXX,XX +XXX,XX @@ static const char *csr_name(int csrno)
     case 0x0383: return "mibound";
     case 0x0384: return "mdbase";
     case 0x0385: return "mdbound";
-    case 0x03a0: return "pmpcfg3";
+    case 0x03a0: return "pmpcfg0";
+    case 0x03a1: return "pmpcfg1";
+    case 0x03a2: return "pmpcfg2";
+    case 0x03a3: return "pmpcfg3";
+    case 0x03a4: return "pmpcfg4";
+    case 0x03a5: return "pmpcfg5";
+    case 0x03a6: return "pmpcfg6";
+    case 0x03a7: return "pmpcfg7";
+    case 0x03a8: return "pmpcfg8";
+    case 0x03a9: return "pmpcfg9";
+    case 0x03aa: return "pmpcfg10";
+    case 0x03ab: return "pmpcfg11";
+    case 0x03ac: return "pmpcfg12";
+    case 0x03ad: return "pmpcfg13";
+    case 0x03ae: return "pmpcfg14";
+    case 0x03af: return "pmpcfg15";
     case 0x03b0: return "pmpaddr0";
     case 0x03b1: return "pmpaddr1";
     case 0x03b2: return "pmpaddr2";
@@ -XXX,XX +XXX,XX @@ static const char *csr_name(int csrno)
     case 0x03bd: return "pmpaddr13";
     case 0x03be: return "pmpaddr14";
     case 0x03bf: return "pmpaddr15";
+    case 0x03c0: return "pmpaddr16";
+    case 0x03c1: return "pmpaddr17";
+    case 0x03c2: return "pmpaddr18";
+    case 0x03c3: return "pmpaddr19";
+    case 0x03c4: return "pmpaddr20";
+    case 0x03c5: return "pmpaddr21";
+    case 0x03c6: return "pmpaddr22";
+    case 0x03c7: return "pmpaddr23";
+    case 0x03c8: return "pmpaddr24";
+    case 0x03c9: return "pmpaddr25";
+    case 0x03ca: return "pmpaddr26";
+    case 0x03cb: return "pmpaddr27";
+    case 0x03cc: return "pmpaddr28";
+    case 0x03cd: return "pmpaddr29";
+    case 0x03ce: return "pmpaddr30";
+    case 0x03cf: return "pmpaddr31";
+    case 0x03d0: return "pmpaddr32";
+    case 0x03d1: return "pmpaddr33";
+    case 0x03d2: return "pmpaddr34";
+    case 0x03d3: return "pmpaddr35";
+    case 0x03d4: return "pmpaddr36";
+    case 0x03d5: return "pmpaddr37";
+    case 0x03d6: return "pmpaddr38";
+    case 0x03d7: return "pmpaddr39";
+    case 0x03d8: return "pmpaddr40";
+    case 0x03d9: return "pmpaddr41";
+    case 0x03da: return "pmpaddr42";
+    case 0x03db: return "pmpaddr43";
+    case 0x03dc: return "pmpaddr44";
+    case 0x03dd: return "pmpaddr45";
+    case 0x03de: return "pmpaddr46";
+    case 0x03df: return "pmpaddr47";
+    case 0x03e0: return "pmpaddr48";
+    case 0x03e1: return "pmpaddr49";
+    case 0x03e2: return "pmpaddr50";
+    case 0x03e3: return "pmpaddr51";
+    case 0x03e4: return "pmpaddr52";
+    case 0x03e5: return "pmpaddr53";
+    case 0x03e6: return "pmpaddr54";
+    case 0x03e7: return "pmpaddr55";
+    case 0x03e8: return "pmpaddr56";
+    case 0x03e9: return "pmpaddr57";
+    case 0x03ea: return "pmpaddr58";
+    case 0x03eb: return "pmpaddr59";
+    case 0x03ec: return "pmpaddr60";
+    case 0x03ed: return "pmpaddr61";
+    case 0x03ee: return "pmpaddr62";
+    case 0x03ef: return "pmpaddr63";
     case 0x0780: return "mtohost";
     case 0x0781: return "mfromhost";
     case 0x0782: return "mreset";
-- 
2.45.1

From: Yu-Ming Chang <yumin686@andestech.com>

Both CSRRS and CSRRC always read the addressed CSR and cause any read side
effects regardless of rs1 and rd fields. Note that if rs1 specifies a register
holding a zero value other than x0, the instruction will still attempt to write
the unmodified value back to the CSR and will cause any attendant side effects.

So if CSRRS or CSRRC tries to write a read-only CSR with rs1 which specifies
a register holding a zero value, an illegal instruction exception should be
raised.

Signed-off-by: Yu-Ming Chang <yumin686@andestech.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20240403070823.80897-1-yumin686@andestech.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/cpu.h       |  4 ++++
 target/riscv/csr.c       | 51 ++++++++++++++++++++++++++++++++++++----
 target/riscv/op_helper.c |  6 ++---
 3 files changed, 53 insertions(+), 8 deletions(-)

diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -XXX,XX +XXX,XX @@ void cpu_get_tb_cpu_state(CPURISCVState *env, vaddr *pc,
 void riscv_cpu_update_mask(CPURISCVState *env);
 bool riscv_cpu_is_32bit(RISCVCPU *cpu);
 
+RISCVException riscv_csrr(CPURISCVState *env, int csrno,
+                          target_ulong *ret_value);
 RISCVException riscv_csrrw(CPURISCVState *env, int csrno,
                            target_ulong *ret_value,
                            target_ulong new_value, target_ulong write_mask);
@@ -XXX,XX +XXX,XX @@ typedef RISCVException (*riscv_csr_op_fn)(CPURISCVState *env, int csrno,
                                           target_ulong new_value,
                                           target_ulong write_mask);
 
+RISCVException riscv_csrr_i128(CPURISCVState *env, int csrno,
+                               Int128 *ret_value);
 RISCVException riscv_csrrw_i128(CPURISCVState *env, int csrno,
                                 Int128 *ret_value,
                                 Int128 new_value, Int128 write_mask);
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -XXX,XX +XXX,XX @@ static RISCVException rmw_seed(CPURISCVState *env, int csrno,
 
 static inline RISCVException riscv_csrrw_check(CPURISCVState *env,
                                                int csrno,
-                                               bool write_mask)
+                                               bool write)
 {
     /* check privileges and return RISCV_EXCP_ILLEGAL_INST if check fails */
     bool read_only = get_field(csrno, 0xC00) == 3;
@@ -XXX,XX +XXX,XX @@ static inline RISCVException riscv_csrrw_check(CPURISCVState *env,
     }
 
     /* read / write check */
-    if (write_mask && read_only) {
+    if (write && read_only) {
         return RISCV_EXCP_ILLEGAL_INST;
     }
 
@@ -XXX,XX +XXX,XX @@ static RISCVException riscv_csrrw_do64(CPURISCVState *env, int csrno,
     return RISCV_EXCP_NONE;
 }
 
+RISCVException riscv_csrr(CPURISCVState *env, int csrno,
+                           target_ulong *ret_value)
+{
+    RISCVException ret = riscv_csrrw_check(env, csrno, false);
+    if (ret != RISCV_EXCP_NONE) {
+        return ret;
+    }
+
+    return riscv_csrrw_do64(env, csrno, ret_value, 0, 0);
+}
+
 RISCVException riscv_csrrw(CPURISCVState *env, int csrno,
                            target_ulong *ret_value,
                            target_ulong new_value, target_ulong write_mask)
 {
-    RISCVException ret = riscv_csrrw_check(env, csrno, write_mask);
+    RISCVException ret = riscv_csrrw_check(env, csrno, true);
     if (ret != RISCV_EXCP_NONE) {
         return ret;
     }
@@ -XXX,XX +XXX,XX @@ static RISCVException riscv_csrrw_do128(CPURISCVState *env, int csrno,
     return RISCV_EXCP_NONE;
 }
 
+RISCVException riscv_csrr_i128(CPURISCVState *env, int csrno,
+                               Int128 *ret_value)
+{
+    RISCVException ret;
+
+    ret = riscv_csrrw_check(env, csrno, false);
+    if (ret != RISCV_EXCP_NONE) {
+        return ret;
+    }
+
+    if (csr_ops[csrno].read128) {
+        return riscv_csrrw_do128(env, csrno, ret_value,
+                                 int128_zero(), int128_zero());
+    }
+
+    /*
+     * Fall back to 64-bit version for now, if the 128-bit alternative isn't
+     * at all defined.
+     * Note, some CSRs don't need to extend to MXLEN (64 upper bits non
+     * significant), for those, this fallback is correctly handling the
+     * accesses
+     */
+    target_ulong old_value;
+    ret = riscv_csrrw_do64(env, csrno, &old_value,
+                           (target_ulong)0,
+                           (target_ulong)0);
+    if (ret == RISCV_EXCP_NONE && ret_value) {
+        *ret_value = int128_make64(old_value);
+    }
+    return ret;
+}
+
 RISCVException riscv_csrrw_i128(CPURISCVState *env, int csrno,
                                 Int128 *ret_value,
                                 Int128 new_value, Int128 write_mask)
 {
     RISCVException ret;
 
-    ret = riscv_csrrw_check(env, csrno, int128_nz(write_mask));
+    ret = riscv_csrrw_check(env, csrno, true);
     if (ret != RISCV_EXCP_NONE) {
         return ret;
     }
diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/op_helper.c
+++ b/target/riscv/op_helper.c
@@ -XXX,XX +XXX,XX @@ target_ulong helper_csrr(CPURISCVState *env, int csr)
     }
 
     target_ulong val = 0;
-    RISCVException ret = riscv_csrrw(env, csr, &val, 0, 0);
+    RISCVException ret = riscv_csrr(env, csr, &val);
 
     if (ret != RISCV_EXCP_NONE) {
         riscv_raise_exception(env, ret, GETPC());
@@ -XXX,XX +XXX,XX @@ target_ulong helper_csrrw(CPURISCVState *env, int csr,
 target_ulong helper_csrr_i128(CPURISCVState *env, int csr)
 {
     Int128 rv = int128_zero();
-    RISCVException ret = riscv_csrrw_i128(env, csr, &rv,
-                                          int128_zero(),
-                                          int128_zero());
+    RISCVException ret = riscv_csrr_i128(env, csr, &rv);
 
     if (ret != RISCV_EXCP_NONE) {
         riscv_raise_exception(env, ret, GETPC());
-- 
2.45.1