[v1] riscv-to-apply queue

[PULL 00/10] riscv-to-apply queue

Alistair Francis posted 10 patches 1 year, 7 months ago

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Maintainers: Palmer Dabbelt <palmer@dabbelt.com>, Alistair Francis <Alistair.Francis@wdc.com>, Peter Maydell <peter.maydell@linaro.org>, Bin Meng <bin.meng@windriver.com>, Xiaojuan Yang <yangxiaojuan@loongson.cn>, Song Gao <gaosong@loongson.cn>, "Philippe Mathieu-Daudé" <f4bug@amsat.org>, Gerd Hoffmann <kraxel@redhat.com>

There is a newer version of this series

include/hw/nvram/fw_cfg.h      |   21 +
include/hw/riscv/boot.h        |    1 +
include/hw/ssi/ibex_spi_host.h |    4 +-
disas/riscv.c                  | 1432 +++++++++++++++++++++++++++++++++++++++-
hw/arm/boot.c                  |   49 --
hw/intc/sifive_plic.c          |   25 +-
hw/loongarch/virt.c            |   33 -
hw/nvram/fw_cfg.c              |   32 +
hw/riscv/boot.c                |   33 +-
hw/riscv/virt.c                |   32 +-
hw/ssi/ibex_spi_host.c         |  166 +++--
target/riscv/pmp.c             |   12 +
12 files changed, 1675 insertions(+), 165 deletions(-)

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[PULL 00/10] riscv-to-apply queue

Posted by Alistair Francis 1 year, 7 months ago

From: Alistair Francis <alistair.francis@wdc.com>

The following changes since commit 2ba341b3694cf3cff7b8a1df4cc765900d5c4f60:

  Merge tag 'kraxel-20221013-pull-request' of https://gitlab.com/kraxel/qemu into staging (2022-10-13 13:55:53 -0400)

are available in the Git repository at:

  https://github.com/alistair23/qemu.git tags/pull-riscv-to-apply-20221014

for you to fetch changes up to 47566421f029b0a489b63f8195b3ff944e017056:

  target/riscv: pmp: Fixup TLB size calculation (2022-10-14 14:36:19 +1000)

----------------------------------------------------------------
Third RISC-V PR for QEMU 7.2

* Update qtest comment
* Fix coverity issue with Ibex SPI
* Move load_image_to_fw_cfg() to common location
* Enable booting S-mode firmware from pflash on virt machine
* Add disas support for vector instructions
* Priority level fixes for PLIC
* Fixup TLB size calculation when using PMP

----------------------------------------------------------------
Alistair Francis (1):
      target/riscv: pmp: Fixup TLB size calculation

Bin Meng (1):
      hw/riscv: Update comment for qtest check in riscv_find_firmware()

Jim Shu (2):
      hw/intc: sifive_plic: fix hard-coded max priority level
      hw/intc: sifive_plic: change interrupt priority register to WARL field

Sunil V L (3):
      hw/arm, loongarch: Move load_image_to_fw_cfg() to common location
      hw/riscv: virt: Move create_fw_cfg() prior to loading kernel
      hw/riscv: virt: Enable booting S-mode firmware from pflash

Wilfred Mallawa (2):
      hw/ssi: ibex_spi: fixup coverity issue
      hw/ssi: ibex_spi: fixup/add rw1c functionality

Yang Liu (1):
      disas/riscv.c: rvv: Add disas support for vector instructions

 include/hw/nvram/fw_cfg.h      |   21 +
 include/hw/riscv/boot.h        |    1 +
 include/hw/ssi/ibex_spi_host.h |    4 +-
 disas/riscv.c                  | 1432 +++++++++++++++++++++++++++++++++++++++-
 hw/arm/boot.c                  |   49 --
 hw/intc/sifive_plic.c          |   25 +-
 hw/loongarch/virt.c            |   33 -
 hw/nvram/fw_cfg.c              |   32 +
 hw/riscv/boot.c                |   33 +-
 hw/riscv/virt.c                |   32 +-
 hw/ssi/ibex_spi_host.c         |  166 +++--
 target/riscv/pmp.c             |   12 +
 12 files changed, 1675 insertions(+), 165 deletions(-)

Re: [PULL 00/10] riscv-to-apply queue

Posted by Stefan Hajnoczi 1 year, 7 months ago

Applied, thanks.

Please update the changelog at https://wiki.qemu.org/ChangeLog/7.2 for any user-visible changes.