On Sat, 1 Oct 2022 at 17:54, Richard Henderson
<richard.henderson@linaro.org> wrote:
>
> Copy attrs and sharability, into the TLB. This will eventually
"shareability" is how the Arm ARM spells it.
> be used by S1_ptw_translate to report stage1 translation failures,
> and by do_ats_write to fill in PAR_EL1.
>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> ---
> target/arm/cpu-param.h | 8 ++++++++
> target/arm/tlb_helper.c | 3 +++
> 2 files changed, 11 insertions(+)
>
> diff --git a/target/arm/cpu-param.h b/target/arm/cpu-param.h
> index 08681828ac..118ca0e5c0 100644
> --- a/target/arm/cpu-param.h
> +++ b/target/arm/cpu-param.h
> @@ -30,6 +30,14 @@
> */
> # define TARGET_PAGE_BITS_VARY
> # define TARGET_PAGE_BITS_MIN 10
> +
> +/*
> + * Cache the attrs and sharability fields from the page table entry.
"shareability".
We should document the format of these fields, similarly to
how the ARMCacheAttrs struct does. In particular, do we guarantee
at the point we fill this in that pte_attrs is in the MAIR_EL1
8-bit format and never the S2 descriptor-bits format?
> + */
> +# define TARGET_PAGE_ENTRY_EXTRA \
> + uint8_t pte_attrs; \
> + uint8_t shareability;
> +
> #endif
>
> #define NB_MMU_MODES 8
> diff --git a/target/arm/tlb_helper.c b/target/arm/tlb_helper.c
> index 49601394ec..353edbeb1d 100644
> --- a/target/arm/tlb_helper.c
> +++ b/target/arm/tlb_helper.c
> @@ -236,6 +236,9 @@ bool arm_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
> arm_tlb_mte_tagged(&res.f.attrs) = true;
> }
>
> + res.f.pte_attrs = res.cacheattrs.attrs;
> + res.f.shareability = res.cacheattrs.shareability;
> +
> tlb_set_page_full(cs, mmu_idx, address, &res.f);
> return true;
> } else if (probe) {
> --
Otherwise
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
thanks
-- PMM