[PULL 00/10] target-arm queue
[PULL 00/24] target-arm queue
1
Hi; not so many patches in this one, but notably it includes the
1
Hi; here's the latest round of arm patches. I have included also
2
fix for various Avocado CI tests failing (incorrectly reported by
2
my patchset for the RTC devices to avoid keeping time_t and
3
Avocado as a timeout, but really a QEMU exit-with-error).
3
time_t diffs in 32-bit variables.
4
4
5
thanks
5
thanks
6
-- PMM
6
-- PMM
7
7
8
The following changes since commit c8de6ec63d766ca1998c5af468483ce912fdc0c2:
8
The following changes since commit 156618d9ea67f2f2e31d9dedd97f2dcccbe6808c:
9
9
10
Merge tag 'pull-request-2022-09-28' of https://gitlab.com/thuth/qemu into staging (2022-09-28 17:04:11 -0400)
10
Merge tag 'block-pull-request' of https://gitlab.com/stefanha/qemu into staging (2023-08-30 09:20:27 -0400)
11
11
12
are available in the Git repository at:
12
are available in the Git repository at:
13
13
14
https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20220930
14
https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20230831
15
15
16
for you to fetch changes up to beeec926d24aac28f95cc7694ef3837d7a4cd3bb:
16
for you to fetch changes up to e73b8bb8a3e9a162f70e9ffbf922d4fafc96bbfb:
17
17
18
target/arm: mark SP_EL1 with ARM_CP_EL3_NO_EL2_KEEP (2022-09-29 18:01:09 +0100)
18
hw/arm: Set number of MPU regions correctly for an505, an521, an524 (2023-08-31 11:07:02 +0100)
19
19
20
----------------------------------------------------------------
20
----------------------------------------------------------------
21
target-arm queue:
21
target-arm queue:
22
* Fix breakage of icount mode when guest touches MDCR_EL3, MDCR_EL2,
22
* Some of the preliminary patches for Cortex-A710 support
23
PMCNTENSET_EL0 or PMCNTENCLR_EL0
23
* i.MX7 and i.MX6UL refactoring
24
* Make writes to MDCR_EL3 use PMU start/finish calls
24
* Implement SRC device for i.MX7
25
* Let AArch32 write to SDCR.SCCD
25
* Catch illegal-exception-return from EL3 with bad NSE/NS
26
* Rearrange cpu64.c so all the CPU initfns are together
26
* Use 64-bit offsets for holding time_t differences in RTC devices
27
* hw/arm/xlnx-zynqmp: Connect ZynqMP's USB controllers
27
* Model correct number of MPU regions for an505, an521, an524 boards
28
* hw/arm/virt: fix some minor issues with generated device tree
29
* Fix regression where EL3 could not write to SP_EL1 if there is no EL2
30
28
31
----------------------------------------------------------------
29
----------------------------------------------------------------
32
Francisco Iglesias (1):
30
Alex Bennée (1):
33
hw/arm/xlnx-zynqmp: Connect ZynqMP's USB controllers
31
target/arm: properly document FEAT_CRC32
34
32
35
Jean-Philippe Brucker (4):
33
Jean-Christophe Dubois (6):
36
hw/arm/virt: Fix devicetree warning about the root node
34
Remove i.MX7 IOMUX GPR device from i.MX6UL
37
hw/arm/virt: Fix devicetree warning about the GIC node
35
Refactor i.MX6UL processor code
38
hw/arm/virt: Use "msi-map" devicetree property for PCI
36
Add i.MX6UL missing devices.
39
hw/arm/virt: Fix devicetree warning about the SMMU node
37
Refactor i.MX7 processor code
38
Add i.MX7 missing TZ devices and memory regions
39
Add i.MX7 SRC device implementation
40
40
41
Jerome Forissier (1):
41
Peter Maydell (8):
42
target/arm: mark SP_EL1 with ARM_CP_EL3_NO_EL2_KEEP
42
target/arm: Catch illegal-exception-return from EL3 with bad NSE/NS
43
hw/rtc/m48t59: Use 64-bit arithmetic in set_alarm()
44
hw/rtc/twl92230: Use int64_t for sec_offset and alm_sec
45
hw/rtc/aspeed_rtc: Use 64-bit offset for holding time_t difference
46
rtc: Use time_t for passing and returning time offsets
47
target/arm: Do all "ARM_FEATURE_X implies Y" checks in post_init
48
hw/arm/armv7m: Add mpu-ns-regions and mpu-s-regions properties
49
hw/arm: Set number of MPU regions correctly for an505, an521, an524
43
50
44
Peter Maydell (4):
51
Richard Henderson (9):
45
target/arm: Mark registers which call pmu_op_start() as ARM_CP_IO
52
target/arm: Reduce dcz_blocksize to uint8_t
46
target/arm: Make writes to MDCR_EL3 use PMU start/finish calls
53
target/arm: Allow cpu to configure GM blocksize
47
target/arm: Update SDCR_VALID_MASK to include SCCD
54
target/arm: Support more GM blocksizes
48
target/arm: Rearrange cpu64.c so all the CPU initfns are together
55
target/arm: When tag memory is not present, set MTE=1
56
target/arm: Introduce make_ccsidr64
57
target/arm: Apply access checks to neoverse-n1 special registers
58
target/arm: Apply access checks to neoverse-v1 special registers
59
target/arm: Suppress FEAT_TRBE (Trace Buffer Extension)
60
target/arm: Implement FEAT_HPDS2 as a no-op
49
61
50
include/hw/arm/xlnx-zynqmp.h | 3 +
62
docs/system/arm/emulation.rst | 2 +
51
target/arm/cpu.h | 8 +-
63
include/hw/arm/armsse.h | 5 +
52
hw/arm/virt.c | 8 +-
64
include/hw/arm/armv7m.h | 8 +
53
hw/arm/xlnx-zynqmp.c | 36 +++
65
include/hw/arm/fsl-imx6ul.h | 158 ++++++++++++++++---
54
target/arm/cpu64.c | 712 +++++++++++++++++++++----------------------
66
include/hw/arm/fsl-imx7.h | 338 ++++++++++++++++++++++++++++++-----------
55
target/arm/helper.c | 32 +-
67
include/hw/misc/imx7_src.h | 66 ++++++++
56
6 files changed, 427 insertions(+), 372 deletions(-)
68
include/hw/rtc/aspeed_rtc.h | 2 +-
69
include/sysemu/rtc.h | 4 +-
70
target/arm/cpregs.h | 2 +
71
target/arm/cpu.h | 5 +-
72
target/arm/internals.h | 6 -
73
target/arm/tcg/translate.h | 2 +
74
hw/arm/armsse.c | 16 ++
75
hw/arm/armv7m.c | 21 +++
76
hw/arm/fsl-imx6ul.c | 174 +++++++++++++--------
77
hw/arm/fsl-imx7.c | 201 +++++++++++++++++++-----
78
hw/arm/mps2-tz.c | 29 ++++
79
hw/misc/imx7_src.c | 276 +++++++++++++++++++++++++++++++++
80
hw/rtc/aspeed_rtc.c | 5 +-
81
hw/rtc/m48t59.c | 2 +-
82
hw/rtc/twl92230.c | 4 +-
83
softmmu/rtc.c | 4 +-
84
target/arm/cpu.c | 207 ++++++++++++++-----------
85
target/arm/helper.c | 15 +-
86
target/arm/tcg/cpu32.c | 2 +-
87
target/arm/tcg/cpu64.c | 102 +++++++++----
88
target/arm/tcg/helper-a64.c | 9 ++
89
target/arm/tcg/mte_helper.c | 90 ++++++++---
90
target/arm/tcg/translate-a64.c | 5 +-
91
hw/misc/meson.build | 1 +
92
hw/misc/trace-events | 4 +
93
31 files changed, 1393 insertions(+), 372 deletions(-)
94
create mode 100644 include/hw/misc/imx7_src.h
95
create mode 100644 hw/misc/imx7_src.c
96
diff view generated by jsdifflib
[PULL 03/10] target/arm: Update SDCR_VALID_MASK to include SCCD
[PULL 01/24] target/arm: Reduce dcz_blocksize to uint8_t
1
Our SDCR_VALID_MASK doesn't include all of the bits which are defined
1
From: Richard Henderson <richard.henderson@linaro.org>
2
by the current architecture. In particular in commit 0b42f4fab9d3 we
3
forgot to add SCCD, which meant that an AArch32 guest couldn't
4
actually use the SCCD bit to disable counting in Secure state.
5
2
6
Add all the currently defined bits; we don't implement all of them,
3
This value is only 4 bits wide.
7
but this makes them be reads-as-written, which is architecturally
8
valid and matches how we currently handle most of the others in the
9
mask.
10
4
5
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
6
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
7
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
8
Message-id: 20230811214031.171020-2-richard.henderson@linaro.org
11
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
12
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
13
Message-id: 20220923123412.1214041-4-peter.maydell@linaro.org
14
---
10
---
15
target/arm/cpu.h | 8 +++++++-
11
target/arm/cpu.h | 3 ++-
16
1 file changed, 7 insertions(+), 1 deletion(-)
12
1 file changed, 2 insertions(+), 1 deletion(-)
17
13
18
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
14
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
19
index XXXXXXX..XXXXXXX 100644
15
index XXXXXXX..XXXXXXX 100644
20
--- a/target/arm/cpu.h
16
--- a/target/arm/cpu.h
21
+++ b/target/arm/cpu.h
17
+++ b/target/arm/cpu.h
22
@@ -XXX,XX +XXX,XX @@ FIELD(CPTR_EL3, TTA, 20, 1)
18
@@ -XXX,XX +XXX,XX @@ struct ArchCPU {
23
FIELD(CPTR_EL3, TAM, 30, 1)
19
bool prop_lpa2;
24
FIELD(CPTR_EL3, TCPAC, 31, 1)
20
25
21
/* DCZ blocksize, in log_2(words), ie low 4 bits of DCZID_EL0 */
26
+#define MDCR_MTPME (1U << 28)
22
- uint32_t dcz_blocksize;
27
+#define MDCR_TDCC (1U << 27)
23
+ uint8_t dcz_blocksize;
28
#define MDCR_HLP (1U << 26) /* MDCR_EL2 */
24
+
29
#define MDCR_SCCD (1U << 23) /* MDCR_EL3 */
25
uint64_t rvbar_prop; /* Property/input signals. */
30
#define MDCR_HCCD (1U << 23) /* MDCR_EL2 */
26
31
#define MDCR_EPMAD (1U << 21)
27
/* Configurable aspects of GIC cpu interface (which is part of the CPU) */
32
#define MDCR_EDAD (1U << 20)
33
+#define MDCR_TTRF (1U << 19)
34
+#define MDCR_STE (1U << 18) /* MDCR_EL3 */
35
#define MDCR_SPME (1U << 17) /* MDCR_EL3 */
36
#define MDCR_HPMD (1U << 17) /* MDCR_EL2 */
37
#define MDCR_SDD (1U << 16)
38
@@ -XXX,XX +XXX,XX @@ FIELD(CPTR_EL3, TCPAC, 31, 1)
39
#define MDCR_HPMN (0x1fU)
40
41
/* Not all of the MDCR_EL3 bits are present in the 32-bit SDCR */
42
-#define SDCR_VALID_MASK (MDCR_EPMAD | MDCR_EDAD | MDCR_SPME | MDCR_SPD)
43
+#define SDCR_VALID_MASK (MDCR_MTPME | MDCR_TDCC | MDCR_SCCD | \
44
+ MDCR_EPMAD | MDCR_EDAD | MDCR_TTRF | \
45
+ MDCR_STE | MDCR_SPME | MDCR_SPD)
46
47
#define CPSR_M (0x1fU)
48
#define CPSR_T (1U << 5)
49
--
28
--
50
2.25.1
29
2.34.1
30
31
diff view generated by jsdifflib
[PULL 10/10] target/arm: mark SP_EL1 with ARM_CP_EL3_NO_EL2_KEEP
[PULL 02/24] target/arm: Allow cpu to configure GM blocksize
1
From: Jerome Forissier <jerome.forissier@linaro.org>
1
From: Richard Henderson <richard.henderson@linaro.org>
2
2
3
SP_EL1 must be kept when EL3 is present but EL2 is not. Therefore mark
3
Previously we hard-coded the blocksize with GMID_EL1_BS.
4
it with ARM_CP_EL3_NO_EL2_KEEP.
4
But the value we choose for -cpu max does not match the
5
5
value that cortex-a710 uses.
6
Cc: qemu-stable@nongnu.org
6
7
Fixes: 696ba3771894 ("target/arm: Handle cpreg registration for missing EL")
7
Mirror the way we handle dcz_blocksize.
8
Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>
8
9
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
9
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
10
Message-id: 20220927120058.670901-1-jerome.forissier@linaro.org
10
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
11
Message-id: 20230811214031.171020-3-richard.henderson@linaro.org
11
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
12
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
12
---
13
---
13
target/arm/helper.c | 2 +-
14
target/arm/cpu.h | 2 ++
14
1 file changed, 1 insertion(+), 1 deletion(-)
15
target/arm/internals.h | 6 -----
15
16
target/arm/tcg/translate.h | 2 ++
17
target/arm/helper.c | 11 +++++---
18
target/arm/tcg/cpu64.c | 1 +
19
target/arm/tcg/mte_helper.c | 46 ++++++++++++++++++++++------------
20
target/arm/tcg/translate-a64.c | 5 ++--
21
7 files changed, 45 insertions(+), 28 deletions(-)
22
23
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
24
index XXXXXXX..XXXXXXX 100644
25
--- a/target/arm/cpu.h
26
+++ b/target/arm/cpu.h
27
@@ -XXX,XX +XXX,XX @@ struct ArchCPU {
28
29
/* DCZ blocksize, in log_2(words), ie low 4 bits of DCZID_EL0 */
30
uint8_t dcz_blocksize;
31
+ /* GM blocksize, in log_2(words), ie low 4 bits of GMID_EL0 */
32
+ uint8_t gm_blocksize;
33
34
uint64_t rvbar_prop; /* Property/input signals. */
35
36
diff --git a/target/arm/internals.h b/target/arm/internals.h
37
index XXXXXXX..XXXXXXX 100644
38
--- a/target/arm/internals.h
39
+++ b/target/arm/internals.h
40
@@ -XXX,XX +XXX,XX @@ void arm_log_exception(CPUState *cs);
41
42
#endif /* !CONFIG_USER_ONLY */
43
44
-/*
45
- * The log2 of the words in the tag block, for GMID_EL1.BS.
46
- * The is the maximum, 256 bytes, which manipulates 64-bits of tags.
47
- */
48
-#define GMID_EL1_BS 6
49
-
50
/*
51
* SVE predicates are 1/8 the size of SVE vectors, and cannot use
52
* the same simd_desc() encoding due to restrictions on size.
53
diff --git a/target/arm/tcg/translate.h b/target/arm/tcg/translate.h
54
index XXXXXXX..XXXXXXX 100644
55
--- a/target/arm/tcg/translate.h
56
+++ b/target/arm/tcg/translate.h
57
@@ -XXX,XX +XXX,XX @@ typedef struct DisasContext {
58
int8_t btype;
59
/* A copy of cpu->dcz_blocksize. */
60
uint8_t dcz_blocksize;
61
+ /* A copy of cpu->gm_blocksize. */
62
+ uint8_t gm_blocksize;
63
/* True if this page is guarded. */
64
bool guarded_page;
65
/* Bottom two bits of XScale c15_cpar coprocessor access control reg */
16
diff --git a/target/arm/helper.c b/target/arm/helper.c
66
diff --git a/target/arm/helper.c b/target/arm/helper.c
17
index XXXXXXX..XXXXXXX 100644
67
index XXXXXXX..XXXXXXX 100644
18
--- a/target/arm/helper.c
68
--- a/target/arm/helper.c
19
+++ b/target/arm/helper.c
69
+++ b/target/arm/helper.c
20
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo v8_cp_reginfo[] = {
70
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo mte_reginfo[] = {
21
.fieldoffset = offsetof(CPUARMState, sp_el[0]) },
71
.opc0 = 3, .opc1 = 0, .crn = 1, .crm = 0, .opc2 = 6,
22
{ .name = "SP_EL1", .state = ARM_CP_STATE_AA64,
72
.access = PL1_RW, .accessfn = access_mte,
23
.opc0 = 3, .opc1 = 4, .crn = 4, .crm = 1, .opc2 = 0,
73
.fieldoffset = offsetof(CPUARMState, cp15.gcr_el1) },
24
- .access = PL2_RW, .type = ARM_CP_ALIAS,
74
- { .name = "GMID_EL1", .state = ARM_CP_STATE_AA64,
25
+ .access = PL2_RW, .type = ARM_CP_ALIAS | ARM_CP_EL3_NO_EL2_KEEP,
75
- .opc0 = 3, .opc1 = 1, .crn = 0, .crm = 0, .opc2 = 4,
26
.fieldoffset = offsetof(CPUARMState, sp_el[1]) },
76
- .access = PL1_R, .accessfn = access_aa64_tid5,
27
{ .name = "SPSel", .state = ARM_CP_STATE_AA64,
77
- .type = ARM_CP_CONST, .resetvalue = GMID_EL1_BS },
28
.opc0 = 3, .opc1 = 0, .crn = 4, .crm = 2, .opc2 = 0,
78
{ .name = "TCO", .state = ARM_CP_STATE_AA64,
79
.opc0 = 3, .opc1 = 3, .crn = 4, .crm = 2, .opc2 = 7,
80
.type = ARM_CP_NO_RAW,
81
@@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu)
82
* then define only a RAZ/WI version of PSTATE.TCO.
83
*/
84
if (cpu_isar_feature(aa64_mte, cpu)) {
85
+ ARMCPRegInfo gmid_reginfo = {
86
+ .name = "GMID_EL1", .state = ARM_CP_STATE_AA64,
87
+ .opc0 = 3, .opc1 = 1, .crn = 0, .crm = 0, .opc2 = 4,
88
+ .access = PL1_R, .accessfn = access_aa64_tid5,
89
+ .type = ARM_CP_CONST, .resetvalue = cpu->gm_blocksize,
90
+ };
91
+ define_one_arm_cp_reg(cpu, &gmid_reginfo);
92
define_arm_cp_regs(cpu, mte_reginfo);
93
define_arm_cp_regs(cpu, mte_el0_cacheop_reginfo);
94
} else if (cpu_isar_feature(aa64_mte_insn_reg, cpu)) {
95
diff --git a/target/arm/tcg/cpu64.c b/target/arm/tcg/cpu64.c
96
index XXXXXXX..XXXXXXX 100644
97
--- a/target/arm/tcg/cpu64.c
98
+++ b/target/arm/tcg/cpu64.c
99
@@ -XXX,XX +XXX,XX @@ void aarch64_max_tcg_initfn(Object *obj)
100
cpu->ctr = 0x80038003; /* 32 byte I and D cacheline size, VIPT icache */
101
cpu->dcz_blocksize = 7; /* 512 bytes */
102
#endif
103
+ cpu->gm_blocksize = 6; /* 256 bytes */
104
105
cpu->sve_vq.supported = MAKE_64BIT_MASK(0, ARM_MAX_VQ);
106
cpu->sme_vq.supported = SVE_VQ_POW2_MAP;
107
diff --git a/target/arm/tcg/mte_helper.c b/target/arm/tcg/mte_helper.c
108
index XXXXXXX..XXXXXXX 100644
109
--- a/target/arm/tcg/mte_helper.c
110
+++ b/target/arm/tcg/mte_helper.c
111
@@ -XXX,XX +XXX,XX @@ void HELPER(st2g_stub)(CPUARMState *env, uint64_t ptr)
112
}
113
}
114
115
-#define LDGM_STGM_SIZE (4 << GMID_EL1_BS)
116
-
117
uint64_t HELPER(ldgm)(CPUARMState *env, uint64_t ptr)
118
{
119
int mmu_idx = cpu_mmu_index(env, false);
120
uintptr_t ra = GETPC();
121
+ int gm_bs = env_archcpu(env)->gm_blocksize;
122
+ int gm_bs_bytes = 4 << gm_bs;
123
void *tag_mem;
124
125
- ptr = QEMU_ALIGN_DOWN(ptr, LDGM_STGM_SIZE);
126
+ ptr = QEMU_ALIGN_DOWN(ptr, gm_bs_bytes);
127
128
/* Trap if accessing an invalid page. */
129
tag_mem = allocation_tag_mem(env, mmu_idx, ptr, MMU_DATA_LOAD,
130
- LDGM_STGM_SIZE, MMU_DATA_LOAD,
131
- LDGM_STGM_SIZE / (2 * TAG_GRANULE), ra);
132
+ gm_bs_bytes, MMU_DATA_LOAD,
133
+ gm_bs_bytes / (2 * TAG_GRANULE), ra);
134
135
/* The tag is squashed to zero if the page does not support tags. */
136
if (!tag_mem) {
137
return 0;
138
}
139
140
- QEMU_BUILD_BUG_ON(GMID_EL1_BS != 6);
141
/*
142
- * We are loading 64-bits worth of tags. The ordering of elements
143
- * within the word corresponds to a 64-bit little-endian operation.
144
+ * The ordering of elements within the word corresponds to
145
+ * a little-endian operation.
146
*/
147
- return ldq_le_p(tag_mem);
148
+ switch (gm_bs) {
149
+ case 6:
150
+ /* 256 bytes -> 16 tags -> 64 result bits */
151
+ return ldq_le_p(tag_mem);
152
+ default:
153
+ /* cpu configured with unsupported gm blocksize. */
154
+ g_assert_not_reached();
155
+ }
156
}
157
158
void HELPER(stgm)(CPUARMState *env, uint64_t ptr, uint64_t val)
159
{
160
int mmu_idx = cpu_mmu_index(env, false);
161
uintptr_t ra = GETPC();
162
+ int gm_bs = env_archcpu(env)->gm_blocksize;
163
+ int gm_bs_bytes = 4 << gm_bs;
164
void *tag_mem;
165
166
- ptr = QEMU_ALIGN_DOWN(ptr, LDGM_STGM_SIZE);
167
+ ptr = QEMU_ALIGN_DOWN(ptr, gm_bs_bytes);
168
169
/* Trap if accessing an invalid page. */
170
tag_mem = allocation_tag_mem(env, mmu_idx, ptr, MMU_DATA_STORE,
171
- LDGM_STGM_SIZE, MMU_DATA_LOAD,
172
- LDGM_STGM_SIZE / (2 * TAG_GRANULE), ra);
173
+ gm_bs_bytes, MMU_DATA_LOAD,
174
+ gm_bs_bytes / (2 * TAG_GRANULE), ra);
175
176
/*
177
* Tag store only happens if the page support tags,
178
@@ -XXX,XX +XXX,XX @@ void HELPER(stgm)(CPUARMState *env, uint64_t ptr, uint64_t val)
179
return;
180
}
181
182
- QEMU_BUILD_BUG_ON(GMID_EL1_BS != 6);
183
/*
184
- * We are storing 64-bits worth of tags. The ordering of elements
185
- * within the word corresponds to a 64-bit little-endian operation.
186
+ * The ordering of elements within the word corresponds to
187
+ * a little-endian operation.
188
*/
189
- stq_le_p(tag_mem, val);
190
+ switch (gm_bs) {
191
+ case 6:
192
+ stq_le_p(tag_mem, val);
193
+ break;
194
+ default:
195
+ /* cpu configured with unsupported gm blocksize. */
196
+ g_assert_not_reached();
197
+ }
198
}
199
200
void HELPER(stzgm_tags)(CPUARMState *env, uint64_t ptr, uint64_t val)
201
diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c
202
index XXXXXXX..XXXXXXX 100644
203
--- a/target/arm/tcg/translate-a64.c
204
+++ b/target/arm/tcg/translate-a64.c
205
@@ -XXX,XX +XXX,XX @@ static bool trans_STGM(DisasContext *s, arg_ldst_tag *a)
206
gen_helper_stgm(cpu_env, addr, tcg_rt);
207
} else {
208
MMUAccessType acc = MMU_DATA_STORE;
209
- int size = 4 << GMID_EL1_BS;
210
+ int size = 4 << s->gm_blocksize;
211
212
clean_addr = clean_data_tbi(s, addr);
213
tcg_gen_andi_i64(clean_addr, clean_addr, -size);
214
@@ -XXX,XX +XXX,XX @@ static bool trans_LDGM(DisasContext *s, arg_ldst_tag *a)
215
gen_helper_ldgm(tcg_rt, cpu_env, addr);
216
} else {
217
MMUAccessType acc = MMU_DATA_LOAD;
218
- int size = 4 << GMID_EL1_BS;
219
+ int size = 4 << s->gm_blocksize;
220
221
clean_addr = clean_data_tbi(s, addr);
222
tcg_gen_andi_i64(clean_addr, clean_addr, -size);
223
@@ -XXX,XX +XXX,XX @@ static void aarch64_tr_init_disas_context(DisasContextBase *dcbase,
224
dc->cp_regs = arm_cpu->cp_regs;
225
dc->features = env->features;
226
dc->dcz_blocksize = arm_cpu->dcz_blocksize;
227
+ dc->gm_blocksize = arm_cpu->gm_blocksize;
228
229
#ifdef CONFIG_USER_ONLY
230
/* In sve_probe_page, we assume TBI is enabled. */
29
--
231
--
30
2.25.1
232
2.34.1
diff view generated by jsdifflib
New patch
[PULL 03/24] target/arm: Support more GM blocksizes
1
From: Richard Henderson <richard.henderson@linaro.org>
1
2
3
Support all of the easy GM block sizes.
4
Use direct memory operations, since the pointers are aligned.
5
6
While BS=2 (16 bytes, 1 tag) is a legal setting, that requires
7
an atomic store of one nibble. This is not difficult, but there
8
is also no point in supporting it until required.
9
10
Note that cortex-a710 sets GM blocksize to match its cacheline
11
size of 64 bytes. I expect many implementations will also
12
match the cacheline, which makes 16 bytes very unlikely.
13
14
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
15
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
16
Message-id: 20230811214031.171020-4-richard.henderson@linaro.org
17
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
18
---
19
target/arm/cpu.c | 18 +++++++++---
20
target/arm/tcg/mte_helper.c | 56 +++++++++++++++++++++++++++++++------
21
2 files changed, 62 insertions(+), 12 deletions(-)
22
23
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
24
index XXXXXXX..XXXXXXX 100644
25
--- a/target/arm/cpu.c
26
+++ b/target/arm/cpu.c
27
@@ -XXX,XX +XXX,XX @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp)
28
ID_PFR1, VIRTUALIZATION, 0);
29
}
30
31
+ if (cpu_isar_feature(aa64_mte, cpu)) {
32
+ /*
33
+ * The architectural range of GM blocksize is 2-6, however qemu
34
+ * doesn't support blocksize of 2 (see HELPER(ldgm)).
35
+ */
36
+ if (tcg_enabled()) {
37
+ assert(cpu->gm_blocksize >= 3 && cpu->gm_blocksize <= 6);
38
+ }
39
+
40
#ifndef CONFIG_USER_ONLY
41
- if (cpu->tag_memory == NULL && cpu_isar_feature(aa64_mte, cpu)) {
42
/*
43
* Disable the MTE feature bits if we do not have tag-memory
44
* provided by the machine.
45
*/
46
- cpu->isar.id_aa64pfr1 =
47
- FIELD_DP64(cpu->isar.id_aa64pfr1, ID_AA64PFR1, MTE, 0);
48
- }
49
+ if (cpu->tag_memory == NULL) {
50
+ cpu->isar.id_aa64pfr1 =
51
+ FIELD_DP64(cpu->isar.id_aa64pfr1, ID_AA64PFR1, MTE, 0);
52
+ }
53
#endif
54
+ }
55
56
if (tcg_enabled()) {
57
/*
58
diff --git a/target/arm/tcg/mte_helper.c b/target/arm/tcg/mte_helper.c
59
index XXXXXXX..XXXXXXX 100644
60
--- a/target/arm/tcg/mte_helper.c
61
+++ b/target/arm/tcg/mte_helper.c
62
@@ -XXX,XX +XXX,XX @@ uint64_t HELPER(ldgm)(CPUARMState *env, uint64_t ptr)
63
int gm_bs = env_archcpu(env)->gm_blocksize;
64
int gm_bs_bytes = 4 << gm_bs;
65
void *tag_mem;
66
+ uint64_t ret;
67
+ int shift;
68
69
ptr = QEMU_ALIGN_DOWN(ptr, gm_bs_bytes);
70
71
@@ -XXX,XX +XXX,XX @@ uint64_t HELPER(ldgm)(CPUARMState *env, uint64_t ptr)
72
73
/*
74
* The ordering of elements within the word corresponds to
75
- * a little-endian operation.
76
+ * a little-endian operation. Computation of shift comes from
77
+ *
78
+ * index = address<LOG2_TAG_GRANULE+3:LOG2_TAG_GRANULE>
79
+ * data<index*4+3:index*4> = tag
80
+ *
81
+ * Because of the alignment of ptr above, BS=6 has shift=0.
82
+ * All memory operations are aligned. Defer support for BS=2,
83
+ * requiring insertion or extraction of a nibble, until we
84
+ * support a cpu that requires it.
85
*/
86
switch (gm_bs) {
87
+ case 3:
88
+ /* 32 bytes -> 2 tags -> 8 result bits */
89
+ ret = *(uint8_t *)tag_mem;
90
+ break;
91
+ case 4:
92
+ /* 64 bytes -> 4 tags -> 16 result bits */
93
+ ret = cpu_to_le16(*(uint16_t *)tag_mem);
94
+ break;
95
+ case 5:
96
+ /* 128 bytes -> 8 tags -> 32 result bits */
97
+ ret = cpu_to_le32(*(uint32_t *)tag_mem);
98
+ break;
99
case 6:
100
/* 256 bytes -> 16 tags -> 64 result bits */
101
- return ldq_le_p(tag_mem);
102
+ return cpu_to_le64(*(uint64_t *)tag_mem);
103
default:
104
- /* cpu configured with unsupported gm blocksize. */
105
+ /*
106
+ * CPU configured with unsupported/invalid gm blocksize.
107
+ * This is detected early in arm_cpu_realizefn.
108
+ */
109
g_assert_not_reached();
110
}
111
+ shift = extract64(ptr, LOG2_TAG_GRANULE, 4) * 4;
112
+ return ret << shift;
113
}
114
115
void HELPER(stgm)(CPUARMState *env, uint64_t ptr, uint64_t val)
116
@@ -XXX,XX +XXX,XX @@ void HELPER(stgm)(CPUARMState *env, uint64_t ptr, uint64_t val)
117
int gm_bs = env_archcpu(env)->gm_blocksize;
118
int gm_bs_bytes = 4 << gm_bs;
119
void *tag_mem;
120
+ int shift;
121
122
ptr = QEMU_ALIGN_DOWN(ptr, gm_bs_bytes);
123
124
@@ -XXX,XX +XXX,XX @@ void HELPER(stgm)(CPUARMState *env, uint64_t ptr, uint64_t val)
125
return;
126
}
127
128
- /*
129
- * The ordering of elements within the word corresponds to
130
- * a little-endian operation.
131
- */
132
+ /* See LDGM for comments on BS and on shift. */
133
+ shift = extract64(ptr, LOG2_TAG_GRANULE, 4) * 4;
134
+ val >>= shift;
135
switch (gm_bs) {
136
+ case 3:
137
+ /* 32 bytes -> 2 tags -> 8 result bits */
138
+ *(uint8_t *)tag_mem = val;
139
+ break;
140
+ case 4:
141
+ /* 64 bytes -> 4 tags -> 16 result bits */
142
+ *(uint16_t *)tag_mem = cpu_to_le16(val);
143
+ break;
144
+ case 5:
145
+ /* 128 bytes -> 8 tags -> 32 result bits */
146
+ *(uint32_t *)tag_mem = cpu_to_le32(val);
147
+ break;
148
case 6:
149
- stq_le_p(tag_mem, val);
150
+ /* 256 bytes -> 16 tags -> 64 result bits */
151
+ *(uint64_t *)tag_mem = cpu_to_le64(val);
152
break;
153
default:
154
/* cpu configured with unsupported gm blocksize. */
155
--
156
2.34.1
diff view generated by jsdifflib
New patch
[PULL 04/24] target/arm: When tag memory is not present, set MTE=1
1
From: Richard Henderson <richard.henderson@linaro.org>
1
2
3
When the cpu support MTE, but the system does not, reduce cpu
4
support to user instructions at EL0 instead of completely
5
disabling MTE. If we encounter a cpu implementation which does
6
something else, we can revisit this setting.
7
8
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
9
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
10
Message-id: 20230811214031.171020-5-richard.henderson@linaro.org
11
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
12
---
13
target/arm/cpu.c | 7 ++++---
14
1 file changed, 4 insertions(+), 3 deletions(-)
15
16
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
17
index XXXXXXX..XXXXXXX 100644
18
--- a/target/arm/cpu.c
19
+++ b/target/arm/cpu.c
20
@@ -XXX,XX +XXX,XX @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp)
21
22
#ifndef CONFIG_USER_ONLY
23
/*
24
- * Disable the MTE feature bits if we do not have tag-memory
25
- * provided by the machine.
26
+ * If we do not have tag-memory provided by the machine,
27
+ * reduce MTE support to instructions enabled at EL0.
28
+ * This matches Cortex-A710 BROADCASTMTE input being LOW.
29
*/
30
if (cpu->tag_memory == NULL) {
31
cpu->isar.id_aa64pfr1 =
32
- FIELD_DP64(cpu->isar.id_aa64pfr1, ID_AA64PFR1, MTE, 0);
33
+ FIELD_DP64(cpu->isar.id_aa64pfr1, ID_AA64PFR1, MTE, 1);
34
}
35
#endif
36
}
37
--
38
2.34.1
diff view generated by jsdifflib
New patch
[PULL 05/24] target/arm: Introduce make_ccsidr64
1
From: Richard Henderson <richard.henderson@linaro.org>
1
2
3
Do not hard-code the constants for Neoverse V1.
4
5
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
6
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
7
Message-id: 20230811214031.171020-6-richard.henderson@linaro.org
8
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
---
10
target/arm/tcg/cpu64.c | 48 ++++++++++++++++++++++++++++--------------
11
1 file changed, 32 insertions(+), 16 deletions(-)
12
13
diff --git a/target/arm/tcg/cpu64.c b/target/arm/tcg/cpu64.c
14
index XXXXXXX..XXXXXXX 100644
15
--- a/target/arm/tcg/cpu64.c
16
+++ b/target/arm/tcg/cpu64.c
17
@@ -XXX,XX +XXX,XX @@
18
#include "qemu/module.h"
19
#include "qapi/visitor.h"
20
#include "hw/qdev-properties.h"
21
+#include "qemu/units.h"
22
#include "internals.h"
23
#include "cpregs.h"
24
25
+static uint64_t make_ccsidr64(unsigned assoc, unsigned linesize,
26
+ unsigned cachesize)
27
+{
28
+ unsigned lg_linesize = ctz32(linesize);
29
+ unsigned sets;
30
+
31
+ /*
32
+ * The 64-bit CCSIDR_EL1 format is:
33
+ * [55:32] number of sets - 1
34
+ * [23:3] associativity - 1
35
+ * [2:0] log2(linesize) - 4
36
+ * so 0 == 16 bytes, 1 == 32 bytes, 2 == 64 bytes, etc
37
+ */
38
+ assert(assoc != 0);
39
+ assert(is_power_of_2(linesize));
40
+ assert(lg_linesize >= 4 && lg_linesize <= 7 + 4);
41
+
42
+ /* sets * associativity * linesize == cachesize. */
43
+ sets = cachesize / (assoc * linesize);
44
+ assert(cachesize % (assoc * linesize) == 0);
45
+
46
+ return ((uint64_t)(sets - 1) << 32)
47
+ | ((assoc - 1) << 3)
48
+ | (lg_linesize - 4);
49
+}
50
+
51
static void aarch64_a35_initfn(Object *obj)
52
{
53
ARMCPU *cpu = ARM_CPU(obj);
54
@@ -XXX,XX +XXX,XX @@ static void aarch64_neoverse_v1_initfn(Object *obj)
55
* The Neoverse-V1 r1p2 TRM lists 32-bit format CCSIDR_EL1 values,
56
* but also says it implements CCIDX, which means they should be
57
* 64-bit format. So we here use values which are based on the textual
58
- * information in chapter 2 of the TRM (and on the fact that
59
- * sets * associativity * linesize == cachesize).
60
- *
61
- * The 64-bit CCSIDR_EL1 format is:
62
- * [55:32] number of sets - 1
63
- * [23:3] associativity - 1
64
- * [2:0] log2(linesize) - 4
65
- * so 0 == 16 bytes, 1 == 32 bytes, 2 == 64 bytes, etc
66
- *
67
- * L1: 4-way set associative 64-byte line size, total size 64K,
68
- * so sets is 256.
69
+ * information in chapter 2 of the TRM:
70
*
71
+ * L1: 4-way set associative 64-byte line size, total size 64K.
72
* L2: 8-way set associative, 64 byte line size, either 512K or 1MB.
73
- * We pick 1MB, so this has 2048 sets.
74
- *
75
* L3: No L3 (this matches the CLIDR_EL1 value).
76
*/
77
- cpu->ccsidr[0] = 0x000000ff0000001aull; /* 64KB L1 dcache */
78
- cpu->ccsidr[1] = 0x000000ff0000001aull; /* 64KB L1 icache */
79
- cpu->ccsidr[2] = 0x000007ff0000003aull; /* 1MB L2 cache */
80
+ cpu->ccsidr[0] = make_ccsidr64(4, 64, 64 * KiB); /* L1 dcache */
81
+ cpu->ccsidr[1] = cpu->ccsidr[0]; /* L1 icache */
82
+ cpu->ccsidr[2] = make_ccsidr64(8, 64, 1 * MiB); /* L2 cache */
83
84
/* From 3.2.115 SCTLR_EL3 */
85
cpu->reset_sctlr = 0x30c50838;
86
--
87
2.34.1
diff view generated by jsdifflib
[PULL 02/10] target/arm: Make writes to MDCR_EL3 use PMU start/finish calls
[PULL 06/24] target/arm: Apply access checks to neoverse-n1 special registers
1
In commit 01765386a88868 we fixed a bug where we weren't correctly
1
From: Richard Henderson <richard.henderson@linaro.org>
2
bracketing changes to some registers with pmu_op_start() and
3
pmu_op_finish() calls for changes which affect whether the PMU
4
counters might be enabled. However, we missed the case of writes to
5
the AArch64 MDCR_EL3 register, because (unlike its AArch32
6
counterpart) they are currently done directly to the CPU state struct
7
without going through the sdcr_write() function.
8
2
9
Give MDCR_EL3 a writefn which handles the PMU start/finish calls.
3
Access to many of the special registers is enabled or disabled
10
The SDCR writefn then simplfies to "call the MDCR_EL3 writefn after
4
by ACTLR_EL[23], which we implement as constant 0, which means
11
masking off the bits which don't exist in the AArch32 register".
5
that all writes outside EL3 should trap.
12
6
7
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
8
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
9
Message-id: 20230811214031.171020-7-richard.henderson@linaro.org
13
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
14
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
15
Message-id: 20220923123412.1214041-3-peter.maydell@linaro.org
16
---
11
---
17
target/arm/helper.c | 18 ++++++++++++++----
12
target/arm/cpregs.h | 2 ++
18
1 file changed, 14 insertions(+), 4 deletions(-)
13
target/arm/helper.c | 4 ++--
14
target/arm/tcg/cpu64.c | 46 +++++++++++++++++++++++++++++++++---------
15
3 files changed, 41 insertions(+), 11 deletions(-)
19
16
17
diff --git a/target/arm/cpregs.h b/target/arm/cpregs.h
18
index XXXXXXX..XXXXXXX 100644
19
--- a/target/arm/cpregs.h
20
+++ b/target/arm/cpregs.h
21
@@ -XXX,XX +XXX,XX @@ static inline void define_cortex_a72_a57_a53_cp_reginfo(ARMCPU *cpu) { }
22
void define_cortex_a72_a57_a53_cp_reginfo(ARMCPU *cpu);
23
#endif
24
25
+CPAccessResult access_tvm_trvm(CPUARMState *, const ARMCPRegInfo *, bool);
26
+
27
#endif /* TARGET_ARM_CPREGS_H */
20
diff --git a/target/arm/helper.c b/target/arm/helper.c
28
diff --git a/target/arm/helper.c b/target/arm/helper.c
21
index XXXXXXX..XXXXXXX 100644
29
index XXXXXXX..XXXXXXX 100644
22
--- a/target/arm/helper.c
30
--- a/target/arm/helper.c
23
+++ b/target/arm/helper.c
31
+++ b/target/arm/helper.c
24
@@ -XXX,XX +XXX,XX @@ static void sctlr_write(CPUARMState *env, const ARMCPRegInfo *ri,
32
@@ -XXX,XX +XXX,XX @@ static CPAccessResult access_tpm(CPUARMState *env, const ARMCPRegInfo *ri,
25
}
26
}
33
}
27
34
28
-static void sdcr_write(CPUARMState *env, const ARMCPRegInfo *ri,
35
/* Check for traps from EL1 due to HCR_EL2.TVM and HCR_EL2.TRVM. */
29
- uint64_t value)
36
-static CPAccessResult access_tvm_trvm(CPUARMState *env, const ARMCPRegInfo *ri,
30
+static void mdcr_el3_write(CPUARMState *env, const ARMCPRegInfo *ri,
37
- bool isread)
31
+ uint64_t value)
38
+CPAccessResult access_tvm_trvm(CPUARMState *env, const ARMCPRegInfo *ri,
39
+ bool isread)
32
{
40
{
33
/*
41
if (arm_current_el(env) == 1) {
34
* Some MDCR_EL3 bits affect whether PMU counters are running:
42
uint64_t trap = isread ? HCR_TRVM : HCR_TVM;
35
@@ -XXX,XX +XXX,XX @@ static void sdcr_write(CPUARMState *env, const ARMCPRegInfo *ri,
43
diff --git a/target/arm/tcg/cpu64.c b/target/arm/tcg/cpu64.c
36
if (pmu_op) {
44
index XXXXXXX..XXXXXXX 100644
37
pmu_op_start(env);
45
--- a/target/arm/tcg/cpu64.c
38
}
46
+++ b/target/arm/tcg/cpu64.c
39
- env->cp15.mdcr_el3 = value & SDCR_VALID_MASK;
47
@@ -XXX,XX +XXX,XX @@ static void aarch64_a64fx_initfn(Object *obj)
40
+ env->cp15.mdcr_el3 = value;
48
/* TODO: Add A64FX specific HPC extension registers */
41
if (pmu_op) {
42
pmu_op_finish(env);
43
}
44
}
49
}
45
50
46
+static void sdcr_write(CPUARMState *env, const ARMCPRegInfo *ri,
51
+static CPAccessResult access_actlr_w(CPUARMState *env, const ARMCPRegInfo *r,
47
+ uint64_t value)
52
+ bool read)
48
+{
53
+{
49
+ /* Not all bits defined for MDCR_EL3 exist in the AArch32 SDCR */
54
+ if (!read) {
50
+ mdcr_el3_write(env, ri, value & SDCR_VALID_MASK);
55
+ int el = arm_current_el(env);
56
+
57
+ /* Because ACTLR_EL2 is constant 0, writes below EL2 trap to EL2. */
58
+ if (el < 2 && arm_is_el2_enabled(env)) {
59
+ return CP_ACCESS_TRAP_EL2;
60
+ }
61
+ /* Because ACTLR_EL3 is constant 0, writes below EL3 trap to EL3. */
62
+ if (el < 3 && arm_feature(env, ARM_FEATURE_EL3)) {
63
+ return CP_ACCESS_TRAP_EL3;
64
+ }
65
+ }
66
+ return CP_ACCESS_OK;
51
+}
67
+}
52
+
68
+
53
static void mdcr_el2_write(CPUARMState *env, const ARMCPRegInfo *ri,
69
static const ARMCPRegInfo neoverse_n1_cp_reginfo[] = {
54
uint64_t value)
70
{ .name = "ATCR_EL1", .state = ARM_CP_STATE_AA64,
55
{
71
.opc0 = 3, .opc1 = 0, .crn = 15, .crm = 7, .opc2 = 0,
56
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo v8_cp_reginfo[] = {
72
- .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
57
.access = PL2_RW,
73
+ .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0,
58
.fieldoffset = offsetof(CPUARMState, banked_spsr[BANK_FIQ]) },
74
+ /* Traps and enables are the same as for TCR_EL1. */
59
{ .name = "MDCR_EL3", .state = ARM_CP_STATE_AA64,
75
+ .accessfn = access_tvm_trvm, .fgt = FGT_TCR_EL1, },
60
+ .type = ARM_CP_IO,
76
{ .name = "ATCR_EL2", .state = ARM_CP_STATE_AA64,
61
.opc0 = 3, .opc1 = 6, .crn = 1, .crm = 3, .opc2 = 1,
77
.opc0 = 3, .opc1 = 4, .crn = 15, .crm = 7, .opc2 = 0,
62
.resetvalue = 0,
78
.access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
63
- .access = PL3_RW, .fieldoffset = offsetof(CPUARMState, cp15.mdcr_el3) },
79
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo neoverse_n1_cp_reginfo[] = {
64
+ .access = PL3_RW,
80
.access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
65
+ .writefn = mdcr_el3_write,
81
{ .name = "CPUACTLR_EL1", .state = ARM_CP_STATE_AA64,
66
+ .fieldoffset = offsetof(CPUARMState, cp15.mdcr_el3) },
82
.opc0 = 3, .opc1 = 0, .crn = 15, .crm = 1, .opc2 = 0,
67
{ .name = "SDCR", .type = ARM_CP_ALIAS | ARM_CP_IO,
83
- .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
68
.cp = 15, .opc1 = 0, .crn = 1, .crm = 3, .opc2 = 1,
84
+ .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0,
69
.access = PL1_RW, .accessfn = access_trap_aa32s_el1,
85
+ .accessfn = access_actlr_w },
86
{ .name = "CPUACTLR2_EL1", .state = ARM_CP_STATE_AA64,
87
.opc0 = 3, .opc1 = 0, .crn = 15, .crm = 1, .opc2 = 1,
88
- .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
89
+ .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0,
90
+ .accessfn = access_actlr_w },
91
{ .name = "CPUACTLR3_EL1", .state = ARM_CP_STATE_AA64,
92
.opc0 = 3, .opc1 = 0, .crn = 15, .crm = 1, .opc2 = 2,
93
- .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
94
+ .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0,
95
+ .accessfn = access_actlr_w },
96
/*
97
* Report CPUCFR_EL1.SCU as 1, as we do not implement the DSU
98
* (and in particular its system registers).
99
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo neoverse_n1_cp_reginfo[] = {
100
.access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 4 },
101
{ .name = "CPUECTLR_EL1", .state = ARM_CP_STATE_AA64,
102
.opc0 = 3, .opc1 = 0, .crn = 15, .crm = 1, .opc2 = 4,
103
- .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0x961563010 },
104
+ .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0x961563010,
105
+ .accessfn = access_actlr_w },
106
{ .name = "CPUPCR_EL3", .state = ARM_CP_STATE_AA64,
107
.opc0 = 3, .opc1 = 6, .crn = 15, .crm = 8, .opc2 = 1,
108
.access = PL3_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
109
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo neoverse_n1_cp_reginfo[] = {
110
.access = PL3_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
111
{ .name = "CPUPWRCTLR_EL1", .state = ARM_CP_STATE_AA64,
112
.opc0 = 3, .opc1 = 0, .crn = 15, .crm = 2, .opc2 = 7,
113
- .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
114
+ .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0,
115
+ .accessfn = access_actlr_w },
116
{ .name = "ERXPFGCDN_EL1", .state = ARM_CP_STATE_AA64,
117
.opc0 = 3, .opc1 = 0, .crn = 15, .crm = 2, .opc2 = 2,
118
- .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
119
+ .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0,
120
+ .accessfn = access_actlr_w },
121
{ .name = "ERXPFGCTL_EL1", .state = ARM_CP_STATE_AA64,
122
.opc0 = 3, .opc1 = 0, .crn = 15, .crm = 2, .opc2 = 1,
123
- .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
124
+ .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0,
125
+ .accessfn = access_actlr_w },
126
{ .name = "ERXPFGF_EL1", .state = ARM_CP_STATE_AA64,
127
.opc0 = 3, .opc1 = 0, .crn = 15, .crm = 2, .opc2 = 0,
128
- .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
129
+ .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0,
130
+ .accessfn = access_actlr_w },
131
};
132
133
static void define_neoverse_n1_cp_reginfo(ARMCPU *cpu)
70
--
134
--
71
2.25.1
135
2.34.1
diff view generated by jsdifflib
New patch
[PULL 07/24] target/arm: Apply access checks to neoverse-v1 special registers
1
From: Richard Henderson <richard.henderson@linaro.org>
1
2
3
There is only one additional EL1 register modeled, which
4
also needs to use access_actlr_w.
5
6
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
7
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
8
Message-id: 20230811214031.171020-8-richard.henderson@linaro.org
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
---
11
target/arm/tcg/cpu64.c | 3 ++-
12
1 file changed, 2 insertions(+), 1 deletion(-)
13
14
diff --git a/target/arm/tcg/cpu64.c b/target/arm/tcg/cpu64.c
15
index XXXXXXX..XXXXXXX 100644
16
--- a/target/arm/tcg/cpu64.c
17
+++ b/target/arm/tcg/cpu64.c
18
@@ -XXX,XX +XXX,XX @@ static void define_neoverse_n1_cp_reginfo(ARMCPU *cpu)
19
static const ARMCPRegInfo neoverse_v1_cp_reginfo[] = {
20
{ .name = "CPUECTLR2_EL1", .state = ARM_CP_STATE_AA64,
21
.opc0 = 3, .opc1 = 0, .crn = 15, .crm = 1, .opc2 = 5,
22
- .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
23
+ .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0,
24
+ .accessfn = access_actlr_w },
25
{ .name = "CPUPPMCR_EL3", .state = ARM_CP_STATE_AA64,
26
.opc0 = 3, .opc1 = 6, .crn = 15, .crm = 2, .opc2 = 0,
27
.access = PL3_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
28
--
29
2.34.1
diff view generated by jsdifflib
New patch
[PULL 08/24] target/arm: Suppress FEAT_TRBE (Trace Buffer Extension)
1
From: Richard Henderson <richard.henderson@linaro.org>
1
2
3
Like FEAT_TRF (Self-hosted Trace Extension), suppress tracing
4
external to the cpu, which is out of scope for QEMU.
5
6
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
7
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
8
Message-id: 20230811214031.171020-10-richard.henderson@linaro.org
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
---
11
target/arm/cpu.c | 3 +++
12
1 file changed, 3 insertions(+)
13
14
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
15
index XXXXXXX..XXXXXXX 100644
16
--- a/target/arm/cpu.c
17
+++ b/target/arm/cpu.c
18
@@ -XXX,XX +XXX,XX @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp)
19
/* FEAT_SPE (Statistical Profiling Extension) */
20
cpu->isar.id_aa64dfr0 =
21
FIELD_DP64(cpu->isar.id_aa64dfr0, ID_AA64DFR0, PMSVER, 0);
22
+ /* FEAT_TRBE (Trace Buffer Extension) */
23
+ cpu->isar.id_aa64dfr0 =
24
+ FIELD_DP64(cpu->isar.id_aa64dfr0, ID_AA64DFR0, TRACEBUFFER, 0);
25
/* FEAT_TRF (Self-hosted Trace Extension) */
26
cpu->isar.id_aa64dfr0 =
27
FIELD_DP64(cpu->isar.id_aa64dfr0, ID_AA64DFR0, TRACEFILT, 0);
28
--
29
2.34.1
diff view generated by jsdifflib
New patch
[PULL 09/24] target/arm: Implement FEAT_HPDS2 as a no-op
1
From: Richard Henderson <richard.henderson@linaro.org>
1
2
3
This feature allows the operating system to set TCR_ELx.HWU*
4
to allow the implementation to use the PBHA bits from the
5
block and page descriptors for for IMPLEMENTATION DEFINED
6
purposes. Since QEMU has no need to use these bits, we may
7
simply ignore them.
8
9
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
10
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
11
Message-id: 20230811214031.171020-11-richard.henderson@linaro.org
12
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
13
---
14
docs/system/arm/emulation.rst | 1 +
15
target/arm/tcg/cpu32.c | 2 +-
16
target/arm/tcg/cpu64.c | 2 +-
17
3 files changed, 3 insertions(+), 2 deletions(-)
18
19
diff --git a/docs/system/arm/emulation.rst b/docs/system/arm/emulation.rst
20
index XXXXXXX..XXXXXXX 100644
21
--- a/docs/system/arm/emulation.rst
22
+++ b/docs/system/arm/emulation.rst
23
@@ -XXX,XX +XXX,XX @@ the following architecture extensions:
24
- FEAT_HAFDBS (Hardware management of the access flag and dirty bit state)
25
- FEAT_HCX (Support for the HCRX_EL2 register)
26
- FEAT_HPDS (Hierarchical permission disables)
27
+- FEAT_HPDS2 (Translation table page-based hardware attributes)
28
- FEAT_I8MM (AArch64 Int8 matrix multiplication instructions)
29
- FEAT_IDST (ID space trap handling)
30
- FEAT_IESB (Implicit error synchronization event)
31
diff --git a/target/arm/tcg/cpu32.c b/target/arm/tcg/cpu32.c
32
index XXXXXXX..XXXXXXX 100644
33
--- a/target/arm/tcg/cpu32.c
34
+++ b/target/arm/tcg/cpu32.c
35
@@ -XXX,XX +XXX,XX @@ void aa32_max_features(ARMCPU *cpu)
36
cpu->isar.id_mmfr3 = t;
37
38
t = cpu->isar.id_mmfr4;
39
- t = FIELD_DP32(t, ID_MMFR4, HPDS, 1); /* FEAT_AA32HPD */
40
+ t = FIELD_DP32(t, ID_MMFR4, HPDS, 2); /* FEAT_HPDS2 */
41
t = FIELD_DP32(t, ID_MMFR4, AC2, 1); /* ACTLR2, HACTLR2 */
42
t = FIELD_DP32(t, ID_MMFR4, CNP, 1); /* FEAT_TTCNP */
43
t = FIELD_DP32(t, ID_MMFR4, XNX, 1); /* FEAT_XNX */
44
diff --git a/target/arm/tcg/cpu64.c b/target/arm/tcg/cpu64.c
45
index XXXXXXX..XXXXXXX 100644
46
--- a/target/arm/tcg/cpu64.c
47
+++ b/target/arm/tcg/cpu64.c
48
@@ -XXX,XX +XXX,XX @@ void aarch64_max_tcg_initfn(Object *obj)
49
t = FIELD_DP64(t, ID_AA64MMFR1, HAFDBS, 2); /* FEAT_HAFDBS */
50
t = FIELD_DP64(t, ID_AA64MMFR1, VMIDBITS, 2); /* FEAT_VMID16 */
51
t = FIELD_DP64(t, ID_AA64MMFR1, VH, 1); /* FEAT_VHE */
52
- t = FIELD_DP64(t, ID_AA64MMFR1, HPDS, 1); /* FEAT_HPDS */
53
+ t = FIELD_DP64(t, ID_AA64MMFR1, HPDS, 2); /* FEAT_HPDS2 */
54
t = FIELD_DP64(t, ID_AA64MMFR1, LO, 1); /* FEAT_LOR */
55
t = FIELD_DP64(t, ID_AA64MMFR1, PAN, 3); /* FEAT_PAN3 */
56
t = FIELD_DP64(t, ID_AA64MMFR1, XNX, 1); /* FEAT_XNX */
57
--
58
2.34.1
diff view generated by jsdifflib
New patch
[PULL 10/24] target/arm: properly document FEAT_CRC32
1
From: Alex Bennée <alex.bennee@linaro.org>
1
2
3
This is a mandatory feature for Armv8.1 architectures but we don't
4
state the feature clearly in our emulation list. Also include
5
FEAT_CRC32 comment in aarch64_max_tcg_initfn for ease of grepping.
6
7
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
8
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
9
Message-id: 20230824075406.1515566-1-alex.bennee@linaro.org
10
Cc: qemu-stable@nongnu.org
11
Message-Id: <20230222110104.3996971-1-alex.bennee@linaro.org>
12
[PMM: pluralize 'instructions' in docs]
13
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
14
---
15
docs/system/arm/emulation.rst | 1 +
16
target/arm/tcg/cpu64.c | 2 +-
17
2 files changed, 2 insertions(+), 1 deletion(-)
18
19
diff --git a/docs/system/arm/emulation.rst b/docs/system/arm/emulation.rst
20
index XXXXXXX..XXXXXXX 100644
21
--- a/docs/system/arm/emulation.rst
22
+++ b/docs/system/arm/emulation.rst
23
@@ -XXX,XX +XXX,XX @@ the following architecture extensions:
24
- FEAT_BBM at level 2 (Translation table break-before-make levels)
25
- FEAT_BF16 (AArch64 BFloat16 instructions)
26
- FEAT_BTI (Branch Target Identification)
27
+- FEAT_CRC32 (CRC32 instructions)
28
- FEAT_CSV2 (Cache speculation variant 2)
29
- FEAT_CSV2_1p1 (Cache speculation variant 2, version 1.1)
30
- FEAT_CSV2_1p2 (Cache speculation variant 2, version 1.2)
31
diff --git a/target/arm/tcg/cpu64.c b/target/arm/tcg/cpu64.c
32
index XXXXXXX..XXXXXXX 100644
33
--- a/target/arm/tcg/cpu64.c
34
+++ b/target/arm/tcg/cpu64.c
35
@@ -XXX,XX +XXX,XX @@ void aarch64_max_tcg_initfn(Object *obj)
36
t = FIELD_DP64(t, ID_AA64ISAR0, AES, 2); /* FEAT_PMULL */
37
t = FIELD_DP64(t, ID_AA64ISAR0, SHA1, 1); /* FEAT_SHA1 */
38
t = FIELD_DP64(t, ID_AA64ISAR0, SHA2, 2); /* FEAT_SHA512 */
39
- t = FIELD_DP64(t, ID_AA64ISAR0, CRC32, 1);
40
+ t = FIELD_DP64(t, ID_AA64ISAR0, CRC32, 1); /* FEAT_CRC32 */
41
t = FIELD_DP64(t, ID_AA64ISAR0, ATOMIC, 2); /* FEAT_LSE */
42
t = FIELD_DP64(t, ID_AA64ISAR0, RDM, 1); /* FEAT_RDM */
43
t = FIELD_DP64(t, ID_AA64ISAR0, SHA3, 1); /* FEAT_SHA3 */
44
--
45
2.34.1
46
47
diff view generated by jsdifflib
[PULL 08/10] hw/arm/virt: Use "msi-map" devicetree property for PCI
[PULL 11/24] Remove i.MX7 IOMUX GPR device from i.MX6UL
1
From: Jean-Philippe Brucker <jean-philippe@linaro.org>
1
From: Jean-Christophe Dubois <jcd@tribudubois.net>
2
2
3
The "msi-parent" property can be used on the PCI node when MSIs do not
3
i.MX7 IOMUX GPR device is not equivalent to i.MX6UL IOMUXC GPR device.
4
contain sideband data (device IDs) [1]. In QEMU, MSI transactions
4
In particular, register 22 is not present on i.MX6UL and this is actualy
5
contain the requester ID, so the PCI node should use the "msi-map"
5
The only register that is really emulated in the i.MX7 IOMUX GPR device.
6
property instead of "msi-parent". In our case the property describes an
7
identity map between requester ID and sideband data.
8
6
9
This fixes a warning when passing the DTB generated by QEMU to dtc,
7
Note: The i.MX6UL code is actually also implementing the IOMUX GPR device
10
following a recent change to the GICv3 node:
8
as an unimplemented device at the same bus adress and the 2 instantiations
9
were actualy colliding. So we go back to the unimplemented device for now.
11
10
12
Warning (msi_parent_property): /pcie@10000000:msi-parent: property size (4) too small for cell size 1
11
Signed-off-by: Jean-Christophe Dubois <jcd@tribudubois.net>
13
12
Message-id: 48681bf51ee97646479bb261bee19abebbc8074e.1692964892.git.jcd@tribudubois.net
14
[1] linux/Documentation/devicetree/bindings/pci/pci-msi.txt
15
16
Signed-off-by: Jean-Philippe Brucker <jean-philippe@linaro.org>
17
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
13
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
18
Reviewed-by: Eric Auger <eric.auger@redhat.com>
19
Message-id: 20220927100347.176606-4-jean-philippe@linaro.org
20
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
14
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
21
---
15
---
22
hw/arm/virt.c | 4 ++--
16
include/hw/arm/fsl-imx6ul.h | 2 --
23
1 file changed, 2 insertions(+), 2 deletions(-)
17
hw/arm/fsl-imx6ul.c | 11 -----------
18
2 files changed, 13 deletions(-)
24
19
25
diff --git a/hw/arm/virt.c b/hw/arm/virt.c
20
diff --git a/include/hw/arm/fsl-imx6ul.h b/include/hw/arm/fsl-imx6ul.h
26
index XXXXXXX..XXXXXXX 100644
21
index XXXXXXX..XXXXXXX 100644
27
--- a/hw/arm/virt.c
22
--- a/include/hw/arm/fsl-imx6ul.h
28
+++ b/hw/arm/virt.c
23
+++ b/include/hw/arm/fsl-imx6ul.h
29
@@ -XXX,XX +XXX,XX @@ static void create_pcie(VirtMachineState *vms)
24
@@ -XXX,XX +XXX,XX @@
30
qemu_fdt_setprop(ms->fdt, nodename, "dma-coherent", NULL, 0);
25
#include "hw/misc/imx6ul_ccm.h"
31
26
#include "hw/misc/imx6_src.h"
32
if (vms->msi_phandle) {
27
#include "hw/misc/imx7_snvs.h"
33
- qemu_fdt_setprop_cells(ms->fdt, nodename, "msi-parent",
28
-#include "hw/misc/imx7_gpr.h"
34
- vms->msi_phandle);
29
#include "hw/intc/imx_gpcv2.h"
35
+ qemu_fdt_setprop_cells(ms->fdt, nodename, "msi-map",
30
#include "hw/watchdog/wdt_imx2.h"
36
+ 0, vms->msi_phandle, 0, 0x10000);
31
#include "hw/gpio/imx_gpio.h"
32
@@ -XXX,XX +XXX,XX @@ struct FslIMX6ULState {
33
IMX6SRCState src;
34
IMX7SNVSState snvs;
35
IMXGPCv2State gpcv2;
36
- IMX7GPRState gpr;
37
IMXSPIState spi[FSL_IMX6UL_NUM_ECSPIS];
38
IMXI2CState i2c[FSL_IMX6UL_NUM_I2CS];
39
IMXSerialState uart[FSL_IMX6UL_NUM_UARTS];
40
diff --git a/hw/arm/fsl-imx6ul.c b/hw/arm/fsl-imx6ul.c
41
index XXXXXXX..XXXXXXX 100644
42
--- a/hw/arm/fsl-imx6ul.c
43
+++ b/hw/arm/fsl-imx6ul.c
44
@@ -XXX,XX +XXX,XX @@ static void fsl_imx6ul_init(Object *obj)
45
*/
46
object_initialize_child(obj, "snvs", &s->snvs, TYPE_IMX7_SNVS);
47
48
- /*
49
- * GPR
50
- */
51
- object_initialize_child(obj, "gpr", &s->gpr, TYPE_IMX7_GPR);
52
-
53
/*
54
* GPIOs 1 to 5
55
*/
56
@@ -XXX,XX +XXX,XX @@ static void fsl_imx6ul_realize(DeviceState *dev, Error **errp)
57
FSL_IMX6UL_WDOGn_IRQ[i]));
37
}
58
}
38
59
39
qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg",
60
- /*
61
- * GPR
62
- */
63
- sysbus_realize(SYS_BUS_DEVICE(&s->gpr), &error_abort);
64
- sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpr), 0, FSL_IMX6UL_IOMUXC_GPR_ADDR);
65
-
66
/*
67
* SDMA
68
*/
40
--
69
--
41
2.25.1
70
2.34.1
diff view generated by jsdifflib
New patch
[PULL 12/24] Refactor i.MX6UL processor code
1
From: Jean-Christophe Dubois <jcd@tribudubois.net>
1
2
3
* Add Addr and size definition for most i.MX6UL devices in i.MX6UL header file.
4
* Use those newly defined named constants whenever possible.
5
* Standardize the way we init a familly of unimplemented devices
6
- SAI
7
- PWM
8
- CAN
9
* Add/rework few comments
10
11
Signed-off-by: Jean-Christophe Dubois <jcd@tribudubois.net>
12
Message-id: d579043fbd4e4b490370783fda43fc02c8e9be75.1692964892.git.jcd@tribudubois.net
13
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
14
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
15
---
16
include/hw/arm/fsl-imx6ul.h | 156 +++++++++++++++++++++++++++++++-----
17
hw/arm/fsl-imx6ul.c | 147 ++++++++++++++++++++++-----------
18
2 files changed, 232 insertions(+), 71 deletions(-)
19
20
diff --git a/include/hw/arm/fsl-imx6ul.h b/include/hw/arm/fsl-imx6ul.h
21
index XXXXXXX..XXXXXXX 100644
22
--- a/include/hw/arm/fsl-imx6ul.h
23
+++ b/include/hw/arm/fsl-imx6ul.h
24
@@ -XXX,XX +XXX,XX @@
25
#include "exec/memory.h"
26
#include "cpu.h"
27
#include "qom/object.h"
28
+#include "qemu/units.h"
29
30
#define TYPE_FSL_IMX6UL "fsl-imx6ul"
31
OBJECT_DECLARE_SIMPLE_TYPE(FslIMX6ULState, FSL_IMX6UL)
32
@@ -XXX,XX +XXX,XX @@ enum FslIMX6ULConfiguration {
33
FSL_IMX6UL_NUM_ADCS = 2,
34
FSL_IMX6UL_NUM_USB_PHYS = 2,
35
FSL_IMX6UL_NUM_USBS = 2,
36
+ FSL_IMX6UL_NUM_SAIS = 3,
37
+ FSL_IMX6UL_NUM_CANS = 2,
38
+ FSL_IMX6UL_NUM_PWMS = 4,
39
};
40
41
struct FslIMX6ULState {
42
@@ -XXX,XX +XXX,XX @@ struct FslIMX6ULState {
43
44
enum FslIMX6ULMemoryMap {
45
FSL_IMX6UL_MMDC_ADDR = 0x80000000,
46
- FSL_IMX6UL_MMDC_SIZE = 2 * 1024 * 1024 * 1024UL,
47
+ FSL_IMX6UL_MMDC_SIZE = (2 * GiB),
48
49
FSL_IMX6UL_QSPI1_MEM_ADDR = 0x60000000,
50
- FSL_IMX6UL_EIM_ALIAS_ADDR = 0x58000000,
51
- FSL_IMX6UL_EIM_CS_ADDR = 0x50000000,
52
- FSL_IMX6UL_AES_ENCRYPT_ADDR = 0x10000000,
53
- FSL_IMX6UL_QSPI1_RX_ADDR = 0x0C000000,
54
+ FSL_IMX6UL_QSPI1_MEM_SIZE = (256 * MiB),
55
56
- /* AIPS-2 */
57
+ FSL_IMX6UL_EIM_ALIAS_ADDR = 0x58000000,
58
+ FSL_IMX6UL_EIM_ALIAS_SIZE = (128 * MiB),
59
+
60
+ FSL_IMX6UL_EIM_CS_ADDR = 0x50000000,
61
+ FSL_IMX6UL_EIM_CS_SIZE = (128 * MiB),
62
+
63
+ FSL_IMX6UL_AES_ENCRYPT_ADDR = 0x10000000,
64
+ FSL_IMX6UL_AES_ENCRYPT_SIZE = (1 * MiB),
65
+
66
+ FSL_IMX6UL_QSPI1_RX_ADDR = 0x0C000000,
67
+ FSL_IMX6UL_QSPI1_RX_SIZE = (32 * MiB),
68
+
69
+ /* AIPS-2 Begin */
70
FSL_IMX6UL_UART6_ADDR = 0x021FC000,
71
+
72
FSL_IMX6UL_I2C4_ADDR = 0x021F8000,
73
+
74
FSL_IMX6UL_UART5_ADDR = 0x021F4000,
75
FSL_IMX6UL_UART4_ADDR = 0x021F0000,
76
FSL_IMX6UL_UART3_ADDR = 0x021EC000,
77
FSL_IMX6UL_UART2_ADDR = 0x021E8000,
78
+
79
FSL_IMX6UL_WDOG3_ADDR = 0x021E4000,
80
+
81
FSL_IMX6UL_QSPI_ADDR = 0x021E0000,
82
+ FSL_IMX6UL_QSPI_SIZE = 0x500,
83
+
84
FSL_IMX6UL_SYS_CNT_CTRL_ADDR = 0x021DC000,
85
+ FSL_IMX6UL_SYS_CNT_CTRL_SIZE = (16 * KiB),
86
+
87
FSL_IMX6UL_SYS_CNT_CMP_ADDR = 0x021D8000,
88
+ FSL_IMX6UL_SYS_CNT_CMP_SIZE = (16 * KiB),
89
+
90
FSL_IMX6UL_SYS_CNT_RD_ADDR = 0x021D4000,
91
+ FSL_IMX6UL_SYS_CNT_RD_SIZE = (16 * KiB),
92
+
93
FSL_IMX6UL_TZASC_ADDR = 0x021D0000,
94
+ FSL_IMX6UL_TZASC_SIZE = (16 * KiB),
95
+
96
FSL_IMX6UL_PXP_ADDR = 0x021CC000,
97
+ FSL_IMX6UL_PXP_SIZE = (16 * KiB),
98
+
99
FSL_IMX6UL_LCDIF_ADDR = 0x021C8000,
100
+ FSL_IMX6UL_LCDIF_SIZE = 0x100,
101
+
102
FSL_IMX6UL_CSI_ADDR = 0x021C4000,
103
+ FSL_IMX6UL_CSI_SIZE = 0x100,
104
+
105
FSL_IMX6UL_CSU_ADDR = 0x021C0000,
106
+ FSL_IMX6UL_CSU_SIZE = (16 * KiB),
107
+
108
FSL_IMX6UL_OCOTP_CTRL_ADDR = 0x021BC000,
109
+ FSL_IMX6UL_OCOTP_CTRL_SIZE = (4 * KiB),
110
+
111
FSL_IMX6UL_EIM_ADDR = 0x021B8000,
112
+ FSL_IMX6UL_EIM_SIZE = 0x100,
113
+
114
FSL_IMX6UL_SIM2_ADDR = 0x021B4000,
115
+
116
FSL_IMX6UL_MMDC_CFG_ADDR = 0x021B0000,
117
+ FSL_IMX6UL_MMDC_CFG_SIZE = (4 * KiB),
118
+
119
FSL_IMX6UL_ROMCP_ADDR = 0x021AC000,
120
+ FSL_IMX6UL_ROMCP_SIZE = 0x300,
121
+
122
FSL_IMX6UL_I2C3_ADDR = 0x021A8000,
123
FSL_IMX6UL_I2C2_ADDR = 0x021A4000,
124
FSL_IMX6UL_I2C1_ADDR = 0x021A0000,
125
+
126
FSL_IMX6UL_ADC2_ADDR = 0x0219C000,
127
FSL_IMX6UL_ADC1_ADDR = 0x02198000,
128
+ FSL_IMX6UL_ADCn_SIZE = 0x100,
129
+
130
FSL_IMX6UL_USDHC2_ADDR = 0x02194000,
131
FSL_IMX6UL_USDHC1_ADDR = 0x02190000,
132
- FSL_IMX6UL_SIM1_ADDR = 0x0218C000,
133
- FSL_IMX6UL_ENET1_ADDR = 0x02188000,
134
- FSL_IMX6UL_USBO2_USBMISC_ADDR = 0x02184800,
135
- FSL_IMX6UL_USBO2_USB_ADDR = 0x02184000,
136
- FSL_IMX6UL_USBO2_PL301_ADDR = 0x02180000,
137
- FSL_IMX6UL_AIPS2_CFG_ADDR = 0x0217C000,
138
- FSL_IMX6UL_CAAM_ADDR = 0x02140000,
139
- FSL_IMX6UL_A7MPCORE_DAP_ADDR = 0x02100000,
140
141
- /* AIPS-1 */
142
+ FSL_IMX6UL_SIM1_ADDR = 0x0218C000,
143
+ FSL_IMX6UL_SIMn_SIZE = (16 * KiB),
144
+
145
+ FSL_IMX6UL_ENET1_ADDR = 0x02188000,
146
+
147
+ FSL_IMX6UL_USBO2_USBMISC_ADDR = 0x02184800,
148
+ FSL_IMX6UL_USBO2_USB1_ADDR = 0x02184000,
149
+ FSL_IMX6UL_USBO2_USB2_ADDR = 0x02184200,
150
+
151
+ FSL_IMX6UL_USBO2_PL301_ADDR = 0x02180000,
152
+ FSL_IMX6UL_USBO2_PL301_SIZE = (16 * KiB),
153
+
154
+ FSL_IMX6UL_AIPS2_CFG_ADDR = 0x0217C000,
155
+ FSL_IMX6UL_AIPS2_CFG_SIZE = 0x100,
156
+
157
+ FSL_IMX6UL_CAAM_ADDR = 0x02140000,
158
+ FSL_IMX6UL_CAAM_SIZE = (16 * KiB),
159
+
160
+ FSL_IMX6UL_A7MPCORE_DAP_ADDR = 0x02100000,
161
+ FSL_IMX6UL_A7MPCORE_DAP_SIZE = (4 * KiB),
162
+ /* AIPS-2 End */
163
+
164
+ /* AIPS-1 Begin */
165
FSL_IMX6UL_PWM8_ADDR = 0x020FC000,
166
FSL_IMX6UL_PWM7_ADDR = 0x020F8000,
167
FSL_IMX6UL_PWM6_ADDR = 0x020F4000,
168
FSL_IMX6UL_PWM5_ADDR = 0x020F0000,
169
+
170
FSL_IMX6UL_SDMA_ADDR = 0x020EC000,
171
+ FSL_IMX6UL_SDMA_SIZE = 0x300,
172
+
173
FSL_IMX6UL_GPT2_ADDR = 0x020E8000,
174
+
175
FSL_IMX6UL_IOMUXC_GPR_ADDR = 0x020E4000,
176
+ FSL_IMX6UL_IOMUXC_GPR_SIZE = 0x40,
177
+
178
FSL_IMX6UL_IOMUXC_ADDR = 0x020E0000,
179
+ FSL_IMX6UL_IOMUXC_SIZE = 0x700,
180
+
181
FSL_IMX6UL_GPC_ADDR = 0x020DC000,
182
+
183
FSL_IMX6UL_SRC_ADDR = 0x020D8000,
184
+
185
FSL_IMX6UL_EPIT2_ADDR = 0x020D4000,
186
FSL_IMX6UL_EPIT1_ADDR = 0x020D0000,
187
+
188
FSL_IMX6UL_SNVS_HP_ADDR = 0x020CC000,
189
+
190
FSL_IMX6UL_USBPHY2_ADDR = 0x020CA000,
191
- FSL_IMX6UL_USBPHY2_SIZE = (4 * 1024),
192
FSL_IMX6UL_USBPHY1_ADDR = 0x020C9000,
193
- FSL_IMX6UL_USBPHY1_SIZE = (4 * 1024),
194
+
195
FSL_IMX6UL_ANALOG_ADDR = 0x020C8000,
196
+ FSL_IMX6UL_ANALOG_SIZE = 0x300,
197
+
198
FSL_IMX6UL_CCM_ADDR = 0x020C4000,
199
+
200
FSL_IMX6UL_WDOG2_ADDR = 0x020C0000,
201
FSL_IMX6UL_WDOG1_ADDR = 0x020BC000,
202
+
203
FSL_IMX6UL_KPP_ADDR = 0x020B8000,
204
+ FSL_IMX6UL_KPP_SIZE = 0x10,
205
+
206
FSL_IMX6UL_ENET2_ADDR = 0x020B4000,
207
+
208
FSL_IMX6UL_SNVS_LP_ADDR = 0x020B0000,
209
+ FSL_IMX6UL_SNVS_LP_SIZE = (16 * KiB),
210
+
211
FSL_IMX6UL_GPIO5_ADDR = 0x020AC000,
212
FSL_IMX6UL_GPIO4_ADDR = 0x020A8000,
213
FSL_IMX6UL_GPIO3_ADDR = 0x020A4000,
214
FSL_IMX6UL_GPIO2_ADDR = 0x020A0000,
215
FSL_IMX6UL_GPIO1_ADDR = 0x0209C000,
216
+
217
FSL_IMX6UL_GPT1_ADDR = 0x02098000,
218
+
219
FSL_IMX6UL_CAN2_ADDR = 0x02094000,
220
FSL_IMX6UL_CAN1_ADDR = 0x02090000,
221
+ FSL_IMX6UL_CANn_SIZE = (4 * KiB),
222
+
223
FSL_IMX6UL_PWM4_ADDR = 0x0208C000,
224
FSL_IMX6UL_PWM3_ADDR = 0x02088000,
225
FSL_IMX6UL_PWM2_ADDR = 0x02084000,
226
FSL_IMX6UL_PWM1_ADDR = 0x02080000,
227
+ FSL_IMX6UL_PWMn_SIZE = 0x20,
228
+
229
FSL_IMX6UL_AIPS1_CFG_ADDR = 0x0207C000,
230
+ FSL_IMX6UL_AIPS1_CFG_SIZE = (16 * KiB),
231
+
232
FSL_IMX6UL_BEE_ADDR = 0x02044000,
233
+ FSL_IMX6UL_BEE_SIZE = (16 * KiB),
234
+
235
FSL_IMX6UL_TOUCH_CTRL_ADDR = 0x02040000,
236
+ FSL_IMX6UL_TOUCH_CTRL_SIZE = 0x100,
237
+
238
FSL_IMX6UL_SPBA_ADDR = 0x0203C000,
239
+ FSL_IMX6UL_SPBA_SIZE = 0x100,
240
+
241
FSL_IMX6UL_ASRC_ADDR = 0x02034000,
242
+ FSL_IMX6UL_ASRC_SIZE = 0x100,
243
+
244
FSL_IMX6UL_SAI3_ADDR = 0x02030000,
245
FSL_IMX6UL_SAI2_ADDR = 0x0202C000,
246
FSL_IMX6UL_SAI1_ADDR = 0x02028000,
247
+ FSL_IMX6UL_SAIn_SIZE = 0x200,
248
+
249
FSL_IMX6UL_UART8_ADDR = 0x02024000,
250
FSL_IMX6UL_UART1_ADDR = 0x02020000,
251
FSL_IMX6UL_UART7_ADDR = 0x02018000,
252
+
253
FSL_IMX6UL_ECSPI4_ADDR = 0x02014000,
254
FSL_IMX6UL_ECSPI3_ADDR = 0x02010000,
255
FSL_IMX6UL_ECSPI2_ADDR = 0x0200C000,
256
FSL_IMX6UL_ECSPI1_ADDR = 0x02008000,
257
+
258
FSL_IMX6UL_SPDIF_ADDR = 0x02004000,
259
+ FSL_IMX6UL_SPDIF_SIZE = 0x100,
260
+ /* AIPS-1 End */
261
+
262
+ FSL_IMX6UL_BCH_ADDR = 0x01808000,
263
+ FSL_IMX6UL_BCH_SIZE = 0x200,
264
+
265
+ FSL_IMX6UL_GPMI_ADDR = 0x01806000,
266
+ FSL_IMX6UL_GPMI_SIZE = 0x200,
267
268
FSL_IMX6UL_APBH_DMA_ADDR = 0x01804000,
269
- FSL_IMX6UL_APBH_DMA_SIZE = (32 * 1024),
270
+ FSL_IMX6UL_APBH_DMA_SIZE = (4 * KiB),
271
272
FSL_IMX6UL_A7MPCORE_ADDR = 0x00A00000,
273
274
FSL_IMX6UL_OCRAM_ALIAS_ADDR = 0x00920000,
275
- FSL_IMX6UL_OCRAM_ALIAS_SIZE = 0x00060000,
276
+ FSL_IMX6UL_OCRAM_ALIAS_SIZE = (384 * KiB),
277
+
278
FSL_IMX6UL_OCRAM_MEM_ADDR = 0x00900000,
279
- FSL_IMX6UL_OCRAM_MEM_SIZE = 0x00020000,
280
+ FSL_IMX6UL_OCRAM_MEM_SIZE = (128 * KiB),
281
+
282
FSL_IMX6UL_CAAM_MEM_ADDR = 0x00100000,
283
- FSL_IMX6UL_CAAM_MEM_SIZE = 0x00008000,
284
+ FSL_IMX6UL_CAAM_MEM_SIZE = (32 * KiB),
285
+
286
FSL_IMX6UL_ROM_ADDR = 0x00000000,
287
- FSL_IMX6UL_ROM_SIZE = 0x00018000,
288
+ FSL_IMX6UL_ROM_SIZE = (96 * KiB),
289
};
290
291
enum FslIMX6ULIRQs {
292
diff --git a/hw/arm/fsl-imx6ul.c b/hw/arm/fsl-imx6ul.c
293
index XXXXXXX..XXXXXXX 100644
294
--- a/hw/arm/fsl-imx6ul.c
295
+++ b/hw/arm/fsl-imx6ul.c
296
@@ -XXX,XX +XXX,XX @@ static void fsl_imx6ul_init(Object *obj)
297
object_initialize_child(obj, "snvs", &s->snvs, TYPE_IMX7_SNVS);
298
299
/*
300
- * GPIOs 1 to 5
301
+ * GPIOs
302
*/
303
for (i = 0; i < FSL_IMX6UL_NUM_GPIOS; i++) {
304
snprintf(name, NAME_SIZE, "gpio%d", i);
305
@@ -XXX,XX +XXX,XX @@ static void fsl_imx6ul_init(Object *obj)
306
}
307
308
/*
309
- * GPT 1, 2
310
+ * GPTs
311
*/
312
for (i = 0; i < FSL_IMX6UL_NUM_GPTS; i++) {
313
snprintf(name, NAME_SIZE, "gpt%d", i);
314
@@ -XXX,XX +XXX,XX @@ static void fsl_imx6ul_init(Object *obj)
315
}
316
317
/*
318
- * EPIT 1, 2
319
+ * EPITs
320
*/
321
for (i = 0; i < FSL_IMX6UL_NUM_EPITS; i++) {
322
snprintf(name, NAME_SIZE, "epit%d", i + 1);
323
@@ -XXX,XX +XXX,XX @@ static void fsl_imx6ul_init(Object *obj)
324
}
325
326
/*
327
- * eCSPI
328
+ * eCSPIs
329
*/
330
for (i = 0; i < FSL_IMX6UL_NUM_ECSPIS; i++) {
331
snprintf(name, NAME_SIZE, "spi%d", i + 1);
332
@@ -XXX,XX +XXX,XX @@ static void fsl_imx6ul_init(Object *obj)
333
}
334
335
/*
336
- * I2C
337
+ * I2Cs
338
*/
339
for (i = 0; i < FSL_IMX6UL_NUM_I2CS; i++) {
340
snprintf(name, NAME_SIZE, "i2c%d", i + 1);
341
@@ -XXX,XX +XXX,XX @@ static void fsl_imx6ul_init(Object *obj)
342
}
343
344
/*
345
- * UART
346
+ * UARTs
347
*/
348
for (i = 0; i < FSL_IMX6UL_NUM_UARTS; i++) {
349
snprintf(name, NAME_SIZE, "uart%d", i);
350
@@ -XXX,XX +XXX,XX @@ static void fsl_imx6ul_init(Object *obj)
351
}
352
353
/*
354
- * Ethernet
355
+ * Ethernets
356
*/
357
for (i = 0; i < FSL_IMX6UL_NUM_ETHS; i++) {
358
snprintf(name, NAME_SIZE, "eth%d", i);
359
object_initialize_child(obj, name, &s->eth[i], TYPE_IMX_ENET);
360
}
361
362
- /* USB */
363
+ /*
364
+ * USB PHYs
365
+ */
366
for (i = 0; i < FSL_IMX6UL_NUM_USB_PHYS; i++) {
367
snprintf(name, NAME_SIZE, "usbphy%d", i);
368
object_initialize_child(obj, name, &s->usbphy[i], TYPE_IMX_USBPHY);
369
}
370
+
371
+ /*
372
+ * USBs
373
+ */
374
for (i = 0; i < FSL_IMX6UL_NUM_USBS; i++) {
375
snprintf(name, NAME_SIZE, "usb%d", i);
376
object_initialize_child(obj, name, &s->usb[i], TYPE_CHIPIDEA);
377
}
378
379
/*
380
- * SDHCI
381
+ * SDHCIs
382
*/
383
for (i = 0; i < FSL_IMX6UL_NUM_USDHCS; i++) {
384
snprintf(name, NAME_SIZE, "usdhc%d", i);
385
@@ -XXX,XX +XXX,XX @@ static void fsl_imx6ul_init(Object *obj)
386
}
387
388
/*
389
- * Watchdog
390
+ * Watchdogs
391
*/
392
for (i = 0; i < FSL_IMX6UL_NUM_WDTS; i++) {
393
snprintf(name, NAME_SIZE, "wdt%d", i);
394
@@ -XXX,XX +XXX,XX @@ static void fsl_imx6ul_realize(DeviceState *dev, Error **errp)
395
* A7MPCORE DAP
396
*/
397
create_unimplemented_device("a7mpcore-dap", FSL_IMX6UL_A7MPCORE_DAP_ADDR,
398
- 0x100000);
399
+ FSL_IMX6UL_A7MPCORE_DAP_SIZE);
400
401
/*
402
- * GPT 1, 2
403
+ * GPTs
404
*/
405
for (i = 0; i < FSL_IMX6UL_NUM_GPTS; i++) {
406
static const hwaddr FSL_IMX6UL_GPTn_ADDR[FSL_IMX6UL_NUM_GPTS] = {
407
@@ -XXX,XX +XXX,XX @@ static void fsl_imx6ul_realize(DeviceState *dev, Error **errp)
408
}
409
410
/*
411
- * EPIT 1, 2
412
+ * EPITs
413
*/
414
for (i = 0; i < FSL_IMX6UL_NUM_EPITS; i++) {
415
static const hwaddr FSL_IMX6UL_EPITn_ADDR[FSL_IMX6UL_NUM_EPITS] = {
416
@@ -XXX,XX +XXX,XX @@ static void fsl_imx6ul_realize(DeviceState *dev, Error **errp)
417
}
418
419
/*
420
- * GPIO
421
+ * GPIOs
422
*/
423
for (i = 0; i < FSL_IMX6UL_NUM_GPIOS; i++) {
424
static const hwaddr FSL_IMX6UL_GPIOn_ADDR[FSL_IMX6UL_NUM_GPIOS] = {
425
@@ -XXX,XX +XXX,XX @@ static void fsl_imx6ul_realize(DeviceState *dev, Error **errp)
426
}
427
428
/*
429
- * IOMUXC and IOMUXC_GPR
430
+ * IOMUXC
431
*/
432
- for (i = 0; i < 1; i++) {
433
- static const hwaddr FSL_IMX6UL_IOMUXCn_ADDR[FSL_IMX6UL_NUM_IOMUXCS] = {
434
- FSL_IMX6UL_IOMUXC_ADDR,
435
- FSL_IMX6UL_IOMUXC_GPR_ADDR,
436
- };
437
-
438
- snprintf(name, NAME_SIZE, "iomuxc%d", i);
439
- create_unimplemented_device(name, FSL_IMX6UL_IOMUXCn_ADDR[i], 0x4000);
440
- }
441
+ create_unimplemented_device("iomuxc", FSL_IMX6UL_IOMUXC_ADDR,
442
+ FSL_IMX6UL_IOMUXC_SIZE);
443
+ create_unimplemented_device("iomuxc_gpr", FSL_IMX6UL_IOMUXC_GPR_ADDR,
444
+ FSL_IMX6UL_IOMUXC_GPR_SIZE);
445
446
/*
447
* CCM
448
@@ -XXX,XX +XXX,XX @@ static void fsl_imx6ul_realize(DeviceState *dev, Error **errp)
449
sysbus_realize(SYS_BUS_DEVICE(&s->gpcv2), &error_abort);
450
sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpcv2), 0, FSL_IMX6UL_GPC_ADDR);
451
452
- /* Initialize all ECSPI */
453
+ /*
454
+ * ECSPIs
455
+ */
456
for (i = 0; i < FSL_IMX6UL_NUM_ECSPIS; i++) {
457
static const hwaddr FSL_IMX6UL_SPIn_ADDR[FSL_IMX6UL_NUM_ECSPIS] = {
458
FSL_IMX6UL_ECSPI1_ADDR,
459
@@ -XXX,XX +XXX,XX @@ static void fsl_imx6ul_realize(DeviceState *dev, Error **errp)
460
}
461
462
/*
463
- * I2C
464
+ * I2Cs
465
*/
466
for (i = 0; i < FSL_IMX6UL_NUM_I2CS; i++) {
467
static const hwaddr FSL_IMX6UL_I2Cn_ADDR[FSL_IMX6UL_NUM_I2CS] = {
468
@@ -XXX,XX +XXX,XX @@ static void fsl_imx6ul_realize(DeviceState *dev, Error **errp)
469
}
470
471
/*
472
- * UART
473
+ * UARTs
474
*/
475
for (i = 0; i < FSL_IMX6UL_NUM_UARTS; i++) {
476
static const hwaddr FSL_IMX6UL_UARTn_ADDR[FSL_IMX6UL_NUM_UARTS] = {
477
@@ -XXX,XX +XXX,XX @@ static void fsl_imx6ul_realize(DeviceState *dev, Error **errp)
478
}
479
480
/*
481
- * Ethernet
482
+ * Ethernets
483
*
484
* We must use two loops since phy_connected affects the other interface
485
* and we have to set all properties before calling sysbus_realize().
486
@@ -XXX,XX +XXX,XX @@ static void fsl_imx6ul_realize(DeviceState *dev, Error **errp)
487
FSL_IMX6UL_ENETn_TIMER_IRQ[i]));
488
}
489
490
- /* USB */
491
+ /*
492
+ * USB PHYs
493
+ */
494
for (i = 0; i < FSL_IMX6UL_NUM_USB_PHYS; i++) {
495
+ static const hwaddr
496
+ FSL_IMX6UL_USB_PHYn_ADDR[FSL_IMX6UL_NUM_USB_PHYS] = {
497
+ FSL_IMX6UL_USBPHY1_ADDR,
498
+ FSL_IMX6UL_USBPHY2_ADDR,
499
+ };
500
+
501
sysbus_realize(SYS_BUS_DEVICE(&s->usbphy[i]), &error_abort);
502
sysbus_mmio_map(SYS_BUS_DEVICE(&s->usbphy[i]), 0,
503
- FSL_IMX6UL_USBPHY1_ADDR + i * 0x1000);
504
+ FSL_IMX6UL_USB_PHYn_ADDR[i]);
505
}
506
507
+ /*
508
+ * USBs
509
+ */
510
for (i = 0; i < FSL_IMX6UL_NUM_USBS; i++) {
511
+ static const hwaddr FSL_IMX6UL_USB02_USBn_ADDR[FSL_IMX6UL_NUM_USBS] = {
512
+ FSL_IMX6UL_USBO2_USB1_ADDR,
513
+ FSL_IMX6UL_USBO2_USB2_ADDR,
514
+ };
515
+
516
static const int FSL_IMX6UL_USBn_IRQ[] = {
517
FSL_IMX6UL_USB1_IRQ,
518
FSL_IMX6UL_USB2_IRQ,
519
};
520
+
521
sysbus_realize(SYS_BUS_DEVICE(&s->usb[i]), &error_abort);
522
sysbus_mmio_map(SYS_BUS_DEVICE(&s->usb[i]), 0,
523
- FSL_IMX6UL_USBO2_USB_ADDR + i * 0x200);
524
+ FSL_IMX6UL_USB02_USBn_ADDR[i]);
525
sysbus_connect_irq(SYS_BUS_DEVICE(&s->usb[i]), 0,
526
qdev_get_gpio_in(DEVICE(&s->a7mpcore),
527
FSL_IMX6UL_USBn_IRQ[i]));
528
}
529
530
/*
531
- * USDHC
532
+ * USDHCs
533
*/
534
for (i = 0; i < FSL_IMX6UL_NUM_USDHCS; i++) {
535
static const hwaddr FSL_IMX6UL_USDHCn_ADDR[FSL_IMX6UL_NUM_USDHCS] = {
536
@@ -XXX,XX +XXX,XX @@ static void fsl_imx6ul_realize(DeviceState *dev, Error **errp)
537
sysbus_mmio_map(SYS_BUS_DEVICE(&s->snvs), 0, FSL_IMX6UL_SNVS_HP_ADDR);
538
539
/*
540
- * Watchdog
541
+ * Watchdogs
542
*/
543
for (i = 0; i < FSL_IMX6UL_NUM_WDTS; i++) {
544
static const hwaddr FSL_IMX6UL_WDOGn_ADDR[FSL_IMX6UL_NUM_WDTS] = {
545
@@ -XXX,XX +XXX,XX @@ static void fsl_imx6ul_realize(DeviceState *dev, Error **errp)
546
FSL_IMX6UL_WDOG2_ADDR,
547
FSL_IMX6UL_WDOG3_ADDR,
548
};
549
+
550
static const int FSL_IMX6UL_WDOGn_IRQ[FSL_IMX6UL_NUM_WDTS] = {
551
FSL_IMX6UL_WDOG1_IRQ,
552
FSL_IMX6UL_WDOG2_IRQ,
553
@@ -XXX,XX +XXX,XX @@ static void fsl_imx6ul_realize(DeviceState *dev, Error **errp)
554
/*
555
* SDMA
556
*/
557
- create_unimplemented_device("sdma", FSL_IMX6UL_SDMA_ADDR, 0x4000);
558
+ create_unimplemented_device("sdma", FSL_IMX6UL_SDMA_ADDR,
559
+ FSL_IMX6UL_SDMA_SIZE);
560
561
/*
562
- * SAI (Audio SSI (Synchronous Serial Interface))
563
+ * SAIs (Audio SSI (Synchronous Serial Interface))
564
*/
565
- create_unimplemented_device("sai1", FSL_IMX6UL_SAI1_ADDR, 0x4000);
566
- create_unimplemented_device("sai2", FSL_IMX6UL_SAI2_ADDR, 0x4000);
567
- create_unimplemented_device("sai3", FSL_IMX6UL_SAI3_ADDR, 0x4000);
568
+ for (i = 0; i < FSL_IMX6UL_NUM_SAIS; i++) {
569
+ static const hwaddr FSL_IMX6UL_SAIn_ADDR[FSL_IMX6UL_NUM_SAIS] = {
570
+ FSL_IMX6UL_SAI1_ADDR,
571
+ FSL_IMX6UL_SAI2_ADDR,
572
+ FSL_IMX6UL_SAI3_ADDR,
573
+ };
574
+
575
+ snprintf(name, NAME_SIZE, "sai%d", i);
576
+ create_unimplemented_device(name, FSL_IMX6UL_SAIn_ADDR[i],
577
+ FSL_IMX6UL_SAIn_SIZE);
578
+ }
579
580
/*
581
- * PWM
582
+ * PWMs
583
*/
584
- create_unimplemented_device("pwm1", FSL_IMX6UL_PWM1_ADDR, 0x4000);
585
- create_unimplemented_device("pwm2", FSL_IMX6UL_PWM2_ADDR, 0x4000);
586
- create_unimplemented_device("pwm3", FSL_IMX6UL_PWM3_ADDR, 0x4000);
587
- create_unimplemented_device("pwm4", FSL_IMX6UL_PWM4_ADDR, 0x4000);
588
+ for (i = 0; i < FSL_IMX6UL_NUM_PWMS; i++) {
589
+ static const hwaddr FSL_IMX6UL_PWMn_ADDR[FSL_IMX6UL_NUM_PWMS] = {
590
+ FSL_IMX6UL_PWM1_ADDR,
591
+ FSL_IMX6UL_PWM2_ADDR,
592
+ FSL_IMX6UL_PWM3_ADDR,
593
+ FSL_IMX6UL_PWM4_ADDR,
594
+ };
595
+
596
+ snprintf(name, NAME_SIZE, "pwm%d", i);
597
+ create_unimplemented_device(name, FSL_IMX6UL_PWMn_ADDR[i],
598
+ FSL_IMX6UL_PWMn_SIZE);
599
+ }
600
601
/*
602
* Audio ASRC (asynchronous sample rate converter)
603
*/
604
- create_unimplemented_device("asrc", FSL_IMX6UL_ASRC_ADDR, 0x4000);
605
+ create_unimplemented_device("asrc", FSL_IMX6UL_ASRC_ADDR,
606
+ FSL_IMX6UL_ASRC_SIZE);
607
608
/*
609
- * CAN
610
+ * CANs
611
*/
612
- create_unimplemented_device("can1", FSL_IMX6UL_CAN1_ADDR, 0x4000);
613
- create_unimplemented_device("can2", FSL_IMX6UL_CAN2_ADDR, 0x4000);
614
+ for (i = 0; i < FSL_IMX6UL_NUM_CANS; i++) {
615
+ static const hwaddr FSL_IMX6UL_CANn_ADDR[FSL_IMX6UL_NUM_CANS] = {
616
+ FSL_IMX6UL_CAN1_ADDR,
617
+ FSL_IMX6UL_CAN2_ADDR,
618
+ };
619
+
620
+ snprintf(name, NAME_SIZE, "can%d", i);
621
+ create_unimplemented_device(name, FSL_IMX6UL_CANn_ADDR[i],
622
+ FSL_IMX6UL_CANn_SIZE);
623
+ }
624
625
/*
626
* APHB_DMA
627
@@ -XXX,XX +XXX,XX @@ static void fsl_imx6ul_realize(DeviceState *dev, Error **errp)
628
};
629
630
snprintf(name, NAME_SIZE, "adc%d", i);
631
- create_unimplemented_device(name, FSL_IMX6UL_ADCn_ADDR[i], 0x4000);
632
+ create_unimplemented_device(name, FSL_IMX6UL_ADCn_ADDR[i],
633
+ FSL_IMX6UL_ADCn_SIZE);
634
}
635
636
/*
637
* LCD
638
*/
639
- create_unimplemented_device("lcdif", FSL_IMX6UL_LCDIF_ADDR, 0x4000);
640
+ create_unimplemented_device("lcdif", FSL_IMX6UL_LCDIF_ADDR,
641
+ FSL_IMX6UL_LCDIF_SIZE);
642
643
/*
644
* ROM memory
645
--
646
2.34.1
diff view generated by jsdifflib
[PULL 09/10] hw/arm/virt: Fix devicetree warning about the SMMU node
[PULL 13/24] Add i.MX6UL missing devices.
1
From: Jean-Philippe Brucker <jean-philippe@linaro.org>
1
From: Jean-Christophe Dubois <jcd@tribudubois.net>
2
2
3
The SMMUv3 node isn't expected to have clock properties
3
* Add TZASC as unimplemented device.
4
(unlike the SMMUv2). Fix the corresponding dt-validate warning:
4
- Allow bare metal application to access this (unimplemented) device
5
* Add CSU as unimplemented device.
6
- Allow bare metal application to access this (unimplemented) device
7
* Add 4 missing PWM devices
5
8
6
smmuv3@9050000: 'clock-names', 'clocks' do not match any of the regexes: 'pinctrl-[0-9]+'
9
Signed-off-by: Jean-Christophe Dubois <jcd@tribudubois.net>
7
From schema: linux/Documentation/devicetree/bindings/iommu/arm,smmu-v3.yaml
10
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
8
11
Message-id: 59e4dc56e14eccfefd379275ec19048dff9c10b3.1692964892.git.jcd@tribudubois.net
9
Signed-off-by: Jean-Philippe Brucker <jean-philippe@linaro.org>
10
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
11
[PMM: tweaked commit message as suggested by Eric]
12
Reviewed-by: Eric Auger <eric.auger@redhat.com>
13
Message-id: 20220927100347.176606-7-jean-philippe@linaro.org
14
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
12
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
15
---
13
---
16
hw/arm/virt.c | 2 --
14
include/hw/arm/fsl-imx6ul.h | 2 +-
17
1 file changed, 2 deletions(-)
15
hw/arm/fsl-imx6ul.c | 16 ++++++++++++++++
16
2 files changed, 17 insertions(+), 1 deletion(-)
18
17
19
diff --git a/hw/arm/virt.c b/hw/arm/virt.c
18
diff --git a/include/hw/arm/fsl-imx6ul.h b/include/hw/arm/fsl-imx6ul.h
20
index XXXXXXX..XXXXXXX 100644
19
index XXXXXXX..XXXXXXX 100644
21
--- a/hw/arm/virt.c
20
--- a/include/hw/arm/fsl-imx6ul.h
22
+++ b/hw/arm/virt.c
21
+++ b/include/hw/arm/fsl-imx6ul.h
23
@@ -XXX,XX +XXX,XX @@ static void create_smmu(const VirtMachineState *vms,
22
@@ -XXX,XX +XXX,XX @@ enum FslIMX6ULConfiguration {
24
qemu_fdt_setprop(ms->fdt, node, "interrupt-names", irq_names,
23
FSL_IMX6UL_NUM_USBS = 2,
25
sizeof(irq_names));
24
FSL_IMX6UL_NUM_SAIS = 3,
26
25
FSL_IMX6UL_NUM_CANS = 2,
27
- qemu_fdt_setprop_cell(ms->fdt, node, "clocks", vms->clock_phandle);
26
- FSL_IMX6UL_NUM_PWMS = 4,
28
- qemu_fdt_setprop_string(ms->fdt, node, "clock-names", "apb_pclk");
27
+ FSL_IMX6UL_NUM_PWMS = 8,
29
qemu_fdt_setprop(ms->fdt, node, "dma-coherent", NULL, 0);
28
};
30
29
31
qemu_fdt_setprop_cell(ms->fdt, node, "#iommu-cells", 1);
30
struct FslIMX6ULState {
31
diff --git a/hw/arm/fsl-imx6ul.c b/hw/arm/fsl-imx6ul.c
32
index XXXXXXX..XXXXXXX 100644
33
--- a/hw/arm/fsl-imx6ul.c
34
+++ b/hw/arm/fsl-imx6ul.c
35
@@ -XXX,XX +XXX,XX @@ static void fsl_imx6ul_realize(DeviceState *dev, Error **errp)
36
FSL_IMX6UL_PWM2_ADDR,
37
FSL_IMX6UL_PWM3_ADDR,
38
FSL_IMX6UL_PWM4_ADDR,
39
+ FSL_IMX6UL_PWM5_ADDR,
40
+ FSL_IMX6UL_PWM6_ADDR,
41
+ FSL_IMX6UL_PWM7_ADDR,
42
+ FSL_IMX6UL_PWM8_ADDR,
43
};
44
45
snprintf(name, NAME_SIZE, "pwm%d", i);
46
@@ -XXX,XX +XXX,XX @@ static void fsl_imx6ul_realize(DeviceState *dev, Error **errp)
47
create_unimplemented_device("lcdif", FSL_IMX6UL_LCDIF_ADDR,
48
FSL_IMX6UL_LCDIF_SIZE);
49
50
+ /*
51
+ * CSU
52
+ */
53
+ create_unimplemented_device("csu", FSL_IMX6UL_CSU_ADDR,
54
+ FSL_IMX6UL_CSU_SIZE);
55
+
56
+ /*
57
+ * TZASC
58
+ */
59
+ create_unimplemented_device("tzasc", FSL_IMX6UL_TZASC_ADDR,
60
+ FSL_IMX6UL_TZASC_SIZE);
61
+
62
/*
63
* ROM memory
64
*/
32
--
65
--
33
2.25.1
66
2.34.1
67
68
diff view generated by jsdifflib
[PULL 07/10] hw/arm/virt: Fix devicetree warning about the GIC node
[PULL 14/24] Refactor i.MX7 processor code
1
From: Jean-Philippe Brucker <jean-philippe@linaro.org>
1
From: Jean-Christophe Dubois <jcd@tribudubois.net>
2
2
3
The GICv3 bindings requires a #msi-cells property for the ITS node. Fix
3
* Add Addr and size definition for all i.MX7 devices in i.MX7 header file.
4
the corresponding dt-validate warning:
4
* Use those newly defined named constants whenever possible.
5
* Standardize the way we init a familly of unimplemented devices
6
- SAI
7
- PWM
8
- CAN
9
* Add/rework few comments
5
10
6
interrupt-controller@8000000: msi-controller@8080000: '#msi-cells' is a required property
11
Signed-off-by: Jean-Christophe Dubois <jcd@tribudubois.net>
7
From schema: linux/Documentation/devicetree/bindings/interrupt-controller/arm,gic-v3.yaml
12
Message-id: 59e195d33e4d486a8d131392acd46633c8c10ed7.1692964892.git.jcd@tribudubois.net
8
9
Signed-off-by: Jean-Philippe Brucker <jean-philippe@linaro.org>
10
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
13
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
11
Reviewed-by: Eric Auger <eric.auger@redhat.com>
12
Message-id: 20220927100347.176606-3-jean-philippe@linaro.org
13
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
14
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
14
---
15
---
15
hw/arm/virt.c | 1 +
16
include/hw/arm/fsl-imx7.h | 330 ++++++++++++++++++++++++++++----------
16
1 file changed, 1 insertion(+)
17
hw/arm/fsl-imx7.c | 130 ++++++++++-----
18
2 files changed, 335 insertions(+), 125 deletions(-)
17
19
18
diff --git a/hw/arm/virt.c b/hw/arm/virt.c
20
diff --git a/include/hw/arm/fsl-imx7.h b/include/hw/arm/fsl-imx7.h
19
index XXXXXXX..XXXXXXX 100644
21
index XXXXXXX..XXXXXXX 100644
20
--- a/hw/arm/virt.c
22
--- a/include/hw/arm/fsl-imx7.h
21
+++ b/hw/arm/virt.c
23
+++ b/include/hw/arm/fsl-imx7.h
22
@@ -XXX,XX +XXX,XX @@ static void fdt_add_its_gic_node(VirtMachineState *vms)
24
@@ -XXX,XX +XXX,XX @@
23
qemu_fdt_setprop_string(ms->fdt, nodename, "compatible",
25
#include "hw/misc/imx7_ccm.h"
24
"arm,gic-v3-its");
26
#include "hw/misc/imx7_snvs.h"
25
qemu_fdt_setprop(ms->fdt, nodename, "msi-controller", NULL, 0);
27
#include "hw/misc/imx7_gpr.h"
26
+ qemu_fdt_setprop_cell(ms->fdt, nodename, "#msi-cells", 1);
28
-#include "hw/misc/imx6_src.h"
27
qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg",
29
#include "hw/watchdog/wdt_imx2.h"
28
2, vms->memmap[VIRT_GIC_ITS].base,
30
#include "hw/gpio/imx_gpio.h"
29
2, vms->memmap[VIRT_GIC_ITS].size);
31
#include "hw/char/imx_serial.h"
32
@@ -XXX,XX +XXX,XX @@
33
#include "hw/usb/chipidea.h"
34
#include "cpu.h"
35
#include "qom/object.h"
36
+#include "qemu/units.h"
37
38
#define TYPE_FSL_IMX7 "fsl-imx7"
39
OBJECT_DECLARE_SIMPLE_TYPE(FslIMX7State, FSL_IMX7)
40
@@ -XXX,XX +XXX,XX @@ enum FslIMX7Configuration {
41
FSL_IMX7_NUM_ECSPIS = 4,
42
FSL_IMX7_NUM_USBS = 3,
43
FSL_IMX7_NUM_ADCS = 2,
44
+ FSL_IMX7_NUM_SAIS = 3,
45
+ FSL_IMX7_NUM_CANS = 2,
46
+ FSL_IMX7_NUM_PWMS = 4,
47
};
48
49
struct FslIMX7State {
50
@@ -XXX,XX +XXX,XX @@ struct FslIMX7State {
51
52
enum FslIMX7MemoryMap {
53
FSL_IMX7_MMDC_ADDR = 0x80000000,
54
- FSL_IMX7_MMDC_SIZE = 2 * 1024 * 1024 * 1024UL,
55
+ FSL_IMX7_MMDC_SIZE = (2 * GiB),
56
57
- FSL_IMX7_GPIO1_ADDR = 0x30200000,
58
- FSL_IMX7_GPIO2_ADDR = 0x30210000,
59
- FSL_IMX7_GPIO3_ADDR = 0x30220000,
60
- FSL_IMX7_GPIO4_ADDR = 0x30230000,
61
- FSL_IMX7_GPIO5_ADDR = 0x30240000,
62
- FSL_IMX7_GPIO6_ADDR = 0x30250000,
63
- FSL_IMX7_GPIO7_ADDR = 0x30260000,
64
+ FSL_IMX7_QSPI1_MEM_ADDR = 0x60000000,
65
+ FSL_IMX7_QSPI1_MEM_SIZE = (256 * MiB),
66
67
- FSL_IMX7_IOMUXC_LPSR_GPR_ADDR = 0x30270000,
68
+ FSL_IMX7_PCIE1_MEM_ADDR = 0x40000000,
69
+ FSL_IMX7_PCIE1_MEM_SIZE = (256 * MiB),
70
71
- FSL_IMX7_WDOG1_ADDR = 0x30280000,
72
- FSL_IMX7_WDOG2_ADDR = 0x30290000,
73
- FSL_IMX7_WDOG3_ADDR = 0x302A0000,
74
- FSL_IMX7_WDOG4_ADDR = 0x302B0000,
75
+ FSL_IMX7_QSPI1_RX_BUF_ADDR = 0x34000000,
76
+ FSL_IMX7_QSPI1_RX_BUF_SIZE = (32 * MiB),
77
78
- FSL_IMX7_IOMUXC_LPSR_ADDR = 0x302C0000,
79
+ /* PCIe Peripherals */
80
+ FSL_IMX7_PCIE_REG_ADDR = 0x33800000,
81
82
- FSL_IMX7_GPT1_ADDR = 0x302D0000,
83
- FSL_IMX7_GPT2_ADDR = 0x302E0000,
84
- FSL_IMX7_GPT3_ADDR = 0x302F0000,
85
- FSL_IMX7_GPT4_ADDR = 0x30300000,
86
+ /* MMAP Peripherals */
87
+ FSL_IMX7_DMA_APBH_ADDR = 0x33000000,
88
+ FSL_IMX7_DMA_APBH_SIZE = 0x8000,
89
90
- FSL_IMX7_IOMUXC_ADDR = 0x30330000,
91
- FSL_IMX7_IOMUXC_GPR_ADDR = 0x30340000,
92
- FSL_IMX7_IOMUXCn_SIZE = 0x1000,
93
+ /* GPV configuration */
94
+ FSL_IMX7_GPV6_ADDR = 0x32600000,
95
+ FSL_IMX7_GPV5_ADDR = 0x32500000,
96
+ FSL_IMX7_GPV4_ADDR = 0x32400000,
97
+ FSL_IMX7_GPV3_ADDR = 0x32300000,
98
+ FSL_IMX7_GPV2_ADDR = 0x32200000,
99
+ FSL_IMX7_GPV1_ADDR = 0x32100000,
100
+ FSL_IMX7_GPV0_ADDR = 0x32000000,
101
+ FSL_IMX7_GPVn_SIZE = (1 * MiB),
102
103
- FSL_IMX7_OCOTP_ADDR = 0x30350000,
104
- FSL_IMX7_OCOTP_SIZE = 0x10000,
105
+ /* Arm Peripherals */
106
+ FSL_IMX7_A7MPCORE_ADDR = 0x31000000,
107
108
- FSL_IMX7_ANALOG_ADDR = 0x30360000,
109
- FSL_IMX7_SNVS_ADDR = 0x30370000,
110
- FSL_IMX7_CCM_ADDR = 0x30380000,
111
+ /* AIPS-3 Begin */
112
113
- FSL_IMX7_SRC_ADDR = 0x30390000,
114
- FSL_IMX7_SRC_SIZE = 0x1000,
115
+ FSL_IMX7_ENET2_ADDR = 0x30BF0000,
116
+ FSL_IMX7_ENET1_ADDR = 0x30BE0000,
117
118
- FSL_IMX7_ADC1_ADDR = 0x30610000,
119
- FSL_IMX7_ADC2_ADDR = 0x30620000,
120
- FSL_IMX7_ADCn_SIZE = 0x1000,
121
+ FSL_IMX7_SDMA_ADDR = 0x30BD0000,
122
+ FSL_IMX7_SDMA_SIZE = (4 * KiB),
123
124
- FSL_IMX7_PWM1_ADDR = 0x30660000,
125
- FSL_IMX7_PWM2_ADDR = 0x30670000,
126
- FSL_IMX7_PWM3_ADDR = 0x30680000,
127
- FSL_IMX7_PWM4_ADDR = 0x30690000,
128
- FSL_IMX7_PWMn_SIZE = 0x10000,
129
+ FSL_IMX7_EIM_ADDR = 0x30BC0000,
130
+ FSL_IMX7_EIM_SIZE = (4 * KiB),
131
132
- FSL_IMX7_PCIE_PHY_ADDR = 0x306D0000,
133
- FSL_IMX7_PCIE_PHY_SIZE = 0x10000,
134
+ FSL_IMX7_QSPI_ADDR = 0x30BB0000,
135
+ FSL_IMX7_QSPI_SIZE = 0x8000,
136
137
- FSL_IMX7_GPC_ADDR = 0x303A0000,
138
+ FSL_IMX7_SIM2_ADDR = 0x30BA0000,
139
+ FSL_IMX7_SIM1_ADDR = 0x30B90000,
140
+ FSL_IMX7_SIMn_SIZE = (4 * KiB),
141
+
142
+ FSL_IMX7_USDHC3_ADDR = 0x30B60000,
143
+ FSL_IMX7_USDHC2_ADDR = 0x30B50000,
144
+ FSL_IMX7_USDHC1_ADDR = 0x30B40000,
145
+
146
+ FSL_IMX7_USB3_ADDR = 0x30B30000,
147
+ FSL_IMX7_USBMISC3_ADDR = 0x30B30200,
148
+ FSL_IMX7_USB2_ADDR = 0x30B20000,
149
+ FSL_IMX7_USBMISC2_ADDR = 0x30B20200,
150
+ FSL_IMX7_USB1_ADDR = 0x30B10000,
151
+ FSL_IMX7_USBMISC1_ADDR = 0x30B10200,
152
+ FSL_IMX7_USBMISCn_SIZE = 0x200,
153
+
154
+ FSL_IMX7_USB_PL301_ADDR = 0x30AD0000,
155
+ FSL_IMX7_USB_PL301_SIZE = (64 * KiB),
156
+
157
+ FSL_IMX7_SEMAPHORE_HS_ADDR = 0x30AC0000,
158
+ FSL_IMX7_SEMAPHORE_HS_SIZE = (64 * KiB),
159
+
160
+ FSL_IMX7_MUB_ADDR = 0x30AB0000,
161
+ FSL_IMX7_MUA_ADDR = 0x30AA0000,
162
+ FSL_IMX7_MUn_SIZE = (KiB),
163
+
164
+ FSL_IMX7_UART7_ADDR = 0x30A90000,
165
+ FSL_IMX7_UART6_ADDR = 0x30A80000,
166
+ FSL_IMX7_UART5_ADDR = 0x30A70000,
167
+ FSL_IMX7_UART4_ADDR = 0x30A60000,
168
+
169
+ FSL_IMX7_I2C4_ADDR = 0x30A50000,
170
+ FSL_IMX7_I2C3_ADDR = 0x30A40000,
171
+ FSL_IMX7_I2C2_ADDR = 0x30A30000,
172
+ FSL_IMX7_I2C1_ADDR = 0x30A20000,
173
+
174
+ FSL_IMX7_CAN2_ADDR = 0x30A10000,
175
+ FSL_IMX7_CAN1_ADDR = 0x30A00000,
176
+ FSL_IMX7_CANn_SIZE = (4 * KiB),
177
+
178
+ FSL_IMX7_AIPS3_CONF_ADDR = 0x309F0000,
179
+ FSL_IMX7_AIPS3_CONF_SIZE = (64 * KiB),
180
181
FSL_IMX7_CAAM_ADDR = 0x30900000,
182
- FSL_IMX7_CAAM_SIZE = 0x40000,
183
+ FSL_IMX7_CAAM_SIZE = (256 * KiB),
184
185
- FSL_IMX7_CAN1_ADDR = 0x30A00000,
186
- FSL_IMX7_CAN2_ADDR = 0x30A10000,
187
- FSL_IMX7_CANn_SIZE = 0x10000,
188
+ FSL_IMX7_SPBA_ADDR = 0x308F0000,
189
+ FSL_IMX7_SPBA_SIZE = (4 * KiB),
190
191
- FSL_IMX7_I2C1_ADDR = 0x30A20000,
192
- FSL_IMX7_I2C2_ADDR = 0x30A30000,
193
- FSL_IMX7_I2C3_ADDR = 0x30A40000,
194
- FSL_IMX7_I2C4_ADDR = 0x30A50000,
195
+ FSL_IMX7_SAI3_ADDR = 0x308C0000,
196
+ FSL_IMX7_SAI2_ADDR = 0x308B0000,
197
+ FSL_IMX7_SAI1_ADDR = 0x308A0000,
198
+ FSL_IMX7_SAIn_SIZE = (4 * KiB),
199
200
- FSL_IMX7_ECSPI1_ADDR = 0x30820000,
201
- FSL_IMX7_ECSPI2_ADDR = 0x30830000,
202
- FSL_IMX7_ECSPI3_ADDR = 0x30840000,
203
- FSL_IMX7_ECSPI4_ADDR = 0x30630000,
204
-
205
- FSL_IMX7_LCDIF_ADDR = 0x30730000,
206
- FSL_IMX7_LCDIF_SIZE = 0x1000,
207
-
208
- FSL_IMX7_UART1_ADDR = 0x30860000,
209
+ FSL_IMX7_UART3_ADDR = 0x30880000,
210
/*
211
* Some versions of the reference manual claim that UART2 is @
212
* 0x30870000, but experiments with HW + DT files in upstream
213
@@ -XXX,XX +XXX,XX @@ enum FslIMX7MemoryMap {
214
* actually located @ 0x30890000
215
*/
216
FSL_IMX7_UART2_ADDR = 0x30890000,
217
- FSL_IMX7_UART3_ADDR = 0x30880000,
218
- FSL_IMX7_UART4_ADDR = 0x30A60000,
219
- FSL_IMX7_UART5_ADDR = 0x30A70000,
220
- FSL_IMX7_UART6_ADDR = 0x30A80000,
221
- FSL_IMX7_UART7_ADDR = 0x30A90000,
222
+ FSL_IMX7_UART1_ADDR = 0x30860000,
223
224
- FSL_IMX7_SAI1_ADDR = 0x308A0000,
225
- FSL_IMX7_SAI2_ADDR = 0x308B0000,
226
- FSL_IMX7_SAI3_ADDR = 0x308C0000,
227
- FSL_IMX7_SAIn_SIZE = 0x10000,
228
+ FSL_IMX7_ECSPI3_ADDR = 0x30840000,
229
+ FSL_IMX7_ECSPI2_ADDR = 0x30830000,
230
+ FSL_IMX7_ECSPI1_ADDR = 0x30820000,
231
+ FSL_IMX7_ECSPIn_SIZE = (4 * KiB),
232
233
- FSL_IMX7_ENET1_ADDR = 0x30BE0000,
234
- FSL_IMX7_ENET2_ADDR = 0x30BF0000,
235
+ /* AIPS-3 End */
236
237
- FSL_IMX7_USB1_ADDR = 0x30B10000,
238
- FSL_IMX7_USBMISC1_ADDR = 0x30B10200,
239
- FSL_IMX7_USB2_ADDR = 0x30B20000,
240
- FSL_IMX7_USBMISC2_ADDR = 0x30B20200,
241
- FSL_IMX7_USB3_ADDR = 0x30B30000,
242
- FSL_IMX7_USBMISC3_ADDR = 0x30B30200,
243
- FSL_IMX7_USBMISCn_SIZE = 0x200,
244
+ /* AIPS-2 Begin */
245
246
- FSL_IMX7_USDHC1_ADDR = 0x30B40000,
247
- FSL_IMX7_USDHC2_ADDR = 0x30B50000,
248
- FSL_IMX7_USDHC3_ADDR = 0x30B60000,
249
+ FSL_IMX7_AXI_DEBUG_MON_ADDR = 0x307E0000,
250
+ FSL_IMX7_AXI_DEBUG_MON_SIZE = (64 * KiB),
251
252
- FSL_IMX7_SDMA_ADDR = 0x30BD0000,
253
- FSL_IMX7_SDMA_SIZE = 0x1000,
254
+ FSL_IMX7_PERFMON2_ADDR = 0x307D0000,
255
+ FSL_IMX7_PERFMON1_ADDR = 0x307C0000,
256
+ FSL_IMX7_PERFMONn_SIZE = (64 * KiB),
257
+
258
+ FSL_IMX7_DDRC_ADDR = 0x307A0000,
259
+ FSL_IMX7_DDRC_SIZE = (4 * KiB),
260
+
261
+ FSL_IMX7_DDRC_PHY_ADDR = 0x30790000,
262
+ FSL_IMX7_DDRC_PHY_SIZE = (4 * KiB),
263
+
264
+ FSL_IMX7_TZASC_ADDR = 0x30780000,
265
+ FSL_IMX7_TZASC_SIZE = (64 * KiB),
266
+
267
+ FSL_IMX7_MIPI_DSI_ADDR = 0x30760000,
268
+ FSL_IMX7_MIPI_DSI_SIZE = (4 * KiB),
269
+
270
+ FSL_IMX7_MIPI_CSI_ADDR = 0x30750000,
271
+ FSL_IMX7_MIPI_CSI_SIZE = 0x4000,
272
+
273
+ FSL_IMX7_LCDIF_ADDR = 0x30730000,
274
+ FSL_IMX7_LCDIF_SIZE = 0x8000,
275
+
276
+ FSL_IMX7_CSI_ADDR = 0x30710000,
277
+ FSL_IMX7_CSI_SIZE = (4 * KiB),
278
+
279
+ FSL_IMX7_PXP_ADDR = 0x30700000,
280
+ FSL_IMX7_PXP_SIZE = 0x4000,
281
+
282
+ FSL_IMX7_EPDC_ADDR = 0x306F0000,
283
+ FSL_IMX7_EPDC_SIZE = (4 * KiB),
284
+
285
+ FSL_IMX7_PCIE_PHY_ADDR = 0x306D0000,
286
+ FSL_IMX7_PCIE_PHY_SIZE = (4 * KiB),
287
+
288
+ FSL_IMX7_SYSCNT_CTRL_ADDR = 0x306C0000,
289
+ FSL_IMX7_SYSCNT_CMP_ADDR = 0x306B0000,
290
+ FSL_IMX7_SYSCNT_RD_ADDR = 0x306A0000,
291
+
292
+ FSL_IMX7_PWM4_ADDR = 0x30690000,
293
+ FSL_IMX7_PWM3_ADDR = 0x30680000,
294
+ FSL_IMX7_PWM2_ADDR = 0x30670000,
295
+ FSL_IMX7_PWM1_ADDR = 0x30660000,
296
+ FSL_IMX7_PWMn_SIZE = (4 * KiB),
297
+
298
+ FSL_IMX7_FlEXTIMER2_ADDR = 0x30650000,
299
+ FSL_IMX7_FlEXTIMER1_ADDR = 0x30640000,
300
+ FSL_IMX7_FLEXTIMERn_SIZE = (4 * KiB),
301
+
302
+ FSL_IMX7_ECSPI4_ADDR = 0x30630000,
303
+
304
+ FSL_IMX7_ADC2_ADDR = 0x30620000,
305
+ FSL_IMX7_ADC1_ADDR = 0x30610000,
306
+ FSL_IMX7_ADCn_SIZE = (4 * KiB),
307
+
308
+ FSL_IMX7_AIPS2_CONF_ADDR = 0x305F0000,
309
+ FSL_IMX7_AIPS2_CONF_SIZE = (64 * KiB),
310
+
311
+ /* AIPS-2 End */
312
+
313
+ /* AIPS-1 Begin */
314
+
315
+ FSL_IMX7_CSU_ADDR = 0x303E0000,
316
+ FSL_IMX7_CSU_SIZE = (64 * KiB),
317
+
318
+ FSL_IMX7_RDC_ADDR = 0x303D0000,
319
+ FSL_IMX7_RDC_SIZE = (4 * KiB),
320
+
321
+ FSL_IMX7_SEMAPHORE2_ADDR = 0x303C0000,
322
+ FSL_IMX7_SEMAPHORE1_ADDR = 0x303B0000,
323
+ FSL_IMX7_SEMAPHOREn_SIZE = (4 * KiB),
324
+
325
+ FSL_IMX7_GPC_ADDR = 0x303A0000,
326
+
327
+ FSL_IMX7_SRC_ADDR = 0x30390000,
328
+ FSL_IMX7_SRC_SIZE = (4 * KiB),
329
+
330
+ FSL_IMX7_CCM_ADDR = 0x30380000,
331
+
332
+ FSL_IMX7_SNVS_HP_ADDR = 0x30370000,
333
+
334
+ FSL_IMX7_ANALOG_ADDR = 0x30360000,
335
+
336
+ FSL_IMX7_OCOTP_ADDR = 0x30350000,
337
+ FSL_IMX7_OCOTP_SIZE = 0x10000,
338
+
339
+ FSL_IMX7_IOMUXC_GPR_ADDR = 0x30340000,
340
+ FSL_IMX7_IOMUXC_GPR_SIZE = (4 * KiB),
341
+
342
+ FSL_IMX7_IOMUXC_ADDR = 0x30330000,
343
+ FSL_IMX7_IOMUXC_SIZE = (4 * KiB),
344
+
345
+ FSL_IMX7_KPP_ADDR = 0x30320000,
346
+ FSL_IMX7_KPP_SIZE = (4 * KiB),
347
+
348
+ FSL_IMX7_ROMCP_ADDR = 0x30310000,
349
+ FSL_IMX7_ROMCP_SIZE = (4 * KiB),
350
+
351
+ FSL_IMX7_GPT4_ADDR = 0x30300000,
352
+ FSL_IMX7_GPT3_ADDR = 0x302F0000,
353
+ FSL_IMX7_GPT2_ADDR = 0x302E0000,
354
+ FSL_IMX7_GPT1_ADDR = 0x302D0000,
355
+
356
+ FSL_IMX7_IOMUXC_LPSR_ADDR = 0x302C0000,
357
+ FSL_IMX7_IOMUXC_LPSR_SIZE = (4 * KiB),
358
+
359
+ FSL_IMX7_WDOG4_ADDR = 0x302B0000,
360
+ FSL_IMX7_WDOG3_ADDR = 0x302A0000,
361
+ FSL_IMX7_WDOG2_ADDR = 0x30290000,
362
+ FSL_IMX7_WDOG1_ADDR = 0x30280000,
363
+
364
+ FSL_IMX7_IOMUXC_LPSR_GPR_ADDR = 0x30270000,
365
+
366
+ FSL_IMX7_GPIO7_ADDR = 0x30260000,
367
+ FSL_IMX7_GPIO6_ADDR = 0x30250000,
368
+ FSL_IMX7_GPIO5_ADDR = 0x30240000,
369
+ FSL_IMX7_GPIO4_ADDR = 0x30230000,
370
+ FSL_IMX7_GPIO3_ADDR = 0x30220000,
371
+ FSL_IMX7_GPIO2_ADDR = 0x30210000,
372
+ FSL_IMX7_GPIO1_ADDR = 0x30200000,
373
+
374
+ FSL_IMX7_AIPS1_CONF_ADDR = 0x301F0000,
375
+ FSL_IMX7_AIPS1_CONF_SIZE = (64 * KiB),
376
377
- FSL_IMX7_A7MPCORE_ADDR = 0x31000000,
378
FSL_IMX7_A7MPCORE_DAP_ADDR = 0x30000000,
379
+ FSL_IMX7_A7MPCORE_DAP_SIZE = (1 * MiB),
380
381
- FSL_IMX7_PCIE_REG_ADDR = 0x33800000,
382
- FSL_IMX7_PCIE_REG_SIZE = 16 * 1024,
383
+ /* AIPS-1 End */
384
385
- FSL_IMX7_GPR_ADDR = 0x30340000,
386
+ FSL_IMX7_EIM_CS0_ADDR = 0x28000000,
387
+ FSL_IMX7_EIM_CS0_SIZE = (128 * MiB),
388
389
- FSL_IMX7_DMA_APBH_ADDR = 0x33000000,
390
- FSL_IMX7_DMA_APBH_SIZE = 0x2000,
391
+ FSL_IMX7_OCRAM_PXP_ADDR = 0x00940000,
392
+ FSL_IMX7_OCRAM_PXP_SIZE = (32 * KiB),
393
+
394
+ FSL_IMX7_OCRAM_EPDC_ADDR = 0x00920000,
395
+ FSL_IMX7_OCRAM_EPDC_SIZE = (128 * KiB),
396
+
397
+ FSL_IMX7_OCRAM_MEM_ADDR = 0x00900000,
398
+ FSL_IMX7_OCRAM_MEM_SIZE = (128 * KiB),
399
+
400
+ FSL_IMX7_TCMU_ADDR = 0x00800000,
401
+ FSL_IMX7_TCMU_SIZE = (32 * KiB),
402
+
403
+ FSL_IMX7_TCML_ADDR = 0x007F8000,
404
+ FSL_IMX7_TCML_SIZE = (32 * KiB),
405
+
406
+ FSL_IMX7_OCRAM_S_ADDR = 0x00180000,
407
+ FSL_IMX7_OCRAM_S_SIZE = (32 * KiB),
408
+
409
+ FSL_IMX7_CAAM_MEM_ADDR = 0x00100000,
410
+ FSL_IMX7_CAAM_MEM_SIZE = (32 * KiB),
411
+
412
+ FSL_IMX7_ROM_ADDR = 0x00000000,
413
+ FSL_IMX7_ROM_SIZE = (96 * KiB),
414
};
415
416
enum FslIMX7IRQs {
417
diff --git a/hw/arm/fsl-imx7.c b/hw/arm/fsl-imx7.c
418
index XXXXXXX..XXXXXXX 100644
419
--- a/hw/arm/fsl-imx7.c
420
+++ b/hw/arm/fsl-imx7.c
421
@@ -XXX,XX +XXX,XX @@ static void fsl_imx7_init(Object *obj)
422
char name[NAME_SIZE];
423
int i;
424
425
+ /*
426
+ * CPUs
427
+ */
428
for (i = 0; i < MIN(ms->smp.cpus, FSL_IMX7_NUM_CPUS); i++) {
429
snprintf(name, NAME_SIZE, "cpu%d", i);
430
object_initialize_child(obj, name, &s->cpu[i],
431
@@ -XXX,XX +XXX,XX @@ static void fsl_imx7_init(Object *obj)
432
TYPE_A15MPCORE_PRIV);
433
434
/*
435
- * GPIOs 1 to 7
436
+ * GPIOs
437
*/
438
for (i = 0; i < FSL_IMX7_NUM_GPIOS; i++) {
439
snprintf(name, NAME_SIZE, "gpio%d", i);
440
@@ -XXX,XX +XXX,XX @@ static void fsl_imx7_init(Object *obj)
441
}
442
443
/*
444
- * GPT1, 2, 3, 4
445
+ * GPTs
446
*/
447
for (i = 0; i < FSL_IMX7_NUM_GPTS; i++) {
448
snprintf(name, NAME_SIZE, "gpt%d", i);
449
@@ -XXX,XX +XXX,XX @@ static void fsl_imx7_init(Object *obj)
450
*/
451
object_initialize_child(obj, "gpcv2", &s->gpcv2, TYPE_IMX_GPCV2);
452
453
+ /*
454
+ * ECSPIs
455
+ */
456
for (i = 0; i < FSL_IMX7_NUM_ECSPIS; i++) {
457
snprintf(name, NAME_SIZE, "spi%d", i + 1);
458
object_initialize_child(obj, name, &s->spi[i], TYPE_IMX_SPI);
459
}
460
461
-
462
+ /*
463
+ * I2Cs
464
+ */
465
for (i = 0; i < FSL_IMX7_NUM_I2CS; i++) {
466
snprintf(name, NAME_SIZE, "i2c%d", i + 1);
467
object_initialize_child(obj, name, &s->i2c[i], TYPE_IMX_I2C);
468
}
469
470
/*
471
- * UART
472
+ * UARTs
473
*/
474
for (i = 0; i < FSL_IMX7_NUM_UARTS; i++) {
475
snprintf(name, NAME_SIZE, "uart%d", i);
476
@@ -XXX,XX +XXX,XX @@ static void fsl_imx7_init(Object *obj)
477
}
478
479
/*
480
- * Ethernet
481
+ * Ethernets
482
*/
483
for (i = 0; i < FSL_IMX7_NUM_ETHS; i++) {
484
snprintf(name, NAME_SIZE, "eth%d", i);
485
@@ -XXX,XX +XXX,XX @@ static void fsl_imx7_init(Object *obj)
486
}
487
488
/*
489
- * SDHCI
490
+ * SDHCIs
491
*/
492
for (i = 0; i < FSL_IMX7_NUM_USDHCS; i++) {
493
snprintf(name, NAME_SIZE, "usdhc%d", i);
494
@@ -XXX,XX +XXX,XX @@ static void fsl_imx7_init(Object *obj)
495
object_initialize_child(obj, "snvs", &s->snvs, TYPE_IMX7_SNVS);
496
497
/*
498
- * Watchdog
499
+ * Watchdogs
500
*/
501
for (i = 0; i < FSL_IMX7_NUM_WDTS; i++) {
502
snprintf(name, NAME_SIZE, "wdt%d", i);
503
@@ -XXX,XX +XXX,XX @@ static void fsl_imx7_init(Object *obj)
504
*/
505
object_initialize_child(obj, "gpr", &s->gpr, TYPE_IMX7_GPR);
506
507
+ /*
508
+ * PCIE
509
+ */
510
object_initialize_child(obj, "pcie", &s->pcie, TYPE_DESIGNWARE_PCIE_HOST);
511
512
+ /*
513
+ * USBs
514
+ */
515
for (i = 0; i < FSL_IMX7_NUM_USBS; i++) {
516
snprintf(name, NAME_SIZE, "usb%d", i);
517
object_initialize_child(obj, name, &s->usb[i], TYPE_CHIPIDEA);
518
@@ -XXX,XX +XXX,XX @@ static void fsl_imx7_realize(DeviceState *dev, Error **errp)
519
return;
520
}
521
522
+ /*
523
+ * CPUs
524
+ */
525
for (i = 0; i < smp_cpus; i++) {
526
o = OBJECT(&s->cpu[i]);
527
528
@@ -XXX,XX +XXX,XX @@ static void fsl_imx7_realize(DeviceState *dev, Error **errp)
529
* A7MPCORE DAP
530
*/
531
create_unimplemented_device("a7mpcore-dap", FSL_IMX7_A7MPCORE_DAP_ADDR,
532
- 0x100000);
533
+ FSL_IMX7_A7MPCORE_DAP_SIZE);
534
535
/*
536
- * GPT1, 2, 3, 4
537
+ * GPTs
538
*/
539
for (i = 0; i < FSL_IMX7_NUM_GPTS; i++) {
540
static const hwaddr FSL_IMX7_GPTn_ADDR[FSL_IMX7_NUM_GPTS] = {
541
@@ -XXX,XX +XXX,XX @@ static void fsl_imx7_realize(DeviceState *dev, Error **errp)
542
FSL_IMX7_GPTn_IRQ[i]));
543
}
544
545
+ /*
546
+ * GPIOs
547
+ */
548
for (i = 0; i < FSL_IMX7_NUM_GPIOS; i++) {
549
static const hwaddr FSL_IMX7_GPIOn_ADDR[FSL_IMX7_NUM_GPIOS] = {
550
FSL_IMX7_GPIO1_ADDR,
551
@@ -XXX,XX +XXX,XX @@ static void fsl_imx7_realize(DeviceState *dev, Error **errp)
552
/*
553
* IOMUXC and IOMUXC_LPSR
554
*/
555
- for (i = 0; i < FSL_IMX7_NUM_IOMUXCS; i++) {
556
- static const hwaddr FSL_IMX7_IOMUXCn_ADDR[FSL_IMX7_NUM_IOMUXCS] = {
557
- FSL_IMX7_IOMUXC_ADDR,
558
- FSL_IMX7_IOMUXC_LPSR_ADDR,
559
- };
560
-
561
- snprintf(name, NAME_SIZE, "iomuxc%d", i);
562
- create_unimplemented_device(name, FSL_IMX7_IOMUXCn_ADDR[i],
563
- FSL_IMX7_IOMUXCn_SIZE);
564
- }
565
+ create_unimplemented_device("iomuxc", FSL_IMX7_IOMUXC_ADDR,
566
+ FSL_IMX7_IOMUXC_SIZE);
567
+ create_unimplemented_device("iomuxc_lspr", FSL_IMX7_IOMUXC_LPSR_ADDR,
568
+ FSL_IMX7_IOMUXC_LPSR_SIZE);
569
570
/*
571
* CCM
572
@@ -XXX,XX +XXX,XX @@ static void fsl_imx7_realize(DeviceState *dev, Error **errp)
573
sysbus_realize(SYS_BUS_DEVICE(&s->gpcv2), &error_abort);
574
sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpcv2), 0, FSL_IMX7_GPC_ADDR);
575
576
- /* Initialize all ECSPI */
577
+ /*
578
+ * ECSPIs
579
+ */
580
for (i = 0; i < FSL_IMX7_NUM_ECSPIS; i++) {
581
static const hwaddr FSL_IMX7_SPIn_ADDR[FSL_IMX7_NUM_ECSPIS] = {
582
FSL_IMX7_ECSPI1_ADDR,
583
@@ -XXX,XX +XXX,XX @@ static void fsl_imx7_realize(DeviceState *dev, Error **errp)
584
FSL_IMX7_SPIn_IRQ[i]));
585
}
586
587
+ /*
588
+ * I2Cs
589
+ */
590
for (i = 0; i < FSL_IMX7_NUM_I2CS; i++) {
591
static const hwaddr FSL_IMX7_I2Cn_ADDR[FSL_IMX7_NUM_I2CS] = {
592
FSL_IMX7_I2C1_ADDR,
593
@@ -XXX,XX +XXX,XX @@ static void fsl_imx7_realize(DeviceState *dev, Error **errp)
594
}
595
596
/*
597
- * UART
598
+ * UARTs
599
*/
600
for (i = 0; i < FSL_IMX7_NUM_UARTS; i++) {
601
static const hwaddr FSL_IMX7_UARTn_ADDR[FSL_IMX7_NUM_UARTS] = {
602
@@ -XXX,XX +XXX,XX @@ static void fsl_imx7_realize(DeviceState *dev, Error **errp)
603
}
604
605
/*
606
- * Ethernet
607
+ * Ethernets
608
*
609
* We must use two loops since phy_connected affects the other interface
610
* and we have to set all properties before calling sysbus_realize().
611
@@ -XXX,XX +XXX,XX @@ static void fsl_imx7_realize(DeviceState *dev, Error **errp)
612
}
613
614
/*
615
- * USDHC
616
+ * USDHCs
617
*/
618
for (i = 0; i < FSL_IMX7_NUM_USDHCS; i++) {
619
static const hwaddr FSL_IMX7_USDHCn_ADDR[FSL_IMX7_NUM_USDHCS] = {
620
@@ -XXX,XX +XXX,XX @@ static void fsl_imx7_realize(DeviceState *dev, Error **errp)
621
* SNVS
622
*/
623
sysbus_realize(SYS_BUS_DEVICE(&s->snvs), &error_abort);
624
- sysbus_mmio_map(SYS_BUS_DEVICE(&s->snvs), 0, FSL_IMX7_SNVS_ADDR);
625
+ sysbus_mmio_map(SYS_BUS_DEVICE(&s->snvs), 0, FSL_IMX7_SNVS_HP_ADDR);
626
627
/*
628
* SRC
629
@@ -XXX,XX +XXX,XX @@ static void fsl_imx7_realize(DeviceState *dev, Error **errp)
630
create_unimplemented_device("src", FSL_IMX7_SRC_ADDR, FSL_IMX7_SRC_SIZE);
631
632
/*
633
- * Watchdog
634
+ * Watchdogs
635
*/
636
for (i = 0; i < FSL_IMX7_NUM_WDTS; i++) {
637
static const hwaddr FSL_IMX7_WDOGn_ADDR[FSL_IMX7_NUM_WDTS] = {
638
@@ -XXX,XX +XXX,XX @@ static void fsl_imx7_realize(DeviceState *dev, Error **errp)
639
create_unimplemented_device("caam", FSL_IMX7_CAAM_ADDR, FSL_IMX7_CAAM_SIZE);
640
641
/*
642
- * PWM
643
+ * PWMs
644
*/
645
- create_unimplemented_device("pwm1", FSL_IMX7_PWM1_ADDR, FSL_IMX7_PWMn_SIZE);
646
- create_unimplemented_device("pwm2", FSL_IMX7_PWM2_ADDR, FSL_IMX7_PWMn_SIZE);
647
- create_unimplemented_device("pwm3", FSL_IMX7_PWM3_ADDR, FSL_IMX7_PWMn_SIZE);
648
- create_unimplemented_device("pwm4", FSL_IMX7_PWM4_ADDR, FSL_IMX7_PWMn_SIZE);
649
+ for (i = 0; i < FSL_IMX7_NUM_PWMS; i++) {
650
+ static const hwaddr FSL_IMX7_PWMn_ADDR[FSL_IMX7_NUM_PWMS] = {
651
+ FSL_IMX7_PWM1_ADDR,
652
+ FSL_IMX7_PWM2_ADDR,
653
+ FSL_IMX7_PWM3_ADDR,
654
+ FSL_IMX7_PWM4_ADDR,
655
+ };
656
+
657
+ snprintf(name, NAME_SIZE, "pwm%d", i);
658
+ create_unimplemented_device(name, FSL_IMX7_PWMn_ADDR[i],
659
+ FSL_IMX7_PWMn_SIZE);
660
+ }
661
662
/*
663
- * CAN
664
+ * CANs
665
*/
666
- create_unimplemented_device("can1", FSL_IMX7_CAN1_ADDR, FSL_IMX7_CANn_SIZE);
667
- create_unimplemented_device("can2", FSL_IMX7_CAN2_ADDR, FSL_IMX7_CANn_SIZE);
668
+ for (i = 0; i < FSL_IMX7_NUM_CANS; i++) {
669
+ static const hwaddr FSL_IMX7_CANn_ADDR[FSL_IMX7_NUM_CANS] = {
670
+ FSL_IMX7_CAN1_ADDR,
671
+ FSL_IMX7_CAN2_ADDR,
672
+ };
673
+
674
+ snprintf(name, NAME_SIZE, "can%d", i);
675
+ create_unimplemented_device(name, FSL_IMX7_CANn_ADDR[i],
676
+ FSL_IMX7_CANn_SIZE);
677
+ }
678
679
/*
680
- * SAI (Audio SSI (Synchronous Serial Interface))
681
+ * SAIs (Audio SSI (Synchronous Serial Interface))
682
*/
683
- create_unimplemented_device("sai1", FSL_IMX7_SAI1_ADDR, FSL_IMX7_SAIn_SIZE);
684
- create_unimplemented_device("sai2", FSL_IMX7_SAI2_ADDR, FSL_IMX7_SAIn_SIZE);
685
- create_unimplemented_device("sai2", FSL_IMX7_SAI3_ADDR, FSL_IMX7_SAIn_SIZE);
686
+ for (i = 0; i < FSL_IMX7_NUM_SAIS; i++) {
687
+ static const hwaddr FSL_IMX7_SAIn_ADDR[FSL_IMX7_NUM_SAIS] = {
688
+ FSL_IMX7_SAI1_ADDR,
689
+ FSL_IMX7_SAI2_ADDR,
690
+ FSL_IMX7_SAI3_ADDR,
691
+ };
692
+
693
+ snprintf(name, NAME_SIZE, "sai%d", i);
694
+ create_unimplemented_device(name, FSL_IMX7_SAIn_ADDR[i],
695
+ FSL_IMX7_SAIn_SIZE);
696
+ }
697
698
/*
699
* OCOTP
700
@@ -XXX,XX +XXX,XX @@ static void fsl_imx7_realize(DeviceState *dev, Error **errp)
701
create_unimplemented_device("ocotp", FSL_IMX7_OCOTP_ADDR,
702
FSL_IMX7_OCOTP_SIZE);
703
704
+ /*
705
+ * GPR
706
+ */
707
sysbus_realize(SYS_BUS_DEVICE(&s->gpr), &error_abort);
708
- sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpr), 0, FSL_IMX7_GPR_ADDR);
709
+ sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpr), 0, FSL_IMX7_IOMUXC_GPR_ADDR);
710
711
+ /*
712
+ * PCIE
713
+ */
714
sysbus_realize(SYS_BUS_DEVICE(&s->pcie), &error_abort);
715
sysbus_mmio_map(SYS_BUS_DEVICE(&s->pcie), 0, FSL_IMX7_PCIE_REG_ADDR);
716
717
@@ -XXX,XX +XXX,XX @@ static void fsl_imx7_realize(DeviceState *dev, Error **errp)
718
irq = qdev_get_gpio_in(DEVICE(&s->a7mpcore), FSL_IMX7_PCI_INTD_IRQ);
719
sysbus_connect_irq(SYS_BUS_DEVICE(&s->pcie), 3, irq);
720
721
-
722
+ /*
723
+ * USBs
724
+ */
725
for (i = 0; i < FSL_IMX7_NUM_USBS; i++) {
726
static const hwaddr FSL_IMX7_USBMISCn_ADDR[FSL_IMX7_NUM_USBS] = {
727
FSL_IMX7_USBMISC1_ADDR,
728
@@ -XXX,XX +XXX,XX @@ static void fsl_imx7_realize(DeviceState *dev, Error **errp)
729
*/
730
create_unimplemented_device("pcie-phy", FSL_IMX7_PCIE_PHY_ADDR,
731
FSL_IMX7_PCIE_PHY_SIZE);
732
+
733
}
734
735
static Property fsl_imx7_properties[] = {
30
--
736
--
31
2.25.1
737
2.34.1
diff view generated by jsdifflib
[PULL 06/10] hw/arm/virt: Fix devicetree warning about the root node
[PULL 15/24] Add i.MX7 missing TZ devices and memory regions
1
From: Jean-Philippe Brucker <jean-philippe@linaro.org>
1
From: Jean-Christophe Dubois <jcd@tribudubois.net>
2
2
3
The devicetree specification requires a 'model' property in the root
3
* Add TZASC as unimplemented device.
4
node. Fix the corresponding dt-validate warning:
4
- Allow bare metal application to access this (unimplemented) device
5
* Add CSU as unimplemented device.
6
- Allow bare metal application to access this (unimplemented) device
7
* Add various memory segments
8
- OCRAM
9
- OCRAM EPDC
10
- OCRAM PXP
11
- OCRAM S
12
- ROM
13
- CAAM
5
14
6
/: 'model' is a required property
15
Signed-off-by: Jean-Christophe Dubois <jcd@tribudubois.net>
7
From schema: dtschema/schemas/root-node.yaml
16
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
8
17
Message-id: f887a3483996ba06d40bd62ffdfb0ecf68621987.1692964892.git.jcd@tribudubois.net
9
Use the same name for model as for compatible. The specification
10
recommends that 'compatible' follows the format 'manufacturer,model' and
11
'model' follows the format 'manufacturer,model-number'. Since our
12
'compatible' doesn't observe this, 'model' doesn't really need to
13
either.
14
15
Signed-off-by: Jean-Philippe Brucker <jean-philippe@linaro.org>
16
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
17
Reviewed-by: Eric Auger <eric.auger@redhat.com>
18
Message-id: 20220927100347.176606-2-jean-philippe@linaro.org
19
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
18
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
20
---
19
---
21
hw/arm/virt.c | 1 +
20
include/hw/arm/fsl-imx7.h | 7 +++++
22
1 file changed, 1 insertion(+)
21
hw/arm/fsl-imx7.c | 63 +++++++++++++++++++++++++++++++++++++++
22
2 files changed, 70 insertions(+)
23
23
24
diff --git a/hw/arm/virt.c b/hw/arm/virt.c
24
diff --git a/include/hw/arm/fsl-imx7.h b/include/hw/arm/fsl-imx7.h
25
index XXXXXXX..XXXXXXX 100644
25
index XXXXXXX..XXXXXXX 100644
26
--- a/hw/arm/virt.c
26
--- a/include/hw/arm/fsl-imx7.h
27
+++ b/hw/arm/virt.c
27
+++ b/include/hw/arm/fsl-imx7.h
28
@@ -XXX,XX +XXX,XX @@ static void create_fdt(VirtMachineState *vms)
28
@@ -XXX,XX +XXX,XX @@ struct FslIMX7State {
29
qemu_fdt_setprop_string(fdt, "/", "compatible", "linux,dummy-virt");
29
IMX7GPRState gpr;
30
qemu_fdt_setprop_cell(fdt, "/", "#address-cells", 0x2);
30
ChipideaState usb[FSL_IMX7_NUM_USBS];
31
qemu_fdt_setprop_cell(fdt, "/", "#size-cells", 0x2);
31
DesignwarePCIEHost pcie;
32
+ qemu_fdt_setprop_string(fdt, "/", "model", "linux,dummy-virt");
32
+ MemoryRegion rom;
33
33
+ MemoryRegion caam;
34
/* /chosen must exist for load_dtb to fill in necessary properties later */
34
+ MemoryRegion ocram;
35
qemu_fdt_add_subnode(fdt, "/chosen");
35
+ MemoryRegion ocram_epdc;
36
+ MemoryRegion ocram_pxp;
37
+ MemoryRegion ocram_s;
38
+
39
uint32_t phy_num[FSL_IMX7_NUM_ETHS];
40
bool phy_connected[FSL_IMX7_NUM_ETHS];
41
};
42
diff --git a/hw/arm/fsl-imx7.c b/hw/arm/fsl-imx7.c
43
index XXXXXXX..XXXXXXX 100644
44
--- a/hw/arm/fsl-imx7.c
45
+++ b/hw/arm/fsl-imx7.c
46
@@ -XXX,XX +XXX,XX @@ static void fsl_imx7_realize(DeviceState *dev, Error **errp)
47
create_unimplemented_device("pcie-phy", FSL_IMX7_PCIE_PHY_ADDR,
48
FSL_IMX7_PCIE_PHY_SIZE);
49
50
+ /*
51
+ * CSU
52
+ */
53
+ create_unimplemented_device("csu", FSL_IMX7_CSU_ADDR,
54
+ FSL_IMX7_CSU_SIZE);
55
+
56
+ /*
57
+ * TZASC
58
+ */
59
+ create_unimplemented_device("tzasc", FSL_IMX7_TZASC_ADDR,
60
+ FSL_IMX7_TZASC_SIZE);
61
+
62
+ /*
63
+ * OCRAM memory
64
+ */
65
+ memory_region_init_ram(&s->ocram, NULL, "imx7.ocram",
66
+ FSL_IMX7_OCRAM_MEM_SIZE,
67
+ &error_abort);
68
+ memory_region_add_subregion(get_system_memory(), FSL_IMX7_OCRAM_MEM_ADDR,
69
+ &s->ocram);
70
+
71
+ /*
72
+ * OCRAM EPDC memory
73
+ */
74
+ memory_region_init_ram(&s->ocram_epdc, NULL, "imx7.ocram_epdc",
75
+ FSL_IMX7_OCRAM_EPDC_SIZE,
76
+ &error_abort);
77
+ memory_region_add_subregion(get_system_memory(), FSL_IMX7_OCRAM_EPDC_ADDR,
78
+ &s->ocram_epdc);
79
+
80
+ /*
81
+ * OCRAM PXP memory
82
+ */
83
+ memory_region_init_ram(&s->ocram_pxp, NULL, "imx7.ocram_pxp",
84
+ FSL_IMX7_OCRAM_PXP_SIZE,
85
+ &error_abort);
86
+ memory_region_add_subregion(get_system_memory(), FSL_IMX7_OCRAM_PXP_ADDR,
87
+ &s->ocram_pxp);
88
+
89
+ /*
90
+ * OCRAM_S memory
91
+ */
92
+ memory_region_init_ram(&s->ocram_s, NULL, "imx7.ocram_s",
93
+ FSL_IMX7_OCRAM_S_SIZE,
94
+ &error_abort);
95
+ memory_region_add_subregion(get_system_memory(), FSL_IMX7_OCRAM_S_ADDR,
96
+ &s->ocram_s);
97
+
98
+ /*
99
+ * ROM memory
100
+ */
101
+ memory_region_init_rom(&s->rom, OBJECT(dev), "imx7.rom",
102
+ FSL_IMX7_ROM_SIZE, &error_abort);
103
+ memory_region_add_subregion(get_system_memory(), FSL_IMX7_ROM_ADDR,
104
+ &s->rom);
105
+
106
+ /*
107
+ * CAAM memory
108
+ */
109
+ memory_region_init_rom(&s->caam, OBJECT(dev), "imx7.caam",
110
+ FSL_IMX7_CAAM_MEM_SIZE, &error_abort);
111
+ memory_region_add_subregion(get_system_memory(), FSL_IMX7_CAAM_MEM_ADDR,
112
+ &s->caam);
113
}
114
115
static Property fsl_imx7_properties[] = {
36
--
116
--
37
2.25.1
117
2.34.1
118
119
diff view generated by jsdifflib
[PULL 05/10] hw/arm/xlnx-zynqmp: Connect ZynqMP's USB controllers
[PULL 16/24] Add i.MX7 SRC device implementation
1
From: Francisco Iglesias <francisco.iglesias@amd.com>
1
From: Jean-Christophe Dubois <jcd@tribudubois.net>
2
2
3
Connect ZynqMP's USB controllers.
3
The SRC device is normally used to start the secondary CPU.
4
4
5
Signed-off-by: Francisco Iglesias <francisco.iglesias@amd.com>
5
When running Linux directly, QEMU is emulating a PSCI interface that UBOOT
6
Acked-by: Alistair Francis <alistair.francis@wdc.com>
6
is installing at boot time and therefore the fact that the SRC device is
7
Message-id: 20220920081517.25401-1-frasse.iglesias@gmail.com
7
unimplemented is hidden as Qemu respond directly to PSCI requets without
8
using the SRC device.
9
10
But if you try to run a more bare metal application (maybe uboot itself),
11
then it is not possible to start the secondary CPU as the SRC is an
12
unimplemented device.
13
14
This patch adds the ability to start the secondary CPU through the SRC
15
device so that you can use this feature in bare metal applications.
16
17
Signed-off-by: Jean-Christophe Dubois <jcd@tribudubois.net>
8
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
18
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
19
Message-id: ce9a0162defd2acee5dc7f8a674743de0cded569.1692964892.git.jcd@tribudubois.net
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
20
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
---
21
---
11
include/hw/arm/xlnx-zynqmp.h | 3 +++
22
include/hw/arm/fsl-imx7.h | 3 +-
12
hw/arm/xlnx-zynqmp.c | 36 ++++++++++++++++++++++++++++++++++++
23
include/hw/misc/imx7_src.h | 66 +++++++++
13
2 files changed, 39 insertions(+)
24
hw/arm/fsl-imx7.c | 8 +-
14
25
hw/misc/imx7_src.c | 276 +++++++++++++++++++++++++++++++++++++
15
diff --git a/include/hw/arm/xlnx-zynqmp.h b/include/hw/arm/xlnx-zynqmp.h
26
hw/misc/meson.build | 1 +
27
hw/misc/trace-events | 4 +
28
6 files changed, 356 insertions(+), 2 deletions(-)
29
create mode 100644 include/hw/misc/imx7_src.h
30
create mode 100644 hw/misc/imx7_src.c
31
32
diff --git a/include/hw/arm/fsl-imx7.h b/include/hw/arm/fsl-imx7.h
16
index XXXXXXX..XXXXXXX 100644
33
index XXXXXXX..XXXXXXX 100644
17
--- a/include/hw/arm/xlnx-zynqmp.h
34
--- a/include/hw/arm/fsl-imx7.h
18
+++ b/include/hw/arm/xlnx-zynqmp.h
35
+++ b/include/hw/arm/fsl-imx7.h
19
@@ -XXX,XX +XXX,XX @@
36
@@ -XXX,XX +XXX,XX @@
20
#include "hw/misc/xlnx-zynqmp-apu-ctrl.h"
37
#include "hw/misc/imx7_ccm.h"
21
#include "hw/misc/xlnx-zynqmp-crf.h"
38
#include "hw/misc/imx7_snvs.h"
22
#include "hw/timer/cadence_ttc.h"
39
#include "hw/misc/imx7_gpr.h"
23
+#include "hw/usb/hcd-dwc3.h"
40
+#include "hw/misc/imx7_src.h"
24
41
#include "hw/watchdog/wdt_imx2.h"
25
#define TYPE_XLNX_ZYNQMP "xlnx-zynqmp"
42
#include "hw/gpio/imx_gpio.h"
26
OBJECT_DECLARE_SIMPLE_TYPE(XlnxZynqMPState, XLNX_ZYNQMP)
43
#include "hw/char/imx_serial.h"
27
@@ -XXX,XX +XXX,XX @@ OBJECT_DECLARE_SIMPLE_TYPE(XlnxZynqMPState, XLNX_ZYNQMP)
44
@@ -XXX,XX +XXX,XX @@ struct FslIMX7State {
28
#define XLNX_ZYNQMP_NUM_SPIS 2
45
IMX7CCMState ccm;
29
#define XLNX_ZYNQMP_NUM_GDMA_CH 8
46
IMX7AnalogState analog;
30
#define XLNX_ZYNQMP_NUM_ADMA_CH 8
47
IMX7SNVSState snvs;
31
+#define XLNX_ZYNQMP_NUM_USB 2
48
+ IMX7SRCState src;
32
49
IMXGPCv2State gpcv2;
33
#define XLNX_ZYNQMP_NUM_QSPI_BUS 2
50
IMXSPIState spi[FSL_IMX7_NUM_ECSPIS];
34
#define XLNX_ZYNQMP_NUM_QSPI_BUS_CS 2
51
IMXI2CState i2c[FSL_IMX7_NUM_I2CS];
35
@@ -XXX,XX +XXX,XX @@ struct XlnxZynqMPState {
52
@@ -XXX,XX +XXX,XX @@ enum FslIMX7MemoryMap {
36
XlnxZynqMPAPUCtrl apu_ctrl;
53
FSL_IMX7_GPC_ADDR = 0x303A0000,
37
XlnxZynqMPCRF crf;
54
38
CadenceTTCState ttc[XLNX_ZYNQMP_NUM_TTC];
55
FSL_IMX7_SRC_ADDR = 0x30390000,
39
+ USBDWC3 usb[XLNX_ZYNQMP_NUM_USB];
56
- FSL_IMX7_SRC_SIZE = (4 * KiB),
40
57
41
char *boot_cpu;
58
FSL_IMX7_CCM_ADDR = 0x30380000,
42
ARMCPU *boot_cpu_ptr;
59
43
diff --git a/hw/arm/xlnx-zynqmp.c b/hw/arm/xlnx-zynqmp.c
60
diff --git a/include/hw/misc/imx7_src.h b/include/hw/misc/imx7_src.h
61
new file mode 100644
62
index XXXXXXX..XXXXXXX
63
--- /dev/null
64
+++ b/include/hw/misc/imx7_src.h
65
@@ -XXX,XX +XXX,XX @@
66
+/*
67
+ * IMX7 System Reset Controller
68
+ *
69
+ * Copyright (C) 2023 Jean-Christophe Dubois <jcd@tribudubois.net>
70
+ *
71
+ * This work is licensed under the terms of the GNU GPL, version 2 or later.
72
+ * See the COPYING file in the top-level directory.
73
+ */
74
+
75
+#ifndef IMX7_SRC_H
76
+#define IMX7_SRC_H
77
+
78
+#include "hw/sysbus.h"
79
+#include "qemu/bitops.h"
80
+#include "qom/object.h"
81
+
82
+#define SRC_SCR 0
83
+#define SRC_A7RCR0 1
84
+#define SRC_A7RCR1 2
85
+#define SRC_M4RCR 3
86
+#define SRC_ERCR 5
87
+#define SRC_HSICPHY_RCR 7
88
+#define SRC_USBOPHY1_RCR 8
89
+#define SRC_USBOPHY2_RCR 9
90
+#define SRC_MPIPHY_RCR 10
91
+#define SRC_PCIEPHY_RCR 11
92
+#define SRC_SBMR1 22
93
+#define SRC_SRSR 23
94
+#define SRC_SISR 26
95
+#define SRC_SIMR 27
96
+#define SRC_SBMR2 28
97
+#define SRC_GPR1 29
98
+#define SRC_GPR2 30
99
+#define SRC_GPR3 31
100
+#define SRC_GPR4 32
101
+#define SRC_GPR5 33
102
+#define SRC_GPR6 34
103
+#define SRC_GPR7 35
104
+#define SRC_GPR8 36
105
+#define SRC_GPR9 37
106
+#define SRC_GPR10 38
107
+#define SRC_MAX 39
108
+
109
+/* SRC_A7SCR1 */
110
+#define R_CORE1_ENABLE_SHIFT 1
111
+#define R_CORE1_ENABLE_LENGTH 1
112
+/* SRC_A7SCR0 */
113
+#define R_CORE1_RST_SHIFT 5
114
+#define R_CORE1_RST_LENGTH 1
115
+#define R_CORE0_RST_SHIFT 4
116
+#define R_CORE0_RST_LENGTH 1
117
+
118
+#define TYPE_IMX7_SRC "imx7.src"
119
+OBJECT_DECLARE_SIMPLE_TYPE(IMX7SRCState, IMX7_SRC)
120
+
121
+struct IMX7SRCState {
122
+ /* <private> */
123
+ SysBusDevice parent_obj;
124
+
125
+ /* <public> */
126
+ MemoryRegion iomem;
127
+
128
+ uint32_t regs[SRC_MAX];
129
+};
130
+
131
+#endif /* IMX7_SRC_H */
132
diff --git a/hw/arm/fsl-imx7.c b/hw/arm/fsl-imx7.c
44
index XXXXXXX..XXXXXXX 100644
133
index XXXXXXX..XXXXXXX 100644
45
--- a/hw/arm/xlnx-zynqmp.c
134
--- a/hw/arm/fsl-imx7.c
46
+++ b/hw/arm/xlnx-zynqmp.c
135
+++ b/hw/arm/fsl-imx7.c
47
@@ -XXX,XX +XXX,XX @@ static const int adma_ch_intr[XLNX_ZYNQMP_NUM_ADMA_CH] = {
136
@@ -XXX,XX +XXX,XX @@ static void fsl_imx7_init(Object *obj)
48
77, 78, 79, 80, 81, 82, 83, 84
137
*/
49
};
138
object_initialize_child(obj, "gpcv2", &s->gpcv2, TYPE_IMX_GPCV2);
50
139
51
+static const uint64_t usb_addr[XLNX_ZYNQMP_NUM_USB] = {
140
+ /*
52
+ 0xFE200000, 0xFE300000
141
+ * SRC
142
+ */
143
+ object_initialize_child(obj, "src", &s->src, TYPE_IMX7_SRC);
144
+
145
/*
146
* ECSPIs
147
*/
148
@@ -XXX,XX +XXX,XX @@ static void fsl_imx7_realize(DeviceState *dev, Error **errp)
149
/*
150
* SRC
151
*/
152
- create_unimplemented_device("src", FSL_IMX7_SRC_ADDR, FSL_IMX7_SRC_SIZE);
153
+ sysbus_realize(SYS_BUS_DEVICE(&s->src), &error_abort);
154
+ sysbus_mmio_map(SYS_BUS_DEVICE(&s->src), 0, FSL_IMX7_SRC_ADDR);
155
156
/*
157
* Watchdogs
158
diff --git a/hw/misc/imx7_src.c b/hw/misc/imx7_src.c
159
new file mode 100644
160
index XXXXXXX..XXXXXXX
161
--- /dev/null
162
+++ b/hw/misc/imx7_src.c
163
@@ -XXX,XX +XXX,XX @@
164
+/*
165
+ * IMX7 System Reset Controller
166
+ *
167
+ * Copyright (c) 2023 Jean-Christophe Dubois <jcd@tribudubois.net>
168
+ *
169
+ * This work is licensed under the terms of the GNU GPL, version 2 or later.
170
+ * See the COPYING file in the top-level directory.
171
+ *
172
+ */
173
+
174
+#include "qemu/osdep.h"
175
+#include "hw/misc/imx7_src.h"
176
+#include "migration/vmstate.h"
177
+#include "qemu/bitops.h"
178
+#include "qemu/log.h"
179
+#include "qemu/main-loop.h"
180
+#include "qemu/module.h"
181
+#include "target/arm/arm-powerctl.h"
182
+#include "hw/core/cpu.h"
183
+#include "hw/registerfields.h"
184
+
185
+#include "trace.h"
186
+
187
+static const char *imx7_src_reg_name(uint32_t reg)
188
+{
189
+ static char unknown[20];
190
+
191
+ switch (reg) {
192
+ case SRC_SCR:
193
+ return "SRC_SCR";
194
+ case SRC_A7RCR0:
195
+ return "SRC_A7RCR0";
196
+ case SRC_A7RCR1:
197
+ return "SRC_A7RCR1";
198
+ case SRC_M4RCR:
199
+ return "SRC_M4RCR";
200
+ case SRC_ERCR:
201
+ return "SRC_ERCR";
202
+ case SRC_HSICPHY_RCR:
203
+ return "SRC_HSICPHY_RCR";
204
+ case SRC_USBOPHY1_RCR:
205
+ return "SRC_USBOPHY1_RCR";
206
+ case SRC_USBOPHY2_RCR:
207
+ return "SRC_USBOPHY2_RCR";
208
+ case SRC_PCIEPHY_RCR:
209
+ return "SRC_PCIEPHY_RCR";
210
+ case SRC_SBMR1:
211
+ return "SRC_SBMR1";
212
+ case SRC_SRSR:
213
+ return "SRC_SRSR";
214
+ case SRC_SISR:
215
+ return "SRC_SISR";
216
+ case SRC_SIMR:
217
+ return "SRC_SIMR";
218
+ case SRC_SBMR2:
219
+ return "SRC_SBMR2";
220
+ case SRC_GPR1:
221
+ return "SRC_GPR1";
222
+ case SRC_GPR2:
223
+ return "SRC_GPR2";
224
+ case SRC_GPR3:
225
+ return "SRC_GPR3";
226
+ case SRC_GPR4:
227
+ return "SRC_GPR4";
228
+ case SRC_GPR5:
229
+ return "SRC_GPR5";
230
+ case SRC_GPR6:
231
+ return "SRC_GPR6";
232
+ case SRC_GPR7:
233
+ return "SRC_GPR7";
234
+ case SRC_GPR8:
235
+ return "SRC_GPR8";
236
+ case SRC_GPR9:
237
+ return "SRC_GPR9";
238
+ case SRC_GPR10:
239
+ return "SRC_GPR10";
240
+ default:
241
+ sprintf(unknown, "%u ?", reg);
242
+ return unknown;
243
+ }
244
+}
245
+
246
+static const VMStateDescription vmstate_imx7_src = {
247
+ .name = TYPE_IMX7_SRC,
248
+ .version_id = 1,
249
+ .minimum_version_id = 1,
250
+ .fields = (VMStateField[]) {
251
+ VMSTATE_UINT32_ARRAY(regs, IMX7SRCState, SRC_MAX),
252
+ VMSTATE_END_OF_LIST()
253
+ },
53
+};
254
+};
54
+
255
+
55
+static const int usb_intr[XLNX_ZYNQMP_NUM_USB] = {
256
+static void imx7_src_reset(DeviceState *dev)
56
+ 65, 70
257
+{
258
+ IMX7SRCState *s = IMX7_SRC(dev);
259
+
260
+ memset(s->regs, 0, sizeof(s->regs));
261
+
262
+ /* Set reset values */
263
+ s->regs[SRC_SCR] = 0xA0;
264
+ s->regs[SRC_SRSR] = 0x1;
265
+ s->regs[SRC_SIMR] = 0x1F;
266
+}
267
+
268
+static uint64_t imx7_src_read(void *opaque, hwaddr offset, unsigned size)
269
+{
270
+ uint32_t value = 0;
271
+ IMX7SRCState *s = (IMX7SRCState *)opaque;
272
+ uint32_t index = offset >> 2;
273
+
274
+ if (index < SRC_MAX) {
275
+ value = s->regs[index];
276
+ } else {
277
+ qemu_log_mask(LOG_GUEST_ERROR, "[%s]%s: Bad register at offset 0x%"
278
+ HWADDR_PRIx "\n", TYPE_IMX7_SRC, __func__, offset);
279
+ }
280
+
281
+ trace_imx7_src_read(imx7_src_reg_name(index), value);
282
+
283
+ return value;
284
+}
285
+
286
+
287
+/*
288
+ * The reset is asynchronous so we need to defer clearing the reset
289
+ * bit until the work is completed.
290
+ */
291
+
292
+struct SRCSCRResetInfo {
293
+ IMX7SRCState *s;
294
+ uint32_t reset_bit;
57
+};
295
+};
58
+
296
+
59
typedef struct XlnxZynqMPGICRegion {
297
+static void imx7_clear_reset_bit(CPUState *cpu, run_on_cpu_data data)
60
int region_index;
298
+{
61
uint32_t address;
299
+ struct SRCSCRResetInfo *ri = data.host_ptr;
62
@@ -XXX,XX +XXX,XX @@ static void xlnx_zynqmp_init(Object *obj)
300
+ IMX7SRCState *s = ri->s;
63
object_initialize_child(obj, "qspi-dma", &s->qspi_dma, TYPE_XLNX_CSU_DMA);
301
+
64
object_initialize_child(obj, "qspi-irq-orgate",
302
+ assert(qemu_mutex_iothread_locked());
65
&s->qspi_irq_orgate, TYPE_OR_IRQ);
303
+
66
+
304
+ s->regs[SRC_A7RCR0] = deposit32(s->regs[SRC_A7RCR0], ri->reset_bit, 1, 0);
67
+ for (i = 0; i < XLNX_ZYNQMP_NUM_USB; i++) {
305
+
68
+ object_initialize_child(obj, "usb[*]", &s->usb[i], TYPE_USB_DWC3);
306
+ trace_imx7_src_write(imx7_src_reg_name(SRC_A7RCR0), s->regs[SRC_A7RCR0]);
307
+
308
+ g_free(ri);
309
+}
310
+
311
+static void imx7_defer_clear_reset_bit(uint32_t cpuid,
312
+ IMX7SRCState *s,
313
+ uint32_t reset_shift)
314
+{
315
+ struct SRCSCRResetInfo *ri;
316
+ CPUState *cpu = arm_get_cpu_by_id(cpuid);
317
+
318
+ if (!cpu) {
319
+ return;
69
+ }
320
+ }
70
}
321
+
71
322
+ ri = g_new(struct SRCSCRResetInfo, 1);
72
static void xlnx_zynqmp_realize(DeviceState *dev, Error **errp)
323
+ ri->s = s;
73
@@ -XXX,XX +XXX,XX @@ static void xlnx_zynqmp_realize(DeviceState *dev, Error **errp)
324
+ ri->reset_bit = reset_shift;
74
object_property_add_alias(OBJECT(s), bus_name,
325
+
75
OBJECT(&s->qspi), target_bus);
326
+ async_run_on_cpu(cpu, imx7_clear_reset_bit, RUN_ON_CPU_HOST_PTR(ri));
76
}
327
+}
77
+
328
+
78
+ for (i = 0; i < XLNX_ZYNQMP_NUM_USB; i++) {
329
+
79
+ if (!object_property_set_link(OBJECT(&s->usb[i].sysbus_xhci), "dma",
330
+static void imx7_src_write(void *opaque, hwaddr offset, uint64_t value,
80
+ OBJECT(system_memory), errp)) {
331
+ unsigned size)
81
+ return;
332
+{
333
+ IMX7SRCState *s = (IMX7SRCState *)opaque;
334
+ uint32_t index = offset >> 2;
335
+ long unsigned int change_mask;
336
+ uint32_t current_value = value;
337
+
338
+ if (index >= SRC_MAX) {
339
+ qemu_log_mask(LOG_GUEST_ERROR, "[%s]%s: Bad register at offset 0x%"
340
+ HWADDR_PRIx "\n", TYPE_IMX7_SRC, __func__, offset);
341
+ return;
342
+ }
343
+
344
+ trace_imx7_src_write(imx7_src_reg_name(SRC_A7RCR0), s->regs[SRC_A7RCR0]);
345
+
346
+ change_mask = s->regs[index] ^ (uint32_t)current_value;
347
+
348
+ switch (index) {
349
+ case SRC_A7RCR0:
350
+ if (FIELD_EX32(change_mask, CORE0, RST)) {
351
+ arm_reset_cpu(0);
352
+ imx7_defer_clear_reset_bit(0, s, R_CORE0_RST_SHIFT);
82
+ }
353
+ }
83
+
354
+ if (FIELD_EX32(change_mask, CORE1, RST)) {
84
+ qdev_prop_set_uint32(DEVICE(&s->usb[i].sysbus_xhci), "intrs", 4);
355
+ arm_reset_cpu(1);
85
+ qdev_prop_set_uint32(DEVICE(&s->usb[i].sysbus_xhci), "slots", 2);
356
+ imx7_defer_clear_reset_bit(1, s, R_CORE1_RST_SHIFT);
86
+
87
+ if (!sysbus_realize(SYS_BUS_DEVICE(&s->usb[i]), errp)) {
88
+ return;
89
+ }
357
+ }
90
+
358
+ s->regs[index] = current_value;
91
+ sysbus_mmio_map(SYS_BUS_DEVICE(&s->usb[i]), 0, usb_addr[i]);
359
+ break;
92
+ sysbus_connect_irq(SYS_BUS_DEVICE(&s->usb[i].sysbus_xhci), 0,
360
+ case SRC_A7RCR1:
93
+ gic_spi[usb_intr[i]]);
361
+ /*
94
+ sysbus_connect_irq(SYS_BUS_DEVICE(&s->usb[i].sysbus_xhci), 1,
362
+ * On real hardware when the system reset controller starts a
95
+ gic_spi[usb_intr[i] + 1]);
363
+ * secondary CPU it runs through some boot ROM code which reads
96
+ sysbus_connect_irq(SYS_BUS_DEVICE(&s->usb[i].sysbus_xhci), 2,
364
+ * the SRC_GPRX registers controlling the start address and branches
97
+ gic_spi[usb_intr[i] + 2]);
365
+ * to it.
98
+ sysbus_connect_irq(SYS_BUS_DEVICE(&s->usb[i].sysbus_xhci), 3,
366
+ * Here we are taking a short cut and branching directly to the
99
+ gic_spi[usb_intr[i] + 3]);
367
+ * requested address (we don't want to run the boot ROM code inside
368
+ * QEMU)
369
+ */
370
+ if (FIELD_EX32(change_mask, CORE1, ENABLE)) {
371
+ if (FIELD_EX32(current_value, CORE1, ENABLE)) {
372
+ /* CORE 1 is brought up */
373
+ arm_set_cpu_on(1, s->regs[SRC_GPR3], s->regs[SRC_GPR4],
374
+ 3, false);
375
+ } else {
376
+ /* CORE 1 is shut down */
377
+ arm_set_cpu_off(1);
378
+ }
379
+ /* We clear the reset bits as the processor changed state */
380
+ imx7_defer_clear_reset_bit(1, s, R_CORE1_RST_SHIFT);
381
+ clear_bit(R_CORE1_RST_SHIFT, &change_mask);
382
+ }
383
+ s->regs[index] = current_value;
384
+ break;
385
+ default:
386
+ s->regs[index] = current_value;
387
+ break;
100
+ }
388
+ }
101
}
389
+}
102
390
+
103
static Property xlnx_zynqmp_props[] = {
391
+static const struct MemoryRegionOps imx7_src_ops = {
392
+ .read = imx7_src_read,
393
+ .write = imx7_src_write,
394
+ .endianness = DEVICE_NATIVE_ENDIAN,
395
+ .valid = {
396
+ /*
397
+ * Our device would not work correctly if the guest was doing
398
+ * unaligned access. This might not be a limitation on the real
399
+ * device but in practice there is no reason for a guest to access
400
+ * this device unaligned.
401
+ */
402
+ .min_access_size = 4,
403
+ .max_access_size = 4,
404
+ .unaligned = false,
405
+ },
406
+};
407
+
408
+static void imx7_src_realize(DeviceState *dev, Error **errp)
409
+{
410
+ IMX7SRCState *s = IMX7_SRC(dev);
411
+
412
+ memory_region_init_io(&s->iomem, OBJECT(dev), &imx7_src_ops, s,
413
+ TYPE_IMX7_SRC, 0x1000);
414
+ sysbus_init_mmio(SYS_BUS_DEVICE(dev), &s->iomem);
415
+}
416
+
417
+static void imx7_src_class_init(ObjectClass *klass, void *data)
418
+{
419
+ DeviceClass *dc = DEVICE_CLASS(klass);
420
+
421
+ dc->realize = imx7_src_realize;
422
+ dc->reset = imx7_src_reset;
423
+ dc->vmsd = &vmstate_imx7_src;
424
+ dc->desc = "i.MX6 System Reset Controller";
425
+}
426
+
427
+static const TypeInfo imx7_src_info = {
428
+ .name = TYPE_IMX7_SRC,
429
+ .parent = TYPE_SYS_BUS_DEVICE,
430
+ .instance_size = sizeof(IMX7SRCState),
431
+ .class_init = imx7_src_class_init,
432
+};
433
+
434
+static void imx7_src_register_types(void)
435
+{
436
+ type_register_static(&imx7_src_info);
437
+}
438
+
439
+type_init(imx7_src_register_types)
440
diff --git a/hw/misc/meson.build b/hw/misc/meson.build
441
index XXXXXXX..XXXXXXX 100644
442
--- a/hw/misc/meson.build
443
+++ b/hw/misc/meson.build
444
@@ -XXX,XX +XXX,XX @@ system_ss.add(when: 'CONFIG_IMX', if_true: files(
445
'imx6_src.c',
446
'imx6ul_ccm.c',
447
'imx7_ccm.c',
448
+ 'imx7_src.c',
449
'imx7_gpr.c',
450
'imx7_snvs.c',
451
'imx_ccm.c',
452
diff --git a/hw/misc/trace-events b/hw/misc/trace-events
453
index XXXXXXX..XXXXXXX 100644
454
--- a/hw/misc/trace-events
455
+++ b/hw/misc/trace-events
456
@@ -XXX,XX +XXX,XX @@ ccm_clock_freq(uint32_t clock, uint32_t freq) "(Clock = %d) = %d"
457
ccm_read_reg(const char *reg_name, uint32_t value) "reg[%s] <= 0x%" PRIx32
458
ccm_write_reg(const char *reg_name, uint32_t value) "reg[%s] => 0x%" PRIx32
459
460
+# imx7_src.c
461
+imx7_src_read(const char *reg_name, uint32_t value) "reg[%s] => 0x%" PRIx32
462
+imx7_src_write(const char *reg_name, uint32_t value) "reg[%s] <= 0x%" PRIx32
463
+
464
# iotkit-sysinfo.c
465
iotkit_sysinfo_read(uint64_t offset, uint64_t data, unsigned size) "IoTKit SysInfo read: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %u"
466
iotkit_sysinfo_write(uint64_t offset, uint64_t data, unsigned size) "IoTKit SysInfo write: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %u"
104
--
467
--
105
2.25.1
468
2.34.1
diff view generated by jsdifflib
New patch
[PULL 17/24] target/arm: Catch illegal-exception-return from EL3 with bad NSE/NS
1
The architecture requires (R_TYTWB) that an attempt to return from EL3
2
when SCR_EL3.{NSE,NS} are {1,0} is an illegal exception return. (This
3
enforces that the CPU can't ever be executing below EL3 with the
4
NSE,NS bits indicating an invalid security state.)
1
5
6
We were missing this check; add it.
7
8
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
10
Message-id: 20230807150618.101357-1-peter.maydell@linaro.org
11
---
12
target/arm/tcg/helper-a64.c | 9 +++++++++
13
1 file changed, 9 insertions(+)
14
15
diff --git a/target/arm/tcg/helper-a64.c b/target/arm/tcg/helper-a64.c
16
index XXXXXXX..XXXXXXX 100644
17
--- a/target/arm/tcg/helper-a64.c
18
+++ b/target/arm/tcg/helper-a64.c
19
@@ -XXX,XX +XXX,XX @@ void HELPER(exception_return)(CPUARMState *env, uint64_t new_pc)
20
spsr &= ~PSTATE_SS;
21
}
22
23
+ /*
24
+ * FEAT_RME forbids return from EL3 with an invalid security state.
25
+ * We don't need an explicit check for FEAT_RME here because we enforce
26
+ * in scr_write() that you can't set the NSE bit without it.
27
+ */
28
+ if (cur_el == 3 && (env->cp15.scr_el3 & (SCR_NS | SCR_NSE)) == SCR_NSE) {
29
+ goto illegal_return;
30
+ }
31
+
32
new_el = el_from_spsr(spsr);
33
if (new_el == -1) {
34
goto illegal_return;
35
--
36
2.34.1
diff view generated by jsdifflib
New patch
[PULL 18/24] hw/rtc/m48t59: Use 64-bit arithmetic in set_alarm()
1
In the m48t59 device we almost always use 64-bit arithmetic when
2
dealing with time_t deltas. The one exception is in set_alarm(),
3
which currently uses a plain 'int' to hold the difference between two
4
time_t values. Switch to int64_t instead to avoid any possible
5
overflow issues.
1
6
7
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
8
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
9
---
10
hw/rtc/m48t59.c | 2 +-
11
1 file changed, 1 insertion(+), 1 deletion(-)
12
13
diff --git a/hw/rtc/m48t59.c b/hw/rtc/m48t59.c
14
index XXXXXXX..XXXXXXX 100644
15
--- a/hw/rtc/m48t59.c
16
+++ b/hw/rtc/m48t59.c
17
@@ -XXX,XX +XXX,XX @@ static void alarm_cb (void *opaque)
18
19
static void set_alarm(M48t59State *NVRAM)
20
{
21
- int diff;
22
+ int64_t diff;
23
if (NVRAM->alrm_timer != NULL) {
24
timer_del(NVRAM->alrm_timer);
25
diff = qemu_timedate_diff(&NVRAM->alarm) - NVRAM->time_offset;
26
--
27
2.34.1
28
29
diff view generated by jsdifflib
New patch
[PULL 19/24] hw/rtc/twl92230: Use int64_t for sec_offset and alm_sec
1
In the twl92230 device, use int64_t for the two state fields
2
sec_offset and alm_sec, because we set these to values that
3
are either time_t or differences between two time_t values.
1
4
5
These fields aren't saved in vmstate anywhere, so we can
6
safely widen them.
7
8
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
10
---
11
hw/rtc/twl92230.c | 4 ++--
12
1 file changed, 2 insertions(+), 2 deletions(-)
13
14
diff --git a/hw/rtc/twl92230.c b/hw/rtc/twl92230.c
15
index XXXXXXX..XXXXXXX 100644
16
--- a/hw/rtc/twl92230.c
17
+++ b/hw/rtc/twl92230.c
18
@@ -XXX,XX +XXX,XX @@ struct MenelausState {
19
struct tm tm;
20
struct tm new;
21
struct tm alm;
22
- int sec_offset;
23
- int alm_sec;
24
+ int64_t sec_offset;
25
+ int64_t alm_sec;
26
int next_comp;
27
} rtc;
28
uint16_t rtc_next_vmstate;
29
--
30
2.34.1
31
32
diff view generated by jsdifflib
New patch
[PULL 20/24] hw/rtc/aspeed_rtc: Use 64-bit offset for holding time_t difference
1
In the aspeed_rtc device we store a difference between two time_t
2
values in an 'int'. This is not really correct when time_t could
3
be 64 bits. Enlarge the field to 'int64_t'.
1
4
5
This is a migration compatibility break for the aspeed boards.
6
While we are changing the vmstate, remove the accidental
7
duplicate of the offset field.
8
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
Reviewed-by: Cédric Le Goater <clg@kaod.org>
11
---
12
include/hw/rtc/aspeed_rtc.h | 2 +-
13
hw/rtc/aspeed_rtc.c | 5 ++---
14
2 files changed, 3 insertions(+), 4 deletions(-)
15
16
diff --git a/include/hw/rtc/aspeed_rtc.h b/include/hw/rtc/aspeed_rtc.h
17
index XXXXXXX..XXXXXXX 100644
18
--- a/include/hw/rtc/aspeed_rtc.h
19
+++ b/include/hw/rtc/aspeed_rtc.h
20
@@ -XXX,XX +XXX,XX @@ struct AspeedRtcState {
21
qemu_irq irq;
22
23
uint32_t reg[0x18];
24
- int offset;
25
+ int64_t offset;
26
27
};
28
29
diff --git a/hw/rtc/aspeed_rtc.c b/hw/rtc/aspeed_rtc.c
30
index XXXXXXX..XXXXXXX 100644
31
--- a/hw/rtc/aspeed_rtc.c
32
+++ b/hw/rtc/aspeed_rtc.c
33
@@ -XXX,XX +XXX,XX @@ static const MemoryRegionOps aspeed_rtc_ops = {
34
35
static const VMStateDescription vmstate_aspeed_rtc = {
36
.name = TYPE_ASPEED_RTC,
37
- .version_id = 1,
38
+ .version_id = 2,
39
.fields = (VMStateField[]) {
40
VMSTATE_UINT32_ARRAY(reg, AspeedRtcState, 0x18),
41
- VMSTATE_INT32(offset, AspeedRtcState),
42
- VMSTATE_INT32(offset, AspeedRtcState),
43
+ VMSTATE_INT64(offset, AspeedRtcState),
44
VMSTATE_END_OF_LIST()
45
}
46
};
47
--
48
2.34.1
49
50
diff view generated by jsdifflib
[PULL 04/10] target/arm: Rearrange cpu64.c so all the CPU initfns are together
[PULL 21/24] rtc: Use time_t for passing and returning time offsets
1
cpu64.c has ended up in a slightly odd order -- it starts with the
1
The functions qemu_get_timedate() and qemu_timedate_diff() take
2
initfns for most of the models-real-hardware CPUs; after that comes a
2
and return a time offset as an integer. Coverity points out that
3
bunch of support code for SVE, SME, pauth and LPA2 properties. Then
3
means that when an RTC device implementation holds an offset
4
come the initfns for the 'host' and 'max' CPU types, and then after
4
as a time_t, as the m48t59 does, the time_t will get truncated.
5
that one more models-real-hardware CPU initfn, for a64fx. (This
5
(CID 1507157, 1517772).
6
ordering is partly historical and partly required because a64fx needs
7
the SVE properties.)
8
6
9
Reorder the file into:
7
The functions work with time_t internally, so make them use that type
10
* CPU property support functions
8
in their APIs.
11
* initfns for real hardware CPUs
9
12
* initfns for host and max
10
Note that this won't help any Y2038 issues where either the device
13
* class boilerplate
11
model itself is keeping the offset in a 32-bit integer, or where the
12
hardware under emulation has Y2038 or other rollover problems. If we
13
missed any cases of the former then hopefully Coverity will warn us
14
about them since after this patch we'd be truncating a time_t in
15
assignments from qemu_timedate_diff().)
14
16
15
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
17
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
16
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
18
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
17
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
18
---
19
---
19
target/arm/cpu64.c | 712 ++++++++++++++++++++++-----------------------
20
include/sysemu/rtc.h | 4 ++--
20
1 file changed, 356 insertions(+), 356 deletions(-)
21
softmmu/rtc.c | 4 ++--
22
2 files changed, 4 insertions(+), 4 deletions(-)
21
23
22
diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
24
diff --git a/include/sysemu/rtc.h b/include/sysemu/rtc.h
23
index XXXXXXX..XXXXXXX 100644
25
index XXXXXXX..XXXXXXX 100644
24
--- a/target/arm/cpu64.c
26
--- a/include/sysemu/rtc.h
25
+++ b/target/arm/cpu64.c
27
+++ b/include/sysemu/rtc.h
26
@@ -XXX,XX +XXX,XX @@ static void aarch64_a35_initfn(Object *obj)
28
@@ -XXX,XX +XXX,XX @@
27
define_cortex_a72_a57_a53_cp_reginfo(cpu);
29
* The behaviour of the clock whose value this function returns will
30
* depend on the -rtc command line option passed by the user.
31
*/
32
-void qemu_get_timedate(struct tm *tm, int offset);
33
+void qemu_get_timedate(struct tm *tm, time_t offset);
34
35
/**
36
* qemu_timedate_diff: Return difference between a struct tm and the RTC
37
@@ -XXX,XX +XXX,XX @@ void qemu_get_timedate(struct tm *tm, int offset);
38
* a timestamp one hour further ahead than the current RTC time
39
* then this function will return 3600.
40
*/
41
-int qemu_timedate_diff(struct tm *tm);
42
+time_t qemu_timedate_diff(struct tm *tm);
43
44
#endif
45
diff --git a/softmmu/rtc.c b/softmmu/rtc.c
46
index XXXXXXX..XXXXXXX 100644
47
--- a/softmmu/rtc.c
48
+++ b/softmmu/rtc.c
49
@@ -XXX,XX +XXX,XX @@ static time_t qemu_ref_timedate(QEMUClockType clock)
50
return value;
28
}
51
}
29
52
30
-static void aarch64_a57_initfn(Object *obj)
53
-void qemu_get_timedate(struct tm *tm, int offset)
31
-{
54
+void qemu_get_timedate(struct tm *tm, time_t offset)
32
- ARMCPU *cpu = ARM_CPU(obj);
33
-
34
- cpu->dtb_compatible = "arm,cortex-a57";
35
- set_feature(&cpu->env, ARM_FEATURE_V8);
36
- set_feature(&cpu->env, ARM_FEATURE_NEON);
37
- set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
38
- set_feature(&cpu->env, ARM_FEATURE_AARCH64);
39
- set_feature(&cpu->env, ARM_FEATURE_CBAR_RO);
40
- set_feature(&cpu->env, ARM_FEATURE_EL2);
41
- set_feature(&cpu->env, ARM_FEATURE_EL3);
42
- set_feature(&cpu->env, ARM_FEATURE_PMU);
43
- cpu->kvm_target = QEMU_KVM_ARM_TARGET_CORTEX_A57;
44
- cpu->midr = 0x411fd070;
45
- cpu->revidr = 0x00000000;
46
- cpu->reset_fpsid = 0x41034070;
47
- cpu->isar.mvfr0 = 0x10110222;
48
- cpu->isar.mvfr1 = 0x12111111;
49
- cpu->isar.mvfr2 = 0x00000043;
50
- cpu->ctr = 0x8444c004;
51
- cpu->reset_sctlr = 0x00c50838;
52
- cpu->isar.id_pfr0 = 0x00000131;
53
- cpu->isar.id_pfr1 = 0x00011011;
54
- cpu->isar.id_dfr0 = 0x03010066;
55
- cpu->id_afr0 = 0x00000000;
56
- cpu->isar.id_mmfr0 = 0x10101105;
57
- cpu->isar.id_mmfr1 = 0x40000000;
58
- cpu->isar.id_mmfr2 = 0x01260000;
59
- cpu->isar.id_mmfr3 = 0x02102211;
60
- cpu->isar.id_isar0 = 0x02101110;
61
- cpu->isar.id_isar1 = 0x13112111;
62
- cpu->isar.id_isar2 = 0x21232042;
63
- cpu->isar.id_isar3 = 0x01112131;
64
- cpu->isar.id_isar4 = 0x00011142;
65
- cpu->isar.id_isar5 = 0x00011121;
66
- cpu->isar.id_isar6 = 0;
67
- cpu->isar.id_aa64pfr0 = 0x00002222;
68
- cpu->isar.id_aa64dfr0 = 0x10305106;
69
- cpu->isar.id_aa64isar0 = 0x00011120;
70
- cpu->isar.id_aa64mmfr0 = 0x00001124;
71
- cpu->isar.dbgdidr = 0x3516d000;
72
- cpu->isar.dbgdevid = 0x01110f13;
73
- cpu->isar.dbgdevid1 = 0x2;
74
- cpu->isar.reset_pmcr_el0 = 0x41013000;
75
- cpu->clidr = 0x0a200023;
76
- cpu->ccsidr[0] = 0x701fe00a; /* 32KB L1 dcache */
77
- cpu->ccsidr[1] = 0x201fe012; /* 48KB L1 icache */
78
- cpu->ccsidr[2] = 0x70ffe07a; /* 2048KB L2 cache */
79
- cpu->dcz_blocksize = 4; /* 64 bytes */
80
- cpu->gic_num_lrs = 4;
81
- cpu->gic_vpribits = 5;
82
- cpu->gic_vprebits = 5;
83
- cpu->gic_pribits = 5;
84
- define_cortex_a72_a57_a53_cp_reginfo(cpu);
85
-}
86
-
87
-static void aarch64_a53_initfn(Object *obj)
88
-{
89
- ARMCPU *cpu = ARM_CPU(obj);
90
-
91
- cpu->dtb_compatible = "arm,cortex-a53";
92
- set_feature(&cpu->env, ARM_FEATURE_V8);
93
- set_feature(&cpu->env, ARM_FEATURE_NEON);
94
- set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
95
- set_feature(&cpu->env, ARM_FEATURE_AARCH64);
96
- set_feature(&cpu->env, ARM_FEATURE_CBAR_RO);
97
- set_feature(&cpu->env, ARM_FEATURE_EL2);
98
- set_feature(&cpu->env, ARM_FEATURE_EL3);
99
- set_feature(&cpu->env, ARM_FEATURE_PMU);
100
- cpu->kvm_target = QEMU_KVM_ARM_TARGET_CORTEX_A53;
101
- cpu->midr = 0x410fd034;
102
- cpu->revidr = 0x00000000;
103
- cpu->reset_fpsid = 0x41034070;
104
- cpu->isar.mvfr0 = 0x10110222;
105
- cpu->isar.mvfr1 = 0x12111111;
106
- cpu->isar.mvfr2 = 0x00000043;
107
- cpu->ctr = 0x84448004; /* L1Ip = VIPT */
108
- cpu->reset_sctlr = 0x00c50838;
109
- cpu->isar.id_pfr0 = 0x00000131;
110
- cpu->isar.id_pfr1 = 0x00011011;
111
- cpu->isar.id_dfr0 = 0x03010066;
112
- cpu->id_afr0 = 0x00000000;
113
- cpu->isar.id_mmfr0 = 0x10101105;
114
- cpu->isar.id_mmfr1 = 0x40000000;
115
- cpu->isar.id_mmfr2 = 0x01260000;
116
- cpu->isar.id_mmfr3 = 0x02102211;
117
- cpu->isar.id_isar0 = 0x02101110;
118
- cpu->isar.id_isar1 = 0x13112111;
119
- cpu->isar.id_isar2 = 0x21232042;
120
- cpu->isar.id_isar3 = 0x01112131;
121
- cpu->isar.id_isar4 = 0x00011142;
122
- cpu->isar.id_isar5 = 0x00011121;
123
- cpu->isar.id_isar6 = 0;
124
- cpu->isar.id_aa64pfr0 = 0x00002222;
125
- cpu->isar.id_aa64dfr0 = 0x10305106;
126
- cpu->isar.id_aa64isar0 = 0x00011120;
127
- cpu->isar.id_aa64mmfr0 = 0x00001122; /* 40 bit physical addr */
128
- cpu->isar.dbgdidr = 0x3516d000;
129
- cpu->isar.dbgdevid = 0x00110f13;
130
- cpu->isar.dbgdevid1 = 0x1;
131
- cpu->isar.reset_pmcr_el0 = 0x41033000;
132
- cpu->clidr = 0x0a200023;
133
- cpu->ccsidr[0] = 0x700fe01a; /* 32KB L1 dcache */
134
- cpu->ccsidr[1] = 0x201fe00a; /* 32KB L1 icache */
135
- cpu->ccsidr[2] = 0x707fe07a; /* 1024KB L2 cache */
136
- cpu->dcz_blocksize = 4; /* 64 bytes */
137
- cpu->gic_num_lrs = 4;
138
- cpu->gic_vpribits = 5;
139
- cpu->gic_vprebits = 5;
140
- cpu->gic_pribits = 5;
141
- define_cortex_a72_a57_a53_cp_reginfo(cpu);
142
-}
143
-
144
-static void aarch64_a72_initfn(Object *obj)
145
-{
146
- ARMCPU *cpu = ARM_CPU(obj);
147
-
148
- cpu->dtb_compatible = "arm,cortex-a72";
149
- set_feature(&cpu->env, ARM_FEATURE_V8);
150
- set_feature(&cpu->env, ARM_FEATURE_NEON);
151
- set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
152
- set_feature(&cpu->env, ARM_FEATURE_AARCH64);
153
- set_feature(&cpu->env, ARM_FEATURE_CBAR_RO);
154
- set_feature(&cpu->env, ARM_FEATURE_EL2);
155
- set_feature(&cpu->env, ARM_FEATURE_EL3);
156
- set_feature(&cpu->env, ARM_FEATURE_PMU);
157
- cpu->midr = 0x410fd083;
158
- cpu->revidr = 0x00000000;
159
- cpu->reset_fpsid = 0x41034080;
160
- cpu->isar.mvfr0 = 0x10110222;
161
- cpu->isar.mvfr1 = 0x12111111;
162
- cpu->isar.mvfr2 = 0x00000043;
163
- cpu->ctr = 0x8444c004;
164
- cpu->reset_sctlr = 0x00c50838;
165
- cpu->isar.id_pfr0 = 0x00000131;
166
- cpu->isar.id_pfr1 = 0x00011011;
167
- cpu->isar.id_dfr0 = 0x03010066;
168
- cpu->id_afr0 = 0x00000000;
169
- cpu->isar.id_mmfr0 = 0x10201105;
170
- cpu->isar.id_mmfr1 = 0x40000000;
171
- cpu->isar.id_mmfr2 = 0x01260000;
172
- cpu->isar.id_mmfr3 = 0x02102211;
173
- cpu->isar.id_isar0 = 0x02101110;
174
- cpu->isar.id_isar1 = 0x13112111;
175
- cpu->isar.id_isar2 = 0x21232042;
176
- cpu->isar.id_isar3 = 0x01112131;
177
- cpu->isar.id_isar4 = 0x00011142;
178
- cpu->isar.id_isar5 = 0x00011121;
179
- cpu->isar.id_aa64pfr0 = 0x00002222;
180
- cpu->isar.id_aa64dfr0 = 0x10305106;
181
- cpu->isar.id_aa64isar0 = 0x00011120;
182
- cpu->isar.id_aa64mmfr0 = 0x00001124;
183
- cpu->isar.dbgdidr = 0x3516d000;
184
- cpu->isar.dbgdevid = 0x01110f13;
185
- cpu->isar.dbgdevid1 = 0x2;
186
- cpu->isar.reset_pmcr_el0 = 0x41023000;
187
- cpu->clidr = 0x0a200023;
188
- cpu->ccsidr[0] = 0x701fe00a; /* 32KB L1 dcache */
189
- cpu->ccsidr[1] = 0x201fe012; /* 48KB L1 icache */
190
- cpu->ccsidr[2] = 0x707fe07a; /* 1MB L2 cache */
191
- cpu->dcz_blocksize = 4; /* 64 bytes */
192
- cpu->gic_num_lrs = 4;
193
- cpu->gic_vpribits = 5;
194
- cpu->gic_vprebits = 5;
195
- cpu->gic_pribits = 5;
196
- define_cortex_a72_a57_a53_cp_reginfo(cpu);
197
-}
198
-
199
-static void aarch64_a76_initfn(Object *obj)
200
-{
201
- ARMCPU *cpu = ARM_CPU(obj);
202
-
203
- cpu->dtb_compatible = "arm,cortex-a76";
204
- set_feature(&cpu->env, ARM_FEATURE_V8);
205
- set_feature(&cpu->env, ARM_FEATURE_NEON);
206
- set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
207
- set_feature(&cpu->env, ARM_FEATURE_AARCH64);
208
- set_feature(&cpu->env, ARM_FEATURE_CBAR_RO);
209
- set_feature(&cpu->env, ARM_FEATURE_EL2);
210
- set_feature(&cpu->env, ARM_FEATURE_EL3);
211
- set_feature(&cpu->env, ARM_FEATURE_PMU);
212
-
213
- /* Ordered by B2.4 AArch64 registers by functional group */
214
- cpu->clidr = 0x82000023;
215
- cpu->ctr = 0x8444C004;
216
- cpu->dcz_blocksize = 4;
217
- cpu->isar.id_aa64dfr0 = 0x0000000010305408ull;
218
- cpu->isar.id_aa64isar0 = 0x0000100010211120ull;
219
- cpu->isar.id_aa64isar1 = 0x0000000000100001ull;
220
- cpu->isar.id_aa64mmfr0 = 0x0000000000101122ull;
221
- cpu->isar.id_aa64mmfr1 = 0x0000000010212122ull;
222
- cpu->isar.id_aa64mmfr2 = 0x0000000000001011ull;
223
- cpu->isar.id_aa64pfr0 = 0x1100000010111112ull; /* GIC filled in later */
224
- cpu->isar.id_aa64pfr1 = 0x0000000000000010ull;
225
- cpu->id_afr0 = 0x00000000;
226
- cpu->isar.id_dfr0 = 0x04010088;
227
- cpu->isar.id_isar0 = 0x02101110;
228
- cpu->isar.id_isar1 = 0x13112111;
229
- cpu->isar.id_isar2 = 0x21232042;
230
- cpu->isar.id_isar3 = 0x01112131;
231
- cpu->isar.id_isar4 = 0x00010142;
232
- cpu->isar.id_isar5 = 0x01011121;
233
- cpu->isar.id_isar6 = 0x00000010;
234
- cpu->isar.id_mmfr0 = 0x10201105;
235
- cpu->isar.id_mmfr1 = 0x40000000;
236
- cpu->isar.id_mmfr2 = 0x01260000;
237
- cpu->isar.id_mmfr3 = 0x02122211;
238
- cpu->isar.id_mmfr4 = 0x00021110;
239
- cpu->isar.id_pfr0 = 0x10010131;
240
- cpu->isar.id_pfr1 = 0x00010000; /* GIC filled in later */
241
- cpu->isar.id_pfr2 = 0x00000011;
242
- cpu->midr = 0x414fd0b1; /* r4p1 */
243
- cpu->revidr = 0;
244
-
245
- /* From B2.18 CCSIDR_EL1 */
246
- cpu->ccsidr[0] = 0x701fe01a; /* 64KB L1 dcache */
247
- cpu->ccsidr[1] = 0x201fe01a; /* 64KB L1 icache */
248
- cpu->ccsidr[2] = 0x707fe03a; /* 512KB L2 cache */
249
-
250
- /* From B2.93 SCTLR_EL3 */
251
- cpu->reset_sctlr = 0x30c50838;
252
-
253
- /* From B4.23 ICH_VTR_EL2 */
254
- cpu->gic_num_lrs = 4;
255
- cpu->gic_vpribits = 5;
256
- cpu->gic_vprebits = 5;
257
- cpu->gic_pribits = 5;
258
-
259
- /* From B5.1 AdvSIMD AArch64 register summary */
260
- cpu->isar.mvfr0 = 0x10110222;
261
- cpu->isar.mvfr1 = 0x13211111;
262
- cpu->isar.mvfr2 = 0x00000043;
263
-
264
- /* From D5.1 AArch64 PMU register summary */
265
- cpu->isar.reset_pmcr_el0 = 0x410b3000;
266
-}
267
-
268
-static void aarch64_neoverse_n1_initfn(Object *obj)
269
-{
270
- ARMCPU *cpu = ARM_CPU(obj);
271
-
272
- cpu->dtb_compatible = "arm,neoverse-n1";
273
- set_feature(&cpu->env, ARM_FEATURE_V8);
274
- set_feature(&cpu->env, ARM_FEATURE_NEON);
275
- set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
276
- set_feature(&cpu->env, ARM_FEATURE_AARCH64);
277
- set_feature(&cpu->env, ARM_FEATURE_CBAR_RO);
278
- set_feature(&cpu->env, ARM_FEATURE_EL2);
279
- set_feature(&cpu->env, ARM_FEATURE_EL3);
280
- set_feature(&cpu->env, ARM_FEATURE_PMU);
281
-
282
- /* Ordered by B2.4 AArch64 registers by functional group */
283
- cpu->clidr = 0x82000023;
284
- cpu->ctr = 0x8444c004;
285
- cpu->dcz_blocksize = 4;
286
- cpu->isar.id_aa64dfr0 = 0x0000000110305408ull;
287
- cpu->isar.id_aa64isar0 = 0x0000100010211120ull;
288
- cpu->isar.id_aa64isar1 = 0x0000000000100001ull;
289
- cpu->isar.id_aa64mmfr0 = 0x0000000000101125ull;
290
- cpu->isar.id_aa64mmfr1 = 0x0000000010212122ull;
291
- cpu->isar.id_aa64mmfr2 = 0x0000000000001011ull;
292
- cpu->isar.id_aa64pfr0 = 0x1100000010111112ull; /* GIC filled in later */
293
- cpu->isar.id_aa64pfr1 = 0x0000000000000020ull;
294
- cpu->id_afr0 = 0x00000000;
295
- cpu->isar.id_dfr0 = 0x04010088;
296
- cpu->isar.id_isar0 = 0x02101110;
297
- cpu->isar.id_isar1 = 0x13112111;
298
- cpu->isar.id_isar2 = 0x21232042;
299
- cpu->isar.id_isar3 = 0x01112131;
300
- cpu->isar.id_isar4 = 0x00010142;
301
- cpu->isar.id_isar5 = 0x01011121;
302
- cpu->isar.id_isar6 = 0x00000010;
303
- cpu->isar.id_mmfr0 = 0x10201105;
304
- cpu->isar.id_mmfr1 = 0x40000000;
305
- cpu->isar.id_mmfr2 = 0x01260000;
306
- cpu->isar.id_mmfr3 = 0x02122211;
307
- cpu->isar.id_mmfr4 = 0x00021110;
308
- cpu->isar.id_pfr0 = 0x10010131;
309
- cpu->isar.id_pfr1 = 0x00010000; /* GIC filled in later */
310
- cpu->isar.id_pfr2 = 0x00000011;
311
- cpu->midr = 0x414fd0c1; /* r4p1 */
312
- cpu->revidr = 0;
313
-
314
- /* From B2.23 CCSIDR_EL1 */
315
- cpu->ccsidr[0] = 0x701fe01a; /* 64KB L1 dcache */
316
- cpu->ccsidr[1] = 0x201fe01a; /* 64KB L1 icache */
317
- cpu->ccsidr[2] = 0x70ffe03a; /* 1MB L2 cache */
318
-
319
- /* From B2.98 SCTLR_EL3 */
320
- cpu->reset_sctlr = 0x30c50838;
321
-
322
- /* From B4.23 ICH_VTR_EL2 */
323
- cpu->gic_num_lrs = 4;
324
- cpu->gic_vpribits = 5;
325
- cpu->gic_vprebits = 5;
326
- cpu->gic_pribits = 5;
327
-
328
- /* From B5.1 AdvSIMD AArch64 register summary */
329
- cpu->isar.mvfr0 = 0x10110222;
330
- cpu->isar.mvfr1 = 0x13211111;
331
- cpu->isar.mvfr2 = 0x00000043;
332
-
333
- /* From D5.1 AArch64 PMU register summary */
334
- cpu->isar.reset_pmcr_el0 = 0x410c3000;
335
-}
336
-
337
void arm_cpu_sve_finalize(ARMCPU *cpu, Error **errp)
338
{
55
{
339
/*
56
time_t ti = qemu_ref_timedate(rtc_clock);
340
@@ -XXX,XX +XXX,XX @@ void arm_cpu_lpa2_finalize(ARMCPU *cpu, Error **errp)
57
341
cpu->isar.id_aa64mmfr0 = t;
58
@@ -XXX,XX +XXX,XX @@ void qemu_get_timedate(struct tm *tm, int offset)
59
}
342
}
60
}
343
61
344
+static void aarch64_a57_initfn(Object *obj)
62
-int qemu_timedate_diff(struct tm *tm)
345
+{
63
+time_t qemu_timedate_diff(struct tm *tm)
346
+ ARMCPU *cpu = ARM_CPU(obj);
347
+
348
+ cpu->dtb_compatible = "arm,cortex-a57";
349
+ set_feature(&cpu->env, ARM_FEATURE_V8);
350
+ set_feature(&cpu->env, ARM_FEATURE_NEON);
351
+ set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
352
+ set_feature(&cpu->env, ARM_FEATURE_AARCH64);
353
+ set_feature(&cpu->env, ARM_FEATURE_CBAR_RO);
354
+ set_feature(&cpu->env, ARM_FEATURE_EL2);
355
+ set_feature(&cpu->env, ARM_FEATURE_EL3);
356
+ set_feature(&cpu->env, ARM_FEATURE_PMU);
357
+ cpu->kvm_target = QEMU_KVM_ARM_TARGET_CORTEX_A57;
358
+ cpu->midr = 0x411fd070;
359
+ cpu->revidr = 0x00000000;
360
+ cpu->reset_fpsid = 0x41034070;
361
+ cpu->isar.mvfr0 = 0x10110222;
362
+ cpu->isar.mvfr1 = 0x12111111;
363
+ cpu->isar.mvfr2 = 0x00000043;
364
+ cpu->ctr = 0x8444c004;
365
+ cpu->reset_sctlr = 0x00c50838;
366
+ cpu->isar.id_pfr0 = 0x00000131;
367
+ cpu->isar.id_pfr1 = 0x00011011;
368
+ cpu->isar.id_dfr0 = 0x03010066;
369
+ cpu->id_afr0 = 0x00000000;
370
+ cpu->isar.id_mmfr0 = 0x10101105;
371
+ cpu->isar.id_mmfr1 = 0x40000000;
372
+ cpu->isar.id_mmfr2 = 0x01260000;
373
+ cpu->isar.id_mmfr3 = 0x02102211;
374
+ cpu->isar.id_isar0 = 0x02101110;
375
+ cpu->isar.id_isar1 = 0x13112111;
376
+ cpu->isar.id_isar2 = 0x21232042;
377
+ cpu->isar.id_isar3 = 0x01112131;
378
+ cpu->isar.id_isar4 = 0x00011142;
379
+ cpu->isar.id_isar5 = 0x00011121;
380
+ cpu->isar.id_isar6 = 0;
381
+ cpu->isar.id_aa64pfr0 = 0x00002222;
382
+ cpu->isar.id_aa64dfr0 = 0x10305106;
383
+ cpu->isar.id_aa64isar0 = 0x00011120;
384
+ cpu->isar.id_aa64mmfr0 = 0x00001124;
385
+ cpu->isar.dbgdidr = 0x3516d000;
386
+ cpu->isar.dbgdevid = 0x01110f13;
387
+ cpu->isar.dbgdevid1 = 0x2;
388
+ cpu->isar.reset_pmcr_el0 = 0x41013000;
389
+ cpu->clidr = 0x0a200023;
390
+ cpu->ccsidr[0] = 0x701fe00a; /* 32KB L1 dcache */
391
+ cpu->ccsidr[1] = 0x201fe012; /* 48KB L1 icache */
392
+ cpu->ccsidr[2] = 0x70ffe07a; /* 2048KB L2 cache */
393
+ cpu->dcz_blocksize = 4; /* 64 bytes */
394
+ cpu->gic_num_lrs = 4;
395
+ cpu->gic_vpribits = 5;
396
+ cpu->gic_vprebits = 5;
397
+ cpu->gic_pribits = 5;
398
+ define_cortex_a72_a57_a53_cp_reginfo(cpu);
399
+}
400
+
401
+static void aarch64_a53_initfn(Object *obj)
402
+{
403
+ ARMCPU *cpu = ARM_CPU(obj);
404
+
405
+ cpu->dtb_compatible = "arm,cortex-a53";
406
+ set_feature(&cpu->env, ARM_FEATURE_V8);
407
+ set_feature(&cpu->env, ARM_FEATURE_NEON);
408
+ set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
409
+ set_feature(&cpu->env, ARM_FEATURE_AARCH64);
410
+ set_feature(&cpu->env, ARM_FEATURE_CBAR_RO);
411
+ set_feature(&cpu->env, ARM_FEATURE_EL2);
412
+ set_feature(&cpu->env, ARM_FEATURE_EL3);
413
+ set_feature(&cpu->env, ARM_FEATURE_PMU);
414
+ cpu->kvm_target = QEMU_KVM_ARM_TARGET_CORTEX_A53;
415
+ cpu->midr = 0x410fd034;
416
+ cpu->revidr = 0x00000000;
417
+ cpu->reset_fpsid = 0x41034070;
418
+ cpu->isar.mvfr0 = 0x10110222;
419
+ cpu->isar.mvfr1 = 0x12111111;
420
+ cpu->isar.mvfr2 = 0x00000043;
421
+ cpu->ctr = 0x84448004; /* L1Ip = VIPT */
422
+ cpu->reset_sctlr = 0x00c50838;
423
+ cpu->isar.id_pfr0 = 0x00000131;
424
+ cpu->isar.id_pfr1 = 0x00011011;
425
+ cpu->isar.id_dfr0 = 0x03010066;
426
+ cpu->id_afr0 = 0x00000000;
427
+ cpu->isar.id_mmfr0 = 0x10101105;
428
+ cpu->isar.id_mmfr1 = 0x40000000;
429
+ cpu->isar.id_mmfr2 = 0x01260000;
430
+ cpu->isar.id_mmfr3 = 0x02102211;
431
+ cpu->isar.id_isar0 = 0x02101110;
432
+ cpu->isar.id_isar1 = 0x13112111;
433
+ cpu->isar.id_isar2 = 0x21232042;
434
+ cpu->isar.id_isar3 = 0x01112131;
435
+ cpu->isar.id_isar4 = 0x00011142;
436
+ cpu->isar.id_isar5 = 0x00011121;
437
+ cpu->isar.id_isar6 = 0;
438
+ cpu->isar.id_aa64pfr0 = 0x00002222;
439
+ cpu->isar.id_aa64dfr0 = 0x10305106;
440
+ cpu->isar.id_aa64isar0 = 0x00011120;
441
+ cpu->isar.id_aa64mmfr0 = 0x00001122; /* 40 bit physical addr */
442
+ cpu->isar.dbgdidr = 0x3516d000;
443
+ cpu->isar.dbgdevid = 0x00110f13;
444
+ cpu->isar.dbgdevid1 = 0x1;
445
+ cpu->isar.reset_pmcr_el0 = 0x41033000;
446
+ cpu->clidr = 0x0a200023;
447
+ cpu->ccsidr[0] = 0x700fe01a; /* 32KB L1 dcache */
448
+ cpu->ccsidr[1] = 0x201fe00a; /* 32KB L1 icache */
449
+ cpu->ccsidr[2] = 0x707fe07a; /* 1024KB L2 cache */
450
+ cpu->dcz_blocksize = 4; /* 64 bytes */
451
+ cpu->gic_num_lrs = 4;
452
+ cpu->gic_vpribits = 5;
453
+ cpu->gic_vprebits = 5;
454
+ cpu->gic_pribits = 5;
455
+ define_cortex_a72_a57_a53_cp_reginfo(cpu);
456
+}
457
+
458
+static void aarch64_a72_initfn(Object *obj)
459
+{
460
+ ARMCPU *cpu = ARM_CPU(obj);
461
+
462
+ cpu->dtb_compatible = "arm,cortex-a72";
463
+ set_feature(&cpu->env, ARM_FEATURE_V8);
464
+ set_feature(&cpu->env, ARM_FEATURE_NEON);
465
+ set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
466
+ set_feature(&cpu->env, ARM_FEATURE_AARCH64);
467
+ set_feature(&cpu->env, ARM_FEATURE_CBAR_RO);
468
+ set_feature(&cpu->env, ARM_FEATURE_EL2);
469
+ set_feature(&cpu->env, ARM_FEATURE_EL3);
470
+ set_feature(&cpu->env, ARM_FEATURE_PMU);
471
+ cpu->midr = 0x410fd083;
472
+ cpu->revidr = 0x00000000;
473
+ cpu->reset_fpsid = 0x41034080;
474
+ cpu->isar.mvfr0 = 0x10110222;
475
+ cpu->isar.mvfr1 = 0x12111111;
476
+ cpu->isar.mvfr2 = 0x00000043;
477
+ cpu->ctr = 0x8444c004;
478
+ cpu->reset_sctlr = 0x00c50838;
479
+ cpu->isar.id_pfr0 = 0x00000131;
480
+ cpu->isar.id_pfr1 = 0x00011011;
481
+ cpu->isar.id_dfr0 = 0x03010066;
482
+ cpu->id_afr0 = 0x00000000;
483
+ cpu->isar.id_mmfr0 = 0x10201105;
484
+ cpu->isar.id_mmfr1 = 0x40000000;
485
+ cpu->isar.id_mmfr2 = 0x01260000;
486
+ cpu->isar.id_mmfr3 = 0x02102211;
487
+ cpu->isar.id_isar0 = 0x02101110;
488
+ cpu->isar.id_isar1 = 0x13112111;
489
+ cpu->isar.id_isar2 = 0x21232042;
490
+ cpu->isar.id_isar3 = 0x01112131;
491
+ cpu->isar.id_isar4 = 0x00011142;
492
+ cpu->isar.id_isar5 = 0x00011121;
493
+ cpu->isar.id_aa64pfr0 = 0x00002222;
494
+ cpu->isar.id_aa64dfr0 = 0x10305106;
495
+ cpu->isar.id_aa64isar0 = 0x00011120;
496
+ cpu->isar.id_aa64mmfr0 = 0x00001124;
497
+ cpu->isar.dbgdidr = 0x3516d000;
498
+ cpu->isar.dbgdevid = 0x01110f13;
499
+ cpu->isar.dbgdevid1 = 0x2;
500
+ cpu->isar.reset_pmcr_el0 = 0x41023000;
501
+ cpu->clidr = 0x0a200023;
502
+ cpu->ccsidr[0] = 0x701fe00a; /* 32KB L1 dcache */
503
+ cpu->ccsidr[1] = 0x201fe012; /* 48KB L1 icache */
504
+ cpu->ccsidr[2] = 0x707fe07a; /* 1MB L2 cache */
505
+ cpu->dcz_blocksize = 4; /* 64 bytes */
506
+ cpu->gic_num_lrs = 4;
507
+ cpu->gic_vpribits = 5;
508
+ cpu->gic_vprebits = 5;
509
+ cpu->gic_pribits = 5;
510
+ define_cortex_a72_a57_a53_cp_reginfo(cpu);
511
+}
512
+
513
+static void aarch64_a76_initfn(Object *obj)
514
+{
515
+ ARMCPU *cpu = ARM_CPU(obj);
516
+
517
+ cpu->dtb_compatible = "arm,cortex-a76";
518
+ set_feature(&cpu->env, ARM_FEATURE_V8);
519
+ set_feature(&cpu->env, ARM_FEATURE_NEON);
520
+ set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
521
+ set_feature(&cpu->env, ARM_FEATURE_AARCH64);
522
+ set_feature(&cpu->env, ARM_FEATURE_CBAR_RO);
523
+ set_feature(&cpu->env, ARM_FEATURE_EL2);
524
+ set_feature(&cpu->env, ARM_FEATURE_EL3);
525
+ set_feature(&cpu->env, ARM_FEATURE_PMU);
526
+
527
+ /* Ordered by B2.4 AArch64 registers by functional group */
528
+ cpu->clidr = 0x82000023;
529
+ cpu->ctr = 0x8444C004;
530
+ cpu->dcz_blocksize = 4;
531
+ cpu->isar.id_aa64dfr0 = 0x0000000010305408ull;
532
+ cpu->isar.id_aa64isar0 = 0x0000100010211120ull;
533
+ cpu->isar.id_aa64isar1 = 0x0000000000100001ull;
534
+ cpu->isar.id_aa64mmfr0 = 0x0000000000101122ull;
535
+ cpu->isar.id_aa64mmfr1 = 0x0000000010212122ull;
536
+ cpu->isar.id_aa64mmfr2 = 0x0000000000001011ull;
537
+ cpu->isar.id_aa64pfr0 = 0x1100000010111112ull; /* GIC filled in later */
538
+ cpu->isar.id_aa64pfr1 = 0x0000000000000010ull;
539
+ cpu->id_afr0 = 0x00000000;
540
+ cpu->isar.id_dfr0 = 0x04010088;
541
+ cpu->isar.id_isar0 = 0x02101110;
542
+ cpu->isar.id_isar1 = 0x13112111;
543
+ cpu->isar.id_isar2 = 0x21232042;
544
+ cpu->isar.id_isar3 = 0x01112131;
545
+ cpu->isar.id_isar4 = 0x00010142;
546
+ cpu->isar.id_isar5 = 0x01011121;
547
+ cpu->isar.id_isar6 = 0x00000010;
548
+ cpu->isar.id_mmfr0 = 0x10201105;
549
+ cpu->isar.id_mmfr1 = 0x40000000;
550
+ cpu->isar.id_mmfr2 = 0x01260000;
551
+ cpu->isar.id_mmfr3 = 0x02122211;
552
+ cpu->isar.id_mmfr4 = 0x00021110;
553
+ cpu->isar.id_pfr0 = 0x10010131;
554
+ cpu->isar.id_pfr1 = 0x00010000; /* GIC filled in later */
555
+ cpu->isar.id_pfr2 = 0x00000011;
556
+ cpu->midr = 0x414fd0b1; /* r4p1 */
557
+ cpu->revidr = 0;
558
+
559
+ /* From B2.18 CCSIDR_EL1 */
560
+ cpu->ccsidr[0] = 0x701fe01a; /* 64KB L1 dcache */
561
+ cpu->ccsidr[1] = 0x201fe01a; /* 64KB L1 icache */
562
+ cpu->ccsidr[2] = 0x707fe03a; /* 512KB L2 cache */
563
+
564
+ /* From B2.93 SCTLR_EL3 */
565
+ cpu->reset_sctlr = 0x30c50838;
566
+
567
+ /* From B4.23 ICH_VTR_EL2 */
568
+ cpu->gic_num_lrs = 4;
569
+ cpu->gic_vpribits = 5;
570
+ cpu->gic_vprebits = 5;
571
+ cpu->gic_pribits = 5;
572
+
573
+ /* From B5.1 AdvSIMD AArch64 register summary */
574
+ cpu->isar.mvfr0 = 0x10110222;
575
+ cpu->isar.mvfr1 = 0x13211111;
576
+ cpu->isar.mvfr2 = 0x00000043;
577
+
578
+ /* From D5.1 AArch64 PMU register summary */
579
+ cpu->isar.reset_pmcr_el0 = 0x410b3000;
580
+}
581
+
582
+static void aarch64_a64fx_initfn(Object *obj)
583
+{
584
+ ARMCPU *cpu = ARM_CPU(obj);
585
+
586
+ cpu->dtb_compatible = "arm,a64fx";
587
+ set_feature(&cpu->env, ARM_FEATURE_V8);
588
+ set_feature(&cpu->env, ARM_FEATURE_NEON);
589
+ set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
590
+ set_feature(&cpu->env, ARM_FEATURE_AARCH64);
591
+ set_feature(&cpu->env, ARM_FEATURE_EL2);
592
+ set_feature(&cpu->env, ARM_FEATURE_EL3);
593
+ set_feature(&cpu->env, ARM_FEATURE_PMU);
594
+ cpu->midr = 0x461f0010;
595
+ cpu->revidr = 0x00000000;
596
+ cpu->ctr = 0x86668006;
597
+ cpu->reset_sctlr = 0x30000180;
598
+ cpu->isar.id_aa64pfr0 = 0x0000000101111111; /* No RAS Extensions */
599
+ cpu->isar.id_aa64pfr1 = 0x0000000000000000;
600
+ cpu->isar.id_aa64dfr0 = 0x0000000010305408;
601
+ cpu->isar.id_aa64dfr1 = 0x0000000000000000;
602
+ cpu->id_aa64afr0 = 0x0000000000000000;
603
+ cpu->id_aa64afr1 = 0x0000000000000000;
604
+ cpu->isar.id_aa64mmfr0 = 0x0000000000001122;
605
+ cpu->isar.id_aa64mmfr1 = 0x0000000011212100;
606
+ cpu->isar.id_aa64mmfr2 = 0x0000000000001011;
607
+ cpu->isar.id_aa64isar0 = 0x0000000010211120;
608
+ cpu->isar.id_aa64isar1 = 0x0000000000010001;
609
+ cpu->isar.id_aa64zfr0 = 0x0000000000000000;
610
+ cpu->clidr = 0x0000000080000023;
611
+ cpu->ccsidr[0] = 0x7007e01c; /* 64KB L1 dcache */
612
+ cpu->ccsidr[1] = 0x2007e01c; /* 64KB L1 icache */
613
+ cpu->ccsidr[2] = 0x70ffe07c; /* 8MB L2 cache */
614
+ cpu->dcz_blocksize = 6; /* 256 bytes */
615
+ cpu->gic_num_lrs = 4;
616
+ cpu->gic_vpribits = 5;
617
+ cpu->gic_vprebits = 5;
618
+ cpu->gic_pribits = 5;
619
+
620
+ /* The A64FX supports only 128, 256 and 512 bit vector lengths */
621
+ aarch64_add_sve_properties(obj);
622
+ cpu->sve_vq.supported = (1 << 0) /* 128bit */
623
+ | (1 << 1) /* 256bit */
624
+ | (1 << 3); /* 512bit */
625
+
626
+ cpu->isar.reset_pmcr_el0 = 0x46014040;
627
+
628
+ /* TODO: Add A64FX specific HPC extension registers */
629
+}
630
+
631
+static void aarch64_neoverse_n1_initfn(Object *obj)
632
+{
633
+ ARMCPU *cpu = ARM_CPU(obj);
634
+
635
+ cpu->dtb_compatible = "arm,neoverse-n1";
636
+ set_feature(&cpu->env, ARM_FEATURE_V8);
637
+ set_feature(&cpu->env, ARM_FEATURE_NEON);
638
+ set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
639
+ set_feature(&cpu->env, ARM_FEATURE_AARCH64);
640
+ set_feature(&cpu->env, ARM_FEATURE_CBAR_RO);
641
+ set_feature(&cpu->env, ARM_FEATURE_EL2);
642
+ set_feature(&cpu->env, ARM_FEATURE_EL3);
643
+ set_feature(&cpu->env, ARM_FEATURE_PMU);
644
+
645
+ /* Ordered by B2.4 AArch64 registers by functional group */
646
+ cpu->clidr = 0x82000023;
647
+ cpu->ctr = 0x8444c004;
648
+ cpu->dcz_blocksize = 4;
649
+ cpu->isar.id_aa64dfr0 = 0x0000000110305408ull;
650
+ cpu->isar.id_aa64isar0 = 0x0000100010211120ull;
651
+ cpu->isar.id_aa64isar1 = 0x0000000000100001ull;
652
+ cpu->isar.id_aa64mmfr0 = 0x0000000000101125ull;
653
+ cpu->isar.id_aa64mmfr1 = 0x0000000010212122ull;
654
+ cpu->isar.id_aa64mmfr2 = 0x0000000000001011ull;
655
+ cpu->isar.id_aa64pfr0 = 0x1100000010111112ull; /* GIC filled in later */
656
+ cpu->isar.id_aa64pfr1 = 0x0000000000000020ull;
657
+ cpu->id_afr0 = 0x00000000;
658
+ cpu->isar.id_dfr0 = 0x04010088;
659
+ cpu->isar.id_isar0 = 0x02101110;
660
+ cpu->isar.id_isar1 = 0x13112111;
661
+ cpu->isar.id_isar2 = 0x21232042;
662
+ cpu->isar.id_isar3 = 0x01112131;
663
+ cpu->isar.id_isar4 = 0x00010142;
664
+ cpu->isar.id_isar5 = 0x01011121;
665
+ cpu->isar.id_isar6 = 0x00000010;
666
+ cpu->isar.id_mmfr0 = 0x10201105;
667
+ cpu->isar.id_mmfr1 = 0x40000000;
668
+ cpu->isar.id_mmfr2 = 0x01260000;
669
+ cpu->isar.id_mmfr3 = 0x02122211;
670
+ cpu->isar.id_mmfr4 = 0x00021110;
671
+ cpu->isar.id_pfr0 = 0x10010131;
672
+ cpu->isar.id_pfr1 = 0x00010000; /* GIC filled in later */
673
+ cpu->isar.id_pfr2 = 0x00000011;
674
+ cpu->midr = 0x414fd0c1; /* r4p1 */
675
+ cpu->revidr = 0;
676
+
677
+ /* From B2.23 CCSIDR_EL1 */
678
+ cpu->ccsidr[0] = 0x701fe01a; /* 64KB L1 dcache */
679
+ cpu->ccsidr[1] = 0x201fe01a; /* 64KB L1 icache */
680
+ cpu->ccsidr[2] = 0x70ffe03a; /* 1MB L2 cache */
681
+
682
+ /* From B2.98 SCTLR_EL3 */
683
+ cpu->reset_sctlr = 0x30c50838;
684
+
685
+ /* From B4.23 ICH_VTR_EL2 */
686
+ cpu->gic_num_lrs = 4;
687
+ cpu->gic_vpribits = 5;
688
+ cpu->gic_vprebits = 5;
689
+ cpu->gic_pribits = 5;
690
+
691
+ /* From B5.1 AdvSIMD AArch64 register summary */
692
+ cpu->isar.mvfr0 = 0x10110222;
693
+ cpu->isar.mvfr1 = 0x13211111;
694
+ cpu->isar.mvfr2 = 0x00000043;
695
+
696
+ /* From D5.1 AArch64 PMU register summary */
697
+ cpu->isar.reset_pmcr_el0 = 0x410c3000;
698
+}
699
+
700
static void aarch64_host_initfn(Object *obj)
701
{
64
{
702
#if defined(CONFIG_KVM)
65
time_t seconds;
703
@@ -XXX,XX +XXX,XX @@ static void aarch64_max_initfn(Object *obj)
66
704
qdev_property_add_static(DEVICE(obj), &arm_cpu_lpa2_property);
705
}
706
707
-static void aarch64_a64fx_initfn(Object *obj)
708
-{
709
- ARMCPU *cpu = ARM_CPU(obj);
710
-
711
- cpu->dtb_compatible = "arm,a64fx";
712
- set_feature(&cpu->env, ARM_FEATURE_V8);
713
- set_feature(&cpu->env, ARM_FEATURE_NEON);
714
- set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
715
- set_feature(&cpu->env, ARM_FEATURE_AARCH64);
716
- set_feature(&cpu->env, ARM_FEATURE_EL2);
717
- set_feature(&cpu->env, ARM_FEATURE_EL3);
718
- set_feature(&cpu->env, ARM_FEATURE_PMU);
719
- cpu->midr = 0x461f0010;
720
- cpu->revidr = 0x00000000;
721
- cpu->ctr = 0x86668006;
722
- cpu->reset_sctlr = 0x30000180;
723
- cpu->isar.id_aa64pfr0 = 0x0000000101111111; /* No RAS Extensions */
724
- cpu->isar.id_aa64pfr1 = 0x0000000000000000;
725
- cpu->isar.id_aa64dfr0 = 0x0000000010305408;
726
- cpu->isar.id_aa64dfr1 = 0x0000000000000000;
727
- cpu->id_aa64afr0 = 0x0000000000000000;
728
- cpu->id_aa64afr1 = 0x0000000000000000;
729
- cpu->isar.id_aa64mmfr0 = 0x0000000000001122;
730
- cpu->isar.id_aa64mmfr1 = 0x0000000011212100;
731
- cpu->isar.id_aa64mmfr2 = 0x0000000000001011;
732
- cpu->isar.id_aa64isar0 = 0x0000000010211120;
733
- cpu->isar.id_aa64isar1 = 0x0000000000010001;
734
- cpu->isar.id_aa64zfr0 = 0x0000000000000000;
735
- cpu->clidr = 0x0000000080000023;
736
- cpu->ccsidr[0] = 0x7007e01c; /* 64KB L1 dcache */
737
- cpu->ccsidr[1] = 0x2007e01c; /* 64KB L1 icache */
738
- cpu->ccsidr[2] = 0x70ffe07c; /* 8MB L2 cache */
739
- cpu->dcz_blocksize = 6; /* 256 bytes */
740
- cpu->gic_num_lrs = 4;
741
- cpu->gic_vpribits = 5;
742
- cpu->gic_vprebits = 5;
743
- cpu->gic_pribits = 5;
744
-
745
- /* The A64FX supports only 128, 256 and 512 bit vector lengths */
746
- aarch64_add_sve_properties(obj);
747
- cpu->sve_vq.supported = (1 << 0) /* 128bit */
748
- | (1 << 1) /* 256bit */
749
- | (1 << 3); /* 512bit */
750
-
751
- cpu->isar.reset_pmcr_el0 = 0x46014040;
752
-
753
- /* TODO: Add A64FX specific HPC extension registers */
754
-}
755
-
756
static const ARMCPUInfo aarch64_cpus[] = {
757
{ .name = "cortex-a35", .initfn = aarch64_a35_initfn },
758
{ .name = "cortex-a57", .initfn = aarch64_a57_initfn },
759
--
67
--
760
2.25.1
68
2.34.1
761
69
762
70
diff view generated by jsdifflib
New patch
[PULL 22/24] target/arm: Do all "ARM_FEATURE_X implies Y" checks in post_init
1
1
Where architecturally one ARM_FEATURE_X flag implies another
2
ARM_FEATURE_Y, we allow the CPU init function to only set X, and then
3
set Y for it. Currently we do this in two places -- we set a few
4
flags in arm_cpu_post_init() because we need them to decide which
5
properties to create on the CPU object, and then we do the rest in
6
arm_cpu_realizefn(). However, this is fragile, because it's easy to
7
add a new property and not notice that this means that an X-implies-Y
8
check now has to move from realize to post-init.
9
10
As a specific example, the pmsav7-dregion property is conditional
11
on ARM_FEATURE_PMSA && ARM_FEATURE_V7, which means it won't appear
12
on the Cortex-M33 and -M55, because they set ARM_FEATURE_V8 and
13
rely on V8-implies-V7, which doesn't happen until the realizefn.
14
15
Move all of these X-implies-Y checks into a new function, which
16
we call at the top of arm_cpu_post_init(), so the feature bits
17
are available at that point.
18
19
This does now give us the reverse issue, that if there's a feature
20
bit which is enabled or disabled by the setting of a property then
21
then X-implies-Y features that are dependent on that property need to
22
be in realize, not in this new function. But the only one of those
23
is the "EL3 implies VBAR" which is already in the right place, so
24
putting things this way round seems better to me.
25
26
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
27
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
28
Message-id: 20230724174335.2150499-2-peter.maydell@linaro.org
29
---
30
target/arm/cpu.c | 179 +++++++++++++++++++++++++----------------------
31
1 file changed, 97 insertions(+), 82 deletions(-)
32
33
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
34
index XXXXXXX..XXXXXXX 100644
35
--- a/target/arm/cpu.c
36
+++ b/target/arm/cpu.c
37
@@ -XXX,XX +XXX,XX @@ unsigned int gt_cntfrq_period_ns(ARMCPU *cpu)
38
NANOSECONDS_PER_SECOND / cpu->gt_cntfrq_hz : 1;
39
}
40
41
+static void arm_cpu_propagate_feature_implications(ARMCPU *cpu)
42
+{
43
+ CPUARMState *env = &cpu->env;
44
+ bool no_aa32 = false;
45
+
46
+ /*
47
+ * Some features automatically imply others: set the feature
48
+ * bits explicitly for these cases.
49
+ */
50
+
51
+ if (arm_feature(env, ARM_FEATURE_M)) {
52
+ set_feature(env, ARM_FEATURE_PMSA);
53
+ }
54
+
55
+ if (arm_feature(env, ARM_FEATURE_V8)) {
56
+ if (arm_feature(env, ARM_FEATURE_M)) {
57
+ set_feature(env, ARM_FEATURE_V7);
58
+ } else {
59
+ set_feature(env, ARM_FEATURE_V7VE);
60
+ }
61
+ }
62
+
63
+ /*
64
+ * There exist AArch64 cpus without AArch32 support. When KVM
65
+ * queries ID_ISAR0_EL1 on such a host, the value is UNKNOWN.
66
+ * Similarly, we cannot check ID_AA64PFR0 without AArch64 support.
67
+ * As a general principle, we also do not make ID register
68
+ * consistency checks anywhere unless using TCG, because only
69
+ * for TCG would a consistency-check failure be a QEMU bug.
70
+ */
71
+ if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) {
72
+ no_aa32 = !cpu_isar_feature(aa64_aa32, cpu);
73
+ }
74
+
75
+ if (arm_feature(env, ARM_FEATURE_V7VE)) {
76
+ /*
77
+ * v7 Virtualization Extensions. In real hardware this implies
78
+ * EL2 and also the presence of the Security Extensions.
79
+ * For QEMU, for backwards-compatibility we implement some
80
+ * CPUs or CPU configs which have no actual EL2 or EL3 but do
81
+ * include the various other features that V7VE implies.
82
+ * Presence of EL2 itself is ARM_FEATURE_EL2, and of the
83
+ * Security Extensions is ARM_FEATURE_EL3.
84
+ */
85
+ assert(!tcg_enabled() || no_aa32 ||
86
+ cpu_isar_feature(aa32_arm_div, cpu));
87
+ set_feature(env, ARM_FEATURE_LPAE);
88
+ set_feature(env, ARM_FEATURE_V7);
89
+ }
90
+ if (arm_feature(env, ARM_FEATURE_V7)) {
91
+ set_feature(env, ARM_FEATURE_VAPA);
92
+ set_feature(env, ARM_FEATURE_THUMB2);
93
+ set_feature(env, ARM_FEATURE_MPIDR);
94
+ if (!arm_feature(env, ARM_FEATURE_M)) {
95
+ set_feature(env, ARM_FEATURE_V6K);
96
+ } else {
97
+ set_feature(env, ARM_FEATURE_V6);
98
+ }
99
+
100
+ /*
101
+ * Always define VBAR for V7 CPUs even if it doesn't exist in
102
+ * non-EL3 configs. This is needed by some legacy boards.
103
+ */
104
+ set_feature(env, ARM_FEATURE_VBAR);
105
+ }
106
+ if (arm_feature(env, ARM_FEATURE_V6K)) {
107
+ set_feature(env, ARM_FEATURE_V6);
108
+ set_feature(env, ARM_FEATURE_MVFR);
109
+ }
110
+ if (arm_feature(env, ARM_FEATURE_V6)) {
111
+ set_feature(env, ARM_FEATURE_V5);
112
+ if (!arm_feature(env, ARM_FEATURE_M)) {
113
+ assert(!tcg_enabled() || no_aa32 ||
114
+ cpu_isar_feature(aa32_jazelle, cpu));
115
+ set_feature(env, ARM_FEATURE_AUXCR);
116
+ }
117
+ }
118
+ if (arm_feature(env, ARM_FEATURE_V5)) {
119
+ set_feature(env, ARM_FEATURE_V4T);
120
+ }
121
+ if (arm_feature(env, ARM_FEATURE_LPAE)) {
122
+ set_feature(env, ARM_FEATURE_V7MP);
123
+ }
124
+ if (arm_feature(env, ARM_FEATURE_CBAR_RO)) {
125
+ set_feature(env, ARM_FEATURE_CBAR);
126
+ }
127
+ if (arm_feature(env, ARM_FEATURE_THUMB2) &&
128
+ !arm_feature(env, ARM_FEATURE_M)) {
129
+ set_feature(env, ARM_FEATURE_THUMB_DSP);
130
+ }
131
+}
132
+
133
void arm_cpu_post_init(Object *obj)
134
{
135
ARMCPU *cpu = ARM_CPU(obj);
136
137
- /* M profile implies PMSA. We have to do this here rather than
138
- * in realize with the other feature-implication checks because
139
- * we look at the PMSA bit to see if we should add some properties.
140
+ /*
141
+ * Some features imply others. Figure this out now, because we
142
+ * are going to look at the feature bits in deciding which
143
+ * properties to add.
144
*/
145
- if (arm_feature(&cpu->env, ARM_FEATURE_M)) {
146
- set_feature(&cpu->env, ARM_FEATURE_PMSA);
147
- }
148
+ arm_cpu_propagate_feature_implications(cpu);
149
150
if (arm_feature(&cpu->env, ARM_FEATURE_CBAR) ||
151
arm_feature(&cpu->env, ARM_FEATURE_CBAR_RO)) {
152
@@ -XXX,XX +XXX,XX @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp)
153
CPUARMState *env = &cpu->env;
154
int pagebits;
155
Error *local_err = NULL;
156
- bool no_aa32 = false;
157
158
/* Use pc-relative instructions in system-mode */
159
#ifndef CONFIG_USER_ONLY
160
@@ -XXX,XX +XXX,XX @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp)
161
cpu->isar.id_isar3 = u;
162
}
163
164
- /* Some features automatically imply others: */
165
- if (arm_feature(env, ARM_FEATURE_V8)) {
166
- if (arm_feature(env, ARM_FEATURE_M)) {
167
- set_feature(env, ARM_FEATURE_V7);
168
- } else {
169
- set_feature(env, ARM_FEATURE_V7VE);
170
- }
171
- }
172
-
173
- /*
174
- * There exist AArch64 cpus without AArch32 support. When KVM
175
- * queries ID_ISAR0_EL1 on such a host, the value is UNKNOWN.
176
- * Similarly, we cannot check ID_AA64PFR0 without AArch64 support.
177
- * As a general principle, we also do not make ID register
178
- * consistency checks anywhere unless using TCG, because only
179
- * for TCG would a consistency-check failure be a QEMU bug.
180
- */
181
- if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) {
182
- no_aa32 = !cpu_isar_feature(aa64_aa32, cpu);
183
- }
184
-
185
- if (arm_feature(env, ARM_FEATURE_V7VE)) {
186
- /* v7 Virtualization Extensions. In real hardware this implies
187
- * EL2 and also the presence of the Security Extensions.
188
- * For QEMU, for backwards-compatibility we implement some
189
- * CPUs or CPU configs which have no actual EL2 or EL3 but do
190
- * include the various other features that V7VE implies.
191
- * Presence of EL2 itself is ARM_FEATURE_EL2, and of the
192
- * Security Extensions is ARM_FEATURE_EL3.
193
- */
194
- assert(!tcg_enabled() || no_aa32 ||
195
- cpu_isar_feature(aa32_arm_div, cpu));
196
- set_feature(env, ARM_FEATURE_LPAE);
197
- set_feature(env, ARM_FEATURE_V7);
198
- }
199
- if (arm_feature(env, ARM_FEATURE_V7)) {
200
- set_feature(env, ARM_FEATURE_VAPA);
201
- set_feature(env, ARM_FEATURE_THUMB2);
202
- set_feature(env, ARM_FEATURE_MPIDR);
203
- if (!arm_feature(env, ARM_FEATURE_M)) {
204
- set_feature(env, ARM_FEATURE_V6K);
205
- } else {
206
- set_feature(env, ARM_FEATURE_V6);
207
- }
208
-
209
- /* Always define VBAR for V7 CPUs even if it doesn't exist in
210
- * non-EL3 configs. This is needed by some legacy boards.
211
- */
212
- set_feature(env, ARM_FEATURE_VBAR);
213
- }
214
- if (arm_feature(env, ARM_FEATURE_V6K)) {
215
- set_feature(env, ARM_FEATURE_V6);
216
- set_feature(env, ARM_FEATURE_MVFR);
217
- }
218
- if (arm_feature(env, ARM_FEATURE_V6)) {
219
- set_feature(env, ARM_FEATURE_V5);
220
- if (!arm_feature(env, ARM_FEATURE_M)) {
221
- assert(!tcg_enabled() || no_aa32 ||
222
- cpu_isar_feature(aa32_jazelle, cpu));
223
- set_feature(env, ARM_FEATURE_AUXCR);
224
- }
225
- }
226
- if (arm_feature(env, ARM_FEATURE_V5)) {
227
- set_feature(env, ARM_FEATURE_V4T);
228
- }
229
- if (arm_feature(env, ARM_FEATURE_LPAE)) {
230
- set_feature(env, ARM_FEATURE_V7MP);
231
- }
232
- if (arm_feature(env, ARM_FEATURE_CBAR_RO)) {
233
- set_feature(env, ARM_FEATURE_CBAR);
234
- }
235
- if (arm_feature(env, ARM_FEATURE_THUMB2) &&
236
- !arm_feature(env, ARM_FEATURE_M)) {
237
- set_feature(env, ARM_FEATURE_THUMB_DSP);
238
- }
239
240
/*
241
* We rely on no XScale CPU having VFP so we can use the same bits in the
242
--
243
2.34.1
diff view generated by jsdifflib
New patch
[PULL 23/24] hw/arm/armv7m: Add mpu-ns-regions and mpu-s-regions properties
1
M-profile CPUs generally allow configuration of the number of MPU
2
regions that they have. We don't currently model this, so our
3
implementations of some of the board models provide CPUs with the
4
wrong number of regions. RTOSes like Zephyr that hardcode the
5
expected number of regions may therefore not run on the model if they
6
are set up to run on real hardware.
1
7
8
Add properties mpu-ns-regions and mpu-s-regions to the ARMV7M object,
9
matching the ability of hardware to configure the number of Secure
10
and NonSecure regions separately. Our actual CPU implementation
11
doesn't currently support that, and it happens that none of the MPS
12
boards we model set the number of regions differently for Secure vs
13
NonSecure, so we provide an interface to the boards and SoCs that
14
won't need to change if we ever do add that functionality in future,
15
but make it an error to configure the two properties to different
16
values.
17
18
(The property name on the CPU is the somewhat misnamed-for-M-profile
19
"pmsav7-dregion", so we don't follow that naming convention for
20
the properties here. The TRM doesn't say what the CPU configuration
21
variable names are, so we pick something, and follow the lowercase
22
convention we already have for properties here.)
23
24
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
25
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
26
Message-id: 20230724174335.2150499-3-peter.maydell@linaro.org
27
---
28
include/hw/arm/armv7m.h | 8 ++++++++
29
hw/arm/armv7m.c | 21 +++++++++++++++++++++
30
2 files changed, 29 insertions(+)
31
32
diff --git a/include/hw/arm/armv7m.h b/include/hw/arm/armv7m.h
33
index XXXXXXX..XXXXXXX 100644
34
--- a/include/hw/arm/armv7m.h
35
+++ b/include/hw/arm/armv7m.h
36
@@ -XXX,XX +XXX,XX @@ OBJECT_DECLARE_SIMPLE_TYPE(ARMv7MState, ARMV7M)
37
* + Property "vfp": enable VFP (forwarded to CPU object)
38
* + Property "dsp": enable DSP (forwarded to CPU object)
39
* + Property "enable-bitband": expose bitbanded IO
40
+ * + Property "mpu-ns-regions": number of Non-Secure MPU regions (forwarded
41
+ * to CPU object pmsav7-dregion property; default is whatever the default
42
+ * for the CPU is)
43
+ * + Property "mpu-s-regions": number of Secure MPU regions (default is
44
+ * whatever the default for the CPU is; must currently be set to the same
45
+ * value as mpu-ns-regions if the CPU implements the Security Extension)
46
* + Clock input "refclk" is the external reference clock for the systick timers
47
* + Clock input "cpuclk" is the main CPU clock
48
*/
49
@@ -XXX,XX +XXX,XX @@ struct ARMv7MState {
50
Object *idau;
51
uint32_t init_svtor;
52
uint32_t init_nsvtor;
53
+ uint32_t mpu_ns_regions;
54
+ uint32_t mpu_s_regions;
55
bool enable_bitband;
56
bool start_powered_off;
57
bool vfp;
58
diff --git a/hw/arm/armv7m.c b/hw/arm/armv7m.c
59
index XXXXXXX..XXXXXXX 100644
60
--- a/hw/arm/armv7m.c
61
+++ b/hw/arm/armv7m.c
62
@@ -XXX,XX +XXX,XX @@ static void armv7m_realize(DeviceState *dev, Error **errp)
63
}
64
}
65
66
+ /*
67
+ * Real M-profile hardware can be configured with a different number of
68
+ * MPU regions for Secure vs NonSecure. QEMU's CPU implementation doesn't
69
+ * support that yet, so catch attempts to select that.
70
+ */
71
+ if (arm_feature(&s->cpu->env, ARM_FEATURE_M_SECURITY) &&
72
+ s->mpu_ns_regions != s->mpu_s_regions) {
73
+ error_setg(errp,
74
+ "mpu-ns-regions and mpu-s-regions properties must have the same value");
75
+ return;
76
+ }
77
+ if (s->mpu_ns_regions != UINT_MAX &&
78
+ object_property_find(OBJECT(s->cpu), "pmsav7-dregion")) {
79
+ if (!object_property_set_uint(OBJECT(s->cpu), "pmsav7-dregion",
80
+ s->mpu_ns_regions, errp)) {
81
+ return;
82
+ }
83
+ }
84
+
85
/*
86
* Tell the CPU where the NVIC is; it will fail realize if it doesn't
87
* have one. Similarly, tell the NVIC where its CPU is.
88
@@ -XXX,XX +XXX,XX @@ static Property armv7m_properties[] = {
89
false),
90
DEFINE_PROP_BOOL("vfp", ARMv7MState, vfp, true),
91
DEFINE_PROP_BOOL("dsp", ARMv7MState, dsp, true),
92
+ DEFINE_PROP_UINT32("mpu-ns-regions", ARMv7MState, mpu_ns_regions, UINT_MAX),
93
+ DEFINE_PROP_UINT32("mpu-s-regions", ARMv7MState, mpu_s_regions, UINT_MAX),
94
DEFINE_PROP_END_OF_LIST(),
95
};
96
97
--
98
2.34.1
99
100
diff view generated by jsdifflib
[PULL 01/10] target/arm: Mark registers which call pmu_op_start() as ARM_CP_IO
[PULL 24/24] hw/arm: Set number of MPU regions correctly for an505, an521, an524
1
In commit 01765386a888 we made some system register write functions
1
The IoTKit, SSE200 and SSE300 all default to 8 MPU regions. The
2
call pmu_op_start()/pmu_op_finish(). This means that they now touch
2
MPS2/MPS3 FPGA images don't override these except in the case of
3
timers, so for icount to work these registers must have the ARM_CP_IO
3
AN547, which uses 16 MPU regions.
4
flag set.
4
5
5
Define properties on the ARMSSE object for the MPU regions (using the
6
This fixes a bug where when icount is enabled a guest that touches
6
same names as the documented RTL configuration settings, and
7
MDCR_EL3, MDCR_EL2, PMCNTENSET_EL0 or PMCNTENCLR_EL0 would cause
7
following the pattern we already have for this device of using
8
QEMU to print an error message and exit, for example:
8
all-caps names as the RTL does), and set them in the board code.
9
9
10
[ 2.495971] TCP: Hash tables configured (established 1024 bind 1024)
10
We don't actually need to override the default except on AN547,
11
[ 2.496213] UDP hash table entries: 256 (order: 1, 8192 bytes)
11
but it's simpler code to have the board code set them always
12
[ 2.496386] UDP-Lite hash table entries: 256 (order: 1, 8192 bytes)
12
rather than tracking which board subtypes want to set them to
13
[ 2.496917] NET: Registered protocol family 1
13
a non-default value separately from what that value is.
14
qemu-system-aarch64: Bad icount read
14
15
15
Tho overall effect is that for mps2-an505, mps2-an521 and mps3-an524
16
Reported-by: Thomas Huth <thuth@redhat.com>
16
we now correctly use 8 MPU regions, while mps3-an547 stays at its
17
current 16 regions.
18
19
It's possible some guest code wrongly depended on the previous
20
incorrectly modeled number of memory regions. (Such guest code
21
should ideally check the number of regions via the MPU_TYPE
22
register.) The old behaviour can be obtained with additional
23
-global arguments to QEMU:
24
25
For mps2-an521 and mps2-an524:
26
-global sse-200.CPU0_MPU_NS=16 -global sse-200.CPU0_MPU_S=16 -global sse-200.CPU1_MPU_NS=16 -global sse-200.CPU1_MPU_S=16
27
28
For mps2-an505:
29
-global sse-200.CPU0_MPU_NS=16 -global sse-200.CPU0_MPU_S=16
30
31
NB that the way the implementation allows this use of -global
32
is slightly fragile: if the board code explicitly sets the
33
properties on the sse-200 object, this overrides the -global
34
command line option. So we rely on:
35
- the boards that need fixing all happen to use the SSE defaults
36
- we can write the board code to only set the property if it
37
is different from the default, rather than having all boards
38
explicitly set the property
39
- the board that does need to use a non-default value happens
40
to need to set it to the same value (16) we previously used
41
This works, but there are some kinds of refactoring of the
42
mps2-tz.c code that would break the support for -global here.
43
44
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1772
17
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
45
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
18
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
46
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
19
Message-id: 20220923123412.1214041-2-peter.maydell@linaro.org
47
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
48
Message-id: 20230724174335.2150499-4-peter.maydell@linaro.org
20
---
49
---
21
target/arm/helper.c | 12 ++++++------
50
include/hw/arm/armsse.h | 5 +++++
22
1 file changed, 6 insertions(+), 6 deletions(-)
51
hw/arm/armsse.c | 16 ++++++++++++++++
23
52
hw/arm/mps2-tz.c | 29 +++++++++++++++++++++++++++++
24
diff --git a/target/arm/helper.c b/target/arm/helper.c
53
3 files changed, 50 insertions(+)
54
55
diff --git a/include/hw/arm/armsse.h b/include/hw/arm/armsse.h
25
index XXXXXXX..XXXXXXX 100644
56
index XXXXXXX..XXXXXXX 100644
26
--- a/target/arm/helper.c
57
--- a/include/hw/arm/armsse.h
27
+++ b/target/arm/helper.c
58
+++ b/include/hw/arm/armsse.h
28
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo v7_cp_reginfo[] = {
59
@@ -XXX,XX +XXX,XX @@
29
* or PL0_RO as appropriate and then check PMUSERENR in the helper fn.
60
* (matching the hardware) is that for CPU0 in an IoTKit and CPU1 in an
30
*/
61
* SSE-200 both are present; CPU0 in an SSE-200 has neither.
31
{ .name = "PMCNTENSET", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 1,
62
* Since the IoTKit has only one CPU, it does not have the CPU1_* properties.
32
- .access = PL0_RW, .type = ARM_CP_ALIAS,
63
+ * + QOM properties "CPU0_MPU_NS", "CPU0_MPU_S", "CPU1_MPU_NS" and "CPU1_MPU_S"
33
+ .access = PL0_RW, .type = ARM_CP_ALIAS | ARM_CP_IO,
64
+ * which set the number of MPU regions on the CPUs. If there is only one
34
.fieldoffset = offsetoflow32(CPUARMState, cp15.c9_pmcnten),
65
+ * CPU the CPU1 properties are not present.
35
.writefn = pmcntenset_write,
66
* + Named GPIO inputs "EXP_IRQ" 0..n are the expansion interrupts for CPU 0,
36
.accessfn = pmreg_access,
67
* which are wired to its NVIC lines 32 .. n+32
37
.raw_writefn = raw_write },
68
* + Named GPIO inputs "EXP_CPU1_IRQ" 0..n are the expansion interrupts for
38
- { .name = "PMCNTENSET_EL0", .state = ARM_CP_STATE_AA64,
69
@@ -XXX,XX +XXX,XX @@ struct ARMSSE {
39
+ { .name = "PMCNTENSET_EL0", .state = ARM_CP_STATE_AA64, .type = ARM_CP_IO,
70
uint32_t exp_numirq;
40
.opc0 = 3, .opc1 = 3, .crn = 9, .crm = 12, .opc2 = 1,
71
uint32_t sram_addr_width;
41
.access = PL0_RW, .accessfn = pmreg_access,
72
uint32_t init_svtor;
42
.fieldoffset = offsetof(CPUARMState, cp15.c9_pmcnten), .resetvalue = 0,
73
+ uint32_t cpu_mpu_ns[SSE_MAX_CPUS];
43
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo v7_cp_reginfo[] = {
74
+ uint32_t cpu_mpu_s[SSE_MAX_CPUS];
44
.fieldoffset = offsetoflow32(CPUARMState, cp15.c9_pmcnten),
75
bool cpu_fpu[SSE_MAX_CPUS];
45
.accessfn = pmreg_access,
76
bool cpu_dsp[SSE_MAX_CPUS];
46
.writefn = pmcntenclr_write,
77
};
47
- .type = ARM_CP_ALIAS },
78
diff --git a/hw/arm/armsse.c b/hw/arm/armsse.c
48
+ .type = ARM_CP_ALIAS | ARM_CP_IO },
79
index XXXXXXX..XXXXXXX 100644
49
{ .name = "PMCNTENCLR_EL0", .state = ARM_CP_STATE_AA64,
80
--- a/hw/arm/armsse.c
50
.opc0 = 3, .opc1 = 3, .crn = 9, .crm = 12, .opc2 = 2,
81
+++ b/hw/arm/armsse.c
51
.access = PL0_RW, .accessfn = pmreg_access,
82
@@ -XXX,XX +XXX,XX @@ static Property iotkit_properties[] = {
52
- .type = ARM_CP_ALIAS,
83
DEFINE_PROP_UINT32("init-svtor", ARMSSE, init_svtor, 0x10000000),
53
+ .type = ARM_CP_ALIAS | ARM_CP_IO,
84
DEFINE_PROP_BOOL("CPU0_FPU", ARMSSE, cpu_fpu[0], true),
54
.fieldoffset = offsetof(CPUARMState, cp15.c9_pmcnten),
85
DEFINE_PROP_BOOL("CPU0_DSP", ARMSSE, cpu_dsp[0], true),
55
.writefn = pmcntenclr_write },
86
+ DEFINE_PROP_UINT32("CPU0_MPU_NS", ARMSSE, cpu_mpu_ns[0], 8),
56
{ .name = "PMOVSR", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 3,
87
+ DEFINE_PROP_UINT32("CPU0_MPU_S", ARMSSE, cpu_mpu_s[0], 8),
57
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo v8_cp_reginfo[] = {
88
DEFINE_PROP_END_OF_LIST()
58
.opc0 = 3, .opc1 = 6, .crn = 1, .crm = 3, .opc2 = 1,
89
};
59
.resetvalue = 0,
90
60
.access = PL3_RW, .fieldoffset = offsetof(CPUARMState, cp15.mdcr_el3) },
91
@@ -XXX,XX +XXX,XX @@ static Property sse200_properties[] = {
61
- { .name = "SDCR", .type = ARM_CP_ALIAS,
92
DEFINE_PROP_BOOL("CPU0_DSP", ARMSSE, cpu_dsp[0], false),
62
+ { .name = "SDCR", .type = ARM_CP_ALIAS | ARM_CP_IO,
93
DEFINE_PROP_BOOL("CPU1_FPU", ARMSSE, cpu_fpu[1], true),
63
.cp = 15, .opc1 = 0, .crn = 1, .crm = 3, .opc2 = 1,
94
DEFINE_PROP_BOOL("CPU1_DSP", ARMSSE, cpu_dsp[1], true),
64
.access = PL1_RW, .accessfn = access_trap_aa32s_el1,
95
+ DEFINE_PROP_UINT32("CPU0_MPU_NS", ARMSSE, cpu_mpu_ns[0], 8),
65
.writefn = sdcr_write,
96
+ DEFINE_PROP_UINT32("CPU0_MPU_S", ARMSSE, cpu_mpu_s[0], 8),
66
@@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu)
97
+ DEFINE_PROP_UINT32("CPU1_MPU_NS", ARMSSE, cpu_mpu_ns[1], 8),
67
* value is MDCR_EL2.HPMN which should reset to the value of PMCR_EL0.N.
98
+ DEFINE_PROP_UINT32("CPU1_MPU_S", ARMSSE, cpu_mpu_s[1], 8),
68
*/
99
DEFINE_PROP_END_OF_LIST()
69
ARMCPRegInfo mdcr_el2 = {
100
};
70
- .name = "MDCR_EL2", .state = ARM_CP_STATE_BOTH,
101
71
+ .name = "MDCR_EL2", .state = ARM_CP_STATE_BOTH, .type = ARM_CP_IO,
102
@@ -XXX,XX +XXX,XX @@ static Property sse300_properties[] = {
72
.opc0 = 3, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 1,
103
DEFINE_PROP_UINT32("init-svtor", ARMSSE, init_svtor, 0x10000000),
73
.writefn = mdcr_el2_write,
104
DEFINE_PROP_BOOL("CPU0_FPU", ARMSSE, cpu_fpu[0], true),
74
.access = PL2_RW, .resetvalue = pmu_num_counters(env),
105
DEFINE_PROP_BOOL("CPU0_DSP", ARMSSE, cpu_dsp[0], true),
106
+ DEFINE_PROP_UINT32("CPU0_MPU_NS", ARMSSE, cpu_mpu_ns[0], 8),
107
+ DEFINE_PROP_UINT32("CPU0_MPU_S", ARMSSE, cpu_mpu_s[0], 8),
108
DEFINE_PROP_END_OF_LIST()
109
};
110
111
@@ -XXX,XX +XXX,XX @@ static void armsse_realize(DeviceState *dev, Error **errp)
112
return;
113
}
114
}
115
+ if (!object_property_set_uint(cpuobj, "mpu-ns-regions",
116
+ s->cpu_mpu_ns[i], errp)) {
117
+ return;
118
+ }
119
+ if (!object_property_set_uint(cpuobj, "mpu-s-regions",
120
+ s->cpu_mpu_s[i], errp)) {
121
+ return;
122
+ }
123
124
if (i > 0) {
125
memory_region_add_subregion_overlap(&s->cpu_container[i], 0,
126
diff --git a/hw/arm/mps2-tz.c b/hw/arm/mps2-tz.c
127
index XXXXXXX..XXXXXXX 100644
128
--- a/hw/arm/mps2-tz.c
129
+++ b/hw/arm/mps2-tz.c
130
@@ -XXX,XX +XXX,XX @@ struct MPS2TZMachineClass {
131
int uart_overflow_irq; /* number of the combined UART overflow IRQ */
132
uint32_t init_svtor; /* init-svtor setting for SSE */
133
uint32_t sram_addr_width; /* SRAM_ADDR_WIDTH setting for SSE */
134
+ uint32_t cpu0_mpu_ns; /* CPU0_MPU_NS setting for SSE */
135
+ uint32_t cpu0_mpu_s; /* CPU0_MPU_S setting for SSE */
136
+ uint32_t cpu1_mpu_ns; /* CPU1_MPU_NS setting for SSE */
137
+ uint32_t cpu1_mpu_s; /* CPU1_MPU_S setting for SSE */
138
const RAMInfo *raminfo;
139
const char *armsse_type;
140
uint32_t boot_ram_size; /* size of ram at address 0; 0 == find in raminfo */
141
@@ -XXX,XX +XXX,XX @@ OBJECT_DECLARE_TYPE(MPS2TZMachineState, MPS2TZMachineClass, MPS2TZ_MACHINE)
142
#define MPS3_DDR_SIZE (2 * GiB)
143
#endif
144
145
+/* For cpu{0,1}_mpu_{ns,s}, means "leave at SSE's default value" */
146
+#define MPU_REGION_DEFAULT UINT32_MAX
147
+
148
static const uint32_t an505_oscclk[] = {
149
40000000,
150
24580000,
151
@@ -XXX,XX +XXX,XX @@ static void mps2tz_common_init(MachineState *machine)
152
OBJECT(system_memory), &error_abort);
153
qdev_prop_set_uint32(iotkitdev, "EXP_NUMIRQ", mmc->numirq);
154
qdev_prop_set_uint32(iotkitdev, "init-svtor", mmc->init_svtor);
155
+ if (mmc->cpu0_mpu_ns != MPU_REGION_DEFAULT) {
156
+ qdev_prop_set_uint32(iotkitdev, "CPU0_MPU_NS", mmc->cpu0_mpu_ns);
157
+ }
158
+ if (mmc->cpu0_mpu_s != MPU_REGION_DEFAULT) {
159
+ qdev_prop_set_uint32(iotkitdev, "CPU0_MPU_S", mmc->cpu0_mpu_s);
160
+ }
161
+ if (object_property_find(OBJECT(iotkitdev), "CPU1_MPU_NS")) {
162
+ if (mmc->cpu1_mpu_ns != MPU_REGION_DEFAULT) {
163
+ qdev_prop_set_uint32(iotkitdev, "CPU1_MPU_NS", mmc->cpu1_mpu_ns);
164
+ }
165
+ if (mmc->cpu1_mpu_s != MPU_REGION_DEFAULT) {
166
+ qdev_prop_set_uint32(iotkitdev, "CPU1_MPU_S", mmc->cpu1_mpu_s);
167
+ }
168
+ }
169
qdev_prop_set_uint32(iotkitdev, "SRAM_ADDR_WIDTH", mmc->sram_addr_width);
170
qdev_connect_clock_in(iotkitdev, "MAINCLK", mms->sysclk);
171
qdev_connect_clock_in(iotkitdev, "S32KCLK", mms->s32kclk);
172
@@ -XXX,XX +XXX,XX @@ static void mps2tz_class_init(ObjectClass *oc, void *data)
173
{
174
MachineClass *mc = MACHINE_CLASS(oc);
175
IDAUInterfaceClass *iic = IDAU_INTERFACE_CLASS(oc);
176
+ MPS2TZMachineClass *mmc = MPS2TZ_MACHINE_CLASS(oc);
177
178
mc->init = mps2tz_common_init;
179
mc->reset = mps2_machine_reset;
180
iic->check = mps2_tz_idau_check;
181
+
182
+ /* Most machines leave these at the SSE defaults */
183
+ mmc->cpu0_mpu_ns = MPU_REGION_DEFAULT;
184
+ mmc->cpu0_mpu_s = MPU_REGION_DEFAULT;
185
+ mmc->cpu1_mpu_ns = MPU_REGION_DEFAULT;
186
+ mmc->cpu1_mpu_s = MPU_REGION_DEFAULT;
187
}
188
189
static void mps2tz_set_default_ram_info(MPS2TZMachineClass *mmc)
190
@@ -XXX,XX +XXX,XX @@ static void mps3tz_an547_class_init(ObjectClass *oc, void *data)
191
mmc->numirq = 96;
192
mmc->uart_overflow_irq = 48;
193
mmc->init_svtor = 0x00000000;
194
+ mmc->cpu0_mpu_s = mmc->cpu0_mpu_ns = 16;
195
mmc->sram_addr_width = 21;
196
mmc->raminfo = an547_raminfo;
197
mmc->armsse_type = TYPE_SSE300;
75
--
198
--
76
2.25.1
199
2.34.1
200
201
diff view generated by jsdifflib

Patchew 2.1-devel-b67e4c2

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