[PATCH] target/loongarch: Fix macros SET_FPU_* in cpu.h

Qi Hu posted 1 patch 1 week ago
Patches applied successfully (tree, apply log)
git fetch https://github.com/patchew-project/qemu tags/patchew/20220804132450.314329-1-huqi@loongson.cn
Maintainers: Song Gao <gaosong@loongson.cn>, Xiaojuan Yang <yangxiaojuan@loongson.cn>
target/loongarch/cpu.h | 18 +++++++++++++++---
1 file changed, 15 insertions(+), 3 deletions(-)
[PATCH] target/loongarch: Fix macros SET_FPU_* in cpu.h
Posted by Qi Hu 1 week ago
The macros SET_FPU_* are used to set corresponding bits of fcsr.
Unfortunately it forgets to set the result and it causes fcsr's
"CAUSE" never being updated. This patch is to fix this bug.

Signed-off-by: Qi Hu <huqi@loongson.cn>
---
 target/loongarch/cpu.h | 18 +++++++++++++++---
 1 file changed, 15 insertions(+), 3 deletions(-)

diff --git a/target/loongarch/cpu.h b/target/loongarch/cpu.h
index a36349df83..dce999aaac 100644
--- a/target/loongarch/cpu.h
+++ b/target/loongarch/cpu.h
@@ -47,11 +47,23 @@ FIELD(FCSR0, FLAGS, 16, 5)
 FIELD(FCSR0, CAUSE, 24, 5)
 
 #define GET_FP_CAUSE(REG)      FIELD_EX32(REG, FCSR0, CAUSE)
-#define SET_FP_CAUSE(REG, V)   FIELD_DP32(REG, FCSR0, CAUSE, V)
+#define SET_FP_CAUSE(REG, V) \
+    do { \
+        (REG) = FIELD_DP32(REG, FCSR0, CAUSE, V); \
+    } while (0)
+
 #define GET_FP_ENABLES(REG)    FIELD_EX32(REG, FCSR0, ENABLES)
-#define SET_FP_ENABLES(REG, V) FIELD_DP32(REG, FCSR0, ENABLES, V)
+#define SET_FP_ENABLES(REG, V) \
+    do { \
+        (REG) = FIELD_DP32(REG, FCSR0, ENABLES, V); \
+    } while (0)
+
 #define GET_FP_FLAGS(REG)      FIELD_EX32(REG, FCSR0, FLAGS)
-#define SET_FP_FLAGS(REG, V)   FIELD_DP32(REG, FCSR0, FLAGS, V)
+#define SET_FP_FLAGS(REG, V) \
+    do { \
+        (REG) = FIELD_DP32(REG, FCSR0, FLAGS, V); \
+    } while (0)
+
 #define UPDATE_FP_FLAGS(REG, V) \
     do { \
         (REG) |= FIELD_DP32(0, FCSR0, FLAGS, V); \
-- 
2.37.1
Re: [PATCH] target/loongarch: Fix macros SET_FPU_* in cpu.h
Posted by Richard Henderson 6 days, 8 hours ago
On 8/4/22 06:24, Qi Hu wrote:
> The macros SET_FPU_* are used to set corresponding bits of fcsr.
> Unfortunately it forgets to set the result and it causes fcsr's
> "CAUSE" never being updated. This patch is to fix this bug.
> 
> Signed-off-by: Qi Hu <huqi@loongson.cn>
> ---
>   target/loongarch/cpu.h | 18 +++++++++++++++---
>   1 file changed, 15 insertions(+), 3 deletions(-)

Thanks, queued.


r~
Re: [PATCH] target/loongarch: Fix macros SET_FPU_* in cpu.h
Posted by gaosong 6 days, 16 hours ago
Cc: Richard

Apply to 7.1?

On 2022/8/4 下午9:24, Qi Hu wrote:
> The macros SET_FPU_* are used to set corresponding bits of fcsr.
> Unfortunately it forgets to set the result and it causes fcsr's
> "CAUSE" never being updated. This patch is to fix this bug.
>
> Signed-off-by: Qi Hu <huqi@loongson.cn>
> ---
>   target/loongarch/cpu.h | 18 +++++++++++++++---
>   1 file changed, 15 insertions(+), 3 deletions(-)

Reviewed-by:  Song Gao <gaosong@loongson.cn>

> diff --git a/target/loongarch/cpu.h b/target/loongarch/cpu.h
> index a36349df83..dce999aaac 100644
> --- a/target/loongarch/cpu.h
> +++ b/target/loongarch/cpu.h
> @@ -47,11 +47,23 @@ FIELD(FCSR0, FLAGS, 16, 5)
>   FIELD(FCSR0, CAUSE, 24, 5)
>   
>   #define GET_FP_CAUSE(REG)      FIELD_EX32(REG, FCSR0, CAUSE)
> -#define SET_FP_CAUSE(REG, V)   FIELD_DP32(REG, FCSR0, CAUSE, V)
> +#define SET_FP_CAUSE(REG, V) \
> +    do { \
> +        (REG) = FIELD_DP32(REG, FCSR0, CAUSE, V); \
> +    } while (0)
> +
>   #define GET_FP_ENABLES(REG)    FIELD_EX32(REG, FCSR0, ENABLES)
> -#define SET_FP_ENABLES(REG, V) FIELD_DP32(REG, FCSR0, ENABLES, V)
> +#define SET_FP_ENABLES(REG, V) \
> +    do { \
> +        (REG) = FIELD_DP32(REG, FCSR0, ENABLES, V); \
> +    } while (0)
> +
>   #define GET_FP_FLAGS(REG)      FIELD_EX32(REG, FCSR0, FLAGS)
> -#define SET_FP_FLAGS(REG, V)   FIELD_DP32(REG, FCSR0, FLAGS, V)
> +#define SET_FP_FLAGS(REG, V) \
> +    do { \
> +        (REG) = FIELD_DP32(REG, FCSR0, FLAGS, V); \
> +    } while (0)
> +
>   #define UPDATE_FP_FLAGS(REG, V) \
>       do { \
>           (REG) |= FIELD_DP32(0, FCSR0, FLAGS, V); \