[PULL 0/3] target-arm queue
[Qemu-devel] [PULL v2 00/47] target-arm queue
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Only thing for Arm for rc1 is RTH's fix for the KVM SVE probe code.
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v2: dropped USHL/SSHL patch
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-- PMM
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The following changes since commit 785a602eae7ad97076b9794ebaba072ad4a9f74f:
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The following changes since commit 4e06b3fc1b5e1ec03f22190eabe56891dc9c2236:
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Merge remote-tracking branch 'remotes/kraxel/tags/vga-20190613-pull-request' into staging (2019-06-13 13:25:25 +0100)
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Merge tag 'pull-hex-20220731' of https://github.com/quic/qemu into staging (2022-07-31 21:38:54 -0700)
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are available in the Git repository at:
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are available in the Git repository at:
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https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20220801
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https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20190613-1
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for you to fetch changes up to 5265d24c981dfdda8d29b44f7e84a514da75eedc:
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for you to fetch changes up to 18cf951af9a27ae573a6fa17f9d0c103f7b7679b:
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target/arm: Move sve probe inside kvm >= 4.15 branch (2022-08-01 16:21:18 +0100)
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target/arm: Fix short-vector increment behaviour (2019-06-13 15:14:06 +0100)
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----------------------------------------------------------------
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----------------------------------------------------------------
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target-arm queue:
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target-arm queue:
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* Fix KVM SVE ID register probe code
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* convert aarch32 VFP decoder to decodetree
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(includes tightening up decode in a few places)
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* fix minor bugs in VFP short-vector handling
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* hw/core/bus.c: Only the main system bus can have no parent
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* smmuv3: Fix decoding of ID register range
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* Implement NSACR gating of floating point
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* Use tcg_gen_gvec_bitsel
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----------------------------------------------------------------
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----------------------------------------------------------------
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Peter Maydell (44):
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target/arm: Implement NSACR gating of floating point
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hw/arm/smmuv3: Fix decoding of ID register range
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hw/core/bus.c: Only the main system bus can have no parent
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target/arm: Add stubs for AArch32 VFP decodetree
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target/arm: Factor out VFP access checking code
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target/arm: Fix Cortex-R5F MVFR values
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target/arm: Explicitly enable VFP short-vectors for aarch32 -cpu max
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target/arm: Convert the VSEL instructions to decodetree
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target/arm: Convert VMINNM, VMAXNM to decodetree
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target/arm: Convert VRINTA/VRINTN/VRINTP/VRINTM to decodetree
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target/arm: Convert VCVTA/VCVTN/VCVTP/VCVTM to decodetree
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target/arm: Move the VFP trans_* functions to translate-vfp.inc.c
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target/arm: Add helpers for VFP register loads and stores
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target/arm: Convert "double-precision" register moves to decodetree
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target/arm: Convert "single-precision" register moves to decodetree
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target/arm: Convert VFP two-register transfer insns to decodetree
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target/arm: Convert VFP VLDR and VSTR to decodetree
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target/arm: Convert the VFP load/store multiple insns to decodetree
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target/arm: Remove VLDR/VSTR/VLDM/VSTM use of cpu_F0s and cpu_F0d
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target/arm: Convert VFP VMLA to decodetree
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target/arm: Convert VFP VMLS to decodetree
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target/arm: Convert VFP VNMLS to decodetree
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target/arm: Convert VFP VNMLA to decodetree
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target/arm: Convert VMUL to decodetree
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target/arm: Convert VNMUL to decodetree
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target/arm: Convert VADD to decodetree
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target/arm: Convert VSUB to decodetree
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target/arm: Convert VDIV to decodetree
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target/arm: Convert VFP fused multiply-add insns to decodetree
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target/arm: Convert VMOV (imm) to decodetree
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target/arm: Convert VABS to decodetree
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target/arm: Convert VNEG to decodetree
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target/arm: Convert VSQRT to decodetree
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target/arm: Convert VMOV (register) to decodetree
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target/arm: Convert VFP comparison insns to decodetree
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target/arm: Convert the VCVT-from-f16 insns to decodetree
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target/arm: Convert the VCVT-to-f16 insns to decodetree
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target/arm: Convert VFP round insns to decodetree
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target/arm: Convert double-single precision conversion insns to decodetree
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target/arm: Convert integer-to-float insns to decodetree
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target/arm: Convert VJCVT to decodetree
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target/arm: Convert VCVT fp/fixed-point conversion insns to decodetree
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target/arm: Convert float-to-integer VCVT insns to decodetree
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target/arm: Fix short-vector increment behaviour
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Richard Henderson (3):
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Richard Henderson (3):
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target/arm: Use kvm_arm_sve_supported in kvm_arm_get_host_cpu_features
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target/arm: Use tcg_gen_gvec_bitsel
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target/arm: Set KVM_ARM_VCPU_SVE while probing the host
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target/arm: Fix output of PAuth Auth
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target/arm: Move sve probe inside kvm >= 4.15 branch
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decodetree: Fix comparison of Field
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target/arm/kvm64.c | 45 ++++++++++++++++++++++-----------------------
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target/arm/Makefile.objs | 13 +
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1 file changed, 22 insertions(+), 23 deletions(-)
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tests/tcg/aarch64/Makefile.target | 2 +-
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target/arm/cpu.h | 11 +
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target/arm/translate-a64.h | 2 +
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target/arm/translate.h | 3 -
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hw/arm/smmuv3.c | 2 +-
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hw/core/bus.c | 21 +-
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target/arm/cpu.c | 6 +
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target/arm/helper.c | 75 +-
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target/arm/pauth_helper.c | 4 +-
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target/arm/translate-a64.c | 15 +-
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target/arm/translate-vfp.inc.c | 2672 +++++++++++++++++++++++++++++++++++++
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target/arm/translate.c | 1581 +---------------------
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tests/tcg/aarch64/pauth-2.c | 61 +
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scripts/decodetree.py | 2 +-
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target/arm/vfp-uncond.decode | 63 +
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target/arm/vfp.decode | 242 ++++
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17 files changed, 3203 insertions(+), 1572 deletions(-)
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create mode 100644 target/arm/translate-vfp.inc.c
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create mode 100644 tests/tcg/aarch64/pauth-2.c
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create mode 100644 target/arm/vfp-uncond.decode
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create mode 100644 target/arm/vfp.decode
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diff view generated by jsdifflib
[PULL 1/3] target/arm: Use kvm_arm_sve_supported in kvm_arm_get_host_cpu_features
Deleted patch
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From: Richard Henderson <richard.henderson@linaro.org>
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Indication for support for SVE will not depend on whether we
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perform the query on the main kvm_state or the temp vcpu.
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Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
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Message-id: 20220726045828.53697-2-richard.henderson@linaro.org
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Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
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Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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---
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target/arm/kvm64.c | 2 +-
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1 file changed, 1 insertion(+), 1 deletion(-)
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diff --git a/target/arm/kvm64.c b/target/arm/kvm64.c
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index XXXXXXX..XXXXXXX 100644
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--- a/target/arm/kvm64.c
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+++ b/target/arm/kvm64.c
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@@ -XXX,XX +XXX,XX @@ bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf)
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}
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}
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- sve_supported = ioctl(fdarray[0], KVM_CHECK_EXTENSION, KVM_CAP_ARM_SVE) > 0;
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+ sve_supported = kvm_arm_sve_supported();
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/* Add feature bits that can't appear until after VCPU init. */
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if (sve_supported) {
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--
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2.25.1
diff view generated by jsdifflib
[PULL 2/3] target/arm: Set KVM_ARM_VCPU_SVE while probing the host
Deleted patch
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From: Richard Henderson <richard.henderson@linaro.org>
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Because we weren't setting this flag, our probe of ID_AA64ZFR0
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was always returning zero. This also obviates the adjustment
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of ID_AA64PFR0, which had sanitized the SVE field.
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The effects of the bug are not visible, because the only thing that
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ID_AA64ZFR0 is used for within qemu at present is tcg translation.
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The other tests for SVE within KVM are via ID_AA64PFR0.SVE.
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Reported-by: Zenghui Yu <yuzenghui@huawei.com>
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Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
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Message-id: 20220726045828.53697-3-richard.henderson@linaro.org
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Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
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Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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---
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target/arm/kvm64.c | 27 +++++++++++++--------------
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1 file changed, 13 insertions(+), 14 deletions(-)
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diff --git a/target/arm/kvm64.c b/target/arm/kvm64.c
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index XXXXXXX..XXXXXXX 100644
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--- a/target/arm/kvm64.c
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+++ b/target/arm/kvm64.c
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@@ -XXX,XX +XXX,XX @@ bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf)
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bool sve_supported;
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bool pmu_supported = false;
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uint64_t features = 0;
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- uint64_t t;
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int err;
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/* Old kernels may not know about the PREFERRED_TARGET ioctl: however
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@@ -XXX,XX +XXX,XX @@ bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf)
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struct kvm_vcpu_init init = { .target = -1, };
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/*
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- * Ask for Pointer Authentication if supported. We can't play the
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- * SVE trick of synthesising the ID reg as KVM won't tell us
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- * whether we have the architected or IMPDEF version of PAuth, so
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- * we have to use the actual ID regs.
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+ * Ask for SVE if supported, so that we can query ID_AA64ZFR0,
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+ * which is otherwise RAZ.
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+ */
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+ sve_supported = kvm_arm_sve_supported();
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+ if (sve_supported) {
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+ init.features[0] |= 1 << KVM_ARM_VCPU_SVE;
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+ }
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+
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+ /*
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+ * Ask for Pointer Authentication if supported, so that we get
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+ * the unsanitized field values for AA64ISAR1_EL1.
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*/
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if (kvm_arm_pauth_supported()) {
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init.features[0] |= (1 << KVM_ARM_VCPU_PTRAUTH_ADDRESS |
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@@ -XXX,XX +XXX,XX @@ bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf)
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}
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}
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- sve_supported = kvm_arm_sve_supported();
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-
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- /* Add feature bits that can't appear until after VCPU init. */
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if (sve_supported) {
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- t = ahcf->isar.id_aa64pfr0;
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- t = FIELD_DP64(t, ID_AA64PFR0, SVE, 1);
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- ahcf->isar.id_aa64pfr0 = t;
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-
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/*
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* There is a range of kernels between kernel commit 73433762fcae
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* and f81cb2c3ad41 which have a bug where the kernel doesn't expose
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* SYS_ID_AA64ZFR0_EL1 via the ONE_REG API unless the VM has enabled
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- * SVE support, so we only read it here, rather than together with all
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- * the other ID registers earlier.
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+ * SVE support, which resulted in an error rather than RAZ.
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+ * So only read the register if we set KVM_ARM_VCPU_SVE above.
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*/
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err |= read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64zfr0,
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ARM64_SYS_REG(3, 0, 0, 4, 4));
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--
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2.25.1
diff view generated by jsdifflib
[PULL 3/3] target/arm: Move sve probe inside kvm >= 4.15 branch
Deleted patch
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From: Richard Henderson <richard.henderson@linaro.org>
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The test for the IF block indicates no ID registers are exposed, much
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less host support for SVE. Move the SVE probe into the ELSE block.
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Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
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Message-id: 20220726045828.53697-4-richard.henderson@linaro.org
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Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
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Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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---
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target/arm/kvm64.c | 22 +++++++++++-----------
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1 file changed, 11 insertions(+), 11 deletions(-)
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diff --git a/target/arm/kvm64.c b/target/arm/kvm64.c
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index XXXXXXX..XXXXXXX 100644
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--- a/target/arm/kvm64.c
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+++ b/target/arm/kvm64.c
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@@ -XXX,XX +XXX,XX @@ bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf)
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err |= read_sys_reg64(fdarray[2], &ahcf->isar.reset_pmcr_el0,
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ARM64_SYS_REG(3, 3, 9, 12, 0));
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}
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- }
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- if (sve_supported) {
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- /*
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- * There is a range of kernels between kernel commit 73433762fcae
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- * and f81cb2c3ad41 which have a bug where the kernel doesn't expose
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- * SYS_ID_AA64ZFR0_EL1 via the ONE_REG API unless the VM has enabled
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- * SVE support, which resulted in an error rather than RAZ.
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- * So only read the register if we set KVM_ARM_VCPU_SVE above.
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- */
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- err |= read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64zfr0,
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- ARM64_SYS_REG(3, 0, 0, 4, 4));
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+ if (sve_supported) {
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+ /*
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+ * There is a range of kernels between kernel commit 73433762fcae
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+ * and f81cb2c3ad41 which have a bug where the kernel doesn't
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+ * expose SYS_ID_AA64ZFR0_EL1 via the ONE_REG API unless the VM has
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+ * enabled SVE support, which resulted in an error rather than RAZ.
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+ * So only read the register if we set KVM_ARM_VCPU_SVE above.
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+ */
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+ err |= read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64zfr0,
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+ ARM64_SYS_REG(3, 0, 0, 4, 4));
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+ }
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}
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kvm_arm_destroy_scratch_host_vcpu(fdarray);
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--
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2.25.1
diff view generated by jsdifflib

Patchew 2.1-devel-b67e4c2

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