Series comparison

-[PULL 00/45] target-arm queue
+[PULL 00/24] target-arm queue
-I don't have anything else queued up at the moment, so this is just
+Hi; here's the latest round of arm patches. I have included also
-Richard's SME patches.
+my patchset for the RTC devices to avoid keeping time_t and
 time_t diffs in 32-bit variables.
+thanks
 -- PMM
-The following changes since commit 63b38f6c85acd312c2cab68554abf33adf4ee2b3:
+The following changes since commit 156618d9ea67f2f2e31d9dedd97f2dcccbe6808c:
-  Merge tag 'pull-target-arm-20220707' of https://git.linaro.org/people/pmaydell/qemu-arm into staging (2022-07-08 06:17:11 +0530)
+  Merge tag 'block-pull-request' of https://gitlab.com/stefanha/qemu into staging (2023-08-30 09:20:27 -0400)
 are available in the Git repository at:
-  https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20220711
+  https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20230831
-for you to fetch changes up to f9982ceaf26df27d15547a3a7990a95019e9e3a8:
+for you to fetch changes up to e73b8bb8a3e9a162f70e9ffbf922d4fafc96bbfb:
-  linux-user/aarch64: Add SME related hwcap entries (2022-07-11 13:43:52 +0100)
+  hw/arm: Set number of MPU regions correctly for an505, an521, an524 (2023-08-31 11:07:02 +0100)
 ----------------------------------------------------------------
-target-arm:
+target-arm queue:
- * Implement SME emulation, for both system and linux-user
+ * Some of the preliminary patches for Cortex-A710 support
  * i.MX7 and i.MX6UL refactoring
  * Implement SRC device for i.MX7
  * Catch illegal-exception-return from EL3 with bad NSE/NS
  * Use 64-bit offsets for holding time_t differences in RTC devices
  * Model correct number of MPU regions for an505, an521, an524 boards
 ----------------------------------------------------------------
-Richard Henderson (45):
+Alex Bennée (1):
-      target/arm: Handle SME in aarch64_cpu_dump_state
+      target/arm: properly document FEAT_CRC32
       target/arm: Add infrastructure for disas_sme
       target/arm: Trap non-streaming usage when Streaming SVE is active
       target/arm: Mark ADR as non-streaming
       target/arm: Mark RDFFR, WRFFR, SETFFR as non-streaming
       target/arm: Mark BDEP, BEXT, BGRP, COMPACT, FEXPA, FTSSEL as non-streaming
       target/arm: Mark PMULL, FMMLA as non-streaming
       target/arm: Mark FTSMUL, FTMAD, FADDA as non-streaming
       target/arm: Mark SMMLA, UMMLA, USMMLA as non-streaming
       target/arm: Mark string/histo/crypto as non-streaming
       target/arm: Mark gather/scatter load/store as non-streaming
       target/arm: Mark gather prefetch as non-streaming
       target/arm: Mark LDFF1 and LDNF1 as non-streaming
       target/arm: Mark LD1RO as non-streaming
       target/arm: Add SME enablement checks
       target/arm: Handle SME in sve_access_check
       target/arm: Implement SME RDSVL, ADDSVL, ADDSPL
       target/arm: Implement SME ZERO
       target/arm: Implement SME MOVA
       target/arm: Implement SME LD1, ST1
       target/arm: Export unpredicated ld/st from translate-sve.c
       target/arm: Implement SME LDR, STR
       target/arm: Implement SME ADDHA, ADDVA
       target/arm: Implement FMOPA, FMOPS (non-widening)
       target/arm: Implement BFMOPA, BFMOPS
       target/arm: Implement FMOPA, FMOPS (widening)
       target/arm: Implement SME integer outer product
       target/arm: Implement PSEL
       target/arm: Implement REVD
       target/arm: Implement SCLAMP, UCLAMP
       target/arm: Reset streaming sve state on exception boundaries
       target/arm: Enable SME for -cpu max
       linux-user/aarch64: Clear tpidr2_el0 if CLONE_SETTLS
       linux-user/aarch64: Reset PSTATE.SM on syscalls
       linux-user/aarch64: Add SM bit to SVE signal context
       linux-user/aarch64: Tidy target_restore_sigframe error return
       linux-user/aarch64: Do not allow duplicate or short sve records
       linux-user/aarch64: Verify extra record lock succeeded
       linux-user/aarch64: Move sve record checks into restore
       linux-user/aarch64: Implement SME signal handling
       linux-user: Rename sve prctls
       linux-user/aarch64: Implement PR_SME_GET_VL, PR_SME_SET_VL
       target/arm: Only set ZEN in reset if SVE present
       target/arm: Enable SME for user-only
       linux-user/aarch64: Add SME related hwcap entries
- docs/system/arm/emulation.rst     |    4 +
+Jean-Christophe Dubois (6):
- linux-user/aarch64/target_cpu.h   |    5 +-
+      Remove i.MX7 IOMUX GPR device from i.MX6UL
- linux-user/aarch64/target_prctl.h |   62 +-
+      Refactor i.MX6UL processor code
- target/arm/cpu.h                  |    7 +
+      Add i.MX6UL missing devices.
- target/arm/helper-sme.h           |  126 ++++
+      Refactor i.MX7 processor code
- target/arm/helper-sve.h           |    4 +
+      Add i.MX7 missing TZ devices and memory regions
- target/arm/helper.h               |   18 +
+      Add i.MX7 SRC device implementation
- target/arm/translate-a64.h        |   45 ++
- target/arm/translate.h            |   16 +
+Peter Maydell (8):
- target/arm/sme-fa64.decode        |   60 ++
+      target/arm: Catch illegal-exception-return from EL3 with bad NSE/NS
- target/arm/sme.decode             |   88 +++
+      hw/rtc/m48t59: Use 64-bit arithmetic in set_alarm()
- target/arm/sve.decode             |   41 +-
+      hw/rtc/twl92230: Use int64_t for sec_offset and alm_sec
- linux-user/aarch64/cpu_loop.c     |    9 +
+      hw/rtc/aspeed_rtc: Use 64-bit offset for holding time_t difference
- linux-user/aarch64/signal.c       |  243 ++++++--
+      rtc: Use time_t for passing and returning time offsets
- linux-user/elfload.c              |   20 +
+      target/arm: Do all "ARM_FEATURE_X implies Y" checks in post_init
- linux-user/syscall.c              |   28 +-
+      hw/arm/armv7m: Add mpu-ns-regions and mpu-s-regions properties
- target/arm/cpu.c                  |   35 +-
+      hw/arm: Set number of MPU regions correctly for an505, an521, an524
- target/arm/cpu64.c                |   11 +
- target/arm/helper.c               |   56 +-
+Richard Henderson (9):
- target/arm/sme_helper.c           | 1140 +++++++++++++++++++++++++++++++++++++
+      target/arm: Reduce dcz_blocksize to uint8_t
- target/arm/sve_helper.c           |   28 +
+      target/arm: Allow cpu to configure GM blocksize
- target/arm/translate-a64.c        |  103 +++-
+      target/arm: Support more GM blocksizes
- target/arm/translate-sme.c        |  373 ++++++++++++
+      target/arm: When tag memory is not present, set MTE=1
- target/arm/translate-sve.c        |  393 ++++++++++---
+      target/arm: Introduce make_ccsidr64
- target/arm/translate-vfp.c        |   12 +
+      target/arm: Apply access checks to neoverse-n1 special registers
- target/arm/translate.c            |    2 +
+      target/arm: Apply access checks to neoverse-v1 special registers
- target/arm/vec_helper.c           |   24 +
+      target/arm: Suppress FEAT_TRBE (Trace Buffer Extension)
- target/arm/meson.build            |    3 +
+      target/arm: Implement FEAT_HPDS2 as a no-op
-files changed, 2821 insertions(+), 135 deletions(-)
- create mode 100644 target/arm/sme-fa64.decode
+ docs/system/arm/emulation.rst  |   2 +
- create mode 100644 target/arm/sme.decode
+ include/hw/arm/armsse.h        |   5 +
- create mode 100644 target/arm/translate-sme.c
+ include/hw/arm/armv7m.h        |   8 +
  include/hw/arm/fsl-imx6ul.h    | 158 ++++++++++++++++---
  include/hw/arm/fsl-imx7.h      | 338 ++++++++++++++++++++++++++++++-----------
  include/hw/misc/imx7_src.h     |  66 ++++++++
  include/hw/rtc/aspeed_rtc.h    |   2 +-
  include/sysemu/rtc.h           |   4 +-
  target/arm/cpregs.h            |   2 +
  target/arm/cpu.h               |   5 +-
  target/arm/internals.h         |   6 -
  target/arm/tcg/translate.h     |   2 +
  hw/arm/armsse.c                |  16 ++
  hw/arm/armv7m.c                |  21 +++
  hw/arm/fsl-imx6ul.c            | 174 +++++++++++++--------
  hw/arm/fsl-imx7.c              | 201 +++++++++++++++++++-----
  hw/arm/mps2-tz.c               |  29 ++++
  hw/misc/imx7_src.c             | 276 +++++++++++++++++++++++++++++++++
  hw/rtc/aspeed_rtc.c            |   5 +-
  hw/rtc/m48t59.c                |   2 +-
  hw/rtc/twl92230.c              |   4 +-
  softmmu/rtc.c                  |   4 +-
  target/arm/cpu.c               | 207 ++++++++++++++-----------
  target/arm/helper.c            |  15 +-
  target/arm/tcg/cpu32.c         |   2 +-
  target/arm/tcg/cpu64.c         | 102 +++++++++----
  target/arm/tcg/helper-a64.c    |   9 ++
  target/arm/tcg/mte_helper.c    |  90 ++++++++---
  target/arm/tcg/translate-a64.c |   5 +-
  hw/misc/meson.build            |   1 +
  hw/misc/trace-events           |   4 +
 files changed, 1393 insertions(+), 372 deletions(-)
  create mode 100644 include/hw/misc/imx7_src.h
  create mode 100644 hw/misc/imx7_src.c

-[PULL 42/45] linux-user/aarch64: Implement PR_SME_GET_VL, PR_SME_SET_VL
+[PULL 01/24] target/arm: Reduce dcz_blocksize to uint8_t
 From: Richard Henderson <richard.henderson@linaro.org>
-These prctl set the Streaming SVE vector length, which may
+This value is only 4 bits wide.
 be completely different from the Normal SVE vector length.
 Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
 Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
-Message-id: 20220708151540.18136-43-richard.henderson@linaro.org
+Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
 Message-id: 20230811214031.171020-2-richard.henderson@linaro.org
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 ---
- linux-user/aarch64/target_prctl.h | 54 +++++++++++++++++++++++++++++++
+ target/arm/cpu.h | 3 ++-
- linux-user/syscall.c              | 16 +++++++++
+file changed, 2 insertions(+), 1 deletion(-)
 files changed, 70 insertions(+)
-diff --git a/linux-user/aarch64/target_prctl.h b/linux-user/aarch64/target_prctl.h
+diff --git a/target/arm/cpu.h b/target/arm/cpu.h
 index XXXXXXX..XXXXXXX 100644
---- a/linux-user/aarch64/target_prctl.h
+--- a/target/arm/cpu.h
-+++ b/linux-user/aarch64/target_prctl.h
++++ b/target/arm/cpu.h
-@@ -XXX,XX +XXX,XX @@ static abi_long do_prctl_sve_get_vl(CPUArchState *env)
+@@ -XXX,XX +XXX,XX @@ struct ArchCPU {
- {
+     bool prop_lpa2;
-     ARMCPU *cpu = env_archcpu(env);
-     if (cpu_isar_feature(aa64_sve, cpu)) {
+     /* DCZ blocksize, in log_2(words), ie low 4 bits of DCZID_EL0 */
-+        /* PSTATE.SM is always unset on syscall entry. */
+-    uint32_t dcz_blocksize;
-         return sve_vq(env) * 16;
++    uint8_t dcz_blocksize;
      }
      return -TARGET_EINVAL;
@@ -XXX,XX +XXX,XX @@ static abi_long do_prctl_sve_set_vl(CPUArchState *env, abi_long arg2)
          && arg2 >= 0 && arg2 <= 512 * 16 && !(arg2 & 15)) {
          uint32_t vq, old_vq;
 +        /* PSTATE.SM is always unset on syscall entry. */
          old_vq = sve_vq(env);
          /*
@@ -XXX,XX +XXX,XX @@ static abi_long do_prctl_sve_set_vl(CPUArchState *env, abi_long arg2)
  }
  #define do_prctl_sve_set_vl do_prctl_sve_set_vl
 +static abi_long do_prctl_sme_get_vl(CPUArchState *env)
 +{
 +    ARMCPU *cpu = env_archcpu(env);
 +    if (cpu_isar_feature(aa64_sme, cpu)) {
 +        return sme_vq(env) * 16;
 +    }
 +    return -TARGET_EINVAL;
 +}
 +#define do_prctl_sme_get_vl do_prctl_sme_get_vl
 +
-+static abi_long do_prctl_sme_set_vl(CPUArchState *env, abi_long arg2)
+     uint64_t rvbar_prop; /* Property/input signals.  */
-+{
-+    /*
+     /* Configurable aspects of GIC cpu interface (which is part of the CPU) */
 +     * We cannot support either PR_SME_SET_VL_ONEXEC or PR_SME_VL_INHERIT.
 +     * Note the kernel definition of sve_vl_valid allows for VQ=512,
 +     * i.e. VL=8192, even though the architectural maximum is VQ=16.
 +     */
 +    if (cpu_isar_feature(aa64_sme, env_archcpu(env))
 +        && arg2 >= 0 && arg2 <= 512 * 16 && !(arg2 & 15)) {
 +        int vq, old_vq;
 +
 +        old_vq = sme_vq(env);
 +
 +        /*
 +         * Bound the value of vq, so that we know that it fits into
 +         * the 4-bit field in SMCR_EL1.  Because PSTATE.SM is cleared
 +         * on syscall entry, we are not modifying the current SVE
 +         * vector length.
 +         */
 +        vq = MAX(arg2 / 16, 1);
 +        vq = MIN(vq, 16);
 +        env->vfp.smcr_el[1] =
 +            FIELD_DP64(env->vfp.smcr_el[1], SMCR, LEN, vq - 1);
 +
 +        /* Delay rebuilding hflags until we know if ZA must change. */
 +        vq = sve_vqm1_for_el_sm(env, 0, true) + 1;
 +
 +        if (vq != old_vq) {
 +            /*
 +             * PSTATE.ZA state is cleared on any change to SVL.
 +             * We need not call arm_rebuild_hflags because PSTATE.SM was
 +             * cleared on syscall entry, so this hasn't changed VL.
 +             */
 +            env->svcr = FIELD_DP64(env->svcr, SVCR, ZA, 0);
 +            arm_rebuild_hflags(env);
 +        }
 +        return vq * 16;
 +    }
 +    return -TARGET_EINVAL;
 +}
 +#define do_prctl_sme_set_vl do_prctl_sme_set_vl
 +
  static abi_long do_prctl_reset_keys(CPUArchState *env, abi_long arg2)
  {
      ARMCPU *cpu = env_archcpu(env);
 diff --git a/linux-user/syscall.c b/linux-user/syscall.c
 index XXXXXXX..XXXXXXX 100644
 --- a/linux-user/syscall.c
 +++ b/linux-user/syscall.c
@@ -XXX,XX +XXX,XX @@ abi_long do_arch_prctl(CPUX86State *env, int code, abi_ulong addr)
  #ifndef PR_SET_SYSCALL_USER_DISPATCH
  # define PR_SET_SYSCALL_USER_DISPATCH 59
  #endif
 +#ifndef PR_SME_SET_VL
 +# define PR_SME_SET_VL  63
 +# define PR_SME_GET_VL  64
 +# define PR_SME_VL_LEN_MASK  0xffff
 +# define PR_SME_VL_INHERIT   (1 << 17)
 +#endif
  #include "target_prctl.h"
@@ -XXX,XX +XXX,XX @@ static abi_long do_prctl_inval1(CPUArchState *env, abi_long arg2)
  #ifndef do_prctl_set_unalign
  #define do_prctl_set_unalign do_prctl_inval1
  #endif
 +#ifndef do_prctl_sme_get_vl
 +#define do_prctl_sme_get_vl do_prctl_inval0
 +#endif
 +#ifndef do_prctl_sme_set_vl
 +#define do_prctl_sme_set_vl do_prctl_inval1
 +#endif
  static abi_long do_prctl(CPUArchState *env, abi_long option, abi_long arg2,
                           abi_long arg3, abi_long arg4, abi_long arg5)
@@ -XXX,XX +XXX,XX @@ static abi_long do_prctl(CPUArchState *env, abi_long option, abi_long arg2,
          return do_prctl_sve_get_vl(env);
      case PR_SVE_SET_VL:
          return do_prctl_sve_set_vl(env, arg2);
 +    case PR_SME_GET_VL:
 +        return do_prctl_sme_get_vl(env);
 +    case PR_SME_SET_VL:
 +        return do_prctl_sme_set_vl(env, arg2);
      case PR_PAC_RESET_KEYS:
          if (arg3 || arg4 || arg5) {
              return -TARGET_EINVAL;
 --
-.25.1
+.34.1

-[PULL 03/45] target/arm: Trap non-streaming usage when Streaming SVE is active
+[PULL 02/24] target/arm: Allow cpu to configure GM blocksize
 From: Richard Henderson <richard.henderson@linaro.org>
-This new behaviour is in the ARM pseudocode function
+Previously we hard-coded the blocksize with GMID_EL1_BS.
-AArch64.CheckFPAdvSIMDEnabled, which applies to AArch32
+But the value we choose for -cpu max does not match the
-via AArch32.CheckAdvSIMDOrFPEnabled when the EL to which
+value that cortex-a710 uses.
-the trap would be delivered is in AArch64 mode.
+Mirror the way we handle dcz_blocksize.
 Given that ARMv9 drops support for AArch32 outside EL0, the trap EL
 detection ought to be trivially true, but the pseudocode still contains
 a number of conditions, and QEMU has not yet committed to dropping A32
 support for EL[12] when v9 features are present.
 Since the computation of SME_TRAP_NONSTREAMING is necessarily different
 for the two modes, we might as well preserve bits within TBFLAG_ANY and
 allocate separate bits within TBFLAG_A32 and TBFLAG_A64 instead.
 Note that DDI0616A.a has typos for bits [22:21] of LD1RO in the table
 of instructions illegal in streaming mode.
 Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
 Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
-Message-id: 20220708151540.18136-4-richard.henderson@linaro.org
+Message-id: 20230811214031.171020-3-richard.henderson@linaro.org
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 ---
- target/arm/cpu.h           |  7 +++
+ target/arm/cpu.h               |  2 ++
- target/arm/translate.h     |  4 ++
+ target/arm/internals.h         |  6 -----
- target/arm/sme-fa64.decode | 90 ++++++++++++++++++++++++++++++++++++++
+ target/arm/tcg/translate.h     |  2 ++
- target/arm/helper.c        | 41 +++++++++++++++++
+ target/arm/helper.c            | 11 +++++---
- target/arm/translate-a64.c | 40 ++++++++++++++++-
+ target/arm/tcg/cpu64.c         |  1 +
- target/arm/translate-vfp.c | 12 +++++
+ target/arm/tcg/mte_helper.c    | 46 ++++++++++++++++++++++------------
- target/arm/translate.c     |  2 +
+ target/arm/tcg/translate-a64.c |  5 ++--
- target/arm/meson.build     |  1 +
+files changed, 45 insertions(+), 28 deletions(-)
 files changed, 195 insertions(+), 2 deletions(-)
  create mode 100644 target/arm/sme-fa64.decode
 diff --git a/target/arm/cpu.h b/target/arm/cpu.h
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/cpu.h
 +++ b/target/arm/cpu.h
-@@ -XXX,XX +XXX,XX @@ FIELD(TBFLAG_A32, HSTR_ACTIVE, 9, 1)
+@@ -XXX,XX +XXX,XX @@ struct ArchCPU {
-  * the same thing as the current security state of the processor!
-  */
+     /* DCZ blocksize, in log_2(words), ie low 4 bits of DCZID_EL0 */
- FIELD(TBFLAG_A32, NS, 10, 1)
+     uint8_t dcz_blocksize;
-+/*
++    /* GM blocksize, in log_2(words), ie low 4 bits of GMID_EL0 */
-+ * Indicates that SME Streaming mode is active, and SMCR_ELx.FA64 is not.
++    uint8_t gm_blocksize;
-+ * This requires an SME trap from AArch32 mode when using NEON.
-+ */
+     uint64_t rvbar_prop; /* Property/input signals.  */
-+FIELD(TBFLAG_A32, SME_TRAP_NONSTREAMING, 11, 1)
+diff --git a/target/arm/internals.h b/target/arm/internals.h
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/internals.h
 +++ b/target/arm/internals.h
@@ -XXX,XX +XXX,XX @@ void arm_log_exception(CPUState *cs);
  #endif /* !CONFIG_USER_ONLY */
 -/*
 - * The log2 of the words in the tag block, for GMID_EL1.BS.
 - * The is the maximum, 256 bytes, which manipulates 64-bits of tags.
 - */
 -#define GMID_EL1_BS  6
 -
  /*
-  * Bit usage when in AArch32 state, for M-profile only.
+  * SVE predicates are 1/8 the size of SVE vectors, and cannot use
-@@ -XXX,XX +XXX,XX @@ FIELD(TBFLAG_A64, SMEEXC_EL, 20, 2)
+  * the same simd_desc() encoding due to restrictions on size.
- FIELD(TBFLAG_A64, PSTATE_SM, 22, 1)
+diff --git a/target/arm/tcg/translate.h b/target/arm/tcg/translate.h
- FIELD(TBFLAG_A64, PSTATE_ZA, 23, 1)
+index XXXXXXX..XXXXXXX 100644
- FIELD(TBFLAG_A64, SVL, 24, 4)
+--- a/target/arm/tcg/translate.h
-+/* Indicates that SME Streaming mode is active, and SMCR_ELx.FA64 is not. */
++++ b/target/arm/tcg/translate.h
 +FIELD(TBFLAG_A64, SME_TRAP_NONSTREAMING, 28, 1)
  /*
   * Helpers for using the above.
 diff --git a/target/arm/translate.h b/target/arm/translate.h
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/translate.h
 +++ b/target/arm/translate.h
 @@ -XXX,XX +XXX,XX @@ typedef struct DisasContext {
-     bool pstate_sm;
+     int8_t btype;
-     /* True if PSTATE.ZA is set. */
+     /* A copy of cpu->dcz_blocksize. */
-     bool pstate_za;
+     uint8_t dcz_blocksize;
-+    /* True if non-streaming insns should raise an SME Streaming exception. */
++    /* A copy of cpu->gm_blocksize. */
-+    bool sme_trap_nonstreaming;
++    uint8_t gm_blocksize;
-+    /* True if the current instruction is non-streaming. */
+     /* True if this page is guarded.  */
-+    bool is_nonstreaming;
+     bool guarded_page;
-     /* True if MVE insns are definitely not predicated by VPR or LTPSIZE */
+     /* Bottom two bits of XScale c15_cpar coprocessor access control reg */
      bool mve_no_pred;
      /*
 diff --git a/target/arm/sme-fa64.decode b/target/arm/sme-fa64.decode
 new file mode 100644
 index XXXXXXX..XXXXXXX
 --- /dev/null
 +++ b/target/arm/sme-fa64.decode
@@ -XXX,XX +XXX,XX @@
 +# AArch64 SME allowed instruction decoding
 +#
 +#  Copyright (c) 2022 Linaro, Ltd
 +#
 +# This library is free software; you can redistribute it and/or
 +# modify it under the terms of the GNU Lesser General Public
 +# License as published by the Free Software Foundation; either
 +# version 2.1 of the License, or (at your option) any later version.
 +#
 +# This library is distributed in the hope that it will be useful,
 +# but WITHOUT ANY WARRANTY; without even the implied warranty of
 +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
 +# Lesser General Public License for more details.
 +#
 +# You should have received a copy of the GNU Lesser General Public
 +# License along with this library; if not, see <http://www.gnu.org/licenses/>.
 +
 +#
 +# This file is processed by scripts/decodetree.py
 +#
 +
 +# These patterns are taken from Appendix E1.1 of DDI0616 A.a,
 +# Arm Architecture Reference Manual Supplement,
 +# The Scalable Matrix Extension (SME), for Armv9-A
 +
 +{
 +  [
 +    OK  0-00 1110 0000 0001 0010 11-- ---- ----   # SMOV W|Xd,Vn.B[0]
 +    OK  0-00 1110 0000 0010 0010 11-- ---- ----   # SMOV W|Xd,Vn.H[0]
 +    OK  0100 1110 0000 0100 0010 11-- ---- ----   # SMOV Xd,Vn.S[0]
 +    OK  0000 1110 0000 0001 0011 11-- ---- ----   # UMOV Wd,Vn.B[0]
 +    OK  0000 1110 0000 0010 0011 11-- ---- ----   # UMOV Wd,Vn.H[0]
 +    OK  0000 1110 0000 0100 0011 11-- ---- ----   # UMOV Wd,Vn.S[0]
 +    OK  0100 1110 0000 1000 0011 11-- ---- ----   # UMOV Xd,Vn.D[0]
 +  ]
 +  FAIL  0--0 111- ---- ---- ---- ---- ---- ----   # Advanced SIMD vector operations
 +}
 +
 +{
 +  [
 +    OK  0101 1110 --1- ---- 11-1 11-- ---- ----   # FMULX/FRECPS/FRSQRTS (scalar)
 +    OK  0101 1110 -10- ---- 00-1 11-- ---- ----   # FMULX/FRECPS/FRSQRTS (scalar, FP16)
 +    OK  01-1 1110 1-10 0001 11-1 10-- ---- ----   # FRECPE/FRSQRTE/FRECPX (scalar)
 +    OK  01-1 1110 1111 1001 11-1 10-- ---- ----   # FRECPE/FRSQRTE/FRECPX (scalar, FP16)
 +  ]
 +  FAIL  01-1 111- ---- ---- ---- ---- ---- ----   # Advanced SIMD single-element operations
 +}
 +
 +FAIL    0-00 110- ---- ---- ---- ---- ---- ----   # Advanced SIMD structure load/store
 +FAIL    1100 1110 ---- ---- ---- ---- ---- ----   # Advanced SIMD cryptography extensions
 +FAIL    0001 1110 0111 1110 0000 00-- ---- ----   # FJCVTZS
 +
 +# These are the "avoidance of doubt" final table of Illegal Advanced SIMD instructions
 +# We don't actually need to include these, as the default is OK.
 +#       -001 111- ---- ---- ---- ---- ---- ----   # Scalar floating-point operations
 +#       --10 110- ---- ---- ---- ---- ---- ----   # Load/store pair of FP registers
 +#       --01 1100 ---- ---- ---- ---- ---- ----   # Load FP register (PC-relative literal)
 +#       --11 1100 --0- ---- ---- ---- ---- ----   # Load/store FP register (unscaled imm)
 +#       --11 1100 --1- ---- ---- ---- ---- --10   # Load/store FP register (register offset)
 +#       --11 1101 ---- ---- ---- ---- ---- ----   # Load/store FP register (scaled imm)
 +
 +FAIL    0000 0100 --1- ---- 1010 ---- ---- ----   # ADR
 +FAIL    0000 0100 --1- ---- 1011 -0-- ---- ----   # FTSSEL, FEXPA
 +FAIL    0000 0101 --10 0001 100- ---- ---- ----   # COMPACT
 +FAIL    0010 0101 --01 100- 1111 000- ---0 ----   # RDFFR, RDFFRS
 +FAIL    0010 0101 --10 1--- 1001 ---- ---- ----   # WRFFR, SETFFR
 +FAIL    0100 0101 --0- ---- 1011 ---- ---- ----   # BDEP, BEXT, BGRP
 +FAIL    0100 0101 000- ---- 0110 1--- ---- ----   # PMULLB, PMULLT (128b result)
 +FAIL    0110 0100 --1- ---- 1110 01-- ---- ----   # FMMLA, BFMMLA
 +FAIL    0110 0101 --0- ---- 0000 11-- ---- ----   # FTSMUL
 +FAIL    0110 0101 --01 0--- 100- ---- ---- ----   # FTMAD
 +FAIL    0110 0101 --01 1--- 001- ---- ---- ----   # FADDA
 +FAIL    0100 0101 --0- ---- 1001 10-- ---- ----   # SMMLA, UMMLA, USMMLA
 +FAIL    0100 0101 --1- ---- 1--- ---- ---- ----   # SVE2 string/histo/crypto instructions
 +FAIL    1000 010- -00- ---- 10-- ---- ---- ----   # SVE2 32-bit gather NT load (vector+scalar)
 +FAIL    1000 010- -00- ---- 111- ---- ---- ----   # SVE 32-bit gather prefetch (vector+imm)
 +FAIL    1000 0100 0-1- ---- 0--- ---- ---- ----   # SVE 32-bit gather prefetch (scalar+vector)
 +FAIL    1000 010- -01- ---- 1--- ---- ---- ----   # SVE 32-bit gather load (vector+imm)
 +FAIL    1000 0100 0-0- ---- 0--- ---- ---- ----   # SVE 32-bit gather load byte (scalar+vector)
 +FAIL    1000 0100 1--- ---- 0--- ---- ---- ----   # SVE 32-bit gather load half (scalar+vector)
 +FAIL    1000 0101 0--- ---- 0--- ---- ---- ----   # SVE 32-bit gather load word (scalar+vector)
 +FAIL    1010 010- ---- ---- 011- ---- ---- ----   # SVE contiguous FF load (scalar+scalar)
 +FAIL    1010 010- ---1 ---- 101- ---- ---- ----   # SVE contiguous NF load (scalar+imm)
 +FAIL    1010 010- -01- ---- 000- ---- ---- ----   # SVE load & replicate 32 bytes (scalar+scalar)
 +FAIL    1010 010- -010 ---- 001- ---- ---- ----   # SVE load & replicate 32 bytes (scalar+imm)
 +FAIL    1100 010- ---- ---- ---- ---- ---- ----   # SVE 64-bit gather load/prefetch
 +FAIL    1110 010- -00- ---- 001- ---- ---- ----   # SVE2 64-bit scatter NT store (vector+scalar)
 +FAIL    1110 010- -10- ---- 001- ---- ---- ----   # SVE2 32-bit scatter NT store (vector+scalar)
 +FAIL    1110 010- ---- ---- 1-0- ---- ---- ----   # SVE scatter store (scalar+32-bit vector)
 +FAIL    1110 010- ---- ---- 101- ---- ---- ----   # SVE scatter store (misc)
 diff --git a/target/arm/helper.c b/target/arm/helper.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/helper.c
 +++ b/target/arm/helper.c
-@@ -XXX,XX +XXX,XX @@ int sme_exception_el(CPUARMState *env, int el)
+@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo mte_reginfo[] = {
-     return 0;
+       .opc0 = 3, .opc1 = 0, .crn = 1, .crm = 0, .opc2 = 6,
- }
+       .access = PL1_RW, .accessfn = access_mte,
+       .fieldoffset = offsetof(CPUARMState, cp15.gcr_el1) },
-+/* This corresponds to the ARM pseudocode function IsFullA64Enabled(). */
+-    { .name = "GMID_EL1", .state = ARM_CP_STATE_AA64,
-+static bool sme_fa64(CPUARMState *env, int el)
+-      .opc0 = 3, .opc1 = 1, .crn = 0, .crm = 0, .opc2 = 4,
-+{
+-      .access = PL1_R, .accessfn = access_aa64_tid5,
-+    if (!cpu_isar_feature(aa64_sme_fa64, env_archcpu(env))) {
+-      .type = ARM_CP_CONST, .resetvalue = GMID_EL1_BS },
-+        return false;
+     { .name = "TCO", .state = ARM_CP_STATE_AA64,
-+    }
+       .opc0 = 3, .opc1 = 3, .crn = 4, .crm = 2, .opc2 = 7,
-+
+       .type = ARM_CP_NO_RAW,
-+    if (el <= 1 && !el_is_in_host(env, el)) {
+@@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu)
-+        if (!FIELD_EX64(env->vfp.smcr_el[1], SMCR, FA64)) {
+      * then define only a RAZ/WI version of PSTATE.TCO.
-+            return false;
+      */
-+        }
+     if (cpu_isar_feature(aa64_mte, cpu)) {
-+    }
++        ARMCPRegInfo gmid_reginfo = {
-+    if (el <= 2 && arm_is_el2_enabled(env)) {
++            .name = "GMID_EL1", .state = ARM_CP_STATE_AA64,
-+        if (!FIELD_EX64(env->vfp.smcr_el[2], SMCR, FA64)) {
++            .opc0 = 3, .opc1 = 1, .crn = 0, .crm = 0, .opc2 = 4,
-+            return false;
++            .access = PL1_R, .accessfn = access_aa64_tid5,
-+        }
++            .type = ARM_CP_CONST, .resetvalue = cpu->gm_blocksize,
-+    }
++        };
-+    if (arm_feature(env, ARM_FEATURE_EL3)) {
++        define_one_arm_cp_reg(cpu, &gmid_reginfo);
-+        if (!FIELD_EX64(env->vfp.smcr_el[3], SMCR, FA64)) {
+         define_arm_cp_regs(cpu, mte_reginfo);
-+            return false;
+         define_arm_cp_regs(cpu, mte_el0_cacheop_reginfo);
-+        }
+     } else if (cpu_isar_feature(aa64_mte_insn_reg, cpu)) {
-+    }
+diff --git a/target/arm/tcg/cpu64.c b/target/arm/tcg/cpu64.c
-+
+index XXXXXXX..XXXXXXX 100644
-+    return true;
+--- a/target/arm/tcg/cpu64.c
-+}
++++ b/target/arm/tcg/cpu64.c
-+
+@@ -XXX,XX +XXX,XX @@ void aarch64_max_tcg_initfn(Object *obj)
- /*
+     cpu->ctr = 0x80038003; /* 32 byte I and D cacheline size, VIPT icache */
-  * Given that SVE is enabled, return the vector length for EL.
+     cpu->dcz_blocksize = 7; /*  512 bytes */
-  */
+ #endif
-@@ -XXX,XX +XXX,XX @@ static CPUARMTBFlags rebuild_hflags_a32(CPUARMState *env, int fp_el,
++    cpu->gm_blocksize = 6;  /*  256 bytes */
-         DP_TBFLAG_ANY(flags, PSTATE__IL, 1);
-     }
+     cpu->sve_vq.supported = MAKE_64BIT_MASK(0, ARM_MAX_VQ);
+     cpu->sme_vq.supported = SVE_VQ_POW2_MAP;
-+    /*
+diff --git a/target/arm/tcg/mte_helper.c b/target/arm/tcg/mte_helper.c
-+     * The SME exception we are testing for is raised via
+index XXXXXXX..XXXXXXX 100644
-+     * AArch64.CheckFPAdvSIMDEnabled(), as called from
+--- a/target/arm/tcg/mte_helper.c
-+     * AArch32.CheckAdvSIMDOrFPEnabled().
++++ b/target/arm/tcg/mte_helper.c
-+     */
+@@ -XXX,XX +XXX,XX @@ void HELPER(st2g_stub)(CPUARMState *env, uint64_t ptr)
 +    if (el == 0
 +        && FIELD_EX64(env->svcr, SVCR, SM)
 +        && (!arm_is_el2_enabled(env)
 +            || (arm_el_is_aa64(env, 2) && !(env->cp15.hcr_el2 & HCR_TGE)))
 +        && arm_el_is_aa64(env, 1)
 +        && !sme_fa64(env, el)) {
 +        DP_TBFLAG_A32(flags, SME_TRAP_NONSTREAMING, 1);
 +    }
 +
      return rebuild_hflags_common_32(env, fp_el, mmu_idx, flags);
  }
@@ -XXX,XX +XXX,XX @@ static CPUARMTBFlags rebuild_hflags_a64(CPUARMState *env, int el, int fp_el,
          }
          if (FIELD_EX64(env->svcr, SVCR, SM)) {
              DP_TBFLAG_A64(flags, PSTATE_SM, 1);
 +            DP_TBFLAG_A64(flags, SME_TRAP_NONSTREAMING, !sme_fa64(env, el));
          }
          DP_TBFLAG_A64(flags, PSTATE_ZA, FIELD_EX64(env->svcr, SVCR, ZA));
      }
 diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/translate-a64.c
 +++ b/target/arm/translate-a64.c
@@ -XXX,XX +XXX,XX @@ static void do_vec_ld(DisasContext *s, int destidx, int element,
   * unallocated-encoding checks (otherwise the syndrome information
   * for the resulting exception will be incorrect).
   */
 -static bool fp_access_check(DisasContext *s)
 +static bool fp_access_check_only(DisasContext *s)
  {
      if (s->fp_excp_el) {
          assert(!s->fp_access_checked);
@@ -XXX,XX +XXX,XX @@ static bool fp_access_check(DisasContext *s)
      return true;
  }
 +static bool fp_access_check(DisasContext *s)
 +{
 +    if (!fp_access_check_only(s)) {
 +        return false;
 +    }
 +    if (s->sme_trap_nonstreaming && s->is_nonstreaming) {
 +        gen_exception_insn(s, s->pc_curr, EXCP_UDEF,
 +                           syn_smetrap(SME_ET_Streaming, false));
 +        return false;
 +    }
 +    return true;
 +}
 +
  /* Check that SVE access is enabled.  If it is, return true.
   * If not, emit code to generate an appropriate exception and return false.
   */
@@ -XXX,XX +XXX,XX @@ static void handle_sys(DisasContext *s, uint32_t insn, bool isread,
      default:
          g_assert_not_reached();
      }
 -    if ((ri->type & ARM_CP_FPU) && !fp_access_check(s)) {
 +    if ((ri->type & ARM_CP_FPU) && !fp_access_check_only(s)) {
          return;
      } else if ((ri->type & ARM_CP_SVE) && !sve_access_check(s)) {
          return;
@@ -XXX,XX +XXX,XX @@ static void disas_data_proc_simd_fp(DisasContext *s, uint32_t insn)
      }
  }
-+/*
+-#define LDGM_STGM_SIZE  (4 << GMID_EL1_BS)
-+ * Include the generated SME FA64 decoder.
+-
-+ */
+ uint64_t HELPER(ldgm)(CPUARMState *env, uint64_t ptr)
-+
+ {
-+#include "decode-sme-fa64.c.inc"
+     int mmu_idx = cpu_mmu_index(env, false);
-+
+     uintptr_t ra = GETPC();
-+static bool trans_OK(DisasContext *s, arg_OK *a)
++    int gm_bs = env_archcpu(env)->gm_blocksize;
-+{
++    int gm_bs_bytes = 4 << gm_bs;
-+    return true;
+     void *tag_mem;
-+}
-+
+-    ptr = QEMU_ALIGN_DOWN(ptr, LDGM_STGM_SIZE);
-+static bool trans_FAIL(DisasContext *s, arg_OK *a)
++    ptr = QEMU_ALIGN_DOWN(ptr, gm_bs_bytes);
-+{
-+    s->is_nonstreaming = true;
+     /* Trap if accessing an invalid page.  */
-+    return true;
+     tag_mem = allocation_tag_mem(env, mmu_idx, ptr, MMU_DATA_LOAD,
-+}
+-                                 LDGM_STGM_SIZE, MMU_DATA_LOAD,
-+
+-                                 LDGM_STGM_SIZE / (2 * TAG_GRANULE), ra);
- /**
++                                 gm_bs_bytes, MMU_DATA_LOAD,
-  * is_guarded_page:
++                                 gm_bs_bytes / (2 * TAG_GRANULE), ra);
-  * @env: The cpu environment
      /* The tag is squashed to zero if the page does not support tags.  */
      if (!tag_mem) {
          return 0;
      }
 -    QEMU_BUILD_BUG_ON(GMID_EL1_BS != 6);
      /*
 -     * We are loading 64-bits worth of tags.  The ordering of elements
 -     * within the word corresponds to a 64-bit little-endian operation.
 +     * The ordering of elements within the word corresponds to
 +     * a little-endian operation.
       */
 -    return ldq_le_p(tag_mem);
 +    switch (gm_bs) {
 +    case 6:
 +        /* 256 bytes -> 16 tags -> 64 result bits */
 +        return ldq_le_p(tag_mem);
 +    default:
 +        /* cpu configured with unsupported gm blocksize. */
 +        g_assert_not_reached();
 +    }
  }
  void HELPER(stgm)(CPUARMState *env, uint64_t ptr, uint64_t val)
  {
      int mmu_idx = cpu_mmu_index(env, false);
      uintptr_t ra = GETPC();
 +    int gm_bs = env_archcpu(env)->gm_blocksize;
 +    int gm_bs_bytes = 4 << gm_bs;
      void *tag_mem;
 -    ptr = QEMU_ALIGN_DOWN(ptr, LDGM_STGM_SIZE);
 +    ptr = QEMU_ALIGN_DOWN(ptr, gm_bs_bytes);
      /* Trap if accessing an invalid page.  */
      tag_mem = allocation_tag_mem(env, mmu_idx, ptr, MMU_DATA_STORE,
 -                                 LDGM_STGM_SIZE, MMU_DATA_LOAD,
 -                                 LDGM_STGM_SIZE / (2 * TAG_GRANULE), ra);
 +                                 gm_bs_bytes, MMU_DATA_LOAD,
 +                                 gm_bs_bytes / (2 * TAG_GRANULE), ra);
      /*
       * Tag store only happens if the page support tags,
@@ -XXX,XX +XXX,XX @@ void HELPER(stgm)(CPUARMState *env, uint64_t ptr, uint64_t val)
          return;
      }
 -    QEMU_BUILD_BUG_ON(GMID_EL1_BS != 6);
      /*
 -     * We are storing 64-bits worth of tags.  The ordering of elements
 -     * within the word corresponds to a 64-bit little-endian operation.
 +     * The ordering of elements within the word corresponds to
 +     * a little-endian operation.
       */
 -    stq_le_p(tag_mem, val);
 +    switch (gm_bs) {
 +    case 6:
 +        stq_le_p(tag_mem, val);
 +        break;
 +    default:
 +        /* cpu configured with unsupported gm blocksize. */
 +        g_assert_not_reached();
 +    }
  }
  void HELPER(stzgm_tags)(CPUARMState *env, uint64_t ptr, uint64_t val)
 diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/tcg/translate-a64.c
 +++ b/target/arm/tcg/translate-a64.c
@@ -XXX,XX +XXX,XX @@ static bool trans_STGM(DisasContext *s, arg_ldst_tag *a)
          gen_helper_stgm(cpu_env, addr, tcg_rt);
      } else {
          MMUAccessType acc = MMU_DATA_STORE;
 -        int size = 4 << GMID_EL1_BS;
 +        int size = 4 << s->gm_blocksize;
          clean_addr = clean_data_tbi(s, addr);
          tcg_gen_andi_i64(clean_addr, clean_addr, -size);
@@ -XXX,XX +XXX,XX @@ static bool trans_LDGM(DisasContext *s, arg_ldst_tag *a)
          gen_helper_ldgm(tcg_rt, cpu_env, addr);
      } else {
          MMUAccessType acc = MMU_DATA_LOAD;
 -        int size = 4 << GMID_EL1_BS;
 +        int size = 4 << s->gm_blocksize;
          clean_addr = clean_data_tbi(s, addr);
          tcg_gen_andi_i64(clean_addr, clean_addr, -size);
 @@ -XXX,XX +XXX,XX @@ static void aarch64_tr_init_disas_context(DisasContextBase *dcbase,
-     dc->mte_active[1] = EX_TBFLAG_A64(tb_flags, MTE0_ACTIVE);
-     dc->pstate_sm = EX_TBFLAG_A64(tb_flags, PSTATE_SM);
-     dc->pstate_za = EX_TBFLAG_A64(tb_flags, PSTATE_ZA);
-+    dc->sme_trap_nonstreaming = EX_TBFLAG_A64(tb_flags, SME_TRAP_NONSTREAMING);
-     dc->vec_len = 0;
-     dc->vec_stride = 0;
      dc->cp_regs = arm_cpu->cp_regs;
-@@ -XXX,XX +XXX,XX @@ static void aarch64_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu)
-         }
-     }
-+    s->is_nonstreaming = false;
-+    if (s->sme_trap_nonstreaming) {
-+        disas_sme_fa64(s, insn);
-+    }
-+
-     switch (extract32(insn, 25, 4)) {
-     case 0x0:
-         if (!extract32(insn, 31, 1) || !disas_sme(s, insn)) {
-diff --git a/target/arm/translate-vfp.c b/target/arm/translate-vfp.c
-index XXXXXXX..XXXXXXX 100644
---- a/target/arm/translate-vfp.c
-+++ b/target/arm/translate-vfp.c
-@@ -XXX,XX +XXX,XX @@ static bool vfp_access_check_a(DisasContext *s, bool ignore_vfp_enabled)
-         return false;
-     }
-+    /*
-+     * Note that rebuild_hflags_a32 has already accounted for being in EL0
-+     * and the higher EL in A64 mode, etc.  Unlike A64 mode, there do not
-+     * appear to be any insns which touch VFP which are allowed.
-+     */
-+    if (s->sme_trap_nonstreaming) {
-+        gen_exception_insn(s, s->pc_curr, EXCP_UDEF,
-+                           syn_smetrap(SME_ET_Streaming,
-+                                       s->base.pc_next - s->pc_curr == 2));
-+        return false;
-+    }
-+
-     if (!s->vfp_enabled && !ignore_vfp_enabled) {
-         assert(!arm_dc_feature(s, ARM_FEATURE_M));
-         unallocated_encoding(s);
-diff --git a/target/arm/translate.c b/target/arm/translate.c
-index XXXXXXX..XXXXXXX 100644
---- a/target/arm/translate.c
-+++ b/target/arm/translate.c
-@@ -XXX,XX +XXX,XX @@ static void arm_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs)
-             dc->vec_len = EX_TBFLAG_A32(tb_flags, VECLEN);
-             dc->vec_stride = EX_TBFLAG_A32(tb_flags, VECSTRIDE);
-         }
-+        dc->sme_trap_nonstreaming =
-+            EX_TBFLAG_A32(tb_flags, SME_TRAP_NONSTREAMING);
-     }
-     dc->cp_regs = cpu->cp_regs;
      dc->features = env->features;
-diff --git a/target/arm/meson.build b/target/arm/meson.build
+     dc->dcz_blocksize = arm_cpu->dcz_blocksize;
-index XXXXXXX..XXXXXXX 100644
++    dc->gm_blocksize = arm_cpu->gm_blocksize;
---- a/target/arm/meson.build
-+++ b/target/arm/meson.build
+ #ifdef CONFIG_USER_ONLY
-@@ -XXX,XX +XXX,XX @@
+     /* In sve_probe_page, we assume TBI is enabled. */
  gen = [
    decodetree.process('sve.decode', extra_args: '--decode=disas_sve'),
    decodetree.process('sme.decode', extra_args: '--decode=disas_sme'),
 +  decodetree.process('sme-fa64.decode', extra_args: '--static-decode=disas_sme_fa64'),
    decodetree.process('neon-shared.decode', extra_args: '--decode=disas_neon_shared'),
    decodetree.process('neon-dp.decode', extra_args: '--decode=disas_neon_dp'),
    decodetree.process('neon-ls.decode', extra_args: '--decode=disas_neon_ls'),
 --
-.25.1
+.34.1

-[PULL 44/45] target/arm: Enable SME for user-only
+[PULL 03/24] target/arm: Support more GM blocksizes
 From: Richard Henderson <richard.henderson@linaro.org>
-Enable SME, TPIDR2_EL0, and FA64 if supported by the cpu.
+Support all of the easy GM block sizes.
 Use direct memory operations, since the pointers are aligned.
+While BS=2 (16 bytes, 1 tag) is a legal setting, that requires
+an atomic store of one nibble.  This is not difficult, but there
+is also no point in supporting it until required.
+Note that cortex-a710 sets GM blocksize to match its cacheline
+size of 64 bytes.  I expect many implementations will also
+match the cacheline, which makes 16 bytes very unlikely.
+Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
 Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
-Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
+Message-id: 20230811214031.171020-4-richard.henderson@linaro.org
 Message-id: 20220708151540.18136-45-richard.henderson@linaro.org
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 ---
- target/arm/cpu.c | 11 +++++++++++
+ target/arm/cpu.c            | 18 +++++++++---
-file changed, 11 insertions(+)
+ target/arm/tcg/mte_helper.c | 56 +++++++++++++++++++++++++++++++------
 files changed, 62 insertions(+), 12 deletions(-)
 diff --git a/target/arm/cpu.c b/target/arm/cpu.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/cpu.c
 +++ b/target/arm/cpu.c
-@@ -XXX,XX +XXX,XX @@ static void arm_cpu_reset(DeviceState *dev)
+@@ -XXX,XX +XXX,XX @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp)
-                                              CPACR_EL1, ZEN, 3);
+                                        ID_PFR1, VIRTUALIZATION, 0);
-             env->vfp.zcr_el[1] = cpu->sve_default_vq - 1;
+     }
-         }
-+        /* and for SME instructions, with default vector length, and TPIDR2 */
++    if (cpu_isar_feature(aa64_mte, cpu)) {
-+        if (cpu_isar_feature(aa64_sme, cpu)) {
++        /*
-+            env->cp15.sctlr_el[1] |= SCTLR_EnTP2;
++         * The architectural range of GM blocksize is 2-6, however qemu
-+            env->cp15.cpacr_el1 = FIELD_DP64(env->cp15.cpacr_el1,
++         * doesn't support blocksize of 2 (see HELPER(ldgm)).
-+                                             CPACR_EL1, SMEN, 3);
++         */
-+            env->vfp.smcr_el[1] = cpu->sme_default_vq - 1;
++        if (tcg_enabled()) {
-+            if (cpu_isar_feature(aa64_sme_fa64, cpu)) {
++            assert(cpu->gm_blocksize >= 3 && cpu->gm_blocksize <= 6);
 +                env->vfp.smcr_el[1] = FIELD_DP64(env->vfp.smcr_el[1],
 +                                                 SMCR, FA64, 1);
 +            }
 +        }
++
+ #ifndef CONFIG_USER_ONLY
+-    if (cpu->tag_memory == NULL && cpu_isar_feature(aa64_mte, cpu)) {
          /*
-          * Enable 48-bit address space (TODO: take reserved_va into account).
+          * Disable the MTE feature bits if we do not have tag-memory
-          * Enable TBI0 but not TBI1.
+          * provided by the machine.
           */
 -        cpu->isar.id_aa64pfr1 =
 -            FIELD_DP64(cpu->isar.id_aa64pfr1, ID_AA64PFR1, MTE, 0);
 -    }
 +        if (cpu->tag_memory == NULL) {
 +            cpu->isar.id_aa64pfr1 =
 +                FIELD_DP64(cpu->isar.id_aa64pfr1, ID_AA64PFR1, MTE, 0);
 +        }
  #endif
 +    }
      if (tcg_enabled()) {
          /*
 diff --git a/target/arm/tcg/mte_helper.c b/target/arm/tcg/mte_helper.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/tcg/mte_helper.c
 +++ b/target/arm/tcg/mte_helper.c
@@ -XXX,XX +XXX,XX @@ uint64_t HELPER(ldgm)(CPUARMState *env, uint64_t ptr)
      int gm_bs = env_archcpu(env)->gm_blocksize;
      int gm_bs_bytes = 4 << gm_bs;
      void *tag_mem;
 +    uint64_t ret;
 +    int shift;
      ptr = QEMU_ALIGN_DOWN(ptr, gm_bs_bytes);
@@ -XXX,XX +XXX,XX @@ uint64_t HELPER(ldgm)(CPUARMState *env, uint64_t ptr)
      /*
       * The ordering of elements within the word corresponds to
 -     * a little-endian operation.
 +     * a little-endian operation.  Computation of shift comes from
 +     *
 +     *     index = address<LOG2_TAG_GRANULE+3:LOG2_TAG_GRANULE>
 +     *     data<index*4+3:index*4> = tag
 +     *
 +     * Because of the alignment of ptr above, BS=6 has shift=0.
 +     * All memory operations are aligned.  Defer support for BS=2,
 +     * requiring insertion or extraction of a nibble, until we
 +     * support a cpu that requires it.
       */
      switch (gm_bs) {
 +    case 3:
 +        /* 32 bytes -> 2 tags -> 8 result bits */
 +        ret = *(uint8_t *)tag_mem;
 +        break;
 +    case 4:
 +        /* 64 bytes -> 4 tags -> 16 result bits */
 +        ret = cpu_to_le16(*(uint16_t *)tag_mem);
 +        break;
 +    case 5:
 +        /* 128 bytes -> 8 tags -> 32 result bits */
 +        ret = cpu_to_le32(*(uint32_t *)tag_mem);
 +        break;
      case 6:
          /* 256 bytes -> 16 tags -> 64 result bits */
 -        return ldq_le_p(tag_mem);
 +        return cpu_to_le64(*(uint64_t *)tag_mem);
      default:
 -        /* cpu configured with unsupported gm blocksize. */
 +        /*
 +         * CPU configured with unsupported/invalid gm blocksize.
 +         * This is detected early in arm_cpu_realizefn.
 +         */
          g_assert_not_reached();
      }
 +    shift = extract64(ptr, LOG2_TAG_GRANULE, 4) * 4;
 +    return ret << shift;
  }
  void HELPER(stgm)(CPUARMState *env, uint64_t ptr, uint64_t val)
@@ -XXX,XX +XXX,XX @@ void HELPER(stgm)(CPUARMState *env, uint64_t ptr, uint64_t val)
      int gm_bs = env_archcpu(env)->gm_blocksize;
      int gm_bs_bytes = 4 << gm_bs;
      void *tag_mem;
 +    int shift;
      ptr = QEMU_ALIGN_DOWN(ptr, gm_bs_bytes);
@@ -XXX,XX +XXX,XX @@ void HELPER(stgm)(CPUARMState *env, uint64_t ptr, uint64_t val)
          return;
      }
 -    /*
 -     * The ordering of elements within the word corresponds to
 -     * a little-endian operation.
 -     */
 +    /* See LDGM for comments on BS and on shift.  */
 +    shift = extract64(ptr, LOG2_TAG_GRANULE, 4) * 4;
 +    val >>= shift;
      switch (gm_bs) {
 +    case 3:
 +        /* 32 bytes -> 2 tags -> 8 result bits */
 +        *(uint8_t *)tag_mem = val;
 +        break;
 +    case 4:
 +        /* 64 bytes -> 4 tags -> 16 result bits */
 +        *(uint16_t *)tag_mem = cpu_to_le16(val);
 +        break;
 +    case 5:
 +        /* 128 bytes -> 8 tags -> 32 result bits */
 +        *(uint32_t *)tag_mem = cpu_to_le32(val);
 +        break;
      case 6:
 -        stq_le_p(tag_mem, val);
 +        /* 256 bytes -> 16 tags -> 64 result bits */
 +        *(uint64_t *)tag_mem = cpu_to_le64(val);
          break;
      default:
          /* cpu configured with unsupported gm blocksize. */
 --
-.25.1
+.34.1

-[PULL 43/45] target/arm: Only set ZEN in reset if SVE present
+[PULL 04/24] target/arm: When tag memory is not present, set MTE=1
 From: Richard Henderson <richard.henderson@linaro.org>
-There's no reason to set CPACR_EL1.ZEN if SVE disabled.
+When the cpu support MTE, but the system does not, reduce cpu
 support to user instructions at EL0 instead of completely
 disabling MTE.  If we encounter a cpu implementation which does
 something else, we can revisit this setting.
+Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
 Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
-Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
+Message-id: 20230811214031.171020-5-richard.henderson@linaro.org
 Message-id: 20220708151540.18136-44-richard.henderson@linaro.org
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 ---
- target/arm/cpu.c | 7 +++----
+ target/arm/cpu.c | 7 ++++---
-file changed, 3 insertions(+), 4 deletions(-)
+file changed, 4 insertions(+), 3 deletions(-)
 diff --git a/target/arm/cpu.c b/target/arm/cpu.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/cpu.c
 +++ b/target/arm/cpu.c
-@@ -XXX,XX +XXX,XX @@ static void arm_cpu_reset(DeviceState *dev)
+@@ -XXX,XX +XXX,XX @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp)
-         /* and to the FP/Neon instructions */
-         env->cp15.cpacr_el1 = FIELD_DP64(env->cp15.cpacr_el1,
+ #ifndef CONFIG_USER_ONLY
-                                          CPACR_EL1, FPEN, 3);
+         /*
--        /* and to the SVE instructions */
+-         * Disable the MTE feature bits if we do not have tag-memory
--        env->cp15.cpacr_el1 = FIELD_DP64(env->cp15.cpacr_el1,
+-         * provided by the machine.
--                                         CPACR_EL1, ZEN, 3);
++         * If we do not have tag-memory provided by the machine,
--        /* with reasonable vector length */
++         * reduce MTE support to instructions enabled at EL0.
-+        /* and to the SVE instructions, with default vector length */
++         * This matches Cortex-A710 BROADCASTMTE input being LOW.
-         if (cpu_isar_feature(aa64_sve, cpu)) {
+          */
-+            env->cp15.cpacr_el1 = FIELD_DP64(env->cp15.cpacr_el1,
+         if (cpu->tag_memory == NULL) {
-+                                             CPACR_EL1, ZEN, 3);
+             cpu->isar.id_aa64pfr1 =
-             env->vfp.zcr_el[1] = cpu->sve_default_vq - 1;
+-                FIELD_DP64(cpu->isar.id_aa64pfr1, ID_AA64PFR1, MTE, 0);
 +                FIELD_DP64(cpu->isar.id_aa64pfr1, ID_AA64PFR1, MTE, 1);
          }
-         /*
+ #endif
      }
 --
-.25.1
+.34.1

-[PULL 30/45] target/arm: Implement SCLAMP, UCLAMP
+[PULL 05/24] target/arm: Introduce make_ccsidr64
 From: Richard Henderson <richard.henderson@linaro.org>
-This is an SVE instruction that operates using the SVE vector
+Do not hard-code the constants for Neoverse V1.
 length but that it is present only if SME is implemented.
+Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
 Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
-Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
+Message-id: 20230811214031.171020-6-richard.henderson@linaro.org
 Message-id: 20220708151540.18136-31-richard.henderson@linaro.org
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 ---
- target/arm/helper.h        |  18 +++++++
+ target/arm/tcg/cpu64.c | 48 ++++++++++++++++++++++++++++--------------
- target/arm/sve.decode      |   5 ++
+file changed, 32 insertions(+), 16 deletions(-)
  target/arm/translate-sve.c | 102 +++++++++++++++++++++++++++++++++++++
  target/arm/vec_helper.c    |  24 +++++++++
 files changed, 149 insertions(+)
-diff --git a/target/arm/helper.h b/target/arm/helper.h
+diff --git a/target/arm/tcg/cpu64.c b/target/arm/tcg/cpu64.c
 index XXXXXXX..XXXXXXX 100644
---- a/target/arm/helper.h
+--- a/target/arm/tcg/cpu64.c
-+++ b/target/arm/helper.h
++++ b/target/arm/tcg/cpu64.c
-@@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_6(gvec_bfmlal, TCG_CALL_NO_RWG,
+@@ -XXX,XX +XXX,XX @@
- DEF_HELPER_FLAGS_6(gvec_bfmlal_idx, TCG_CALL_NO_RWG,
+ #include "qemu/module.h"
-                    void, ptr, ptr, ptr, ptr, ptr, i32)
+ #include "qapi/visitor.h"
+ #include "hw/qdev-properties.h"
-+DEF_HELPER_FLAGS_5(gvec_sclamp_b, TCG_CALL_NO_RWG,
++#include "qemu/units.h"
-+                   void, ptr, ptr, ptr, ptr, i32)
+ #include "internals.h"
-+DEF_HELPER_FLAGS_5(gvec_sclamp_h, TCG_CALL_NO_RWG,
+ #include "cpregs.h"
-+                   void, ptr, ptr, ptr, ptr, i32)
-+DEF_HELPER_FLAGS_5(gvec_sclamp_s, TCG_CALL_NO_RWG,
++static uint64_t make_ccsidr64(unsigned assoc, unsigned linesize,
-+                   void, ptr, ptr, ptr, ptr, i32)
++                              unsigned cachesize)
-+DEF_HELPER_FLAGS_5(gvec_sclamp_d, TCG_CALL_NO_RWG,
++{
-+                   void, ptr, ptr, ptr, ptr, i32)
++    unsigned lg_linesize = ctz32(linesize);
 +    unsigned sets;
 +
-+DEF_HELPER_FLAGS_5(gvec_uclamp_b, TCG_CALL_NO_RWG,
++    /*
-+                   void, ptr, ptr, ptr, ptr, i32)
++     * The 64-bit CCSIDR_EL1 format is:
-+DEF_HELPER_FLAGS_5(gvec_uclamp_h, TCG_CALL_NO_RWG,
++     *   [55:32] number of sets - 1
-+                   void, ptr, ptr, ptr, ptr, i32)
++     *   [23:3]  associativity - 1
-+DEF_HELPER_FLAGS_5(gvec_uclamp_s, TCG_CALL_NO_RWG,
++     *   [2:0]   log2(linesize) - 4
-+                   void, ptr, ptr, ptr, ptr, i32)
++     *           so 0 == 16 bytes, 1 == 32 bytes, 2 == 64 bytes, etc
-+DEF_HELPER_FLAGS_5(gvec_uclamp_d, TCG_CALL_NO_RWG,
++     */
-+                   void, ptr, ptr, ptr, ptr, i32)
++    assert(assoc != 0);
 +    assert(is_power_of_2(linesize));
 +    assert(lg_linesize >= 4 && lg_linesize <= 7 + 4);
 +
- #ifdef TARGET_AARCH64
++    /* sets * associativity * linesize == cachesize. */
- #include "helper-a64.h"
++    sets = cachesize / (assoc * linesize);
- #include "helper-sve.h"
++    assert(cachesize % (assoc * linesize) == 0);
 diff --git a/target/arm/sve.decode b/target/arm/sve.decode
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/sve.decode
 +++ b/target/arm/sve.decode
@@ -XXX,XX +XXX,XX @@ PSEL            00100101 .. 1 100 .. 01 .... 0 .... 0 ....  \
                  @psel esz=2 imm=%psel_imm_s
  PSEL            00100101 .1 1 000 .. 01 .... 0 .... 0 ....  \
                  @psel esz=3 imm=%psel_imm_d
 +
-+### SVE clamp
++    return ((uint64_t)(sets - 1) << 32)
-+
++         | ((assoc - 1) << 3)
-+SCLAMP          01000100 .. 0 ..... 110000 ..... .....          @rda_rn_rm
++         | (lg_linesize - 4);
 +UCLAMP          01000100 .. 0 ..... 110001 ..... .....          @rda_rn_rm
 diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/translate-sve.c
 +++ b/target/arm/translate-sve.c
@@ -XXX,XX +XXX,XX @@ static bool trans_PSEL(DisasContext *s, arg_psel *a)
      tcg_temp_free_ptr(ptr);
      return true;
  }
 +
 +static void gen_sclamp_i32(TCGv_i32 d, TCGv_i32 n, TCGv_i32 m, TCGv_i32 a)
 +{
 +    tcg_gen_smax_i32(d, a, n);
 +    tcg_gen_smin_i32(d, d, m);
 +}
 +
-+static void gen_sclamp_i64(TCGv_i64 d, TCGv_i64 n, TCGv_i64 m, TCGv_i64 a)
+ static void aarch64_a35_initfn(Object *obj)
-+{
+ {
-+    tcg_gen_smax_i64(d, a, n);
+     ARMCPU *cpu = ARM_CPU(obj);
-+    tcg_gen_smin_i64(d, d, m);
+@@ -XXX,XX +XXX,XX @@ static void aarch64_neoverse_v1_initfn(Object *obj)
-+}
+      * The Neoverse-V1 r1p2 TRM lists 32-bit format CCSIDR_EL1 values,
-+
+      * but also says it implements CCIDX, which means they should be
-+static void gen_sclamp_vec(unsigned vece, TCGv_vec d, TCGv_vec n,
+      * 64-bit format. So we here use values which are based on the textual
-+                           TCGv_vec m, TCGv_vec a)
+-     * information in chapter 2 of the TRM (and on the fact that
-+{
+-     * sets * associativity * linesize == cachesize).
-+    tcg_gen_smax_vec(vece, d, a, n);
+-     *
-+    tcg_gen_smin_vec(vece, d, d, m);
+-     * The 64-bit CCSIDR_EL1 format is:
-+}
+-     *   [55:32] number of sets - 1
-+
+-     *   [23:3]  associativity - 1
-+static void gen_sclamp(unsigned vece, uint32_t d, uint32_t n, uint32_t m,
+-     *   [2:0]   log2(linesize) - 4
-+                       uint32_t a, uint32_t oprsz, uint32_t maxsz)
+-     *           so 0 == 16 bytes, 1 == 32 bytes, 2 == 64 bytes, etc
-+{
+-     *
-+    static const TCGOpcode vecop[] = {
+-     * L1: 4-way set associative 64-byte line size, total size 64K,
-+        INDEX_op_smin_vec, INDEX_op_smax_vec, 0
+-     * so sets is 256.
-+    };
++     * information in chapter 2 of the TRM:
-+    static const GVecGen4 ops[4] = {
+      *
-+        { .fniv = gen_sclamp_vec,
++     * L1: 4-way set associative 64-byte line size, total size 64K.
-+          .fno  = gen_helper_gvec_sclamp_b,
+      * L2: 8-way set associative, 64 byte line size, either 512K or 1MB.
-+          .opt_opc = vecop,
+-     * We pick 1MB, so this has 2048 sets.
-+          .vece = MO_8 },
+-     *
-+        { .fniv = gen_sclamp_vec,
+      * L3: No L3 (this matches the CLIDR_EL1 value).
-+          .fno  = gen_helper_gvec_sclamp_h,
+      */
-+          .opt_opc = vecop,
+-    cpu->ccsidr[0] = 0x000000ff0000001aull; /* 64KB L1 dcache */
-+          .vece = MO_16 },
+-    cpu->ccsidr[1] = 0x000000ff0000001aull; /* 64KB L1 icache */
-+        { .fni4 = gen_sclamp_i32,
+-    cpu->ccsidr[2] = 0x000007ff0000003aull; /* 1MB L2 cache */
-+          .fniv = gen_sclamp_vec,
++    cpu->ccsidr[0] = make_ccsidr64(4, 64, 64 * KiB); /* L1 dcache */
-+          .fno  = gen_helper_gvec_sclamp_s,
++    cpu->ccsidr[1] = cpu->ccsidr[0];                 /* L1 icache */
-+          .opt_opc = vecop,
++    cpu->ccsidr[2] = make_ccsidr64(8, 64, 1 * MiB);  /* L2 cache */
-+          .vece = MO_32 },
-+        { .fni8 = gen_sclamp_i64,
+     /* From 3.2.115 SCTLR_EL3 */
-+          .fniv = gen_sclamp_vec,
+     cpu->reset_sctlr = 0x30c50838;
 +          .fno  = gen_helper_gvec_sclamp_d,
 +          .opt_opc = vecop,
 +          .vece = MO_64,
 +          .prefer_i64 = TCG_TARGET_REG_BITS == 64 }
 +    };
 +    tcg_gen_gvec_4(d, n, m, a, oprsz, maxsz, &ops[vece]);
 +}
 +
 +TRANS_FEAT(SCLAMP, aa64_sme, gen_gvec_fn_arg_zzzz, gen_sclamp, a)
 +
 +static void gen_uclamp_i32(TCGv_i32 d, TCGv_i32 n, TCGv_i32 m, TCGv_i32 a)
 +{
 +    tcg_gen_umax_i32(d, a, n);
 +    tcg_gen_umin_i32(d, d, m);
 +}
 +
 +static void gen_uclamp_i64(TCGv_i64 d, TCGv_i64 n, TCGv_i64 m, TCGv_i64 a)
 +{
 +    tcg_gen_umax_i64(d, a, n);
 +    tcg_gen_umin_i64(d, d, m);
 +}
 +
 +static void gen_uclamp_vec(unsigned vece, TCGv_vec d, TCGv_vec n,
 +                           TCGv_vec m, TCGv_vec a)
 +{
 +    tcg_gen_umax_vec(vece, d, a, n);
 +    tcg_gen_umin_vec(vece, d, d, m);
 +}
 +
 +static void gen_uclamp(unsigned vece, uint32_t d, uint32_t n, uint32_t m,
 +                       uint32_t a, uint32_t oprsz, uint32_t maxsz)
 +{
 +    static const TCGOpcode vecop[] = {
 +        INDEX_op_umin_vec, INDEX_op_umax_vec, 0
 +    };
 +    static const GVecGen4 ops[4] = {
 +        { .fniv = gen_uclamp_vec,
 +          .fno  = gen_helper_gvec_uclamp_b,
 +          .opt_opc = vecop,
 +          .vece = MO_8 },
 +        { .fniv = gen_uclamp_vec,
 +          .fno  = gen_helper_gvec_uclamp_h,
 +          .opt_opc = vecop,
 +          .vece = MO_16 },
 +        { .fni4 = gen_uclamp_i32,
 +          .fniv = gen_uclamp_vec,
 +          .fno  = gen_helper_gvec_uclamp_s,
 +          .opt_opc = vecop,
 +          .vece = MO_32 },
 +        { .fni8 = gen_uclamp_i64,
 +          .fniv = gen_uclamp_vec,
 +          .fno  = gen_helper_gvec_uclamp_d,
 +          .opt_opc = vecop,
 +          .vece = MO_64,
 +          .prefer_i64 = TCG_TARGET_REG_BITS == 64 }
 +    };
 +    tcg_gen_gvec_4(d, n, m, a, oprsz, maxsz, &ops[vece]);
 +}
 +
 +TRANS_FEAT(UCLAMP, aa64_sme, gen_gvec_fn_arg_zzzz, gen_uclamp, a)
 diff --git a/target/arm/vec_helper.c b/target/arm/vec_helper.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/vec_helper.c
 +++ b/target/arm/vec_helper.c
@@ -XXX,XX +XXX,XX @@ void HELPER(gvec_bfmlal_idx)(void *vd, void *vn, void *vm,
      }
      clear_tail(d, opr_sz, simd_maxsz(desc));
  }
 +
 +#define DO_CLAMP(NAME, TYPE) \
 +void HELPER(NAME)(void *d, void *n, void *m, void *a, uint32_t desc)    \
 +{                                                                       \
 +    intptr_t i, opr_sz = simd_oprsz(desc);                              \
 +    for (i = 0; i < opr_sz; i += sizeof(TYPE)) {                        \
 +        TYPE aa = *(TYPE *)(a + i);                                     \
 +        TYPE nn = *(TYPE *)(n + i);                                     \
 +        TYPE mm = *(TYPE *)(m + i);                                     \
 +        TYPE dd = MIN(MAX(aa, nn), mm);                                 \
 +        *(TYPE *)(d + i) = dd;                                          \
 +    }                                                                   \
 +    clear_tail(d, opr_sz, simd_maxsz(desc));                            \
 +}
 +
 +DO_CLAMP(gvec_sclamp_b, int8_t)
 +DO_CLAMP(gvec_sclamp_h, int16_t)
 +DO_CLAMP(gvec_sclamp_s, int32_t)
 +DO_CLAMP(gvec_sclamp_d, int64_t)
 +
 +DO_CLAMP(gvec_uclamp_b, uint8_t)
 +DO_CLAMP(gvec_uclamp_h, uint16_t)
 +DO_CLAMP(gvec_uclamp_s, uint32_t)
 +DO_CLAMP(gvec_uclamp_d, uint64_t)
 --
-.25.1
+.34.1

-[PULL 31/45] target/arm: Reset streaming sve state on exception boundaries
+[PULL 06/24] target/arm: Apply access checks to neoverse-n1 special registers
 From: Richard Henderson <richard.henderson@linaro.org>
-We can handle both exception entry and exception return by
+Access to many of the special registers is enabled or disabled
-hooking into aarch64_sve_change_el.
+by ACTLR_EL[23], which we implement as constant 0, which means
 that all writes outside EL3 should trap.
+Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
 Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
-Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
+Message-id: 20230811214031.171020-7-richard.henderson@linaro.org
 Message-id: 20220708151540.18136-32-richard.henderson@linaro.org
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 ---
- target/arm/helper.c | 15 +++++++++++++--
+ target/arm/cpregs.h    |  2 ++
-file changed, 13 insertions(+), 2 deletions(-)
+ target/arm/helper.c    |  4 ++--
  target/arm/tcg/cpu64.c | 46 +++++++++++++++++++++++++++++++++---------
 files changed, 41 insertions(+), 11 deletions(-)
+diff --git a/target/arm/cpregs.h b/target/arm/cpregs.h
+index XXXXXXX..XXXXXXX 100644
+--- a/target/arm/cpregs.h
++++ b/target/arm/cpregs.h
+@@ -XXX,XX +XXX,XX @@ static inline void define_cortex_a72_a57_a53_cp_reginfo(ARMCPU *cpu) { }
+ void define_cortex_a72_a57_a53_cp_reginfo(ARMCPU *cpu);
+ #endif
++CPAccessResult access_tvm_trvm(CPUARMState *, const ARMCPRegInfo *, bool);
++
+ #endif /* TARGET_ARM_CPREGS_H */
 diff --git a/target/arm/helper.c b/target/arm/helper.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/helper.c
 +++ b/target/arm/helper.c
-@@ -XXX,XX +XXX,XX @@ void aarch64_sve_change_el(CPUARMState *env, int old_el,
+@@ -XXX,XX +XXX,XX @@ static CPAccessResult access_tpm(CPUARMState *env, const ARMCPRegInfo *ri,
-         return;
+ }
-     }
+ /* Check for traps from EL1 due to HCR_EL2.TVM and HCR_EL2.TRVM.  */
-+    old_a64 = old_el ? arm_el_is_aa64(env, old_el) : el0_a64;
+-static CPAccessResult access_tvm_trvm(CPUARMState *env, const ARMCPRegInfo *ri,
-+    new_a64 = new_el ? arm_el_is_aa64(env, new_el) : el0_a64;
+-                                      bool isread)
 +CPAccessResult access_tvm_trvm(CPUARMState *env, const ARMCPRegInfo *ri,
 +                               bool isread)
  {
      if (arm_current_el(env) == 1) {
          uint64_t trap = isread ? HCR_TRVM : HCR_TVM;
 diff --git a/target/arm/tcg/cpu64.c b/target/arm/tcg/cpu64.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/tcg/cpu64.c
 +++ b/target/arm/tcg/cpu64.c
@@ -XXX,XX +XXX,XX @@ static void aarch64_a64fx_initfn(Object *obj)
      /* TODO:  Add A64FX specific HPC extension registers */
  }
 +static CPAccessResult access_actlr_w(CPUARMState *env, const ARMCPRegInfo *r,
 +                                     bool read)
 +{
 +    if (!read) {
 +        int el = arm_current_el(env);
 +
-+    /*
++        /* Because ACTLR_EL2 is constant 0, writes below EL2 trap to EL2. */
-+     * Both AArch64.TakeException and AArch64.ExceptionReturn
++        if (el < 2 && arm_is_el2_enabled(env)) {
-+     * invoke ResetSVEState when taking an exception from, or
++            return CP_ACCESS_TRAP_EL2;
-+     * returning to, AArch32 state when PSTATE.SM is enabled.
++        }
-+     */
++        /* Because ACTLR_EL3 is constant 0, writes below EL3 trap to EL3. */
-+    if (old_a64 != new_a64 && FIELD_EX64(env->svcr, SVCR, SM)) {
++        if (el < 3 && arm_feature(env, ARM_FEATURE_EL3)) {
-+        arm_reset_sve_state(env);
++            return CP_ACCESS_TRAP_EL3;
-+        return;
++        }
 +    }
++    return CP_ACCESS_OK;
++}
 +
+ static const ARMCPRegInfo neoverse_n1_cp_reginfo[] = {
+     { .name = "ATCR_EL1", .state = ARM_CP_STATE_AA64,
+       .opc0 = 3, .opc1 = 0, .crn = 15, .crm = 7, .opc2 = 0,
+-      .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
++      .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0,
++      /* Traps and enables are the same as for TCR_EL1. */
++      .accessfn = access_tvm_trvm, .fgt = FGT_TCR_EL1, },
+     { .name = "ATCR_EL2", .state = ARM_CP_STATE_AA64,
+       .opc0 = 3, .opc1 = 4, .crn = 15, .crm = 7, .opc2 = 0,
+       .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
+@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo neoverse_n1_cp_reginfo[] = {
+       .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
+     { .name = "CPUACTLR_EL1", .state = ARM_CP_STATE_AA64,
+       .opc0 = 3, .opc1 = 0, .crn = 15, .crm = 1, .opc2 = 0,
+-      .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
++      .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0,
++      .accessfn = access_actlr_w },
+     { .name = "CPUACTLR2_EL1", .state = ARM_CP_STATE_AA64,
+       .opc0 = 3, .opc1 = 0, .crn = 15, .crm = 1, .opc2 = 1,
+-      .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
++      .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0,
++      .accessfn = access_actlr_w },
+     { .name = "CPUACTLR3_EL1", .state = ARM_CP_STATE_AA64,
+       .opc0 = 3, .opc1 = 0, .crn = 15, .crm = 1, .opc2 = 2,
+-      .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
++      .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0,
++      .accessfn = access_actlr_w },
      /*
-      * DDI0584A.d sec 3.2: "If SVE instructions are disabled or trapped
+      * Report CPUCFR_EL1.SCU as 1, as we do not implement the DSU
-      * at ELx, or not available because the EL is in AArch32 state, then
+      * (and in particular its system registers).
-@@ -XXX,XX +XXX,XX @@ void aarch64_sve_change_el(CPUARMState *env, int old_el,
+@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo neoverse_n1_cp_reginfo[] = {
-      * we already have the correct register contents when encountering the
+       .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 4 },
-      * vq0->vq0 transition between EL0->EL1.
+     { .name = "CPUECTLR_EL1", .state = ARM_CP_STATE_AA64,
-      */
+       .opc0 = 3, .opc1 = 0, .crn = 15, .crm = 1, .opc2 = 4,
--    old_a64 = old_el ? arm_el_is_aa64(env, old_el) : el0_a64;
+-      .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0x961563010 },
-     old_len = (old_a64 && !sve_exception_el(env, old_el)
++      .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0x961563010,
-                ? sve_vqm1_for_el(env, old_el) : 0);
++      .accessfn = access_actlr_w },
--    new_a64 = new_el ? arm_el_is_aa64(env, new_el) : el0_a64;
+     { .name = "CPUPCR_EL3", .state = ARM_CP_STATE_AA64,
-     new_len = (new_a64 && !sve_exception_el(env, new_el)
+       .opc0 = 3, .opc1 = 6, .crn = 15, .crm = 8, .opc2 = 1,
-                ? sve_vqm1_for_el(env, new_el) : 0);
+       .access = PL3_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
+@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo neoverse_n1_cp_reginfo[] = {
        .access = PL3_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
      { .name = "CPUPWRCTLR_EL1", .state = ARM_CP_STATE_AA64,
        .opc0 = 3, .opc1 = 0, .crn = 15, .crm = 2, .opc2 = 7,
 -      .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
 +      .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0,
 +      .accessfn = access_actlr_w },
      { .name = "ERXPFGCDN_EL1", .state = ARM_CP_STATE_AA64,
        .opc0 = 3, .opc1 = 0, .crn = 15, .crm = 2, .opc2 = 2,
 -      .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
 +      .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0,
 +      .accessfn = access_actlr_w },
      { .name = "ERXPFGCTL_EL1", .state = ARM_CP_STATE_AA64,
        .opc0 = 3, .opc1 = 0, .crn = 15, .crm = 2, .opc2 = 1,
 -      .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
 +      .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0,
 +      .accessfn = access_actlr_w },
      { .name = "ERXPFGF_EL1", .state = ARM_CP_STATE_AA64,
        .opc0 = 3, .opc1 = 0, .crn = 15, .crm = 2, .opc2 = 0,
 -      .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
 +      .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0,
 +      .accessfn = access_actlr_w },
  };
  static void define_neoverse_n1_cp_reginfo(ARMCPU *cpu)
 --
-.25.1
+.34.1

-[PULL 41/45] linux-user: Rename sve prctls
+[PULL 07/24] target/arm: Apply access checks to neoverse-v1 special registers
 From: Richard Henderson <richard.henderson@linaro.org>
-Add "sve" to the sve prctl functions, to distinguish
+There is only one additional EL1 register modeled, which
-them from the coming "sme" prctls with similar names.
+also needs to use access_actlr_w.
+Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
 Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
-Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
+Message-id: 20230811214031.171020-8-richard.henderson@linaro.org
 Message-id: 20220708151540.18136-42-richard.henderson@linaro.org
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 ---
- linux-user/aarch64/target_prctl.h |  8 ++++----
+ target/arm/tcg/cpu64.c | 3 ++-
- linux-user/syscall.c              | 12 ++++++------
+file changed, 2 insertions(+), 1 deletion(-)
 files changed, 10 insertions(+), 10 deletions(-)
-diff --git a/linux-user/aarch64/target_prctl.h b/linux-user/aarch64/target_prctl.h
+diff --git a/target/arm/tcg/cpu64.c b/target/arm/tcg/cpu64.c
 index XXXXXXX..XXXXXXX 100644
---- a/linux-user/aarch64/target_prctl.h
+--- a/target/arm/tcg/cpu64.c
-+++ b/linux-user/aarch64/target_prctl.h
++++ b/target/arm/tcg/cpu64.c
-@@ -XXX,XX +XXX,XX @@
+@@ -XXX,XX +XXX,XX @@ static void define_neoverse_n1_cp_reginfo(ARMCPU *cpu)
- #ifndef AARCH64_TARGET_PRCTL_H
+ static const ARMCPRegInfo neoverse_v1_cp_reginfo[] = {
- #define AARCH64_TARGET_PRCTL_H
+     { .name = "CPUECTLR2_EL1", .state = ARM_CP_STATE_AA64,
+       .opc0 = 3, .opc1 = 0, .crn = 15, .crm = 1, .opc2 = 5,
--static abi_long do_prctl_get_vl(CPUArchState *env)
+-      .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
-+static abi_long do_prctl_sve_get_vl(CPUArchState *env)
++      .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0,
- {
++      .accessfn = access_actlr_w },
-     ARMCPU *cpu = env_archcpu(env);
+     { .name = "CPUPPMCR_EL3", .state = ARM_CP_STATE_AA64,
-     if (cpu_isar_feature(aa64_sve, cpu)) {
+       .opc0 = 3, .opc1 = 6, .crn = 15, .crm = 2, .opc2 = 0,
-@@ -XXX,XX +XXX,XX @@ static abi_long do_prctl_get_vl(CPUArchState *env)
+       .access = PL3_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
      }
      return -TARGET_EINVAL;
  }
 -#define do_prctl_get_vl do_prctl_get_vl
 +#define do_prctl_sve_get_vl do_prctl_sve_get_vl
 -static abi_long do_prctl_set_vl(CPUArchState *env, abi_long arg2)
 +static abi_long do_prctl_sve_set_vl(CPUArchState *env, abi_long arg2)
  {
      /*
       * We cannot support either PR_SVE_SET_VL_ONEXEC or PR_SVE_VL_INHERIT.
@@ -XXX,XX +XXX,XX @@ static abi_long do_prctl_set_vl(CPUArchState *env, abi_long arg2)
      }
      return -TARGET_EINVAL;
  }
 -#define do_prctl_set_vl do_prctl_set_vl
 +#define do_prctl_sve_set_vl do_prctl_sve_set_vl
  static abi_long do_prctl_reset_keys(CPUArchState *env, abi_long arg2)
  {
 diff --git a/linux-user/syscall.c b/linux-user/syscall.c
 index XXXXXXX..XXXXXXX 100644
 --- a/linux-user/syscall.c
 +++ b/linux-user/syscall.c
@@ -XXX,XX +XXX,XX @@ static abi_long do_prctl_inval1(CPUArchState *env, abi_long arg2)
  #ifndef do_prctl_set_fp_mode
  #define do_prctl_set_fp_mode do_prctl_inval1
  #endif
 -#ifndef do_prctl_get_vl
 -#define do_prctl_get_vl do_prctl_inval0
 +#ifndef do_prctl_sve_get_vl
 +#define do_prctl_sve_get_vl do_prctl_inval0
  #endif
 -#ifndef do_prctl_set_vl
 -#define do_prctl_set_vl do_prctl_inval1
 +#ifndef do_prctl_sve_set_vl
 +#define do_prctl_sve_set_vl do_prctl_inval1
  #endif
  #ifndef do_prctl_reset_keys
  #define do_prctl_reset_keys do_prctl_inval1
@@ -XXX,XX +XXX,XX @@ static abi_long do_prctl(CPUArchState *env, abi_long option, abi_long arg2,
      case PR_SET_FP_MODE:
          return do_prctl_set_fp_mode(env, arg2);
      case PR_SVE_GET_VL:
 -        return do_prctl_get_vl(env);
 +        return do_prctl_sve_get_vl(env);
      case PR_SVE_SET_VL:
 -        return do_prctl_set_vl(env, arg2);
 +        return do_prctl_sve_set_vl(env, arg2);
      case PR_PAC_RESET_KEYS:
          if (arg3 || arg4 || arg5) {
              return -TARGET_EINVAL;
 --
-.25.1
+.34.1

-[PULL 01/45] target/arm: Handle SME in aarch64_cpu_dump_state
+[PULL 08/24] target/arm: Suppress FEAT_TRBE (Trace Buffer Extension)
 From: Richard Henderson <richard.henderson@linaro.org>
-Dump SVCR, plus use the correct access check for Streaming Mode.
+Like FEAT_TRF (Self-hosted Trace Extension), suppress tracing
 external to the cpu, which is out of scope for QEMU.
+Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
 Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
-Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
+Message-id: 20230811214031.171020-10-richard.henderson@linaro.org
 Message-id: 20220708151540.18136-2-richard.henderson@linaro.org
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 ---
- target/arm/cpu.c | 17 ++++++++++++++++-
+ target/arm/cpu.c | 3 +++
-file changed, 16 insertions(+), 1 deletion(-)
+file changed, 3 insertions(+)
 diff --git a/target/arm/cpu.c b/target/arm/cpu.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/cpu.c
 +++ b/target/arm/cpu.c
-@@ -XXX,XX +XXX,XX @@ static void aarch64_cpu_dump_state(CPUState *cs, FILE *f, int flags)
+@@ -XXX,XX +XXX,XX @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp)
-     int i;
+         /* FEAT_SPE (Statistical Profiling Extension) */
-     int el = arm_current_el(env);
+         cpu->isar.id_aa64dfr0 =
-     const char *ns_status;
+             FIELD_DP64(cpu->isar.id_aa64dfr0, ID_AA64DFR0, PMSVER, 0);
-+    bool sve;
++        /* FEAT_TRBE (Trace Buffer Extension) */
++        cpu->isar.id_aa64dfr0 =
-     qemu_fprintf(f, " PC=%016" PRIx64 " ", env->pc);
++            FIELD_DP64(cpu->isar.id_aa64dfr0, ID_AA64DFR0, TRACEBUFFER, 0);
-     for (i = 0; i < 32; i++) {
+         /* FEAT_TRF (Self-hosted Trace Extension) */
-@@ -XXX,XX +XXX,XX @@ static void aarch64_cpu_dump_state(CPUState *cs, FILE *f, int flags)
+         cpu->isar.id_aa64dfr0 =
-                  el,
+             FIELD_DP64(cpu->isar.id_aa64dfr0, ID_AA64DFR0, TRACEFILT, 0);
                   psr & PSTATE_SP ? 'h' : 't');
 +    if (cpu_isar_feature(aa64_sme, cpu)) {
 +        qemu_fprintf(f, "  SVCR=%08" PRIx64 " %c%c",
 +                     env->svcr,
 +                     (FIELD_EX64(env->svcr, SVCR, ZA) ? 'Z' : '-'),
 +                     (FIELD_EX64(env->svcr, SVCR, SM) ? 'S' : '-'));
 +    }
      if (cpu_isar_feature(aa64_bti, cpu)) {
          qemu_fprintf(f, "  BTYPE=%d", (psr & PSTATE_BTYPE) >> 10);
      }
@@ -XXX,XX +XXX,XX @@ static void aarch64_cpu_dump_state(CPUState *cs, FILE *f, int flags)
      qemu_fprintf(f, "     FPCR=%08x FPSR=%08x\n",
                   vfp_get_fpcr(env), vfp_get_fpsr(env));
 -    if (cpu_isar_feature(aa64_sve, cpu) && sve_exception_el(env, el) == 0) {
 +    if (cpu_isar_feature(aa64_sme, cpu) && FIELD_EX64(env->svcr, SVCR, SM)) {
 +        sve = sme_exception_el(env, el) == 0;
 +    } else if (cpu_isar_feature(aa64_sve, cpu)) {
 +        sve = sve_exception_el(env, el) == 0;
 +    } else {
 +        sve = false;
 +    }
 +
 +    if (sve) {
          int j, zcr_len = sve_vqm1_for_el(env, el);
          for (i = 0; i <= FFR_PRED_NUM; i++) {
 --
-.25.1
+.34.1

-[PULL 38/45] linux-user/aarch64: Verify extra record lock succeeded
+[PULL 09/24] target/arm: Implement FEAT_HPDS2 as a no-op
 From: Richard Henderson <richard.henderson@linaro.org>
+This feature allows the operating system to set TCR_ELx.HWU*
+to allow the implementation to use the PBHA bits from the
+block and page descriptors for for IMPLEMENTATION DEFINED
+purposes.  Since QEMU has no need to use these bits, we may
+simply ignore them.
+Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
 Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
-Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
+Message-id: 20230811214031.171020-11-richard.henderson@linaro.org
 Message-id: 20220708151540.18136-39-richard.henderson@linaro.org
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 ---
- linux-user/aarch64/signal.c | 3 +++
+ docs/system/arm/emulation.rst | 1 +
-file changed, 3 insertions(+)
+ target/arm/tcg/cpu32.c        | 2 +-
  target/arm/tcg/cpu64.c        | 2 +-
 files changed, 3 insertions(+), 2 deletions(-)
-diff --git a/linux-user/aarch64/signal.c b/linux-user/aarch64/signal.c
+diff --git a/docs/system/arm/emulation.rst b/docs/system/arm/emulation.rst
 index XXXXXXX..XXXXXXX 100644
---- a/linux-user/aarch64/signal.c
+--- a/docs/system/arm/emulation.rst
-+++ b/linux-user/aarch64/signal.c
++++ b/docs/system/arm/emulation.rst
-@@ -XXX,XX +XXX,XX @@ static int target_restore_sigframe(CPUARMState *env,
+@@ -XXX,XX +XXX,XX @@ the following architecture extensions:
-             __get_user(extra_size,
+ - FEAT_HAFDBS (Hardware management of the access flag and dirty bit state)
-                        &((struct target_extra_context *)ctx)->size);
+ - FEAT_HCX (Support for the HCRX_EL2 register)
-             extra = lock_user(VERIFY_READ, extra_datap, extra_size, 0);
+ - FEAT_HPDS (Hierarchical permission disables)
-+            if (!extra) {
++- FEAT_HPDS2 (Translation table page-based hardware attributes)
-+                return 1;
+ - FEAT_I8MM (AArch64 Int8 matrix multiplication instructions)
-+            }
+ - FEAT_IDST (ID space trap handling)
-             break;
+ - FEAT_IESB (Implicit error synchronization event)
+diff --git a/target/arm/tcg/cpu32.c b/target/arm/tcg/cpu32.c
-         default:
+index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/tcg/cpu32.c
 +++ b/target/arm/tcg/cpu32.c
@@ -XXX,XX +XXX,XX @@ void aa32_max_features(ARMCPU *cpu)
      cpu->isar.id_mmfr3 = t;
      t = cpu->isar.id_mmfr4;
 -    t = FIELD_DP32(t, ID_MMFR4, HPDS, 1);         /* FEAT_AA32HPD */
 +    t = FIELD_DP32(t, ID_MMFR4, HPDS, 2);         /* FEAT_HPDS2 */
      t = FIELD_DP32(t, ID_MMFR4, AC2, 1);          /* ACTLR2, HACTLR2 */
      t = FIELD_DP32(t, ID_MMFR4, CNP, 1);          /* FEAT_TTCNP */
      t = FIELD_DP32(t, ID_MMFR4, XNX, 1);          /* FEAT_XNX */
 diff --git a/target/arm/tcg/cpu64.c b/target/arm/tcg/cpu64.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/tcg/cpu64.c
 +++ b/target/arm/tcg/cpu64.c
@@ -XXX,XX +XXX,XX @@ void aarch64_max_tcg_initfn(Object *obj)
      t = FIELD_DP64(t, ID_AA64MMFR1, HAFDBS, 2);   /* FEAT_HAFDBS */
      t = FIELD_DP64(t, ID_AA64MMFR1, VMIDBITS, 2); /* FEAT_VMID16 */
      t = FIELD_DP64(t, ID_AA64MMFR1, VH, 1);       /* FEAT_VHE */
 -    t = FIELD_DP64(t, ID_AA64MMFR1, HPDS, 1);     /* FEAT_HPDS */
 +    t = FIELD_DP64(t, ID_AA64MMFR1, HPDS, 2);     /* FEAT_HPDS2 */
      t = FIELD_DP64(t, ID_AA64MMFR1, LO, 1);       /* FEAT_LOR */
      t = FIELD_DP64(t, ID_AA64MMFR1, PAN, 3);      /* FEAT_PAN3 */
      t = FIELD_DP64(t, ID_AA64MMFR1, XNX, 1);      /* FEAT_XNX */
 --
-.25.1
+.34.1

-[PULL 32/45] target/arm: Enable SME for -cpu max
+[PULL 10/24] target/arm: properly document FEAT_CRC32
-From: Richard Henderson <richard.henderson@linaro.org>
+From: Alex Bennée <alex.bennee@linaro.org>
-Note that SME remains effectively disabled for user-only,
+This is a mandatory feature for Armv8.1 architectures but we don't
-because we do not yet set CPACR_EL1.SMEN.  This needs to
+state the feature clearly in our emulation list. Also include
-wait until the kernel ABI is implemented.
+FEAT_CRC32 comment in aarch64_max_tcg_initfn for ease of grepping.
-Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
+Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
-Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
+Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
-Message-id: 20220708151540.18136-33-richard.henderson@linaro.org
+Message-id: 20230824075406.1515566-1-alex.bennee@linaro.org
 Cc: qemu-stable@nongnu.org
 Message-Id: <20230222110104.3996971-1-alex.bennee@linaro.org>
 [PMM: pluralize 'instructions' in docs]
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 ---
- docs/system/arm/emulation.rst |  4 ++++
+ docs/system/arm/emulation.rst | 1 +
- target/arm/cpu64.c            | 11 +++++++++++
+ target/arm/tcg/cpu64.c        | 2 +-
-files changed, 15 insertions(+)
+files changed, 2 insertions(+), 1 deletion(-)
 diff --git a/docs/system/arm/emulation.rst b/docs/system/arm/emulation.rst
 index XXXXXXX..XXXXXXX 100644
 --- a/docs/system/arm/emulation.rst
 +++ b/docs/system/arm/emulation.rst
 @@ -XXX,XX +XXX,XX @@ the following architecture extensions:
- - FEAT_SHA512 (Advanced SIMD SHA512 instructions)
+ - FEAT_BBM at level 2 (Translation table break-before-make levels)
- - FEAT_SM3 (Advanced SIMD SM3 instructions)
+ - FEAT_BF16 (AArch64 BFloat16 instructions)
- - FEAT_SM4 (Advanced SIMD SM4 instructions)
+ - FEAT_BTI (Branch Target Identification)
-+- FEAT_SME (Scalable Matrix Extension)
++- FEAT_CRC32 (CRC32 instructions)
-+- FEAT_SME_FA64 (Full A64 instruction set in Streaming SVE mode)
+ - FEAT_CSV2 (Cache speculation variant 2)
-+- FEAT_SME_F64F64 (Double-precision floating-point outer product instructions)
+ - FEAT_CSV2_1p1 (Cache speculation variant 2, version 1.1)
-+- FEAT_SME_I16I64 (16-bit to 64-bit integer widening outer product instructions)
+ - FEAT_CSV2_1p2 (Cache speculation variant 2, version 1.2)
- - FEAT_SPECRES (Speculation restriction instructions)
+diff --git a/target/arm/tcg/cpu64.c b/target/arm/tcg/cpu64.c
  - FEAT_SSBS (Speculative Store Bypass Safe)
  - FEAT_TLBIOS (TLB invalidate instructions in Outer Shareable domain)
 diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
 index XXXXXXX..XXXXXXX 100644
---- a/target/arm/cpu64.c
+--- a/target/arm/tcg/cpu64.c
-+++ b/target/arm/cpu64.c
++++ b/target/arm/tcg/cpu64.c
-@@ -XXX,XX +XXX,XX @@ static void aarch64_max_initfn(Object *obj)
+@@ -XXX,XX +XXX,XX @@ void aarch64_max_tcg_initfn(Object *obj)
-      */
+     t = FIELD_DP64(t, ID_AA64ISAR0, AES, 2);      /* FEAT_PMULL */
-     t = FIELD_DP64(t, ID_AA64PFR1, MTE, 3);       /* FEAT_MTE3 */
+     t = FIELD_DP64(t, ID_AA64ISAR0, SHA1, 1);     /* FEAT_SHA1 */
-     t = FIELD_DP64(t, ID_AA64PFR1, RAS_FRAC, 0);  /* FEAT_RASv1p1 + FEAT_DoubleFault */
+     t = FIELD_DP64(t, ID_AA64ISAR0, SHA2, 2);     /* FEAT_SHA512 */
-+    t = FIELD_DP64(t, ID_AA64PFR1, SME, 1);       /* FEAT_SME */
+-    t = FIELD_DP64(t, ID_AA64ISAR0, CRC32, 1);
-     t = FIELD_DP64(t, ID_AA64PFR1, CSV2_FRAC, 0); /* FEAT_CSV2_2 */
++    t = FIELD_DP64(t, ID_AA64ISAR0, CRC32, 1);    /* FEAT_CRC32 */
-     cpu->isar.id_aa64pfr1 = t;
+     t = FIELD_DP64(t, ID_AA64ISAR0, ATOMIC, 2);   /* FEAT_LSE */
+     t = FIELD_DP64(t, ID_AA64ISAR0, RDM, 1);      /* FEAT_RDM */
-@@ -XXX,XX +XXX,XX @@ static void aarch64_max_initfn(Object *obj)
+     t = FIELD_DP64(t, ID_AA64ISAR0, SHA3, 1);     /* FEAT_SHA3 */
      t = FIELD_DP64(t, ID_AA64DFR0, PMUVER, 5);    /* FEAT_PMUv3p4 */
      cpu->isar.id_aa64dfr0 = t;
 +    t = cpu->isar.id_aa64smfr0;
 +    t = FIELD_DP64(t, ID_AA64SMFR0, F32F32, 1);   /* FEAT_SME */
 +    t = FIELD_DP64(t, ID_AA64SMFR0, B16F32, 1);   /* FEAT_SME */
 +    t = FIELD_DP64(t, ID_AA64SMFR0, F16F32, 1);   /* FEAT_SME */
 +    t = FIELD_DP64(t, ID_AA64SMFR0, I8I32, 0xf);  /* FEAT_SME */
 +    t = FIELD_DP64(t, ID_AA64SMFR0, F64F64, 1);   /* FEAT_SME_F64F64 */
 +    t = FIELD_DP64(t, ID_AA64SMFR0, I16I64, 0xf); /* FEAT_SME_I16I64 */
 +    t = FIELD_DP64(t, ID_AA64SMFR0, FA64, 1);     /* FEAT_SME_FA64 */
 +    cpu->isar.id_aa64smfr0 = t;
 +
      /* Replicate the same data to the 32-bit id registers.  */
      aa32_max_features(cpu);
 --
-.25.1
+.34.1

-[PULL 21/45] target/arm: Export unpredicated ld/st from translate-sve.c
+[PULL 11/24] Remove i.MX7 IOMUX GPR device from i.MX6UL
-From: Richard Henderson <richard.henderson@linaro.org>
+From: Jean-Christophe Dubois <jcd@tribudubois.net>
-Add a TCGv_ptr base argument, which will be cpu_env for SVE.
+i.MX7 IOMUX GPR device is not equivalent to i.MX6UL IOMUXC GPR device.
-We will reuse this for SME save and restore array insns.
+In particular, register 22 is not present on i.MX6UL and this is actualy
 The only register that is really emulated in the i.MX7 IOMUX GPR device.
+Note: The i.MX6UL code is actually also implementing the IOMUX GPR device
+as an unimplemented device at the same bus adress and the 2 instantiations
+were actualy colliding. So we go back to the unimplemented device for now.
+Signed-off-by: Jean-Christophe Dubois <jcd@tribudubois.net>
+Message-id: 48681bf51ee97646479bb261bee19abebbc8074e.1692964892.git.jcd@tribudubois.net
 Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
-Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
-Message-id: 20220708151540.18136-22-richard.henderson@linaro.org
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 ---
- target/arm/translate-a64.h |  3 +++
+ include/hw/arm/fsl-imx6ul.h |  2 --
- target/arm/translate-sve.c | 48 ++++++++++++++++++++++++++++----------
+ hw/arm/fsl-imx6ul.c         | 11 -----------
-files changed, 39 insertions(+), 12 deletions(-)
+files changed, 13 deletions(-)
-diff --git a/target/arm/translate-a64.h b/target/arm/translate-a64.h
+diff --git a/include/hw/arm/fsl-imx6ul.h b/include/hw/arm/fsl-imx6ul.h
 index XXXXXXX..XXXXXXX 100644
---- a/target/arm/translate-a64.h
+--- a/include/hw/arm/fsl-imx6ul.h
-+++ b/target/arm/translate-a64.h
++++ b/include/hw/arm/fsl-imx6ul.h
-@@ -XXX,XX +XXX,XX @@ void gen_gvec_xar(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs,
+@@ -XXX,XX +XXX,XX @@
-                   uint32_t rm_ofs, int64_t shift,
+ #include "hw/misc/imx6ul_ccm.h"
-                   uint32_t opr_sz, uint32_t max_sz);
+ #include "hw/misc/imx6_src.h"
+ #include "hw/misc/imx7_snvs.h"
-+void gen_sve_ldr(DisasContext *s, TCGv_ptr, int vofs, int len, int rn, int imm);
+-#include "hw/misc/imx7_gpr.h"
-+void gen_sve_str(DisasContext *s, TCGv_ptr, int vofs, int len, int rn, int imm);
+ #include "hw/intc/imx_gpcv2.h"
-+
+ #include "hw/watchdog/wdt_imx2.h"
- #endif /* TARGET_ARM_TRANSLATE_A64_H */
+ #include "hw/gpio/imx_gpio.h"
-diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
+@@ -XXX,XX +XXX,XX @@ struct FslIMX6ULState {
      IMX6SRCState       src;
      IMX7SNVSState      snvs;
      IMXGPCv2State      gpcv2;
 -    IMX7GPRState       gpr;
      IMXSPIState        spi[FSL_IMX6UL_NUM_ECSPIS];
      IMXI2CState        i2c[FSL_IMX6UL_NUM_I2CS];
      IMXSerialState     uart[FSL_IMX6UL_NUM_UARTS];
 diff --git a/hw/arm/fsl-imx6ul.c b/hw/arm/fsl-imx6ul.c
 index XXXXXXX..XXXXXXX 100644
---- a/target/arm/translate-sve.c
+--- a/hw/arm/fsl-imx6ul.c
-+++ b/target/arm/translate-sve.c
++++ b/hw/arm/fsl-imx6ul.c
-@@ -XXX,XX +XXX,XX @@ TRANS_FEAT(UCVTF_dd, aa64_sve, gen_gvec_fpst_arg_zpz,
+@@ -XXX,XX +XXX,XX @@ static void fsl_imx6ul_init(Object *obj)
-  * The load should begin at the address Rn + IMM.
+      */
-  */
+     object_initialize_child(obj, "snvs", &s->snvs, TYPE_IMX7_SNVS);
--static void do_ldr(DisasContext *s, uint32_t vofs, int len, int rn, int imm)
+-    /*
-+void gen_sve_ldr(DisasContext *s, TCGv_ptr base, int vofs,
+-     * GPR
-+                 int len, int rn, int imm)
+-     */
- {
+-    object_initialize_child(obj, "gpr", &s->gpr, TYPE_IMX7_GPR);
-     int len_align = QEMU_ALIGN_DOWN(len, 8);
+-
-     int len_remain = len % 8;
+     /*
-@@ -XXX,XX +XXX,XX @@ static void do_ldr(DisasContext *s, uint32_t vofs, int len, int rn, int imm)
+      * GPIOs 1 to 5
-         t0 = tcg_temp_new_i64();
+      */
-         for (i = 0; i < len_align; i += 8) {
+@@ -XXX,XX +XXX,XX @@ static void fsl_imx6ul_realize(DeviceState *dev, Error **errp)
-             tcg_gen_qemu_ld_i64(t0, clean_addr, midx, MO_LEUQ);
+                                             FSL_IMX6UL_WDOGn_IRQ[i]));
 -            tcg_gen_st_i64(t0, cpu_env, vofs + i);
 +            tcg_gen_st_i64(t0, base, vofs + i);
              tcg_gen_addi_i64(clean_addr, clean_addr, 8);
          }
          tcg_temp_free_i64(t0);
@@ -XXX,XX +XXX,XX @@ static void do_ldr(DisasContext *s, uint32_t vofs, int len, int rn, int imm)
          clean_addr = new_tmp_a64_local(s);
          tcg_gen_mov_i64(clean_addr, t0);
 +        if (base != cpu_env) {
 +            TCGv_ptr b = tcg_temp_local_new_ptr();
 +            tcg_gen_mov_ptr(b, base);
 +            base = b;
 +        }
 +
          gen_set_label(loop);
          t0 = tcg_temp_new_i64();
@@ -XXX,XX +XXX,XX @@ static void do_ldr(DisasContext *s, uint32_t vofs, int len, int rn, int imm)
          tcg_gen_addi_i64(clean_addr, clean_addr, 8);
          tp = tcg_temp_new_ptr();
 -        tcg_gen_add_ptr(tp, cpu_env, i);
 +        tcg_gen_add_ptr(tp, base, i);
          tcg_gen_addi_ptr(i, i, 8);
          tcg_gen_st_i64(t0, tp, vofs);
          tcg_temp_free_ptr(tp);
@@ -XXX,XX +XXX,XX @@ static void do_ldr(DisasContext *s, uint32_t vofs, int len, int rn, int imm)
          tcg_gen_brcondi_ptr(TCG_COND_LTU, i, len_align, loop);
          tcg_temp_free_ptr(i);
 +
 +        if (base != cpu_env) {
 +            tcg_temp_free_ptr(base);
 +            assert(len_remain == 0);
 +        }
      }
+-    /*
+-     * GPR
+-     */
+-    sysbus_realize(SYS_BUS_DEVICE(&s->gpr), &error_abort);
+-    sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpr), 0, FSL_IMX6UL_IOMUXC_GPR_ADDR);
+-
      /*
-@@ -XXX,XX +XXX,XX @@ static void do_ldr(DisasContext *s, uint32_t vofs, int len, int rn, int imm)
+      * SDMA
-         default:
+      */
              g_assert_not_reached();
          }
 -        tcg_gen_st_i64(t0, cpu_env, vofs + len_align);
 +        tcg_gen_st_i64(t0, base, vofs + len_align);
          tcg_temp_free_i64(t0);
      }
  }
  /* Similarly for stores.  */
 -static void do_str(DisasContext *s, uint32_t vofs, int len, int rn, int imm)
 +void gen_sve_str(DisasContext *s, TCGv_ptr base, int vofs,
 +                 int len, int rn, int imm)
  {
      int len_align = QEMU_ALIGN_DOWN(len, 8);
      int len_remain = len % 8;
@@ -XXX,XX +XXX,XX @@ static void do_str(DisasContext *s, uint32_t vofs, int len, int rn, int imm)
          t0 = tcg_temp_new_i64();
          for (i = 0; i < len_align; i += 8) {
 -            tcg_gen_ld_i64(t0, cpu_env, vofs + i);
 +            tcg_gen_ld_i64(t0, base, vofs + i);
              tcg_gen_qemu_st_i64(t0, clean_addr, midx, MO_LEUQ);
              tcg_gen_addi_i64(clean_addr, clean_addr, 8);
          }
@@ -XXX,XX +XXX,XX @@ static void do_str(DisasContext *s, uint32_t vofs, int len, int rn, int imm)
          clean_addr = new_tmp_a64_local(s);
          tcg_gen_mov_i64(clean_addr, t0);
 +        if (base != cpu_env) {
 +            TCGv_ptr b = tcg_temp_local_new_ptr();
 +            tcg_gen_mov_ptr(b, base);
 +            base = b;
 +        }
 +
          gen_set_label(loop);
          t0 = tcg_temp_new_i64();
          tp = tcg_temp_new_ptr();
 -        tcg_gen_add_ptr(tp, cpu_env, i);
 +        tcg_gen_add_ptr(tp, base, i);
          tcg_gen_ld_i64(t0, tp, vofs);
          tcg_gen_addi_ptr(i, i, 8);
          tcg_temp_free_ptr(tp);
@@ -XXX,XX +XXX,XX @@ static void do_str(DisasContext *s, uint32_t vofs, int len, int rn, int imm)
          tcg_gen_brcondi_ptr(TCG_COND_LTU, i, len_align, loop);
          tcg_temp_free_ptr(i);
 +
 +        if (base != cpu_env) {
 +            tcg_temp_free_ptr(base);
 +            assert(len_remain == 0);
 +        }
      }
      /* Predicate register stores can be any multiple of 2.  */
      if (len_remain) {
          t0 = tcg_temp_new_i64();
 -        tcg_gen_ld_i64(t0, cpu_env, vofs + len_align);
 +        tcg_gen_ld_i64(t0, base, vofs + len_align);
          switch (len_remain) {
          case 2:
@@ -XXX,XX +XXX,XX @@ static bool trans_LDR_zri(DisasContext *s, arg_rri *a)
      if (sve_access_check(s)) {
          int size = vec_full_reg_size(s);
          int off = vec_full_reg_offset(s, a->rd);
 -        do_ldr(s, off, size, a->rn, a->imm * size);
 +        gen_sve_ldr(s, cpu_env, off, size, a->rn, a->imm * size);
      }
      return true;
  }
@@ -XXX,XX +XXX,XX @@ static bool trans_LDR_pri(DisasContext *s, arg_rri *a)
      if (sve_access_check(s)) {
          int size = pred_full_reg_size(s);
          int off = pred_full_reg_offset(s, a->rd);
 -        do_ldr(s, off, size, a->rn, a->imm * size);
 +        gen_sve_ldr(s, cpu_env, off, size, a->rn, a->imm * size);
      }
      return true;
  }
@@ -XXX,XX +XXX,XX @@ static bool trans_STR_zri(DisasContext *s, arg_rri *a)
      if (sve_access_check(s)) {
          int size = vec_full_reg_size(s);
          int off = vec_full_reg_offset(s, a->rd);
 -        do_str(s, off, size, a->rn, a->imm * size);
 +        gen_sve_str(s, cpu_env, off, size, a->rn, a->imm * size);
      }
      return true;
  }
@@ -XXX,XX +XXX,XX @@ static bool trans_STR_pri(DisasContext *s, arg_rri *a)
      if (sve_access_check(s)) {
          int size = pred_full_reg_size(s);
          int off = pred_full_reg_offset(s, a->rd);
 -        do_str(s, off, size, a->rn, a->imm * size);
 +        gen_sve_str(s, cpu_env, off, size, a->rn, a->imm * size);
      }
      return true;
  }
 --
-.25.1
+.34.1

-[PULL 35/45] linux-user/aarch64: Add SM bit to SVE signal context
+[PULL 12/24] Refactor i.MX6UL processor code
-From: Richard Henderson <richard.henderson@linaro.org>
+From: Jean-Christophe Dubois <jcd@tribudubois.net>
-Make sure to zero the currently reserved fields.
+* Add Addr and size definition for most i.MX6UL devices in i.MX6UL header file.
 * Use those newly defined named constants whenever possible.
 * Standardize the way we init a familly of unimplemented devices
   - SAI
   - PWM
   - CAN
 * Add/rework few comments
+Signed-off-by: Jean-Christophe Dubois <jcd@tribudubois.net>
+Message-id: d579043fbd4e4b490370783fda43fc02c8e9be75.1692964892.git.jcd@tribudubois.net
 Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
-Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
-Message-id: 20220708151540.18136-36-richard.henderson@linaro.org
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 ---
- linux-user/aarch64/signal.c | 9 ++++++++-
+ include/hw/arm/fsl-imx6ul.h | 156 +++++++++++++++++++++++++++++++-----
-file changed, 8 insertions(+), 1 deletion(-)
+ hw/arm/fsl-imx6ul.c         | 147 ++++++++++++++++++++++-----------
 files changed, 232 insertions(+), 71 deletions(-)
-diff --git a/linux-user/aarch64/signal.c b/linux-user/aarch64/signal.c
+diff --git a/include/hw/arm/fsl-imx6ul.h b/include/hw/arm/fsl-imx6ul.h
 index XXXXXXX..XXXXXXX 100644
---- a/linux-user/aarch64/signal.c
+--- a/include/hw/arm/fsl-imx6ul.h
-+++ b/linux-user/aarch64/signal.c
++++ b/include/hw/arm/fsl-imx6ul.h
-@@ -XXX,XX +XXX,XX @@ struct target_extra_context {
+@@ -XXX,XX +XXX,XX @@
- struct target_sve_context {
+ #include "exec/memory.h"
-     struct target_aarch64_ctx head;
+ #include "cpu.h"
-     uint16_t vl;
+ #include "qom/object.h"
--    uint16_t reserved[3];
++#include "qemu/units.h"
-+    uint16_t flags;
-+    uint16_t reserved[2];
+ #define TYPE_FSL_IMX6UL "fsl-imx6ul"
-     /* The actual SVE data immediately follows.  It is laid out
+ OBJECT_DECLARE_SIMPLE_TYPE(FslIMX6ULState, FSL_IMX6UL)
-      * according to TARGET_SVE_SIG_{Z,P}REG_OFFSET, based off of
+@@ -XXX,XX +XXX,XX @@ enum FslIMX6ULConfiguration {
-      * the original struct pointer.
+     FSL_IMX6UL_NUM_ADCS         = 2,
-@@ -XXX,XX +XXX,XX @@ struct target_sve_context {
+     FSL_IMX6UL_NUM_USB_PHYS     = 2,
- #define TARGET_SVE_SIG_CONTEXT_SIZE(VQ) \
+     FSL_IMX6UL_NUM_USBS         = 2,
-     (TARGET_SVE_SIG_PREG_OFFSET(VQ, 17))
++    FSL_IMX6UL_NUM_SAIS         = 3,
++    FSL_IMX6UL_NUM_CANS         = 2,
-+#define TARGET_SVE_SIG_FLAG_SM  1
++    FSL_IMX6UL_NUM_PWMS         = 4,
-+
+ };
- struct target_rt_sigframe {
-     struct target_siginfo info;
+ struct FslIMX6ULState {
-     struct target_ucontext uc;
+@@ -XXX,XX +XXX,XX @@ struct FslIMX6ULState {
-@@ -XXX,XX +XXX,XX @@ static void target_setup_sve_record(struct target_sve_context *sve,
- {
+ enum FslIMX6ULMemoryMap {
-     int i, j;
+     FSL_IMX6UL_MMDC_ADDR            = 0x80000000,
+-    FSL_IMX6UL_MMDC_SIZE            = 2 * 1024 * 1024 * 1024UL,
-+    memset(sve, 0, sizeof(*sve));
++    FSL_IMX6UL_MMDC_SIZE            = (2 * GiB),
-     __put_user(TARGET_SVE_MAGIC, &sve->head.magic);
-     __put_user(size, &sve->head.size);
+     FSL_IMX6UL_QSPI1_MEM_ADDR       = 0x60000000,
-     __put_user(vq * TARGET_SVE_VQ_BYTES, &sve->vl);
+-    FSL_IMX6UL_EIM_ALIAS_ADDR       = 0x58000000,
-+    if (FIELD_EX64(env->svcr, SVCR, SM)) {
+-    FSL_IMX6UL_EIM_CS_ADDR          = 0x50000000,
-+        __put_user(TARGET_SVE_SIG_FLAG_SM, &sve->flags);
+-    FSL_IMX6UL_AES_ENCRYPT_ADDR     = 0x10000000,
 -    FSL_IMX6UL_QSPI1_RX_ADDR        = 0x0C000000,
 +    FSL_IMX6UL_QSPI1_MEM_SIZE       = (256 * MiB),
 -    /* AIPS-2 */
 +    FSL_IMX6UL_EIM_ALIAS_ADDR       = 0x58000000,
 +    FSL_IMX6UL_EIM_ALIAS_SIZE       = (128 * MiB),
 +
 +    FSL_IMX6UL_EIM_CS_ADDR          = 0x50000000,
 +    FSL_IMX6UL_EIM_CS_SIZE          = (128 * MiB),
 +
 +    FSL_IMX6UL_AES_ENCRYPT_ADDR     = 0x10000000,
 +    FSL_IMX6UL_AES_ENCRYPT_SIZE     = (1 * MiB),
 +
 +    FSL_IMX6UL_QSPI1_RX_ADDR        = 0x0C000000,
 +    FSL_IMX6UL_QSPI1_RX_SIZE        = (32 * MiB),
 +
 +    /* AIPS-2 Begin */
      FSL_IMX6UL_UART6_ADDR           = 0x021FC000,
 +
      FSL_IMX6UL_I2C4_ADDR            = 0x021F8000,
 +
      FSL_IMX6UL_UART5_ADDR           = 0x021F4000,
      FSL_IMX6UL_UART4_ADDR           = 0x021F0000,
      FSL_IMX6UL_UART3_ADDR           = 0x021EC000,
      FSL_IMX6UL_UART2_ADDR           = 0x021E8000,
 +
      FSL_IMX6UL_WDOG3_ADDR           = 0x021E4000,
 +
      FSL_IMX6UL_QSPI_ADDR            = 0x021E0000,
 +    FSL_IMX6UL_QSPI_SIZE            = 0x500,
 +
      FSL_IMX6UL_SYS_CNT_CTRL_ADDR    = 0x021DC000,
 +    FSL_IMX6UL_SYS_CNT_CTRL_SIZE    = (16 * KiB),
 +
      FSL_IMX6UL_SYS_CNT_CMP_ADDR     = 0x021D8000,
 +    FSL_IMX6UL_SYS_CNT_CMP_SIZE     = (16 * KiB),
 +
      FSL_IMX6UL_SYS_CNT_RD_ADDR      = 0x021D4000,
 +    FSL_IMX6UL_SYS_CNT_RD_SIZE      = (16 * KiB),
 +
      FSL_IMX6UL_TZASC_ADDR           = 0x021D0000,
 +    FSL_IMX6UL_TZASC_SIZE           = (16 * KiB),
 +
      FSL_IMX6UL_PXP_ADDR             = 0x021CC000,
 +    FSL_IMX6UL_PXP_SIZE             = (16 * KiB),
 +
      FSL_IMX6UL_LCDIF_ADDR           = 0x021C8000,
 +    FSL_IMX6UL_LCDIF_SIZE           = 0x100,
 +
      FSL_IMX6UL_CSI_ADDR             = 0x021C4000,
 +    FSL_IMX6UL_CSI_SIZE             = 0x100,
 +
      FSL_IMX6UL_CSU_ADDR             = 0x021C0000,
 +    FSL_IMX6UL_CSU_SIZE             = (16 * KiB),
 +
      FSL_IMX6UL_OCOTP_CTRL_ADDR      = 0x021BC000,
 +    FSL_IMX6UL_OCOTP_CTRL_SIZE      = (4 * KiB),
 +
      FSL_IMX6UL_EIM_ADDR             = 0x021B8000,
 +    FSL_IMX6UL_EIM_SIZE             = 0x100,
 +
      FSL_IMX6UL_SIM2_ADDR            = 0x021B4000,
 +
      FSL_IMX6UL_MMDC_CFG_ADDR        = 0x021B0000,
 +    FSL_IMX6UL_MMDC_CFG_SIZE        = (4 * KiB),
 +
      FSL_IMX6UL_ROMCP_ADDR           = 0x021AC000,
 +    FSL_IMX6UL_ROMCP_SIZE           = 0x300,
 +
      FSL_IMX6UL_I2C3_ADDR            = 0x021A8000,
      FSL_IMX6UL_I2C2_ADDR            = 0x021A4000,
      FSL_IMX6UL_I2C1_ADDR            = 0x021A0000,
 +
      FSL_IMX6UL_ADC2_ADDR            = 0x0219C000,
      FSL_IMX6UL_ADC1_ADDR            = 0x02198000,
 +    FSL_IMX6UL_ADCn_SIZE            = 0x100,
 +
      FSL_IMX6UL_USDHC2_ADDR          = 0x02194000,
      FSL_IMX6UL_USDHC1_ADDR          = 0x02190000,
 -    FSL_IMX6UL_SIM1_ADDR            = 0x0218C000,
 -    FSL_IMX6UL_ENET1_ADDR           = 0x02188000,
 -    FSL_IMX6UL_USBO2_USBMISC_ADDR   = 0x02184800,
 -    FSL_IMX6UL_USBO2_USB_ADDR       = 0x02184000,
 -    FSL_IMX6UL_USBO2_PL301_ADDR     = 0x02180000,
 -    FSL_IMX6UL_AIPS2_CFG_ADDR       = 0x0217C000,
 -    FSL_IMX6UL_CAAM_ADDR            = 0x02140000,
 -    FSL_IMX6UL_A7MPCORE_DAP_ADDR    = 0x02100000,
 -    /* AIPS-1 */
 +    FSL_IMX6UL_SIM1_ADDR            = 0x0218C000,
 +    FSL_IMX6UL_SIMn_SIZE            = (16 * KiB),
 +
 +    FSL_IMX6UL_ENET1_ADDR           = 0x02188000,
 +
 +    FSL_IMX6UL_USBO2_USBMISC_ADDR   = 0x02184800,
 +    FSL_IMX6UL_USBO2_USB1_ADDR      = 0x02184000,
 +    FSL_IMX6UL_USBO2_USB2_ADDR      = 0x02184200,
 +
 +    FSL_IMX6UL_USBO2_PL301_ADDR     = 0x02180000,
 +    FSL_IMX6UL_USBO2_PL301_SIZE     = (16 * KiB),
 +
 +    FSL_IMX6UL_AIPS2_CFG_ADDR       = 0x0217C000,
 +    FSL_IMX6UL_AIPS2_CFG_SIZE       = 0x100,
 +
 +    FSL_IMX6UL_CAAM_ADDR            = 0x02140000,
 +    FSL_IMX6UL_CAAM_SIZE            = (16 * KiB),
 +
 +    FSL_IMX6UL_A7MPCORE_DAP_ADDR    = 0x02100000,
 +    FSL_IMX6UL_A7MPCORE_DAP_SIZE    = (4 * KiB),
 +    /* AIPS-2 End */
 +
 +    /* AIPS-1 Begin */
      FSL_IMX6UL_PWM8_ADDR            = 0x020FC000,
      FSL_IMX6UL_PWM7_ADDR            = 0x020F8000,
      FSL_IMX6UL_PWM6_ADDR            = 0x020F4000,
      FSL_IMX6UL_PWM5_ADDR            = 0x020F0000,
 +
      FSL_IMX6UL_SDMA_ADDR            = 0x020EC000,
 +    FSL_IMX6UL_SDMA_SIZE            = 0x300,
 +
      FSL_IMX6UL_GPT2_ADDR            = 0x020E8000,
 +
      FSL_IMX6UL_IOMUXC_GPR_ADDR      = 0x020E4000,
 +    FSL_IMX6UL_IOMUXC_GPR_SIZE      = 0x40,
 +
      FSL_IMX6UL_IOMUXC_ADDR          = 0x020E0000,
 +    FSL_IMX6UL_IOMUXC_SIZE          = 0x700,
 +
      FSL_IMX6UL_GPC_ADDR             = 0x020DC000,
 +
      FSL_IMX6UL_SRC_ADDR             = 0x020D8000,
 +
      FSL_IMX6UL_EPIT2_ADDR           = 0x020D4000,
      FSL_IMX6UL_EPIT1_ADDR           = 0x020D0000,
 +
      FSL_IMX6UL_SNVS_HP_ADDR         = 0x020CC000,
 +
      FSL_IMX6UL_USBPHY2_ADDR         = 0x020CA000,
 -    FSL_IMX6UL_USBPHY2_SIZE         = (4 * 1024),
      FSL_IMX6UL_USBPHY1_ADDR         = 0x020C9000,
 -    FSL_IMX6UL_USBPHY1_SIZE         = (4 * 1024),
 +
      FSL_IMX6UL_ANALOG_ADDR          = 0x020C8000,
 +    FSL_IMX6UL_ANALOG_SIZE          = 0x300,
 +
      FSL_IMX6UL_CCM_ADDR             = 0x020C4000,
 +
      FSL_IMX6UL_WDOG2_ADDR           = 0x020C0000,
      FSL_IMX6UL_WDOG1_ADDR           = 0x020BC000,
 +
      FSL_IMX6UL_KPP_ADDR             = 0x020B8000,
 +    FSL_IMX6UL_KPP_SIZE             = 0x10,
 +
      FSL_IMX6UL_ENET2_ADDR           = 0x020B4000,
 +
      FSL_IMX6UL_SNVS_LP_ADDR         = 0x020B0000,
 +    FSL_IMX6UL_SNVS_LP_SIZE         = (16 * KiB),
 +
      FSL_IMX6UL_GPIO5_ADDR           = 0x020AC000,
      FSL_IMX6UL_GPIO4_ADDR           = 0x020A8000,
      FSL_IMX6UL_GPIO3_ADDR           = 0x020A4000,
      FSL_IMX6UL_GPIO2_ADDR           = 0x020A0000,
      FSL_IMX6UL_GPIO1_ADDR           = 0x0209C000,
 +
      FSL_IMX6UL_GPT1_ADDR            = 0x02098000,
 +
      FSL_IMX6UL_CAN2_ADDR            = 0x02094000,
      FSL_IMX6UL_CAN1_ADDR            = 0x02090000,
 +    FSL_IMX6UL_CANn_SIZE            = (4 * KiB),
 +
      FSL_IMX6UL_PWM4_ADDR            = 0x0208C000,
      FSL_IMX6UL_PWM3_ADDR            = 0x02088000,
      FSL_IMX6UL_PWM2_ADDR            = 0x02084000,
      FSL_IMX6UL_PWM1_ADDR            = 0x02080000,
 +    FSL_IMX6UL_PWMn_SIZE            = 0x20,
 +
      FSL_IMX6UL_AIPS1_CFG_ADDR       = 0x0207C000,
 +    FSL_IMX6UL_AIPS1_CFG_SIZE       = (16 * KiB),
 +
      FSL_IMX6UL_BEE_ADDR             = 0x02044000,
 +    FSL_IMX6UL_BEE_SIZE             = (16 * KiB),
 +
      FSL_IMX6UL_TOUCH_CTRL_ADDR      = 0x02040000,
 +    FSL_IMX6UL_TOUCH_CTRL_SIZE      = 0x100,
 +
      FSL_IMX6UL_SPBA_ADDR            = 0x0203C000,
 +    FSL_IMX6UL_SPBA_SIZE            = 0x100,
 +
      FSL_IMX6UL_ASRC_ADDR            = 0x02034000,
 +    FSL_IMX6UL_ASRC_SIZE            = 0x100,
 +
      FSL_IMX6UL_SAI3_ADDR            = 0x02030000,
      FSL_IMX6UL_SAI2_ADDR            = 0x0202C000,
      FSL_IMX6UL_SAI1_ADDR            = 0x02028000,
 +    FSL_IMX6UL_SAIn_SIZE            = 0x200,
 +
      FSL_IMX6UL_UART8_ADDR           = 0x02024000,
      FSL_IMX6UL_UART1_ADDR           = 0x02020000,
      FSL_IMX6UL_UART7_ADDR           = 0x02018000,
 +
      FSL_IMX6UL_ECSPI4_ADDR          = 0x02014000,
      FSL_IMX6UL_ECSPI3_ADDR          = 0x02010000,
      FSL_IMX6UL_ECSPI2_ADDR          = 0x0200C000,
      FSL_IMX6UL_ECSPI1_ADDR          = 0x02008000,
 +
      FSL_IMX6UL_SPDIF_ADDR           = 0x02004000,
 +    FSL_IMX6UL_SPDIF_SIZE           = 0x100,
 +    /* AIPS-1 End */
 +
 +    FSL_IMX6UL_BCH_ADDR             = 0x01808000,
 +    FSL_IMX6UL_BCH_SIZE             = 0x200,
 +
 +    FSL_IMX6UL_GPMI_ADDR            = 0x01806000,
 +    FSL_IMX6UL_GPMI_SIZE            = 0x200,
      FSL_IMX6UL_APBH_DMA_ADDR        = 0x01804000,
 -    FSL_IMX6UL_APBH_DMA_SIZE        = (32 * 1024),
 +    FSL_IMX6UL_APBH_DMA_SIZE        = (4 * KiB),
      FSL_IMX6UL_A7MPCORE_ADDR        = 0x00A00000,
      FSL_IMX6UL_OCRAM_ALIAS_ADDR     = 0x00920000,
 -    FSL_IMX6UL_OCRAM_ALIAS_SIZE     = 0x00060000,
 +    FSL_IMX6UL_OCRAM_ALIAS_SIZE     = (384 * KiB),
 +
      FSL_IMX6UL_OCRAM_MEM_ADDR       = 0x00900000,
 -    FSL_IMX6UL_OCRAM_MEM_SIZE       = 0x00020000,
 +    FSL_IMX6UL_OCRAM_MEM_SIZE       = (128 * KiB),
 +
      FSL_IMX6UL_CAAM_MEM_ADDR        = 0x00100000,
 -    FSL_IMX6UL_CAAM_MEM_SIZE        = 0x00008000,
 +    FSL_IMX6UL_CAAM_MEM_SIZE        = (32 * KiB),
 +
      FSL_IMX6UL_ROM_ADDR             = 0x00000000,
 -    FSL_IMX6UL_ROM_SIZE             = 0x00018000,
 +    FSL_IMX6UL_ROM_SIZE             = (96 * KiB),
  };
  enum FslIMX6ULIRQs {
 diff --git a/hw/arm/fsl-imx6ul.c b/hw/arm/fsl-imx6ul.c
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/arm/fsl-imx6ul.c
 +++ b/hw/arm/fsl-imx6ul.c
@@ -XXX,XX +XXX,XX @@ static void fsl_imx6ul_init(Object *obj)
      object_initialize_child(obj, "snvs", &s->snvs, TYPE_IMX7_SNVS);
      /*
 -     * GPIOs 1 to 5
 +     * GPIOs
       */
      for (i = 0; i < FSL_IMX6UL_NUM_GPIOS; i++) {
          snprintf(name, NAME_SIZE, "gpio%d", i);
@@ -XXX,XX +XXX,XX @@ static void fsl_imx6ul_init(Object *obj)
      }
      /*
 -     * GPT 1, 2
 +     * GPTs
       */
      for (i = 0; i < FSL_IMX6UL_NUM_GPTS; i++) {
          snprintf(name, NAME_SIZE, "gpt%d", i);
@@ -XXX,XX +XXX,XX @@ static void fsl_imx6ul_init(Object *obj)
      }
      /*
 -     * EPIT 1, 2
 +     * EPITs
       */
      for (i = 0; i < FSL_IMX6UL_NUM_EPITS; i++) {
          snprintf(name, NAME_SIZE, "epit%d", i + 1);
@@ -XXX,XX +XXX,XX @@ static void fsl_imx6ul_init(Object *obj)
      }
      /*
 -     * eCSPI
 +     * eCSPIs
       */
      for (i = 0; i < FSL_IMX6UL_NUM_ECSPIS; i++) {
          snprintf(name, NAME_SIZE, "spi%d", i + 1);
@@ -XXX,XX +XXX,XX @@ static void fsl_imx6ul_init(Object *obj)
      }
      /*
 -     * I2C
 +     * I2Cs
       */
      for (i = 0; i < FSL_IMX6UL_NUM_I2CS; i++) {
          snprintf(name, NAME_SIZE, "i2c%d", i + 1);
@@ -XXX,XX +XXX,XX @@ static void fsl_imx6ul_init(Object *obj)
      }
      /*
 -     * UART
 +     * UARTs
       */
      for (i = 0; i < FSL_IMX6UL_NUM_UARTS; i++) {
          snprintf(name, NAME_SIZE, "uart%d", i);
@@ -XXX,XX +XXX,XX @@ static void fsl_imx6ul_init(Object *obj)
      }
      /*
 -     * Ethernet
 +     * Ethernets
       */
      for (i = 0; i < FSL_IMX6UL_NUM_ETHS; i++) {
          snprintf(name, NAME_SIZE, "eth%d", i);
          object_initialize_child(obj, name, &s->eth[i], TYPE_IMX_ENET);
      }
 -    /* USB */
 +    /*
 +     * USB PHYs
 +     */
      for (i = 0; i < FSL_IMX6UL_NUM_USB_PHYS; i++) {
          snprintf(name, NAME_SIZE, "usbphy%d", i);
          object_initialize_child(obj, name, &s->usbphy[i], TYPE_IMX_USBPHY);
      }
 +
 +    /*
 +     * USBs
 +     */
      for (i = 0; i < FSL_IMX6UL_NUM_USBS; i++) {
          snprintf(name, NAME_SIZE, "usb%d", i);
          object_initialize_child(obj, name, &s->usb[i], TYPE_CHIPIDEA);
      }
      /*
 -     * SDHCI
 +     * SDHCIs
       */
      for (i = 0; i < FSL_IMX6UL_NUM_USDHCS; i++) {
          snprintf(name, NAME_SIZE, "usdhc%d", i);
@@ -XXX,XX +XXX,XX @@ static void fsl_imx6ul_init(Object *obj)
      }
      /*
 -     * Watchdog
 +     * Watchdogs
       */
      for (i = 0; i < FSL_IMX6UL_NUM_WDTS; i++) {
          snprintf(name, NAME_SIZE, "wdt%d", i);
@@ -XXX,XX +XXX,XX @@ static void fsl_imx6ul_realize(DeviceState *dev, Error **errp)
       * A7MPCORE DAP
       */
      create_unimplemented_device("a7mpcore-dap", FSL_IMX6UL_A7MPCORE_DAP_ADDR,
 -                                0x100000);
 +                                FSL_IMX6UL_A7MPCORE_DAP_SIZE);
      /*
 -     * GPT 1, 2
 +     * GPTs
       */
      for (i = 0; i < FSL_IMX6UL_NUM_GPTS; i++) {
          static const hwaddr FSL_IMX6UL_GPTn_ADDR[FSL_IMX6UL_NUM_GPTS] = {
@@ -XXX,XX +XXX,XX @@ static void fsl_imx6ul_realize(DeviceState *dev, Error **errp)
      }
      /*
 -     * EPIT 1, 2
 +     * EPITs
       */
      for (i = 0; i < FSL_IMX6UL_NUM_EPITS; i++) {
          static const hwaddr FSL_IMX6UL_EPITn_ADDR[FSL_IMX6UL_NUM_EPITS] = {
@@ -XXX,XX +XXX,XX @@ static void fsl_imx6ul_realize(DeviceState *dev, Error **errp)
      }
      /*
 -     * GPIO
 +     * GPIOs
       */
      for (i = 0; i < FSL_IMX6UL_NUM_GPIOS; i++) {
          static const hwaddr FSL_IMX6UL_GPIOn_ADDR[FSL_IMX6UL_NUM_GPIOS] = {
@@ -XXX,XX +XXX,XX @@ static void fsl_imx6ul_realize(DeviceState *dev, Error **errp)
      }
      /*
 -     * IOMUXC and IOMUXC_GPR
 +     * IOMUXC
       */
 -    for (i = 0; i < 1; i++) {
 -        static const hwaddr FSL_IMX6UL_IOMUXCn_ADDR[FSL_IMX6UL_NUM_IOMUXCS] = {
 -            FSL_IMX6UL_IOMUXC_ADDR,
 -            FSL_IMX6UL_IOMUXC_GPR_ADDR,
 -        };
 -
 -        snprintf(name, NAME_SIZE, "iomuxc%d", i);
 -        create_unimplemented_device(name, FSL_IMX6UL_IOMUXCn_ADDR[i], 0x4000);
 -    }
 +    create_unimplemented_device("iomuxc", FSL_IMX6UL_IOMUXC_ADDR,
 +                                FSL_IMX6UL_IOMUXC_SIZE);
 +    create_unimplemented_device("iomuxc_gpr", FSL_IMX6UL_IOMUXC_GPR_ADDR,
 +                                FSL_IMX6UL_IOMUXC_GPR_SIZE);
      /*
       * CCM
@@ -XXX,XX +XXX,XX @@ static void fsl_imx6ul_realize(DeviceState *dev, Error **errp)
      sysbus_realize(SYS_BUS_DEVICE(&s->gpcv2), &error_abort);
      sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpcv2), 0, FSL_IMX6UL_GPC_ADDR);
 -    /* Initialize all ECSPI */
 +    /*
 +     * ECSPIs
 +     */
      for (i = 0; i < FSL_IMX6UL_NUM_ECSPIS; i++) {
          static const hwaddr FSL_IMX6UL_SPIn_ADDR[FSL_IMX6UL_NUM_ECSPIS] = {
              FSL_IMX6UL_ECSPI1_ADDR,
@@ -XXX,XX +XXX,XX @@ static void fsl_imx6ul_realize(DeviceState *dev, Error **errp)
      }
      /*
 -     * I2C
 +     * I2Cs
       */
      for (i = 0; i < FSL_IMX6UL_NUM_I2CS; i++) {
          static const hwaddr FSL_IMX6UL_I2Cn_ADDR[FSL_IMX6UL_NUM_I2CS] = {
@@ -XXX,XX +XXX,XX @@ static void fsl_imx6ul_realize(DeviceState *dev, Error **errp)
      }
      /*
 -     * UART
 +     * UARTs
       */
      for (i = 0; i < FSL_IMX6UL_NUM_UARTS; i++) {
          static const hwaddr FSL_IMX6UL_UARTn_ADDR[FSL_IMX6UL_NUM_UARTS] = {
@@ -XXX,XX +XXX,XX @@ static void fsl_imx6ul_realize(DeviceState *dev, Error **errp)
      }
      /*
 -     * Ethernet
 +     * Ethernets
       *
       * We must use two loops since phy_connected affects the other interface
       * and we have to set all properties before calling sysbus_realize().
@@ -XXX,XX +XXX,XX @@ static void fsl_imx6ul_realize(DeviceState *dev, Error **errp)
                                              FSL_IMX6UL_ENETn_TIMER_IRQ[i]));
      }
 -    /* USB */
 +    /*
 +     * USB PHYs
 +     */
      for (i = 0; i < FSL_IMX6UL_NUM_USB_PHYS; i++) {
 +        static const hwaddr
 +                     FSL_IMX6UL_USB_PHYn_ADDR[FSL_IMX6UL_NUM_USB_PHYS] = {
 +            FSL_IMX6UL_USBPHY1_ADDR,
 +            FSL_IMX6UL_USBPHY2_ADDR,
 +        };
 +
          sysbus_realize(SYS_BUS_DEVICE(&s->usbphy[i]), &error_abort);
          sysbus_mmio_map(SYS_BUS_DEVICE(&s->usbphy[i]), 0,
 -                        FSL_IMX6UL_USBPHY1_ADDR + i * 0x1000);
 +                        FSL_IMX6UL_USB_PHYn_ADDR[i]);
      }
 +    /*
 +     * USBs
 +     */
      for (i = 0; i < FSL_IMX6UL_NUM_USBS; i++) {
 +        static const hwaddr FSL_IMX6UL_USB02_USBn_ADDR[FSL_IMX6UL_NUM_USBS] = {
 +            FSL_IMX6UL_USBO2_USB1_ADDR,
 +            FSL_IMX6UL_USBO2_USB2_ADDR,
 +        };
 +
          static const int FSL_IMX6UL_USBn_IRQ[] = {
              FSL_IMX6UL_USB1_IRQ,
              FSL_IMX6UL_USB2_IRQ,
          };
 +
          sysbus_realize(SYS_BUS_DEVICE(&s->usb[i]), &error_abort);
          sysbus_mmio_map(SYS_BUS_DEVICE(&s->usb[i]), 0,
 -                        FSL_IMX6UL_USBO2_USB_ADDR + i * 0x200);
 +                        FSL_IMX6UL_USB02_USBn_ADDR[i]);
          sysbus_connect_irq(SYS_BUS_DEVICE(&s->usb[i]), 0,
                             qdev_get_gpio_in(DEVICE(&s->a7mpcore),
                                              FSL_IMX6UL_USBn_IRQ[i]));
      }
      /*
 -     * USDHC
 +     * USDHCs
       */
      for (i = 0; i < FSL_IMX6UL_NUM_USDHCS; i++) {
          static const hwaddr FSL_IMX6UL_USDHCn_ADDR[FSL_IMX6UL_NUM_USDHCS] = {
@@ -XXX,XX +XXX,XX @@ static void fsl_imx6ul_realize(DeviceState *dev, Error **errp)
      sysbus_mmio_map(SYS_BUS_DEVICE(&s->snvs), 0, FSL_IMX6UL_SNVS_HP_ADDR);
      /*
 -     * Watchdog
 +     * Watchdogs
       */
      for (i = 0; i < FSL_IMX6UL_NUM_WDTS; i++) {
          static const hwaddr FSL_IMX6UL_WDOGn_ADDR[FSL_IMX6UL_NUM_WDTS] = {
@@ -XXX,XX +XXX,XX @@ static void fsl_imx6ul_realize(DeviceState *dev, Error **errp)
              FSL_IMX6UL_WDOG2_ADDR,
              FSL_IMX6UL_WDOG3_ADDR,
          };
 +
          static const int FSL_IMX6UL_WDOGn_IRQ[FSL_IMX6UL_NUM_WDTS] = {
              FSL_IMX6UL_WDOG1_IRQ,
              FSL_IMX6UL_WDOG2_IRQ,
@@ -XXX,XX +XXX,XX @@ static void fsl_imx6ul_realize(DeviceState *dev, Error **errp)
      /*
       * SDMA
       */
 -    create_unimplemented_device("sdma", FSL_IMX6UL_SDMA_ADDR, 0x4000);
 +    create_unimplemented_device("sdma", FSL_IMX6UL_SDMA_ADDR,
 +                                FSL_IMX6UL_SDMA_SIZE);
      /*
 -     * SAI (Audio SSI (Synchronous Serial Interface))
 +     * SAIs (Audio SSI (Synchronous Serial Interface))
       */
 -    create_unimplemented_device("sai1", FSL_IMX6UL_SAI1_ADDR, 0x4000);
 -    create_unimplemented_device("sai2", FSL_IMX6UL_SAI2_ADDR, 0x4000);
 -    create_unimplemented_device("sai3", FSL_IMX6UL_SAI3_ADDR, 0x4000);
 +    for (i = 0; i < FSL_IMX6UL_NUM_SAIS; i++) {
 +        static const hwaddr FSL_IMX6UL_SAIn_ADDR[FSL_IMX6UL_NUM_SAIS] = {
 +            FSL_IMX6UL_SAI1_ADDR,
 +            FSL_IMX6UL_SAI2_ADDR,
 +            FSL_IMX6UL_SAI3_ADDR,
 +        };
 +
 +        snprintf(name, NAME_SIZE, "sai%d", i);
 +        create_unimplemented_device(name, FSL_IMX6UL_SAIn_ADDR[i],
 +                                    FSL_IMX6UL_SAIn_SIZE);
 +    }
-     /* Note that SVE regs are stored as a byte stream, with each byte element
+     /*
-      * at a subsequent address.  This corresponds to a little-endian store
+-     * PWM
 +     * PWMs
       */
 -    create_unimplemented_device("pwm1", FSL_IMX6UL_PWM1_ADDR, 0x4000);
 -    create_unimplemented_device("pwm2", FSL_IMX6UL_PWM2_ADDR, 0x4000);
 -    create_unimplemented_device("pwm3", FSL_IMX6UL_PWM3_ADDR, 0x4000);
 -    create_unimplemented_device("pwm4", FSL_IMX6UL_PWM4_ADDR, 0x4000);
 +    for (i = 0; i < FSL_IMX6UL_NUM_PWMS; i++) {
 +        static const hwaddr FSL_IMX6UL_PWMn_ADDR[FSL_IMX6UL_NUM_PWMS] = {
 +            FSL_IMX6UL_PWM1_ADDR,
 +            FSL_IMX6UL_PWM2_ADDR,
 +            FSL_IMX6UL_PWM3_ADDR,
 +            FSL_IMX6UL_PWM4_ADDR,
 +        };
 +
 +        snprintf(name, NAME_SIZE, "pwm%d", i);
 +        create_unimplemented_device(name, FSL_IMX6UL_PWMn_ADDR[i],
 +                                    FSL_IMX6UL_PWMn_SIZE);
 +    }
      /*
       * Audio ASRC (asynchronous sample rate converter)
       */
 -    create_unimplemented_device("asrc", FSL_IMX6UL_ASRC_ADDR, 0x4000);
 +    create_unimplemented_device("asrc", FSL_IMX6UL_ASRC_ADDR,
 +                                FSL_IMX6UL_ASRC_SIZE);
      /*
 -     * CAN
 +     * CANs
       */
 -    create_unimplemented_device("can1", FSL_IMX6UL_CAN1_ADDR, 0x4000);
 -    create_unimplemented_device("can2", FSL_IMX6UL_CAN2_ADDR, 0x4000);
 +    for (i = 0; i < FSL_IMX6UL_NUM_CANS; i++) {
 +        static const hwaddr FSL_IMX6UL_CANn_ADDR[FSL_IMX6UL_NUM_CANS] = {
 +            FSL_IMX6UL_CAN1_ADDR,
 +            FSL_IMX6UL_CAN2_ADDR,
 +        };
 +
 +        snprintf(name, NAME_SIZE, "can%d", i);
 +        create_unimplemented_device(name, FSL_IMX6UL_CANn_ADDR[i],
 +                                    FSL_IMX6UL_CANn_SIZE);
 +    }
      /*
       * APHB_DMA
@@ -XXX,XX +XXX,XX @@ static void fsl_imx6ul_realize(DeviceState *dev, Error **errp)
          };
          snprintf(name, NAME_SIZE, "adc%d", i);
 -        create_unimplemented_device(name, FSL_IMX6UL_ADCn_ADDR[i], 0x4000);
 +        create_unimplemented_device(name, FSL_IMX6UL_ADCn_ADDR[i],
 +                                    FSL_IMX6UL_ADCn_SIZE);
      }
      /*
       * LCD
       */
 -    create_unimplemented_device("lcdif", FSL_IMX6UL_LCDIF_ADDR, 0x4000);
 +    create_unimplemented_device("lcdif", FSL_IMX6UL_LCDIF_ADDR,
 +                                FSL_IMX6UL_LCDIF_SIZE);
      /*
       * ROM memory
 --
-.25.1
+.34.1

-[PULL 40/45] linux-user/aarch64: Implement SME signal handling
+[PULL 13/24] Add i.MX6UL missing devices.
-From: Richard Henderson <richard.henderson@linaro.org>
+From: Jean-Christophe Dubois <jcd@tribudubois.net>
-Set the SM bit in the SVE record on signal delivery, create the ZA record.
+* Add TZASC as unimplemented device.
-Restore SM and ZA state according to the records present on return.
+  - Allow bare metal application to access this (unimplemented) device
 * Add CSU as unimplemented device.
   - Allow bare metal application to access this (unimplemented) device
 * Add 4 missing PWM devices
-Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
+Signed-off-by: Jean-Christophe Dubois <jcd@tribudubois.net>
-Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
+Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
-Message-id: 20220708151540.18136-41-richard.henderson@linaro.org
+Message-id: 59e4dc56e14eccfefd379275ec19048dff9c10b3.1692964892.git.jcd@tribudubois.net
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 ---
- linux-user/aarch64/signal.c | 167 +++++++++++++++++++++++++++++++++---
+ include/hw/arm/fsl-imx6ul.h |  2 +-
-file changed, 154 insertions(+), 13 deletions(-)
+ hw/arm/fsl-imx6ul.c         | 16 ++++++++++++++++
 files changed, 17 insertions(+), 1 deletion(-)
-diff --git a/linux-user/aarch64/signal.c b/linux-user/aarch64/signal.c
+diff --git a/include/hw/arm/fsl-imx6ul.h b/include/hw/arm/fsl-imx6ul.h
 index XXXXXXX..XXXXXXX 100644
---- a/linux-user/aarch64/signal.c
+--- a/include/hw/arm/fsl-imx6ul.h
-+++ b/linux-user/aarch64/signal.c
++++ b/include/hw/arm/fsl-imx6ul.h
-@@ -XXX,XX +XXX,XX @@ struct target_sve_context {
+@@ -XXX,XX +XXX,XX @@ enum FslIMX6ULConfiguration {
+     FSL_IMX6UL_NUM_USBS         = 2,
- #define TARGET_SVE_SIG_FLAG_SM  1
+     FSL_IMX6UL_NUM_SAIS         = 3,
+     FSL_IMX6UL_NUM_CANS         = 2,
-+#define TARGET_ZA_MAGIC        0x54366345
+-    FSL_IMX6UL_NUM_PWMS         = 4,
-+
++    FSL_IMX6UL_NUM_PWMS         = 8,
-+struct target_za_context {
+ };
-+    struct target_aarch64_ctx head;
-+    uint16_t vl;
+ struct FslIMX6ULState {
-+    uint16_t reserved[3];
+diff --git a/hw/arm/fsl-imx6ul.c b/hw/arm/fsl-imx6ul.c
-+    /* The actual ZA data immediately follows. */
+index XXXXXXX..XXXXXXX 100644
-+};
+--- a/hw/arm/fsl-imx6ul.c
-+
++++ b/hw/arm/fsl-imx6ul.c
-+#define TARGET_ZA_SIG_REGS_OFFSET \
+@@ -XXX,XX +XXX,XX @@ static void fsl_imx6ul_realize(DeviceState *dev, Error **errp)
-+    QEMU_ALIGN_UP(sizeof(struct target_za_context), TARGET_SVE_VQ_BYTES)
+             FSL_IMX6UL_PWM2_ADDR,
-+#define TARGET_ZA_SIG_ZAV_OFFSET(VQ, N) \
+             FSL_IMX6UL_PWM3_ADDR,
-+    (TARGET_ZA_SIG_REGS_OFFSET + (VQ) * TARGET_SVE_VQ_BYTES * (N))
+             FSL_IMX6UL_PWM4_ADDR,
-+#define TARGET_ZA_SIG_CONTEXT_SIZE(VQ) \
++            FSL_IMX6UL_PWM5_ADDR,
-+    TARGET_ZA_SIG_ZAV_OFFSET(VQ, VQ * TARGET_SVE_VQ_BYTES)
++            FSL_IMX6UL_PWM6_ADDR,
-+
++            FSL_IMX6UL_PWM7_ADDR,
- struct target_rt_sigframe {
++            FSL_IMX6UL_PWM8_ADDR,
-     struct target_siginfo info;
+         };
-     struct target_ucontext uc;
-@@ -XXX,XX +XXX,XX @@ static void target_setup_end_record(struct target_aarch64_ctx *end)
+         snprintf(name, NAME_SIZE, "pwm%d", i);
- }
+@@ -XXX,XX +XXX,XX @@ static void fsl_imx6ul_realize(DeviceState *dev, Error **errp)
+     create_unimplemented_device("lcdif", FSL_IMX6UL_LCDIF_ADDR,
- static void target_setup_sve_record(struct target_sve_context *sve,
+                                 FSL_IMX6UL_LCDIF_SIZE);
--                                    CPUARMState *env, int vq, int size)
-+                                    CPUARMState *env, int size)
++    /*
- {
++     * CSU
--    int i, j;
++     */
-+    int i, j, vq = sve_vq(env);
++    create_unimplemented_device("csu", FSL_IMX6UL_CSU_ADDR,
++                                FSL_IMX6UL_CSU_SIZE);
      memset(sve, 0, sizeof(*sve));
      __put_user(TARGET_SVE_MAGIC, &sve->head.magic);
@@ -XXX,XX +XXX,XX @@ static void target_setup_sve_record(struct target_sve_context *sve,
      }
  }
 +static void target_setup_za_record(struct target_za_context *za,
 +                                   CPUARMState *env, int size)
 +{
 +    int vq = sme_vq(env);
 +    int vl = vq * TARGET_SVE_VQ_BYTES;
 +    int i, j;
 +
 +    memset(za, 0, sizeof(*za));
 +    __put_user(TARGET_ZA_MAGIC, &za->head.magic);
 +    __put_user(size, &za->head.size);
 +    __put_user(vl, &za->vl);
 +
 +    if (size == TARGET_ZA_SIG_CONTEXT_SIZE(0)) {
 +        return;
 +    }
 +    assert(size == TARGET_ZA_SIG_CONTEXT_SIZE(vq));
 +
 +    /*
-+     * Note that ZA vectors are stored as a byte stream,
++     * TZASC
 +     * with each byte element at a subsequent address.
 +     */
-+    for (i = 0; i < vl; ++i) {
++    create_unimplemented_device("tzasc", FSL_IMX6UL_TZASC_ADDR,
-+        uint64_t *z = (void *)za + TARGET_ZA_SIG_ZAV_OFFSET(vq, i);
++                                FSL_IMX6UL_TZASC_SIZE);
 +        for (j = 0; j < vq * 2; ++j) {
 +            __put_user_e(env->zarray[i].d[j], z + j, le);
 +        }
 +    }
 +}
 +
  static void target_restore_general_frame(CPUARMState *env,
                                           struct target_rt_sigframe *sf)
  {
@@ -XXX,XX +XXX,XX @@ static void target_restore_fpsimd_record(CPUARMState *env,
  static bool target_restore_sve_record(CPUARMState *env,
                                        struct target_sve_context *sve,
 -                                      int size)
 +                                      int size, int *svcr)
  {
 -    int i, j, vl, vq;
 +    int i, j, vl, vq, flags;
 +    bool sm;
 -    if (!cpu_isar_feature(aa64_sve, env_archcpu(env))) {
 +    __get_user(vl, &sve->vl);
 +    __get_user(flags, &sve->flags);
 +
 +    sm = flags & TARGET_SVE_SIG_FLAG_SM;
 +
 +    /* The cpu must support Streaming or Non-streaming SVE. */
 +    if (sm
 +        ? !cpu_isar_feature(aa64_sme, env_archcpu(env))
 +        : !cpu_isar_feature(aa64_sve, env_archcpu(env))) {
          return false;
      }
 -    __get_user(vl, &sve->vl);
 -    vq = sve_vq(env);
 +    /*
 +     * Note that we cannot use sve_vq() because that depends on the
 +     * current setting of PSTATE.SM, not the state to be restored.
 +     */
 +    vq = sve_vqm1_for_el_sm(env, 0, sm) + 1;
      /* Reject mismatched VL. */
      if (vl != vq * TARGET_SVE_VQ_BYTES) {
@@ -XXX,XX +XXX,XX @@ static bool target_restore_sve_record(CPUARMState *env,
          return false;
      }
 +    *svcr = FIELD_DP64(*svcr, SVCR, SM, sm);
 +
      /*
-      * Note that SVE regs are stored as a byte stream, with each byte element
+      * ROM memory
-      * at a subsequent address.  This corresponds to a little-endian load
+      */
@@ -XXX,XX +XXX,XX @@ static bool target_restore_sve_record(CPUARMState *env,
      return true;
  }
 +static bool target_restore_za_record(CPUARMState *env,
 +                                     struct target_za_context *za,
 +                                     int size, int *svcr)
 +{
 +    int i, j, vl, vq;
 +
 +    if (!cpu_isar_feature(aa64_sme, env_archcpu(env))) {
 +        return false;
 +    }
 +
 +    __get_user(vl, &za->vl);
 +    vq = sme_vq(env);
 +
 +    /* Reject mismatched VL. */
 +    if (vl != vq * TARGET_SVE_VQ_BYTES) {
 +        return false;
 +    }
 +
 +    /* Accept empty record -- used to clear PSTATE.ZA. */
 +    if (size <= TARGET_ZA_SIG_CONTEXT_SIZE(0)) {
 +        return true;
 +    }
 +
 +    /* Reject non-empty but incomplete record. */
 +    if (size < TARGET_ZA_SIG_CONTEXT_SIZE(vq)) {
 +        return false;
 +    }
 +
 +    *svcr = FIELD_DP64(*svcr, SVCR, ZA, 1);
 +
 +    for (i = 0; i < vl; ++i) {
 +        uint64_t *z = (void *)za + TARGET_ZA_SIG_ZAV_OFFSET(vq, i);
 +        for (j = 0; j < vq * 2; ++j) {
 +            __get_user_e(env->zarray[i].d[j], z + j, le);
 +        }
 +    }
 +    return true;
 +}
 +
  static int target_restore_sigframe(CPUARMState *env,
                                     struct target_rt_sigframe *sf)
  {
      struct target_aarch64_ctx *ctx, *extra = NULL;
      struct target_fpsimd_context *fpsimd = NULL;
      struct target_sve_context *sve = NULL;
 +    struct target_za_context *za = NULL;
      uint64_t extra_datap = 0;
      bool used_extra = false;
      int sve_size = 0;
 +    int za_size = 0;
 +    int svcr = 0;
      target_restore_general_frame(env, sf);
@@ -XXX,XX +XXX,XX @@ static int target_restore_sigframe(CPUARMState *env,
              sve_size = size;
              break;
 +        case TARGET_ZA_MAGIC:
 +            if (za || size < sizeof(struct target_za_context)) {
 +                goto err;
 +            }
 +            za = (struct target_za_context *)ctx;
 +            za_size = size;
 +            break;
 +
          case TARGET_EXTRA_MAGIC:
              if (extra || size != sizeof(struct target_extra_context)) {
                  goto err;
@@ -XXX,XX +XXX,XX @@ static int target_restore_sigframe(CPUARMState *env,
      }
      /* SVE data, if present, overwrites FPSIMD data.  */
 -    if (sve && !target_restore_sve_record(env, sve, sve_size)) {
 +    if (sve && !target_restore_sve_record(env, sve, sve_size, &svcr)) {
          goto err;
      }
 +    if (za && !target_restore_za_record(env, za, za_size, &svcr)) {
 +        goto err;
 +    }
 +    if (env->svcr != svcr) {
 +        env->svcr = svcr;
 +        arm_rebuild_hflags(env);
 +    }
      unlock_user(extra, extra_datap, 0);
      return 0;
@@ -XXX,XX +XXX,XX @@ static void target_setup_frame(int usig, struct target_sigaction *ka,
          .total_size = offsetof(struct target_rt_sigframe,
                                 uc.tuc_mcontext.__reserved),
      };
 -    int fpsimd_ofs, fr_ofs, sve_ofs = 0, vq = 0, sve_size = 0;
 +    int fpsimd_ofs, fr_ofs, sve_ofs = 0, za_ofs = 0;
 +    int sve_size = 0, za_size = 0;
      struct target_rt_sigframe *frame;
      struct target_rt_frame_record *fr;
      abi_ulong frame_addr, return_addr;
@@ -XXX,XX +XXX,XX @@ static void target_setup_frame(int usig, struct target_sigaction *ka,
                                        &layout);
      /* SVE state needs saving only if it exists.  */
 -    if (cpu_isar_feature(aa64_sve, env_archcpu(env))) {
 -        vq = sve_vq(env);
 -        sve_size = QEMU_ALIGN_UP(TARGET_SVE_SIG_CONTEXT_SIZE(vq), 16);
 +    if (cpu_isar_feature(aa64_sve, env_archcpu(env)) ||
 +        cpu_isar_feature(aa64_sme, env_archcpu(env))) {
 +        sve_size = QEMU_ALIGN_UP(TARGET_SVE_SIG_CONTEXT_SIZE(sve_vq(env)), 16);
          sve_ofs = alloc_sigframe_space(sve_size, &layout);
      }
 +    if (cpu_isar_feature(aa64_sme, env_archcpu(env))) {
 +        /* ZA state needs saving only if it is enabled.  */
 +        if (FIELD_EX64(env->svcr, SVCR, ZA)) {
 +            za_size = TARGET_ZA_SIG_CONTEXT_SIZE(sme_vq(env));
 +        } else {
 +            za_size = TARGET_ZA_SIG_CONTEXT_SIZE(0);
 +        }
 +        za_ofs = alloc_sigframe_space(za_size, &layout);
 +    }
      if (layout.extra_ofs) {
          /* Reserve space for the extra end marker.  The standard end marker
@@ -XXX,XX +XXX,XX @@ static void target_setup_frame(int usig, struct target_sigaction *ka,
          target_setup_end_record((void *)frame + layout.extra_end_ofs);
      }
      if (sve_ofs) {
 -        target_setup_sve_record((void *)frame + sve_ofs, env, vq, sve_size);
 +        target_setup_sve_record((void *)frame + sve_ofs, env, sve_size);
 +    }
 +    if (za_ofs) {
 +        target_setup_za_record((void *)frame + za_ofs, env, za_size);
      }
      /* Set up the stack frame for unwinding.  */
@@ -XXX,XX +XXX,XX @@ static void target_setup_frame(int usig, struct target_sigaction *ka,
          env->btype = 2;
      }
 +    /*
 +     * Invoke the signal handler with both SM and ZA disabled.
 +     * When clearing SM, ResetSVEState, per SMSTOP.
 +     */
 +    if (FIELD_EX64(env->svcr, SVCR, SM)) {
 +        arm_reset_sve_state(env);
 +    }
 +    if (env->svcr) {
 +        env->svcr = 0;
 +        arm_rebuild_hflags(env);
 +    }
 +
      if (info) {
          tswap_siginfo(&frame->info, info);
          env->xregs[1] = frame_addr + offsetof(struct target_rt_sigframe, info);
 --
-.25.1
+.34.1

-[PULL 36/45] linux-user/aarch64: Tidy target_restore_sigframe error return
+[PULL 14/24] Refactor i.MX7 processor code
-From: Richard Henderson <richard.henderson@linaro.org>
+From: Jean-Christophe Dubois <jcd@tribudubois.net>
-Fold the return value setting into the goto, so each
+* Add Addr and size definition for all i.MX7 devices in i.MX7 header file.
-point of failure need not do both.
+* Use those newly defined named constants whenever possible.
 * Standardize the way we init a familly of unimplemented devices
   - SAI
   - PWM
   - CAN
 * Add/rework few comments
+Signed-off-by: Jean-Christophe Dubois <jcd@tribudubois.net>
+Message-id: 59e195d33e4d486a8d131392acd46633c8c10ed7.1692964892.git.jcd@tribudubois.net
 Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
-Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
-Message-id: 20220708151540.18136-37-richard.henderson@linaro.org
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 ---
- linux-user/aarch64/signal.c | 26 +++++++++++---------------
+ include/hw/arm/fsl-imx7.h | 330 ++++++++++++++++++++++++++++----------
-file changed, 11 insertions(+), 15 deletions(-)
+ hw/arm/fsl-imx7.c         | 130 ++++++++++-----
 files changed, 335 insertions(+), 125 deletions(-)
-diff --git a/linux-user/aarch64/signal.c b/linux-user/aarch64/signal.c
+diff --git a/include/hw/arm/fsl-imx7.h b/include/hw/arm/fsl-imx7.h
 index XXXXXXX..XXXXXXX 100644
---- a/linux-user/aarch64/signal.c
+--- a/include/hw/arm/fsl-imx7.h
-+++ b/linux-user/aarch64/signal.c
++++ b/include/hw/arm/fsl-imx7.h
-@@ -XXX,XX +XXX,XX @@ static int target_restore_sigframe(CPUARMState *env,
+@@ -XXX,XX +XXX,XX @@
-     struct target_sve_context *sve = NULL;
+ #include "hw/misc/imx7_ccm.h"
-     uint64_t extra_datap = 0;
+ #include "hw/misc/imx7_snvs.h"
-     bool used_extra = false;
+ #include "hw/misc/imx7_gpr.h"
--    bool err = false;
+-#include "hw/misc/imx6_src.h"
-     int vq = 0, sve_size = 0;
+ #include "hw/watchdog/wdt_imx2.h"
+ #include "hw/gpio/imx_gpio.h"
-     target_restore_general_frame(env, sf);
+ #include "hw/char/imx_serial.h"
-@@ -XXX,XX +XXX,XX @@ static int target_restore_sigframe(CPUARMState *env,
+@@ -XXX,XX +XXX,XX @@
-         switch (magic) {
+ #include "hw/usb/chipidea.h"
-         case 0:
+ #include "cpu.h"
-             if (size != 0) {
+ #include "qom/object.h"
--                err = true;
++#include "qemu/units.h"
--                goto exit;
-+                goto err;
+ #define TYPE_FSL_IMX7 "fsl-imx7"
-             }
+ OBJECT_DECLARE_SIMPLE_TYPE(FslIMX7State, FSL_IMX7)
-             if (used_extra) {
+@@ -XXX,XX +XXX,XX @@ enum FslIMX7Configuration {
-                 ctx = NULL;
+     FSL_IMX7_NUM_ECSPIS       = 4,
-@@ -XXX,XX +XXX,XX @@ static int target_restore_sigframe(CPUARMState *env,
+     FSL_IMX7_NUM_USBS         = 3,
+     FSL_IMX7_NUM_ADCS         = 2,
-         case TARGET_FPSIMD_MAGIC:
++    FSL_IMX7_NUM_SAIS         = 3,
-             if (fpsimd || size != sizeof(struct target_fpsimd_context)) {
++    FSL_IMX7_NUM_CANS         = 2,
--                err = true;
++    FSL_IMX7_NUM_PWMS         = 4,
--                goto exit;
+ };
-+                goto err;
-             }
+ struct FslIMX7State {
-             fpsimd = (struct target_fpsimd_context *)ctx;
+@@ -XXX,XX +XXX,XX @@ struct FslIMX7State {
-             break;
-@@ -XXX,XX +XXX,XX @@ static int target_restore_sigframe(CPUARMState *env,
+ enum FslIMX7MemoryMap {
-                     break;
+     FSL_IMX7_MMDC_ADDR            = 0x80000000,
-                 }
+-    FSL_IMX7_MMDC_SIZE            = 2 * 1024 * 1024 * 1024UL,
-             }
++    FSL_IMX7_MMDC_SIZE            = (2 * GiB),
--            err = true;
--            goto exit;
+-    FSL_IMX7_GPIO1_ADDR           = 0x30200000,
-+            goto err;
+-    FSL_IMX7_GPIO2_ADDR           = 0x30210000,
+-    FSL_IMX7_GPIO3_ADDR           = 0x30220000,
-         case TARGET_EXTRA_MAGIC:
+-    FSL_IMX7_GPIO4_ADDR           = 0x30230000,
-             if (extra || size != sizeof(struct target_extra_context)) {
+-    FSL_IMX7_GPIO5_ADDR           = 0x30240000,
--                err = true;
+-    FSL_IMX7_GPIO6_ADDR           = 0x30250000,
--                goto exit;
+-    FSL_IMX7_GPIO7_ADDR           = 0x30260000,
-+                goto err;
++    FSL_IMX7_QSPI1_MEM_ADDR       = 0x60000000,
-             }
++    FSL_IMX7_QSPI1_MEM_SIZE       = (256 * MiB),
-             __get_user(extra_datap,
-                        &((struct target_extra_context *)ctx)->datap);
+-    FSL_IMX7_IOMUXC_LPSR_GPR_ADDR = 0x30270000,
-@@ -XXX,XX +XXX,XX @@ static int target_restore_sigframe(CPUARMState *env,
++    FSL_IMX7_PCIE1_MEM_ADDR       = 0x40000000,
-             /* Unknown record -- we certainly didn't generate it.
++    FSL_IMX7_PCIE1_MEM_SIZE       = (256 * MiB),
-              * Did we in fact get out of sync?
-              */
+-    FSL_IMX7_WDOG1_ADDR           = 0x30280000,
--            err = true;
+-    FSL_IMX7_WDOG2_ADDR           = 0x30290000,
--            goto exit;
+-    FSL_IMX7_WDOG3_ADDR           = 0x302A0000,
-+            goto err;
+-    FSL_IMX7_WDOG4_ADDR           = 0x302B0000,
-         }
++    FSL_IMX7_QSPI1_RX_BUF_ADDR    = 0x34000000,
-         ctx = (void *)ctx + size;
++    FSL_IMX7_QSPI1_RX_BUF_SIZE    = (32 * MiB),
-     }
-@@ -XXX,XX +XXX,XX @@ static int target_restore_sigframe(CPUARMState *env,
+-    FSL_IMX7_IOMUXC_LPSR_ADDR     = 0x302C0000,
-     if (fpsimd) {
++    /* PCIe Peripherals */
-         target_restore_fpsimd_record(env, fpsimd);
++    FSL_IMX7_PCIE_REG_ADDR        = 0x33800000,
-     } else {
--        err = true;
+-    FSL_IMX7_GPT1_ADDR            = 0x302D0000,
-+        goto err;
+-    FSL_IMX7_GPT2_ADDR            = 0x302E0000,
-     }
+-    FSL_IMX7_GPT3_ADDR            = 0x302F0000,
+-    FSL_IMX7_GPT4_ADDR            = 0x30300000,
-     /* SVE data, if present, overwrites FPSIMD data.  */
++    /* MMAP Peripherals */
-     if (sve) {
++    FSL_IMX7_DMA_APBH_ADDR        = 0x33000000,
-         target_restore_sve_record(env, sve, vq);
++    FSL_IMX7_DMA_APBH_SIZE        = 0x8000,
-     }
 -    FSL_IMX7_IOMUXC_ADDR          = 0x30330000,
 -    FSL_IMX7_IOMUXC_GPR_ADDR      = 0x30340000,
 -    FSL_IMX7_IOMUXCn_SIZE         = 0x1000,
 +    /* GPV configuration */
 +    FSL_IMX7_GPV6_ADDR            = 0x32600000,
 +    FSL_IMX7_GPV5_ADDR            = 0x32500000,
 +    FSL_IMX7_GPV4_ADDR            = 0x32400000,
 +    FSL_IMX7_GPV3_ADDR            = 0x32300000,
 +    FSL_IMX7_GPV2_ADDR            = 0x32200000,
 +    FSL_IMX7_GPV1_ADDR            = 0x32100000,
 +    FSL_IMX7_GPV0_ADDR            = 0x32000000,
 +    FSL_IMX7_GPVn_SIZE            = (1 * MiB),
 -    FSL_IMX7_OCOTP_ADDR           = 0x30350000,
 -    FSL_IMX7_OCOTP_SIZE           = 0x10000,
 +    /* Arm Peripherals */
 +    FSL_IMX7_A7MPCORE_ADDR        = 0x31000000,
 -    FSL_IMX7_ANALOG_ADDR          = 0x30360000,
 -    FSL_IMX7_SNVS_ADDR            = 0x30370000,
 -    FSL_IMX7_CCM_ADDR             = 0x30380000,
 +    /* AIPS-3 Begin */
 -    FSL_IMX7_SRC_ADDR             = 0x30390000,
 -    FSL_IMX7_SRC_SIZE             = 0x1000,
 +    FSL_IMX7_ENET2_ADDR           = 0x30BF0000,
 +    FSL_IMX7_ENET1_ADDR           = 0x30BE0000,
 -    FSL_IMX7_ADC1_ADDR            = 0x30610000,
 -    FSL_IMX7_ADC2_ADDR            = 0x30620000,
 -    FSL_IMX7_ADCn_SIZE            = 0x1000,
 +    FSL_IMX7_SDMA_ADDR            = 0x30BD0000,
 +    FSL_IMX7_SDMA_SIZE            = (4 * KiB),
 -    FSL_IMX7_PWM1_ADDR            = 0x30660000,
 -    FSL_IMX7_PWM2_ADDR            = 0x30670000,
 -    FSL_IMX7_PWM3_ADDR            = 0x30680000,
 -    FSL_IMX7_PWM4_ADDR            = 0x30690000,
 -    FSL_IMX7_PWMn_SIZE            = 0x10000,
 +    FSL_IMX7_EIM_ADDR             = 0x30BC0000,
 +    FSL_IMX7_EIM_SIZE             = (4 * KiB),
 -    FSL_IMX7_PCIE_PHY_ADDR        = 0x306D0000,
 -    FSL_IMX7_PCIE_PHY_SIZE        = 0x10000,
 +    FSL_IMX7_QSPI_ADDR            = 0x30BB0000,
 +    FSL_IMX7_QSPI_SIZE            = 0x8000,
 -    FSL_IMX7_GPC_ADDR             = 0x303A0000,
 +    FSL_IMX7_SIM2_ADDR            = 0x30BA0000,
 +    FSL_IMX7_SIM1_ADDR            = 0x30B90000,
 +    FSL_IMX7_SIMn_SIZE            = (4 * KiB),
 +
 +    FSL_IMX7_USDHC3_ADDR          = 0x30B60000,
 +    FSL_IMX7_USDHC2_ADDR          = 0x30B50000,
 +    FSL_IMX7_USDHC1_ADDR          = 0x30B40000,
 +
 +    FSL_IMX7_USB3_ADDR            = 0x30B30000,
 +    FSL_IMX7_USBMISC3_ADDR        = 0x30B30200,
 +    FSL_IMX7_USB2_ADDR            = 0x30B20000,
 +    FSL_IMX7_USBMISC2_ADDR        = 0x30B20200,
 +    FSL_IMX7_USB1_ADDR            = 0x30B10000,
 +    FSL_IMX7_USBMISC1_ADDR        = 0x30B10200,
 +    FSL_IMX7_USBMISCn_SIZE        = 0x200,
 +
 +    FSL_IMX7_USB_PL301_ADDR       = 0x30AD0000,
 +    FSL_IMX7_USB_PL301_SIZE       = (64 * KiB),
 +
 +    FSL_IMX7_SEMAPHORE_HS_ADDR    = 0x30AC0000,
 +    FSL_IMX7_SEMAPHORE_HS_SIZE    = (64 * KiB),
 +
 +    FSL_IMX7_MUB_ADDR             = 0x30AB0000,
 +    FSL_IMX7_MUA_ADDR             = 0x30AA0000,
 +    FSL_IMX7_MUn_SIZE             = (KiB),
 +
 +    FSL_IMX7_UART7_ADDR           = 0x30A90000,
 +    FSL_IMX7_UART6_ADDR           = 0x30A80000,
 +    FSL_IMX7_UART5_ADDR           = 0x30A70000,
 +    FSL_IMX7_UART4_ADDR           = 0x30A60000,
 +
 +    FSL_IMX7_I2C4_ADDR            = 0x30A50000,
 +    FSL_IMX7_I2C3_ADDR            = 0x30A40000,
 +    FSL_IMX7_I2C2_ADDR            = 0x30A30000,
 +    FSL_IMX7_I2C1_ADDR            = 0x30A20000,
 +
 +    FSL_IMX7_CAN2_ADDR            = 0x30A10000,
 +    FSL_IMX7_CAN1_ADDR            = 0x30A00000,
 +    FSL_IMX7_CANn_SIZE            = (4 * KiB),
 +
 +    FSL_IMX7_AIPS3_CONF_ADDR      = 0x309F0000,
 +    FSL_IMX7_AIPS3_CONF_SIZE      = (64 * KiB),
      FSL_IMX7_CAAM_ADDR            = 0x30900000,
 -    FSL_IMX7_CAAM_SIZE            = 0x40000,
 +    FSL_IMX7_CAAM_SIZE            = (256 * KiB),
 -    FSL_IMX7_CAN1_ADDR            = 0x30A00000,
 -    FSL_IMX7_CAN2_ADDR            = 0x30A10000,
 -    FSL_IMX7_CANn_SIZE            = 0x10000,
 +    FSL_IMX7_SPBA_ADDR            = 0x308F0000,
 +    FSL_IMX7_SPBA_SIZE            = (4 * KiB),
 -    FSL_IMX7_I2C1_ADDR            = 0x30A20000,
 -    FSL_IMX7_I2C2_ADDR            = 0x30A30000,
 -    FSL_IMX7_I2C3_ADDR            = 0x30A40000,
 -    FSL_IMX7_I2C4_ADDR            = 0x30A50000,
 +    FSL_IMX7_SAI3_ADDR            = 0x308C0000,
 +    FSL_IMX7_SAI2_ADDR            = 0x308B0000,
 +    FSL_IMX7_SAI1_ADDR            = 0x308A0000,
 +    FSL_IMX7_SAIn_SIZE            = (4 * KiB),
 -    FSL_IMX7_ECSPI1_ADDR          = 0x30820000,
 -    FSL_IMX7_ECSPI2_ADDR          = 0x30830000,
 -    FSL_IMX7_ECSPI3_ADDR          = 0x30840000,
 -    FSL_IMX7_ECSPI4_ADDR          = 0x30630000,
 -
-- exit:
+-    FSL_IMX7_LCDIF_ADDR           = 0x30730000,
-     unlock_user(extra, extra_datap, 0);
+-    FSL_IMX7_LCDIF_SIZE           = 0x1000,
--    return err;
+-
-+    return 0;
+-    FSL_IMX7_UART1_ADDR           = 0x30860000,
-+
++    FSL_IMX7_UART3_ADDR           = 0x30880000,
-+ err:
+     /*
-+    unlock_user(extra, extra_datap, 0);
+      * Some versions of the reference manual claim that UART2 is @
-+    return 1;
+      * 0x30870000, but experiments with HW + DT files in upstream
@@ -XXX,XX +XXX,XX @@ enum FslIMX7MemoryMap {
       * actually located @ 0x30890000
       */
      FSL_IMX7_UART2_ADDR           = 0x30890000,
 -    FSL_IMX7_UART3_ADDR           = 0x30880000,
 -    FSL_IMX7_UART4_ADDR           = 0x30A60000,
 -    FSL_IMX7_UART5_ADDR           = 0x30A70000,
 -    FSL_IMX7_UART6_ADDR           = 0x30A80000,
 -    FSL_IMX7_UART7_ADDR           = 0x30A90000,
 +    FSL_IMX7_UART1_ADDR           = 0x30860000,
 -    FSL_IMX7_SAI1_ADDR            = 0x308A0000,
 -    FSL_IMX7_SAI2_ADDR            = 0x308B0000,
 -    FSL_IMX7_SAI3_ADDR            = 0x308C0000,
 -    FSL_IMX7_SAIn_SIZE            = 0x10000,
 +    FSL_IMX7_ECSPI3_ADDR          = 0x30840000,
 +    FSL_IMX7_ECSPI2_ADDR          = 0x30830000,
 +    FSL_IMX7_ECSPI1_ADDR          = 0x30820000,
 +    FSL_IMX7_ECSPIn_SIZE          = (4 * KiB),
 -    FSL_IMX7_ENET1_ADDR           = 0x30BE0000,
 -    FSL_IMX7_ENET2_ADDR           = 0x30BF0000,
 +    /* AIPS-3 End */
 -    FSL_IMX7_USB1_ADDR            = 0x30B10000,
 -    FSL_IMX7_USBMISC1_ADDR        = 0x30B10200,
 -    FSL_IMX7_USB2_ADDR            = 0x30B20000,
 -    FSL_IMX7_USBMISC2_ADDR        = 0x30B20200,
 -    FSL_IMX7_USB3_ADDR            = 0x30B30000,
 -    FSL_IMX7_USBMISC3_ADDR        = 0x30B30200,
 -    FSL_IMX7_USBMISCn_SIZE        = 0x200,
 +    /* AIPS-2 Begin */
 -    FSL_IMX7_USDHC1_ADDR          = 0x30B40000,
 -    FSL_IMX7_USDHC2_ADDR          = 0x30B50000,
 -    FSL_IMX7_USDHC3_ADDR          = 0x30B60000,
 +    FSL_IMX7_AXI_DEBUG_MON_ADDR   = 0x307E0000,
 +    FSL_IMX7_AXI_DEBUG_MON_SIZE   = (64 * KiB),
 -    FSL_IMX7_SDMA_ADDR            = 0x30BD0000,
 -    FSL_IMX7_SDMA_SIZE            = 0x1000,
 +    FSL_IMX7_PERFMON2_ADDR        = 0x307D0000,
 +    FSL_IMX7_PERFMON1_ADDR        = 0x307C0000,
 +    FSL_IMX7_PERFMONn_SIZE        = (64 * KiB),
 +
 +    FSL_IMX7_DDRC_ADDR            = 0x307A0000,
 +    FSL_IMX7_DDRC_SIZE            = (4 * KiB),
 +
 +    FSL_IMX7_DDRC_PHY_ADDR        = 0x30790000,
 +    FSL_IMX7_DDRC_PHY_SIZE        = (4 * KiB),
 +
 +    FSL_IMX7_TZASC_ADDR           = 0x30780000,
 +    FSL_IMX7_TZASC_SIZE           = (64 * KiB),
 +
 +    FSL_IMX7_MIPI_DSI_ADDR        = 0x30760000,
 +    FSL_IMX7_MIPI_DSI_SIZE        = (4 * KiB),
 +
 +    FSL_IMX7_MIPI_CSI_ADDR        = 0x30750000,
 +    FSL_IMX7_MIPI_CSI_SIZE        = 0x4000,
 +
 +    FSL_IMX7_LCDIF_ADDR           = 0x30730000,
 +    FSL_IMX7_LCDIF_SIZE           = 0x8000,
 +
 +    FSL_IMX7_CSI_ADDR             = 0x30710000,
 +    FSL_IMX7_CSI_SIZE             = (4 * KiB),
 +
 +    FSL_IMX7_PXP_ADDR             = 0x30700000,
 +    FSL_IMX7_PXP_SIZE             = 0x4000,
 +
 +    FSL_IMX7_EPDC_ADDR            = 0x306F0000,
 +    FSL_IMX7_EPDC_SIZE            = (4 * KiB),
 +
 +    FSL_IMX7_PCIE_PHY_ADDR        = 0x306D0000,
 +    FSL_IMX7_PCIE_PHY_SIZE        = (4 * KiB),
 +
 +    FSL_IMX7_SYSCNT_CTRL_ADDR     = 0x306C0000,
 +    FSL_IMX7_SYSCNT_CMP_ADDR      = 0x306B0000,
 +    FSL_IMX7_SYSCNT_RD_ADDR       = 0x306A0000,
 +
 +    FSL_IMX7_PWM4_ADDR            = 0x30690000,
 +    FSL_IMX7_PWM3_ADDR            = 0x30680000,
 +    FSL_IMX7_PWM2_ADDR            = 0x30670000,
 +    FSL_IMX7_PWM1_ADDR            = 0x30660000,
 +    FSL_IMX7_PWMn_SIZE            = (4 * KiB),
 +
 +    FSL_IMX7_FlEXTIMER2_ADDR      = 0x30650000,
 +    FSL_IMX7_FlEXTIMER1_ADDR      = 0x30640000,
 +    FSL_IMX7_FLEXTIMERn_SIZE      = (4 * KiB),
 +
 +    FSL_IMX7_ECSPI4_ADDR          = 0x30630000,
 +
 +    FSL_IMX7_ADC2_ADDR            = 0x30620000,
 +    FSL_IMX7_ADC1_ADDR            = 0x30610000,
 +    FSL_IMX7_ADCn_SIZE            = (4 * KiB),
 +
 +    FSL_IMX7_AIPS2_CONF_ADDR      = 0x305F0000,
 +    FSL_IMX7_AIPS2_CONF_SIZE      = (64 * KiB),
 +
 +    /* AIPS-2 End */
 +
 +    /* AIPS-1 Begin */
 +
 +    FSL_IMX7_CSU_ADDR             = 0x303E0000,
 +    FSL_IMX7_CSU_SIZE             = (64 * KiB),
 +
 +    FSL_IMX7_RDC_ADDR             = 0x303D0000,
 +    FSL_IMX7_RDC_SIZE             = (4 * KiB),
 +
 +    FSL_IMX7_SEMAPHORE2_ADDR      = 0x303C0000,
 +    FSL_IMX7_SEMAPHORE1_ADDR      = 0x303B0000,
 +    FSL_IMX7_SEMAPHOREn_SIZE      = (4 * KiB),
 +
 +    FSL_IMX7_GPC_ADDR             = 0x303A0000,
 +
 +    FSL_IMX7_SRC_ADDR             = 0x30390000,
 +    FSL_IMX7_SRC_SIZE             = (4 * KiB),
 +
 +    FSL_IMX7_CCM_ADDR             = 0x30380000,
 +
 +    FSL_IMX7_SNVS_HP_ADDR         = 0x30370000,
 +
 +    FSL_IMX7_ANALOG_ADDR          = 0x30360000,
 +
 +    FSL_IMX7_OCOTP_ADDR           = 0x30350000,
 +    FSL_IMX7_OCOTP_SIZE           = 0x10000,
 +
 +    FSL_IMX7_IOMUXC_GPR_ADDR      = 0x30340000,
 +    FSL_IMX7_IOMUXC_GPR_SIZE      = (4 * KiB),
 +
 +    FSL_IMX7_IOMUXC_ADDR          = 0x30330000,
 +    FSL_IMX7_IOMUXC_SIZE          = (4 * KiB),
 +
 +    FSL_IMX7_KPP_ADDR             = 0x30320000,
 +    FSL_IMX7_KPP_SIZE             = (4 * KiB),
 +
 +    FSL_IMX7_ROMCP_ADDR           = 0x30310000,
 +    FSL_IMX7_ROMCP_SIZE           = (4 * KiB),
 +
 +    FSL_IMX7_GPT4_ADDR            = 0x30300000,
 +    FSL_IMX7_GPT3_ADDR            = 0x302F0000,
 +    FSL_IMX7_GPT2_ADDR            = 0x302E0000,
 +    FSL_IMX7_GPT1_ADDR            = 0x302D0000,
 +
 +    FSL_IMX7_IOMUXC_LPSR_ADDR     = 0x302C0000,
 +    FSL_IMX7_IOMUXC_LPSR_SIZE     = (4 * KiB),
 +
 +    FSL_IMX7_WDOG4_ADDR           = 0x302B0000,
 +    FSL_IMX7_WDOG3_ADDR           = 0x302A0000,
 +    FSL_IMX7_WDOG2_ADDR           = 0x30290000,
 +    FSL_IMX7_WDOG1_ADDR           = 0x30280000,
 +
 +    FSL_IMX7_IOMUXC_LPSR_GPR_ADDR = 0x30270000,
 +
 +    FSL_IMX7_GPIO7_ADDR           = 0x30260000,
 +    FSL_IMX7_GPIO6_ADDR           = 0x30250000,
 +    FSL_IMX7_GPIO5_ADDR           = 0x30240000,
 +    FSL_IMX7_GPIO4_ADDR           = 0x30230000,
 +    FSL_IMX7_GPIO3_ADDR           = 0x30220000,
 +    FSL_IMX7_GPIO2_ADDR           = 0x30210000,
 +    FSL_IMX7_GPIO1_ADDR           = 0x30200000,
 +
 +    FSL_IMX7_AIPS1_CONF_ADDR      = 0x301F0000,
 +    FSL_IMX7_AIPS1_CONF_SIZE      = (64 * KiB),
 -    FSL_IMX7_A7MPCORE_ADDR        = 0x31000000,
      FSL_IMX7_A7MPCORE_DAP_ADDR    = 0x30000000,
 +    FSL_IMX7_A7MPCORE_DAP_SIZE    = (1 * MiB),
 -    FSL_IMX7_PCIE_REG_ADDR        = 0x33800000,
 -    FSL_IMX7_PCIE_REG_SIZE        = 16 * 1024,
 +    /* AIPS-1 End */
 -    FSL_IMX7_GPR_ADDR             = 0x30340000,
 +    FSL_IMX7_EIM_CS0_ADDR         = 0x28000000,
 +    FSL_IMX7_EIM_CS0_SIZE         = (128 * MiB),
 -    FSL_IMX7_DMA_APBH_ADDR        = 0x33000000,
 -    FSL_IMX7_DMA_APBH_SIZE        = 0x2000,
 +    FSL_IMX7_OCRAM_PXP_ADDR       = 0x00940000,
 +    FSL_IMX7_OCRAM_PXP_SIZE       = (32 * KiB),
 +
 +    FSL_IMX7_OCRAM_EPDC_ADDR      = 0x00920000,
 +    FSL_IMX7_OCRAM_EPDC_SIZE      = (128 * KiB),
 +
 +    FSL_IMX7_OCRAM_MEM_ADDR       = 0x00900000,
 +    FSL_IMX7_OCRAM_MEM_SIZE       = (128 * KiB),
 +
 +    FSL_IMX7_TCMU_ADDR            = 0x00800000,
 +    FSL_IMX7_TCMU_SIZE            = (32 * KiB),
 +
 +    FSL_IMX7_TCML_ADDR            = 0x007F8000,
 +    FSL_IMX7_TCML_SIZE            = (32 * KiB),
 +
 +    FSL_IMX7_OCRAM_S_ADDR         = 0x00180000,
 +    FSL_IMX7_OCRAM_S_SIZE         = (32 * KiB),
 +
 +    FSL_IMX7_CAAM_MEM_ADDR        = 0x00100000,
 +    FSL_IMX7_CAAM_MEM_SIZE        = (32 * KiB),
 +
 +    FSL_IMX7_ROM_ADDR             = 0x00000000,
 +    FSL_IMX7_ROM_SIZE             = (96 * KiB),
  };
  enum FslIMX7IRQs {
 diff --git a/hw/arm/fsl-imx7.c b/hw/arm/fsl-imx7.c
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/arm/fsl-imx7.c
 +++ b/hw/arm/fsl-imx7.c
@@ -XXX,XX +XXX,XX @@ static void fsl_imx7_init(Object *obj)
      char name[NAME_SIZE];
      int i;
 +    /*
 +     * CPUs
 +     */
      for (i = 0; i < MIN(ms->smp.cpus, FSL_IMX7_NUM_CPUS); i++) {
          snprintf(name, NAME_SIZE, "cpu%d", i);
          object_initialize_child(obj, name, &s->cpu[i],
@@ -XXX,XX +XXX,XX @@ static void fsl_imx7_init(Object *obj)
                              TYPE_A15MPCORE_PRIV);
      /*
 -     * GPIOs 1 to 7
 +     * GPIOs
       */
      for (i = 0; i < FSL_IMX7_NUM_GPIOS; i++) {
          snprintf(name, NAME_SIZE, "gpio%d", i);
@@ -XXX,XX +XXX,XX @@ static void fsl_imx7_init(Object *obj)
      }
      /*
 -     * GPT1, 2, 3, 4
 +     * GPTs
       */
      for (i = 0; i < FSL_IMX7_NUM_GPTS; i++) {
          snprintf(name, NAME_SIZE, "gpt%d", i);
@@ -XXX,XX +XXX,XX @@ static void fsl_imx7_init(Object *obj)
       */
      object_initialize_child(obj, "gpcv2", &s->gpcv2, TYPE_IMX_GPCV2);
 +    /*
 +     * ECSPIs
 +     */
      for (i = 0; i < FSL_IMX7_NUM_ECSPIS; i++) {
          snprintf(name, NAME_SIZE, "spi%d", i + 1);
          object_initialize_child(obj, name, &s->spi[i], TYPE_IMX_SPI);
      }
 -
 +    /*
 +     * I2Cs
 +     */
      for (i = 0; i < FSL_IMX7_NUM_I2CS; i++) {
          snprintf(name, NAME_SIZE, "i2c%d", i + 1);
          object_initialize_child(obj, name, &s->i2c[i], TYPE_IMX_I2C);
      }
      /*
 -     * UART
 +     * UARTs
       */
      for (i = 0; i < FSL_IMX7_NUM_UARTS; i++) {
              snprintf(name, NAME_SIZE, "uart%d", i);
@@ -XXX,XX +XXX,XX @@ static void fsl_imx7_init(Object *obj)
      }
      /*
 -     * Ethernet
 +     * Ethernets
       */
      for (i = 0; i < FSL_IMX7_NUM_ETHS; i++) {
              snprintf(name, NAME_SIZE, "eth%d", i);
@@ -XXX,XX +XXX,XX @@ static void fsl_imx7_init(Object *obj)
      }
      /*
 -     * SDHCI
 +     * SDHCIs
       */
      for (i = 0; i < FSL_IMX7_NUM_USDHCS; i++) {
              snprintf(name, NAME_SIZE, "usdhc%d", i);
@@ -XXX,XX +XXX,XX @@ static void fsl_imx7_init(Object *obj)
      object_initialize_child(obj, "snvs", &s->snvs, TYPE_IMX7_SNVS);
      /*
 -     * Watchdog
 +     * Watchdogs
       */
      for (i = 0; i < FSL_IMX7_NUM_WDTS; i++) {
              snprintf(name, NAME_SIZE, "wdt%d", i);
@@ -XXX,XX +XXX,XX @@ static void fsl_imx7_init(Object *obj)
       */
      object_initialize_child(obj, "gpr", &s->gpr, TYPE_IMX7_GPR);
 +    /*
 +     * PCIE
 +     */
      object_initialize_child(obj, "pcie", &s->pcie, TYPE_DESIGNWARE_PCIE_HOST);
 +    /*
 +     * USBs
 +     */
      for (i = 0; i < FSL_IMX7_NUM_USBS; i++) {
          snprintf(name, NAME_SIZE, "usb%d", i);
          object_initialize_child(obj, name, &s->usb[i], TYPE_CHIPIDEA);
@@ -XXX,XX +XXX,XX @@ static void fsl_imx7_realize(DeviceState *dev, Error **errp)
          return;
      }
 +    /*
 +     * CPUs
 +     */
      for (i = 0; i < smp_cpus; i++) {
          o = OBJECT(&s->cpu[i]);
@@ -XXX,XX +XXX,XX @@ static void fsl_imx7_realize(DeviceState *dev, Error **errp)
       * A7MPCORE DAP
       */
      create_unimplemented_device("a7mpcore-dap", FSL_IMX7_A7MPCORE_DAP_ADDR,
 -                                0x100000);
 +                                FSL_IMX7_A7MPCORE_DAP_SIZE);
      /*
 -     * GPT1, 2, 3, 4
 +     * GPTs
       */
      for (i = 0; i < FSL_IMX7_NUM_GPTS; i++) {
          static const hwaddr FSL_IMX7_GPTn_ADDR[FSL_IMX7_NUM_GPTS] = {
@@ -XXX,XX +XXX,XX @@ static void fsl_imx7_realize(DeviceState *dev, Error **errp)
                                              FSL_IMX7_GPTn_IRQ[i]));
      }
 +    /*
 +     * GPIOs
 +     */
      for (i = 0; i < FSL_IMX7_NUM_GPIOS; i++) {
          static const hwaddr FSL_IMX7_GPIOn_ADDR[FSL_IMX7_NUM_GPIOS] = {
              FSL_IMX7_GPIO1_ADDR,
@@ -XXX,XX +XXX,XX @@ static void fsl_imx7_realize(DeviceState *dev, Error **errp)
      /*
       * IOMUXC and IOMUXC_LPSR
       */
 -    for (i = 0; i < FSL_IMX7_NUM_IOMUXCS; i++) {
 -        static const hwaddr FSL_IMX7_IOMUXCn_ADDR[FSL_IMX7_NUM_IOMUXCS] = {
 -            FSL_IMX7_IOMUXC_ADDR,
 -            FSL_IMX7_IOMUXC_LPSR_ADDR,
 -        };
 -
 -        snprintf(name, NAME_SIZE, "iomuxc%d", i);
 -        create_unimplemented_device(name, FSL_IMX7_IOMUXCn_ADDR[i],
 -                                    FSL_IMX7_IOMUXCn_SIZE);
 -    }
 +    create_unimplemented_device("iomuxc", FSL_IMX7_IOMUXC_ADDR,
 +                                FSL_IMX7_IOMUXC_SIZE);
 +    create_unimplemented_device("iomuxc_lspr", FSL_IMX7_IOMUXC_LPSR_ADDR,
 +                                FSL_IMX7_IOMUXC_LPSR_SIZE);
      /*
       * CCM
@@ -XXX,XX +XXX,XX @@ static void fsl_imx7_realize(DeviceState *dev, Error **errp)
      sysbus_realize(SYS_BUS_DEVICE(&s->gpcv2), &error_abort);
      sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpcv2), 0, FSL_IMX7_GPC_ADDR);
 -    /* Initialize all ECSPI */
 +    /*
 +     * ECSPIs
 +     */
      for (i = 0; i < FSL_IMX7_NUM_ECSPIS; i++) {
          static const hwaddr FSL_IMX7_SPIn_ADDR[FSL_IMX7_NUM_ECSPIS] = {
              FSL_IMX7_ECSPI1_ADDR,
@@ -XXX,XX +XXX,XX @@ static void fsl_imx7_realize(DeviceState *dev, Error **errp)
                                              FSL_IMX7_SPIn_IRQ[i]));
      }
 +    /*
 +     * I2Cs
 +     */
      for (i = 0; i < FSL_IMX7_NUM_I2CS; i++) {
          static const hwaddr FSL_IMX7_I2Cn_ADDR[FSL_IMX7_NUM_I2CS] = {
              FSL_IMX7_I2C1_ADDR,
@@ -XXX,XX +XXX,XX @@ static void fsl_imx7_realize(DeviceState *dev, Error **errp)
      }
      /*
 -     * UART
 +     * UARTs
       */
      for (i = 0; i < FSL_IMX7_NUM_UARTS; i++) {
          static const hwaddr FSL_IMX7_UARTn_ADDR[FSL_IMX7_NUM_UARTS] = {
@@ -XXX,XX +XXX,XX @@ static void fsl_imx7_realize(DeviceState *dev, Error **errp)
      }
      /*
 -     * Ethernet
 +     * Ethernets
       *
       * We must use two loops since phy_connected affects the other interface
       * and we have to set all properties before calling sysbus_realize().
@@ -XXX,XX +XXX,XX @@ static void fsl_imx7_realize(DeviceState *dev, Error **errp)
      }
      /*
 -     * USDHC
 +     * USDHCs
       */
      for (i = 0; i < FSL_IMX7_NUM_USDHCS; i++) {
          static const hwaddr FSL_IMX7_USDHCn_ADDR[FSL_IMX7_NUM_USDHCS] = {
@@ -XXX,XX +XXX,XX @@ static void fsl_imx7_realize(DeviceState *dev, Error **errp)
       * SNVS
       */
      sysbus_realize(SYS_BUS_DEVICE(&s->snvs), &error_abort);
 -    sysbus_mmio_map(SYS_BUS_DEVICE(&s->snvs), 0, FSL_IMX7_SNVS_ADDR);
 +    sysbus_mmio_map(SYS_BUS_DEVICE(&s->snvs), 0, FSL_IMX7_SNVS_HP_ADDR);
      /*
       * SRC
@@ -XXX,XX +XXX,XX @@ static void fsl_imx7_realize(DeviceState *dev, Error **errp)
      create_unimplemented_device("src", FSL_IMX7_SRC_ADDR, FSL_IMX7_SRC_SIZE);
      /*
 -     * Watchdog
 +     * Watchdogs
       */
      for (i = 0; i < FSL_IMX7_NUM_WDTS; i++) {
          static const hwaddr FSL_IMX7_WDOGn_ADDR[FSL_IMX7_NUM_WDTS] = {
@@ -XXX,XX +XXX,XX @@ static void fsl_imx7_realize(DeviceState *dev, Error **errp)
      create_unimplemented_device("caam", FSL_IMX7_CAAM_ADDR, FSL_IMX7_CAAM_SIZE);
      /*
 -     * PWM
 +     * PWMs
       */
 -    create_unimplemented_device("pwm1", FSL_IMX7_PWM1_ADDR, FSL_IMX7_PWMn_SIZE);
 -    create_unimplemented_device("pwm2", FSL_IMX7_PWM2_ADDR, FSL_IMX7_PWMn_SIZE);
 -    create_unimplemented_device("pwm3", FSL_IMX7_PWM3_ADDR, FSL_IMX7_PWMn_SIZE);
 -    create_unimplemented_device("pwm4", FSL_IMX7_PWM4_ADDR, FSL_IMX7_PWMn_SIZE);
 +    for (i = 0; i < FSL_IMX7_NUM_PWMS; i++) {
 +        static const hwaddr FSL_IMX7_PWMn_ADDR[FSL_IMX7_NUM_PWMS] = {
 +            FSL_IMX7_PWM1_ADDR,
 +            FSL_IMX7_PWM2_ADDR,
 +            FSL_IMX7_PWM3_ADDR,
 +            FSL_IMX7_PWM4_ADDR,
 +        };
 +
 +        snprintf(name, NAME_SIZE, "pwm%d", i);
 +        create_unimplemented_device(name, FSL_IMX7_PWMn_ADDR[i],
 +                                    FSL_IMX7_PWMn_SIZE);
 +    }
      /*
 -     * CAN
 +     * CANs
       */
 -    create_unimplemented_device("can1", FSL_IMX7_CAN1_ADDR, FSL_IMX7_CANn_SIZE);
 -    create_unimplemented_device("can2", FSL_IMX7_CAN2_ADDR, FSL_IMX7_CANn_SIZE);
 +    for (i = 0; i < FSL_IMX7_NUM_CANS; i++) {
 +        static const hwaddr FSL_IMX7_CANn_ADDR[FSL_IMX7_NUM_CANS] = {
 +            FSL_IMX7_CAN1_ADDR,
 +            FSL_IMX7_CAN2_ADDR,
 +        };
 +
 +        snprintf(name, NAME_SIZE, "can%d", i);
 +        create_unimplemented_device(name, FSL_IMX7_CANn_ADDR[i],
 +                                    FSL_IMX7_CANn_SIZE);
 +    }
      /*
 -     * SAI (Audio SSI (Synchronous Serial Interface))
 +     * SAIs (Audio SSI (Synchronous Serial Interface))
       */
 -    create_unimplemented_device("sai1", FSL_IMX7_SAI1_ADDR, FSL_IMX7_SAIn_SIZE);
 -    create_unimplemented_device("sai2", FSL_IMX7_SAI2_ADDR, FSL_IMX7_SAIn_SIZE);
 -    create_unimplemented_device("sai2", FSL_IMX7_SAI3_ADDR, FSL_IMX7_SAIn_SIZE);
 +    for (i = 0; i < FSL_IMX7_NUM_SAIS; i++) {
 +        static const hwaddr FSL_IMX7_SAIn_ADDR[FSL_IMX7_NUM_SAIS] = {
 +            FSL_IMX7_SAI1_ADDR,
 +            FSL_IMX7_SAI2_ADDR,
 +            FSL_IMX7_SAI3_ADDR,
 +        };
 +
 +        snprintf(name, NAME_SIZE, "sai%d", i);
 +        create_unimplemented_device(name, FSL_IMX7_SAIn_ADDR[i],
 +                                    FSL_IMX7_SAIn_SIZE);
 +    }
      /*
       * OCOTP
@@ -XXX,XX +XXX,XX @@ static void fsl_imx7_realize(DeviceState *dev, Error **errp)
      create_unimplemented_device("ocotp", FSL_IMX7_OCOTP_ADDR,
                                  FSL_IMX7_OCOTP_SIZE);
 +    /*
 +     * GPR
 +     */
      sysbus_realize(SYS_BUS_DEVICE(&s->gpr), &error_abort);
 -    sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpr), 0, FSL_IMX7_GPR_ADDR);
 +    sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpr), 0, FSL_IMX7_IOMUXC_GPR_ADDR);
 +    /*
 +     * PCIE
 +     */
      sysbus_realize(SYS_BUS_DEVICE(&s->pcie), &error_abort);
      sysbus_mmio_map(SYS_BUS_DEVICE(&s->pcie), 0, FSL_IMX7_PCIE_REG_ADDR);
@@ -XXX,XX +XXX,XX @@ static void fsl_imx7_realize(DeviceState *dev, Error **errp)
      irq = qdev_get_gpio_in(DEVICE(&s->a7mpcore), FSL_IMX7_PCI_INTD_IRQ);
      sysbus_connect_irq(SYS_BUS_DEVICE(&s->pcie), 3, irq);
 -
 +    /*
 +     * USBs
 +     */
      for (i = 0; i < FSL_IMX7_NUM_USBS; i++) {
          static const hwaddr FSL_IMX7_USBMISCn_ADDR[FSL_IMX7_NUM_USBS] = {
              FSL_IMX7_USBMISC1_ADDR,
@@ -XXX,XX +XXX,XX @@ static void fsl_imx7_realize(DeviceState *dev, Error **errp)
       */
      create_unimplemented_device("pcie-phy", FSL_IMX7_PCIE_PHY_ADDR,
                                  FSL_IMX7_PCIE_PHY_SIZE);
 +
  }
- static abi_ulong get_sigframe(struct target_sigaction *ka,
+ static Property fsl_imx7_properties[] = {
 --
-.25.1
+.34.1

-[PULL 20/45] target/arm: Implement SME LD1, ST1
+[PULL 15/24] Add i.MX7 missing TZ devices and memory regions
-From: Richard Henderson <richard.henderson@linaro.org>
+From: Jean-Christophe Dubois <jcd@tribudubois.net>
-We cannot reuse the SVE functions for LD[1-4] and ST[1-4],
+* Add TZASC as unimplemented device.
-because those functions accept only a Zreg register number.
+  - Allow bare metal application to access this (unimplemented) device
-For SME, we want to pass a pointer into ZA storage.
+* Add CSU as unimplemented device.
   - Allow bare metal application to access this (unimplemented) device
 * Add various memory segments
   - OCRAM
   - OCRAM EPDC
   - OCRAM PXP
   - OCRAM S
   - ROM
   - CAAM
-Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
+Signed-off-by: Jean-Christophe Dubois <jcd@tribudubois.net>
-Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
+Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
-Message-id: 20220708151540.18136-21-richard.henderson@linaro.org
+Message-id: f887a3483996ba06d40bd62ffdfb0ecf68621987.1692964892.git.jcd@tribudubois.net
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 ---
- target/arm/helper-sme.h    |  82 +++++
+ include/hw/arm/fsl-imx7.h |  7 +++++
- target/arm/sme.decode      |   9 +
+ hw/arm/fsl-imx7.c         | 63 +++++++++++++++++++++++++++++++++++++++
- target/arm/sme_helper.c    | 595 +++++++++++++++++++++++++++++++++++++
+files changed, 70 insertions(+)
  target/arm/translate-sme.c |  70 +++++
 files changed, 756 insertions(+)
-diff --git a/target/arm/helper-sme.h b/target/arm/helper-sme.h
+diff --git a/include/hw/arm/fsl-imx7.h b/include/hw/arm/fsl-imx7.h
 index XXXXXXX..XXXXXXX 100644
---- a/target/arm/helper-sme.h
+--- a/include/hw/arm/fsl-imx7.h
-+++ b/target/arm/helper-sme.h
++++ b/include/hw/arm/fsl-imx7.h
-@@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_4(sme_mova_cz_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
+@@ -XXX,XX +XXX,XX @@ struct FslIMX7State {
- DEF_HELPER_FLAGS_4(sme_mova_zc_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
+     IMX7GPRState       gpr;
- DEF_HELPER_FLAGS_4(sme_mova_cz_q, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
+     ChipideaState      usb[FSL_IMX7_NUM_USBS];
- DEF_HELPER_FLAGS_4(sme_mova_zc_q, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
+     DesignwarePCIEHost pcie;
 +    MemoryRegion       rom;
 +    MemoryRegion       caam;
 +    MemoryRegion       ocram;
 +    MemoryRegion       ocram_epdc;
 +    MemoryRegion       ocram_pxp;
 +    MemoryRegion       ocram_s;
 +
-+DEF_HELPER_FLAGS_5(sme_ld1b_h, TCG_CALL_NO_WG, void, env, ptr, ptr, tl, i32)
+     uint32_t           phy_num[FSL_IMX7_NUM_ETHS];
-+DEF_HELPER_FLAGS_5(sme_ld1b_v, TCG_CALL_NO_WG, void, env, ptr, ptr, tl, i32)
+     bool               phy_connected[FSL_IMX7_NUM_ETHS];
-+DEF_HELPER_FLAGS_5(sme_ld1b_h_mte, TCG_CALL_NO_WG, void, env, ptr, ptr, tl, i32)
+ };
-+DEF_HELPER_FLAGS_5(sme_ld1b_v_mte, TCG_CALL_NO_WG, void, env, ptr, ptr, tl, i32)
+diff --git a/hw/arm/fsl-imx7.c b/hw/arm/fsl-imx7.c
 +
 +DEF_HELPER_FLAGS_5(sme_ld1h_be_h, TCG_CALL_NO_WG, void, env, ptr, ptr, tl, i32)
 +DEF_HELPER_FLAGS_5(sme_ld1h_le_h, TCG_CALL_NO_WG, void, env, ptr, ptr, tl, i32)
 +DEF_HELPER_FLAGS_5(sme_ld1h_be_v, TCG_CALL_NO_WG, void, env, ptr, ptr, tl, i32)
 +DEF_HELPER_FLAGS_5(sme_ld1h_le_v, TCG_CALL_NO_WG, void, env, ptr, ptr, tl, i32)
 +DEF_HELPER_FLAGS_5(sme_ld1h_be_h_mte, TCG_CALL_NO_WG, void, env, ptr, ptr, tl, i32)
 +DEF_HELPER_FLAGS_5(sme_ld1h_le_h_mte, TCG_CALL_NO_WG, void, env, ptr, ptr, tl, i32)
 +DEF_HELPER_FLAGS_5(sme_ld1h_be_v_mte, TCG_CALL_NO_WG, void, env, ptr, ptr, tl, i32)
 +DEF_HELPER_FLAGS_5(sme_ld1h_le_v_mte, TCG_CALL_NO_WG, void, env, ptr, ptr, tl, i32)
 +
 +DEF_HELPER_FLAGS_5(sme_ld1s_be_h, TCG_CALL_NO_WG, void, env, ptr, ptr, tl, i32)
 +DEF_HELPER_FLAGS_5(sme_ld1s_le_h, TCG_CALL_NO_WG, void, env, ptr, ptr, tl, i32)
 +DEF_HELPER_FLAGS_5(sme_ld1s_be_v, TCG_CALL_NO_WG, void, env, ptr, ptr, tl, i32)
 +DEF_HELPER_FLAGS_5(sme_ld1s_le_v, TCG_CALL_NO_WG, void, env, ptr, ptr, tl, i32)
 +DEF_HELPER_FLAGS_5(sme_ld1s_be_h_mte, TCG_CALL_NO_WG, void, env, ptr, ptr, tl, i32)
 +DEF_HELPER_FLAGS_5(sme_ld1s_le_h_mte, TCG_CALL_NO_WG, void, env, ptr, ptr, tl, i32)
 +DEF_HELPER_FLAGS_5(sme_ld1s_be_v_mte, TCG_CALL_NO_WG, void, env, ptr, ptr, tl, i32)
 +DEF_HELPER_FLAGS_5(sme_ld1s_le_v_mte, TCG_CALL_NO_WG, void, env, ptr, ptr, tl, i32)
 +
 +DEF_HELPER_FLAGS_5(sme_ld1d_be_h, TCG_CALL_NO_WG, void, env, ptr, ptr, tl, i32)
 +DEF_HELPER_FLAGS_5(sme_ld1d_le_h, TCG_CALL_NO_WG, void, env, ptr, ptr, tl, i32)
 +DEF_HELPER_FLAGS_5(sme_ld1d_be_v, TCG_CALL_NO_WG, void, env, ptr, ptr, tl, i32)
 +DEF_HELPER_FLAGS_5(sme_ld1d_le_v, TCG_CALL_NO_WG, void, env, ptr, ptr, tl, i32)
 +DEF_HELPER_FLAGS_5(sme_ld1d_be_h_mte, TCG_CALL_NO_WG, void, env, ptr, ptr, tl, i32)
 +DEF_HELPER_FLAGS_5(sme_ld1d_le_h_mte, TCG_CALL_NO_WG, void, env, ptr, ptr, tl, i32)
 +DEF_HELPER_FLAGS_5(sme_ld1d_be_v_mte, TCG_CALL_NO_WG, void, env, ptr, ptr, tl, i32)
 +DEF_HELPER_FLAGS_5(sme_ld1d_le_v_mte, TCG_CALL_NO_WG, void, env, ptr, ptr, tl, i32)
 +
 +DEF_HELPER_FLAGS_5(sme_ld1q_be_h, TCG_CALL_NO_WG, void, env, ptr, ptr, tl, i32)
 +DEF_HELPER_FLAGS_5(sme_ld1q_le_h, TCG_CALL_NO_WG, void, env, ptr, ptr, tl, i32)
 +DEF_HELPER_FLAGS_5(sme_ld1q_be_v, TCG_CALL_NO_WG, void, env, ptr, ptr, tl, i32)
 +DEF_HELPER_FLAGS_5(sme_ld1q_le_v, TCG_CALL_NO_WG, void, env, ptr, ptr, tl, i32)
 +DEF_HELPER_FLAGS_5(sme_ld1q_be_h_mte, TCG_CALL_NO_WG, void, env, ptr, ptr, tl, i32)
 +DEF_HELPER_FLAGS_5(sme_ld1q_le_h_mte, TCG_CALL_NO_WG, void, env, ptr, ptr, tl, i32)
 +DEF_HELPER_FLAGS_5(sme_ld1q_be_v_mte, TCG_CALL_NO_WG, void, env, ptr, ptr, tl, i32)
 +DEF_HELPER_FLAGS_5(sme_ld1q_le_v_mte, TCG_CALL_NO_WG, void, env, ptr, ptr, tl, i32)
 +
 +DEF_HELPER_FLAGS_5(sme_st1b_h, TCG_CALL_NO_WG, void, env, ptr, ptr, tl, i32)
 +DEF_HELPER_FLAGS_5(sme_st1b_v, TCG_CALL_NO_WG, void, env, ptr, ptr, tl, i32)
 +DEF_HELPER_FLAGS_5(sme_st1b_h_mte, TCG_CALL_NO_WG, void, env, ptr, ptr, tl, i32)
 +DEF_HELPER_FLAGS_5(sme_st1b_v_mte, TCG_CALL_NO_WG, void, env, ptr, ptr, tl, i32)
 +
 +DEF_HELPER_FLAGS_5(sme_st1h_be_h, TCG_CALL_NO_WG, void, env, ptr, ptr, tl, i32)
 +DEF_HELPER_FLAGS_5(sme_st1h_le_h, TCG_CALL_NO_WG, void, env, ptr, ptr, tl, i32)
 +DEF_HELPER_FLAGS_5(sme_st1h_be_v, TCG_CALL_NO_WG, void, env, ptr, ptr, tl, i32)
 +DEF_HELPER_FLAGS_5(sme_st1h_le_v, TCG_CALL_NO_WG, void, env, ptr, ptr, tl, i32)
 +DEF_HELPER_FLAGS_5(sme_st1h_be_h_mte, TCG_CALL_NO_WG, void, env, ptr, ptr, tl, i32)
 +DEF_HELPER_FLAGS_5(sme_st1h_le_h_mte, TCG_CALL_NO_WG, void, env, ptr, ptr, tl, i32)
 +DEF_HELPER_FLAGS_5(sme_st1h_be_v_mte, TCG_CALL_NO_WG, void, env, ptr, ptr, tl, i32)
 +DEF_HELPER_FLAGS_5(sme_st1h_le_v_mte, TCG_CALL_NO_WG, void, env, ptr, ptr, tl, i32)
 +
 +DEF_HELPER_FLAGS_5(sme_st1s_be_h, TCG_CALL_NO_WG, void, env, ptr, ptr, tl, i32)
 +DEF_HELPER_FLAGS_5(sme_st1s_le_h, TCG_CALL_NO_WG, void, env, ptr, ptr, tl, i32)
 +DEF_HELPER_FLAGS_5(sme_st1s_be_v, TCG_CALL_NO_WG, void, env, ptr, ptr, tl, i32)
 +DEF_HELPER_FLAGS_5(sme_st1s_le_v, TCG_CALL_NO_WG, void, env, ptr, ptr, tl, i32)
 +DEF_HELPER_FLAGS_5(sme_st1s_be_h_mte, TCG_CALL_NO_WG, void, env, ptr, ptr, tl, i32)
 +DEF_HELPER_FLAGS_5(sme_st1s_le_h_mte, TCG_CALL_NO_WG, void, env, ptr, ptr, tl, i32)
 +DEF_HELPER_FLAGS_5(sme_st1s_be_v_mte, TCG_CALL_NO_WG, void, env, ptr, ptr, tl, i32)
 +DEF_HELPER_FLAGS_5(sme_st1s_le_v_mte, TCG_CALL_NO_WG, void, env, ptr, ptr, tl, i32)
 +
 +DEF_HELPER_FLAGS_5(sme_st1d_be_h, TCG_CALL_NO_WG, void, env, ptr, ptr, tl, i32)
 +DEF_HELPER_FLAGS_5(sme_st1d_le_h, TCG_CALL_NO_WG, void, env, ptr, ptr, tl, i32)
 +DEF_HELPER_FLAGS_5(sme_st1d_be_v, TCG_CALL_NO_WG, void, env, ptr, ptr, tl, i32)
 +DEF_HELPER_FLAGS_5(sme_st1d_le_v, TCG_CALL_NO_WG, void, env, ptr, ptr, tl, i32)
 +DEF_HELPER_FLAGS_5(sme_st1d_be_h_mte, TCG_CALL_NO_WG, void, env, ptr, ptr, tl, i32)
 +DEF_HELPER_FLAGS_5(sme_st1d_le_h_mte, TCG_CALL_NO_WG, void, env, ptr, ptr, tl, i32)
 +DEF_HELPER_FLAGS_5(sme_st1d_be_v_mte, TCG_CALL_NO_WG, void, env, ptr, ptr, tl, i32)
 +DEF_HELPER_FLAGS_5(sme_st1d_le_v_mte, TCG_CALL_NO_WG, void, env, ptr, ptr, tl, i32)
 +
 +DEF_HELPER_FLAGS_5(sme_st1q_be_h, TCG_CALL_NO_WG, void, env, ptr, ptr, tl, i32)
 +DEF_HELPER_FLAGS_5(sme_st1q_le_h, TCG_CALL_NO_WG, void, env, ptr, ptr, tl, i32)
 +DEF_HELPER_FLAGS_5(sme_st1q_be_v, TCG_CALL_NO_WG, void, env, ptr, ptr, tl, i32)
 +DEF_HELPER_FLAGS_5(sme_st1q_le_v, TCG_CALL_NO_WG, void, env, ptr, ptr, tl, i32)
 +DEF_HELPER_FLAGS_5(sme_st1q_be_h_mte, TCG_CALL_NO_WG, void, env, ptr, ptr, tl, i32)
 +DEF_HELPER_FLAGS_5(sme_st1q_le_h_mte, TCG_CALL_NO_WG, void, env, ptr, ptr, tl, i32)
 +DEF_HELPER_FLAGS_5(sme_st1q_be_v_mte, TCG_CALL_NO_WG, void, env, ptr, ptr, tl, i32)
 +DEF_HELPER_FLAGS_5(sme_st1q_le_v_mte, TCG_CALL_NO_WG, void, env, ptr, ptr, tl, i32)
 diff --git a/target/arm/sme.decode b/target/arm/sme.decode
 index XXXXXXX..XXXXXXX 100644
---- a/target/arm/sme.decode
+--- a/hw/arm/fsl-imx7.c
-+++ b/target/arm/sme.decode
++++ b/hw/arm/fsl-imx7.c
-@@ -XXX,XX +XXX,XX @@ MOVA            11000000 esz:2 00001 0 v:1 .. pg:3 0 za_imm:4 zr:5  \
+@@ -XXX,XX +XXX,XX @@ static void fsl_imx7_realize(DeviceState *dev, Error **errp)
-                 &mova to_vec=1 rs=%mova_rs
+     create_unimplemented_device("pcie-phy", FSL_IMX7_PCIE_PHY_ADDR,
- MOVA            11000000 11    00001 1 v:1 .. pg:3 0 za_imm:4 zr:5  \
+                                 FSL_IMX7_PCIE_PHY_SIZE);
-                 &mova to_vec=1 rs=%mova_rs esz=4
-+
++    /*
-+### SME Memory
++     * CSU
-+
++     */
-+&ldst           esz rs pg rn rm za_imm v:bool st:bool
++    create_unimplemented_device("csu", FSL_IMX7_CSU_ADDR,
-+
++                                FSL_IMX7_CSU_SIZE);
 +LDST1           1110000 0 esz:2 st:1 rm:5 v:1 .. pg:3 rn:5 0 za_imm:4  \
 +                &ldst rs=%mova_rs
 +LDST1           1110000 111     st:1 rm:5 v:1 .. pg:3 rn:5 0 za_imm:4  \
 +                &ldst esz=4 rs=%mova_rs
 diff --git a/target/arm/sme_helper.c b/target/arm/sme_helper.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/sme_helper.c
 +++ b/target/arm/sme_helper.c
@@ -XXX,XX +XXX,XX @@
  #include "qemu/osdep.h"
  #include "cpu.h"
 +#include "internals.h"
  #include "tcg/tcg-gvec-desc.h"
  #include "exec/helper-proto.h"
 +#include "exec/cpu_ldst.h"
 +#include "exec/exec-all.h"
  #include "qemu/int128.h"
  #include "vec_internal.h"
 +#include "sve_ldst_internal.h"
  /* ResetSVEState */
  void arm_reset_sve_state(CPUARMState *env)
@@ -XXX,XX +XXX,XX @@ void HELPER(sme_mova_zc_q)(void *vd, void *za, void *vg, uint32_t desc)
  }
  #undef DO_MOVA_Z
 +
 +/*
 + * Clear elements in a tile slice comprising len bytes.
 + */
 +
 +typedef void ClearFn(void *ptr, size_t off, size_t len);
 +
 +static void clear_horizontal(void *ptr, size_t off, size_t len)
 +{
 +    memset(ptr + off, 0, len);
 +}
 +
 +static void clear_vertical_b(void *vptr, size_t off, size_t len)
 +{
 +    for (size_t i = 0; i < len; ++i) {
 +        *(uint8_t *)(vptr + tile_vslice_offset(i + off)) = 0;
 +    }
 +}
 +
 +static void clear_vertical_h(void *vptr, size_t off, size_t len)
 +{
 +    for (size_t i = 0; i < len; i += 2) {
 +        *(uint16_t *)(vptr + tile_vslice_offset(i + off)) = 0;
 +    }
 +}
 +
 +static void clear_vertical_s(void *vptr, size_t off, size_t len)
 +{
 +    for (size_t i = 0; i < len; i += 4) {
 +        *(uint32_t *)(vptr + tile_vslice_offset(i + off)) = 0;
 +    }
 +}
 +
 +static void clear_vertical_d(void *vptr, size_t off, size_t len)
 +{
 +    for (size_t i = 0; i < len; i += 8) {
 +        *(uint64_t *)(vptr + tile_vslice_offset(i + off)) = 0;
 +    }
 +}
 +
 +static void clear_vertical_q(void *vptr, size_t off, size_t len)
 +{
 +    for (size_t i = 0; i < len; i += 16) {
 +        memset(vptr + tile_vslice_offset(i + off), 0, 16);
 +    }
 +}
 +
 +/*
 + * Copy elements from an array into a tile slice comprising len bytes.
 + */
 +
 +typedef void CopyFn(void *dst, const void *src, size_t len);
 +
 +static void copy_horizontal(void *dst, const void *src, size_t len)
 +{
 +    memcpy(dst, src, len);
 +}
 +
 +static void copy_vertical_b(void *vdst, const void *vsrc, size_t len)
 +{
 +    const uint8_t *src = vsrc;
 +    uint8_t *dst = vdst;
 +    size_t i;
 +
 +    for (i = 0; i < len; ++i) {
 +        dst[tile_vslice_index(i)] = src[i];
 +    }
 +}
 +
 +static void copy_vertical_h(void *vdst, const void *vsrc, size_t len)
 +{
 +    const uint16_t *src = vsrc;
 +    uint16_t *dst = vdst;
 +    size_t i;
 +
 +    for (i = 0; i < len / 2; ++i) {
 +        dst[tile_vslice_index(i)] = src[i];
 +    }
 +}
 +
 +static void copy_vertical_s(void *vdst, const void *vsrc, size_t len)
 +{
 +    const uint32_t *src = vsrc;
 +    uint32_t *dst = vdst;
 +    size_t i;
 +
 +    for (i = 0; i < len / 4; ++i) {
 +        dst[tile_vslice_index(i)] = src[i];
 +    }
 +}
 +
 +static void copy_vertical_d(void *vdst, const void *vsrc, size_t len)
 +{
 +    const uint64_t *src = vsrc;
 +    uint64_t *dst = vdst;
 +    size_t i;
 +
 +    for (i = 0; i < len / 8; ++i) {
 +        dst[tile_vslice_index(i)] = src[i];
 +    }
 +}
 +
 +static void copy_vertical_q(void *vdst, const void *vsrc, size_t len)
 +{
 +    for (size_t i = 0; i < len; i += 16) {
 +        memcpy(vdst + tile_vslice_offset(i), vsrc + i, 16);
 +    }
 +}
 +
 +/*
 + * Host and TLB primitives for vertical tile slice addressing.
 + */
 +
 +#define DO_LD(NAME, TYPE, HOST, TLB)                                        \
 +static inline void sme_##NAME##_v_host(void *za, intptr_t off, void *host)  \
 +{                                                                           \
 +    TYPE val = HOST(host);                                                  \
 +    *(TYPE *)(za + tile_vslice_offset(off)) = val;                          \
 +}                                                                           \
 +static inline void sme_##NAME##_v_tlb(CPUARMState *env, void *za,           \
 +                        intptr_t off, target_ulong addr, uintptr_t ra)      \
 +{                                                                           \
 +    TYPE val = TLB(env, useronly_clean_ptr(addr), ra);                      \
 +    *(TYPE *)(za + tile_vslice_offset(off)) = val;                          \
 +}
 +
 +#define DO_ST(NAME, TYPE, HOST, TLB)                                        \
 +static inline void sme_##NAME##_v_host(void *za, intptr_t off, void *host)  \
 +{                                                                           \
 +    TYPE val = *(TYPE *)(za + tile_vslice_offset(off));                     \
 +    HOST(host, val);                                                        \
 +}                                                                           \
 +static inline void sme_##NAME##_v_tlb(CPUARMState *env, void *za,           \
 +                        intptr_t off, target_ulong addr, uintptr_t ra)      \
 +{                                                                           \
 +    TYPE val = *(TYPE *)(za + tile_vslice_offset(off));                     \
 +    TLB(env, useronly_clean_ptr(addr), val, ra);                            \
 +}
 +
 +/*
 + * The ARMVectorReg elements are stored in host-endian 64-bit units.
 + * For 128-bit quantities, the sequence defined by the Elem[] pseudocode
 + * corresponds to storing the two 64-bit pieces in little-endian order.
 + */
 +#define DO_LDQ(HNAME, VNAME, BE, HOST, TLB)                                 \
 +static inline void HNAME##_host(void *za, intptr_t off, void *host)         \
 +{                                                                           \
 +    uint64_t val0 = HOST(host), val1 = HOST(host + 8);                      \
 +    uint64_t *ptr = za + off;                                               \
 +    ptr[0] = BE ? val1 : val0, ptr[1] = BE ? val0 : val1;                   \
 +}                                                                           \
 +static inline void VNAME##_v_host(void *za, intptr_t off, void *host)       \
 +{                                                                           \
 +    HNAME##_host(za, tile_vslice_offset(off), host);                        \
 +}                                                                           \
 +static inline void HNAME##_tlb(CPUARMState *env, void *za, intptr_t off,    \
 +                               target_ulong addr, uintptr_t ra)             \
 +{                                                                           \
 +    uint64_t val0 = TLB(env, useronly_clean_ptr(addr), ra);                 \
 +    uint64_t val1 = TLB(env, useronly_clean_ptr(addr + 8), ra);             \
 +    uint64_t *ptr = za + off;                                               \
 +    ptr[0] = BE ? val1 : val0, ptr[1] = BE ? val0 : val1;                   \
 +}                                                                           \
 +static inline void VNAME##_v_tlb(CPUARMState *env, void *za, intptr_t off,  \
 +                               target_ulong addr, uintptr_t ra)             \
 +{                                                                           \
 +    HNAME##_tlb(env, za, tile_vslice_offset(off), addr, ra);                \
 +}
 +
 +#define DO_STQ(HNAME, VNAME, BE, HOST, TLB)                                 \
 +static inline void HNAME##_host(void *za, intptr_t off, void *host)         \
 +{                                                                           \
 +    uint64_t *ptr = za + off;                                               \
 +    HOST(host, ptr[BE]);                                                    \
 +    HOST(host + 1, ptr[!BE]);                                               \
 +}                                                                           \
 +static inline void VNAME##_v_host(void *za, intptr_t off, void *host)       \
 +{                                                                           \
 +    HNAME##_host(za, tile_vslice_offset(off), host);                        \
 +}                                                                           \
 +static inline void HNAME##_tlb(CPUARMState *env, void *za, intptr_t off,    \
 +                               target_ulong addr, uintptr_t ra)             \
 +{                                                                           \
 +    uint64_t *ptr = za + off;                                               \
 +    TLB(env, useronly_clean_ptr(addr), ptr[BE], ra);                        \
 +    TLB(env, useronly_clean_ptr(addr + 8), ptr[!BE], ra);                   \
 +}                                                                           \
 +static inline void VNAME##_v_tlb(CPUARMState *env, void *za, intptr_t off,  \
 +                               target_ulong addr, uintptr_t ra)             \
 +{                                                                           \
 +    HNAME##_tlb(env, za, tile_vslice_offset(off), addr, ra);                \
 +}
 +
 +DO_LD(ld1b, uint8_t, ldub_p, cpu_ldub_data_ra)
 +DO_LD(ld1h_be, uint16_t, lduw_be_p, cpu_lduw_be_data_ra)
 +DO_LD(ld1h_le, uint16_t, lduw_le_p, cpu_lduw_le_data_ra)
 +DO_LD(ld1s_be, uint32_t, ldl_be_p, cpu_ldl_be_data_ra)
 +DO_LD(ld1s_le, uint32_t, ldl_le_p, cpu_ldl_le_data_ra)
 +DO_LD(ld1d_be, uint64_t, ldq_be_p, cpu_ldq_be_data_ra)
 +DO_LD(ld1d_le, uint64_t, ldq_le_p, cpu_ldq_le_data_ra)
 +
 +DO_LDQ(sve_ld1qq_be, sme_ld1q_be, 1, ldq_be_p, cpu_ldq_be_data_ra)
 +DO_LDQ(sve_ld1qq_le, sme_ld1q_le, 0, ldq_le_p, cpu_ldq_le_data_ra)
 +
 +DO_ST(st1b, uint8_t, stb_p, cpu_stb_data_ra)
 +DO_ST(st1h_be, uint16_t, stw_be_p, cpu_stw_be_data_ra)
 +DO_ST(st1h_le, uint16_t, stw_le_p, cpu_stw_le_data_ra)
 +DO_ST(st1s_be, uint32_t, stl_be_p, cpu_stl_be_data_ra)
 +DO_ST(st1s_le, uint32_t, stl_le_p, cpu_stl_le_data_ra)
 +DO_ST(st1d_be, uint64_t, stq_be_p, cpu_stq_be_data_ra)
 +DO_ST(st1d_le, uint64_t, stq_le_p, cpu_stq_le_data_ra)
 +
 +DO_STQ(sve_st1qq_be, sme_st1q_be, 1, stq_be_p, cpu_stq_be_data_ra)
 +DO_STQ(sve_st1qq_le, sme_st1q_le, 0, stq_le_p, cpu_stq_le_data_ra)
 +
 +#undef DO_LD
 +#undef DO_ST
 +#undef DO_LDQ
 +#undef DO_STQ
 +
 +/*
 + * Common helper for all contiguous predicated loads.
 + */
 +
 +static inline QEMU_ALWAYS_INLINE
 +void sme_ld1(CPUARMState *env, void *za, uint64_t *vg,
 +             const target_ulong addr, uint32_t desc, const uintptr_t ra,
 +             const int esz, uint32_t mtedesc, bool vertical,
 +             sve_ldst1_host_fn *host_fn,
 +             sve_ldst1_tlb_fn *tlb_fn,
 +             ClearFn *clr_fn,
 +             CopyFn *cpy_fn)
 +{
 +    const intptr_t reg_max = simd_oprsz(desc);
 +    const intptr_t esize = 1 << esz;
 +    intptr_t reg_off, reg_last;
 +    SVEContLdSt info;
 +    void *host;
 +    int flags;
 +
 +    /* Find the active elements.  */
 +    if (!sve_cont_ldst_elements(&info, addr, vg, reg_max, esz, esize)) {
 +        /* The entire predicate was false; no load occurs.  */
 +        clr_fn(za, 0, reg_max);
 +        return;
 +    }
 +
 +    /* Probe the page(s).  Exit with exception for any invalid page. */
 +    sve_cont_ldst_pages(&info, FAULT_ALL, env, addr, MMU_DATA_LOAD, ra);
 +
 +    /* Handle watchpoints for all active elements. */
 +    sve_cont_ldst_watchpoints(&info, env, vg, addr, esize, esize,
 +                              BP_MEM_READ, ra);
 +
 +    /*
-+     * Handle mte checks for all active elements.
++     * TZASC
 +     * Since TBI must be set for MTE, !mtedesc => !mte_active.
 +     */
-+    if (mtedesc) {
++    create_unimplemented_device("tzasc", FSL_IMX7_TZASC_ADDR,
-+        sve_cont_ldst_mte_check(&info, env, vg, addr, esize, esize,
++                                FSL_IMX7_TZASC_SIZE);
 +                                mtedesc, ra);
 +    }
 +
 +    flags = info.page[0].flags | info.page[1].flags;
 +    if (unlikely(flags != 0)) {
 +#ifdef CONFIG_USER_ONLY
 +        g_assert_not_reached();
 +#else
 +        /*
 +         * At least one page includes MMIO.
 +         * Any bus operation can fail with cpu_transaction_failed,
 +         * which for ARM will raise SyncExternal.  Perform the load
 +         * into scratch memory to preserve register state until the end.
 +         */
 +        ARMVectorReg scratch = { };
 +
 +        reg_off = info.reg_off_first[0];
 +        reg_last = info.reg_off_last[1];
 +        if (reg_last < 0) {
 +            reg_last = info.reg_off_split;
 +            if (reg_last < 0) {
 +                reg_last = info.reg_off_last[0];
 +            }
 +        }
 +
 +        do {
 +            uint64_t pg = vg[reg_off >> 6];
 +            do {
 +                if ((pg >> (reg_off & 63)) & 1) {
 +                    tlb_fn(env, &scratch, reg_off, addr + reg_off, ra);
 +                }
 +                reg_off += esize;
 +            } while (reg_off & 63);
 +        } while (reg_off <= reg_last);
 +
 +        cpy_fn(za, &scratch, reg_max);
 +        return;
 +#endif
 +    }
 +
 +    /* The entire operation is in RAM, on valid pages. */
 +
 +    reg_off = info.reg_off_first[0];
 +    reg_last = info.reg_off_last[0];
 +    host = info.page[0].host;
 +
 +    if (!vertical) {
 +        memset(za, 0, reg_max);
 +    } else if (reg_off) {
 +        clr_fn(za, 0, reg_off);
 +    }
 +
 +    while (reg_off <= reg_last) {
 +        uint64_t pg = vg[reg_off >> 6];
 +        do {
 +            if ((pg >> (reg_off & 63)) & 1) {
 +                host_fn(za, reg_off, host + reg_off);
 +            } else if (vertical) {
 +                clr_fn(za, reg_off, esize);
 +            }
 +            reg_off += esize;
 +        } while (reg_off <= reg_last && (reg_off & 63));
 +    }
 +
 +    /*
-+     * Use the slow path to manage the cross-page misalignment.
++     * OCRAM memory
 +     * But we know this is RAM and cannot trap.
 +     */
-+    reg_off = info.reg_off_split;
++    memory_region_init_ram(&s->ocram, NULL, "imx7.ocram",
-+    if (unlikely(reg_off >= 0)) {
++                           FSL_IMX7_OCRAM_MEM_SIZE,
-+        tlb_fn(env, za, reg_off, addr + reg_off, ra);
++                           &error_abort);
-+    }
++    memory_region_add_subregion(get_system_memory(), FSL_IMX7_OCRAM_MEM_ADDR,
-+
++                                &s->ocram);
 +    reg_off = info.reg_off_first[1];
 +    if (unlikely(reg_off >= 0)) {
 +        reg_last = info.reg_off_last[1];
 +        host = info.page[1].host;
 +
 +        do {
 +            uint64_t pg = vg[reg_off >> 6];
 +            do {
 +                if ((pg >> (reg_off & 63)) & 1) {
 +                    host_fn(za, reg_off, host + reg_off);
 +                } else if (vertical) {
 +                    clr_fn(za, reg_off, esize);
 +                }
 +                reg_off += esize;
 +            } while (reg_off & 63);
 +        } while (reg_off <= reg_last);
 +    }
 +}
 +
 +static inline QEMU_ALWAYS_INLINE
 +void sme_ld1_mte(CPUARMState *env, void *za, uint64_t *vg,
 +                 target_ulong addr, uint32_t desc, uintptr_t ra,
 +                 const int esz, bool vertical,
 +                 sve_ldst1_host_fn *host_fn,
 +                 sve_ldst1_tlb_fn *tlb_fn,
 +                 ClearFn *clr_fn,
 +                 CopyFn *cpy_fn)
 +{
 +    uint32_t mtedesc = desc >> (SIMD_DATA_SHIFT + SVE_MTEDESC_SHIFT);
 +    int bit55 = extract64(addr, 55, 1);
 +
 +    /* Remove mtedesc from the normal sve descriptor. */
 +    desc = extract32(desc, 0, SIMD_DATA_SHIFT + SVE_MTEDESC_SHIFT);
 +
 +    /* Perform gross MTE suppression early. */
 +    if (!tbi_check(desc, bit55) ||
 +        tcma_check(desc, bit55, allocation_tag_from_addr(addr))) {
 +        mtedesc = 0;
 +    }
 +
 +    sme_ld1(env, za, vg, addr, desc, ra, esz, mtedesc, vertical,
 +            host_fn, tlb_fn, clr_fn, cpy_fn);
 +}
 +
 +#define DO_LD(L, END, ESZ)                                                 \
 +void HELPER(sme_ld1##L##END##_h)(CPUARMState *env, void *za, void *vg,     \
 +                                 target_ulong addr, uint32_t desc)         \
 +{                                                                          \
 +    sme_ld1(env, za, vg, addr, desc, GETPC(), ESZ, 0, false,               \
 +            sve_ld1##L##L##END##_host, sve_ld1##L##L##END##_tlb,           \
 +            clear_horizontal, copy_horizontal);                            \
 +}                                                                          \
 +void HELPER(sme_ld1##L##END##_v)(CPUARMState *env, void *za, void *vg,     \
 +                                 target_ulong addr, uint32_t desc)         \
 +{                                                                          \
 +    sme_ld1(env, za, vg, addr, desc, GETPC(), ESZ, 0, true,                \
 +            sme_ld1##L##END##_v_host, sme_ld1##L##END##_v_tlb,             \
 +            clear_vertical_##L, copy_vertical_##L);                        \
 +}                                                                          \
 +void HELPER(sme_ld1##L##END##_h_mte)(CPUARMState *env, void *za, void *vg, \
 +                                     target_ulong addr, uint32_t desc)     \
 +{                                                                          \
 +    sme_ld1_mte(env, za, vg, addr, desc, GETPC(), ESZ, false,              \
 +                sve_ld1##L##L##END##_host, sve_ld1##L##L##END##_tlb,       \
 +                clear_horizontal, copy_horizontal);                        \
 +}                                                                          \
 +void HELPER(sme_ld1##L##END##_v_mte)(CPUARMState *env, void *za, void *vg, \
 +                                     target_ulong addr, uint32_t desc)     \
 +{                                                                          \
 +    sme_ld1_mte(env, za, vg, addr, desc, GETPC(), ESZ, true,               \
 +                sme_ld1##L##END##_v_host, sme_ld1##L##END##_v_tlb,         \
 +                clear_vertical_##L, copy_vertical_##L);                    \
 +}
 +
 +DO_LD(b, , MO_8)
 +DO_LD(h, _be, MO_16)
 +DO_LD(h, _le, MO_16)
 +DO_LD(s, _be, MO_32)
 +DO_LD(s, _le, MO_32)
 +DO_LD(d, _be, MO_64)
 +DO_LD(d, _le, MO_64)
 +DO_LD(q, _be, MO_128)
 +DO_LD(q, _le, MO_128)
 +
 +#undef DO_LD
 +
 +/*
 + * Common helper for all contiguous predicated stores.
 + */
 +
 +static inline QEMU_ALWAYS_INLINE
 +void sme_st1(CPUARMState *env, void *za, uint64_t *vg,
 +             const target_ulong addr, uint32_t desc, const uintptr_t ra,
 +             const int esz, uint32_t mtedesc, bool vertical,
 +             sve_ldst1_host_fn *host_fn,
 +             sve_ldst1_tlb_fn *tlb_fn)
 +{
 +    const intptr_t reg_max = simd_oprsz(desc);
 +    const intptr_t esize = 1 << esz;
 +    intptr_t reg_off, reg_last;
 +    SVEContLdSt info;
 +    void *host;
 +    int flags;
 +
 +    /* Find the active elements.  */
 +    if (!sve_cont_ldst_elements(&info, addr, vg, reg_max, esz, esize)) {
 +        /* The entire predicate was false; no store occurs.  */
 +        return;
 +    }
 +
 +    /* Probe the page(s).  Exit with exception for any invalid page. */
 +    sve_cont_ldst_pages(&info, FAULT_ALL, env, addr, MMU_DATA_STORE, ra);
 +
 +    /* Handle watchpoints for all active elements. */
 +    sve_cont_ldst_watchpoints(&info, env, vg, addr, esize, esize,
 +                              BP_MEM_WRITE, ra);
 +
 +    /*
-+     * Handle mte checks for all active elements.
++     * OCRAM EPDC memory
 +     * Since TBI must be set for MTE, !mtedesc => !mte_active.
 +     */
-+    if (mtedesc) {
++    memory_region_init_ram(&s->ocram_epdc, NULL, "imx7.ocram_epdc",
-+        sve_cont_ldst_mte_check(&info, env, vg, addr, esize, esize,
++                           FSL_IMX7_OCRAM_EPDC_SIZE,
-+                                mtedesc, ra);
++                           &error_abort);
-+    }
++    memory_region_add_subregion(get_system_memory(), FSL_IMX7_OCRAM_EPDC_ADDR,
-+
++                                &s->ocram_epdc);
 +    flags = info.page[0].flags | info.page[1].flags;
 +    if (unlikely(flags != 0)) {
 +#ifdef CONFIG_USER_ONLY
 +        g_assert_not_reached();
 +#else
 +        /*
 +         * At least one page includes MMIO.
 +         * Any bus operation can fail with cpu_transaction_failed,
 +         * which for ARM will raise SyncExternal.  We cannot avoid
 +         * this fault and will leave with the store incomplete.
 +         */
 +        reg_off = info.reg_off_first[0];
 +        reg_last = info.reg_off_last[1];
 +        if (reg_last < 0) {
 +            reg_last = info.reg_off_split;
 +            if (reg_last < 0) {
 +                reg_last = info.reg_off_last[0];
 +            }
 +        }
 +
 +        do {
 +            uint64_t pg = vg[reg_off >> 6];
 +            do {
 +                if ((pg >> (reg_off & 63)) & 1) {
 +                    tlb_fn(env, za, reg_off, addr + reg_off, ra);
 +                }
 +                reg_off += esize;
 +            } while (reg_off & 63);
 +        } while (reg_off <= reg_last);
 +        return;
 +#endif
 +    }
 +
 +    reg_off = info.reg_off_first[0];
 +    reg_last = info.reg_off_last[0];
 +    host = info.page[0].host;
 +
 +    while (reg_off <= reg_last) {
 +        uint64_t pg = vg[reg_off >> 6];
 +        do {
 +            if ((pg >> (reg_off & 63)) & 1) {
 +                host_fn(za, reg_off, host + reg_off);
 +            }
 +            reg_off += 1 << esz;
 +        } while (reg_off <= reg_last && (reg_off & 63));
 +    }
 +
 +    /*
-+     * Use the slow path to manage the cross-page misalignment.
++     * OCRAM PXP memory
 +     * But we know this is RAM and cannot trap.
 +     */
-+    reg_off = info.reg_off_split;
++    memory_region_init_ram(&s->ocram_pxp, NULL, "imx7.ocram_pxp",
-+    if (unlikely(reg_off >= 0)) {
++                           FSL_IMX7_OCRAM_PXP_SIZE,
-+        tlb_fn(env, za, reg_off, addr + reg_off, ra);
++                           &error_abort);
-+    }
++    memory_region_add_subregion(get_system_memory(), FSL_IMX7_OCRAM_PXP_ADDR,
-+
++                                &s->ocram_pxp);
 +    reg_off = info.reg_off_first[1];
 +    if (unlikely(reg_off >= 0)) {
 +        reg_last = info.reg_off_last[1];
 +        host = info.page[1].host;
 +
 +        do {
 +            uint64_t pg = vg[reg_off >> 6];
 +            do {
 +                if ((pg >> (reg_off & 63)) & 1) {
 +                    host_fn(za, reg_off, host + reg_off);
 +                }
 +                reg_off += 1 << esz;
 +            } while (reg_off & 63);
 +        } while (reg_off <= reg_last);
 +    }
 +}
 +
 +static inline QEMU_ALWAYS_INLINE
 +void sme_st1_mte(CPUARMState *env, void *za, uint64_t *vg, target_ulong addr,
 +                 uint32_t desc, uintptr_t ra, int esz, bool vertical,
 +                 sve_ldst1_host_fn *host_fn,
 +                 sve_ldst1_tlb_fn *tlb_fn)
 +{
 +    uint32_t mtedesc = desc >> (SIMD_DATA_SHIFT + SVE_MTEDESC_SHIFT);
 +    int bit55 = extract64(addr, 55, 1);
 +
 +    /* Remove mtedesc from the normal sve descriptor. */
 +    desc = extract32(desc, 0, SIMD_DATA_SHIFT + SVE_MTEDESC_SHIFT);
 +
 +    /* Perform gross MTE suppression early. */
 +    if (!tbi_check(desc, bit55) ||
 +        tcma_check(desc, bit55, allocation_tag_from_addr(addr))) {
 +        mtedesc = 0;
 +    }
 +
 +    sme_st1(env, za, vg, addr, desc, ra, esz, mtedesc,
 +            vertical, host_fn, tlb_fn);
 +}
 +
 +#define DO_ST(L, END, ESZ)                                                 \
 +void HELPER(sme_st1##L##END##_h)(CPUARMState *env, void *za, void *vg,     \
 +                                 target_ulong addr, uint32_t desc)         \
 +{                                                                          \
 +    sme_st1(env, za, vg, addr, desc, GETPC(), ESZ, 0, false,               \
 +            sve_st1##L##L##END##_host, sve_st1##L##L##END##_tlb);          \
 +}                                                                          \
 +void HELPER(sme_st1##L##END##_v)(CPUARMState *env, void *za, void *vg,     \
 +                                 target_ulong addr, uint32_t desc)         \
 +{                                                                          \
 +    sme_st1(env, za, vg, addr, desc, GETPC(), ESZ, 0, true,                \
 +            sme_st1##L##END##_v_host, sme_st1##L##END##_v_tlb);            \
 +}                                                                          \
 +void HELPER(sme_st1##L##END##_h_mte)(CPUARMState *env, void *za, void *vg, \
 +                                     target_ulong addr, uint32_t desc)     \
 +{                                                                          \
 +    sme_st1_mte(env, za, vg, addr, desc, GETPC(), ESZ, false,              \
 +                sve_st1##L##L##END##_host, sve_st1##L##L##END##_tlb);      \
 +}                                                                          \
 +void HELPER(sme_st1##L##END##_v_mte)(CPUARMState *env, void *za, void *vg, \
 +                                     target_ulong addr, uint32_t desc)     \
 +{                                                                          \
 +    sme_st1_mte(env, za, vg, addr, desc, GETPC(), ESZ, true,               \
 +                sme_st1##L##END##_v_host, sme_st1##L##END##_v_tlb);        \
 +}
 +
 +DO_ST(b, , MO_8)
 +DO_ST(h, _be, MO_16)
 +DO_ST(h, _le, MO_16)
 +DO_ST(s, _be, MO_32)
 +DO_ST(s, _le, MO_32)
 +DO_ST(d, _be, MO_64)
 +DO_ST(d, _le, MO_64)
 +DO_ST(q, _be, MO_128)
 +DO_ST(q, _le, MO_128)
 +
 +#undef DO_ST
 diff --git a/target/arm/translate-sme.c b/target/arm/translate-sme.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/translate-sme.c
 +++ b/target/arm/translate-sme.c
@@ -XXX,XX +XXX,XX @@ static bool trans_MOVA(DisasContext *s, arg_MOVA *a)
      return true;
  }
 +
 +static bool trans_LDST1(DisasContext *s, arg_LDST1 *a)
 +{
 +    typedef void GenLdSt1(TCGv_env, TCGv_ptr, TCGv_ptr, TCGv, TCGv_i32);
 +
 +    /*
-+     * Indexed by [esz][be][v][mte][st], which is (except for load/store)
++     * OCRAM_S memory
 +     * also the order in which the elements appear in the function names,
 +     * and so how we must concatenate the pieces.
 +     */
++    memory_region_init_ram(&s->ocram_s, NULL, "imx7.ocram_s",
++                           FSL_IMX7_OCRAM_S_SIZE,
++                           &error_abort);
++    memory_region_add_subregion(get_system_memory(), FSL_IMX7_OCRAM_S_ADDR,
++                                &s->ocram_s);
 +
-+#define FN_LS(F)     { gen_helper_sme_ld1##F, gen_helper_sme_st1##F }
++    /*
-+#define FN_MTE(F)    { FN_LS(F), FN_LS(F##_mte) }
++     * ROM memory
-+#define FN_HV(F)     { FN_MTE(F##_h), FN_MTE(F##_v) }
++     */
-+#define FN_END(L, B) { FN_HV(L), FN_HV(B) }
++    memory_region_init_rom(&s->rom, OBJECT(dev), "imx7.rom",
 +                           FSL_IMX7_ROM_SIZE, &error_abort);
 +    memory_region_add_subregion(get_system_memory(), FSL_IMX7_ROM_ADDR,
 +                                &s->rom);
 +
-+    static GenLdSt1 * const fns[5][2][2][2][2] = {
++    /*
-+        FN_END(b, b),
++     * CAAM memory
-+        FN_END(h_le, h_be),
++     */
-+        FN_END(s_le, s_be),
++    memory_region_init_rom(&s->caam, OBJECT(dev), "imx7.caam",
-+        FN_END(d_le, d_be),
++                           FSL_IMX7_CAAM_MEM_SIZE, &error_abort);
-+        FN_END(q_le, q_be),
++    memory_region_add_subregion(get_system_memory(), FSL_IMX7_CAAM_MEM_ADDR,
-+    };
++                                &s->caam);
-+
+ }
-+#undef FN_LS
-+#undef FN_MTE
+ static Property fsl_imx7_properties[] = {
 +#undef FN_HV
 +#undef FN_END
 +
 +    TCGv_ptr t_za, t_pg;
 +    TCGv_i64 addr;
 +    int svl, desc = 0;
 +    bool be = s->be_data == MO_BE;
 +    bool mte = s->mte_active[0];
 +
 +    if (!dc_isar_feature(aa64_sme, s)) {
 +        return false;
 +    }
 +    if (!sme_smza_enabled_check(s)) {
 +        return true;
 +    }
 +
 +    t_za = get_tile_rowcol(s, a->esz, a->rs, a->za_imm, a->v);
 +    t_pg = pred_full_reg_ptr(s, a->pg);
 +    addr = tcg_temp_new_i64();
 +
 +    tcg_gen_shli_i64(addr, cpu_reg(s, a->rm), a->esz);
 +    tcg_gen_add_i64(addr, addr, cpu_reg_sp(s, a->rn));
 +
 +    if (mte) {
 +        desc = FIELD_DP32(desc, MTEDESC, MIDX, get_mem_index(s));
 +        desc = FIELD_DP32(desc, MTEDESC, TBI, s->tbid);
 +        desc = FIELD_DP32(desc, MTEDESC, TCMA, s->tcma);
 +        desc = FIELD_DP32(desc, MTEDESC, WRITE, a->st);
 +        desc = FIELD_DP32(desc, MTEDESC, SIZEM1, (1 << a->esz) - 1);
 +        desc <<= SVE_MTEDESC_SHIFT;
 +    } else {
 +        addr = clean_data_tbi(s, addr);
 +    }
 +    svl = streaming_vec_reg_size(s);
 +    desc = simd_desc(svl, svl, desc);
 +
 +    fns[a->esz][be][a->v][mte][a->st](cpu_env, t_za, t_pg, addr,
 +                                      tcg_constant_i32(desc));
 +
 +    tcg_temp_free_ptr(t_za);
 +    tcg_temp_free_ptr(t_pg);
 +    tcg_temp_free_i64(addr);
 +    return true;
 +}
 --
-.25.1
+.34.1

-[PULL 02/45] target/arm: Add infrastructure for disas_sme
+[PULL 16/24] Add i.MX7 SRC device implementation
-From: Richard Henderson <richard.henderson@linaro.org>
+From: Jean-Christophe Dubois <jcd@tribudubois.net>
-This includes the build rules for the decoder, and the
+The SRC device is normally used to start the secondary CPU.
-new file for translation, but excludes any instructions.
+When running Linux directly, QEMU is emulating a PSCI interface that UBOOT
 is installing at boot time and therefore the fact that the SRC device is
 unimplemented is hidden as Qemu respond directly to PSCI requets without
 using the SRC device.
 But if you try to run a more bare metal application (maybe uboot itself),
 then it is not possible to start the secondary CPU as the SRC is an
 unimplemented device.
 This patch adds the ability to start the secondary CPU through the SRC
 device so that you can use this feature in bare metal applications.
 Signed-off-by: Jean-Christophe Dubois <jcd@tribudubois.net>
 Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
-Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
+Message-id: ce9a0162defd2acee5dc7f8a674743de0cded569.1692964892.git.jcd@tribudubois.net
 Message-id: 20220708151540.18136-3-richard.henderson@linaro.org
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 ---
- target/arm/translate-a64.h |  1 +
+ include/hw/arm/fsl-imx7.h  |   3 +-
- target/arm/sme.decode      | 20 ++++++++++++++++++++
+ include/hw/misc/imx7_src.h |  66 +++++++++
- target/arm/translate-a64.c |  7 ++++++-
+ hw/arm/fsl-imx7.c          |   8 +-
- target/arm/translate-sme.c | 35 +++++++++++++++++++++++++++++++++++
+ hw/misc/imx7_src.c         | 276 +++++++++++++++++++++++++++++++++++++
- target/arm/meson.build     |  2 ++
+ hw/misc/meson.build        |   1 +
-files changed, 64 insertions(+), 1 deletion(-)
+ hw/misc/trace-events       |   4 +
- create mode 100644 target/arm/sme.decode
+files changed, 356 insertions(+), 2 deletions(-)
- create mode 100644 target/arm/translate-sme.c
+ create mode 100644 include/hw/misc/imx7_src.h
+ create mode 100644 hw/misc/imx7_src.c
-diff --git a/target/arm/translate-a64.h b/target/arm/translate-a64.h
 diff --git a/include/hw/arm/fsl-imx7.h b/include/hw/arm/fsl-imx7.h
 index XXXXXXX..XXXXXXX 100644
---- a/target/arm/translate-a64.h
+--- a/include/hw/arm/fsl-imx7.h
-+++ b/target/arm/translate-a64.h
++++ b/include/hw/arm/fsl-imx7.h
-@@ -XXX,XX +XXX,XX @@ static inline int pred_gvec_reg_size(DisasContext *s)
+@@ -XXX,XX +XXX,XX @@
- }
+ #include "hw/misc/imx7_ccm.h"
+ #include "hw/misc/imx7_snvs.h"
- bool disas_sve(DisasContext *, uint32_t);
+ #include "hw/misc/imx7_gpr.h"
-+bool disas_sme(DisasContext *, uint32_t);
++#include "hw/misc/imx7_src.h"
+ #include "hw/watchdog/wdt_imx2.h"
- void gen_gvec_rax1(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs,
+ #include "hw/gpio/imx_gpio.h"
-                    uint32_t rm_ofs, uint32_t opr_sz, uint32_t max_sz);
+ #include "hw/char/imx_serial.h"
-diff --git a/target/arm/sme.decode b/target/arm/sme.decode
+@@ -XXX,XX +XXX,XX @@ struct FslIMX7State {
      IMX7CCMState       ccm;
      IMX7AnalogState    analog;
      IMX7SNVSState      snvs;
 +    IMX7SRCState       src;
      IMXGPCv2State      gpcv2;
      IMXSPIState        spi[FSL_IMX7_NUM_ECSPIS];
      IMXI2CState        i2c[FSL_IMX7_NUM_I2CS];
@@ -XXX,XX +XXX,XX @@ enum FslIMX7MemoryMap {
      FSL_IMX7_GPC_ADDR             = 0x303A0000,
      FSL_IMX7_SRC_ADDR             = 0x30390000,
 -    FSL_IMX7_SRC_SIZE             = (4 * KiB),
      FSL_IMX7_CCM_ADDR             = 0x30380000,
 diff --git a/include/hw/misc/imx7_src.h b/include/hw/misc/imx7_src.h
 new file mode 100644
 index XXXXXXX..XXXXXXX
 --- /dev/null
-+++ b/target/arm/sme.decode
++++ b/include/hw/misc/imx7_src.h
 @@ -XXX,XX +XXX,XX @@
-+# AArch64 SME instruction descriptions
++/*
-+#
++ * IMX7 System Reset Controller
-+#  Copyright (c) 2022 Linaro, Ltd
++ *
-+#
++ * Copyright (C) 2023 Jean-Christophe Dubois <jcd@tribudubois.net>
-+# This library is free software; you can redistribute it and/or
++ *
-+# modify it under the terms of the GNU Lesser General Public
++ * This work is licensed under the terms of the GNU GPL, version 2 or later.
-+# License as published by the Free Software Foundation; either
++ * See the COPYING file in the top-level directory.
-+# version 2.1 of the License, or (at your option) any later version.
++ */
-+#
++
-+# This library is distributed in the hope that it will be useful,
++#ifndef IMX7_SRC_H
-+# but WITHOUT ANY WARRANTY; without even the implied warranty of
++#define IMX7_SRC_H
-+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
++
-+# Lesser General Public License for more details.
++#include "hw/sysbus.h"
-+#
++#include "qemu/bitops.h"
-+# You should have received a copy of the GNU Lesser General Public
++#include "qom/object.h"
-+# License along with this library; if not, see <http://www.gnu.org/licenses/>.
++
-+
++#define SRC_SCR 0
-+#
++#define SRC_A7RCR0 1
-+# This file is processed by scripts/decodetree.py
++#define SRC_A7RCR1 2
-+#
++#define SRC_M4RCR 3
-diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
++#define SRC_ERCR 5
 +#define SRC_HSICPHY_RCR 7
 +#define SRC_USBOPHY1_RCR 8
 +#define SRC_USBOPHY2_RCR 9
 +#define SRC_MPIPHY_RCR 10
 +#define SRC_PCIEPHY_RCR 11
 +#define SRC_SBMR1 22
 +#define SRC_SRSR 23
 +#define SRC_SISR 26
 +#define SRC_SIMR 27
 +#define SRC_SBMR2 28
 +#define SRC_GPR1 29
 +#define SRC_GPR2 30
 +#define SRC_GPR3 31
 +#define SRC_GPR4 32
 +#define SRC_GPR5 33
 +#define SRC_GPR6 34
 +#define SRC_GPR7 35
 +#define SRC_GPR8 36
 +#define SRC_GPR9 37
 +#define SRC_GPR10 38
 +#define SRC_MAX 39
 +
 +/* SRC_A7SCR1 */
 +#define R_CORE1_ENABLE_SHIFT     1
 +#define R_CORE1_ENABLE_LENGTH    1
 +/* SRC_A7SCR0 */
 +#define R_CORE1_RST_SHIFT        5
 +#define R_CORE1_RST_LENGTH       1
 +#define R_CORE0_RST_SHIFT        4
 +#define R_CORE0_RST_LENGTH       1
 +
 +#define TYPE_IMX7_SRC "imx7.src"
 +OBJECT_DECLARE_SIMPLE_TYPE(IMX7SRCState, IMX7_SRC)
 +
 +struct IMX7SRCState {
 +    /* <private> */
 +    SysBusDevice parent_obj;
 +
 +    /* <public> */
 +    MemoryRegion iomem;
 +
 +    uint32_t regs[SRC_MAX];
 +};
 +
 +#endif /* IMX7_SRC_H */
 diff --git a/hw/arm/fsl-imx7.c b/hw/arm/fsl-imx7.c
 index XXXXXXX..XXXXXXX 100644
---- a/target/arm/translate-a64.c
+--- a/hw/arm/fsl-imx7.c
-+++ b/target/arm/translate-a64.c
++++ b/hw/arm/fsl-imx7.c
-@@ -XXX,XX +XXX,XX @@ static void aarch64_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu)
+@@ -XXX,XX +XXX,XX @@ static void fsl_imx7_init(Object *obj)
-     }
+      */
+     object_initialize_child(obj, "gpcv2", &s->gpcv2, TYPE_IMX_GPCV2);
-     switch (extract32(insn, 25, 4)) {
--    case 0x0: case 0x1: case 0x3: /* UNALLOCATED */
++    /*
-+    case 0x0:
++     * SRC
-+        if (!extract32(insn, 31, 1) || !disas_sme(s, insn)) {
++     */
-+            unallocated_encoding(s);
++    object_initialize_child(obj, "src", &s->src, TYPE_IMX7_SRC);
-+        }
++
-+        break;
+     /*
-+    case 0x1: case 0x3: /* UNALLOCATED */
+      * ECSPIs
-         unallocated_encoding(s);
+      */
-         break;
+@@ -XXX,XX +XXX,XX @@ static void fsl_imx7_realize(DeviceState *dev, Error **errp)
-     case 0x2:
+     /*
-diff --git a/target/arm/translate-sme.c b/target/arm/translate-sme.c
+      * SRC
       */
 -    create_unimplemented_device("src", FSL_IMX7_SRC_ADDR, FSL_IMX7_SRC_SIZE);
 +    sysbus_realize(SYS_BUS_DEVICE(&s->src), &error_abort);
 +    sysbus_mmio_map(SYS_BUS_DEVICE(&s->src), 0, FSL_IMX7_SRC_ADDR);
      /*
       * Watchdogs
 diff --git a/hw/misc/imx7_src.c b/hw/misc/imx7_src.c
 new file mode 100644
 index XXXXXXX..XXXXXXX
 --- /dev/null
-+++ b/target/arm/translate-sme.c
++++ b/hw/misc/imx7_src.c
 @@ -XXX,XX +XXX,XX @@
 +/*
-+ * AArch64 SME translation
++ * IMX7 System Reset Controller
 + *
-+ * Copyright (c) 2022 Linaro, Ltd
++ * Copyright (c) 2023 Jean-Christophe Dubois <jcd@tribudubois.net>
 + *
-+ * This library is free software; you can redistribute it and/or
++ * This work is licensed under the terms of the GNU GPL, version 2 or later.
-+ * modify it under the terms of the GNU Lesser General Public
++ * See the COPYING file in the top-level directory.
 + * License as published by the Free Software Foundation; either
 + * version 2.1 of the License, or (at your option) any later version.
 + *
-+ * This library is distributed in the hope that it will be useful,
-+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
-+ * Lesser General Public License for more details.
-+ *
-+ * You should have received a copy of the GNU Lesser General Public
-+ * License along with this library; if not, see <http://www.gnu.org/licenses/>.
 + */
 +
 +#include "qemu/osdep.h"
-+#include "cpu.h"
++#include "hw/misc/imx7_src.h"
-+#include "tcg/tcg-op.h"
++#include "migration/vmstate.h"
-+#include "tcg/tcg-op-gvec.h"
++#include "qemu/bitops.h"
-+#include "tcg/tcg-gvec-desc.h"
++#include "qemu/log.h"
-+#include "translate.h"
++#include "qemu/main-loop.h"
-+#include "exec/helper-gen.h"
++#include "qemu/module.h"
-+#include "translate-a64.h"
++#include "target/arm/arm-powerctl.h"
-+#include "fpu/softfloat.h"
++#include "hw/core/cpu.h"
 +#include "hw/registerfields.h"
 +
 +#include "trace.h"
 +
 +static const char *imx7_src_reg_name(uint32_t reg)
 +{
 +    static char unknown[20];
 +
 +    switch (reg) {
 +    case SRC_SCR:
 +        return "SRC_SCR";
 +    case SRC_A7RCR0:
 +        return "SRC_A7RCR0";
 +    case SRC_A7RCR1:
 +        return "SRC_A7RCR1";
 +    case SRC_M4RCR:
 +        return "SRC_M4RCR";
 +    case SRC_ERCR:
 +        return "SRC_ERCR";
 +    case SRC_HSICPHY_RCR:
 +        return "SRC_HSICPHY_RCR";
 +    case SRC_USBOPHY1_RCR:
 +        return "SRC_USBOPHY1_RCR";
 +    case SRC_USBOPHY2_RCR:
 +        return "SRC_USBOPHY2_RCR";
 +    case SRC_PCIEPHY_RCR:
 +        return "SRC_PCIEPHY_RCR";
 +    case SRC_SBMR1:
 +        return "SRC_SBMR1";
 +    case SRC_SRSR:
 +        return "SRC_SRSR";
 +    case SRC_SISR:
 +        return "SRC_SISR";
 +    case SRC_SIMR:
 +        return "SRC_SIMR";
 +    case SRC_SBMR2:
 +        return "SRC_SBMR2";
 +    case SRC_GPR1:
 +        return "SRC_GPR1";
 +    case SRC_GPR2:
 +        return "SRC_GPR2";
 +    case SRC_GPR3:
 +        return "SRC_GPR3";
 +    case SRC_GPR4:
 +        return "SRC_GPR4";
 +    case SRC_GPR5:
 +        return "SRC_GPR5";
 +    case SRC_GPR6:
 +        return "SRC_GPR6";
 +    case SRC_GPR7:
 +        return "SRC_GPR7";
 +    case SRC_GPR8:
 +        return "SRC_GPR8";
 +    case SRC_GPR9:
 +        return "SRC_GPR9";
 +    case SRC_GPR10:
 +        return "SRC_GPR10";
 +    default:
 +        sprintf(unknown, "%u ?", reg);
 +        return unknown;
 +    }
 +}
 +
 +static const VMStateDescription vmstate_imx7_src = {
 +    .name = TYPE_IMX7_SRC,
 +    .version_id = 1,
 +    .minimum_version_id = 1,
 +    .fields = (VMStateField[]) {
 +        VMSTATE_UINT32_ARRAY(regs, IMX7SRCState, SRC_MAX),
 +        VMSTATE_END_OF_LIST()
 +    },
 +};
 +
 +static void imx7_src_reset(DeviceState *dev)
 +{
 +    IMX7SRCState *s = IMX7_SRC(dev);
 +
 +    memset(s->regs, 0, sizeof(s->regs));
 +
 +    /* Set reset values */
 +    s->regs[SRC_SCR] = 0xA0;
 +    s->regs[SRC_SRSR] = 0x1;
 +    s->regs[SRC_SIMR] = 0x1F;
 +}
 +
 +static uint64_t imx7_src_read(void *opaque, hwaddr offset, unsigned size)
 +{
 +    uint32_t value = 0;
 +    IMX7SRCState *s = (IMX7SRCState *)opaque;
 +    uint32_t index = offset >> 2;
 +
 +    if (index < SRC_MAX) {
 +        value = s->regs[index];
 +    } else {
 +        qemu_log_mask(LOG_GUEST_ERROR, "[%s]%s: Bad register at offset 0x%"
 +                      HWADDR_PRIx "\n", TYPE_IMX7_SRC, __func__, offset);
 +    }
 +
 +    trace_imx7_src_read(imx7_src_reg_name(index), value);
 +
 +    return value;
 +}
 +
 +
 +/*
-+ * Include the generated decoder.
++ * The reset is asynchronous so we need to defer clearing the reset
 + * bit until the work is completed.
 + */
 +
-+#include "decode-sme.c.inc"
++struct SRCSCRResetInfo {
-diff --git a/target/arm/meson.build b/target/arm/meson.build
++    IMX7SRCState *s;
 +    uint32_t reset_bit;
 +};
 +
 +static void imx7_clear_reset_bit(CPUState *cpu, run_on_cpu_data data)
 +{
 +    struct SRCSCRResetInfo *ri = data.host_ptr;
 +    IMX7SRCState *s = ri->s;
 +
 +    assert(qemu_mutex_iothread_locked());
 +
 +    s->regs[SRC_A7RCR0] = deposit32(s->regs[SRC_A7RCR0], ri->reset_bit, 1, 0);
 +
 +    trace_imx7_src_write(imx7_src_reg_name(SRC_A7RCR0), s->regs[SRC_A7RCR0]);
 +
 +    g_free(ri);
 +}
 +
 +static void imx7_defer_clear_reset_bit(uint32_t cpuid,
 +                                       IMX7SRCState *s,
 +                                       uint32_t reset_shift)
 +{
 +    struct SRCSCRResetInfo *ri;
 +    CPUState *cpu = arm_get_cpu_by_id(cpuid);
 +
 +    if (!cpu) {
 +        return;
 +    }
 +
 +    ri = g_new(struct SRCSCRResetInfo, 1);
 +    ri->s = s;
 +    ri->reset_bit = reset_shift;
 +
 +    async_run_on_cpu(cpu, imx7_clear_reset_bit, RUN_ON_CPU_HOST_PTR(ri));
 +}
 +
 +
 +static void imx7_src_write(void *opaque, hwaddr offset, uint64_t value,
 +                           unsigned size)
 +{
 +    IMX7SRCState *s = (IMX7SRCState *)opaque;
 +    uint32_t index = offset >> 2;
 +    long unsigned int change_mask;
 +    uint32_t current_value = value;
 +
 +    if (index >= SRC_MAX) {
 +        qemu_log_mask(LOG_GUEST_ERROR, "[%s]%s: Bad register at offset 0x%"
 +                      HWADDR_PRIx "\n", TYPE_IMX7_SRC, __func__, offset);
 +        return;
 +    }
 +
 +    trace_imx7_src_write(imx7_src_reg_name(SRC_A7RCR0), s->regs[SRC_A7RCR0]);
 +
 +    change_mask = s->regs[index] ^ (uint32_t)current_value;
 +
 +    switch (index) {
 +    case SRC_A7RCR0:
 +        if (FIELD_EX32(change_mask, CORE0, RST)) {
 +            arm_reset_cpu(0);
 +            imx7_defer_clear_reset_bit(0, s, R_CORE0_RST_SHIFT);
 +        }
 +        if (FIELD_EX32(change_mask, CORE1, RST)) {
 +            arm_reset_cpu(1);
 +            imx7_defer_clear_reset_bit(1, s, R_CORE1_RST_SHIFT);
 +        }
 +        s->regs[index] = current_value;
 +        break;
 +    case SRC_A7RCR1:
 +        /*
 +         * On real hardware when the system reset controller starts a
 +         * secondary CPU it runs through some boot ROM code which reads
 +         * the SRC_GPRX registers controlling the start address and branches
 +         * to it.
 +         * Here we are taking a short cut and branching directly to the
 +         * requested address (we don't want to run the boot ROM code inside
 +         * QEMU)
 +         */
 +        if (FIELD_EX32(change_mask, CORE1, ENABLE)) {
 +            if (FIELD_EX32(current_value, CORE1, ENABLE)) {
 +                /* CORE 1 is brought up */
 +                arm_set_cpu_on(1, s->regs[SRC_GPR3], s->regs[SRC_GPR4],
 +                               3, false);
 +            } else {
 +                /* CORE 1 is shut down */
 +                arm_set_cpu_off(1);
 +            }
 +            /* We clear the reset bits as the processor changed state */
 +            imx7_defer_clear_reset_bit(1, s, R_CORE1_RST_SHIFT);
 +            clear_bit(R_CORE1_RST_SHIFT, &change_mask);
 +        }
 +        s->regs[index] = current_value;
 +        break;
 +    default:
 +        s->regs[index] = current_value;
 +        break;
 +    }
 +}
 +
 +static const struct MemoryRegionOps imx7_src_ops = {
 +    .read = imx7_src_read,
 +    .write = imx7_src_write,
 +    .endianness = DEVICE_NATIVE_ENDIAN,
 +    .valid = {
 +        /*
 +         * Our device would not work correctly if the guest was doing
 +         * unaligned access. This might not be a limitation on the real
 +         * device but in practice there is no reason for a guest to access
 +         * this device unaligned.
 +         */
 +        .min_access_size = 4,
 +        .max_access_size = 4,
 +        .unaligned = false,
 +    },
 +};
 +
 +static void imx7_src_realize(DeviceState *dev, Error **errp)
 +{
 +    IMX7SRCState *s = IMX7_SRC(dev);
 +
 +    memory_region_init_io(&s->iomem, OBJECT(dev), &imx7_src_ops, s,
 +                          TYPE_IMX7_SRC, 0x1000);
 +    sysbus_init_mmio(SYS_BUS_DEVICE(dev), &s->iomem);
 +}
 +
 +static void imx7_src_class_init(ObjectClass *klass, void *data)
 +{
 +    DeviceClass *dc = DEVICE_CLASS(klass);
 +
 +    dc->realize = imx7_src_realize;
 +    dc->reset = imx7_src_reset;
 +    dc->vmsd = &vmstate_imx7_src;
 +    dc->desc = "i.MX6 System Reset Controller";
 +}
 +
 +static const TypeInfo imx7_src_info = {
 +    .name          = TYPE_IMX7_SRC,
 +    .parent        = TYPE_SYS_BUS_DEVICE,
 +    .instance_size = sizeof(IMX7SRCState),
 +    .class_init    = imx7_src_class_init,
 +};
 +
 +static void imx7_src_register_types(void)
 +{
 +    type_register_static(&imx7_src_info);
 +}
 +
 +type_init(imx7_src_register_types)
 diff --git a/hw/misc/meson.build b/hw/misc/meson.build
 index XXXXXXX..XXXXXXX 100644
---- a/target/arm/meson.build
+--- a/hw/misc/meson.build
-+++ b/target/arm/meson.build
++++ b/hw/misc/meson.build
-@@ -XXX,XX +XXX,XX @@
+@@ -XXX,XX +XXX,XX @@ system_ss.add(when: 'CONFIG_IMX', if_true: files(
- gen = [
+   'imx6_src.c',
-   decodetree.process('sve.decode', extra_args: '--decode=disas_sve'),
+   'imx6ul_ccm.c',
-+  decodetree.process('sme.decode', extra_args: '--decode=disas_sme'),
+   'imx7_ccm.c',
-   decodetree.process('neon-shared.decode', extra_args: '--decode=disas_neon_shared'),
++  'imx7_src.c',
-   decodetree.process('neon-dp.decode', extra_args: '--decode=disas_neon_dp'),
+   'imx7_gpr.c',
-   decodetree.process('neon-ls.decode', extra_args: '--decode=disas_neon_ls'),
+   'imx7_snvs.c',
-@@ -XXX,XX +XXX,XX @@ arm_ss.add(when: 'TARGET_AARCH64', if_true: files(
+   'imx_ccm.c',
-   'sme_helper.c',
+diff --git a/hw/misc/trace-events b/hw/misc/trace-events
-   'translate-a64.c',
+index XXXXXXX..XXXXXXX 100644
-   'translate-sve.c',
+--- a/hw/misc/trace-events
-+  'translate-sme.c',
++++ b/hw/misc/trace-events
- ))
+@@ -XXX,XX +XXX,XX @@ ccm_clock_freq(uint32_t clock, uint32_t freq) "(Clock = %d) = %d"
+ ccm_read_reg(const char *reg_name, uint32_t value) "reg[%s] <= 0x%" PRIx32
- arm_softmmu_ss = ss.source_set()
+ ccm_write_reg(const char *reg_name, uint32_t value) "reg[%s] => 0x%" PRIx32
 +# imx7_src.c
 +imx7_src_read(const char *reg_name, uint32_t value) "reg[%s] => 0x%" PRIx32
 +imx7_src_write(const char *reg_name, uint32_t value) "reg[%s] <= 0x%" PRIx32
 +
  # iotkit-sysinfo.c
  iotkit_sysinfo_read(uint64_t offset, uint64_t data, unsigned size) "IoTKit SysInfo read: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %u"
  iotkit_sysinfo_write(uint64_t offset, uint64_t data, unsigned size) "IoTKit SysInfo write: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %u"
 --
-.25.1
+.34.1

-[PULL 04/45] target/arm: Mark ADR as non-streaming
+Deleted patch
-From: Richard Henderson <richard.henderson@linaro.org>
-Mark ADR as a non-streaming instruction, which should trap
-if full a64 support is not enabled in streaming mode.
-Removing entries from sme-fa64.decode is an easy way to see
-what remains to be done.
-Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
-Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
-Message-id: 20220708151540.18136-5-richard.henderson@linaro.org
-Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
----
- target/arm/translate.h     | 7 +++++++
- target/arm/sme-fa64.decode | 1 -
- target/arm/translate-sve.c | 8 ++++----
-files changed, 11 insertions(+), 5 deletions(-)
-diff --git a/target/arm/translate.h b/target/arm/translate.h
-index XXXXXXX..XXXXXXX 100644
---- a/target/arm/translate.h
-+++ b/target/arm/translate.h
-@@ -XXX,XX +XXX,XX @@ uint64_t asimd_imm_const(uint32_t imm, int cmode, int op);
-     static bool trans_##NAME(DisasContext *s, arg_##NAME *a) \
-     { return dc_isar_feature(FEAT, s) && FUNC(s, __VA_ARGS__); }
-+#define TRANS_FEAT_NONSTREAMING(NAME, FEAT, FUNC, ...)            \
-+    static bool trans_##NAME(DisasContext *s, arg_##NAME *a)      \
-+    {                                                             \
-+        s->is_nonstreaming = true;                                \
-+        return dc_isar_feature(FEAT, s) && FUNC(s, __VA_ARGS__);  \
-+    }
-+
- #endif /* TARGET_ARM_TRANSLATE_H */
-diff --git a/target/arm/sme-fa64.decode b/target/arm/sme-fa64.decode
-index XXXXXXX..XXXXXXX 100644
---- a/target/arm/sme-fa64.decode
-+++ b/target/arm/sme-fa64.decode
-@@ -XXX,XX +XXX,XX @@ FAIL    0001 1110 0111 1110 0000 00-- ---- ----   # FJCVTZS
- #       --11 1100 --1- ---- ---- ---- ---- --10   # Load/store FP register (register offset)
- #       --11 1101 ---- ---- ---- ---- ---- ----   # Load/store FP register (scaled imm)
--FAIL    0000 0100 --1- ---- 1010 ---- ---- ----   # ADR
- FAIL    0000 0100 --1- ---- 1011 -0-- ---- ----   # FTSSEL, FEXPA
- FAIL    0000 0101 --10 0001 100- ---- ---- ----   # COMPACT
- FAIL    0010 0101 --01 100- 1111 000- ---0 ----   # RDFFR, RDFFRS
-diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
-index XXXXXXX..XXXXXXX 100644
---- a/target/arm/translate-sve.c
-+++ b/target/arm/translate-sve.c
-@@ -XXX,XX +XXX,XX @@ static bool do_adr(DisasContext *s, arg_rrri *a, gen_helper_gvec_3 *fn)
-     return gen_gvec_ool_zzz(s, fn, a->rd, a->rn, a->rm, a->imm);
- }
--TRANS_FEAT(ADR_p32, aa64_sve, do_adr, a, gen_helper_sve_adr_p32)
--TRANS_FEAT(ADR_p64, aa64_sve, do_adr, a, gen_helper_sve_adr_p64)
--TRANS_FEAT(ADR_s32, aa64_sve, do_adr, a, gen_helper_sve_adr_s32)
--TRANS_FEAT(ADR_u32, aa64_sve, do_adr, a, gen_helper_sve_adr_u32)
-+TRANS_FEAT_NONSTREAMING(ADR_p32, aa64_sve, do_adr, a, gen_helper_sve_adr_p32)
-+TRANS_FEAT_NONSTREAMING(ADR_p64, aa64_sve, do_adr, a, gen_helper_sve_adr_p64)
-+TRANS_FEAT_NONSTREAMING(ADR_s32, aa64_sve, do_adr, a, gen_helper_sve_adr_s32)
-+TRANS_FEAT_NONSTREAMING(ADR_u32, aa64_sve, do_adr, a, gen_helper_sve_adr_u32)
- /*
-  *** SVE Integer Misc - Unpredicated Group
---
-.25.1

-[PULL 05/45] target/arm: Mark RDFFR, WRFFR, SETFFR as non-streaming
+Deleted patch
-From: Richard Henderson <richard.henderson@linaro.org>
-Mark these as a non-streaming instructions, which should trap
-if full a64 support is not enabled in streaming mode.
-Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
-Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
-Message-id: 20220708151540.18136-6-richard.henderson@linaro.org
-Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
----
- target/arm/sme-fa64.decode | 2 --
- target/arm/translate-sve.c | 9 ++++++---
-files changed, 6 insertions(+), 5 deletions(-)
-diff --git a/target/arm/sme-fa64.decode b/target/arm/sme-fa64.decode
-index XXXXXXX..XXXXXXX 100644
---- a/target/arm/sme-fa64.decode
-+++ b/target/arm/sme-fa64.decode
-@@ -XXX,XX +XXX,XX @@ FAIL    0001 1110 0111 1110 0000 00-- ---- ----   # FJCVTZS
- FAIL    0000 0100 --1- ---- 1011 -0-- ---- ----   # FTSSEL, FEXPA
- FAIL    0000 0101 --10 0001 100- ---- ---- ----   # COMPACT
--FAIL    0010 0101 --01 100- 1111 000- ---0 ----   # RDFFR, RDFFRS
--FAIL    0010 0101 --10 1--- 1001 ---- ---- ----   # WRFFR, SETFFR
- FAIL    0100 0101 --0- ---- 1011 ---- ---- ----   # BDEP, BEXT, BGRP
- FAIL    0100 0101 000- ---- 0110 1--- ---- ----   # PMULLB, PMULLT (128b result)
- FAIL    0110 0100 --1- ---- 1110 01-- ---- ----   # FMMLA, BFMMLA
-diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
-index XXXXXXX..XXXXXXX 100644
---- a/target/arm/translate-sve.c
-+++ b/target/arm/translate-sve.c
-@@ -XXX,XX +XXX,XX @@ static bool do_predset(DisasContext *s, int esz, int rd, int pat, bool setflag)
- TRANS_FEAT(PTRUE, aa64_sve, do_predset, a->esz, a->rd, a->pat, a->s)
- /* Note pat == 31 is #all, to set all elements.  */
--TRANS_FEAT(SETFFR, aa64_sve, do_predset, 0, FFR_PRED_NUM, 31, false)
-+TRANS_FEAT_NONSTREAMING(SETFFR, aa64_sve,
-+                        do_predset, 0, FFR_PRED_NUM, 31, false)
- /* Note pat == 32 is #unimp, to set no elements.  */
- TRANS_FEAT(PFALSE, aa64_sve, do_predset, 0, a->rd, 32, false)
-@@ -XXX,XX +XXX,XX @@ static bool trans_RDFFR_p(DisasContext *s, arg_RDFFR_p *a)
-         .rd = a->rd, .pg = a->pg, .s = a->s,
-         .rn = FFR_PRED_NUM, .rm = FFR_PRED_NUM,
-     };
-+
-+    s->is_nonstreaming = true;
-     return trans_AND_pppp(s, &alt_a);
- }
--TRANS_FEAT(RDFFR, aa64_sve, do_mov_p, a->rd, FFR_PRED_NUM)
--TRANS_FEAT(WRFFR, aa64_sve, do_mov_p, FFR_PRED_NUM, a->rn)
-+TRANS_FEAT_NONSTREAMING(RDFFR, aa64_sve, do_mov_p, a->rd, FFR_PRED_NUM)
-+TRANS_FEAT_NONSTREAMING(WRFFR, aa64_sve, do_mov_p, FFR_PRED_NUM, a->rn)
- static bool do_pfirst_pnext(DisasContext *s, arg_rr_esz *a,
-                             void (*gen_fn)(TCGv_i32, TCGv_ptr,
---
-.25.1

-[PULL 06/45] target/arm: Mark BDEP, BEXT, BGRP, COMPACT, FEXPA, FTSSEL as non-streaming
+Deleted patch
-From: Richard Henderson <richard.henderson@linaro.org>
-Mark these as a non-streaming instructions, which should trap
-if full a64 support is not enabled in streaming mode.
-Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
-Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
-Message-id: 20220708151540.18136-7-richard.henderson@linaro.org
-Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
----
- target/arm/sme-fa64.decode |  3 ---
- target/arm/translate-sve.c | 22 ++++++++++++----------
-files changed, 12 insertions(+), 13 deletions(-)
-diff --git a/target/arm/sme-fa64.decode b/target/arm/sme-fa64.decode
-index XXXXXXX..XXXXXXX 100644
---- a/target/arm/sme-fa64.decode
-+++ b/target/arm/sme-fa64.decode
-@@ -XXX,XX +XXX,XX @@ FAIL    0001 1110 0111 1110 0000 00-- ---- ----   # FJCVTZS
- #       --11 1100 --1- ---- ---- ---- ---- --10   # Load/store FP register (register offset)
- #       --11 1101 ---- ---- ---- ---- ---- ----   # Load/store FP register (scaled imm)
--FAIL    0000 0100 --1- ---- 1011 -0-- ---- ----   # FTSSEL, FEXPA
--FAIL    0000 0101 --10 0001 100- ---- ---- ----   # COMPACT
--FAIL    0100 0101 --0- ---- 1011 ---- ---- ----   # BDEP, BEXT, BGRP
- FAIL    0100 0101 000- ---- 0110 1--- ---- ----   # PMULLB, PMULLT (128b result)
- FAIL    0110 0100 --1- ---- 1110 01-- ---- ----   # FMMLA, BFMMLA
- FAIL    0110 0101 --0- ---- 0000 11-- ---- ----   # FTSMUL
-diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
-index XXXXXXX..XXXXXXX 100644
---- a/target/arm/translate-sve.c
-+++ b/target/arm/translate-sve.c
-@@ -XXX,XX +XXX,XX @@ static gen_helper_gvec_2 * const fexpa_fns[4] = {
-     NULL,                   gen_helper_sve_fexpa_h,
-     gen_helper_sve_fexpa_s, gen_helper_sve_fexpa_d,
- };
--TRANS_FEAT(FEXPA, aa64_sve, gen_gvec_ool_zz,
--           fexpa_fns[a->esz], a->rd, a->rn, 0)
-+TRANS_FEAT_NONSTREAMING(FEXPA, aa64_sve, gen_gvec_ool_zz,
-+                        fexpa_fns[a->esz], a->rd, a->rn, 0)
- static gen_helper_gvec_3 * const ftssel_fns[4] = {
-     NULL,                    gen_helper_sve_ftssel_h,
-     gen_helper_sve_ftssel_s, gen_helper_sve_ftssel_d,
- };
--TRANS_FEAT(FTSSEL, aa64_sve, gen_gvec_ool_arg_zzz, ftssel_fns[a->esz], a, 0)
-+TRANS_FEAT_NONSTREAMING(FTSSEL, aa64_sve, gen_gvec_ool_arg_zzz,
-+                        ftssel_fns[a->esz], a, 0)
- /*
-  *** SVE Predicate Logical Operations Group
-@@ -XXX,XX +XXX,XX @@ TRANS_FEAT(TRN2_q, aa64_sve_f64mm, gen_gvec_ool_arg_zzz,
- static gen_helper_gvec_3 * const compact_fns[4] = {
-     NULL, NULL, gen_helper_sve_compact_s, gen_helper_sve_compact_d
- };
--TRANS_FEAT(COMPACT, aa64_sve, gen_gvec_ool_arg_zpz, compact_fns[a->esz], a, 0)
-+TRANS_FEAT_NONSTREAMING(COMPACT, aa64_sve, gen_gvec_ool_arg_zpz,
-+                        compact_fns[a->esz], a, 0)
- /* Call the helper that computes the ARM LastActiveElement pseudocode
-  * function, scaled by the element size.  This includes the not found
-@@ -XXX,XX +XXX,XX @@ static gen_helper_gvec_3 * const bext_fns[4] = {
-     gen_helper_sve2_bext_b, gen_helper_sve2_bext_h,
-     gen_helper_sve2_bext_s, gen_helper_sve2_bext_d,
- };
--TRANS_FEAT(BEXT, aa64_sve2_bitperm, gen_gvec_ool_arg_zzz,
--           bext_fns[a->esz], a, 0)
-+TRANS_FEAT_NONSTREAMING(BEXT, aa64_sve2_bitperm, gen_gvec_ool_arg_zzz,
-+                        bext_fns[a->esz], a, 0)
- static gen_helper_gvec_3 * const bdep_fns[4] = {
-     gen_helper_sve2_bdep_b, gen_helper_sve2_bdep_h,
-     gen_helper_sve2_bdep_s, gen_helper_sve2_bdep_d,
- };
--TRANS_FEAT(BDEP, aa64_sve2_bitperm, gen_gvec_ool_arg_zzz,
--           bdep_fns[a->esz], a, 0)
-+TRANS_FEAT_NONSTREAMING(BDEP, aa64_sve2_bitperm, gen_gvec_ool_arg_zzz,
-+                        bdep_fns[a->esz], a, 0)
- static gen_helper_gvec_3 * const bgrp_fns[4] = {
-     gen_helper_sve2_bgrp_b, gen_helper_sve2_bgrp_h,
-     gen_helper_sve2_bgrp_s, gen_helper_sve2_bgrp_d,
- };
--TRANS_FEAT(BGRP, aa64_sve2_bitperm, gen_gvec_ool_arg_zzz,
--           bgrp_fns[a->esz], a, 0)
-+TRANS_FEAT_NONSTREAMING(BGRP, aa64_sve2_bitperm, gen_gvec_ool_arg_zzz,
-+                        bgrp_fns[a->esz], a, 0)
- static gen_helper_gvec_3 * const cadd_fns[4] = {
-     gen_helper_sve2_cadd_b, gen_helper_sve2_cadd_h,
---
-.25.1

-[PULL 07/45] target/arm: Mark PMULL, FMMLA as non-streaming
+Deleted patch
-From: Richard Henderson <richard.henderson@linaro.org>
-Mark these as a non-streaming instructions, which should trap
-if full a64 support is not enabled in streaming mode.
-Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
-Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
-Message-id: 20220708151540.18136-8-richard.henderson@linaro.org
-Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
----
- target/arm/sme-fa64.decode |  2 --
- target/arm/translate-sve.c | 24 +++++++++++++++---------
-files changed, 15 insertions(+), 11 deletions(-)
-diff --git a/target/arm/sme-fa64.decode b/target/arm/sme-fa64.decode
-index XXXXXXX..XXXXXXX 100644
---- a/target/arm/sme-fa64.decode
-+++ b/target/arm/sme-fa64.decode
-@@ -XXX,XX +XXX,XX @@ FAIL    0001 1110 0111 1110 0000 00-- ---- ----   # FJCVTZS
- #       --11 1100 --1- ---- ---- ---- ---- --10   # Load/store FP register (register offset)
- #       --11 1101 ---- ---- ---- ---- ---- ----   # Load/store FP register (scaled imm)
--FAIL    0100 0101 000- ---- 0110 1--- ---- ----   # PMULLB, PMULLT (128b result)
--FAIL    0110 0100 --1- ---- 1110 01-- ---- ----   # FMMLA, BFMMLA
- FAIL    0110 0101 --0- ---- 0000 11-- ---- ----   # FTSMUL
- FAIL    0110 0101 --01 0--- 100- ---- ---- ----   # FTMAD
- FAIL    0110 0101 --01 1--- 001- ---- ---- ----   # FADDA
-diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
-index XXXXXXX..XXXXXXX 100644
---- a/target/arm/translate-sve.c
-+++ b/target/arm/translate-sve.c
-@@ -XXX,XX +XXX,XX @@ static bool do_trans_pmull(DisasContext *s, arg_rrr_esz *a, bool sel)
-         gen_helper_gvec_pmull_q, gen_helper_sve2_pmull_h,
-         NULL,                    gen_helper_sve2_pmull_d,
-     };
--    if (a->esz == 0
--        ? !dc_isar_feature(aa64_sve2_pmull128, s)
--        : !dc_isar_feature(aa64_sve, s)) {
-+
-+    if (a->esz == 0) {
-+        if (!dc_isar_feature(aa64_sve2_pmull128, s)) {
-+            return false;
-+        }
-+        s->is_nonstreaming = true;
-+    } else if (!dc_isar_feature(aa64_sve, s)) {
-         return false;
-     }
-     return gen_gvec_ool_arg_zzz(s, fns[a->esz], a, sel);
-@@ -XXX,XX +XXX,XX @@ DO_ZPZZ_FP(FMINP, aa64_sve2, sve2_fminp_zpzz)
-  * SVE Integer Multiply-Add (unpredicated)
-  */
--TRANS_FEAT(FMMLA_s, aa64_sve_f32mm, gen_gvec_fpst_zzzz, gen_helper_fmmla_s,
--           a->rd, a->rn, a->rm, a->ra, 0, FPST_FPCR)
--TRANS_FEAT(FMMLA_d, aa64_sve_f64mm, gen_gvec_fpst_zzzz, gen_helper_fmmla_d,
--           a->rd, a->rn, a->rm, a->ra, 0, FPST_FPCR)
-+TRANS_FEAT_NONSTREAMING(FMMLA_s, aa64_sve_f32mm, gen_gvec_fpst_zzzz,
-+                        gen_helper_fmmla_s, a->rd, a->rn, a->rm, a->ra,
-+                        0, FPST_FPCR)
-+TRANS_FEAT_NONSTREAMING(FMMLA_d, aa64_sve_f64mm, gen_gvec_fpst_zzzz,
-+                        gen_helper_fmmla_d, a->rd, a->rn, a->rm, a->ra,
-+                        0, FPST_FPCR)
- static gen_helper_gvec_4 * const sqdmlal_zzzw_fns[] = {
-     NULL,                           gen_helper_sve2_sqdmlal_zzzw_h,
-@@ -XXX,XX +XXX,XX @@ TRANS_FEAT(BFDOT_zzzz, aa64_sve_bf16, gen_gvec_ool_arg_zzzz,
- TRANS_FEAT(BFDOT_zzxz, aa64_sve_bf16, gen_gvec_ool_arg_zzxz,
-            gen_helper_gvec_bfdot_idx, a)
--TRANS_FEAT(BFMMLA, aa64_sve_bf16, gen_gvec_ool_arg_zzzz,
--           gen_helper_gvec_bfmmla, a, 0)
-+TRANS_FEAT_NONSTREAMING(BFMMLA, aa64_sve_bf16, gen_gvec_ool_arg_zzzz,
-+                        gen_helper_gvec_bfmmla, a, 0)
- static bool do_BFMLAL_zzzw(DisasContext *s, arg_rrrr_esz *a, bool sel)
- {
---
-.25.1

-[PULL 08/45] target/arm: Mark FTSMUL, FTMAD, FADDA as non-streaming
+Deleted patch
-From: Richard Henderson <richard.henderson@linaro.org>
-Mark these as a non-streaming instructions, which should trap
-if full a64 support is not enabled in streaming mode.
-Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
-Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
-Message-id: 20220708151540.18136-9-richard.henderson@linaro.org
-Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
----
- target/arm/sme-fa64.decode |  3 ---
- target/arm/translate-sve.c | 15 +++++++++++----
-files changed, 11 insertions(+), 7 deletions(-)
-diff --git a/target/arm/sme-fa64.decode b/target/arm/sme-fa64.decode
-index XXXXXXX..XXXXXXX 100644
---- a/target/arm/sme-fa64.decode
-+++ b/target/arm/sme-fa64.decode
-@@ -XXX,XX +XXX,XX @@ FAIL    0001 1110 0111 1110 0000 00-- ---- ----   # FJCVTZS
- #       --11 1100 --1- ---- ---- ---- ---- --10   # Load/store FP register (register offset)
- #       --11 1101 ---- ---- ---- ---- ---- ----   # Load/store FP register (scaled imm)
--FAIL    0110 0101 --0- ---- 0000 11-- ---- ----   # FTSMUL
--FAIL    0110 0101 --01 0--- 100- ---- ---- ----   # FTMAD
--FAIL    0110 0101 --01 1--- 001- ---- ---- ----   # FADDA
- FAIL    0100 0101 --0- ---- 1001 10-- ---- ----   # SMMLA, UMMLA, USMMLA
- FAIL    0100 0101 --1- ---- 1--- ---- ---- ----   # SVE2 string/histo/crypto instructions
- FAIL    1000 010- -00- ---- 10-- ---- ---- ----   # SVE2 32-bit gather NT load (vector+scalar)
-diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
-index XXXXXXX..XXXXXXX 100644
---- a/target/arm/translate-sve.c
-+++ b/target/arm/translate-sve.c
-@@ -XXX,XX +XXX,XX @@ static gen_helper_gvec_3_ptr * const ftmad_fns[4] = {
-     NULL,                   gen_helper_sve_ftmad_h,
-     gen_helper_sve_ftmad_s, gen_helper_sve_ftmad_d,
- };
--TRANS_FEAT(FTMAD, aa64_sve, gen_gvec_fpst_zzz,
--           ftmad_fns[a->esz], a->rd, a->rn, a->rm, a->imm,
--           a->esz == MO_16 ? FPST_FPCR_F16 : FPST_FPCR)
-+TRANS_FEAT_NONSTREAMING(FTMAD, aa64_sve, gen_gvec_fpst_zzz,
-+                        ftmad_fns[a->esz], a->rd, a->rn, a->rm, a->imm,
-+                        a->esz == MO_16 ? FPST_FPCR_F16 : FPST_FPCR)
- /*
-  *** SVE Floating Point Accumulating Reduction Group
-@@ -XXX,XX +XXX,XX @@ static bool trans_FADDA(DisasContext *s, arg_rprr_esz *a)
-     if (a->esz == 0 || !dc_isar_feature(aa64_sve, s)) {
-         return false;
-     }
-+    s->is_nonstreaming = true;
-     if (!sve_access_check(s)) {
-         return true;
-     }
-@@ -XXX,XX +XXX,XX @@ static bool trans_FADDA(DisasContext *s, arg_rprr_esz *a)
- DO_FP3(FADD_zzz, fadd)
- DO_FP3(FSUB_zzz, fsub)
- DO_FP3(FMUL_zzz, fmul)
--DO_FP3(FTSMUL, ftsmul)
- DO_FP3(FRECPS, recps)
- DO_FP3(FRSQRTS, rsqrts)
- #undef DO_FP3
-+static gen_helper_gvec_3_ptr * const ftsmul_fns[4] = {
-+    NULL,                     gen_helper_gvec_ftsmul_h,
-+    gen_helper_gvec_ftsmul_s, gen_helper_gvec_ftsmul_d
-+};
-+TRANS_FEAT_NONSTREAMING(FTSMUL, aa64_sve, gen_gvec_fpst_arg_zzz,
-+                        ftsmul_fns[a->esz], a, 0)
-+
- /*
-  *** SVE Floating Point Arithmetic - Predicated Group
-  */
---
-.25.1

-[PULL 09/45] target/arm: Mark SMMLA, UMMLA, USMMLA as non-streaming
+Deleted patch
-From: Richard Henderson <richard.henderson@linaro.org>
-Mark these as a non-streaming instructions, which should trap
-if full a64 support is not enabled in streaming mode.
-Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
-Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
-Message-id: 20220708151540.18136-10-richard.henderson@linaro.org
-Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
----
- target/arm/sme-fa64.decode |  1 -
- target/arm/translate-sve.c | 12 ++++++------
-files changed, 6 insertions(+), 7 deletions(-)
-diff --git a/target/arm/sme-fa64.decode b/target/arm/sme-fa64.decode
-index XXXXXXX..XXXXXXX 100644
---- a/target/arm/sme-fa64.decode
-+++ b/target/arm/sme-fa64.decode
-@@ -XXX,XX +XXX,XX @@ FAIL    0001 1110 0111 1110 0000 00-- ---- ----   # FJCVTZS
- #       --11 1100 --1- ---- ---- ---- ---- --10   # Load/store FP register (register offset)
- #       --11 1101 ---- ---- ---- ---- ---- ----   # Load/store FP register (scaled imm)
--FAIL    0100 0101 --0- ---- 1001 10-- ---- ----   # SMMLA, UMMLA, USMMLA
- FAIL    0100 0101 --1- ---- 1--- ---- ---- ----   # SVE2 string/histo/crypto instructions
- FAIL    1000 010- -00- ---- 10-- ---- ---- ----   # SVE2 32-bit gather NT load (vector+scalar)
- FAIL    1000 010- -00- ---- 111- ---- ---- ----   # SVE 32-bit gather prefetch (vector+imm)
-diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
-index XXXXXXX..XXXXXXX 100644
---- a/target/arm/translate-sve.c
-+++ b/target/arm/translate-sve.c
-@@ -XXX,XX +XXX,XX @@ TRANS_FEAT(FMLALT_zzxw, aa64_sve2, do_FMLAL_zzxw, a, false, true)
- TRANS_FEAT(FMLSLB_zzxw, aa64_sve2, do_FMLAL_zzxw, a, true, false)
- TRANS_FEAT(FMLSLT_zzxw, aa64_sve2, do_FMLAL_zzxw, a, true, true)
--TRANS_FEAT(SMMLA, aa64_sve_i8mm, gen_gvec_ool_arg_zzzz,
--           gen_helper_gvec_smmla_b, a, 0)
--TRANS_FEAT(USMMLA, aa64_sve_i8mm, gen_gvec_ool_arg_zzzz,
--           gen_helper_gvec_usmmla_b, a, 0)
--TRANS_FEAT(UMMLA, aa64_sve_i8mm, gen_gvec_ool_arg_zzzz,
--           gen_helper_gvec_ummla_b, a, 0)
-+TRANS_FEAT_NONSTREAMING(SMMLA, aa64_sve_i8mm, gen_gvec_ool_arg_zzzz,
-+                        gen_helper_gvec_smmla_b, a, 0)
-+TRANS_FEAT_NONSTREAMING(USMMLA, aa64_sve_i8mm, gen_gvec_ool_arg_zzzz,
-+                        gen_helper_gvec_usmmla_b, a, 0)
-+TRANS_FEAT_NONSTREAMING(UMMLA, aa64_sve_i8mm, gen_gvec_ool_arg_zzzz,
-+                        gen_helper_gvec_ummla_b, a, 0)
- TRANS_FEAT(BFDOT_zzzz, aa64_sve_bf16, gen_gvec_ool_arg_zzzz,
-            gen_helper_gvec_bfdot, a, 0)
---
-.25.1

-[PULL 10/45] target/arm: Mark string/histo/crypto as non-streaming
+Deleted patch
-From: Richard Henderson <richard.henderson@linaro.org>
-Mark these as non-streaming instructions, which should trap
-if full a64 support is not enabled in streaming mode.
-Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
-Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
-Message-id: 20220708151540.18136-11-richard.henderson@linaro.org
-Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
----
- target/arm/sme-fa64.decode |  1 -
- target/arm/translate-sve.c | 35 ++++++++++++++++++-----------------
-files changed, 18 insertions(+), 18 deletions(-)
-diff --git a/target/arm/sme-fa64.decode b/target/arm/sme-fa64.decode
-index XXXXXXX..XXXXXXX 100644
---- a/target/arm/sme-fa64.decode
-+++ b/target/arm/sme-fa64.decode
-@@ -XXX,XX +XXX,XX @@ FAIL    0001 1110 0111 1110 0000 00-- ---- ----   # FJCVTZS
- #       --11 1100 --1- ---- ---- ---- ---- --10   # Load/store FP register (register offset)
- #       --11 1101 ---- ---- ---- ---- ---- ----   # Load/store FP register (scaled imm)
--FAIL    0100 0101 --1- ---- 1--- ---- ---- ----   # SVE2 string/histo/crypto instructions
- FAIL    1000 010- -00- ---- 10-- ---- ---- ----   # SVE2 32-bit gather NT load (vector+scalar)
- FAIL    1000 010- -00- ---- 111- ---- ---- ----   # SVE 32-bit gather prefetch (vector+imm)
- FAIL    1000 0100 0-1- ---- 0--- ---- ---- ----   # SVE 32-bit gather prefetch (scalar+vector)
-diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
-index XXXXXXX..XXXXXXX 100644
---- a/target/arm/translate-sve.c
-+++ b/target/arm/translate-sve.c
-@@ -XXX,XX +XXX,XX @@ DO_SVE2_ZZZ_NARROW(RSUBHNT, rsubhnt)
- static gen_helper_gvec_flags_4 * const match_fns[4] = {
-     gen_helper_sve2_match_ppzz_b, gen_helper_sve2_match_ppzz_h, NULL, NULL
- };
--TRANS_FEAT(MATCH, aa64_sve2, do_ppzz_flags, a, match_fns[a->esz])
-+TRANS_FEAT_NONSTREAMING(MATCH, aa64_sve2, do_ppzz_flags, a, match_fns[a->esz])
- static gen_helper_gvec_flags_4 * const nmatch_fns[4] = {
-     gen_helper_sve2_nmatch_ppzz_b, gen_helper_sve2_nmatch_ppzz_h, NULL, NULL
- };
--TRANS_FEAT(NMATCH, aa64_sve2, do_ppzz_flags, a, nmatch_fns[a->esz])
-+TRANS_FEAT_NONSTREAMING(NMATCH, aa64_sve2, do_ppzz_flags, a, nmatch_fns[a->esz])
- static gen_helper_gvec_4 * const histcnt_fns[4] = {
-     NULL, NULL, gen_helper_sve2_histcnt_s, gen_helper_sve2_histcnt_d
- };
--TRANS_FEAT(HISTCNT, aa64_sve2, gen_gvec_ool_arg_zpzz,
--           histcnt_fns[a->esz], a, 0)
-+TRANS_FEAT_NONSTREAMING(HISTCNT, aa64_sve2, gen_gvec_ool_arg_zpzz,
-+                        histcnt_fns[a->esz], a, 0)
--TRANS_FEAT(HISTSEG, aa64_sve2, gen_gvec_ool_arg_zzz,
--           a->esz == 0 ? gen_helper_sve2_histseg : NULL, a, 0)
-+TRANS_FEAT_NONSTREAMING(HISTSEG, aa64_sve2, gen_gvec_ool_arg_zzz,
-+                        a->esz == 0 ? gen_helper_sve2_histseg : NULL, a, 0)
- DO_ZPZZ_FP(FADDP, aa64_sve2, sve2_faddp_zpzz)
- DO_ZPZZ_FP(FMAXNMP, aa64_sve2, sve2_fmaxnmp_zpzz)
-@@ -XXX,XX +XXX,XX @@ TRANS_FEAT(SQRDCMLAH_zzzz, aa64_sve2, gen_gvec_ool_zzzz,
- TRANS_FEAT(USDOT_zzzz, aa64_sve_i8mm, gen_gvec_ool_arg_zzzz,
-            a->esz == 2 ? gen_helper_gvec_usdot_b : NULL, a, 0)
--TRANS_FEAT(AESMC, aa64_sve2_aes, gen_gvec_ool_zz,
--           gen_helper_crypto_aesmc, a->rd, a->rd, a->decrypt)
-+TRANS_FEAT_NONSTREAMING(AESMC, aa64_sve2_aes, gen_gvec_ool_zz,
-+                        gen_helper_crypto_aesmc, a->rd, a->rd, a->decrypt)
--TRANS_FEAT(AESE, aa64_sve2_aes, gen_gvec_ool_arg_zzz,
--           gen_helper_crypto_aese, a, false)
--TRANS_FEAT(AESD, aa64_sve2_aes, gen_gvec_ool_arg_zzz,
--           gen_helper_crypto_aese, a, true)
-+TRANS_FEAT_NONSTREAMING(AESE, aa64_sve2_aes, gen_gvec_ool_arg_zzz,
-+                        gen_helper_crypto_aese, a, false)
-+TRANS_FEAT_NONSTREAMING(AESD, aa64_sve2_aes, gen_gvec_ool_arg_zzz,
-+                        gen_helper_crypto_aese, a, true)
--TRANS_FEAT(SM4E, aa64_sve2_sm4, gen_gvec_ool_arg_zzz,
--           gen_helper_crypto_sm4e, a, 0)
--TRANS_FEAT(SM4EKEY, aa64_sve2_sm4, gen_gvec_ool_arg_zzz,
--           gen_helper_crypto_sm4ekey, a, 0)
-+TRANS_FEAT_NONSTREAMING(SM4E, aa64_sve2_sm4, gen_gvec_ool_arg_zzz,
-+                        gen_helper_crypto_sm4e, a, 0)
-+TRANS_FEAT_NONSTREAMING(SM4EKEY, aa64_sve2_sm4, gen_gvec_ool_arg_zzz,
-+                        gen_helper_crypto_sm4ekey, a, 0)
--TRANS_FEAT(RAX1, aa64_sve2_sha3, gen_gvec_fn_arg_zzz, gen_gvec_rax1, a)
-+TRANS_FEAT_NONSTREAMING(RAX1, aa64_sve2_sha3, gen_gvec_fn_arg_zzz,
-+                        gen_gvec_rax1, a)
- TRANS_FEAT(FCVTNT_sh, aa64_sve2, gen_gvec_fpst_arg_zpz,
-            gen_helper_sve2_fcvtnt_sh, a, 0, FPST_FPCR)
---
-.25.1

-[PULL 11/45] target/arm: Mark gather/scatter load/store as non-streaming
+Deleted patch
-From: Richard Henderson <richard.henderson@linaro.org>
-Mark these as a non-streaming instructions, which should trap
-if full a64 support is not enabled in streaming mode.
-Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
-Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
-Message-id: 20220708151540.18136-12-richard.henderson@linaro.org
-Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
----
- target/arm/sme-fa64.decode | 9 ---------
- target/arm/translate-sve.c | 6 ++++++
-files changed, 6 insertions(+), 9 deletions(-)
-diff --git a/target/arm/sme-fa64.decode b/target/arm/sme-fa64.decode
-index XXXXXXX..XXXXXXX 100644
---- a/target/arm/sme-fa64.decode
-+++ b/target/arm/sme-fa64.decode
-@@ -XXX,XX +XXX,XX @@ FAIL    0001 1110 0111 1110 0000 00-- ---- ----   # FJCVTZS
- #       --11 1100 --1- ---- ---- ---- ---- --10   # Load/store FP register (register offset)
- #       --11 1101 ---- ---- ---- ---- ---- ----   # Load/store FP register (scaled imm)
--FAIL    1000 010- -00- ---- 10-- ---- ---- ----   # SVE2 32-bit gather NT load (vector+scalar)
- FAIL    1000 010- -00- ---- 111- ---- ---- ----   # SVE 32-bit gather prefetch (vector+imm)
- FAIL    1000 0100 0-1- ---- 0--- ---- ---- ----   # SVE 32-bit gather prefetch (scalar+vector)
--FAIL    1000 010- -01- ---- 1--- ---- ---- ----   # SVE 32-bit gather load (vector+imm)
--FAIL    1000 0100 0-0- ---- 0--- ---- ---- ----   # SVE 32-bit gather load byte (scalar+vector)
--FAIL    1000 0100 1--- ---- 0--- ---- ---- ----   # SVE 32-bit gather load half (scalar+vector)
--FAIL    1000 0101 0--- ---- 0--- ---- ---- ----   # SVE 32-bit gather load word (scalar+vector)
- FAIL    1010 010- ---- ---- 011- ---- ---- ----   # SVE contiguous FF load (scalar+scalar)
- FAIL    1010 010- ---1 ---- 101- ---- ---- ----   # SVE contiguous NF load (scalar+imm)
- FAIL    1010 010- -01- ---- 000- ---- ---- ----   # SVE load & replicate 32 bytes (scalar+scalar)
- FAIL    1010 010- -010 ---- 001- ---- ---- ----   # SVE load & replicate 32 bytes (scalar+imm)
- FAIL    1100 010- ---- ---- ---- ---- ---- ----   # SVE 64-bit gather load/prefetch
--FAIL    1110 010- -00- ---- 001- ---- ---- ----   # SVE2 64-bit scatter NT store (vector+scalar)
--FAIL    1110 010- -10- ---- 001- ---- ---- ----   # SVE2 32-bit scatter NT store (vector+scalar)
--FAIL    1110 010- ---- ---- 1-0- ---- ---- ----   # SVE scatter store (scalar+32-bit vector)
--FAIL    1110 010- ---- ---- 101- ---- ---- ----   # SVE scatter store (misc)
-diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
-index XXXXXXX..XXXXXXX 100644
---- a/target/arm/translate-sve.c
-+++ b/target/arm/translate-sve.c
-@@ -XXX,XX +XXX,XX @@ static bool trans_LD1_zprz(DisasContext *s, arg_LD1_zprz *a)
-     if (!dc_isar_feature(aa64_sve, s)) {
-         return false;
-     }
-+    s->is_nonstreaming = true;
-     if (!sve_access_check(s)) {
-         return true;
-     }
-@@ -XXX,XX +XXX,XX @@ static bool trans_LD1_zpiz(DisasContext *s, arg_LD1_zpiz *a)
-     if (!dc_isar_feature(aa64_sve, s)) {
-         return false;
-     }
-+    s->is_nonstreaming = true;
-     if (!sve_access_check(s)) {
-         return true;
-     }
-@@ -XXX,XX +XXX,XX @@ static bool trans_LDNT1_zprz(DisasContext *s, arg_LD1_zprz *a)
-     if (!dc_isar_feature(aa64_sve2, s)) {
-         return false;
-     }
-+    s->is_nonstreaming = true;
-     if (!sve_access_check(s)) {
-         return true;
-     }
-@@ -XXX,XX +XXX,XX @@ static bool trans_ST1_zprz(DisasContext *s, arg_ST1_zprz *a)
-     if (!dc_isar_feature(aa64_sve, s)) {
-         return false;
-     }
-+    s->is_nonstreaming = true;
-     if (!sve_access_check(s)) {
-         return true;
-     }
-@@ -XXX,XX +XXX,XX @@ static bool trans_ST1_zpiz(DisasContext *s, arg_ST1_zpiz *a)
-     if (!dc_isar_feature(aa64_sve, s)) {
-         return false;
-     }
-+    s->is_nonstreaming = true;
-     if (!sve_access_check(s)) {
-         return true;
-     }
-@@ -XXX,XX +XXX,XX @@ static bool trans_STNT1_zprz(DisasContext *s, arg_ST1_zprz *a)
-     if (!dc_isar_feature(aa64_sve2, s)) {
-         return false;
-     }
-+    s->is_nonstreaming = true;
-     if (!sve_access_check(s)) {
-         return true;
-     }
---
-.25.1

-[PULL 12/45] target/arm: Mark gather prefetch as non-streaming
+Deleted patch
-From: Richard Henderson <richard.henderson@linaro.org>
-Mark these as a non-streaming instructions, which should trap if full
-a64 support is not enabled in streaming mode.  In this case, introduce
-PRF_ns (prefetch non-streaming) to handle the checks.
-Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
-Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
-Message-id: 20220708151540.18136-13-richard.henderson@linaro.org
-Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
----
- target/arm/sme-fa64.decode |  3 ---
- target/arm/sve.decode      | 10 +++++-----
- target/arm/translate-sve.c | 11 +++++++++++
-files changed, 16 insertions(+), 8 deletions(-)
-diff --git a/target/arm/sme-fa64.decode b/target/arm/sme-fa64.decode
-index XXXXXXX..XXXXXXX 100644
---- a/target/arm/sme-fa64.decode
-+++ b/target/arm/sme-fa64.decode
-@@ -XXX,XX +XXX,XX @@ FAIL    0001 1110 0111 1110 0000 00-- ---- ----   # FJCVTZS
- #       --11 1100 --1- ---- ---- ---- ---- --10   # Load/store FP register (register offset)
- #       --11 1101 ---- ---- ---- ---- ---- ----   # Load/store FP register (scaled imm)
--FAIL    1000 010- -00- ---- 111- ---- ---- ----   # SVE 32-bit gather prefetch (vector+imm)
--FAIL    1000 0100 0-1- ---- 0--- ---- ---- ----   # SVE 32-bit gather prefetch (scalar+vector)
- FAIL    1010 010- ---- ---- 011- ---- ---- ----   # SVE contiguous FF load (scalar+scalar)
- FAIL    1010 010- ---1 ---- 101- ---- ---- ----   # SVE contiguous NF load (scalar+imm)
- FAIL    1010 010- -01- ---- 000- ---- ---- ----   # SVE load & replicate 32 bytes (scalar+scalar)
- FAIL    1010 010- -010 ---- 001- ---- ---- ----   # SVE load & replicate 32 bytes (scalar+imm)
--FAIL    1100 010- ---- ---- ---- ---- ---- ----   # SVE 64-bit gather load/prefetch
-diff --git a/target/arm/sve.decode b/target/arm/sve.decode
-index XXXXXXX..XXXXXXX 100644
---- a/target/arm/sve.decode
-+++ b/target/arm/sve.decode
-@@ -XXX,XX +XXX,XX @@ LD1RO_zpri      1010010 .. 01 0.... 001 ... ..... ..... \
-                 @rpri_load_msz nreg=0
- # SVE 32-bit gather prefetch (scalar plus 32-bit scaled offsets)
--PRF             1000010 00 -1 ----- 0-- --- ----- 0 ----
-+PRF_ns          1000010 00 -1 ----- 0-- --- ----- 0 ----
- # SVE 32-bit gather prefetch (vector plus immediate)
--PRF             1000010 -- 00 ----- 111 --- ----- 0 ----
-+PRF_ns          1000010 -- 00 ----- 111 --- ----- 0 ----
- # SVE contiguous prefetch (scalar plus immediate)
- PRF             1000010 11 1- ----- 0-- --- ----- 0 ----
-@@ -XXX,XX +XXX,XX @@ LD1_zpiz        1100010 .. 01 ..... 1.. ... ..... ..... \
-                 @rpri_g_load esz=3
- # SVE 64-bit gather prefetch (scalar plus 64-bit scaled offsets)
--PRF             1100010 00 11 ----- 1-- --- ----- 0 ----
-+PRF_ns          1100010 00 11 ----- 1-- --- ----- 0 ----
- # SVE 64-bit gather prefetch (scalar plus unpacked 32-bit scaled offsets)
--PRF             1100010 00 -1 ----- 0-- --- ----- 0 ----
-+PRF_ns          1100010 00 -1 ----- 0-- --- ----- 0 ----
- # SVE 64-bit gather prefetch (vector plus immediate)
--PRF             1100010 -- 00 ----- 111 --- ----- 0 ----
-+PRF_ns          1100010 -- 00 ----- 111 --- ----- 0 ----
- ### SVE Memory Store Group
-diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
-index XXXXXXX..XXXXXXX 100644
---- a/target/arm/translate-sve.c
-+++ b/target/arm/translate-sve.c
-@@ -XXX,XX +XXX,XX @@ static bool trans_PRF_rr(DisasContext *s, arg_PRF_rr *a)
-     return true;
- }
-+static bool trans_PRF_ns(DisasContext *s, arg_PRF_ns *a)
-+{
-+    if (!dc_isar_feature(aa64_sve, s)) {
-+        return false;
-+    }
-+    /* Prefetch is a nop within QEMU.  */
-+    s->is_nonstreaming = true;
-+    (void)sve_access_check(s);
-+    return true;
-+}
-+
- /*
-  * Move Prefix
-  *
---
-.25.1

-[PULL 13/45] target/arm: Mark LDFF1 and LDNF1 as non-streaming
+Deleted patch
-From: Richard Henderson <richard.henderson@linaro.org>
-Mark these as a non-streaming instructions, which should trap
-if full a64 support is not enabled in streaming mode.
-Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
-Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
-Message-id: 20220708151540.18136-14-richard.henderson@linaro.org
-Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
----
- target/arm/sme-fa64.decode | 2 --
- target/arm/translate-sve.c | 2 ++
-files changed, 2 insertions(+), 2 deletions(-)
-diff --git a/target/arm/sme-fa64.decode b/target/arm/sme-fa64.decode
-index XXXXXXX..XXXXXXX 100644
---- a/target/arm/sme-fa64.decode
-+++ b/target/arm/sme-fa64.decode
-@@ -XXX,XX +XXX,XX @@ FAIL    0001 1110 0111 1110 0000 00-- ---- ----   # FJCVTZS
- #       --11 1100 --1- ---- ---- ---- ---- --10   # Load/store FP register (register offset)
- #       --11 1101 ---- ---- ---- ---- ---- ----   # Load/store FP register (scaled imm)
--FAIL    1010 010- ---- ---- 011- ---- ---- ----   # SVE contiguous FF load (scalar+scalar)
--FAIL    1010 010- ---1 ---- 101- ---- ---- ----   # SVE contiguous NF load (scalar+imm)
- FAIL    1010 010- -01- ---- 000- ---- ---- ----   # SVE load & replicate 32 bytes (scalar+scalar)
- FAIL    1010 010- -010 ---- 001- ---- ---- ----   # SVE load & replicate 32 bytes (scalar+imm)
-diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
-index XXXXXXX..XXXXXXX 100644
---- a/target/arm/translate-sve.c
-+++ b/target/arm/translate-sve.c
-@@ -XXX,XX +XXX,XX @@ static bool trans_LDFF1_zprr(DisasContext *s, arg_rprr_load *a)
-     if (!dc_isar_feature(aa64_sve, s)) {
-         return false;
-     }
-+    s->is_nonstreaming = true;
-     if (sve_access_check(s)) {
-         TCGv_i64 addr = new_tmp_a64(s);
-         tcg_gen_shli_i64(addr, cpu_reg(s, a->rm), dtype_msz(a->dtype));
-@@ -XXX,XX +XXX,XX @@ static bool trans_LDNF1_zpri(DisasContext *s, arg_rpri_load *a)
-     if (!dc_isar_feature(aa64_sve, s)) {
-         return false;
-     }
-+    s->is_nonstreaming = true;
-     if (sve_access_check(s)) {
-         int vsz = vec_full_reg_size(s);
-         int elements = vsz >> dtype_esz[a->dtype];
---
-.25.1

-[PULL 14/45] target/arm: Mark LD1RO as non-streaming
+Deleted patch
-From: Richard Henderson <richard.henderson@linaro.org>
-Mark these as a non-streaming instructions, which should trap
-if full a64 support is not enabled in streaming mode.
-Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
-Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
-Message-id: 20220708151540.18136-15-richard.henderson@linaro.org
-Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
----
- target/arm/sme-fa64.decode | 3 ---
- target/arm/translate-sve.c | 2 ++
-files changed, 2 insertions(+), 3 deletions(-)
-diff --git a/target/arm/sme-fa64.decode b/target/arm/sme-fa64.decode
-index XXXXXXX..XXXXXXX 100644
---- a/target/arm/sme-fa64.decode
-+++ b/target/arm/sme-fa64.decode
-@@ -XXX,XX +XXX,XX @@ FAIL    0001 1110 0111 1110 0000 00-- ---- ----   # FJCVTZS
- #       --11 1100 --0- ---- ---- ---- ---- ----   # Load/store FP register (unscaled imm)
- #       --11 1100 --1- ---- ---- ---- ---- --10   # Load/store FP register (register offset)
- #       --11 1101 ---- ---- ---- ---- ---- ----   # Load/store FP register (scaled imm)
--
--FAIL    1010 010- -01- ---- 000- ---- ---- ----   # SVE load & replicate 32 bytes (scalar+scalar)
--FAIL    1010 010- -010 ---- 001- ---- ---- ----   # SVE load & replicate 32 bytes (scalar+imm)
-diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
-index XXXXXXX..XXXXXXX 100644
---- a/target/arm/translate-sve.c
-+++ b/target/arm/translate-sve.c
-@@ -XXX,XX +XXX,XX @@ static bool trans_LD1RO_zprr(DisasContext *s, arg_rprr_load *a)
-     if (a->rm == 31) {
-         return false;
-     }
-+    s->is_nonstreaming = true;
-     if (sve_access_check(s)) {
-         TCGv_i64 addr = new_tmp_a64(s);
-         tcg_gen_shli_i64(addr, cpu_reg(s, a->rm), dtype_msz(a->dtype));
-@@ -XXX,XX +XXX,XX @@ static bool trans_LD1RO_zpri(DisasContext *s, arg_rpri_load *a)
-     if (!dc_isar_feature(aa64_sve_f64mm, s)) {
-         return false;
-     }
-+    s->is_nonstreaming = true;
-     if (sve_access_check(s)) {
-         TCGv_i64 addr = new_tmp_a64(s);
-         tcg_gen_addi_i64(addr, cpu_reg_sp(s, a->rn), a->imm * 32);
---
-.25.1

-[PULL 15/45] target/arm: Add SME enablement checks
+Deleted patch
-From: Richard Henderson <richard.henderson@linaro.org>
-These functions will be used to verify that the cpu
-is in the correct state for a given instruction.
-Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
-Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
-Message-id: 20220708151540.18136-16-richard.henderson@linaro.org
-Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
----
- target/arm/translate-a64.h | 21 +++++++++++++++++++++
- target/arm/translate-a64.c | 34 ++++++++++++++++++++++++++++++++++
-files changed, 55 insertions(+)
-diff --git a/target/arm/translate-a64.h b/target/arm/translate-a64.h
-index XXXXXXX..XXXXXXX 100644
---- a/target/arm/translate-a64.h
-+++ b/target/arm/translate-a64.h
-@@ -XXX,XX +XXX,XX @@ void write_fp_dreg(DisasContext *s, int reg, TCGv_i64 v);
- bool logic_imm_decode_wmask(uint64_t *result, unsigned int immn,
-                             unsigned int imms, unsigned int immr);
- bool sve_access_check(DisasContext *s);
-+bool sme_enabled_check(DisasContext *s);
-+bool sme_enabled_check_with_svcr(DisasContext *s, unsigned);
-+
-+/* This function corresponds to CheckStreamingSVEEnabled. */
-+static inline bool sme_sm_enabled_check(DisasContext *s)
-+{
-+    return sme_enabled_check_with_svcr(s, R_SVCR_SM_MASK);
-+}
-+
-+/* This function corresponds to CheckSMEAndZAEnabled. */
-+static inline bool sme_za_enabled_check(DisasContext *s)
-+{
-+    return sme_enabled_check_with_svcr(s, R_SVCR_ZA_MASK);
-+}
-+
-+/* Note that this function corresponds to CheckStreamingSVEAndZAEnabled. */
-+static inline bool sme_smza_enabled_check(DisasContext *s)
-+{
-+    return sme_enabled_check_with_svcr(s, R_SVCR_SM_MASK | R_SVCR_ZA_MASK);
-+}
-+
- TCGv_i64 clean_data_tbi(DisasContext *s, TCGv_i64 addr);
- TCGv_i64 gen_mte_check1(DisasContext *s, TCGv_i64 addr, bool is_write,
-                         bool tag_checked, int log2_size);
-diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
-index XXXXXXX..XXXXXXX 100644
---- a/target/arm/translate-a64.c
-+++ b/target/arm/translate-a64.c
-@@ -XXX,XX +XXX,XX @@ static bool sme_access_check(DisasContext *s)
-     return true;
- }
-+/* This function corresponds to CheckSMEEnabled. */
-+bool sme_enabled_check(DisasContext *s)
-+{
-+    /*
-+     * Note that unlike sve_excp_el, we have not constrained sme_excp_el
-+     * to be zero when fp_excp_el has priority.  This is because we need
-+     * sme_excp_el by itself for cpregs access checks.
-+     */
-+    if (!s->fp_excp_el || s->sme_excp_el < s->fp_excp_el) {
-+        s->fp_access_checked = true;
-+        return sme_access_check(s);
-+    }
-+    return fp_access_check_only(s);
-+}
-+
-+/* Common subroutine for CheckSMEAnd*Enabled. */
-+bool sme_enabled_check_with_svcr(DisasContext *s, unsigned req)
-+{
-+    if (!sme_enabled_check(s)) {
-+        return false;
-+    }
-+    if (FIELD_EX64(req, SVCR, SM) && !s->pstate_sm) {
-+        gen_exception_insn(s, s->pc_curr, EXCP_UDEF,
-+                           syn_smetrap(SME_ET_NotStreaming, false));
-+        return false;
-+    }
-+    if (FIELD_EX64(req, SVCR, ZA) && !s->pstate_za) {
-+        gen_exception_insn(s, s->pc_curr, EXCP_UDEF,
-+                           syn_smetrap(SME_ET_InactiveZA, false));
-+        return false;
-+    }
-+    return true;
-+}
-+
- /*
-  * This utility function is for doing register extension with an
-  * optional shift. You will likely want to pass a temporary for the
---
-.25.1

-[PULL 16/45] target/arm: Handle SME in sve_access_check
+Deleted patch
-From: Richard Henderson <richard.henderson@linaro.org>
-The pseudocode for CheckSVEEnabled gains a check for Streaming
-SVE mode, and for SME present but SVE absent.
-Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
-Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
-Message-id: 20220708151540.18136-17-richard.henderson@linaro.org
-Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
----
- target/arm/translate-a64.c | 22 ++++++++++++++++------
-file changed, 16 insertions(+), 6 deletions(-)
-diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
-index XXXXXXX..XXXXXXX 100644
---- a/target/arm/translate-a64.c
-+++ b/target/arm/translate-a64.c
-@@ -XXX,XX +XXX,XX @@ static bool fp_access_check(DisasContext *s)
-     return true;
- }
--/* Check that SVE access is enabled.  If it is, return true.
-+/*
-+ * Check that SVE access is enabled.  If it is, return true.
-  * If not, emit code to generate an appropriate exception and return false.
-+ * This function corresponds to CheckSVEEnabled().
-  */
- bool sve_access_check(DisasContext *s)
- {
--    if (s->sve_excp_el) {
--        assert(!s->sve_access_checked);
--        s->sve_access_checked = true;
--
-+    if (s->pstate_sm || !dc_isar_feature(aa64_sve, s)) {
-+        assert(dc_isar_feature(aa64_sme, s));
-+        if (!sme_sm_enabled_check(s)) {
-+            goto fail_exit;
-+        }
-+    } else if (s->sve_excp_el) {
-         gen_exception_insn_el(s, s->pc_curr, EXCP_UDEF,
-                               syn_sve_access_trap(), s->sve_excp_el);
--        return false;
-+        goto fail_exit;
-     }
-     s->sve_access_checked = true;
-     return fp_access_check(s);
-+
-+ fail_exit:
-+    /* Assert that we only raise one exception per instruction. */
-+    assert(!s->sve_access_checked);
-+    s->sve_access_checked = true;
-+    return false;
- }
- /*
---
-.25.1

-[PULL 17/45] target/arm: Implement SME RDSVL, ADDSVL, ADDSPL
+Deleted patch
-From: Richard Henderson <richard.henderson@linaro.org>
-These SME instructions are nominally within the SVE decode space,
-so we add them to sve.decode and translate-sve.c.
-Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
-Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
-Message-id: 20220708151540.18136-18-richard.henderson@linaro.org
-Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
----
- target/arm/translate-a64.h | 12 ++++++++++++
- target/arm/sve.decode      |  5 ++++-
- target/arm/translate-sve.c | 38 ++++++++++++++++++++++++++++++++++++++
-files changed, 54 insertions(+), 1 deletion(-)
-diff --git a/target/arm/translate-a64.h b/target/arm/translate-a64.h
-index XXXXXXX..XXXXXXX 100644
---- a/target/arm/translate-a64.h
-+++ b/target/arm/translate-a64.h
-@@ -XXX,XX +XXX,XX @@ static inline int vec_full_reg_size(DisasContext *s)
-     return s->vl;
- }
-+/* Return the byte size of the vector register, SVL / 8. */
-+static inline int streaming_vec_reg_size(DisasContext *s)
-+{
-+    return s->svl;
-+}
-+
- /*
-  * Return the offset info CPUARMState of the predicate vector register Pn.
-  * Note for this purpose, FFR is P16.
-@@ -XXX,XX +XXX,XX @@ static inline int pred_full_reg_size(DisasContext *s)
-     return s->vl >> 3;
- }
-+/* Return the byte size of the predicate register, SVL / 64.  */
-+static inline int streaming_pred_reg_size(DisasContext *s)
-+{
-+    return s->svl >> 3;
-+}
-+
- /*
-  * Round up the size of a register to a size allowed by
-  * the tcg vector infrastructure.  Any operation which uses this
-diff --git a/target/arm/sve.decode b/target/arm/sve.decode
-index XXXXXXX..XXXXXXX 100644
---- a/target/arm/sve.decode
-+++ b/target/arm/sve.decode
-@@ -XXX,XX +XXX,XX @@ INDEX_ri        00000100 esz:2 1 imm:s5 010001 rn:5 rd:5
- # SVE index generation (register start, register increment)
- INDEX_rr        00000100 .. 1 ..... 010011 ..... .....          @rd_rn_rm
--### SVE Stack Allocation Group
-+### SVE / Streaming SVE Stack Allocation Group
- # SVE stack frame adjustment
- ADDVL           00000100 001 ..... 01010 ...... .....           @rd_rn_i6
-+ADDSVL          00000100 001 ..... 01011 ...... .....           @rd_rn_i6
- ADDPL           00000100 011 ..... 01010 ...... .....           @rd_rn_i6
-+ADDSPL          00000100 011 ..... 01011 ...... .....           @rd_rn_i6
- # SVE stack frame size
- RDVL            00000100 101 11111 01010 imm:s6 rd:5
-+RDSVL           00000100 101 11111 01011 imm:s6 rd:5
- ### SVE Bitwise Shift - Unpredicated Group
-diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
-index XXXXXXX..XXXXXXX 100644
---- a/target/arm/translate-sve.c
-+++ b/target/arm/translate-sve.c
-@@ -XXX,XX +XXX,XX @@ static bool trans_ADDVL(DisasContext *s, arg_ADDVL *a)
-     return true;
- }
-+static bool trans_ADDSVL(DisasContext *s, arg_ADDSVL *a)
-+{
-+    if (!dc_isar_feature(aa64_sme, s)) {
-+        return false;
-+    }
-+    if (sme_enabled_check(s)) {
-+        TCGv_i64 rd = cpu_reg_sp(s, a->rd);
-+        TCGv_i64 rn = cpu_reg_sp(s, a->rn);
-+        tcg_gen_addi_i64(rd, rn, a->imm * streaming_vec_reg_size(s));
-+    }
-+    return true;
-+}
-+
- static bool trans_ADDPL(DisasContext *s, arg_ADDPL *a)
- {
-     if (!dc_isar_feature(aa64_sve, s)) {
-@@ -XXX,XX +XXX,XX @@ static bool trans_ADDPL(DisasContext *s, arg_ADDPL *a)
-     return true;
- }
-+static bool trans_ADDSPL(DisasContext *s, arg_ADDSPL *a)
-+{
-+    if (!dc_isar_feature(aa64_sme, s)) {
-+        return false;
-+    }
-+    if (sme_enabled_check(s)) {
-+        TCGv_i64 rd = cpu_reg_sp(s, a->rd);
-+        TCGv_i64 rn = cpu_reg_sp(s, a->rn);
-+        tcg_gen_addi_i64(rd, rn, a->imm * streaming_pred_reg_size(s));
-+    }
-+    return true;
-+}
-+
- static bool trans_RDVL(DisasContext *s, arg_RDVL *a)
- {
-     if (!dc_isar_feature(aa64_sve, s)) {
-@@ -XXX,XX +XXX,XX @@ static bool trans_RDVL(DisasContext *s, arg_RDVL *a)
-     return true;
- }
-+static bool trans_RDSVL(DisasContext *s, arg_RDSVL *a)
-+{
-+    if (!dc_isar_feature(aa64_sme, s)) {
-+        return false;
-+    }
-+    if (sme_enabled_check(s)) {
-+        TCGv_i64 reg = cpu_reg(s, a->rd);
-+        tcg_gen_movi_i64(reg, a->imm * streaming_vec_reg_size(s));
-+    }
-+    return true;
-+}
-+
- /*
-  *** SVE Compute Vector Address Group
-  */
---
-.25.1

-[PULL 18/45] target/arm: Implement SME ZERO
+Deleted patch
-From: Richard Henderson <richard.henderson@linaro.org>
-Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
-Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
-Message-id: 20220708151540.18136-19-richard.henderson@linaro.org
-Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
----
- target/arm/helper-sme.h    |  2 ++
- target/arm/sme.decode      |  4 ++++
- target/arm/sme_helper.c    | 25 +++++++++++++++++++++++++
- target/arm/translate-sme.c | 13 +++++++++++++
-files changed, 44 insertions(+)
-diff --git a/target/arm/helper-sme.h b/target/arm/helper-sme.h
-index XXXXXXX..XXXXXXX 100644
---- a/target/arm/helper-sme.h
-+++ b/target/arm/helper-sme.h
-@@ -XXX,XX +XXX,XX @@
- DEF_HELPER_FLAGS_2(set_pstate_sm, TCG_CALL_NO_RWG, void, env, i32)
- DEF_HELPER_FLAGS_2(set_pstate_za, TCG_CALL_NO_RWG, void, env, i32)
-+
-+DEF_HELPER_FLAGS_3(sme_zero, TCG_CALL_NO_RWG, void, env, i32, i32)
-diff --git a/target/arm/sme.decode b/target/arm/sme.decode
-index XXXXXXX..XXXXXXX 100644
---- a/target/arm/sme.decode
-+++ b/target/arm/sme.decode
-@@ -XXX,XX +XXX,XX @@
- #
- # This file is processed by scripts/decodetree.py
- #
-+
-+### SME Misc
-+
-+ZERO            11000000 00 001 00000000000 imm:8
-diff --git a/target/arm/sme_helper.c b/target/arm/sme_helper.c
-index XXXXXXX..XXXXXXX 100644
---- a/target/arm/sme_helper.c
-+++ b/target/arm/sme_helper.c
-@@ -XXX,XX +XXX,XX @@ void helper_set_pstate_za(CPUARMState *env, uint32_t i)
-         memset(env->zarray, 0, sizeof(env->zarray));
-     }
- }
-+
-+void helper_sme_zero(CPUARMState *env, uint32_t imm, uint32_t svl)
-+{
-+    uint32_t i;
-+
-+    /*
-+     * Special case clearing the entire ZA space.
-+     * This falls into the CONSTRAINED UNPREDICTABLE zeroing of any
-+     * parts of the ZA storage outside of SVL.
-+     */
-+    if (imm == 0xff) {
-+        memset(env->zarray, 0, sizeof(env->zarray));
-+        return;
-+    }
-+
-+    /*
-+     * Recall that ZAnH.D[m] is spread across ZA[n+8*m],
-+     * so each row is discontiguous within ZA[].
-+     */
-+    for (i = 0; i < svl; i++) {
-+        if (imm & (1 << (i % 8))) {
-+            memset(&env->zarray[i], 0, svl);
-+        }
-+    }
-+}
-diff --git a/target/arm/translate-sme.c b/target/arm/translate-sme.c
-index XXXXXXX..XXXXXXX 100644
---- a/target/arm/translate-sme.c
-+++ b/target/arm/translate-sme.c
-@@ -XXX,XX +XXX,XX @@
-  */
- #include "decode-sme.c.inc"
-+
-+
-+static bool trans_ZERO(DisasContext *s, arg_ZERO *a)
-+{
-+    if (!dc_isar_feature(aa64_sme, s)) {
-+        return false;
-+    }
-+    if (sme_za_enabled_check(s)) {
-+        gen_helper_sme_zero(cpu_env, tcg_constant_i32(a->imm),
-+                            tcg_constant_i32(streaming_vec_reg_size(s)));
-+    }
-+    return true;
-+}
---
-.25.1

-[PULL 34/45] linux-user/aarch64: Reset PSTATE.SM on syscalls
+[PULL 17/24] target/arm: Catch illegal-exception-return from EL3 with bad NSE/NS
-From: Richard Henderson <richard.henderson@linaro.org>
+The architecture requires (R_TYTWB) that an attempt to return from EL3
 when SCR_EL3.{NSE,NS} are {1,0} is an illegal exception return. (This
 enforces that the CPU can't ever be executing below EL3 with the
 NSE,NS bits indicating an invalid security state.)
-Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
+We were missing this check; add it.
-Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
 Message-id: 20220708151540.18136-35-richard.henderson@linaro.org
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
+Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
+Message-id: 20230807150618.101357-1-peter.maydell@linaro.org
 ---
- linux-user/aarch64/cpu_loop.c | 9 +++++++++
+ target/arm/tcg/helper-a64.c | 9 +++++++++
 file changed, 9 insertions(+)
-diff --git a/linux-user/aarch64/cpu_loop.c b/linux-user/aarch64/cpu_loop.c
+diff --git a/target/arm/tcg/helper-a64.c b/target/arm/tcg/helper-a64.c
 index XXXXXXX..XXXXXXX 100644
---- a/linux-user/aarch64/cpu_loop.c
+--- a/target/arm/tcg/helper-a64.c
-+++ b/linux-user/aarch64/cpu_loop.c
++++ b/target/arm/tcg/helper-a64.c
-@@ -XXX,XX +XXX,XX @@ void cpu_loop(CPUARMState *env)
+@@ -XXX,XX +XXX,XX @@ void HELPER(exception_return)(CPUARMState *env, uint64_t new_pc)
+         spsr &= ~PSTATE_SS;
-         switch (trapnr) {
+     }
-         case EXCP_SWI:
-+            /*
++    /*
-+             * On syscall, PSTATE.ZA is preserved, along with the ZA matrix.
++     * FEAT_RME forbids return from EL3 with an invalid security state.
-+             * PSTATE.SM is cleared, per SMSTOP, which does ResetSVEState.
++     * We don't need an explicit check for FEAT_RME here because we enforce
-+             */
++     * in scr_write() that you can't set the NSE bit without it.
-+            if (FIELD_EX64(env->svcr, SVCR, SM)) {
++     */
-+                env->svcr = FIELD_DP64(env->svcr, SVCR, SM, 0);
++    if (cur_el == 3 && (env->cp15.scr_el3 & (SCR_NS | SCR_NSE)) == SCR_NSE) {
-+                arm_rebuild_hflags(env);
++        goto illegal_return;
-+                arm_reset_sve_state(env);
++    }
-+            }
++
-             ret = do_syscall(env,
+     new_el = el_from_spsr(spsr);
-                              env->xregs[8],
+     if (new_el == -1) {
-                              env->xregs[0],
+         goto illegal_return;
 --
-.25.1
+.34.1

-[PULL 37/45] linux-user/aarch64: Do not allow duplicate or short sve records
+[PULL 18/24] hw/rtc/m48t59: Use 64-bit arithmetic in set_alarm()
-From: Richard Henderson <richard.henderson@linaro.org>
+In the m48t59 device we almost always use 64-bit arithmetic when
 dealing with time_t deltas.  The one exception is in set_alarm(),
 which currently uses a plain 'int' to hold the difference between two
 time_t values.  Switch to int64_t instead to avoid any possible
 overflow issues.
-In parse_user_sigframe, the kernel rejects duplicate sve records,
+Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
-or records that are smaller than the header.  We were silently
+Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
-allowing these cases to pass, dropping the record.
+---
  hw/rtc/m48t59.c | 2 +-
 file changed, 1 insertion(+), 1 deletion(-)
-Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
+diff --git a/hw/rtc/m48t59.c b/hw/rtc/m48t59.c
-Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
+index XXXXXXX..XXXXXXX 100644
-Message-id: 20220708151540.18136-38-richard.henderson@linaro.org
+--- a/hw/rtc/m48t59.c
-Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
++++ b/hw/rtc/m48t59.c
----
+@@ -XXX,XX +XXX,XX @@ static void alarm_cb (void *opaque)
- linux-user/aarch64/signal.c | 5 ++++-
-file changed, 4 insertions(+), 1 deletion(-)
+ static void set_alarm(M48t59State *NVRAM)
  {
 -    int diff;
 +    int64_t diff;
      if (NVRAM->alrm_timer != NULL) {
          timer_del(NVRAM->alrm_timer);
          diff = qemu_timedate_diff(&NVRAM->alarm) - NVRAM->time_offset;
 --
 .34.1
-diff --git a/linux-user/aarch64/signal.c b/linux-user/aarch64/signal.c
 index XXXXXXX..XXXXXXX 100644
 --- a/linux-user/aarch64/signal.c
 +++ b/linux-user/aarch64/signal.c
@@ -XXX,XX +XXX,XX @@ static int target_restore_sigframe(CPUARMState *env,
              break;
          case TARGET_SVE_MAGIC:
 +            if (sve || size < sizeof(struct target_sve_context)) {
 +                goto err;
 +            }
              if (cpu_isar_feature(aa64_sve, env_archcpu(env))) {
                  vq = sve_vq(env);
                  sve_size = QEMU_ALIGN_UP(TARGET_SVE_SIG_CONTEXT_SIZE(vq), 16);
 -                if (!sve && size == sve_size) {
 +                if (size == sve_size) {
                      sve = (struct target_sve_context *)ctx;
                      break;
                  }
 --
 .25.1

-[PULL 33/45] linux-user/aarch64: Clear tpidr2_el0 if CLONE_SETTLS
+[PULL 19/24] hw/rtc/twl92230: Use int64_t for sec_offset and alm_sec
-From: Richard Henderson <richard.henderson@linaro.org>
+In the twl92230 device, use int64_t for the two state fields
 sec_offset and alm_sec, because we set these to values that
 are either time_t or differences between two time_t values.
-Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
+These fields aren't saved in vmstate anywhere, so we can
-Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
+safely widen them.
-Message-id: 20220708151540.18136-34-richard.henderson@linaro.org
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
+Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
 ---
- linux-user/aarch64/target_cpu.h | 5 ++++-
+ hw/rtc/twl92230.c | 4 ++--
-file changed, 4 insertions(+), 1 deletion(-)
+file changed, 2 insertions(+), 2 deletions(-)
-diff --git a/linux-user/aarch64/target_cpu.h b/linux-user/aarch64/target_cpu.h
+diff --git a/hw/rtc/twl92230.c b/hw/rtc/twl92230.c
 index XXXXXXX..XXXXXXX 100644
---- a/linux-user/aarch64/target_cpu.h
+--- a/hw/rtc/twl92230.c
-+++ b/linux-user/aarch64/target_cpu.h
++++ b/hw/rtc/twl92230.c
-@@ -XXX,XX +XXX,XX @@ static inline void cpu_clone_regs_parent(CPUARMState *env, unsigned flags)
+@@ -XXX,XX +XXX,XX @@ struct MenelausState {
+         struct tm tm;
- static inline void cpu_set_tls(CPUARMState *env, target_ulong newtls)
+         struct tm new;
- {
+         struct tm alm;
--    /* Note that AArch64 Linux keeps the TLS pointer in TPIDR; this is
+-        int sec_offset;
-+    /*
+-        int alm_sec;
-+     * Note that AArch64 Linux keeps the TLS pointer in TPIDR; this is
++        int64_t sec_offset;
-      * different from AArch32 Linux, which uses TPIDRRO.
++        int64_t alm_sec;
-      */
+         int next_comp;
-     env->cp15.tpidr_el[0] = newtls;
+     } rtc;
-+    /* TPIDR2_EL0 is cleared with CLONE_SETTLS. */
+     uint16_t rtc_next_vmstate;
 +    env->cp15.tpidr2_el0 = 0;
  }
  static inline abi_ulong get_sp_from_cpustate(CPUARMState *state)
 --
-.25.1
+.34.1

-[PULL 45/45] linux-user/aarch64: Add SME related hwcap entries
+[PULL 20/24] hw/rtc/aspeed_rtc: Use 64-bit offset for holding time_t difference
-From: Richard Henderson <richard.henderson@linaro.org>
+In the aspeed_rtc device we store a difference between two time_t
 values in an 'int'. This is not really correct when time_t could
 be 64 bits. Enlarge the field to 'int64_t'.
-Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
+This is a migration compatibility break for the aspeed boards.
-Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
+While we are changing the vmstate, remove the accidental
-Message-id: 20220708151540.18136-46-richard.henderson@linaro.org
+duplicate of the offset field.
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
+Reviewed-by: Cédric Le Goater <clg@kaod.org>
 ---
- linux-user/elfload.c | 20 ++++++++++++++++++++
+ include/hw/rtc/aspeed_rtc.h | 2 +-
-file changed, 20 insertions(+)
+ hw/rtc/aspeed_rtc.c         | 5 ++---
 files changed, 3 insertions(+), 4 deletions(-)
-diff --git a/linux-user/elfload.c b/linux-user/elfload.c
+diff --git a/include/hw/rtc/aspeed_rtc.h b/include/hw/rtc/aspeed_rtc.h
 index XXXXXXX..XXXXXXX 100644
---- a/linux-user/elfload.c
+--- a/include/hw/rtc/aspeed_rtc.h
-+++ b/linux-user/elfload.c
++++ b/include/hw/rtc/aspeed_rtc.h
-@@ -XXX,XX +XXX,XX @@ enum {
+@@ -XXX,XX +XXX,XX @@ struct AspeedRtcState {
-     ARM_HWCAP2_A64_RNG          = 1 << 16,
+     qemu_irq irq;
-     ARM_HWCAP2_A64_BTI          = 1 << 17,
-     ARM_HWCAP2_A64_MTE          = 1 << 18,
+     uint32_t reg[0x18];
-+    ARM_HWCAP2_A64_ECV          = 1 << 19,
+-    int offset;
-+    ARM_HWCAP2_A64_AFP          = 1 << 20,
++    int64_t offset;
-+    ARM_HWCAP2_A64_RPRES        = 1 << 21,
 +    ARM_HWCAP2_A64_MTE3         = 1 << 22,
 +    ARM_HWCAP2_A64_SME          = 1 << 23,
 +    ARM_HWCAP2_A64_SME_I16I64   = 1 << 24,
 +    ARM_HWCAP2_A64_SME_F64F64   = 1 << 25,
 +    ARM_HWCAP2_A64_SME_I8I32    = 1 << 26,
 +    ARM_HWCAP2_A64_SME_F16F32   = 1 << 27,
 +    ARM_HWCAP2_A64_SME_B16F32   = 1 << 28,
 +    ARM_HWCAP2_A64_SME_F32F32   = 1 << 29,
 +    ARM_HWCAP2_A64_SME_FA64     = 1 << 30,
  };
- #define ELF_HWCAP   get_elf_hwcap()
+diff --git a/hw/rtc/aspeed_rtc.c b/hw/rtc/aspeed_rtc.c
-@@ -XXX,XX +XXX,XX @@ static uint32_t get_elf_hwcap2(void)
+index XXXXXXX..XXXXXXX 100644
-     GET_FEATURE_ID(aa64_rndr, ARM_HWCAP2_A64_RNG);
+--- a/hw/rtc/aspeed_rtc.c
-     GET_FEATURE_ID(aa64_bti, ARM_HWCAP2_A64_BTI);
++++ b/hw/rtc/aspeed_rtc.c
-     GET_FEATURE_ID(aa64_mte, ARM_HWCAP2_A64_MTE);
+@@ -XXX,XX +XXX,XX @@ static const MemoryRegionOps aspeed_rtc_ops = {
-+    GET_FEATURE_ID(aa64_sme, (ARM_HWCAP2_A64_SME |
-+                              ARM_HWCAP2_A64_SME_F32F32 |
+ static const VMStateDescription vmstate_aspeed_rtc = {
-+                              ARM_HWCAP2_A64_SME_B16F32 |
+     .name = TYPE_ASPEED_RTC,
-+                              ARM_HWCAP2_A64_SME_F16F32 |
+-    .version_id = 1,
-+                              ARM_HWCAP2_A64_SME_I8I32));
++    .version_id = 2,
-+    GET_FEATURE_ID(aa64_sme_f64f64, ARM_HWCAP2_A64_SME_F64F64);
+     .fields = (VMStateField[]) {
-+    GET_FEATURE_ID(aa64_sme_i16i64, ARM_HWCAP2_A64_SME_I16I64);
+         VMSTATE_UINT32_ARRAY(reg, AspeedRtcState, 0x18),
-+    GET_FEATURE_ID(aa64_sme_fa64, ARM_HWCAP2_A64_SME_FA64);
+-        VMSTATE_INT32(offset, AspeedRtcState),
+-        VMSTATE_INT32(offset, AspeedRtcState),
-     return hwcaps;
++        VMSTATE_INT64(offset, AspeedRtcState),
- }
+         VMSTATE_END_OF_LIST()
      }
  };
 --
-.25.1
+.34.1

-[PULL 26/45] target/arm: Implement FMOPA, FMOPS (widening)
+[PULL 21/24] rtc: Use time_t for passing and returning time offsets
-From: Richard Henderson <richard.henderson@linaro.org>
+The functions qemu_get_timedate() and qemu_timedate_diff() take
 and return a time offset as an integer. Coverity points out that
 means that when an RTC device implementation holds an offset
 as a time_t, as the m48t59 does, the time_t will get truncated.
 (CID 1507157, 1517772).
-Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
+The functions work with time_t internally, so make them use that type
-Message-id: 20220708151540.18136-27-richard.henderson@linaro.org
+in their APIs.
 Note that this won't help any Y2038 issues where either the device
 model itself is keeping the offset in a 32-bit integer, or where the
 hardware under emulation has Y2038 or other rollover problems.  If we
 missed any cases of the former then hopefully Coverity will warn us
 about them since after this patch we'd be truncating a time_t in
 assignments from qemu_timedate_diff().)
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
-Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
+Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
 ---
- target/arm/helper-sme.h    |  2 ++
+ include/sysemu/rtc.h | 4 ++--
- target/arm/sme.decode      |  1 +
+ softmmu/rtc.c        | 4 ++--
- target/arm/sme_helper.c    | 74 ++++++++++++++++++++++++++++++++++++++
+files changed, 4 insertions(+), 4 deletions(-)
  target/arm/translate-sme.c |  1 +
 files changed, 78 insertions(+)
-diff --git a/target/arm/helper-sme.h b/target/arm/helper-sme.h
+diff --git a/include/sysemu/rtc.h b/include/sysemu/rtc.h
 index XXXXXXX..XXXXXXX 100644
---- a/target/arm/helper-sme.h
+--- a/include/sysemu/rtc.h
-+++ b/target/arm/helper-sme.h
++++ b/include/sysemu/rtc.h
-@@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_5(sme_addva_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32)
+@@ -XXX,XX +XXX,XX @@
- DEF_HELPER_FLAGS_5(sme_addha_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32)
+  * The behaviour of the clock whose value this function returns will
- DEF_HELPER_FLAGS_5(sme_addva_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32)
+  * depend on the -rtc command line option passed by the user.
+  */
-+DEF_HELPER_FLAGS_7(sme_fmopa_h, TCG_CALL_NO_RWG,
+-void qemu_get_timedate(struct tm *tm, int offset);
-+                   void, ptr, ptr, ptr, ptr, ptr, ptr, i32)
++void qemu_get_timedate(struct tm *tm, time_t offset);
- DEF_HELPER_FLAGS_7(sme_fmopa_s, TCG_CALL_NO_RWG,
-                    void, ptr, ptr, ptr, ptr, ptr, ptr, i32)
+ /**
- DEF_HELPER_FLAGS_7(sme_fmopa_d, TCG_CALL_NO_RWG,
+  * qemu_timedate_diff: Return difference between a struct tm and the RTC
-diff --git a/target/arm/sme.decode b/target/arm/sme.decode
+@@ -XXX,XX +XXX,XX @@ void qemu_get_timedate(struct tm *tm, int offset);
   * a timestamp one hour further ahead than the current RTC time
   * then this function will return 3600.
   */
 -int qemu_timedate_diff(struct tm *tm);
 +time_t qemu_timedate_diff(struct tm *tm);
  #endif
 diff --git a/softmmu/rtc.c b/softmmu/rtc.c
 index XXXXXXX..XXXXXXX 100644
---- a/target/arm/sme.decode
+--- a/softmmu/rtc.c
-+++ b/target/arm/sme.decode
++++ b/softmmu/rtc.c
-@@ -XXX,XX +XXX,XX @@ FMOPA_s         10000000 100 ..... ... ... ..... . 00 ..        @op_32
+@@ -XXX,XX +XXX,XX @@ static time_t qemu_ref_timedate(QEMUClockType clock)
- FMOPA_d         10000000 110 ..... ... ... ..... . 0 ...        @op_64
+     return value;
  BFMOPA          10000001 100 ..... ... ... ..... . 00 ..        @op_32
 +FMOPA_h         10000001 101 ..... ... ... ..... . 00 ..        @op_32
 diff --git a/target/arm/sme_helper.c b/target/arm/sme_helper.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/sme_helper.c
 +++ b/target/arm/sme_helper.c
@@ -XXX,XX +XXX,XX @@ static inline uint32_t f16mop_adj_pair(uint32_t pair, uint32_t pg, uint32_t neg)
      return pair;
  }
-+static float32 f16_dotadd(float32 sum, uint32_t e1, uint32_t e2,
+-void qemu_get_timedate(struct tm *tm, int offset)
-+                          float_status *s_std, float_status *s_odd)
++void qemu_get_timedate(struct tm *tm, time_t offset)
 +{
 +    float64 e1r = float16_to_float64(e1 & 0xffff, true, s_std);
 +    float64 e1c = float16_to_float64(e1 >> 16, true, s_std);
 +    float64 e2r = float16_to_float64(e2 & 0xffff, true, s_std);
 +    float64 e2c = float16_to_float64(e2 >> 16, true, s_std);
 +    float64 t64;
 +    float32 t32;
 +
 +    /*
 +     * The ARM pseudocode function FPDot performs both multiplies
 +     * and the add with a single rounding operation.  Emulate this
 +     * by performing the first multiply in round-to-odd, then doing
 +     * the second multiply as fused multiply-add, and rounding to
 +     * float32 all in one step.
 +     */
 +    t64 = float64_mul(e1r, e2r, s_odd);
 +    t64 = float64r32_muladd(e1c, e2c, t64, 0, s_std);
 +
 +    /* This conversion is exact, because we've already rounded. */
 +    t32 = float64_to_float32(t64, s_std);
 +
 +    /* The final accumulation step is not fused. */
 +    return float32_add(sum, t32, s_std);
 +}
 +
 +void HELPER(sme_fmopa_h)(void *vza, void *vzn, void *vzm, void *vpn,
 +                         void *vpm, void *vst, uint32_t desc)
 +{
 +    intptr_t row, col, oprsz = simd_maxsz(desc);
 +    uint32_t neg = simd_data(desc) * 0x80008000u;
 +    uint16_t *pn = vpn, *pm = vpm;
 +    float_status fpst_odd, fpst_std;
 +
 +    /*
 +     * Make a copy of float_status because this operation does not
 +     * update the cumulative fp exception status.  It also produces
 +     * default nans.  Make a second copy with round-to-odd -- see above.
 +     */
 +    fpst_std = *(float_status *)vst;
 +    set_default_nan_mode(true, &fpst_std);
 +    fpst_odd = fpst_std;
 +    set_float_rounding_mode(float_round_to_odd, &fpst_odd);
 +
 +    for (row = 0; row < oprsz; ) {
 +        uint16_t prow = pn[H2(row >> 4)];
 +        do {
 +            void *vza_row = vza + tile_vslice_offset(row);
 +            uint32_t n = *(uint32_t *)(vzn + H1_4(row));
 +
 +            n = f16mop_adj_pair(n, prow, neg);
 +
 +            for (col = 0; col < oprsz; ) {
 +                uint16_t pcol = pm[H2(col >> 4)];
 +                do {
 +                    if (prow & pcol & 0b0101) {
 +                        uint32_t *a = vza_row + H1_4(col);
 +                        uint32_t m = *(uint32_t *)(vzm + H1_4(col));
 +
 +                        m = f16mop_adj_pair(m, pcol, 0);
 +                        *a = f16_dotadd(*a, n, m, &fpst_std, &fpst_odd);
 +
 +                        col += 4;
 +                        pcol >>= 4;
 +                    }
 +                } while (col & 15);
 +            }
 +            row += 4;
 +            prow >>= 4;
 +        } while (row & 15);
 +    }
 +}
 +
  void HELPER(sme_bfmopa)(void *vza, void *vzn, void *vzm, void *vpn,
                          void *vpm, uint32_t desc)
  {
-diff --git a/target/arm/translate-sme.c b/target/arm/translate-sme.c
+     time_t ti = qemu_ref_timedate(rtc_clock);
-index XXXXXXX..XXXXXXX 100644
---- a/target/arm/translate-sme.c
+@@ -XXX,XX +XXX,XX @@ void qemu_get_timedate(struct tm *tm, int offset)
-+++ b/target/arm/translate-sme.c
+     }
@@ -XXX,XX +XXX,XX @@ static bool do_outprod_fpst(DisasContext *s, arg_op *a, MemOp esz,
      return true;
  }
-+TRANS_FEAT(FMOPA_h, aa64_sme, do_outprod_fpst, a, MO_32, gen_helper_sme_fmopa_h)
+-int qemu_timedate_diff(struct tm *tm)
- TRANS_FEAT(FMOPA_s, aa64_sme, do_outprod_fpst, a, MO_32, gen_helper_sme_fmopa_s)
++time_t qemu_timedate_diff(struct tm *tm)
- TRANS_FEAT(FMOPA_d, aa64_sme_f64f64, do_outprod_fpst, a, MO_64, gen_helper_sme_fmopa_d)
+ {
      time_t seconds;
 --
-.25.1
+.34.1

-[PULL 29/45] target/arm: Implement REVD
+[PULL 22/24] target/arm: Do all "ARM_FEATURE_X implies Y" checks in post_init
-From: Richard Henderson <richard.henderson@linaro.org>
+Where architecturally one ARM_FEATURE_X flag implies another
+ARM_FEATURE_Y, we allow the CPU init function to only set X, and then
-This is an SVE instruction that operates using the SVE vector
+set Y for it.  Currently we do this in two places -- we set a few
-length but that it is present only if SME is implemented.
+flags in arm_cpu_post_init() because we need them to decide which
+properties to create on the CPU object, and then we do the rest in
-Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
+arm_cpu_realizefn().  However, this is fragile, because it's easy to
-Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
+add a new property and not notice that this means that an X-implies-Y
-Message-id: 20220708151540.18136-30-richard.henderson@linaro.org
+check now has to move from realize to post-init.
 As a specific example, the pmsav7-dregion property is conditional
 on ARM_FEATURE_PMSA && ARM_FEATURE_V7, which means it won't appear
 on the Cortex-M33 and -M55, because they set ARM_FEATURE_V8 and
 rely on V8-implies-V7, which doesn't happen until the realizefn.
 Move all of these X-implies-Y checks into a new function, which
 we call at the top of arm_cpu_post_init(), so the feature bits
 are available at that point.
 This does now give us the reverse issue, that if there's a feature
 bit which is enabled or disabled by the setting of a property then
 then X-implies-Y features that are dependent on that property need to
 be in realize, not in this new function.  But the only one of those
 is the "EL3 implies VBAR" which is already in the right place, so
 putting things this way round seems better to me.
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
+Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
+Message-id: 20230724174335.2150499-2-peter.maydell@linaro.org
 ---
- target/arm/helper-sve.h    |  2 ++
+ target/arm/cpu.c | 179 +++++++++++++++++++++++++----------------------
- target/arm/sve.decode      |  1 +
+file changed, 97 insertions(+), 82 deletions(-)
- target/arm/sve_helper.c    | 16 ++++++++++++++++
- target/arm/translate-sve.c |  2 ++
+diff --git a/target/arm/cpu.c b/target/arm/cpu.c
 files changed, 21 insertions(+)
 diff --git a/target/arm/helper-sve.h b/target/arm/helper-sve.h
 index XXXXXXX..XXXXXXX 100644
---- a/target/arm/helper-sve.h
+--- a/target/arm/cpu.c
-+++ b/target/arm/helper-sve.h
++++ b/target/arm/cpu.c
-@@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_4(sve_revh_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
+@@ -XXX,XX +XXX,XX @@ unsigned int gt_cntfrq_period_ns(ARMCPU *cpu)
+       NANOSECONDS_PER_SECOND / cpu->gt_cntfrq_hz : 1;
- DEF_HELPER_FLAGS_4(sve_revw_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
+ }
-+DEF_HELPER_FLAGS_4(sme_revd_q, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
++static void arm_cpu_propagate_feature_implications(ARMCPU *cpu)
 +
  DEF_HELPER_FLAGS_4(sve_rbit_b, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
  DEF_HELPER_FLAGS_4(sve_rbit_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
  DEF_HELPER_FLAGS_4(sve_rbit_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
 diff --git a/target/arm/sve.decode b/target/arm/sve.decode
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/sve.decode
 +++ b/target/arm/sve.decode
@@ -XXX,XX +XXX,XX @@ REVB            00000101 .. 1001 00 100 ... ..... .....         @rd_pg_rn
  REVH            00000101 .. 1001 01 100 ... ..... .....         @rd_pg_rn
  REVW            00000101 .. 1001 10 100 ... ..... .....         @rd_pg_rn
  RBIT            00000101 .. 1001 11 100 ... ..... .....         @rd_pg_rn
 +REVD            00000101 00 1011 10 100 ... ..... .....         @rd_pg_rn_e0
  # SVE vector splice (predicated, destructive)
  SPLICE          00000101 .. 101 100 100 ... ..... .....         @rdn_pg_rm
 diff --git a/target/arm/sve_helper.c b/target/arm/sve_helper.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/sve_helper.c
 +++ b/target/arm/sve_helper.c
@@ -XXX,XX +XXX,XX @@ DO_ZPZ_D(sve_revh_d, uint64_t, hswap64)
  DO_ZPZ_D(sve_revw_d, uint64_t, wswap64)
 +void HELPER(sme_revd_q)(void *vd, void *vn, void *vg, uint32_t desc)
 +{
-+    intptr_t i, opr_sz = simd_oprsz(desc) / 8;
++    CPUARMState *env = &cpu->env;
-+    uint64_t *d = vd, *n = vn;
++    bool no_aa32 = false;
-+    uint8_t *pg = vg;
++
-+
++    /*
-+    for (i = 0; i < opr_sz; i += 2) {
++     * Some features automatically imply others: set the feature
-+        if (pg[H1(i)] & 1) {
++     * bits explicitly for these cases.
-+            uint64_t n0 = n[i + 0];
++     */
-+            uint64_t n1 = n[i + 1];
++
-+            d[i + 0] = n1;
++    if (arm_feature(env, ARM_FEATURE_M)) {
-+            d[i + 1] = n0;
++        set_feature(env, ARM_FEATURE_PMSA);
 +    }
 +
 +    if (arm_feature(env, ARM_FEATURE_V8)) {
 +        if (arm_feature(env, ARM_FEATURE_M)) {
 +            set_feature(env, ARM_FEATURE_V7);
 +        } else {
 +            set_feature(env, ARM_FEATURE_V7VE);
 +        }
 +    }
++
++    /*
++     * There exist AArch64 cpus without AArch32 support.  When KVM
++     * queries ID_ISAR0_EL1 on such a host, the value is UNKNOWN.
++     * Similarly, we cannot check ID_AA64PFR0 without AArch64 support.
++     * As a general principle, we also do not make ID register
++     * consistency checks anywhere unless using TCG, because only
++     * for TCG would a consistency-check failure be a QEMU bug.
++     */
++    if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) {
++        no_aa32 = !cpu_isar_feature(aa64_aa32, cpu);
++    }
++
++    if (arm_feature(env, ARM_FEATURE_V7VE)) {
++        /*
++         * v7 Virtualization Extensions. In real hardware this implies
++         * EL2 and also the presence of the Security Extensions.
++         * For QEMU, for backwards-compatibility we implement some
++         * CPUs or CPU configs which have no actual EL2 or EL3 but do
++         * include the various other features that V7VE implies.
++         * Presence of EL2 itself is ARM_FEATURE_EL2, and of the
++         * Security Extensions is ARM_FEATURE_EL3.
++         */
++        assert(!tcg_enabled() || no_aa32 ||
++               cpu_isar_feature(aa32_arm_div, cpu));
++        set_feature(env, ARM_FEATURE_LPAE);
++        set_feature(env, ARM_FEATURE_V7);
++    }
++    if (arm_feature(env, ARM_FEATURE_V7)) {
++        set_feature(env, ARM_FEATURE_VAPA);
++        set_feature(env, ARM_FEATURE_THUMB2);
++        set_feature(env, ARM_FEATURE_MPIDR);
++        if (!arm_feature(env, ARM_FEATURE_M)) {
++            set_feature(env, ARM_FEATURE_V6K);
++        } else {
++            set_feature(env, ARM_FEATURE_V6);
++        }
++
++        /*
++         * Always define VBAR for V7 CPUs even if it doesn't exist in
++         * non-EL3 configs. This is needed by some legacy boards.
++         */
++        set_feature(env, ARM_FEATURE_VBAR);
++    }
++    if (arm_feature(env, ARM_FEATURE_V6K)) {
++        set_feature(env, ARM_FEATURE_V6);
++        set_feature(env, ARM_FEATURE_MVFR);
++    }
++    if (arm_feature(env, ARM_FEATURE_V6)) {
++        set_feature(env, ARM_FEATURE_V5);
++        if (!arm_feature(env, ARM_FEATURE_M)) {
++            assert(!tcg_enabled() || no_aa32 ||
++                   cpu_isar_feature(aa32_jazelle, cpu));
++            set_feature(env, ARM_FEATURE_AUXCR);
++        }
++    }
++    if (arm_feature(env, ARM_FEATURE_V5)) {
++        set_feature(env, ARM_FEATURE_V4T);
++    }
++    if (arm_feature(env, ARM_FEATURE_LPAE)) {
++        set_feature(env, ARM_FEATURE_V7MP);
++    }
++    if (arm_feature(env, ARM_FEATURE_CBAR_RO)) {
++        set_feature(env, ARM_FEATURE_CBAR);
++    }
++    if (arm_feature(env, ARM_FEATURE_THUMB2) &&
++        !arm_feature(env, ARM_FEATURE_M)) {
++        set_feature(env, ARM_FEATURE_THUMB_DSP);
++    }
 +}
 +
- DO_ZPZ(sve_rbit_b, uint8_t, H1, revbit8)
+ void arm_cpu_post_init(Object *obj)
- DO_ZPZ(sve_rbit_h, uint16_t, H1_2, revbit16)
+ {
- DO_ZPZ(sve_rbit_s, uint32_t, H1_4, revbit32)
+     ARMCPU *cpu = ARM_CPU(obj);
-diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
-index XXXXXXX..XXXXXXX 100644
+-    /* M profile implies PMSA. We have to do this here rather than
---- a/target/arm/translate-sve.c
+-     * in realize with the other feature-implication checks because
-+++ b/target/arm/translate-sve.c
+-     * we look at the PMSA bit to see if we should add some properties.
-@@ -XXX,XX +XXX,XX @@ TRANS_FEAT(REVH, aa64_sve, gen_gvec_ool_arg_zpz, revh_fns[a->esz], a, 0)
++    /*
- TRANS_FEAT(REVW, aa64_sve, gen_gvec_ool_arg_zpz,
++     * Some features imply others. Figure this out now, because we
-            a->esz == 3 ? gen_helper_sve_revw_d : NULL, a, 0)
++     * are going to look at the feature bits in deciding which
++     * properties to add.
-+TRANS_FEAT(REVD, aa64_sme, gen_gvec_ool_arg_zpz, gen_helper_sme_revd_q, a, 0)
+      */
-+
+-    if (arm_feature(&cpu->env, ARM_FEATURE_M)) {
- TRANS_FEAT(SPLICE, aa64_sve, gen_gvec_ool_arg_zpzz,
+-        set_feature(&cpu->env, ARM_FEATURE_PMSA);
-            gen_helper_sve_splice, a, a->esz)
+-    }
++    arm_cpu_propagate_feature_implications(cpu);
      if (arm_feature(&cpu->env, ARM_FEATURE_CBAR) ||
          arm_feature(&cpu->env, ARM_FEATURE_CBAR_RO)) {
@@ -XXX,XX +XXX,XX @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp)
      CPUARMState *env = &cpu->env;
      int pagebits;
      Error *local_err = NULL;
 -    bool no_aa32 = false;
      /* Use pc-relative instructions in system-mode */
  #ifndef CONFIG_USER_ONLY
@@ -XXX,XX +XXX,XX @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp)
          cpu->isar.id_isar3 = u;
      }
 -    /* Some features automatically imply others: */
 -    if (arm_feature(env, ARM_FEATURE_V8)) {
 -        if (arm_feature(env, ARM_FEATURE_M)) {
 -            set_feature(env, ARM_FEATURE_V7);
 -        } else {
 -            set_feature(env, ARM_FEATURE_V7VE);
 -        }
 -    }
 -
 -    /*
 -     * There exist AArch64 cpus without AArch32 support.  When KVM
 -     * queries ID_ISAR0_EL1 on such a host, the value is UNKNOWN.
 -     * Similarly, we cannot check ID_AA64PFR0 without AArch64 support.
 -     * As a general principle, we also do not make ID register
 -     * consistency checks anywhere unless using TCG, because only
 -     * for TCG would a consistency-check failure be a QEMU bug.
 -     */
 -    if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) {
 -        no_aa32 = !cpu_isar_feature(aa64_aa32, cpu);
 -    }
 -
 -    if (arm_feature(env, ARM_FEATURE_V7VE)) {
 -        /* v7 Virtualization Extensions. In real hardware this implies
 -         * EL2 and also the presence of the Security Extensions.
 -         * For QEMU, for backwards-compatibility we implement some
 -         * CPUs or CPU configs which have no actual EL2 or EL3 but do
 -         * include the various other features that V7VE implies.
 -         * Presence of EL2 itself is ARM_FEATURE_EL2, and of the
 -         * Security Extensions is ARM_FEATURE_EL3.
 -         */
 -        assert(!tcg_enabled() || no_aa32 ||
 -               cpu_isar_feature(aa32_arm_div, cpu));
 -        set_feature(env, ARM_FEATURE_LPAE);
 -        set_feature(env, ARM_FEATURE_V7);
 -    }
 -    if (arm_feature(env, ARM_FEATURE_V7)) {
 -        set_feature(env, ARM_FEATURE_VAPA);
 -        set_feature(env, ARM_FEATURE_THUMB2);
 -        set_feature(env, ARM_FEATURE_MPIDR);
 -        if (!arm_feature(env, ARM_FEATURE_M)) {
 -            set_feature(env, ARM_FEATURE_V6K);
 -        } else {
 -            set_feature(env, ARM_FEATURE_V6);
 -        }
 -
 -        /* Always define VBAR for V7 CPUs even if it doesn't exist in
 -         * non-EL3 configs. This is needed by some legacy boards.
 -         */
 -        set_feature(env, ARM_FEATURE_VBAR);
 -    }
 -    if (arm_feature(env, ARM_FEATURE_V6K)) {
 -        set_feature(env, ARM_FEATURE_V6);
 -        set_feature(env, ARM_FEATURE_MVFR);
 -    }
 -    if (arm_feature(env, ARM_FEATURE_V6)) {
 -        set_feature(env, ARM_FEATURE_V5);
 -        if (!arm_feature(env, ARM_FEATURE_M)) {
 -            assert(!tcg_enabled() || no_aa32 ||
 -                   cpu_isar_feature(aa32_jazelle, cpu));
 -            set_feature(env, ARM_FEATURE_AUXCR);
 -        }
 -    }
 -    if (arm_feature(env, ARM_FEATURE_V5)) {
 -        set_feature(env, ARM_FEATURE_V4T);
 -    }
 -    if (arm_feature(env, ARM_FEATURE_LPAE)) {
 -        set_feature(env, ARM_FEATURE_V7MP);
 -    }
 -    if (arm_feature(env, ARM_FEATURE_CBAR_RO)) {
 -        set_feature(env, ARM_FEATURE_CBAR);
 -    }
 -    if (arm_feature(env, ARM_FEATURE_THUMB2) &&
 -        !arm_feature(env, ARM_FEATURE_M)) {
 -        set_feature(env, ARM_FEATURE_THUMB_DSP);
 -    }
      /*
       * We rely on no XScale CPU having VFP so we can use the same bits in the
 --
-.25.1
+.34.1

-[PULL 19/45] target/arm: Implement SME MOVA
+[PULL 23/24] hw/arm/armv7m: Add mpu-ns-regions and mpu-s-regions properties
-From: Richard Henderson <richard.henderson@linaro.org>
+M-profile CPUs generally allow configuration of the number of MPU
 regions that they have.  We don't currently model this, so our
 implementations of some of the board models provide CPUs with the
 wrong number of regions.  RTOSes like Zephyr that hardcode the
 expected number of regions may therefore not run on the model if they
 are set up to run on real hardware.
-We can reuse the SVE functions for implementing moves to/from
+Add properties mpu-ns-regions and mpu-s-regions to the ARMV7M object,
-horizontal tile slices, but we need new ones for moves to/from
+matching the ability of hardware to configure the number of Secure
-vertical tile slices.
+and NonSecure regions separately.  Our actual CPU implementation
 doesn't currently support that, and it happens that none of the MPS
 boards we model set the number of regions differently for Secure vs
 NonSecure, so we provide an interface to the boards and SoCs that
 won't need to change if we ever do add that functionality in future,
 but make it an error to configure the two properties to different
 values.
-Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
+(The property name on the CPU is the somewhat misnamed-for-M-profile
-Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
+"pmsav7-dregion", so we don't follow that naming convention for
-Message-id: 20220708151540.18136-20-richard.henderson@linaro.org
+the properties here. The TRM doesn't say what the CPU configuration
 variable names are, so we pick something, and follow the lowercase
 convention we already have for properties here.)
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
+Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
+Message-id: 20230724174335.2150499-3-peter.maydell@linaro.org
 ---
- target/arm/helper-sme.h    |  12 +++
+ include/hw/arm/armv7m.h |  8 ++++++++
- target/arm/helper-sve.h    |   2 +
+ hw/arm/armv7m.c         | 21 +++++++++++++++++++++
- target/arm/translate-a64.h |   8 ++
+files changed, 29 insertions(+)
  target/arm/translate.h     |   5 ++
  target/arm/sme.decode      |  15 ++++
  target/arm/sme_helper.c    | 151 ++++++++++++++++++++++++++++++++++++-
  target/arm/sve_helper.c    |  12 +++
  target/arm/translate-sme.c | 127 +++++++++++++++++++++++++++++++
 files changed, 331 insertions(+), 1 deletion(-)
-diff --git a/target/arm/helper-sme.h b/target/arm/helper-sme.h
+diff --git a/include/hw/arm/armv7m.h b/include/hw/arm/armv7m.h
 index XXXXXXX..XXXXXXX 100644
---- a/target/arm/helper-sme.h
+--- a/include/hw/arm/armv7m.h
-+++ b/target/arm/helper-sme.h
++++ b/include/hw/arm/armv7m.h
-@@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_2(set_pstate_sm, TCG_CALL_NO_RWG, void, env, i32)
+@@ -XXX,XX +XXX,XX @@ OBJECT_DECLARE_SIMPLE_TYPE(ARMv7MState, ARMV7M)
- DEF_HELPER_FLAGS_2(set_pstate_za, TCG_CALL_NO_RWG, void, env, i32)
+  * + Property "vfp": enable VFP (forwarded to CPU object)
+  * + Property "dsp": enable DSP (forwarded to CPU object)
- DEF_HELPER_FLAGS_3(sme_zero, TCG_CALL_NO_RWG, void, env, i32, i32)
+  * + Property "enable-bitband": expose bitbanded IO
-+
++ * + Property "mpu-ns-regions": number of Non-Secure MPU regions (forwarded
-+/* Move to/from vertical array slices, i.e. columns, so 'c'.  */
++ *   to CPU object pmsav7-dregion property; default is whatever the default
-+DEF_HELPER_FLAGS_4(sme_mova_cz_b, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
++ *   for the CPU is)
-+DEF_HELPER_FLAGS_4(sme_mova_zc_b, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
++ * + Property "mpu-s-regions": number of Secure MPU regions (default is
-+DEF_HELPER_FLAGS_4(sme_mova_cz_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
++ *   whatever the default for the CPU is; must currently be set to the same
-+DEF_HELPER_FLAGS_4(sme_mova_zc_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
++ *   value as mpu-ns-regions if the CPU implements the Security Extension)
-+DEF_HELPER_FLAGS_4(sme_mova_cz_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
+  * + Clock input "refclk" is the external reference clock for the systick timers
-+DEF_HELPER_FLAGS_4(sme_mova_zc_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
+  * + Clock input "cpuclk" is the main CPU clock
-+DEF_HELPER_FLAGS_4(sme_mova_cz_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
+  */
-+DEF_HELPER_FLAGS_4(sme_mova_zc_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
+@@ -XXX,XX +XXX,XX @@ struct ARMv7MState {
-+DEF_HELPER_FLAGS_4(sme_mova_cz_q, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
+     Object *idau;
-+DEF_HELPER_FLAGS_4(sme_mova_zc_q, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
+     uint32_t init_svtor;
-diff --git a/target/arm/helper-sve.h b/target/arm/helper-sve.h
+     uint32_t init_nsvtor;
 +    uint32_t mpu_ns_regions;
 +    uint32_t mpu_s_regions;
      bool enable_bitband;
      bool start_powered_off;
      bool vfp;
 diff --git a/hw/arm/armv7m.c b/hw/arm/armv7m.c
 index XXXXXXX..XXXXXXX 100644
---- a/target/arm/helper-sve.h
+--- a/hw/arm/armv7m.c
-+++ b/target/arm/helper-sve.h
++++ b/hw/arm/armv7m.c
-@@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_5(sve_sel_zpzz_s, TCG_CALL_NO_RWG,
+@@ -XXX,XX +XXX,XX @@ static void armv7m_realize(DeviceState *dev, Error **errp)
                     void, ptr, ptr, ptr, ptr, i32)
  DEF_HELPER_FLAGS_5(sve_sel_zpzz_d, TCG_CALL_NO_RWG,
                     void, ptr, ptr, ptr, ptr, i32)
 +DEF_HELPER_FLAGS_5(sve_sel_zpzz_q, TCG_CALL_NO_RWG,
 +                   void, ptr, ptr, ptr, ptr, i32)
  DEF_HELPER_FLAGS_5(sve2_addp_zpzz_b, TCG_CALL_NO_RWG,
                     void, ptr, ptr, ptr, ptr, i32)
 diff --git a/target/arm/translate-a64.h b/target/arm/translate-a64.h
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/translate-a64.h
 +++ b/target/arm/translate-a64.h
@@ -XXX,XX +XXX,XX @@ static inline int pred_gvec_reg_size(DisasContext *s)
      return size_for_gvec(pred_full_reg_size(s));
  }
 +/* Return a newly allocated pointer to the predicate register.  */
 +static inline TCGv_ptr pred_full_reg_ptr(DisasContext *s, int regno)
 +{
 +    TCGv_ptr ret = tcg_temp_new_ptr();
 +    tcg_gen_addi_ptr(ret, cpu_env, pred_full_reg_offset(s, regno));
 +    return ret;
 +}
 +
  bool disas_sve(DisasContext *, uint32_t);
  bool disas_sme(DisasContext *, uint32_t);
 diff --git a/target/arm/translate.h b/target/arm/translate.h
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/translate.h
 +++ b/target/arm/translate.h
@@ -XXX,XX +XXX,XX @@ static inline int plus_2(DisasContext *s, int x)
      return x + 2;
  }
 +static inline int plus_12(DisasContext *s, int x)
 +{
 +    return x + 12;
 +}
 +
  static inline int times_2(DisasContext *s, int x)
  {
      return x * 2;
 diff --git a/target/arm/sme.decode b/target/arm/sme.decode
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/sme.decode
 +++ b/target/arm/sme.decode
@@ -XXX,XX +XXX,XX @@
  ### SME Misc
  ZERO            11000000 00 001 00000000000 imm:8
 +
 +### SME Move into/from Array
 +
 +%mova_rs        13:2 !function=plus_12
 +&mova           esz rs pg zr za_imm v:bool to_vec:bool
 +
 +MOVA            11000000 esz:2 00000 0 v:1 .. pg:3 zr:5 0 za_imm:4  \
 +                &mova to_vec=0 rs=%mova_rs
 +MOVA            11000000 11    00000 1 v:1 .. pg:3 zr:5 0 za_imm:4  \
 +                &mova to_vec=0 rs=%mova_rs esz=4
 +
 +MOVA            11000000 esz:2 00001 0 v:1 .. pg:3 0 za_imm:4 zr:5  \
 +                &mova to_vec=1 rs=%mova_rs
 +MOVA            11000000 11    00001 1 v:1 .. pg:3 0 za_imm:4 zr:5  \
 +                &mova to_vec=1 rs=%mova_rs esz=4
 diff --git a/target/arm/sme_helper.c b/target/arm/sme_helper.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/sme_helper.c
 +++ b/target/arm/sme_helper.c
@@ -XXX,XX +XXX,XX @@
  #include "qemu/osdep.h"
  #include "cpu.h"
 -#include "internals.h"
 +#include "tcg/tcg-gvec-desc.h"
  #include "exec/helper-proto.h"
 +#include "qemu/int128.h"
 +#include "vec_internal.h"
  /* ResetSVEState */
  void arm_reset_sve_state(CPUARMState *env)
@@ -XXX,XX +XXX,XX @@ void helper_sme_zero(CPUARMState *env, uint32_t imm, uint32_t svl)
          }
      }
- }
-+
++    /*
-+
++     * Real M-profile hardware can be configured with a different number of
-+/*
++     * MPU regions for Secure vs NonSecure. QEMU's CPU implementation doesn't
-+ * When considering the ZA storage as an array of elements of
++     * support that yet, so catch attempts to select that.
-+ * type T, the index within that array of the Nth element of
++     */
-+ * a vertical slice of a tile can be calculated like this,
++    if (arm_feature(&s->cpu->env, ARM_FEATURE_M_SECURITY) &&
-+ * regardless of the size of type T. This is because the tiles
++        s->mpu_ns_regions != s->mpu_s_regions) {
-+ * are interleaved, so if type T is size N bytes then row 1 of
++        error_setg(errp,
-+ * the tile is N rows away from row 0. The division by N to
++                   "mpu-ns-regions and mpu-s-regions properties must have the same value");
-+ * convert a byte offset into an array index and the multiplication
++        return;
 + * by N to convert from vslice-index-within-the-tile to
 + * the index within the ZA storage cancel out.
 + */
 +#define tile_vslice_index(i) ((i) * sizeof(ARMVectorReg))
 +
 +/*
 + * When doing byte arithmetic on the ZA storage, the element
 + * byteoff bytes away in a tile vertical slice is always this
 + * many bytes away in the ZA storage, regardless of the
 + * size of the tile element, assuming that byteoff is a multiple
 + * of the element size. Again this is because of the interleaving
 + * of the tiles. For instance if we have 1 byte per element then
 + * each row of the ZA storage has one byte of the vslice data,
 + * and (counting from 0) byte 8 goes in row 8 of the storage
 + * at offset (8 * row-size-in-bytes).
 + * If we have 8 bytes per element then each row of the ZA storage
 + * has 8 bytes of the data, but there are 8 interleaved tiles and
 + * so byte 8 of the data goes into row 1 of the tile,
 + * which is again row 8 of the storage, so the offset is still
 + * (8 * row-size-in-bytes). Similarly for other element sizes.
 + */
 +#define tile_vslice_offset(byteoff) ((byteoff) * sizeof(ARMVectorReg))
 +
 +
 +/*
 + * Move Zreg vector to ZArray column.
 + */
 +#define DO_MOVA_C(NAME, TYPE, H)                                        \
 +void HELPER(NAME)(void *za, void *vn, void *vg, uint32_t desc)          \
 +{                                                                       \
 +    int i, oprsz = simd_oprsz(desc);                                    \
 +    for (i = 0; i < oprsz; ) {                                          \
 +        uint16_t pg = *(uint16_t *)(vg + H1_2(i >> 3));                 \
 +        do {                                                            \
 +            if (pg & 1) {                                               \
 +                *(TYPE *)(za + tile_vslice_offset(i)) = *(TYPE *)(vn + H(i)); \
 +            }                                                           \
 +            i += sizeof(TYPE);                                          \
 +            pg >>= sizeof(TYPE);                                        \
 +        } while (i & 15);                                               \
 +    }                                                                   \
 +}
 +
 +DO_MOVA_C(sme_mova_cz_b, uint8_t, H1)
 +DO_MOVA_C(sme_mova_cz_h, uint16_t, H1_2)
 +DO_MOVA_C(sme_mova_cz_s, uint32_t, H1_4)
 +
 +void HELPER(sme_mova_cz_d)(void *za, void *vn, void *vg, uint32_t desc)
 +{
 +    int i, oprsz = simd_oprsz(desc) / 8;
 +    uint8_t *pg = vg;
 +    uint64_t *n = vn;
 +    uint64_t *a = za;
 +
 +    for (i = 0; i < oprsz; i++) {
 +        if (pg[H1(i)] & 1) {
 +            a[tile_vslice_index(i)] = n[i];
 +        }
 +    }
-+}
++    if (s->mpu_ns_regions != UINT_MAX &&
-+
++        object_property_find(OBJECT(s->cpu), "pmsav7-dregion")) {
-+void HELPER(sme_mova_cz_q)(void *za, void *vn, void *vg, uint32_t desc)
++        if (!object_property_set_uint(OBJECT(s->cpu), "pmsav7-dregion",
-+{
++                                      s->mpu_ns_regions, errp)) {
-+    int i, oprsz = simd_oprsz(desc) / 16;
++            return;
 +    uint16_t *pg = vg;
 +    Int128 *n = vn;
 +    Int128 *a = za;
 +
 +    /*
 +     * Int128 is used here simply to copy 16 bytes, and to simplify
 +     * the address arithmetic.
 +     */
 +    for (i = 0; i < oprsz; i++) {
 +        if (pg[H2(i)] & 1) {
 +            a[tile_vslice_index(i)] = n[i];
 +        }
 +    }
 +}
 +
 +#undef DO_MOVA_C
 +
 +/*
 + * Move ZArray column to Zreg vector.
 + */
 +#define DO_MOVA_Z(NAME, TYPE, H)                                        \
 +void HELPER(NAME)(void *vd, void *za, void *vg, uint32_t desc)          \
 +{                                                                       \
 +    int i, oprsz = simd_oprsz(desc);                                    \
 +    for (i = 0; i < oprsz; ) {                                          \
 +        uint16_t pg = *(uint16_t *)(vg + H1_2(i >> 3));                 \
 +        do {                                                            \
 +            if (pg & 1) {                                               \
 +                *(TYPE *)(vd + H(i)) = *(TYPE *)(za + tile_vslice_offset(i)); \
 +            }                                                           \
 +            i += sizeof(TYPE);                                          \
 +            pg >>= sizeof(TYPE);                                        \
 +        } while (i & 15);                                               \
 +    }                                                                   \
 +}
 +
 +DO_MOVA_Z(sme_mova_zc_b, uint8_t, H1)
 +DO_MOVA_Z(sme_mova_zc_h, uint16_t, H1_2)
 +DO_MOVA_Z(sme_mova_zc_s, uint32_t, H1_4)
 +
 +void HELPER(sme_mova_zc_d)(void *vd, void *za, void *vg, uint32_t desc)
 +{
 +    int i, oprsz = simd_oprsz(desc) / 8;
 +    uint8_t *pg = vg;
 +    uint64_t *d = vd;
 +    uint64_t *a = za;
 +
 +    for (i = 0; i < oprsz; i++) {
 +        if (pg[H1(i)] & 1) {
 +            d[i] = a[tile_vslice_index(i)];
 +        }
 +    }
 +}
 +
 +void HELPER(sme_mova_zc_q)(void *vd, void *za, void *vg, uint32_t desc)
 +{
 +    int i, oprsz = simd_oprsz(desc) / 16;
 +    uint16_t *pg = vg;
 +    Int128 *d = vd;
 +    Int128 *a = za;
 +
 +    /*
 +     * Int128 is used here simply to copy 16 bytes, and to simplify
 +     * the address arithmetic.
 +     */
 +    for (i = 0; i < oprsz; i++, za += sizeof(ARMVectorReg)) {
 +        if (pg[H2(i)] & 1) {
 +            d[i] = a[tile_vslice_index(i)];
 +        }
 +    }
 +}
 +
 +#undef DO_MOVA_Z
 diff --git a/target/arm/sve_helper.c b/target/arm/sve_helper.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/sve_helper.c
 +++ b/target/arm/sve_helper.c
@@ -XXX,XX +XXX,XX @@ void HELPER(sve_sel_zpzz_d)(void *vd, void *vn, void *vm,
      }
  }
 +void HELPER(sve_sel_zpzz_q)(void *vd, void *vn, void *vm,
 +                            void *vg, uint32_t desc)
 +{
 +    intptr_t i, opr_sz = simd_oprsz(desc) / 16;
 +    Int128 *d = vd, *n = vn, *m = vm;
 +    uint16_t *pg = vg;
 +
 +    for (i = 0; i < opr_sz; i += 1) {
 +        d[i] = (pg[H2(i)] & 1 ? n : m)[i];
 +    }
 +}
 +
  /* Two operand comparison controlled by a predicate.
   * ??? It is very tempting to want to be able to expand this inline
   * with x86 instructions, e.g.
 diff --git a/target/arm/translate-sme.c b/target/arm/translate-sme.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/translate-sme.c
 +++ b/target/arm/translate-sme.c
@@ -XXX,XX +XXX,XX @@
  #include "decode-sme.c.inc"
 +/*
 + * Resolve tile.size[index] to a host pointer, where tile and index
 + * are always decoded together, dependent on the element size.
 + */
 +static TCGv_ptr get_tile_rowcol(DisasContext *s, int esz, int rs,
 +                                int tile_index, bool vertical)
 +{
 +    int tile = tile_index >> (4 - esz);
 +    int index = esz == MO_128 ? 0 : extract32(tile_index, 0, 4 - esz);
 +    int pos, len, offset;
 +    TCGv_i32 tmp;
 +    TCGv_ptr addr;
 +
 +    /* Compute the final index, which is Rs+imm. */
 +    tmp = tcg_temp_new_i32();
 +    tcg_gen_trunc_tl_i32(tmp, cpu_reg(s, rs));
 +    tcg_gen_addi_i32(tmp, tmp, index);
 +
 +    /* Prepare a power-of-two modulo via extraction of @len bits. */
 +    len = ctz32(streaming_vec_reg_size(s)) - esz;
 +
 +    if (vertical) {
 +        /*
 +         * Compute the byte offset of the index within the tile:
 +         *     (index % (svl / size)) * size
 +         *   = (index % (svl >> esz)) << esz
 +         * Perform the power-of-two modulo via extraction of the low @len bits.
 +         * Perform the multiply by shifting left by @pos bits.
 +         * Perform these operations simultaneously via deposit into zero.
 +         */
 +        pos = esz;
 +        tcg_gen_deposit_z_i32(tmp, tmp, pos, len);
 +
 +        /*
 +         * For big-endian, adjust the indexed column byte offset within
 +         * the uint64_t host words that make up env->zarray[].
 +         */
 +        if (HOST_BIG_ENDIAN && esz < MO_64) {
 +            tcg_gen_xori_i32(tmp, tmp, 8 - (1 << esz));
 +        }
 +    } else {
 +        /*
 +         * Compute the byte offset of the index within the tile:
 +         *     (index % (svl / size)) * (size * sizeof(row))
 +         *   = (index % (svl >> esz)) << (esz + log2(sizeof(row)))
 +         */
 +        pos = esz + ctz32(sizeof(ARMVectorReg));
 +        tcg_gen_deposit_z_i32(tmp, tmp, pos, len);
 +
 +        /* Row slices are always aligned and need no endian adjustment. */
 +    }
 +
 +    /* The tile byte offset within env->zarray is the row. */
 +    offset = tile * sizeof(ARMVectorReg);
 +
 +    /* Include the byte offset of zarray to make this relative to env. */
 +    offset += offsetof(CPUARMState, zarray);
 +    tcg_gen_addi_i32(tmp, tmp, offset);
 +
 +    /* Add the byte offset to env to produce the final pointer. */
 +    addr = tcg_temp_new_ptr();
 +    tcg_gen_ext_i32_ptr(addr, tmp);
 +    tcg_temp_free_i32(tmp);
 +    tcg_gen_add_ptr(addr, addr, cpu_env);
 +
 +    return addr;
 +}
 +
  static bool trans_ZERO(DisasContext *s, arg_ZERO *a)
  {
      if (!dc_isar_feature(aa64_sme, s)) {
@@ -XXX,XX +XXX,XX @@ static bool trans_ZERO(DisasContext *s, arg_ZERO *a)
      }
      return true;
  }
 +
 +static bool trans_MOVA(DisasContext *s, arg_MOVA *a)
 +{
 +    static gen_helper_gvec_4 * const h_fns[5] = {
 +        gen_helper_sve_sel_zpzz_b, gen_helper_sve_sel_zpzz_h,
 +        gen_helper_sve_sel_zpzz_s, gen_helper_sve_sel_zpzz_d,
 +        gen_helper_sve_sel_zpzz_q
 +    };
 +    static gen_helper_gvec_3 * const cz_fns[5] = {
 +        gen_helper_sme_mova_cz_b, gen_helper_sme_mova_cz_h,
 +        gen_helper_sme_mova_cz_s, gen_helper_sme_mova_cz_d,
 +        gen_helper_sme_mova_cz_q,
 +    };
 +    static gen_helper_gvec_3 * const zc_fns[5] = {
 +        gen_helper_sme_mova_zc_b, gen_helper_sme_mova_zc_h,
 +        gen_helper_sme_mova_zc_s, gen_helper_sme_mova_zc_d,
 +        gen_helper_sme_mova_zc_q,
 +    };
 +
 +    TCGv_ptr t_za, t_zr, t_pg;
 +    TCGv_i32 t_desc;
 +    int svl;
 +
 +    if (!dc_isar_feature(aa64_sme, s)) {
 +        return false;
 +    }
 +    if (!sme_smza_enabled_check(s)) {
 +        return true;
 +    }
 +
 +    t_za = get_tile_rowcol(s, a->esz, a->rs, a->za_imm, a->v);
 +    t_zr = vec_full_reg_ptr(s, a->zr);
 +    t_pg = pred_full_reg_ptr(s, a->pg);
 +
 +    svl = streaming_vec_reg_size(s);
 +    t_desc = tcg_constant_i32(simd_desc(svl, svl, 0));
 +
 +    if (a->v) {
 +        /* Vertical slice -- use sme mova helpers. */
 +        if (a->to_vec) {
 +            zc_fns[a->esz](t_zr, t_za, t_pg, t_desc);
 +        } else {
 +            cz_fns[a->esz](t_za, t_zr, t_pg, t_desc);
 +        }
 +    } else {
 +        /* Horizontal slice -- reuse sve sel helpers. */
 +        if (a->to_vec) {
 +            h_fns[a->esz](t_zr, t_za, t_zr, t_pg, t_desc);
 +        } else {
 +            h_fns[a->esz](t_za, t_zr, t_za, t_pg, t_desc);
 +        }
 +    }
 +
-+    tcg_temp_free_ptr(t_za);
+     /*
-+    tcg_temp_free_ptr(t_zr);
+      * Tell the CPU where the NVIC is; it will fail realize if it doesn't
-+    tcg_temp_free_ptr(t_pg);
+      * have one. Similarly, tell the NVIC where its CPU is.
-+
+@@ -XXX,XX +XXX,XX @@ static Property armv7m_properties[] = {
-+    return true;
+                      false),
-+}
+     DEFINE_PROP_BOOL("vfp", ARMv7MState, vfp, true),
      DEFINE_PROP_BOOL("dsp", ARMv7MState, dsp, true),
 +    DEFINE_PROP_UINT32("mpu-ns-regions", ARMv7MState, mpu_ns_regions, UINT_MAX),
 +    DEFINE_PROP_UINT32("mpu-s-regions", ARMv7MState, mpu_s_regions, UINT_MAX),
      DEFINE_PROP_END_OF_LIST(),
  };
 --
-.25.1
+.34.1

-[PULL 22/45] target/arm: Implement SME LDR, STR
+Deleted patch
-From: Richard Henderson <richard.henderson@linaro.org>
-We can reuse the SVE functions for LDR and STR, passing in the
-base of the ZA vector and a zero offset.
-Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
-Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
-Message-id: 20220708151540.18136-23-richard.henderson@linaro.org
-Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
----
- target/arm/sme.decode      |  7 +++++++
- target/arm/translate-sme.c | 24 ++++++++++++++++++++++++
-files changed, 31 insertions(+)
-diff --git a/target/arm/sme.decode b/target/arm/sme.decode
-index XXXXXXX..XXXXXXX 100644
---- a/target/arm/sme.decode
-+++ b/target/arm/sme.decode
-@@ -XXX,XX +XXX,XX @@ LDST1           1110000 0 esz:2 st:1 rm:5 v:1 .. pg:3 rn:5 0 za_imm:4  \
-                 &ldst rs=%mova_rs
- LDST1           1110000 111     st:1 rm:5 v:1 .. pg:3 rn:5 0 za_imm:4  \
-                 &ldst esz=4 rs=%mova_rs
-+
-+&ldstr          rv rn imm
-+@ldstr          ....... ... . ...... .. ... rn:5 . imm:4 \
-+                &ldstr rv=%mova_rs
-+
-+LDR             1110000 100 0 000000 .. 000 ..... 0 ....        @ldstr
-+STR             1110000 100 1 000000 .. 000 ..... 0 ....        @ldstr
-diff --git a/target/arm/translate-sme.c b/target/arm/translate-sme.c
-index XXXXXXX..XXXXXXX 100644
---- a/target/arm/translate-sme.c
-+++ b/target/arm/translate-sme.c
-@@ -XXX,XX +XXX,XX @@ static bool trans_LDST1(DisasContext *s, arg_LDST1 *a)
-     tcg_temp_free_i64(addr);
-     return true;
- }
-+
-+typedef void GenLdStR(DisasContext *, TCGv_ptr, int, int, int, int);
-+
-+static bool do_ldst_r(DisasContext *s, arg_ldstr *a, GenLdStR *fn)
-+{
-+    int svl = streaming_vec_reg_size(s);
-+    int imm = a->imm;
-+    TCGv_ptr base;
-+
-+    if (!sme_za_enabled_check(s)) {
-+        return true;
-+    }
-+
-+    /* ZA[n] equates to ZA0H.B[n]. */
-+    base = get_tile_rowcol(s, MO_8, a->rv, imm, false);
-+
-+    fn(s, base, 0, svl, a->rn, imm * svl);
-+
-+    tcg_temp_free_ptr(base);
-+    return true;
-+}
-+
-+TRANS_FEAT(LDR, aa64_sme, do_ldst_r, a, gen_sve_ldr)
-+TRANS_FEAT(STR, aa64_sme, do_ldst_r, a, gen_sve_str)
---
-.25.1

-[PULL 23/45] target/arm: Implement SME ADDHA, ADDVA
+Deleted patch
-From: Richard Henderson <richard.henderson@linaro.org>
-Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
-Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
-Message-id: 20220708151540.18136-24-richard.henderson@linaro.org
-Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
----
- target/arm/helper-sme.h    |  5 +++
- target/arm/sme.decode      | 11 +++++
- target/arm/sme_helper.c    | 90 ++++++++++++++++++++++++++++++++++++++
- target/arm/translate-sme.c | 31 +++++++++++++
-files changed, 137 insertions(+)
-diff --git a/target/arm/helper-sme.h b/target/arm/helper-sme.h
-index XXXXXXX..XXXXXXX 100644
---- a/target/arm/helper-sme.h
-+++ b/target/arm/helper-sme.h
-@@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_5(sme_st1q_be_h_mte, TCG_CALL_NO_WG, void, env, ptr, ptr, tl, i
- DEF_HELPER_FLAGS_5(sme_st1q_le_h_mte, TCG_CALL_NO_WG, void, env, ptr, ptr, tl, i32)
- DEF_HELPER_FLAGS_5(sme_st1q_be_v_mte, TCG_CALL_NO_WG, void, env, ptr, ptr, tl, i32)
- DEF_HELPER_FLAGS_5(sme_st1q_le_v_mte, TCG_CALL_NO_WG, void, env, ptr, ptr, tl, i32)
-+
-+DEF_HELPER_FLAGS_5(sme_addha_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32)
-+DEF_HELPER_FLAGS_5(sme_addva_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32)
-+DEF_HELPER_FLAGS_5(sme_addha_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32)
-+DEF_HELPER_FLAGS_5(sme_addva_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32)
-diff --git a/target/arm/sme.decode b/target/arm/sme.decode
-index XXXXXXX..XXXXXXX 100644
---- a/target/arm/sme.decode
-+++ b/target/arm/sme.decode
-@@ -XXX,XX +XXX,XX @@ LDST1           1110000 111     st:1 rm:5 v:1 .. pg:3 rn:5 0 za_imm:4  \
- LDR             1110000 100 0 000000 .. 000 ..... 0 ....        @ldstr
- STR             1110000 100 1 000000 .. 000 ..... 0 ....        @ldstr
-+
-+### SME Add Vector to Array
-+
-+&adda           zad zn pm pn
-+@adda_32        ........ .. ..... . pm:3 pn:3 zn:5 ... zad:2    &adda
-+@adda_64        ........ .. ..... . pm:3 pn:3 zn:5 ..  zad:3    &adda
-+
-+ADDHA_s         11000000 10 01000 0 ... ... ..... 000 ..        @adda_32
-+ADDVA_s         11000000 10 01000 1 ... ... ..... 000 ..        @adda_32
-+ADDHA_d         11000000 11 01000 0 ... ... ..... 00 ...        @adda_64
-+ADDVA_d         11000000 11 01000 1 ... ... ..... 00 ...        @adda_64
-diff --git a/target/arm/sme_helper.c b/target/arm/sme_helper.c
-index XXXXXXX..XXXXXXX 100644
---- a/target/arm/sme_helper.c
-+++ b/target/arm/sme_helper.c
-@@ -XXX,XX +XXX,XX @@ DO_ST(q, _be, MO_128)
- DO_ST(q, _le, MO_128)
- #undef DO_ST
-+
-+void HELPER(sme_addha_s)(void *vzda, void *vzn, void *vpn,
-+                         void *vpm, uint32_t desc)
-+{
-+    intptr_t row, col, oprsz = simd_oprsz(desc) / 4;
-+    uint64_t *pn = vpn, *pm = vpm;
-+    uint32_t *zda = vzda, *zn = vzn;
-+
-+    for (row = 0; row < oprsz; ) {
-+        uint64_t pa = pn[row >> 4];
-+        do {
-+            if (pa & 1) {
-+                for (col = 0; col < oprsz; ) {
-+                    uint64_t pb = pm[col >> 4];
-+                    do {
-+                        if (pb & 1) {
-+                            zda[tile_vslice_index(row) + H4(col)] += zn[H4(col)];
-+                        }
-+                        pb >>= 4;
-+                    } while (++col & 15);
-+                }
-+            }
-+            pa >>= 4;
-+        } while (++row & 15);
-+    }
-+}
-+
-+void HELPER(sme_addha_d)(void *vzda, void *vzn, void *vpn,
-+                         void *vpm, uint32_t desc)
-+{
-+    intptr_t row, col, oprsz = simd_oprsz(desc) / 8;
-+    uint8_t *pn = vpn, *pm = vpm;
-+    uint64_t *zda = vzda, *zn = vzn;
-+
-+    for (row = 0; row < oprsz; ++row) {
-+        if (pn[H1(row)] & 1) {
-+            for (col = 0; col < oprsz; ++col) {
-+                if (pm[H1(col)] & 1) {
-+                    zda[tile_vslice_index(row) + col] += zn[col];
-+                }
-+            }
-+        }
-+    }
-+}
-+
-+void HELPER(sme_addva_s)(void *vzda, void *vzn, void *vpn,
-+                         void *vpm, uint32_t desc)
-+{
-+    intptr_t row, col, oprsz = simd_oprsz(desc) / 4;
-+    uint64_t *pn = vpn, *pm = vpm;
-+    uint32_t *zda = vzda, *zn = vzn;
-+
-+    for (row = 0; row < oprsz; ) {
-+        uint64_t pa = pn[row >> 4];
-+        do {
-+            if (pa & 1) {
-+                uint32_t zn_row = zn[H4(row)];
-+                for (col = 0; col < oprsz; ) {
-+                    uint64_t pb = pm[col >> 4];
-+                    do {
-+                        if (pb & 1) {
-+                            zda[tile_vslice_index(row) + H4(col)] += zn_row;
-+                        }
-+                        pb >>= 4;
-+                    } while (++col & 15);
-+                }
-+            }
-+            pa >>= 4;
-+        } while (++row & 15);
-+    }
-+}
-+
-+void HELPER(sme_addva_d)(void *vzda, void *vzn, void *vpn,
-+                         void *vpm, uint32_t desc)
-+{
-+    intptr_t row, col, oprsz = simd_oprsz(desc) / 8;
-+    uint8_t *pn = vpn, *pm = vpm;
-+    uint64_t *zda = vzda, *zn = vzn;
-+
-+    for (row = 0; row < oprsz; ++row) {
-+        if (pn[H1(row)] & 1) {
-+            uint64_t zn_row = zn[row];
-+            for (col = 0; col < oprsz; ++col) {
-+                if (pm[H1(col)] & 1) {
-+                    zda[tile_vslice_index(row) + col] += zn_row;
-+                }
-+            }
-+        }
-+    }
-+}
-diff --git a/target/arm/translate-sme.c b/target/arm/translate-sme.c
-index XXXXXXX..XXXXXXX 100644
---- a/target/arm/translate-sme.c
-+++ b/target/arm/translate-sme.c
-@@ -XXX,XX +XXX,XX @@ static bool do_ldst_r(DisasContext *s, arg_ldstr *a, GenLdStR *fn)
- TRANS_FEAT(LDR, aa64_sme, do_ldst_r, a, gen_sve_ldr)
- TRANS_FEAT(STR, aa64_sme, do_ldst_r, a, gen_sve_str)
-+
-+static bool do_adda(DisasContext *s, arg_adda *a, MemOp esz,
-+                    gen_helper_gvec_4 *fn)
-+{
-+    int svl = streaming_vec_reg_size(s);
-+    uint32_t desc = simd_desc(svl, svl, 0);
-+    TCGv_ptr za, zn, pn, pm;
-+
-+    if (!sme_smza_enabled_check(s)) {
-+        return true;
-+    }
-+
-+    /* Sum XZR+zad to find ZAd. */
-+    za = get_tile_rowcol(s, esz, 31, a->zad, false);
-+    zn = vec_full_reg_ptr(s, a->zn);
-+    pn = pred_full_reg_ptr(s, a->pn);
-+    pm = pred_full_reg_ptr(s, a->pm);
-+
-+    fn(za, zn, pn, pm, tcg_constant_i32(desc));
-+
-+    tcg_temp_free_ptr(za);
-+    tcg_temp_free_ptr(zn);
-+    tcg_temp_free_ptr(pn);
-+    tcg_temp_free_ptr(pm);
-+    return true;
-+}
-+
-+TRANS_FEAT(ADDHA_s, aa64_sme, do_adda, a, MO_32, gen_helper_sme_addha_s)
-+TRANS_FEAT(ADDVA_s, aa64_sme, do_adda, a, MO_32, gen_helper_sme_addva_s)
-+TRANS_FEAT(ADDHA_d, aa64_sme_i16i64, do_adda, a, MO_64, gen_helper_sme_addha_d)
-+TRANS_FEAT(ADDVA_d, aa64_sme_i16i64, do_adda, a, MO_64, gen_helper_sme_addva_d)
---
-.25.1

-[PULL 24/45] target/arm: Implement FMOPA, FMOPS (non-widening)
+Deleted patch
-From: Richard Henderson <richard.henderson@linaro.org>
-Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
-Message-id: 20220708151540.18136-25-richard.henderson@linaro.org
-Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
-Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
----
- target/arm/helper-sme.h    |  5 +++
- target/arm/sme.decode      |  9 +++++
- target/arm/sme_helper.c    | 69 ++++++++++++++++++++++++++++++++++++++
- target/arm/translate-sme.c | 32 ++++++++++++++++++
-files changed, 115 insertions(+)
-diff --git a/target/arm/helper-sme.h b/target/arm/helper-sme.h
-index XXXXXXX..XXXXXXX 100644
---- a/target/arm/helper-sme.h
-+++ b/target/arm/helper-sme.h
-@@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_5(sme_addha_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32)
- DEF_HELPER_FLAGS_5(sme_addva_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32)
- DEF_HELPER_FLAGS_5(sme_addha_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32)
- DEF_HELPER_FLAGS_5(sme_addva_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32)
-+
-+DEF_HELPER_FLAGS_7(sme_fmopa_s, TCG_CALL_NO_RWG,
-+                   void, ptr, ptr, ptr, ptr, ptr, ptr, i32)
-+DEF_HELPER_FLAGS_7(sme_fmopa_d, TCG_CALL_NO_RWG,
-+                   void, ptr, ptr, ptr, ptr, ptr, ptr, i32)
-diff --git a/target/arm/sme.decode b/target/arm/sme.decode
-index XXXXXXX..XXXXXXX 100644
---- a/target/arm/sme.decode
-+++ b/target/arm/sme.decode
-@@ -XXX,XX +XXX,XX @@ ADDHA_s         11000000 10 01000 0 ... ... ..... 000 ..        @adda_32
- ADDVA_s         11000000 10 01000 1 ... ... ..... 000 ..        @adda_32
- ADDHA_d         11000000 11 01000 0 ... ... ..... 00 ...        @adda_64
- ADDVA_d         11000000 11 01000 1 ... ... ..... 00 ...        @adda_64
-+
-+### SME Outer Product
-+
-+&op             zad zn zm pm pn sub:bool
-+@op_32          ........ ... zm:5 pm:3 pn:3 zn:5 sub:1 .. zad:2 &op
-+@op_64          ........ ... zm:5 pm:3 pn:3 zn:5 sub:1 .  zad:3 &op
-+
-+FMOPA_s         10000000 100 ..... ... ... ..... . 00 ..        @op_32
-+FMOPA_d         10000000 110 ..... ... ... ..... . 0 ...        @op_64
-diff --git a/target/arm/sme_helper.c b/target/arm/sme_helper.c
-index XXXXXXX..XXXXXXX 100644
---- a/target/arm/sme_helper.c
-+++ b/target/arm/sme_helper.c
-@@ -XXX,XX +XXX,XX @@
- #include "exec/cpu_ldst.h"
- #include "exec/exec-all.h"
- #include "qemu/int128.h"
-+#include "fpu/softfloat.h"
- #include "vec_internal.h"
- #include "sve_ldst_internal.h"
-@@ -XXX,XX +XXX,XX @@ void HELPER(sme_addva_d)(void *vzda, void *vzn, void *vpn,
-         }
-     }
- }
-+
-+void HELPER(sme_fmopa_s)(void *vza, void *vzn, void *vzm, void *vpn,
-+                         void *vpm, void *vst, uint32_t desc)
-+{
-+    intptr_t row, col, oprsz = simd_maxsz(desc);
-+    uint32_t neg = simd_data(desc) << 31;
-+    uint16_t *pn = vpn, *pm = vpm;
-+    float_status fpst;
-+
-+    /*
-+     * Make a copy of float_status because this operation does not
-+     * update the cumulative fp exception status.  It also produces
-+     * default nans.
-+     */
-+    fpst = *(float_status *)vst;
-+    set_default_nan_mode(true, &fpst);
-+
-+    for (row = 0; row < oprsz; ) {
-+        uint16_t pa = pn[H2(row >> 4)];
-+        do {
-+            if (pa & 1) {
-+                void *vza_row = vza + tile_vslice_offset(row);
-+                uint32_t n = *(uint32_t *)(vzn + H1_4(row)) ^ neg;
-+
-+                for (col = 0; col < oprsz; ) {
-+                    uint16_t pb = pm[H2(col >> 4)];
-+                    do {
-+                        if (pb & 1) {
-+                            uint32_t *a = vza_row + H1_4(col);
-+                            uint32_t *m = vzm + H1_4(col);
-+                            *a = float32_muladd(n, *m, *a, 0, vst);
-+                        }
-+                        col += 4;
-+                        pb >>= 4;
-+                    } while (col & 15);
-+                }
-+            }
-+            row += 4;
-+            pa >>= 4;
-+        } while (row & 15);
-+    }
-+}
-+
-+void HELPER(sme_fmopa_d)(void *vza, void *vzn, void *vzm, void *vpn,
-+                         void *vpm, void *vst, uint32_t desc)
-+{
-+    intptr_t row, col, oprsz = simd_oprsz(desc) / 8;
-+    uint64_t neg = (uint64_t)simd_data(desc) << 63;
-+    uint64_t *za = vza, *zn = vzn, *zm = vzm;
-+    uint8_t *pn = vpn, *pm = vpm;
-+    float_status fpst = *(float_status *)vst;
-+
-+    set_default_nan_mode(true, &fpst);
-+
-+    for (row = 0; row < oprsz; ++row) {
-+        if (pn[H1(row)] & 1) {
-+            uint64_t *za_row = &za[tile_vslice_index(row)];
-+            uint64_t n = zn[row] ^ neg;
-+
-+            for (col = 0; col < oprsz; ++col) {
-+                if (pm[H1(col)] & 1) {
-+                    uint64_t *a = &za_row[col];
-+                    *a = float64_muladd(n, zm[col], *a, 0, &fpst);
-+                }
-+            }
-+        }
-+    }
-+}
-diff --git a/target/arm/translate-sme.c b/target/arm/translate-sme.c
-index XXXXXXX..XXXXXXX 100644
---- a/target/arm/translate-sme.c
-+++ b/target/arm/translate-sme.c
-@@ -XXX,XX +XXX,XX @@ TRANS_FEAT(ADDHA_s, aa64_sme, do_adda, a, MO_32, gen_helper_sme_addha_s)
- TRANS_FEAT(ADDVA_s, aa64_sme, do_adda, a, MO_32, gen_helper_sme_addva_s)
- TRANS_FEAT(ADDHA_d, aa64_sme_i16i64, do_adda, a, MO_64, gen_helper_sme_addha_d)
- TRANS_FEAT(ADDVA_d, aa64_sme_i16i64, do_adda, a, MO_64, gen_helper_sme_addva_d)
-+
-+static bool do_outprod_fpst(DisasContext *s, arg_op *a, MemOp esz,
-+                            gen_helper_gvec_5_ptr *fn)
-+{
-+    int svl = streaming_vec_reg_size(s);
-+    uint32_t desc = simd_desc(svl, svl, a->sub);
-+    TCGv_ptr za, zn, zm, pn, pm, fpst;
-+
-+    if (!sme_smza_enabled_check(s)) {
-+        return true;
-+    }
-+
-+    /* Sum XZR+zad to find ZAd. */
-+    za = get_tile_rowcol(s, esz, 31, a->zad, false);
-+    zn = vec_full_reg_ptr(s, a->zn);
-+    zm = vec_full_reg_ptr(s, a->zm);
-+    pn = pred_full_reg_ptr(s, a->pn);
-+    pm = pred_full_reg_ptr(s, a->pm);
-+    fpst = fpstatus_ptr(FPST_FPCR);
-+
-+    fn(za, zn, zm, pn, pm, fpst, tcg_constant_i32(desc));
-+
-+    tcg_temp_free_ptr(za);
-+    tcg_temp_free_ptr(zn);
-+    tcg_temp_free_ptr(pn);
-+    tcg_temp_free_ptr(pm);
-+    tcg_temp_free_ptr(fpst);
-+    return true;
-+}
-+
-+TRANS_FEAT(FMOPA_s, aa64_sme, do_outprod_fpst, a, MO_32, gen_helper_sme_fmopa_s)
-+TRANS_FEAT(FMOPA_d, aa64_sme_f64f64, do_outprod_fpst, a, MO_64, gen_helper_sme_fmopa_d)
---
-.25.1

-[PULL 25/45] target/arm: Implement BFMOPA, BFMOPS
+Deleted patch
-From: Richard Henderson <richard.henderson@linaro.org>
-Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
-Message-id: 20220708151540.18136-26-richard.henderson@linaro.org
-Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
-Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
----
- target/arm/helper-sme.h    |  2 ++
- target/arm/sme.decode      |  2 ++
- target/arm/sme_helper.c    | 56 ++++++++++++++++++++++++++++++++++++++
- target/arm/translate-sme.c | 30 ++++++++++++++++++++
-files changed, 90 insertions(+)
-diff --git a/target/arm/helper-sme.h b/target/arm/helper-sme.h
-index XXXXXXX..XXXXXXX 100644
---- a/target/arm/helper-sme.h
-+++ b/target/arm/helper-sme.h
-@@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_7(sme_fmopa_s, TCG_CALL_NO_RWG,
-                    void, ptr, ptr, ptr, ptr, ptr, ptr, i32)
- DEF_HELPER_FLAGS_7(sme_fmopa_d, TCG_CALL_NO_RWG,
-                    void, ptr, ptr, ptr, ptr, ptr, ptr, i32)
-+DEF_HELPER_FLAGS_6(sme_bfmopa, TCG_CALL_NO_RWG,
-+                   void, ptr, ptr, ptr, ptr, ptr, i32)
-diff --git a/target/arm/sme.decode b/target/arm/sme.decode
-index XXXXXXX..XXXXXXX 100644
---- a/target/arm/sme.decode
-+++ b/target/arm/sme.decode
-@@ -XXX,XX +XXX,XX @@ ADDVA_d         11000000 11 01000 1 ... ... ..... 00 ...        @adda_64
- FMOPA_s         10000000 100 ..... ... ... ..... . 00 ..        @op_32
- FMOPA_d         10000000 110 ..... ... ... ..... . 0 ...        @op_64
-+
-+BFMOPA          10000001 100 ..... ... ... ..... . 00 ..        @op_32
-diff --git a/target/arm/sme_helper.c b/target/arm/sme_helper.c
-index XXXXXXX..XXXXXXX 100644
---- a/target/arm/sme_helper.c
-+++ b/target/arm/sme_helper.c
-@@ -XXX,XX +XXX,XX @@ void HELPER(sme_fmopa_d)(void *vza, void *vzn, void *vzm, void *vpn,
-         }
-     }
- }
-+
-+/*
-+ * Alter PAIR as needed for controlling predicates being false,
-+ * and for NEG on an enabled row element.
-+ */
-+static inline uint32_t f16mop_adj_pair(uint32_t pair, uint32_t pg, uint32_t neg)
-+{
-+    /*
-+     * The pseudocode uses a conditional negate after the conditional zero.
-+     * It is simpler here to unconditionally negate before conditional zero.
-+     */
-+    pair ^= neg;
-+    if (!(pg & 1)) {
-+        pair &= 0xffff0000u;
-+    }
-+    if (!(pg & 4)) {
-+        pair &= 0x0000ffffu;
-+    }
-+    return pair;
-+}
-+
-+void HELPER(sme_bfmopa)(void *vza, void *vzn, void *vzm, void *vpn,
-+                        void *vpm, uint32_t desc)
-+{
-+    intptr_t row, col, oprsz = simd_maxsz(desc);
-+    uint32_t neg = simd_data(desc) * 0x80008000u;
-+    uint16_t *pn = vpn, *pm = vpm;
-+
-+    for (row = 0; row < oprsz; ) {
-+        uint16_t prow = pn[H2(row >> 4)];
-+        do {
-+            void *vza_row = vza + tile_vslice_offset(row);
-+            uint32_t n = *(uint32_t *)(vzn + H1_4(row));
-+
-+            n = f16mop_adj_pair(n, prow, neg);
-+
-+            for (col = 0; col < oprsz; ) {
-+                uint16_t pcol = pm[H2(col >> 4)];
-+                do {
-+                    if (prow & pcol & 0b0101) {
-+                        uint32_t *a = vza_row + H1_4(col);
-+                        uint32_t m = *(uint32_t *)(vzm + H1_4(col));
-+
-+                        m = f16mop_adj_pair(m, pcol, 0);
-+                        *a = bfdotadd(*a, n, m);
-+
-+                        col += 4;
-+                        pcol >>= 4;
-+                    }
-+                } while (col & 15);
-+            }
-+            row += 4;
-+            prow >>= 4;
-+        } while (row & 15);
-+    }
-+}
-diff --git a/target/arm/translate-sme.c b/target/arm/translate-sme.c
-index XXXXXXX..XXXXXXX 100644
---- a/target/arm/translate-sme.c
-+++ b/target/arm/translate-sme.c
-@@ -XXX,XX +XXX,XX @@ TRANS_FEAT(ADDVA_s, aa64_sme, do_adda, a, MO_32, gen_helper_sme_addva_s)
- TRANS_FEAT(ADDHA_d, aa64_sme_i16i64, do_adda, a, MO_64, gen_helper_sme_addha_d)
- TRANS_FEAT(ADDVA_d, aa64_sme_i16i64, do_adda, a, MO_64, gen_helper_sme_addva_d)
-+static bool do_outprod(DisasContext *s, arg_op *a, MemOp esz,
-+                       gen_helper_gvec_5 *fn)
-+{
-+    int svl = streaming_vec_reg_size(s);
-+    uint32_t desc = simd_desc(svl, svl, a->sub);
-+    TCGv_ptr za, zn, zm, pn, pm;
-+
-+    if (!sme_smza_enabled_check(s)) {
-+        return true;
-+    }
-+
-+    /* Sum XZR+zad to find ZAd. */
-+    za = get_tile_rowcol(s, esz, 31, a->zad, false);
-+    zn = vec_full_reg_ptr(s, a->zn);
-+    zm = vec_full_reg_ptr(s, a->zm);
-+    pn = pred_full_reg_ptr(s, a->pn);
-+    pm = pred_full_reg_ptr(s, a->pm);
-+
-+    fn(za, zn, zm, pn, pm, tcg_constant_i32(desc));
-+
-+    tcg_temp_free_ptr(za);
-+    tcg_temp_free_ptr(zn);
-+    tcg_temp_free_ptr(pn);
-+    tcg_temp_free_ptr(pm);
-+    return true;
-+}
-+
- static bool do_outprod_fpst(DisasContext *s, arg_op *a, MemOp esz,
-                             gen_helper_gvec_5_ptr *fn)
- {
-@@ -XXX,XX +XXX,XX @@ static bool do_outprod_fpst(DisasContext *s, arg_op *a, MemOp esz,
- TRANS_FEAT(FMOPA_s, aa64_sme, do_outprod_fpst, a, MO_32, gen_helper_sme_fmopa_s)
- TRANS_FEAT(FMOPA_d, aa64_sme_f64f64, do_outprod_fpst, a, MO_64, gen_helper_sme_fmopa_d)
-+
-+/* TODO: FEAT_EBF16 */
-+TRANS_FEAT(BFMOPA, aa64_sme, do_outprod, a, MO_32, gen_helper_sme_bfmopa)
---
-.25.1

-[PULL 27/45] target/arm: Implement SME integer outer product
+Deleted patch
-From: Richard Henderson <richard.henderson@linaro.org>
-This is SMOPA, SUMOPA, USMOPA_s, UMOPA, for both Int8 and Int16.
-Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
-Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
-Message-id: 20220708151540.18136-28-richard.henderson@linaro.org
-Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
----
- target/arm/helper-sme.h    | 16 ++++++++
- target/arm/sme.decode      | 10 +++++
- target/arm/sme_helper.c    | 82 ++++++++++++++++++++++++++++++++++++++
- target/arm/translate-sme.c | 10 +++++
-files changed, 118 insertions(+)
-diff --git a/target/arm/helper-sme.h b/target/arm/helper-sme.h
-index XXXXXXX..XXXXXXX 100644
---- a/target/arm/helper-sme.h
-+++ b/target/arm/helper-sme.h
-@@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_7(sme_fmopa_d, TCG_CALL_NO_RWG,
-                    void, ptr, ptr, ptr, ptr, ptr, ptr, i32)
- DEF_HELPER_FLAGS_6(sme_bfmopa, TCG_CALL_NO_RWG,
-                    void, ptr, ptr, ptr, ptr, ptr, i32)
-+DEF_HELPER_FLAGS_6(sme_smopa_s, TCG_CALL_NO_RWG,
-+                   void, ptr, ptr, ptr, ptr, ptr, i32)
-+DEF_HELPER_FLAGS_6(sme_umopa_s, TCG_CALL_NO_RWG,
-+                   void, ptr, ptr, ptr, ptr, ptr, i32)
-+DEF_HELPER_FLAGS_6(sme_sumopa_s, TCG_CALL_NO_RWG,
-+                   void, ptr, ptr, ptr, ptr, ptr, i32)
-+DEF_HELPER_FLAGS_6(sme_usmopa_s, TCG_CALL_NO_RWG,
-+                   void, ptr, ptr, ptr, ptr, ptr, i32)
-+DEF_HELPER_FLAGS_6(sme_smopa_d, TCG_CALL_NO_RWG,
-+                   void, ptr, ptr, ptr, ptr, ptr, i32)
-+DEF_HELPER_FLAGS_6(sme_umopa_d, TCG_CALL_NO_RWG,
-+                   void, ptr, ptr, ptr, ptr, ptr, i32)
-+DEF_HELPER_FLAGS_6(sme_sumopa_d, TCG_CALL_NO_RWG,
-+                   void, ptr, ptr, ptr, ptr, ptr, i32)
-+DEF_HELPER_FLAGS_6(sme_usmopa_d, TCG_CALL_NO_RWG,
-+                   void, ptr, ptr, ptr, ptr, ptr, i32)
-diff --git a/target/arm/sme.decode b/target/arm/sme.decode
-index XXXXXXX..XXXXXXX 100644
---- a/target/arm/sme.decode
-+++ b/target/arm/sme.decode
-@@ -XXX,XX +XXX,XX @@ FMOPA_d         10000000 110 ..... ... ... ..... . 0 ...        @op_64
- BFMOPA          10000001 100 ..... ... ... ..... . 00 ..        @op_32
- FMOPA_h         10000001 101 ..... ... ... ..... . 00 ..        @op_32
-+
-+SMOPA_s         1010000 0 10 0 ..... ... ... ..... . 00 ..      @op_32
-+SUMOPA_s        1010000 0 10 1 ..... ... ... ..... . 00 ..      @op_32
-+USMOPA_s        1010000 1 10 0 ..... ... ... ..... . 00 ..      @op_32
-+UMOPA_s         1010000 1 10 1 ..... ... ... ..... . 00 ..      @op_32
-+
-+SMOPA_d         1010000 0 11 0 ..... ... ... ..... . 0 ...      @op_64
-+SUMOPA_d        1010000 0 11 1 ..... ... ... ..... . 0 ...      @op_64
-+USMOPA_d        1010000 1 11 0 ..... ... ... ..... . 0 ...      @op_64
-+UMOPA_d         1010000 1 11 1 ..... ... ... ..... . 0 ...      @op_64
-diff --git a/target/arm/sme_helper.c b/target/arm/sme_helper.c
-index XXXXXXX..XXXXXXX 100644
---- a/target/arm/sme_helper.c
-+++ b/target/arm/sme_helper.c
-@@ -XXX,XX +XXX,XX @@ void HELPER(sme_bfmopa)(void *vza, void *vzn, void *vzm, void *vpn,
-         } while (row & 15);
-     }
- }
-+
-+typedef uint64_t IMOPFn(uint64_t, uint64_t, uint64_t, uint8_t, bool);
-+
-+static inline void do_imopa(uint64_t *za, uint64_t *zn, uint64_t *zm,
-+                            uint8_t *pn, uint8_t *pm,
-+                            uint32_t desc, IMOPFn *fn)
-+{
-+    intptr_t row, col, oprsz = simd_oprsz(desc) / 8;
-+    bool neg = simd_data(desc);
-+
-+    for (row = 0; row < oprsz; ++row) {
-+        uint8_t pa = pn[H1(row)];
-+        uint64_t *za_row = &za[tile_vslice_index(row)];
-+        uint64_t n = zn[row];
-+
-+        for (col = 0; col < oprsz; ++col) {
-+            uint8_t pb = pm[H1(col)];
-+            uint64_t *a = &za_row[col];
-+
-+            *a = fn(n, zm[col], *a, pa & pb, neg);
-+        }
-+    }
-+}
-+
-+#define DEF_IMOP_32(NAME, NTYPE, MTYPE) \
-+static uint64_t NAME(uint64_t n, uint64_t m, uint64_t a, uint8_t p, bool neg) \
-+{                                                                           \
-+    uint32_t sum0 = 0, sum1 = 0;                                            \
-+    /* Apply P to N as a mask, making the inactive elements 0. */           \
-+    n &= expand_pred_b(p);                                                  \
-+    sum0 += (NTYPE)(n >> 0) * (MTYPE)(m >> 0);                              \
-+    sum0 += (NTYPE)(n >> 8) * (MTYPE)(m >> 8);                              \
-+    sum0 += (NTYPE)(n >> 16) * (MTYPE)(m >> 16);                            \
-+    sum0 += (NTYPE)(n >> 24) * (MTYPE)(m >> 24);                            \
-+    sum1 += (NTYPE)(n >> 32) * (MTYPE)(m >> 32);                            \
-+    sum1 += (NTYPE)(n >> 40) * (MTYPE)(m >> 40);                            \
-+    sum1 += (NTYPE)(n >> 48) * (MTYPE)(m >> 48);                            \
-+    sum1 += (NTYPE)(n >> 56) * (MTYPE)(m >> 56);                            \
-+    if (neg) {                                                              \
-+        sum0 = (uint32_t)a - sum0, sum1 = (uint32_t)(a >> 32) - sum1;       \
-+    } else {                                                                \
-+        sum0 = (uint32_t)a + sum0, sum1 = (uint32_t)(a >> 32) + sum1;       \
-+    }                                                                       \
-+    return ((uint64_t)sum1 << 32) | sum0;                                   \
-+}
-+
-+#define DEF_IMOP_64(NAME, NTYPE, MTYPE) \
-+static uint64_t NAME(uint64_t n, uint64_t m, uint64_t a, uint8_t p, bool neg) \
-+{                                                                           \
-+    uint64_t sum = 0;                                                       \
-+    /* Apply P to N as a mask, making the inactive elements 0. */           \
-+    n &= expand_pred_h(p);                                                  \
-+    sum += (NTYPE)(n >> 0) * (MTYPE)(m >> 0);                               \
-+    sum += (NTYPE)(n >> 16) * (MTYPE)(m >> 16);                             \
-+    sum += (NTYPE)(n >> 32) * (MTYPE)(m >> 32);                             \
-+    sum += (NTYPE)(n >> 48) * (MTYPE)(m >> 48);                             \
-+    return neg ? a - sum : a + sum;                                         \
-+}
-+
-+DEF_IMOP_32(smopa_s, int8_t, int8_t)
-+DEF_IMOP_32(umopa_s, uint8_t, uint8_t)
-+DEF_IMOP_32(sumopa_s, int8_t, uint8_t)
-+DEF_IMOP_32(usmopa_s, uint8_t, int8_t)
-+
-+DEF_IMOP_64(smopa_d, int16_t, int16_t)
-+DEF_IMOP_64(umopa_d, uint16_t, uint16_t)
-+DEF_IMOP_64(sumopa_d, int16_t, uint16_t)
-+DEF_IMOP_64(usmopa_d, uint16_t, int16_t)
-+
-+#define DEF_IMOPH(NAME) \
-+    void HELPER(sme_##NAME)(void *vza, void *vzn, void *vzm, void *vpn,      \
-+                            void *vpm, uint32_t desc)                        \
-+    { do_imopa(vza, vzn, vzm, vpn, vpm, desc, NAME); }
-+
-+DEF_IMOPH(smopa_s)
-+DEF_IMOPH(umopa_s)
-+DEF_IMOPH(sumopa_s)
-+DEF_IMOPH(usmopa_s)
-+DEF_IMOPH(smopa_d)
-+DEF_IMOPH(umopa_d)
-+DEF_IMOPH(sumopa_d)
-+DEF_IMOPH(usmopa_d)
-diff --git a/target/arm/translate-sme.c b/target/arm/translate-sme.c
-index XXXXXXX..XXXXXXX 100644
---- a/target/arm/translate-sme.c
-+++ b/target/arm/translate-sme.c
-@@ -XXX,XX +XXX,XX @@ TRANS_FEAT(FMOPA_d, aa64_sme_f64f64, do_outprod_fpst, a, MO_64, gen_helper_sme_f
- /* TODO: FEAT_EBF16 */
- TRANS_FEAT(BFMOPA, aa64_sme, do_outprod, a, MO_32, gen_helper_sme_bfmopa)
-+
-+TRANS_FEAT(SMOPA_s, aa64_sme, do_outprod, a, MO_32, gen_helper_sme_smopa_s)
-+TRANS_FEAT(UMOPA_s, aa64_sme, do_outprod, a, MO_32, gen_helper_sme_umopa_s)
-+TRANS_FEAT(SUMOPA_s, aa64_sme, do_outprod, a, MO_32, gen_helper_sme_sumopa_s)
-+TRANS_FEAT(USMOPA_s, aa64_sme, do_outprod, a, MO_32, gen_helper_sme_usmopa_s)
-+
-+TRANS_FEAT(SMOPA_d, aa64_sme_i16i64, do_outprod, a, MO_64, gen_helper_sme_smopa_d)
-+TRANS_FEAT(UMOPA_d, aa64_sme_i16i64, do_outprod, a, MO_64, gen_helper_sme_umopa_d)
-+TRANS_FEAT(SUMOPA_d, aa64_sme_i16i64, do_outprod, a, MO_64, gen_helper_sme_sumopa_d)
-+TRANS_FEAT(USMOPA_d, aa64_sme_i16i64, do_outprod, a, MO_64, gen_helper_sme_usmopa_d)
---
-.25.1

-[PULL 28/45] target/arm: Implement PSEL
+Deleted patch
-From: Richard Henderson <richard.henderson@linaro.org>
-This is an SVE instruction that operates using the SVE vector
-length but that it is present only if SME is implemented.
-Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
-Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
-Message-id: 20220708151540.18136-29-richard.henderson@linaro.org
-Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
----
- target/arm/sve.decode      | 20 +++++++++++++
- target/arm/translate-sve.c | 57 ++++++++++++++++++++++++++++++++++++++
-files changed, 77 insertions(+)
-diff --git a/target/arm/sve.decode b/target/arm/sve.decode
-index XXXXXXX..XXXXXXX 100644
---- a/target/arm/sve.decode
-+++ b/target/arm/sve.decode
-@@ -XXX,XX +XXX,XX @@ BFMLALT_zzxw    01100100 11 1 ..... 0100.1 ..... .....     @rrxr_3a esz=2
- ### SVE2 floating-point bfloat16 dot-product (indexed)
- BFDOT_zzxz      01100100 01 1 ..... 010000 ..... .....     @rrxr_2 esz=2
-+
-+### SVE broadcast predicate element
-+
-+&psel           esz pd pn pm rv imm
-+%psel_rv        16:2 !function=plus_12
-+%psel_imm_b     22:2 19:2
-+%psel_imm_h     22:2 20:1
-+%psel_imm_s     22:2
-+%psel_imm_d     23:1
-+@psel           ........ .. . ... .. .. pn:4 . pm:4 . pd:4  \
-+                &psel rv=%psel_rv
-+
-+PSEL            00100101 .. 1 ..1 .. 01 .... 0 .... 0 ....  \
-+                @psel esz=0 imm=%psel_imm_b
-+PSEL            00100101 .. 1 .10 .. 01 .... 0 .... 0 ....  \
-+                @psel esz=1 imm=%psel_imm_h
-+PSEL            00100101 .. 1 100 .. 01 .... 0 .... 0 ....  \
-+                @psel esz=2 imm=%psel_imm_s
-+PSEL            00100101 .1 1 000 .. 01 .... 0 .... 0 ....  \
-+                @psel esz=3 imm=%psel_imm_d
-diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
-index XXXXXXX..XXXXXXX 100644
---- a/target/arm/translate-sve.c
-+++ b/target/arm/translate-sve.c
-@@ -XXX,XX +XXX,XX @@ static bool do_BFMLAL_zzxw(DisasContext *s, arg_rrxr_esz *a, bool sel)
- TRANS_FEAT(BFMLALB_zzxw, aa64_sve_bf16, do_BFMLAL_zzxw, a, false)
- TRANS_FEAT(BFMLALT_zzxw, aa64_sve_bf16, do_BFMLAL_zzxw, a, true)
-+
-+static bool trans_PSEL(DisasContext *s, arg_psel *a)
-+{
-+    int vl = vec_full_reg_size(s);
-+    int pl = pred_gvec_reg_size(s);
-+    int elements = vl >> a->esz;
-+    TCGv_i64 tmp, didx, dbit;
-+    TCGv_ptr ptr;
-+
-+    if (!dc_isar_feature(aa64_sme, s)) {
-+        return false;
-+    }
-+    if (!sve_access_check(s)) {
-+        return true;
-+    }
-+
-+    tmp = tcg_temp_new_i64();
-+    dbit = tcg_temp_new_i64();
-+    didx = tcg_temp_new_i64();
-+    ptr = tcg_temp_new_ptr();
-+
-+    /* Compute the predicate element. */
-+    tcg_gen_addi_i64(tmp, cpu_reg(s, a->rv), a->imm);
-+    if (is_power_of_2(elements)) {
-+        tcg_gen_andi_i64(tmp, tmp, elements - 1);
-+    } else {
-+        tcg_gen_remu_i64(tmp, tmp, tcg_constant_i64(elements));
-+    }
-+
-+    /* Extract the predicate byte and bit indices. */
-+    tcg_gen_shli_i64(tmp, tmp, a->esz);
-+    tcg_gen_andi_i64(dbit, tmp, 7);
-+    tcg_gen_shri_i64(didx, tmp, 3);
-+    if (HOST_BIG_ENDIAN) {
-+        tcg_gen_xori_i64(didx, didx, 7);
-+    }
-+
-+    /* Load the predicate word. */
-+    tcg_gen_trunc_i64_ptr(ptr, didx);
-+    tcg_gen_add_ptr(ptr, ptr, cpu_env);
-+    tcg_gen_ld8u_i64(tmp, ptr, pred_full_reg_offset(s, a->pm));
-+
-+    /* Extract the predicate bit and replicate to MO_64. */
-+    tcg_gen_shr_i64(tmp, tmp, dbit);
-+    tcg_gen_andi_i64(tmp, tmp, 1);
-+    tcg_gen_neg_i64(tmp, tmp);
-+
-+    /* Apply to either copy the source, or write zeros. */
-+    tcg_gen_gvec_ands(MO_64, pred_full_reg_offset(s, a->pd),
-+                      pred_full_reg_offset(s, a->pn), tmp, pl, pl);
-+
-+    tcg_temp_free_i64(tmp);
-+    tcg_temp_free_i64(dbit);
-+    tcg_temp_free_i64(didx);
-+    tcg_temp_free_ptr(ptr);
-+    return true;
-+}
---
-.25.1

-[PULL 39/45] linux-user/aarch64: Move sve record checks into restore
+[PULL 24/24] hw/arm: Set number of MPU regions correctly for an505, an521, an524
-From: Richard Henderson <richard.henderson@linaro.org>
+The IoTKit, SSE200 and SSE300 all default to 8 MPU regions.  The
+MPS2/MPS3 FPGA images don't override these except in the case of
-Move the checks out of the parsing loop and into the
+AN547, which uses 16 MPU regions.
-restore function.  This more closely mirrors the code
-structure in the kernel, and is slightly clearer.
+Define properties on the ARMSSE object for the MPU regions (using the
+same names as the documented RTL configuration settings, and
-Reject rather than silently skip incorrect VL and SVE record sizes,
+following the pattern we already have for this device of using
-bringing our checks in to line with those the kernel does.
+all-caps names as the RTL does), and set them in the board code.
-Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
+We don't actually need to override the default except on AN547,
-Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
+but it's simpler code to have the board code set them always
-Message-id: 20220708151540.18136-40-richard.henderson@linaro.org
+rather than tracking which board subtypes want to set them to
 a non-default value separately from what that value is.
 Tho overall effect is that for mps2-an505, mps2-an521 and mps3-an524
 we now correctly use 8 MPU regions, while mps3-an547 stays at its
 current 16 regions.
 It's possible some guest code wrongly depended on the previous
 incorrectly modeled number of memory regions. (Such guest code
 should ideally check the number of regions via the MPU_TYPE
 register.) The old behaviour can be obtained with additional
 -global arguments to QEMU:
 For mps2-an521 and mps2-an524:
  -global sse-200.CPU0_MPU_NS=16 -global sse-200.CPU0_MPU_S=16 -global sse-200.CPU1_MPU_NS=16 -global sse-200.CPU1_MPU_S=16
 For mps2-an505:
  -global sse-200.CPU0_MPU_NS=16 -global sse-200.CPU0_MPU_S=16
 NB that the way the implementation allows this use of -global
 is slightly fragile: if the board code explicitly sets the
 properties on the sse-200 object, this overrides the -global
 command line option. So we rely on:
  - the boards that need fixing all happen to use the SSE defaults
  - we can write the board code to only set the property if it
    is different from the default, rather than having all boards
    explicitly set the property
  - the board that does need to use a non-default value happens
    to need to set it to the same value (16) we previously used
 This works, but there are some kinds of refactoring of the
 mps2-tz.c code that would break the support for -global here.
 Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1772
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
+Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
+Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
+Message-id: 20230724174335.2150499-4-peter.maydell@linaro.org
 ---
- linux-user/aarch64/signal.c | 51 +++++++++++++++++++++++++------------
+ include/hw/arm/armsse.h |  5 +++++
-file changed, 35 insertions(+), 16 deletions(-)
+ hw/arm/armsse.c         | 16 ++++++++++++++++
+ hw/arm/mps2-tz.c        | 29 +++++++++++++++++++++++++++++
-diff --git a/linux-user/aarch64/signal.c b/linux-user/aarch64/signal.c
+files changed, 50 insertions(+)
 diff --git a/include/hw/arm/armsse.h b/include/hw/arm/armsse.h
 index XXXXXXX..XXXXXXX 100644
---- a/linux-user/aarch64/signal.c
+--- a/include/hw/arm/armsse.h
-+++ b/linux-user/aarch64/signal.c
++++ b/include/hw/arm/armsse.h
-@@ -XXX,XX +XXX,XX @@ static void target_restore_fpsimd_record(CPUARMState *env,
+@@ -XXX,XX +XXX,XX @@
-     }
+  *    (matching the hardware) is that for CPU0 in an IoTKit and CPU1 in an
- }
+  *    SSE-200 both are present; CPU0 in an SSE-200 has neither.
+  *    Since the IoTKit has only one CPU, it does not have the CPU1_* properties.
--static void target_restore_sve_record(CPUARMState *env,
++ *  + QOM properties "CPU0_MPU_NS", "CPU0_MPU_S", "CPU1_MPU_NS" and "CPU1_MPU_S"
--                                      struct target_sve_context *sve, int vq)
++ *    which set the number of MPU regions on the CPUs. If there is only one
-+static bool target_restore_sve_record(CPUARMState *env,
++ *    CPU the CPU1 properties are not present.
-+                                      struct target_sve_context *sve,
+  *  + Named GPIO inputs "EXP_IRQ" 0..n are the expansion interrupts for CPU 0,
-+                                      int size)
+  *    which are wired to its NVIC lines 32 .. n+32
- {
+  *  + Named GPIO inputs "EXP_CPU1_IRQ" 0..n are the expansion interrupts for
--    int i, j;
+@@ -XXX,XX +XXX,XX @@ struct ARMSSE {
-+    int i, j, vl, vq;
+     uint32_t exp_numirq;
+     uint32_t sram_addr_width;
--    /* Note that SVE regs are stored as a byte stream, with each byte element
+     uint32_t init_svtor;
-+    if (!cpu_isar_feature(aa64_sve, env_archcpu(env))) {
++    uint32_t cpu_mpu_ns[SSE_MAX_CPUS];
-+        return false;
++    uint32_t cpu_mpu_s[SSE_MAX_CPUS];
-+    }
+     bool cpu_fpu[SSE_MAX_CPUS];
-+
+     bool cpu_dsp[SSE_MAX_CPUS];
-+    __get_user(vl, &sve->vl);
+ };
-+    vq = sve_vq(env);
+diff --git a/hw/arm/armsse.c b/hw/arm/armsse.c
-+
+index XXXXXXX..XXXXXXX 100644
-+    /* Reject mismatched VL. */
+--- a/hw/arm/armsse.c
-+    if (vl != vq * TARGET_SVE_VQ_BYTES) {
++++ b/hw/arm/armsse.c
-+        return false;
+@@ -XXX,XX +XXX,XX @@ static Property iotkit_properties[] = {
-+    }
+     DEFINE_PROP_UINT32("init-svtor", ARMSSE, init_svtor, 0x10000000),
-+
+     DEFINE_PROP_BOOL("CPU0_FPU", ARMSSE, cpu_fpu[0], true),
-+    /* Accept empty record -- used to clear PSTATE.SM. */
+     DEFINE_PROP_BOOL("CPU0_DSP", ARMSSE, cpu_dsp[0], true),
-+    if (size <= sizeof(*sve)) {
++    DEFINE_PROP_UINT32("CPU0_MPU_NS", ARMSSE, cpu_mpu_ns[0], 8),
-+        return true;
++    DEFINE_PROP_UINT32("CPU0_MPU_S", ARMSSE, cpu_mpu_s[0], 8),
-+    }
+     DEFINE_PROP_END_OF_LIST()
-+
+ };
-+    /* Reject non-empty but incomplete record. */
-+    if (size < TARGET_SVE_SIG_CONTEXT_SIZE(vq)) {
+@@ -XXX,XX +XXX,XX @@ static Property sse200_properties[] = {
-+        return false;
+     DEFINE_PROP_BOOL("CPU0_DSP", ARMSSE, cpu_dsp[0], false),
-+    }
+     DEFINE_PROP_BOOL("CPU1_FPU", ARMSSE, cpu_fpu[1], true),
-+
+     DEFINE_PROP_BOOL("CPU1_DSP", ARMSSE, cpu_dsp[1], true),
-+    /*
++    DEFINE_PROP_UINT32("CPU0_MPU_NS", ARMSSE, cpu_mpu_ns[0], 8),
-+     * Note that SVE regs are stored as a byte stream, with each byte element
++    DEFINE_PROP_UINT32("CPU0_MPU_S", ARMSSE, cpu_mpu_s[0], 8),
-      * at a subsequent address.  This corresponds to a little-endian load
++    DEFINE_PROP_UINT32("CPU1_MPU_NS", ARMSSE, cpu_mpu_ns[1], 8),
-      * of our 64-bit hunks.
++    DEFINE_PROP_UINT32("CPU1_MPU_S", ARMSSE, cpu_mpu_s[1], 8),
-      */
+     DEFINE_PROP_END_OF_LIST()
-@@ -XXX,XX +XXX,XX @@ static void target_restore_sve_record(CPUARMState *env,
+ };
@@ -XXX,XX +XXX,XX @@ static Property sse300_properties[] = {
      DEFINE_PROP_UINT32("init-svtor", ARMSSE, init_svtor, 0x10000000),
      DEFINE_PROP_BOOL("CPU0_FPU", ARMSSE, cpu_fpu[0], true),
      DEFINE_PROP_BOOL("CPU0_DSP", ARMSSE, cpu_dsp[0], true),
 +    DEFINE_PROP_UINT32("CPU0_MPU_NS", ARMSSE, cpu_mpu_ns[0], 8),
 +    DEFINE_PROP_UINT32("CPU0_MPU_S", ARMSSE, cpu_mpu_s[0], 8),
      DEFINE_PROP_END_OF_LIST()
  };
@@ -XXX,XX +XXX,XX @@ static void armsse_realize(DeviceState *dev, Error **errp)
                  return;
              }
          }
-     }
++        if (!object_property_set_uint(cpuobj, "mpu-ns-regions",
-+    return true;
++                                      s->cpu_mpu_ns[i], errp)) {
 +            return;
 +        }
 +        if (!object_property_set_uint(cpuobj, "mpu-s-regions",
 +                                      s->cpu_mpu_s[i], errp)) {
 +            return;
 +        }
          if (i > 0) {
              memory_region_add_subregion_overlap(&s->cpu_container[i], 0,
 diff --git a/hw/arm/mps2-tz.c b/hw/arm/mps2-tz.c
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/arm/mps2-tz.c
 +++ b/hw/arm/mps2-tz.c
@@ -XXX,XX +XXX,XX @@ struct MPS2TZMachineClass {
      int uart_overflow_irq; /* number of the combined UART overflow IRQ */
      uint32_t init_svtor; /* init-svtor setting for SSE */
      uint32_t sram_addr_width; /* SRAM_ADDR_WIDTH setting for SSE */
 +    uint32_t cpu0_mpu_ns; /* CPU0_MPU_NS setting for SSE */
 +    uint32_t cpu0_mpu_s; /* CPU0_MPU_S setting for SSE */
 +    uint32_t cpu1_mpu_ns; /* CPU1_MPU_NS setting for SSE */
 +    uint32_t cpu1_mpu_s; /* CPU1_MPU_S setting for SSE */
      const RAMInfo *raminfo;
      const char *armsse_type;
      uint32_t boot_ram_size; /* size of ram at address 0; 0 == find in raminfo */
@@ -XXX,XX +XXX,XX @@ OBJECT_DECLARE_TYPE(MPS2TZMachineState, MPS2TZMachineClass, MPS2TZ_MACHINE)
  #define MPS3_DDR_SIZE (2 * GiB)
  #endif
 +/* For cpu{0,1}_mpu_{ns,s}, means "leave at SSE's default value" */
 +#define MPU_REGION_DEFAULT UINT32_MAX
 +
  static const uint32_t an505_oscclk[] = {
      40000000,
      24580000,
@@ -XXX,XX +XXX,XX @@ static void mps2tz_common_init(MachineState *machine)
                               OBJECT(system_memory), &error_abort);
      qdev_prop_set_uint32(iotkitdev, "EXP_NUMIRQ", mmc->numirq);
      qdev_prop_set_uint32(iotkitdev, "init-svtor", mmc->init_svtor);
 +    if (mmc->cpu0_mpu_ns != MPU_REGION_DEFAULT) {
 +        qdev_prop_set_uint32(iotkitdev, "CPU0_MPU_NS", mmc->cpu0_mpu_ns);
 +    }
 +    if (mmc->cpu0_mpu_s != MPU_REGION_DEFAULT) {
 +        qdev_prop_set_uint32(iotkitdev, "CPU0_MPU_S", mmc->cpu0_mpu_s);
 +    }
 +    if (object_property_find(OBJECT(iotkitdev), "CPU1_MPU_NS")) {
 +        if (mmc->cpu1_mpu_ns != MPU_REGION_DEFAULT) {
 +            qdev_prop_set_uint32(iotkitdev, "CPU1_MPU_NS", mmc->cpu1_mpu_ns);
 +        }
 +        if (mmc->cpu1_mpu_s != MPU_REGION_DEFAULT) {
 +            qdev_prop_set_uint32(iotkitdev, "CPU1_MPU_S", mmc->cpu1_mpu_s);
 +        }
 +    }
      qdev_prop_set_uint32(iotkitdev, "SRAM_ADDR_WIDTH", mmc->sram_addr_width);
      qdev_connect_clock_in(iotkitdev, "MAINCLK", mms->sysclk);
      qdev_connect_clock_in(iotkitdev, "S32KCLK", mms->s32kclk);
@@ -XXX,XX +XXX,XX @@ static void mps2tz_class_init(ObjectClass *oc, void *data)
  {
      MachineClass *mc = MACHINE_CLASS(oc);
      IDAUInterfaceClass *iic = IDAU_INTERFACE_CLASS(oc);
 +    MPS2TZMachineClass *mmc = MPS2TZ_MACHINE_CLASS(oc);
      mc->init = mps2tz_common_init;
      mc->reset = mps2_machine_reset;
      iic->check = mps2_tz_idau_check;
 +
 +    /* Most machines leave these at the SSE defaults */
 +    mmc->cpu0_mpu_ns = MPU_REGION_DEFAULT;
 +    mmc->cpu0_mpu_s = MPU_REGION_DEFAULT;
 +    mmc->cpu1_mpu_ns = MPU_REGION_DEFAULT;
 +    mmc->cpu1_mpu_s = MPU_REGION_DEFAULT;
  }
- static int target_restore_sigframe(CPUARMState *env,
+ static void mps2tz_set_default_ram_info(MPS2TZMachineClass *mmc)
-@@ -XXX,XX +XXX,XX @@ static int target_restore_sigframe(CPUARMState *env,
+@@ -XXX,XX +XXX,XX @@ static void mps3tz_an547_class_init(ObjectClass *oc, void *data)
-     struct target_sve_context *sve = NULL;
+     mmc->numirq = 96;
-     uint64_t extra_datap = 0;
+     mmc->uart_overflow_irq = 48;
-     bool used_extra = false;
+     mmc->init_svtor = 0x00000000;
--    int vq = 0, sve_size = 0;
++    mmc->cpu0_mpu_s = mmc->cpu0_mpu_ns = 16;
-+    int sve_size = 0;
+     mmc->sram_addr_width = 21;
+     mmc->raminfo = an547_raminfo;
-     target_restore_general_frame(env, sf);
+     mmc->armsse_type = TYPE_SSE300;
@@ -XXX,XX +XXX,XX @@ static int target_restore_sigframe(CPUARMState *env,
              if (sve || size < sizeof(struct target_sve_context)) {
                  goto err;
              }
 -            if (cpu_isar_feature(aa64_sve, env_archcpu(env))) {
 -                vq = sve_vq(env);
 -                sve_size = QEMU_ALIGN_UP(TARGET_SVE_SIG_CONTEXT_SIZE(vq), 16);
 -                if (size == sve_size) {
 -                    sve = (struct target_sve_context *)ctx;
 -                    break;
 -                }
 -            }
 -            goto err;
 +            sve = (struct target_sve_context *)ctx;
 +            sve_size = size;
 +            break;
          case TARGET_EXTRA_MAGIC:
              if (extra || size != sizeof(struct target_extra_context)) {
@@ -XXX,XX +XXX,XX @@ static int target_restore_sigframe(CPUARMState *env,
      }
      /* SVE data, if present, overwrites FPSIMD data.  */
 -    if (sve) {
 -        target_restore_sve_record(env, sve, vq);
 +    if (sve && !target_restore_sve_record(env, sve, sve_size)) {
 +        goto err;
      }
      unlock_user(extra, extra_datap, 0);
      return 0;
 --
-.25.1
+.34.1

I don't have anything else queued up at the moment, so this is just
Richard's SME patches.

-- PMM

The following changes since commit 63b38f6c85acd312c2cab68554abf33adf4ee2b3:

Merge tag 'pull-target-arm-20220707' of https://git.linaro.org/people/pmaydell/qemu-arm into staging (2022-07-08 06:17:11 +0530)

are available in the Git repository at:

https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20220711

for you to fetch changes up to f9982ceaf26df27d15547a3a7990a95019e9e3a8:

linux-user/aarch64: Add SME related hwcap entries (2022-07-11 13:43:52 +0100)

----------------------------------------------------------------
target-arm:
 * Implement SME emulation, for both system and linux-user

----------------------------------------------------------------
Richard Henderson (45):
      target/arm: Handle SME in aarch64_cpu_dump_state
      target/arm: Add infrastructure for disas_sme
      target/arm: Trap non-streaming usage when Streaming SVE is active
      target/arm: Mark ADR as non-streaming
      target/arm: Mark RDFFR, WRFFR, SETFFR as non-streaming
      target/arm: Mark BDEP, BEXT, BGRP, COMPACT, FEXPA, FTSSEL as non-streaming
      target/arm: Mark PMULL, FMMLA as non-streaming
      target/arm: Mark FTSMUL, FTMAD, FADDA as non-streaming
      target/arm: Mark SMMLA, UMMLA, USMMLA as non-streaming
      target/arm: Mark string/histo/crypto as non-streaming
      target/arm: Mark gather/scatter load/store as non-streaming
      target/arm: Mark gather prefetch as non-streaming
      target/arm: Mark LDFF1 and LDNF1 as non-streaming
      target/arm: Mark LD1RO as non-streaming
      target/arm: Add SME enablement checks
      target/arm: Handle SME in sve_access_check
      target/arm: Implement SME RDSVL, ADDSVL, ADDSPL
      target/arm: Implement SME ZERO
      target/arm: Implement SME MOVA
      target/arm: Implement SME LD1, ST1
      target/arm: Export unpredicated ld/st from translate-sve.c
      target/arm: Implement SME LDR, STR
      target/arm: Implement SME ADDHA, ADDVA
      target/arm: Implement FMOPA, FMOPS (non-widening)
      target/arm: Implement BFMOPA, BFMOPS
      target/arm: Implement FMOPA, FMOPS (widening)
      target/arm: Implement SME integer outer product
      target/arm: Implement PSEL
      target/arm: Implement REVD
      target/arm: Implement SCLAMP, UCLAMP
      target/arm: Reset streaming sve state on exception boundaries
      target/arm: Enable SME for -cpu max
      linux-user/aarch64: Clear tpidr2_el0 if CLONE_SETTLS
      linux-user/aarch64: Reset PSTATE.SM on syscalls
      linux-user/aarch64: Add SM bit to SVE signal context
      linux-user/aarch64: Tidy target_restore_sigframe error return
      linux-user/aarch64: Do not allow duplicate or short sve records
      linux-user/aarch64: Verify extra record lock succeeded
      linux-user/aarch64: Move sve record checks into restore
      linux-user/aarch64: Implement SME signal handling
      linux-user: Rename sve prctls
      linux-user/aarch64: Implement PR_SME_GET_VL, PR_SME_SET_VL
      target/arm: Only set ZEN in reset if SVE present
      target/arm: Enable SME for user-only
      linux-user/aarch64: Add SME related hwcap entries

From: Richard Henderson <richard.henderson@linaro.org>

Dump SVCR, plus use the correct access check for Streaming Mode.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220708151540.18136-2-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/cpu.c | 17 ++++++++++++++++-
 1 file changed, 16 insertions(+), 1 deletion(-)

diff --git a/target/arm/cpu.c b/target/arm/cpu.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/cpu.c
+++ b/target/arm/cpu.c
@@ -XXX,XX +XXX,XX @@ static void aarch64_cpu_dump_state(CPUState *cs, FILE *f, int flags)
     int i;
     int el = arm_current_el(env);
     const char *ns_status;
+    bool sve;
 
     qemu_fprintf(f, " PC=%016" PRIx64 " ", env->pc);
     for (i = 0; i < 32; i++) {
@@ -XXX,XX +XXX,XX @@ static void aarch64_cpu_dump_state(CPUState *cs, FILE *f, int flags)
                  el,
                  psr & PSTATE_SP ? 'h' : 't');
 
+    if (cpu_isar_feature(aa64_sme, cpu)) {
+        qemu_fprintf(f, "  SVCR=%08" PRIx64 " %c%c",
+                     env->svcr,
+                     (FIELD_EX64(env->svcr, SVCR, ZA) ? 'Z' : '-'),
+                     (FIELD_EX64(env->svcr, SVCR, SM) ? 'S' : '-'));
+    }
     if (cpu_isar_feature(aa64_bti, cpu)) {
         qemu_fprintf(f, "  BTYPE=%d", (psr & PSTATE_BTYPE) >> 10);
     }
@@ -XXX,XX +XXX,XX @@ static void aarch64_cpu_dump_state(CPUState *cs, FILE *f, int flags)
     qemu_fprintf(f, "     FPCR=%08x FPSR=%08x\n",
                  vfp_get_fpcr(env), vfp_get_fpsr(env));
 
-    if (cpu_isar_feature(aa64_sve, cpu) && sve_exception_el(env, el) == 0) {
+    if (cpu_isar_feature(aa64_sme, cpu) && FIELD_EX64(env->svcr, SVCR, SM)) {
+        sve = sme_exception_el(env, el) == 0;
+    } else if (cpu_isar_feature(aa64_sve, cpu)) {
+        sve = sve_exception_el(env, el) == 0;
+    } else {
+        sve = false;
+    }
+
+    if (sve) {
         int j, zcr_len = sve_vqm1_for_el(env, el);
 
         for (i = 0; i <= FFR_PRED_NUM; i++) {
-- 
2.25.1

From: Richard Henderson <richard.henderson@linaro.org>

This includes the build rules for the decoder, and the
new file for translation, but excludes any instructions.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220708151540.18136-3-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/translate-a64.h |  1 +
 target/arm/sme.decode      | 20 ++++++++++++++++++++
 target/arm/translate-a64.c |  7 ++++++-
 target/arm/translate-sme.c | 35 +++++++++++++++++++++++++++++++++++
 target/arm/meson.build     |  2 ++
 5 files changed, 64 insertions(+), 1 deletion(-)
 create mode 100644 target/arm/sme.decode
 create mode 100644 target/arm/translate-sme.c

diff --git a/target/arm/translate-a64.h b/target/arm/translate-a64.h
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/translate-a64.h
+++ b/target/arm/translate-a64.h
@@ -XXX,XX +XXX,XX @@ static inline int pred_gvec_reg_size(DisasContext *s)
 }
 
 bool disas_sve(DisasContext *, uint32_t);
+bool disas_sme(DisasContext *, uint32_t);
 
 void gen_gvec_rax1(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs,
                    uint32_t rm_ofs, uint32_t opr_sz, uint32_t max_sz);
diff --git a/target/arm/sme.decode b/target/arm/sme.decode
new file mode 100644
index XXXXXXX..XXXXXXX
--- /dev/null
+++ b/target/arm/sme.decode
@@ -XXX,XX +XXX,XX @@
+# AArch64 SME instruction descriptions
+#
+#  Copyright (c) 2022 Linaro, Ltd
+#
+# This library is free software; you can redistribute it and/or
+# modify it under the terms of the GNU Lesser General Public
+# License as published by the Free Software Foundation; either
+# version 2.1 of the License, or (at your option) any later version.
+#
+# This library is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+# Lesser General Public License for more details.
+#
+# You should have received a copy of the GNU Lesser General Public
+# License along with this library; if not, see <http://www.gnu.org/licenses/>.
+
+#
+# This file is processed by scripts/decodetree.py
+#
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/translate-a64.c
+++ b/target/arm/translate-a64.c
@@ -XXX,XX +XXX,XX @@ static void aarch64_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu)
     }
 
     switch (extract32(insn, 25, 4)) {
-    case 0x0: case 0x1: case 0x3: /* UNALLOCATED */
+    case 0x0:
+        if (!extract32(insn, 31, 1) || !disas_sme(s, insn)) {
+            unallocated_encoding(s);
+        }
+        break;
+    case 0x1: case 0x3: /* UNALLOCATED */
         unallocated_encoding(s);
         break;
     case 0x2:
diff --git a/target/arm/translate-sme.c b/target/arm/translate-sme.c
new file mode 100644
index XXXXXXX..XXXXXXX
--- /dev/null
+++ b/target/arm/translate-sme.c
@@ -XXX,XX +XXX,XX @@
+/*
+ * AArch64 SME translation
+ *
+ * Copyright (c) 2022 Linaro, Ltd
+ *
+ * This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU Lesser General Public
+ * License as published by the Free Software Foundation; either
+ * version 2.1 of the License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+ * Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public
+ * License along with this library; if not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include "qemu/osdep.h"
+#include "cpu.h"
+#include "tcg/tcg-op.h"
+#include "tcg/tcg-op-gvec.h"
+#include "tcg/tcg-gvec-desc.h"
+#include "translate.h"
+#include "exec/helper-gen.h"
+#include "translate-a64.h"
+#include "fpu/softfloat.h"
+
+
+/*
+ * Include the generated decoder.
+ */
+
+#include "decode-sme.c.inc"
diff --git a/target/arm/meson.build b/target/arm/meson.build
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/meson.build
+++ b/target/arm/meson.build
@@ -XXX,XX +XXX,XX @@
 gen = [
   decodetree.process('sve.decode', extra_args: '--decode=disas_sve'),
+  decodetree.process('sme.decode', extra_args: '--decode=disas_sme'),
   decodetree.process('neon-shared.decode', extra_args: '--decode=disas_neon_shared'),
   decodetree.process('neon-dp.decode', extra_args: '--decode=disas_neon_dp'),
   decodetree.process('neon-ls.decode', extra_args: '--decode=disas_neon_ls'),
@@ -XXX,XX +XXX,XX @@ arm_ss.add(when: 'TARGET_AARCH64', if_true: files(
   'sme_helper.c',
   'translate-a64.c',
   'translate-sve.c',
+  'translate-sme.c',
 ))
 
 arm_softmmu_ss = ss.source_set()
-- 
2.25.1

From: Richard Henderson <richard.henderson@linaro.org>

This new behaviour is in the ARM pseudocode function
AArch64.CheckFPAdvSIMDEnabled, which applies to AArch32
via AArch32.CheckAdvSIMDOrFPEnabled when the EL to which
the trap would be delivered is in AArch64 mode.

Given that ARMv9 drops support for AArch32 outside EL0, the trap EL
detection ought to be trivially true, but the pseudocode still contains
a number of conditions, and QEMU has not yet committed to dropping A32
support for EL[12] when v9 features are present.

Since the computation of SME_TRAP_NONSTREAMING is necessarily different
for the two modes, we might as well preserve bits within TBFLAG_ANY and
allocate separate bits within TBFLAG_A32 and TBFLAG_A64 instead.

Note that DDI0616A.a has typos for bits [22:21] of LD1RO in the table
of instructions illegal in streaming mode.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220708151540.18136-4-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/cpu.h           |  7 +++
 target/arm/translate.h     |  4 ++
 target/arm/sme-fa64.decode | 90 ++++++++++++++++++++++++++++++++++++++
 target/arm/helper.c        | 41 +++++++++++++++++
 target/arm/translate-a64.c | 40 ++++++++++++++++-
 target/arm/translate-vfp.c | 12 +++++
 target/arm/translate.c     |  2 +
 target/arm/meson.build     |  1 +
 8 files changed, 195 insertions(+), 2 deletions(-)
 create mode 100644 target/arm/sme-fa64.decode

diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -XXX,XX +XXX,XX @@ FIELD(TBFLAG_A32, HSTR_ACTIVE, 9, 1)
  * the same thing as the current security state of the processor!
  */
 FIELD(TBFLAG_A32, NS, 10, 1)
+/*
+ * Indicates that SME Streaming mode is active, and SMCR_ELx.FA64 is not.
+ * This requires an SME trap from AArch32 mode when using NEON.
+ */
+FIELD(TBFLAG_A32, SME_TRAP_NONSTREAMING, 11, 1)
 
 /*
  * Bit usage when in AArch32 state, for M-profile only.
@@ -XXX,XX +XXX,XX @@ FIELD(TBFLAG_A64, SMEEXC_EL, 20, 2)
 FIELD(TBFLAG_A64, PSTATE_SM, 22, 1)
 FIELD(TBFLAG_A64, PSTATE_ZA, 23, 1)
 FIELD(TBFLAG_A64, SVL, 24, 4)
+/* Indicates that SME Streaming mode is active, and SMCR_ELx.FA64 is not. */
+FIELD(TBFLAG_A64, SME_TRAP_NONSTREAMING, 28, 1)
 
 /*
  * Helpers for using the above.
diff --git a/target/arm/translate.h b/target/arm/translate.h
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/translate.h
+++ b/target/arm/translate.h
@@ -XXX,XX +XXX,XX @@ typedef struct DisasContext {
     bool pstate_sm;
     /* True if PSTATE.ZA is set. */
     bool pstate_za;
+    /* True if non-streaming insns should raise an SME Streaming exception. */
+    bool sme_trap_nonstreaming;
+    /* True if the current instruction is non-streaming. */
+    bool is_nonstreaming;
     /* True if MVE insns are definitely not predicated by VPR or LTPSIZE */
     bool mve_no_pred;
     /*
diff --git a/target/arm/sme-fa64.decode b/target/arm/sme-fa64.decode
new file mode 100644
index XXXXXXX..XXXXXXX
--- /dev/null
+++ b/target/arm/sme-fa64.decode
@@ -XXX,XX +XXX,XX @@
+# AArch64 SME allowed instruction decoding
+#
+#  Copyright (c) 2022 Linaro, Ltd
+#
+# This library is free software; you can redistribute it and/or
+# modify it under the terms of the GNU Lesser General Public
+# License as published by the Free Software Foundation; either
+# version 2.1 of the License, or (at your option) any later version.
+#
+# This library is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+# Lesser General Public License for more details.
+#
+# You should have received a copy of the GNU Lesser General Public
+# License along with this library; if not, see <http://www.gnu.org/licenses/>.
+
+#
+# This file is processed by scripts/decodetree.py
+#
+
+# These patterns are taken from Appendix E1.1 of DDI0616 A.a,
+# Arm Architecture Reference Manual Supplement,
+# The Scalable Matrix Extension (SME), for Armv9-A
+
+{
+  [
+    OK  0-00 1110 0000 0001 0010 11-- ---- ----   # SMOV W|Xd,Vn.B[0]
+    OK  0-00 1110 0000 0010 0010 11-- ---- ----   # SMOV W|Xd,Vn.H[0]
+    OK  0100 1110 0000 0100 0010 11-- ---- ----   # SMOV Xd,Vn.S[0]
+    OK  0000 1110 0000 0001 0011 11-- ---- ----   # UMOV Wd,Vn.B[0]
+    OK  0000 1110 0000 0010 0011 11-- ---- ----   # UMOV Wd,Vn.H[0]
+    OK  0000 1110 0000 0100 0011 11-- ---- ----   # UMOV Wd,Vn.S[0]
+    OK  0100 1110 0000 1000 0011 11-- ---- ----   # UMOV Xd,Vn.D[0]
+  ]
+  FAIL  0--0 111- ---- ---- ---- ---- ---- ----   # Advanced SIMD vector operations
+}
+
+{
+  [
+    OK  0101 1110 --1- ---- 11-1 11-- ---- ----   # FMULX/FRECPS/FRSQRTS (scalar)
+    OK  0101 1110 -10- ---- 00-1 11-- ---- ----   # FMULX/FRECPS/FRSQRTS (scalar, FP16)
+    OK  01-1 1110 1-10 0001 11-1 10-- ---- ----   # FRECPE/FRSQRTE/FRECPX (scalar)
+    OK  01-1 1110 1111 1001 11-1 10-- ---- ----   # FRECPE/FRSQRTE/FRECPX (scalar, FP16)
+  ]
+  FAIL  01-1 111- ---- ---- ---- ---- ---- ----   # Advanced SIMD single-element operations
+}
+
+FAIL    0-00 110- ---- ---- ---- ---- ---- ----   # Advanced SIMD structure load/store
+FAIL    1100 1110 ---- ---- ---- ---- ---- ----   # Advanced SIMD cryptography extensions
+FAIL    0001 1110 0111 1110 0000 00-- ---- ----   # FJCVTZS
+
+# These are the "avoidance of doubt" final table of Illegal Advanced SIMD instructions
+# We don't actually need to include these, as the default is OK.
+#       -001 111- ---- ---- ---- ---- ---- ----   # Scalar floating-point operations
+#       --10 110- ---- ---- ---- ---- ---- ----   # Load/store pair of FP registers
+#       --01 1100 ---- ---- ---- ---- ---- ----   # Load FP register (PC-relative literal)
+#       --11 1100 --0- ---- ---- ---- ---- ----   # Load/store FP register (unscaled imm)
+#       --11 1100 --1- ---- ---- ---- ---- --10   # Load/store FP register (register offset)
+#       --11 1101 ---- ---- ---- ---- ---- ----   # Load/store FP register (scaled imm)
+
+FAIL    0000 0100 --1- ---- 1010 ---- ---- ----   # ADR
+FAIL    0000 0100 --1- ---- 1011 -0-- ---- ----   # FTSSEL, FEXPA
+FAIL    0000 0101 --10 0001 100- ---- ---- ----   # COMPACT
+FAIL    0010 0101 --01 100- 1111 000- ---0 ----   # RDFFR, RDFFRS
+FAIL    0010 0101 --10 1--- 1001 ---- ---- ----   # WRFFR, SETFFR
+FAIL    0100 0101 --0- ---- 1011 ---- ---- ----   # BDEP, BEXT, BGRP
+FAIL    0100 0101 000- ---- 0110 1--- ---- ----   # PMULLB, PMULLT (128b result)
+FAIL    0110 0100 --1- ---- 1110 01-- ---- ----   # FMMLA, BFMMLA
+FAIL    0110 0101 --0- ---- 0000 11-- ---- ----   # FTSMUL
+FAIL    0110 0101 --01 0--- 100- ---- ---- ----   # FTMAD
+FAIL    0110 0101 --01 1--- 001- ---- ---- ----   # FADDA
+FAIL    0100 0101 --0- ---- 1001 10-- ---- ----   # SMMLA, UMMLA, USMMLA
+FAIL    0100 0101 --1- ---- 1--- ---- ---- ----   # SVE2 string/histo/crypto instructions
+FAIL    1000 010- -00- ---- 10-- ---- ---- ----   # SVE2 32-bit gather NT load (vector+scalar)
+FAIL    1000 010- -00- ---- 111- ---- ---- ----   # SVE 32-bit gather prefetch (vector+imm)
+FAIL    1000 0100 0-1- ---- 0--- ---- ---- ----   # SVE 32-bit gather prefetch (scalar+vector)
+FAIL    1000 010- -01- ---- 1--- ---- ---- ----   # SVE 32-bit gather load (vector+imm)
+FAIL    1000 0100 0-0- ---- 0--- ---- ---- ----   # SVE 32-bit gather load byte (scalar+vector)
+FAIL    1000 0100 1--- ---- 0--- ---- ---- ----   # SVE 32-bit gather load half (scalar+vector)
+FAIL    1000 0101 0--- ---- 0--- ---- ---- ----   # SVE 32-bit gather load word (scalar+vector)
+FAIL    1010 010- ---- ---- 011- ---- ---- ----   # SVE contiguous FF load (scalar+scalar)
+FAIL    1010 010- ---1 ---- 101- ---- ---- ----   # SVE contiguous NF load (scalar+imm)
+FAIL    1010 010- -01- ---- 000- ---- ---- ----   # SVE load & replicate 32 bytes (scalar+scalar)
+FAIL    1010 010- -010 ---- 001- ---- ---- ----   # SVE load & replicate 32 bytes (scalar+imm)
+FAIL    1100 010- ---- ---- ---- ---- ---- ----   # SVE 64-bit gather load/prefetch
+FAIL    1110 010- -00- ---- 001- ---- ---- ----   # SVE2 64-bit scatter NT store (vector+scalar)
+FAIL    1110 010- -10- ---- 001- ---- ---- ----   # SVE2 32-bit scatter NT store (vector+scalar)
+FAIL    1110 010- ---- ---- 1-0- ---- ---- ----   # SVE scatter store (scalar+32-bit vector)
+FAIL    1110 010- ---- ---- 101- ---- ---- ----   # SVE scatter store (misc)
diff --git a/target/arm/helper.c b/target/arm/helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -XXX,XX +XXX,XX @@ int sme_exception_el(CPUARMState *env, int el)
     return 0;
 }
 
+/* This corresponds to the ARM pseudocode function IsFullA64Enabled(). */
+static bool sme_fa64(CPUARMState *env, int el)
+{
+    if (!cpu_isar_feature(aa64_sme_fa64, env_archcpu(env))) {
+        return false;
+    }
+
+    if (el <= 1 && !el_is_in_host(env, el)) {
+        if (!FIELD_EX64(env->vfp.smcr_el[1], SMCR, FA64)) {
+            return false;
+        }
+    }
+    if (el <= 2 && arm_is_el2_enabled(env)) {
+        if (!FIELD_EX64(env->vfp.smcr_el[2], SMCR, FA64)) {
+            return false;
+        }
+    }
+    if (arm_feature(env, ARM_FEATURE_EL3)) {
+        if (!FIELD_EX64(env->vfp.smcr_el[3], SMCR, FA64)) {
+            return false;
+        }
+    }
+
+    return true;
+}
+
 /*
  * Given that SVE is enabled, return the vector length for EL.
  */
@@ -XXX,XX +XXX,XX @@ static CPUARMTBFlags rebuild_hflags_a32(CPUARMState *env, int fp_el,
         DP_TBFLAG_ANY(flags, PSTATE__IL, 1);
     }
 
+    /*
+     * The SME exception we are testing for is raised via
+     * AArch64.CheckFPAdvSIMDEnabled(), as called from
+     * AArch32.CheckAdvSIMDOrFPEnabled().
+     */
+    if (el == 0
+        && FIELD_EX64(env->svcr, SVCR, SM)
+        && (!arm_is_el2_enabled(env)
+            || (arm_el_is_aa64(env, 2) && !(env->cp15.hcr_el2 & HCR_TGE)))
+        && arm_el_is_aa64(env, 1)
+        && !sme_fa64(env, el)) {
+        DP_TBFLAG_A32(flags, SME_TRAP_NONSTREAMING, 1);
+    }
+
     return rebuild_hflags_common_32(env, fp_el, mmu_idx, flags);
 }
 
@@ -XXX,XX +XXX,XX @@ static CPUARMTBFlags rebuild_hflags_a64(CPUARMState *env, int el, int fp_el,
         }
         if (FIELD_EX64(env->svcr, SVCR, SM)) {
             DP_TBFLAG_A64(flags, PSTATE_SM, 1);
+            DP_TBFLAG_A64(flags, SME_TRAP_NONSTREAMING, !sme_fa64(env, el));
         }
         DP_TBFLAG_A64(flags, PSTATE_ZA, FIELD_EX64(env->svcr, SVCR, ZA));
     }
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/translate-a64.c
+++ b/target/arm/translate-a64.c
@@ -XXX,XX +XXX,XX @@ static void do_vec_ld(DisasContext *s, int destidx, int element,
  * unallocated-encoding checks (otherwise the syndrome information
  * for the resulting exception will be incorrect).
  */
-static bool fp_access_check(DisasContext *s)
+static bool fp_access_check_only(DisasContext *s)
 {
     if (s->fp_excp_el) {
         assert(!s->fp_access_checked);
@@ -XXX,XX +XXX,XX @@ static bool fp_access_check(DisasContext *s)
     return true;
 }
 
+static bool fp_access_check(DisasContext *s)
+{
+    if (!fp_access_check_only(s)) {
+        return false;
+    }
+    if (s->sme_trap_nonstreaming && s->is_nonstreaming) {
+        gen_exception_insn(s, s->pc_curr, EXCP_UDEF,
+                           syn_smetrap(SME_ET_Streaming, false));
+        return false;
+    }
+    return true;
+}
+
 /* Check that SVE access is enabled.  If it is, return true.
  * If not, emit code to generate an appropriate exception and return false.
  */
@@ -XXX,XX +XXX,XX @@ static void handle_sys(DisasContext *s, uint32_t insn, bool isread,
     default:
         g_assert_not_reached();
     }
-    if ((ri->type & ARM_CP_FPU) && !fp_access_check(s)) {
+    if ((ri->type & ARM_CP_FPU) && !fp_access_check_only(s)) {
         return;
     } else if ((ri->type & ARM_CP_SVE) && !sve_access_check(s)) {
         return;
@@ -XXX,XX +XXX,XX @@ static void disas_data_proc_simd_fp(DisasContext *s, uint32_t insn)
     }
 }
 
+/*
+ * Include the generated SME FA64 decoder.
+ */
+
+#include "decode-sme-fa64.c.inc"
+
+static bool trans_OK(DisasContext *s, arg_OK *a)
+{
+    return true;
+}
+
+static bool trans_FAIL(DisasContext *s, arg_OK *a)
+{
+    s->is_nonstreaming = true;
+    return true;
+}
+
 /**
  * is_guarded_page:
  * @env: The cpu environment
@@ -XXX,XX +XXX,XX @@ static void aarch64_tr_init_disas_context(DisasContextBase *dcbase,
     dc->mte_active[1] = EX_TBFLAG_A64(tb_flags, MTE0_ACTIVE);
     dc->pstate_sm = EX_TBFLAG_A64(tb_flags, PSTATE_SM);
     dc->pstate_za = EX_TBFLAG_A64(tb_flags, PSTATE_ZA);
+    dc->sme_trap_nonstreaming = EX_TBFLAG_A64(tb_flags, SME_TRAP_NONSTREAMING);
     dc->vec_len = 0;
     dc->vec_stride = 0;
     dc->cp_regs = arm_cpu->cp_regs;
@@ -XXX,XX +XXX,XX @@ static void aarch64_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu)
         }
     }
 
+    s->is_nonstreaming = false;
+    if (s->sme_trap_nonstreaming) {
+        disas_sme_fa64(s, insn);
+    }
+
     switch (extract32(insn, 25, 4)) {
     case 0x0:
         if (!extract32(insn, 31, 1) || !disas_sme(s, insn)) {
diff --git a/target/arm/translate-vfp.c b/target/arm/translate-vfp.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/translate-vfp.c
+++ b/target/arm/translate-vfp.c
@@ -XXX,XX +XXX,XX @@ static bool vfp_access_check_a(DisasContext *s, bool ignore_vfp_enabled)
         return false;
     }
 
+    /*
+     * Note that rebuild_hflags_a32 has already accounted for being in EL0
+     * and the higher EL in A64 mode, etc.  Unlike A64 mode, there do not
+     * appear to be any insns which touch VFP which are allowed.
+     */
+    if (s->sme_trap_nonstreaming) {
+        gen_exception_insn(s, s->pc_curr, EXCP_UDEF,
+                           syn_smetrap(SME_ET_Streaming,
+                                       s->base.pc_next - s->pc_curr == 2));
+        return false;
+    }
+
     if (!s->vfp_enabled && !ignore_vfp_enabled) {
         assert(!arm_dc_feature(s, ARM_FEATURE_M));
         unallocated_encoding(s);
diff --git a/target/arm/translate.c b/target/arm/translate.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -XXX,XX +XXX,XX @@ static void arm_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs)
             dc->vec_len = EX_TBFLAG_A32(tb_flags, VECLEN);
             dc->vec_stride = EX_TBFLAG_A32(tb_flags, VECSTRIDE);
         }
+        dc->sme_trap_nonstreaming =
+            EX_TBFLAG_A32(tb_flags, SME_TRAP_NONSTREAMING);
     }
     dc->cp_regs = cpu->cp_regs;
     dc->features = env->features;
diff --git a/target/arm/meson.build b/target/arm/meson.build
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/meson.build
+++ b/target/arm/meson.build
@@ -XXX,XX +XXX,XX @@
 gen = [
   decodetree.process('sve.decode', extra_args: '--decode=disas_sve'),
   decodetree.process('sme.decode', extra_args: '--decode=disas_sme'),
+  decodetree.process('sme-fa64.decode', extra_args: '--static-decode=disas_sme_fa64'),
   decodetree.process('neon-shared.decode', extra_args: '--decode=disas_neon_shared'),
   decodetree.process('neon-dp.decode', extra_args: '--decode=disas_neon_dp'),
   decodetree.process('neon-ls.decode', extra_args: '--decode=disas_neon_ls'),
-- 
2.25.1

From: Richard Henderson <richard.henderson@linaro.org>

Mark ADR as a non-streaming instruction, which should trap
if full a64 support is not enabled in streaming mode.

Removing entries from sme-fa64.decode is an easy way to see
what remains to be done.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220708151540.18136-5-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/translate.h     | 7 +++++++
 target/arm/sme-fa64.decode | 1 -
 target/arm/translate-sve.c | 8 ++++----
 3 files changed, 11 insertions(+), 5 deletions(-)

diff --git a/target/arm/translate.h b/target/arm/translate.h
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/translate.h
+++ b/target/arm/translate.h
@@ -XXX,XX +XXX,XX @@ uint64_t asimd_imm_const(uint32_t imm, int cmode, int op);
     static bool trans_##NAME(DisasContext *s, arg_##NAME *a) \
     { return dc_isar_feature(FEAT, s) && FUNC(s, __VA_ARGS__); }
 
+#define TRANS_FEAT_NONSTREAMING(NAME, FEAT, FUNC, ...)            \
+    static bool trans_##NAME(DisasContext *s, arg_##NAME *a)      \
+    {                                                             \
+        s->is_nonstreaming = true;                                \
+        return dc_isar_feature(FEAT, s) && FUNC(s, __VA_ARGS__);  \
+    }
+
 #endif /* TARGET_ARM_TRANSLATE_H */
diff --git a/target/arm/sme-fa64.decode b/target/arm/sme-fa64.decode
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/sme-fa64.decode
+++ b/target/arm/sme-fa64.decode
@@ -XXX,XX +XXX,XX @@ FAIL    0001 1110 0111 1110 0000 00-- ---- ----   # FJCVTZS
 #       --11 1100 --1- ---- ---- ---- ---- --10   # Load/store FP register (register offset)
 #       --11 1101 ---- ---- ---- ---- ---- ----   # Load/store FP register (scaled imm)
 
-FAIL    0000 0100 --1- ---- 1010 ---- ---- ----   # ADR
 FAIL    0000 0100 --1- ---- 1011 -0-- ---- ----   # FTSSEL, FEXPA
 FAIL    0000 0101 --10 0001 100- ---- ---- ----   # COMPACT
 FAIL    0010 0101 --01 100- 1111 000- ---0 ----   # RDFFR, RDFFRS
diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/translate-sve.c
+++ b/target/arm/translate-sve.c
@@ -XXX,XX +XXX,XX @@ static bool do_adr(DisasContext *s, arg_rrri *a, gen_helper_gvec_3 *fn)
     return gen_gvec_ool_zzz(s, fn, a->rd, a->rn, a->rm, a->imm);
 }
 
-TRANS_FEAT(ADR_p32, aa64_sve, do_adr, a, gen_helper_sve_adr_p32)
-TRANS_FEAT(ADR_p64, aa64_sve, do_adr, a, gen_helper_sve_adr_p64)
-TRANS_FEAT(ADR_s32, aa64_sve, do_adr, a, gen_helper_sve_adr_s32)
-TRANS_FEAT(ADR_u32, aa64_sve, do_adr, a, gen_helper_sve_adr_u32)
+TRANS_FEAT_NONSTREAMING(ADR_p32, aa64_sve, do_adr, a, gen_helper_sve_adr_p32)
+TRANS_FEAT_NONSTREAMING(ADR_p64, aa64_sve, do_adr, a, gen_helper_sve_adr_p64)
+TRANS_FEAT_NONSTREAMING(ADR_s32, aa64_sve, do_adr, a, gen_helper_sve_adr_s32)
+TRANS_FEAT_NONSTREAMING(ADR_u32, aa64_sve, do_adr, a, gen_helper_sve_adr_u32)
 
 /*
  *** SVE Integer Misc - Unpredicated Group
-- 
2.25.1

From: Richard Henderson <richard.henderson@linaro.org>

Mark these as a non-streaming instructions, which should trap
if full a64 support is not enabled in streaming mode.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220708151540.18136-6-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/sme-fa64.decode | 2 --
 target/arm/translate-sve.c | 9 ++++++---
 2 files changed, 6 insertions(+), 5 deletions(-)

From: Richard Henderson <richard.henderson@linaro.org>

Mark these as a non-streaming instructions, which should trap
if full a64 support is not enabled in streaming mode.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220708151540.18136-7-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/sme-fa64.decode |  3 ---
 target/arm/translate-sve.c | 22 ++++++++++++----------
 2 files changed, 12 insertions(+), 13 deletions(-)

diff --git a/target/arm/sme-fa64.decode b/target/arm/sme-fa64.decode
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/sme-fa64.decode
+++ b/target/arm/sme-fa64.decode
@@ -XXX,XX +XXX,XX @@ FAIL    0001 1110 0111 1110 0000 00-- ---- ----   # FJCVTZS
 #       --11 1100 --1- ---- ---- ---- ---- --10   # Load/store FP register (register offset)
 #       --11 1101 ---- ---- ---- ---- ---- ----   # Load/store FP register (scaled imm)
 
-FAIL    0000 0100 --1- ---- 1011 -0-- ---- ----   # FTSSEL, FEXPA
-FAIL    0000 0101 --10 0001 100- ---- ---- ----   # COMPACT
-FAIL    0100 0101 --0- ---- 1011 ---- ---- ----   # BDEP, BEXT, BGRP
 FAIL    0100 0101 000- ---- 0110 1--- ---- ----   # PMULLB, PMULLT (128b result)
 FAIL    0110 0100 --1- ---- 1110 01-- ---- ----   # FMMLA, BFMMLA
 FAIL    0110 0101 --0- ---- 0000 11-- ---- ----   # FTSMUL
diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/translate-sve.c
+++ b/target/arm/translate-sve.c
@@ -XXX,XX +XXX,XX @@ static gen_helper_gvec_2 * const fexpa_fns[4] = {
     NULL,                   gen_helper_sve_fexpa_h,
     gen_helper_sve_fexpa_s, gen_helper_sve_fexpa_d,
 };
-TRANS_FEAT(FEXPA, aa64_sve, gen_gvec_ool_zz,
-           fexpa_fns[a->esz], a->rd, a->rn, 0)
+TRANS_FEAT_NONSTREAMING(FEXPA, aa64_sve, gen_gvec_ool_zz,
+                        fexpa_fns[a->esz], a->rd, a->rn, 0)
 
 static gen_helper_gvec_3 * const ftssel_fns[4] = {
     NULL,                    gen_helper_sve_ftssel_h,
     gen_helper_sve_ftssel_s, gen_helper_sve_ftssel_d,
 };
-TRANS_FEAT(FTSSEL, aa64_sve, gen_gvec_ool_arg_zzz, ftssel_fns[a->esz], a, 0)
+TRANS_FEAT_NONSTREAMING(FTSSEL, aa64_sve, gen_gvec_ool_arg_zzz,
+                        ftssel_fns[a->esz], a, 0)
 
 /*
  *** SVE Predicate Logical Operations Group
@@ -XXX,XX +XXX,XX @@ TRANS_FEAT(TRN2_q, aa64_sve_f64mm, gen_gvec_ool_arg_zzz,
 static gen_helper_gvec_3 * const compact_fns[4] = {
     NULL, NULL, gen_helper_sve_compact_s, gen_helper_sve_compact_d
 };
-TRANS_FEAT(COMPACT, aa64_sve, gen_gvec_ool_arg_zpz, compact_fns[a->esz], a, 0)
+TRANS_FEAT_NONSTREAMING(COMPACT, aa64_sve, gen_gvec_ool_arg_zpz,
+                        compact_fns[a->esz], a, 0)
 
 /* Call the helper that computes the ARM LastActiveElement pseudocode
  * function, scaled by the element size.  This includes the not found
@@ -XXX,XX +XXX,XX @@ static gen_helper_gvec_3 * const bext_fns[4] = {
     gen_helper_sve2_bext_b, gen_helper_sve2_bext_h,
     gen_helper_sve2_bext_s, gen_helper_sve2_bext_d,
 };
-TRANS_FEAT(BEXT, aa64_sve2_bitperm, gen_gvec_ool_arg_zzz,
-           bext_fns[a->esz], a, 0)
+TRANS_FEAT_NONSTREAMING(BEXT, aa64_sve2_bitperm, gen_gvec_ool_arg_zzz,
+                        bext_fns[a->esz], a, 0)
 
 static gen_helper_gvec_3 * const bdep_fns[4] = {
     gen_helper_sve2_bdep_b, gen_helper_sve2_bdep_h,
     gen_helper_sve2_bdep_s, gen_helper_sve2_bdep_d,
 };
-TRANS_FEAT(BDEP, aa64_sve2_bitperm, gen_gvec_ool_arg_zzz,
-           bdep_fns[a->esz], a, 0)
+TRANS_FEAT_NONSTREAMING(BDEP, aa64_sve2_bitperm, gen_gvec_ool_arg_zzz,
+                        bdep_fns[a->esz], a, 0)
 
 static gen_helper_gvec_3 * const bgrp_fns[4] = {
     gen_helper_sve2_bgrp_b, gen_helper_sve2_bgrp_h,
     gen_helper_sve2_bgrp_s, gen_helper_sve2_bgrp_d,
 };
-TRANS_FEAT(BGRP, aa64_sve2_bitperm, gen_gvec_ool_arg_zzz,
-           bgrp_fns[a->esz], a, 0)
+TRANS_FEAT_NONSTREAMING(BGRP, aa64_sve2_bitperm, gen_gvec_ool_arg_zzz,
+                        bgrp_fns[a->esz], a, 0)
 
 static gen_helper_gvec_3 * const cadd_fns[4] = {
     gen_helper_sve2_cadd_b, gen_helper_sve2_cadd_h,
-- 
2.25.1

From: Richard Henderson <richard.henderson@linaro.org>

Mark these as a non-streaming instructions, which should trap
if full a64 support is not enabled in streaming mode.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220708151540.18136-8-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/sme-fa64.decode |  2 --
 target/arm/translate-sve.c | 24 +++++++++++++++---------
 2 files changed, 15 insertions(+), 11 deletions(-)

diff --git a/target/arm/sme-fa64.decode b/target/arm/sme-fa64.decode
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/sme-fa64.decode
+++ b/target/arm/sme-fa64.decode
@@ -XXX,XX +XXX,XX @@ FAIL    0001 1110 0111 1110 0000 00-- ---- ----   # FJCVTZS
 #       --11 1100 --1- ---- ---- ---- ---- --10   # Load/store FP register (register offset)
 #       --11 1101 ---- ---- ---- ---- ---- ----   # Load/store FP register (scaled imm)
 
-FAIL    0100 0101 000- ---- 0110 1--- ---- ----   # PMULLB, PMULLT (128b result)
-FAIL    0110 0100 --1- ---- 1110 01-- ---- ----   # FMMLA, BFMMLA
 FAIL    0110 0101 --0- ---- 0000 11-- ---- ----   # FTSMUL
 FAIL    0110 0101 --01 0--- 100- ---- ---- ----   # FTMAD
 FAIL    0110 0101 --01 1--- 001- ---- ---- ----   # FADDA
diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/translate-sve.c
+++ b/target/arm/translate-sve.c
@@ -XXX,XX +XXX,XX @@ static bool do_trans_pmull(DisasContext *s, arg_rrr_esz *a, bool sel)
         gen_helper_gvec_pmull_q, gen_helper_sve2_pmull_h,
         NULL,                    gen_helper_sve2_pmull_d,
     };
-    if (a->esz == 0
-        ? !dc_isar_feature(aa64_sve2_pmull128, s)
-        : !dc_isar_feature(aa64_sve, s)) {
+
+    if (a->esz == 0) {
+        if (!dc_isar_feature(aa64_sve2_pmull128, s)) {
+            return false;
+        }
+        s->is_nonstreaming = true;
+    } else if (!dc_isar_feature(aa64_sve, s)) {
         return false;
     }
     return gen_gvec_ool_arg_zzz(s, fns[a->esz], a, sel);
@@ -XXX,XX +XXX,XX @@ DO_ZPZZ_FP(FMINP, aa64_sve2, sve2_fminp_zpzz)
  * SVE Integer Multiply-Add (unpredicated)
  */
 
-TRANS_FEAT(FMMLA_s, aa64_sve_f32mm, gen_gvec_fpst_zzzz, gen_helper_fmmla_s,
-           a->rd, a->rn, a->rm, a->ra, 0, FPST_FPCR)
-TRANS_FEAT(FMMLA_d, aa64_sve_f64mm, gen_gvec_fpst_zzzz, gen_helper_fmmla_d,
-           a->rd, a->rn, a->rm, a->ra, 0, FPST_FPCR)
+TRANS_FEAT_NONSTREAMING(FMMLA_s, aa64_sve_f32mm, gen_gvec_fpst_zzzz,
+                        gen_helper_fmmla_s, a->rd, a->rn, a->rm, a->ra,
+                        0, FPST_FPCR)
+TRANS_FEAT_NONSTREAMING(FMMLA_d, aa64_sve_f64mm, gen_gvec_fpst_zzzz,
+                        gen_helper_fmmla_d, a->rd, a->rn, a->rm, a->ra,
+                        0, FPST_FPCR)
 
 static gen_helper_gvec_4 * const sqdmlal_zzzw_fns[] = {
     NULL,                           gen_helper_sve2_sqdmlal_zzzw_h,
@@ -XXX,XX +XXX,XX @@ TRANS_FEAT(BFDOT_zzzz, aa64_sve_bf16, gen_gvec_ool_arg_zzzz,
 TRANS_FEAT(BFDOT_zzxz, aa64_sve_bf16, gen_gvec_ool_arg_zzxz,
            gen_helper_gvec_bfdot_idx, a)
 
-TRANS_FEAT(BFMMLA, aa64_sve_bf16, gen_gvec_ool_arg_zzzz,
-           gen_helper_gvec_bfmmla, a, 0)
+TRANS_FEAT_NONSTREAMING(BFMMLA, aa64_sve_bf16, gen_gvec_ool_arg_zzzz,
+                        gen_helper_gvec_bfmmla, a, 0)
 
 static bool do_BFMLAL_zzzw(DisasContext *s, arg_rrrr_esz *a, bool sel)
 {
-- 
2.25.1

From: Richard Henderson <richard.henderson@linaro.org>

Mark these as a non-streaming instructions, which should trap
if full a64 support is not enabled in streaming mode.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220708151540.18136-9-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/sme-fa64.decode |  3 ---
 target/arm/translate-sve.c | 15 +++++++++++----
 2 files changed, 11 insertions(+), 7 deletions(-)

From: Richard Henderson <richard.henderson@linaro.org>

Mark these as a non-streaming instructions, which should trap
if full a64 support is not enabled in streaming mode.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220708151540.18136-10-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/sme-fa64.decode |  1 -
 target/arm/translate-sve.c | 12 ++++++------
 2 files changed, 6 insertions(+), 7 deletions(-)

From: Richard Henderson <richard.henderson@linaro.org>

Mark these as non-streaming instructions, which should trap
if full a64 support is not enabled in streaming mode.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220708151540.18136-11-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/sme-fa64.decode |  1 -
 target/arm/translate-sve.c | 35 ++++++++++++++++++-----------------
 2 files changed, 18 insertions(+), 18 deletions(-)

diff --git a/target/arm/sme-fa64.decode b/target/arm/sme-fa64.decode
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/sme-fa64.decode
+++ b/target/arm/sme-fa64.decode
@@ -XXX,XX +XXX,XX @@ FAIL    0001 1110 0111 1110 0000 00-- ---- ----   # FJCVTZS
 #       --11 1100 --1- ---- ---- ---- ---- --10   # Load/store FP register (register offset)
 #       --11 1101 ---- ---- ---- ---- ---- ----   # Load/store FP register (scaled imm)
 
-FAIL    0100 0101 --1- ---- 1--- ---- ---- ----   # SVE2 string/histo/crypto instructions
 FAIL    1000 010- -00- ---- 10-- ---- ---- ----   # SVE2 32-bit gather NT load (vector+scalar)
 FAIL    1000 010- -00- ---- 111- ---- ---- ----   # SVE 32-bit gather prefetch (vector+imm)
 FAIL    1000 0100 0-1- ---- 0--- ---- ---- ----   # SVE 32-bit gather prefetch (scalar+vector)
diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/translate-sve.c
+++ b/target/arm/translate-sve.c
@@ -XXX,XX +XXX,XX @@ DO_SVE2_ZZZ_NARROW(RSUBHNT, rsubhnt)
 static gen_helper_gvec_flags_4 * const match_fns[4] = {
     gen_helper_sve2_match_ppzz_b, gen_helper_sve2_match_ppzz_h, NULL, NULL
 };
-TRANS_FEAT(MATCH, aa64_sve2, do_ppzz_flags, a, match_fns[a->esz])
+TRANS_FEAT_NONSTREAMING(MATCH, aa64_sve2, do_ppzz_flags, a, match_fns[a->esz])
 
 static gen_helper_gvec_flags_4 * const nmatch_fns[4] = {
     gen_helper_sve2_nmatch_ppzz_b, gen_helper_sve2_nmatch_ppzz_h, NULL, NULL
 };
-TRANS_FEAT(NMATCH, aa64_sve2, do_ppzz_flags, a, nmatch_fns[a->esz])
+TRANS_FEAT_NONSTREAMING(NMATCH, aa64_sve2, do_ppzz_flags, a, nmatch_fns[a->esz])
 
 static gen_helper_gvec_4 * const histcnt_fns[4] = {
     NULL, NULL, gen_helper_sve2_histcnt_s, gen_helper_sve2_histcnt_d
 };
-TRANS_FEAT(HISTCNT, aa64_sve2, gen_gvec_ool_arg_zpzz,
-           histcnt_fns[a->esz], a, 0)
+TRANS_FEAT_NONSTREAMING(HISTCNT, aa64_sve2, gen_gvec_ool_arg_zpzz,
+                        histcnt_fns[a->esz], a, 0)
 
-TRANS_FEAT(HISTSEG, aa64_sve2, gen_gvec_ool_arg_zzz,
-           a->esz == 0 ? gen_helper_sve2_histseg : NULL, a, 0)
+TRANS_FEAT_NONSTREAMING(HISTSEG, aa64_sve2, gen_gvec_ool_arg_zzz,
+                        a->esz == 0 ? gen_helper_sve2_histseg : NULL, a, 0)
 
 DO_ZPZZ_FP(FADDP, aa64_sve2, sve2_faddp_zpzz)
 DO_ZPZZ_FP(FMAXNMP, aa64_sve2, sve2_fmaxnmp_zpzz)
@@ -XXX,XX +XXX,XX @@ TRANS_FEAT(SQRDCMLAH_zzzz, aa64_sve2, gen_gvec_ool_zzzz,
 TRANS_FEAT(USDOT_zzzz, aa64_sve_i8mm, gen_gvec_ool_arg_zzzz,
            a->esz == 2 ? gen_helper_gvec_usdot_b : NULL, a, 0)
 
-TRANS_FEAT(AESMC, aa64_sve2_aes, gen_gvec_ool_zz,
-           gen_helper_crypto_aesmc, a->rd, a->rd, a->decrypt)
+TRANS_FEAT_NONSTREAMING(AESMC, aa64_sve2_aes, gen_gvec_ool_zz,
+                        gen_helper_crypto_aesmc, a->rd, a->rd, a->decrypt)
 
-TRANS_FEAT(AESE, aa64_sve2_aes, gen_gvec_ool_arg_zzz,
-           gen_helper_crypto_aese, a, false)
-TRANS_FEAT(AESD, aa64_sve2_aes, gen_gvec_ool_arg_zzz,
-           gen_helper_crypto_aese, a, true)
+TRANS_FEAT_NONSTREAMING(AESE, aa64_sve2_aes, gen_gvec_ool_arg_zzz,
+                        gen_helper_crypto_aese, a, false)
+TRANS_FEAT_NONSTREAMING(AESD, aa64_sve2_aes, gen_gvec_ool_arg_zzz,
+                        gen_helper_crypto_aese, a, true)
 
-TRANS_FEAT(SM4E, aa64_sve2_sm4, gen_gvec_ool_arg_zzz,
-           gen_helper_crypto_sm4e, a, 0)
-TRANS_FEAT(SM4EKEY, aa64_sve2_sm4, gen_gvec_ool_arg_zzz,
-           gen_helper_crypto_sm4ekey, a, 0)
+TRANS_FEAT_NONSTREAMING(SM4E, aa64_sve2_sm4, gen_gvec_ool_arg_zzz,
+                        gen_helper_crypto_sm4e, a, 0)
+TRANS_FEAT_NONSTREAMING(SM4EKEY, aa64_sve2_sm4, gen_gvec_ool_arg_zzz,
+                        gen_helper_crypto_sm4ekey, a, 0)
 
-TRANS_FEAT(RAX1, aa64_sve2_sha3, gen_gvec_fn_arg_zzz, gen_gvec_rax1, a)
+TRANS_FEAT_NONSTREAMING(RAX1, aa64_sve2_sha3, gen_gvec_fn_arg_zzz,
+                        gen_gvec_rax1, a)
 
 TRANS_FEAT(FCVTNT_sh, aa64_sve2, gen_gvec_fpst_arg_zpz,
            gen_helper_sve2_fcvtnt_sh, a, 0, FPST_FPCR)
-- 
2.25.1

From: Richard Henderson <richard.henderson@linaro.org>

Mark these as a non-streaming instructions, which should trap
if full a64 support is not enabled in streaming mode.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220708151540.18136-12-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/sme-fa64.decode | 9 ---------
 target/arm/translate-sve.c | 6 ++++++
 2 files changed, 6 insertions(+), 9 deletions(-)

diff --git a/target/arm/sme-fa64.decode b/target/arm/sme-fa64.decode
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/sme-fa64.decode
+++ b/target/arm/sme-fa64.decode
@@ -XXX,XX +XXX,XX @@ FAIL    0001 1110 0111 1110 0000 00-- ---- ----   # FJCVTZS
 #       --11 1100 --1- ---- ---- ---- ---- --10   # Load/store FP register (register offset)
 #       --11 1101 ---- ---- ---- ---- ---- ----   # Load/store FP register (scaled imm)
 
-FAIL    1000 010- -00- ---- 10-- ---- ---- ----   # SVE2 32-bit gather NT load (vector+scalar)
 FAIL    1000 010- -00- ---- 111- ---- ---- ----   # SVE 32-bit gather prefetch (vector+imm)
 FAIL    1000 0100 0-1- ---- 0--- ---- ---- ----   # SVE 32-bit gather prefetch (scalar+vector)
-FAIL    1000 010- -01- ---- 1--- ---- ---- ----   # SVE 32-bit gather load (vector+imm)
-FAIL    1000 0100 0-0- ---- 0--- ---- ---- ----   # SVE 32-bit gather load byte (scalar+vector)
-FAIL    1000 0100 1--- ---- 0--- ---- ---- ----   # SVE 32-bit gather load half (scalar+vector)
-FAIL    1000 0101 0--- ---- 0--- ---- ---- ----   # SVE 32-bit gather load word (scalar+vector)
 FAIL    1010 010- ---- ---- 011- ---- ---- ----   # SVE contiguous FF load (scalar+scalar)
 FAIL    1010 010- ---1 ---- 101- ---- ---- ----   # SVE contiguous NF load (scalar+imm)
 FAIL    1010 010- -01- ---- 000- ---- ---- ----   # SVE load & replicate 32 bytes (scalar+scalar)
 FAIL    1010 010- -010 ---- 001- ---- ---- ----   # SVE load & replicate 32 bytes (scalar+imm)
 FAIL    1100 010- ---- ---- ---- ---- ---- ----   # SVE 64-bit gather load/prefetch
-FAIL    1110 010- -00- ---- 001- ---- ---- ----   # SVE2 64-bit scatter NT store (vector+scalar)
-FAIL    1110 010- -10- ---- 001- ---- ---- ----   # SVE2 32-bit scatter NT store (vector+scalar)
-FAIL    1110 010- ---- ---- 1-0- ---- ---- ----   # SVE scatter store (scalar+32-bit vector)
-FAIL    1110 010- ---- ---- 101- ---- ---- ----   # SVE scatter store (misc)
diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/translate-sve.c
+++ b/target/arm/translate-sve.c
@@ -XXX,XX +XXX,XX @@ static bool trans_LD1_zprz(DisasContext *s, arg_LD1_zprz *a)
     if (!dc_isar_feature(aa64_sve, s)) {
         return false;
     }
+    s->is_nonstreaming = true;
     if (!sve_access_check(s)) {
         return true;
     }
@@ -XXX,XX +XXX,XX @@ static bool trans_LD1_zpiz(DisasContext *s, arg_LD1_zpiz *a)
     if (!dc_isar_feature(aa64_sve, s)) {
         return false;
     }
+    s->is_nonstreaming = true;
     if (!sve_access_check(s)) {
         return true;
     }
@@ -XXX,XX +XXX,XX @@ static bool trans_LDNT1_zprz(DisasContext *s, arg_LD1_zprz *a)
     if (!dc_isar_feature(aa64_sve2, s)) {
         return false;
     }
+    s->is_nonstreaming = true;
     if (!sve_access_check(s)) {
         return true;
     }
@@ -XXX,XX +XXX,XX @@ static bool trans_ST1_zprz(DisasContext *s, arg_ST1_zprz *a)
     if (!dc_isar_feature(aa64_sve, s)) {
         return false;
     }
+    s->is_nonstreaming = true;
     if (!sve_access_check(s)) {
         return true;
     }
@@ -XXX,XX +XXX,XX @@ static bool trans_ST1_zpiz(DisasContext *s, arg_ST1_zpiz *a)
     if (!dc_isar_feature(aa64_sve, s)) {
         return false;
     }
+    s->is_nonstreaming = true;
     if (!sve_access_check(s)) {
         return true;
     }
@@ -XXX,XX +XXX,XX @@ static bool trans_STNT1_zprz(DisasContext *s, arg_ST1_zprz *a)
     if (!dc_isar_feature(aa64_sve2, s)) {
         return false;
     }
+    s->is_nonstreaming = true;
     if (!sve_access_check(s)) {
         return true;
     }
-- 
2.25.1

From: Richard Henderson <richard.henderson@linaro.org>

Mark these as a non-streaming instructions, which should trap if full
a64 support is not enabled in streaming mode.  In this case, introduce
PRF_ns (prefetch non-streaming) to handle the checks.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220708151540.18136-13-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/sme-fa64.decode |  3 ---
 target/arm/sve.decode      | 10 +++++-----
 target/arm/translate-sve.c | 11 +++++++++++
 3 files changed, 16 insertions(+), 8 deletions(-)

diff --git a/target/arm/sme-fa64.decode b/target/arm/sme-fa64.decode
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/sme-fa64.decode
+++ b/target/arm/sme-fa64.decode
@@ -XXX,XX +XXX,XX @@ FAIL    0001 1110 0111 1110 0000 00-- ---- ----   # FJCVTZS
 #       --11 1100 --1- ---- ---- ---- ---- --10   # Load/store FP register (register offset)
 #       --11 1101 ---- ---- ---- ---- ---- ----   # Load/store FP register (scaled imm)
 
-FAIL    1000 010- -00- ---- 111- ---- ---- ----   # SVE 32-bit gather prefetch (vector+imm)
-FAIL    1000 0100 0-1- ---- 0--- ---- ---- ----   # SVE 32-bit gather prefetch (scalar+vector)
 FAIL    1010 010- ---- ---- 011- ---- ---- ----   # SVE contiguous FF load (scalar+scalar)
 FAIL    1010 010- ---1 ---- 101- ---- ---- ----   # SVE contiguous NF load (scalar+imm)
 FAIL    1010 010- -01- ---- 000- ---- ---- ----   # SVE load & replicate 32 bytes (scalar+scalar)
 FAIL    1010 010- -010 ---- 001- ---- ---- ----   # SVE load & replicate 32 bytes (scalar+imm)
-FAIL    1100 010- ---- ---- ---- ---- ---- ----   # SVE 64-bit gather load/prefetch
diff --git a/target/arm/sve.decode b/target/arm/sve.decode
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/sve.decode
+++ b/target/arm/sve.decode
@@ -XXX,XX +XXX,XX @@ LD1RO_zpri      1010010 .. 01 0.... 001 ... ..... ..... \
                 @rpri_load_msz nreg=0
 
 # SVE 32-bit gather prefetch (scalar plus 32-bit scaled offsets)
-PRF             1000010 00 -1 ----- 0-- --- ----- 0 ----
+PRF_ns          1000010 00 -1 ----- 0-- --- ----- 0 ----
 
 # SVE 32-bit gather prefetch (vector plus immediate)
-PRF             1000010 -- 00 ----- 111 --- ----- 0 ----
+PRF_ns          1000010 -- 00 ----- 111 --- ----- 0 ----
 
 # SVE contiguous prefetch (scalar plus immediate)
 PRF             1000010 11 1- ----- 0-- --- ----- 0 ----
@@ -XXX,XX +XXX,XX @@ LD1_zpiz        1100010 .. 01 ..... 1.. ... ..... ..... \
                 @rpri_g_load esz=3
 
 # SVE 64-bit gather prefetch (scalar plus 64-bit scaled offsets)
-PRF             1100010 00 11 ----- 1-- --- ----- 0 ----
+PRF_ns          1100010 00 11 ----- 1-- --- ----- 0 ----
 
 # SVE 64-bit gather prefetch (scalar plus unpacked 32-bit scaled offsets)
-PRF             1100010 00 -1 ----- 0-- --- ----- 0 ----
+PRF_ns          1100010 00 -1 ----- 0-- --- ----- 0 ----
 
 # SVE 64-bit gather prefetch (vector plus immediate)
-PRF             1100010 -- 00 ----- 111 --- ----- 0 ----
+PRF_ns          1100010 -- 00 ----- 111 --- ----- 0 ----
 
 ### SVE Memory Store Group
 
diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/translate-sve.c
+++ b/target/arm/translate-sve.c
@@ -XXX,XX +XXX,XX @@ static bool trans_PRF_rr(DisasContext *s, arg_PRF_rr *a)
     return true;
 }
 
+static bool trans_PRF_ns(DisasContext *s, arg_PRF_ns *a)
+{
+    if (!dc_isar_feature(aa64_sve, s)) {
+        return false;
+    }
+    /* Prefetch is a nop within QEMU.  */
+    s->is_nonstreaming = true;
+    (void)sve_access_check(s);
+    return true;
+}
+
 /*
  * Move Prefix
  *
-- 
2.25.1

From: Richard Henderson <richard.henderson@linaro.org>

Mark these as a non-streaming instructions, which should trap
if full a64 support is not enabled in streaming mode.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220708151540.18136-14-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/sme-fa64.decode | 2 --
 target/arm/translate-sve.c | 2 ++
 2 files changed, 2 insertions(+), 2 deletions(-)

From: Richard Henderson <richard.henderson@linaro.org>

Mark these as a non-streaming instructions, which should trap
if full a64 support is not enabled in streaming mode.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220708151540.18136-15-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/sme-fa64.decode | 3 ---
 target/arm/translate-sve.c | 2 ++
 2 files changed, 2 insertions(+), 3 deletions(-)

From: Richard Henderson <richard.henderson@linaro.org>

These functions will be used to verify that the cpu
is in the correct state for a given instruction.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220708151540.18136-16-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/translate-a64.h | 21 +++++++++++++++++++++
 target/arm/translate-a64.c | 34 ++++++++++++++++++++++++++++++++++
 2 files changed, 55 insertions(+)

diff --git a/target/arm/translate-a64.h b/target/arm/translate-a64.h
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/translate-a64.h
+++ b/target/arm/translate-a64.h
@@ -XXX,XX +XXX,XX @@ void write_fp_dreg(DisasContext *s, int reg, TCGv_i64 v);
 bool logic_imm_decode_wmask(uint64_t *result, unsigned int immn,
                             unsigned int imms, unsigned int immr);
 bool sve_access_check(DisasContext *s);
+bool sme_enabled_check(DisasContext *s);
+bool sme_enabled_check_with_svcr(DisasContext *s, unsigned);
+
+/* This function corresponds to CheckStreamingSVEEnabled. */
+static inline bool sme_sm_enabled_check(DisasContext *s)
+{
+    return sme_enabled_check_with_svcr(s, R_SVCR_SM_MASK);
+}
+
+/* This function corresponds to CheckSMEAndZAEnabled. */
+static inline bool sme_za_enabled_check(DisasContext *s)
+{
+    return sme_enabled_check_with_svcr(s, R_SVCR_ZA_MASK);
+}
+
+/* Note that this function corresponds to CheckStreamingSVEAndZAEnabled. */
+static inline bool sme_smza_enabled_check(DisasContext *s)
+{
+    return sme_enabled_check_with_svcr(s, R_SVCR_SM_MASK | R_SVCR_ZA_MASK);
+}
+
 TCGv_i64 clean_data_tbi(DisasContext *s, TCGv_i64 addr);
 TCGv_i64 gen_mte_check1(DisasContext *s, TCGv_i64 addr, bool is_write,
                         bool tag_checked, int log2_size);
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/translate-a64.c
+++ b/target/arm/translate-a64.c
@@ -XXX,XX +XXX,XX @@ static bool sme_access_check(DisasContext *s)
     return true;
 }
 
+/* This function corresponds to CheckSMEEnabled. */
+bool sme_enabled_check(DisasContext *s)
+{
+    /*
+     * Note that unlike sve_excp_el, we have not constrained sme_excp_el
+     * to be zero when fp_excp_el has priority.  This is because we need
+     * sme_excp_el by itself for cpregs access checks.
+     */
+    if (!s->fp_excp_el || s->sme_excp_el < s->fp_excp_el) {
+        s->fp_access_checked = true;
+        return sme_access_check(s);
+    }
+    return fp_access_check_only(s);
+}
+
+/* Common subroutine for CheckSMEAnd*Enabled. */
+bool sme_enabled_check_with_svcr(DisasContext *s, unsigned req)
+{
+    if (!sme_enabled_check(s)) {
+        return false;
+    }
+    if (FIELD_EX64(req, SVCR, SM) && !s->pstate_sm) {
+        gen_exception_insn(s, s->pc_curr, EXCP_UDEF,
+                           syn_smetrap(SME_ET_NotStreaming, false));
+        return false;
+    }
+    if (FIELD_EX64(req, SVCR, ZA) && !s->pstate_za) {
+        gen_exception_insn(s, s->pc_curr, EXCP_UDEF,
+                           syn_smetrap(SME_ET_InactiveZA, false));
+        return false;
+    }
+    return true;
+}
+
 /*
  * This utility function is for doing register extension with an
  * optional shift. You will likely want to pass a temporary for the
-- 
2.25.1

From: Richard Henderson <richard.henderson@linaro.org>

The pseudocode for CheckSVEEnabled gains a check for Streaming
SVE mode, and for SME present but SVE absent.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220708151540.18136-17-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/translate-a64.c | 22 ++++++++++++++++------
 1 file changed, 16 insertions(+), 6 deletions(-)

diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/translate-a64.c
+++ b/target/arm/translate-a64.c
@@ -XXX,XX +XXX,XX @@ static bool fp_access_check(DisasContext *s)
     return true;
 }
 
-/* Check that SVE access is enabled.  If it is, return true.
+/*
+ * Check that SVE access is enabled.  If it is, return true.
  * If not, emit code to generate an appropriate exception and return false.
+ * This function corresponds to CheckSVEEnabled().
  */
 bool sve_access_check(DisasContext *s)
 {
-    if (s->sve_excp_el) {
-        assert(!s->sve_access_checked);
-        s->sve_access_checked = true;
-
+    if (s->pstate_sm || !dc_isar_feature(aa64_sve, s)) {
+        assert(dc_isar_feature(aa64_sme, s));
+        if (!sme_sm_enabled_check(s)) {
+            goto fail_exit;
+        }
+    } else if (s->sve_excp_el) {
         gen_exception_insn_el(s, s->pc_curr, EXCP_UDEF,
                               syn_sve_access_trap(), s->sve_excp_el);
-        return false;
+        goto fail_exit;
     }
     s->sve_access_checked = true;
     return fp_access_check(s);
+
+ fail_exit:
+    /* Assert that we only raise one exception per instruction. */
+    assert(!s->sve_access_checked);
+    s->sve_access_checked = true;
+    return false;
 }
 
 /*
-- 
2.25.1

From: Richard Henderson <richard.henderson@linaro.org>

These SME instructions are nominally within the SVE decode space,
so we add them to sve.decode and translate-sve.c.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220708151540.18136-18-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/translate-a64.h | 12 ++++++++++++
 target/arm/sve.decode      |  5 ++++-
 target/arm/translate-sve.c | 38 ++++++++++++++++++++++++++++++++++++++
 3 files changed, 54 insertions(+), 1 deletion(-)

diff --git a/target/arm/translate-a64.h b/target/arm/translate-a64.h
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/translate-a64.h
+++ b/target/arm/translate-a64.h
@@ -XXX,XX +XXX,XX @@ static inline int vec_full_reg_size(DisasContext *s)
     return s->vl;
 }
 
+/* Return the byte size of the vector register, SVL / 8. */
+static inline int streaming_vec_reg_size(DisasContext *s)
+{
+    return s->svl;
+}
+
 /*
  * Return the offset info CPUARMState of the predicate vector register Pn.
  * Note for this purpose, FFR is P16.
@@ -XXX,XX +XXX,XX @@ static inline int pred_full_reg_size(DisasContext *s)
     return s->vl >> 3;
 }
 
+/* Return the byte size of the predicate register, SVL / 64.  */
+static inline int streaming_pred_reg_size(DisasContext *s)
+{
+    return s->svl >> 3;
+}
+
 /*
  * Round up the size of a register to a size allowed by
  * the tcg vector infrastructure.  Any operation which uses this
diff --git a/target/arm/sve.decode b/target/arm/sve.decode
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/sve.decode
+++ b/target/arm/sve.decode
@@ -XXX,XX +XXX,XX @@ INDEX_ri        00000100 esz:2 1 imm:s5 010001 rn:5 rd:5
 # SVE index generation (register start, register increment)
 INDEX_rr        00000100 .. 1 ..... 010011 ..... .....          @rd_rn_rm
 
-### SVE Stack Allocation Group
+### SVE / Streaming SVE Stack Allocation Group
 
 # SVE stack frame adjustment
 ADDVL           00000100 001 ..... 01010 ...... .....           @rd_rn_i6
+ADDSVL          00000100 001 ..... 01011 ...... .....           @rd_rn_i6
 ADDPL           00000100 011 ..... 01010 ...... .....           @rd_rn_i6
+ADDSPL          00000100 011 ..... 01011 ...... .....           @rd_rn_i6
 
 # SVE stack frame size
 RDVL            00000100 101 11111 01010 imm:s6 rd:5
+RDSVL           00000100 101 11111 01011 imm:s6 rd:5
 
 ### SVE Bitwise Shift - Unpredicated Group
 
diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/translate-sve.c
+++ b/target/arm/translate-sve.c
@@ -XXX,XX +XXX,XX @@ static bool trans_ADDVL(DisasContext *s, arg_ADDVL *a)
     return true;
 }
 
+static bool trans_ADDSVL(DisasContext *s, arg_ADDSVL *a)
+{
+    if (!dc_isar_feature(aa64_sme, s)) {
+        return false;
+    }
+    if (sme_enabled_check(s)) {
+        TCGv_i64 rd = cpu_reg_sp(s, a->rd);
+        TCGv_i64 rn = cpu_reg_sp(s, a->rn);
+        tcg_gen_addi_i64(rd, rn, a->imm * streaming_vec_reg_size(s));
+    }
+    return true;
+}
+
 static bool trans_ADDPL(DisasContext *s, arg_ADDPL *a)
 {
     if (!dc_isar_feature(aa64_sve, s)) {
@@ -XXX,XX +XXX,XX @@ static bool trans_ADDPL(DisasContext *s, arg_ADDPL *a)
     return true;
 }
 
+static bool trans_ADDSPL(DisasContext *s, arg_ADDSPL *a)
+{
+    if (!dc_isar_feature(aa64_sme, s)) {
+        return false;
+    }
+    if (sme_enabled_check(s)) {
+        TCGv_i64 rd = cpu_reg_sp(s, a->rd);
+        TCGv_i64 rn = cpu_reg_sp(s, a->rn);
+        tcg_gen_addi_i64(rd, rn, a->imm * streaming_pred_reg_size(s));
+    }
+    return true;
+}
+
 static bool trans_RDVL(DisasContext *s, arg_RDVL *a)
 {
     if (!dc_isar_feature(aa64_sve, s)) {
@@ -XXX,XX +XXX,XX @@ static bool trans_RDVL(DisasContext *s, arg_RDVL *a)
     return true;
 }
 
+static bool trans_RDSVL(DisasContext *s, arg_RDSVL *a)
+{
+    if (!dc_isar_feature(aa64_sme, s)) {
+        return false;
+    }
+    if (sme_enabled_check(s)) {
+        TCGv_i64 reg = cpu_reg(s, a->rd);
+        tcg_gen_movi_i64(reg, a->imm * streaming_vec_reg_size(s));
+    }
+    return true;
+}
+
 /*
  *** SVE Compute Vector Address Group
  */
-- 
2.25.1

From: Richard Henderson <richard.henderson@linaro.org>

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220708151540.18136-19-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/helper-sme.h    |  2 ++
 target/arm/sme.decode      |  4 ++++
 target/arm/sme_helper.c    | 25 +++++++++++++++++++++++++
 target/arm/translate-sme.c | 13 +++++++++++++
 4 files changed, 44 insertions(+)

From: Richard Henderson <richard.henderson@linaro.org>

We can reuse the SVE functions for implementing moves to/from
horizontal tile slices, but we need new ones for moves to/from
vertical tile slices.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220708151540.18136-20-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/helper-sme.h    |  12 +++
 target/arm/helper-sve.h    |   2 +
 target/arm/translate-a64.h |   8 ++
 target/arm/translate.h     |   5 ++
 target/arm/sme.decode      |  15 ++++
 target/arm/sme_helper.c    | 151 ++++++++++++++++++++++++++++++++++++-
 target/arm/sve_helper.c    |  12 +++
 target/arm/translate-sme.c | 127 +++++++++++++++++++++++++++++++
 8 files changed, 331 insertions(+), 1 deletion(-)

From: Richard Henderson <richard.henderson@linaro.org>

We cannot reuse the SVE functions for LD[1-4] and ST[1-4],
because those functions accept only a Zreg register number.
For SME, we want to pass a pointer into ZA storage.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220708151540.18136-21-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/helper-sme.h    |  82 +++++
 target/arm/sme.decode      |   9 +
 target/arm/sme_helper.c    | 595 +++++++++++++++++++++++++++++++++++++
 target/arm/translate-sme.c |  70 +++++
 4 files changed, 756 insertions(+)

diff --git a/target/arm/helper-sme.h b/target/arm/helper-sme.h
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/helper-sme.h
+++ b/target/arm/helper-sme.h
@@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_4(sme_mova_cz_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
 DEF_HELPER_FLAGS_4(sme_mova_zc_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
 DEF_HELPER_FLAGS_4(sme_mova_cz_q, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
 DEF_HELPER_FLAGS_4(sme_mova_zc_q, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
+
+DEF_HELPER_FLAGS_5(sme_ld1b_h, TCG_CALL_NO_WG, void, env, ptr, ptr, tl, i32)
+DEF_HELPER_FLAGS_5(sme_ld1b_v, TCG_CALL_NO_WG, void, env, ptr, ptr, tl, i32)
+DEF_HELPER_FLAGS_5(sme_ld1b_h_mte, TCG_CALL_NO_WG, void, env, ptr, ptr, tl, i32)
+DEF_HELPER_FLAGS_5(sme_ld1b_v_mte, TCG_CALL_NO_WG, void, env, ptr, ptr, tl, i32)
+
+DEF_HELPER_FLAGS_5(sme_ld1h_be_h, TCG_CALL_NO_WG, void, env, ptr, ptr, tl, i32)
+DEF_HELPER_FLAGS_5(sme_ld1h_le_h, TCG_CALL_NO_WG, void, env, ptr, ptr, tl, i32)
+DEF_HELPER_FLAGS_5(sme_ld1h_be_v, TCG_CALL_NO_WG, void, env, ptr, ptr, tl, i32)
+DEF_HELPER_FLAGS_5(sme_ld1h_le_v, TCG_CALL_NO_WG, void, env, ptr, ptr, tl, i32)
+DEF_HELPER_FLAGS_5(sme_ld1h_be_h_mte, TCG_CALL_NO_WG, void, env, ptr, ptr, tl, i32)
+DEF_HELPER_FLAGS_5(sme_ld1h_le_h_mte, TCG_CALL_NO_WG, void, env, ptr, ptr, tl, i32)
+DEF_HELPER_FLAGS_5(sme_ld1h_be_v_mte, TCG_CALL_NO_WG, void, env, ptr, ptr, tl, i32)
+DEF_HELPER_FLAGS_5(sme_ld1h_le_v_mte, TCG_CALL_NO_WG, void, env, ptr, ptr, tl, i32)
+
+DEF_HELPER_FLAGS_5(sme_ld1s_be_h, TCG_CALL_NO_WG, void, env, ptr, ptr, tl, i32)
+DEF_HELPER_FLAGS_5(sme_ld1s_le_h, TCG_CALL_NO_WG, void, env, ptr, ptr, tl, i32)
+DEF_HELPER_FLAGS_5(sme_ld1s_be_v, TCG_CALL_NO_WG, void, env, ptr, ptr, tl, i32)
+DEF_HELPER_FLAGS_5(sme_ld1s_le_v, TCG_CALL_NO_WG, void, env, ptr, ptr, tl, i32)
+DEF_HELPER_FLAGS_5(sme_ld1s_be_h_mte, TCG_CALL_NO_WG, void, env, ptr, ptr, tl, i32)
+DEF_HELPER_FLAGS_5(sme_ld1s_le_h_mte, TCG_CALL_NO_WG, void, env, ptr, ptr, tl, i32)
+DEF_HELPER_FLAGS_5(sme_ld1s_be_v_mte, TCG_CALL_NO_WG, void, env, ptr, ptr, tl, i32)
+DEF_HELPER_FLAGS_5(sme_ld1s_le_v_mte, TCG_CALL_NO_WG, void, env, ptr, ptr, tl, i32)
+
+DEF_HELPER_FLAGS_5(sme_ld1d_be_h, TCG_CALL_NO_WG, void, env, ptr, ptr, tl, i32)
+DEF_HELPER_FLAGS_5(sme_ld1d_le_h, TCG_CALL_NO_WG, void, env, ptr, ptr, tl, i32)
+DEF_HELPER_FLAGS_5(sme_ld1d_be_v, TCG_CALL_NO_WG, void, env, ptr, ptr, tl, i32)
+DEF_HELPER_FLAGS_5(sme_ld1d_le_v, TCG_CALL_NO_WG, void, env, ptr, ptr, tl, i32)
+DEF_HELPER_FLAGS_5(sme_ld1d_be_h_mte, TCG_CALL_NO_WG, void, env, ptr, ptr, tl, i32)
+DEF_HELPER_FLAGS_5(sme_ld1d_le_h_mte, TCG_CALL_NO_WG, void, env, ptr, ptr, tl, i32)
+DEF_HELPER_FLAGS_5(sme_ld1d_be_v_mte, TCG_CALL_NO_WG, void, env, ptr, ptr, tl, i32)
+DEF_HELPER_FLAGS_5(sme_ld1d_le_v_mte, TCG_CALL_NO_WG, void, env, ptr, ptr, tl, i32)
+
+DEF_HELPER_FLAGS_5(sme_ld1q_be_h, TCG_CALL_NO_WG, void, env, ptr, ptr, tl, i32)
+DEF_HELPER_FLAGS_5(sme_ld1q_le_h, TCG_CALL_NO_WG, void, env, ptr, ptr, tl, i32)
+DEF_HELPER_FLAGS_5(sme_ld1q_be_v, TCG_CALL_NO_WG, void, env, ptr, ptr, tl, i32)
+DEF_HELPER_FLAGS_5(sme_ld1q_le_v, TCG_CALL_NO_WG, void, env, ptr, ptr, tl, i32)
+DEF_HELPER_FLAGS_5(sme_ld1q_be_h_mte, TCG_CALL_NO_WG, void, env, ptr, ptr, tl, i32)
+DEF_HELPER_FLAGS_5(sme_ld1q_le_h_mte, TCG_CALL_NO_WG, void, env, ptr, ptr, tl, i32)
+DEF_HELPER_FLAGS_5(sme_ld1q_be_v_mte, TCG_CALL_NO_WG, void, env, ptr, ptr, tl, i32)
+DEF_HELPER_FLAGS_5(sme_ld1q_le_v_mte, TCG_CALL_NO_WG, void, env, ptr, ptr, tl, i32)
+
+DEF_HELPER_FLAGS_5(sme_st1b_h, TCG_CALL_NO_WG, void, env, ptr, ptr, tl, i32)
+DEF_HELPER_FLAGS_5(sme_st1b_v, TCG_CALL_NO_WG, void, env, ptr, ptr, tl, i32)
+DEF_HELPER_FLAGS_5(sme_st1b_h_mte, TCG_CALL_NO_WG, void, env, ptr, ptr, tl, i32)
+DEF_HELPER_FLAGS_5(sme_st1b_v_mte, TCG_CALL_NO_WG, void, env, ptr, ptr, tl, i32)
+
+DEF_HELPER_FLAGS_5(sme_st1h_be_h, TCG_CALL_NO_WG, void, env, ptr, ptr, tl, i32)
+DEF_HELPER_FLAGS_5(sme_st1h_le_h, TCG_CALL_NO_WG, void, env, ptr, ptr, tl, i32)
+DEF_HELPER_FLAGS_5(sme_st1h_be_v, TCG_CALL_NO_WG, void, env, ptr, ptr, tl, i32)
+DEF_HELPER_FLAGS_5(sme_st1h_le_v, TCG_CALL_NO_WG, void, env, ptr, ptr, tl, i32)
+DEF_HELPER_FLAGS_5(sme_st1h_be_h_mte, TCG_CALL_NO_WG, void, env, ptr, ptr, tl, i32)
+DEF_HELPER_FLAGS_5(sme_st1h_le_h_mte, TCG_CALL_NO_WG, void, env, ptr, ptr, tl, i32)
+DEF_HELPER_FLAGS_5(sme_st1h_be_v_mte, TCG_CALL_NO_WG, void, env, ptr, ptr, tl, i32)
+DEF_HELPER_FLAGS_5(sme_st1h_le_v_mte, TCG_CALL_NO_WG, void, env, ptr, ptr, tl, i32)
+
+DEF_HELPER_FLAGS_5(sme_st1s_be_h, TCG_CALL_NO_WG, void, env, ptr, ptr, tl, i32)
+DEF_HELPER_FLAGS_5(sme_st1s_le_h, TCG_CALL_NO_WG, void, env, ptr, ptr, tl, i32)
+DEF_HELPER_FLAGS_5(sme_st1s_be_v, TCG_CALL_NO_WG, void, env, ptr, ptr, tl, i32)
+DEF_HELPER_FLAGS_5(sme_st1s_le_v, TCG_CALL_NO_WG, void, env, ptr, ptr, tl, i32)
+DEF_HELPER_FLAGS_5(sme_st1s_be_h_mte, TCG_CALL_NO_WG, void, env, ptr, ptr, tl, i32)
+DEF_HELPER_FLAGS_5(sme_st1s_le_h_mte, TCG_CALL_NO_WG, void, env, ptr, ptr, tl, i32)
+DEF_HELPER_FLAGS_5(sme_st1s_be_v_mte, TCG_CALL_NO_WG, void, env, ptr, ptr, tl, i32)
+DEF_HELPER_FLAGS_5(sme_st1s_le_v_mte, TCG_CALL_NO_WG, void, env, ptr, ptr, tl, i32)
+
+DEF_HELPER_FLAGS_5(sme_st1d_be_h, TCG_CALL_NO_WG, void, env, ptr, ptr, tl, i32)
+DEF_HELPER_FLAGS_5(sme_st1d_le_h, TCG_CALL_NO_WG, void, env, ptr, ptr, tl, i32)
+DEF_HELPER_FLAGS_5(sme_st1d_be_v, TCG_CALL_NO_WG, void, env, ptr, ptr, tl, i32)
+DEF_HELPER_FLAGS_5(sme_st1d_le_v, TCG_CALL_NO_WG, void, env, ptr, ptr, tl, i32)
+DEF_HELPER_FLAGS_5(sme_st1d_be_h_mte, TCG_CALL_NO_WG, void, env, ptr, ptr, tl, i32)
+DEF_HELPER_FLAGS_5(sme_st1d_le_h_mte, TCG_CALL_NO_WG, void, env, ptr, ptr, tl, i32)
+DEF_HELPER_FLAGS_5(sme_st1d_be_v_mte, TCG_CALL_NO_WG, void, env, ptr, ptr, tl, i32)
+DEF_HELPER_FLAGS_5(sme_st1d_le_v_mte, TCG_CALL_NO_WG, void, env, ptr, ptr, tl, i32)
+
+DEF_HELPER_FLAGS_5(sme_st1q_be_h, TCG_CALL_NO_WG, void, env, ptr, ptr, tl, i32)
+DEF_HELPER_FLAGS_5(sme_st1q_le_h, TCG_CALL_NO_WG, void, env, ptr, ptr, tl, i32)
+DEF_HELPER_FLAGS_5(sme_st1q_be_v, TCG_CALL_NO_WG, void, env, ptr, ptr, tl, i32)
+DEF_HELPER_FLAGS_5(sme_st1q_le_v, TCG_CALL_NO_WG, void, env, ptr, ptr, tl, i32)
+DEF_HELPER_FLAGS_5(sme_st1q_be_h_mte, TCG_CALL_NO_WG, void, env, ptr, ptr, tl, i32)
+DEF_HELPER_FLAGS_5(sme_st1q_le_h_mte, TCG_CALL_NO_WG, void, env, ptr, ptr, tl, i32)
+DEF_HELPER_FLAGS_5(sme_st1q_be_v_mte, TCG_CALL_NO_WG, void, env, ptr, ptr, tl, i32)
+DEF_HELPER_FLAGS_5(sme_st1q_le_v_mte, TCG_CALL_NO_WG, void, env, ptr, ptr, tl, i32)
diff --git a/target/arm/sme.decode b/target/arm/sme.decode
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/sme.decode
+++ b/target/arm/sme.decode
@@ -XXX,XX +XXX,XX @@ MOVA            11000000 esz:2 00001 0 v:1 .. pg:3 0 za_imm:4 zr:5  \
                 &mova to_vec=1 rs=%mova_rs
 MOVA            11000000 11    00001 1 v:1 .. pg:3 0 za_imm:4 zr:5  \
                 &mova to_vec=1 rs=%mova_rs esz=4
+
+### SME Memory
+
+&ldst           esz rs pg rn rm za_imm v:bool st:bool
+
+LDST1           1110000 0 esz:2 st:1 rm:5 v:1 .. pg:3 rn:5 0 za_imm:4  \
+                &ldst rs=%mova_rs
+LDST1           1110000 111     st:1 rm:5 v:1 .. pg:3 rn:5 0 za_imm:4  \
+                &ldst esz=4 rs=%mova_rs
diff --git a/target/arm/sme_helper.c b/target/arm/sme_helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/sme_helper.c
+++ b/target/arm/sme_helper.c
@@ -XXX,XX +XXX,XX @@
 
 #include "qemu/osdep.h"
 #include "cpu.h"
+#include "internals.h"
 #include "tcg/tcg-gvec-desc.h"
 #include "exec/helper-proto.h"
+#include "exec/cpu_ldst.h"
+#include "exec/exec-all.h"
 #include "qemu/int128.h"
 #include "vec_internal.h"
+#include "sve_ldst_internal.h"
 
 /* ResetSVEState */
 void arm_reset_sve_state(CPUARMState *env)
@@ -XXX,XX +XXX,XX @@ void HELPER(sme_mova_zc_q)(void *vd, void *za, void *vg, uint32_t desc)
 }
 
 #undef DO_MOVA_Z
+
+/*
+ * Clear elements in a tile slice comprising len bytes.
+ */
+
+typedef void ClearFn(void *ptr, size_t off, size_t len);
+
+static void clear_horizontal(void *ptr, size_t off, size_t len)
+{
+    memset(ptr + off, 0, len);
+}
+
+static void clear_vertical_b(void *vptr, size_t off, size_t len)
+{
+    for (size_t i = 0; i < len; ++i) {
+        *(uint8_t *)(vptr + tile_vslice_offset(i + off)) = 0;
+    }
+}
+
+static void clear_vertical_h(void *vptr, size_t off, size_t len)
+{
+    for (size_t i = 0; i < len; i += 2) {
+        *(uint16_t *)(vptr + tile_vslice_offset(i + off)) = 0;
+    }
+}
+
+static void clear_vertical_s(void *vptr, size_t off, size_t len)
+{
+    for (size_t i = 0; i < len; i += 4) {
+        *(uint32_t *)(vptr + tile_vslice_offset(i + off)) = 0;
+    }
+}
+
+static void clear_vertical_d(void *vptr, size_t off, size_t len)
+{
+    for (size_t i = 0; i < len; i += 8) {
+        *(uint64_t *)(vptr + tile_vslice_offset(i + off)) = 0;
+    }
+}
+
+static void clear_vertical_q(void *vptr, size_t off, size_t len)
+{
+    for (size_t i = 0; i < len; i += 16) {
+        memset(vptr + tile_vslice_offset(i + off), 0, 16);
+    }
+}
+
+/*
+ * Copy elements from an array into a tile slice comprising len bytes.
+ */
+
+typedef void CopyFn(void *dst, const void *src, size_t len);
+
+static void copy_horizontal(void *dst, const void *src, size_t len)
+{
+    memcpy(dst, src, len);
+}
+
+static void copy_vertical_b(void *vdst, const void *vsrc, size_t len)
+{
+    const uint8_t *src = vsrc;
+    uint8_t *dst = vdst;
+    size_t i;
+
+    for (i = 0; i < len; ++i) {
+        dst[tile_vslice_index(i)] = src[i];
+    }
+}
+
+static void copy_vertical_h(void *vdst, const void *vsrc, size_t len)
+{
+    const uint16_t *src = vsrc;
+    uint16_t *dst = vdst;
+    size_t i;
+
+    for (i = 0; i < len / 2; ++i) {
+        dst[tile_vslice_index(i)] = src[i];
+    }
+}
+
+static void copy_vertical_s(void *vdst, const void *vsrc, size_t len)
+{
+    const uint32_t *src = vsrc;
+    uint32_t *dst = vdst;
+    size_t i;
+
+    for (i = 0; i < len / 4; ++i) {
+        dst[tile_vslice_index(i)] = src[i];
+    }
+}
+
+static void copy_vertical_d(void *vdst, const void *vsrc, size_t len)
+{
+    const uint64_t *src = vsrc;
+    uint64_t *dst = vdst;
+    size_t i;
+
+    for (i = 0; i < len / 8; ++i) {
+        dst[tile_vslice_index(i)] = src[i];
+    }
+}
+
+static void copy_vertical_q(void *vdst, const void *vsrc, size_t len)
+{
+    for (size_t i = 0; i < len; i += 16) {
+        memcpy(vdst + tile_vslice_offset(i), vsrc + i, 16);
+    }
+}
+
+/*
+ * Host and TLB primitives for vertical tile slice addressing.
+ */
+
+#define DO_LD(NAME, TYPE, HOST, TLB)                                        \
+static inline void sme_##NAME##_v_host(void *za, intptr_t off, void *host)  \
+{                                                                           \
+    TYPE val = HOST(host);                                                  \
+    *(TYPE *)(za + tile_vslice_offset(off)) = val;                          \
+}                                                                           \
+static inline void sme_##NAME##_v_tlb(CPUARMState *env, void *za,           \
+                        intptr_t off, target_ulong addr, uintptr_t ra)      \
+{                                                                           \
+    TYPE val = TLB(env, useronly_clean_ptr(addr), ra);                      \
+    *(TYPE *)(za + tile_vslice_offset(off)) = val;                          \
+}
+
+#define DO_ST(NAME, TYPE, HOST, TLB)                                        \
+static inline void sme_##NAME##_v_host(void *za, intptr_t off, void *host)  \
+{                                                                           \
+    TYPE val = *(TYPE *)(za + tile_vslice_offset(off));                     \
+    HOST(host, val);                                                        \
+}                                                                           \
+static inline void sme_##NAME##_v_tlb(CPUARMState *env, void *za,           \
+                        intptr_t off, target_ulong addr, uintptr_t ra)      \
+{                                                                           \
+    TYPE val = *(TYPE *)(za + tile_vslice_offset(off));                     \
+    TLB(env, useronly_clean_ptr(addr), val, ra);                            \
+}
+
+/*
+ * The ARMVectorReg elements are stored in host-endian 64-bit units.
+ * For 128-bit quantities, the sequence defined by the Elem[] pseudocode
+ * corresponds to storing the two 64-bit pieces in little-endian order.
+ */
+#define DO_LDQ(HNAME, VNAME, BE, HOST, TLB)                                 \
+static inline void HNAME##_host(void *za, intptr_t off, void *host)         \
+{                                                                           \
+    uint64_t val0 = HOST(host), val1 = HOST(host + 8);                      \
+    uint64_t *ptr = za + off;                                               \
+    ptr[0] = BE ? val1 : val0, ptr[1] = BE ? val0 : val1;                   \
+}                                                                           \
+static inline void VNAME##_v_host(void *za, intptr_t off, void *host)       \
+{                                                                           \
+    HNAME##_host(za, tile_vslice_offset(off), host);                        \
+}                                                                           \
+static inline void HNAME##_tlb(CPUARMState *env, void *za, intptr_t off,    \
+                               target_ulong addr, uintptr_t ra)             \
+{                                                                           \
+    uint64_t val0 = TLB(env, useronly_clean_ptr(addr), ra);                 \
+    uint64_t val1 = TLB(env, useronly_clean_ptr(addr + 8), ra);             \
+    uint64_t *ptr = za + off;                                               \
+    ptr[0] = BE ? val1 : val0, ptr[1] = BE ? val0 : val1;                   \
+}                                                                           \
+static inline void VNAME##_v_tlb(CPUARMState *env, void *za, intptr_t off,  \
+                               target_ulong addr, uintptr_t ra)             \
+{                                                                           \
+    HNAME##_tlb(env, za, tile_vslice_offset(off), addr, ra);                \
+}
+
+#define DO_STQ(HNAME, VNAME, BE, HOST, TLB)                                 \
+static inline void HNAME##_host(void *za, intptr_t off, void *host)         \
+{                                                                           \
+    uint64_t *ptr = za + off;                                               \
+    HOST(host, ptr[BE]);                                                    \
+    HOST(host + 1, ptr[!BE]);                                               \
+}                                                                           \
+static inline void VNAME##_v_host(void *za, intptr_t off, void *host)       \
+{                                                                           \
+    HNAME##_host(za, tile_vslice_offset(off), host);                        \
+}                                                                           \
+static inline void HNAME##_tlb(CPUARMState *env, void *za, intptr_t off,    \
+                               target_ulong addr, uintptr_t ra)             \
+{                                                                           \
+    uint64_t *ptr = za + off;                                               \
+    TLB(env, useronly_clean_ptr(addr), ptr[BE], ra);                        \
+    TLB(env, useronly_clean_ptr(addr + 8), ptr[!BE], ra);                   \
+}                                                                           \
+static inline void VNAME##_v_tlb(CPUARMState *env, void *za, intptr_t off,  \
+                               target_ulong addr, uintptr_t ra)             \
+{                                                                           \
+    HNAME##_tlb(env, za, tile_vslice_offset(off), addr, ra);                \
+}
+
+DO_LD(ld1b, uint8_t, ldub_p, cpu_ldub_data_ra)
+DO_LD(ld1h_be, uint16_t, lduw_be_p, cpu_lduw_be_data_ra)
+DO_LD(ld1h_le, uint16_t, lduw_le_p, cpu_lduw_le_data_ra)
+DO_LD(ld1s_be, uint32_t, ldl_be_p, cpu_ldl_be_data_ra)
+DO_LD(ld1s_le, uint32_t, ldl_le_p, cpu_ldl_le_data_ra)
+DO_LD(ld1d_be, uint64_t, ldq_be_p, cpu_ldq_be_data_ra)
+DO_LD(ld1d_le, uint64_t, ldq_le_p, cpu_ldq_le_data_ra)
+
+DO_LDQ(sve_ld1qq_be, sme_ld1q_be, 1, ldq_be_p, cpu_ldq_be_data_ra)
+DO_LDQ(sve_ld1qq_le, sme_ld1q_le, 0, ldq_le_p, cpu_ldq_le_data_ra)
+
+DO_ST(st1b, uint8_t, stb_p, cpu_stb_data_ra)
+DO_ST(st1h_be, uint16_t, stw_be_p, cpu_stw_be_data_ra)
+DO_ST(st1h_le, uint16_t, stw_le_p, cpu_stw_le_data_ra)
+DO_ST(st1s_be, uint32_t, stl_be_p, cpu_stl_be_data_ra)
+DO_ST(st1s_le, uint32_t, stl_le_p, cpu_stl_le_data_ra)
+DO_ST(st1d_be, uint64_t, stq_be_p, cpu_stq_be_data_ra)
+DO_ST(st1d_le, uint64_t, stq_le_p, cpu_stq_le_data_ra)
+
+DO_STQ(sve_st1qq_be, sme_st1q_be, 1, stq_be_p, cpu_stq_be_data_ra)
+DO_STQ(sve_st1qq_le, sme_st1q_le, 0, stq_le_p, cpu_stq_le_data_ra)
+
+#undef DO_LD
+#undef DO_ST
+#undef DO_LDQ
+#undef DO_STQ
+
+/*
+ * Common helper for all contiguous predicated loads.
+ */
+
+static inline QEMU_ALWAYS_INLINE
+void sme_ld1(CPUARMState *env, void *za, uint64_t *vg,
+             const target_ulong addr, uint32_t desc, const uintptr_t ra,
+             const int esz, uint32_t mtedesc, bool vertical,
+             sve_ldst1_host_fn *host_fn,
+             sve_ldst1_tlb_fn *tlb_fn,
+             ClearFn *clr_fn,
+             CopyFn *cpy_fn)
+{
+    const intptr_t reg_max = simd_oprsz(desc);
+    const intptr_t esize = 1 << esz;
+    intptr_t reg_off, reg_last;
+    SVEContLdSt info;
+    void *host;
+    int flags;
+
+    /* Find the active elements.  */
+    if (!sve_cont_ldst_elements(&info, addr, vg, reg_max, esz, esize)) {
+        /* The entire predicate was false; no load occurs.  */
+        clr_fn(za, 0, reg_max);
+        return;
+    }
+
+    /* Probe the page(s).  Exit with exception for any invalid page. */
+    sve_cont_ldst_pages(&info, FAULT_ALL, env, addr, MMU_DATA_LOAD, ra);
+
+    /* Handle watchpoints for all active elements. */
+    sve_cont_ldst_watchpoints(&info, env, vg, addr, esize, esize,
+                              BP_MEM_READ, ra);
+
+    /*
+     * Handle mte checks for all active elements.
+     * Since TBI must be set for MTE, !mtedesc => !mte_active.
+     */
+    if (mtedesc) {
+        sve_cont_ldst_mte_check(&info, env, vg, addr, esize, esize,
+                                mtedesc, ra);
+    }
+
+    flags = info.page[0].flags | info.page[1].flags;
+    if (unlikely(flags != 0)) {
+#ifdef CONFIG_USER_ONLY
+        g_assert_not_reached();
+#else
+        /*
+         * At least one page includes MMIO.
+         * Any bus operation can fail with cpu_transaction_failed,
+         * which for ARM will raise SyncExternal.  Perform the load
+         * into scratch memory to preserve register state until the end.
+         */
+        ARMVectorReg scratch = { };
+
+        reg_off = info.reg_off_first[0];
+        reg_last = info.reg_off_last[1];
+        if (reg_last < 0) {
+            reg_last = info.reg_off_split;
+            if (reg_last < 0) {
+                reg_last = info.reg_off_last[0];
+            }
+        }
+
+        do {
+            uint64_t pg = vg[reg_off >> 6];
+            do {
+                if ((pg >> (reg_off & 63)) & 1) {
+                    tlb_fn(env, &scratch, reg_off, addr + reg_off, ra);
+                }
+                reg_off += esize;
+            } while (reg_off & 63);
+        } while (reg_off <= reg_last);
+
+        cpy_fn(za, &scratch, reg_max);
+        return;
+#endif
+    }
+
+    /* The entire operation is in RAM, on valid pages. */
+
+    reg_off = info.reg_off_first[0];
+    reg_last = info.reg_off_last[0];
+    host = info.page[0].host;
+
+    if (!vertical) {
+        memset(za, 0, reg_max);
+    } else if (reg_off) {
+        clr_fn(za, 0, reg_off);
+    }
+
+    while (reg_off <= reg_last) {
+        uint64_t pg = vg[reg_off >> 6];
+        do {
+            if ((pg >> (reg_off & 63)) & 1) {
+                host_fn(za, reg_off, host + reg_off);
+            } else if (vertical) {
+                clr_fn(za, reg_off, esize);
+            }
+            reg_off += esize;
+        } while (reg_off <= reg_last && (reg_off & 63));
+    }
+
+    /*
+     * Use the slow path to manage the cross-page misalignment.
+     * But we know this is RAM and cannot trap.
+     */
+    reg_off = info.reg_off_split;
+    if (unlikely(reg_off >= 0)) {
+        tlb_fn(env, za, reg_off, addr + reg_off, ra);
+    }
+
+    reg_off = info.reg_off_first[1];
+    if (unlikely(reg_off >= 0)) {
+        reg_last = info.reg_off_last[1];
+        host = info.page[1].host;
+
+        do {
+            uint64_t pg = vg[reg_off >> 6];
+            do {
+                if ((pg >> (reg_off & 63)) & 1) {
+                    host_fn(za, reg_off, host + reg_off);
+                } else if (vertical) {
+                    clr_fn(za, reg_off, esize);
+                }
+                reg_off += esize;
+            } while (reg_off & 63);
+        } while (reg_off <= reg_last);
+    }
+}
+
+static inline QEMU_ALWAYS_INLINE
+void sme_ld1_mte(CPUARMState *env, void *za, uint64_t *vg,
+                 target_ulong addr, uint32_t desc, uintptr_t ra,
+                 const int esz, bool vertical,
+                 sve_ldst1_host_fn *host_fn,
+                 sve_ldst1_tlb_fn *tlb_fn,
+                 ClearFn *clr_fn,
+                 CopyFn *cpy_fn)
+{
+    uint32_t mtedesc = desc >> (SIMD_DATA_SHIFT + SVE_MTEDESC_SHIFT);
+    int bit55 = extract64(addr, 55, 1);
+
+    /* Remove mtedesc from the normal sve descriptor. */
+    desc = extract32(desc, 0, SIMD_DATA_SHIFT + SVE_MTEDESC_SHIFT);
+
+    /* Perform gross MTE suppression early. */
+    if (!tbi_check(desc, bit55) ||
+        tcma_check(desc, bit55, allocation_tag_from_addr(addr))) {
+        mtedesc = 0;
+    }
+
+    sme_ld1(env, za, vg, addr, desc, ra, esz, mtedesc, vertical,
+            host_fn, tlb_fn, clr_fn, cpy_fn);
+}
+
+#define DO_LD(L, END, ESZ)                                                 \
+void HELPER(sme_ld1##L##END##_h)(CPUARMState *env, void *za, void *vg,     \
+                                 target_ulong addr, uint32_t desc)         \
+{                                                                          \
+    sme_ld1(env, za, vg, addr, desc, GETPC(), ESZ, 0, false,               \
+            sve_ld1##L##L##END##_host, sve_ld1##L##L##END##_tlb,           \
+            clear_horizontal, copy_horizontal);                            \
+}                                                                          \
+void HELPER(sme_ld1##L##END##_v)(CPUARMState *env, void *za, void *vg,     \
+                                 target_ulong addr, uint32_t desc)         \
+{                                                                          \
+    sme_ld1(env, za, vg, addr, desc, GETPC(), ESZ, 0, true,                \
+            sme_ld1##L##END##_v_host, sme_ld1##L##END##_v_tlb,             \
+            clear_vertical_##L, copy_vertical_##L);                        \
+}                                                                          \
+void HELPER(sme_ld1##L##END##_h_mte)(CPUARMState *env, void *za, void *vg, \
+                                     target_ulong addr, uint32_t desc)     \
+{                                                                          \
+    sme_ld1_mte(env, za, vg, addr, desc, GETPC(), ESZ, false,              \
+                sve_ld1##L##L##END##_host, sve_ld1##L##L##END##_tlb,       \
+                clear_horizontal, copy_horizontal);                        \
+}                                                                          \
+void HELPER(sme_ld1##L##END##_v_mte)(CPUARMState *env, void *za, void *vg, \
+                                     target_ulong addr, uint32_t desc)     \
+{                                                                          \
+    sme_ld1_mte(env, za, vg, addr, desc, GETPC(), ESZ, true,               \
+                sme_ld1##L##END##_v_host, sme_ld1##L##END##_v_tlb,         \
+                clear_vertical_##L, copy_vertical_##L);                    \
+}
+
+DO_LD(b, , MO_8)
+DO_LD(h, _be, MO_16)
+DO_LD(h, _le, MO_16)
+DO_LD(s, _be, MO_32)
+DO_LD(s, _le, MO_32)
+DO_LD(d, _be, MO_64)
+DO_LD(d, _le, MO_64)
+DO_LD(q, _be, MO_128)
+DO_LD(q, _le, MO_128)
+
+#undef DO_LD
+
+/*
+ * Common helper for all contiguous predicated stores.
+ */
+
+static inline QEMU_ALWAYS_INLINE
+void sme_st1(CPUARMState *env, void *za, uint64_t *vg,
+             const target_ulong addr, uint32_t desc, const uintptr_t ra,
+             const int esz, uint32_t mtedesc, bool vertical,
+             sve_ldst1_host_fn *host_fn,
+             sve_ldst1_tlb_fn *tlb_fn)
+{
+    const intptr_t reg_max = simd_oprsz(desc);
+    const intptr_t esize = 1 << esz;
+    intptr_t reg_off, reg_last;
+    SVEContLdSt info;
+    void *host;
+    int flags;
+
+    /* Find the active elements.  */
+    if (!sve_cont_ldst_elements(&info, addr, vg, reg_max, esz, esize)) {
+        /* The entire predicate was false; no store occurs.  */
+        return;
+    }
+
+    /* Probe the page(s).  Exit with exception for any invalid page. */
+    sve_cont_ldst_pages(&info, FAULT_ALL, env, addr, MMU_DATA_STORE, ra);
+
+    /* Handle watchpoints for all active elements. */
+    sve_cont_ldst_watchpoints(&info, env, vg, addr, esize, esize,
+                              BP_MEM_WRITE, ra);
+
+    /*
+     * Handle mte checks for all active elements.
+     * Since TBI must be set for MTE, !mtedesc => !mte_active.
+     */
+    if (mtedesc) {
+        sve_cont_ldst_mte_check(&info, env, vg, addr, esize, esize,
+                                mtedesc, ra);
+    }
+
+    flags = info.page[0].flags | info.page[1].flags;
+    if (unlikely(flags != 0)) {
+#ifdef CONFIG_USER_ONLY
+        g_assert_not_reached();
+#else
+        /*
+         * At least one page includes MMIO.
+         * Any bus operation can fail with cpu_transaction_failed,
+         * which for ARM will raise SyncExternal.  We cannot avoid
+         * this fault and will leave with the store incomplete.
+         */
+        reg_off = info.reg_off_first[0];
+        reg_last = info.reg_off_last[1];
+        if (reg_last < 0) {
+            reg_last = info.reg_off_split;
+            if (reg_last < 0) {
+                reg_last = info.reg_off_last[0];
+            }
+        }
+
+        do {
+            uint64_t pg = vg[reg_off >> 6];
+            do {
+                if ((pg >> (reg_off & 63)) & 1) {
+                    tlb_fn(env, za, reg_off, addr + reg_off, ra);
+                }
+                reg_off += esize;
+            } while (reg_off & 63);
+        } while (reg_off <= reg_last);
+        return;
+#endif
+    }
+
+    reg_off = info.reg_off_first[0];
+    reg_last = info.reg_off_last[0];
+    host = info.page[0].host;
+
+    while (reg_off <= reg_last) {
+        uint64_t pg = vg[reg_off >> 6];
+        do {
+            if ((pg >> (reg_off & 63)) & 1) {
+                host_fn(za, reg_off, host + reg_off);
+            }
+            reg_off += 1 << esz;
+        } while (reg_off <= reg_last && (reg_off & 63));
+    }
+
+    /*
+     * Use the slow path to manage the cross-page misalignment.
+     * But we know this is RAM and cannot trap.
+     */
+    reg_off = info.reg_off_split;
+    if (unlikely(reg_off >= 0)) {
+        tlb_fn(env, za, reg_off, addr + reg_off, ra);
+    }
+
+    reg_off = info.reg_off_first[1];
+    if (unlikely(reg_off >= 0)) {
+        reg_last = info.reg_off_last[1];
+        host = info.page[1].host;
+
+        do {
+            uint64_t pg = vg[reg_off >> 6];
+            do {
+                if ((pg >> (reg_off & 63)) & 1) {
+                    host_fn(za, reg_off, host + reg_off);
+                }
+                reg_off += 1 << esz;
+            } while (reg_off & 63);
+        } while (reg_off <= reg_last);
+    }
+}
+
+static inline QEMU_ALWAYS_INLINE
+void sme_st1_mte(CPUARMState *env, void *za, uint64_t *vg, target_ulong addr,
+                 uint32_t desc, uintptr_t ra, int esz, bool vertical,
+                 sve_ldst1_host_fn *host_fn,
+                 sve_ldst1_tlb_fn *tlb_fn)
+{
+    uint32_t mtedesc = desc >> (SIMD_DATA_SHIFT + SVE_MTEDESC_SHIFT);
+    int bit55 = extract64(addr, 55, 1);
+
+    /* Remove mtedesc from the normal sve descriptor. */
+    desc = extract32(desc, 0, SIMD_DATA_SHIFT + SVE_MTEDESC_SHIFT);
+
+    /* Perform gross MTE suppression early. */
+    if (!tbi_check(desc, bit55) ||
+        tcma_check(desc, bit55, allocation_tag_from_addr(addr))) {
+        mtedesc = 0;
+    }
+
+    sme_st1(env, za, vg, addr, desc, ra, esz, mtedesc,
+            vertical, host_fn, tlb_fn);
+}
+
+#define DO_ST(L, END, ESZ)                                                 \
+void HELPER(sme_st1##L##END##_h)(CPUARMState *env, void *za, void *vg,     \
+                                 target_ulong addr, uint32_t desc)         \
+{                                                                          \
+    sme_st1(env, za, vg, addr, desc, GETPC(), ESZ, 0, false,               \
+            sve_st1##L##L##END##_host, sve_st1##L##L##END##_tlb);          \
+}                                                                          \
+void HELPER(sme_st1##L##END##_v)(CPUARMState *env, void *za, void *vg,     \
+                                 target_ulong addr, uint32_t desc)         \
+{                                                                          \
+    sme_st1(env, za, vg, addr, desc, GETPC(), ESZ, 0, true,                \
+            sme_st1##L##END##_v_host, sme_st1##L##END##_v_tlb);            \
+}                                                                          \
+void HELPER(sme_st1##L##END##_h_mte)(CPUARMState *env, void *za, void *vg, \
+                                     target_ulong addr, uint32_t desc)     \
+{                                                                          \
+    sme_st1_mte(env, za, vg, addr, desc, GETPC(), ESZ, false,              \
+                sve_st1##L##L##END##_host, sve_st1##L##L##END##_tlb);      \
+}                                                                          \
+void HELPER(sme_st1##L##END##_v_mte)(CPUARMState *env, void *za, void *vg, \
+                                     target_ulong addr, uint32_t desc)     \
+{                                                                          \
+    sme_st1_mte(env, za, vg, addr, desc, GETPC(), ESZ, true,               \
+                sme_st1##L##END##_v_host, sme_st1##L##END##_v_tlb);        \
+}
+
+DO_ST(b, , MO_8)
+DO_ST(h, _be, MO_16)
+DO_ST(h, _le, MO_16)
+DO_ST(s, _be, MO_32)
+DO_ST(s, _le, MO_32)
+DO_ST(d, _be, MO_64)
+DO_ST(d, _le, MO_64)
+DO_ST(q, _be, MO_128)
+DO_ST(q, _le, MO_128)
+
+#undef DO_ST
diff --git a/target/arm/translate-sme.c b/target/arm/translate-sme.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/translate-sme.c
+++ b/target/arm/translate-sme.c
@@ -XXX,XX +XXX,XX @@ static bool trans_MOVA(DisasContext *s, arg_MOVA *a)
 
     return true;
 }
+
+static bool trans_LDST1(DisasContext *s, arg_LDST1 *a)
+{
+    typedef void GenLdSt1(TCGv_env, TCGv_ptr, TCGv_ptr, TCGv, TCGv_i32);
+
+    /*
+     * Indexed by [esz][be][v][mte][st], which is (except for load/store)
+     * also the order in which the elements appear in the function names,
+     * and so how we must concatenate the pieces.
+     */
+
+#define FN_LS(F)     { gen_helper_sme_ld1##F, gen_helper_sme_st1##F }
+#define FN_MTE(F)    { FN_LS(F), FN_LS(F##_mte) }
+#define FN_HV(F)     { FN_MTE(F##_h), FN_MTE(F##_v) }
+#define FN_END(L, B) { FN_HV(L), FN_HV(B) }
+
+    static GenLdSt1 * const fns[5][2][2][2][2] = {
+        FN_END(b, b),
+        FN_END(h_le, h_be),
+        FN_END(s_le, s_be),
+        FN_END(d_le, d_be),
+        FN_END(q_le, q_be),
+    };
+
+#undef FN_LS
+#undef FN_MTE
+#undef FN_HV
+#undef FN_END
+
+    TCGv_ptr t_za, t_pg;
+    TCGv_i64 addr;
+    int svl, desc = 0;
+    bool be = s->be_data == MO_BE;
+    bool mte = s->mte_active[0];
+
+    if (!dc_isar_feature(aa64_sme, s)) {
+        return false;
+    }
+    if (!sme_smza_enabled_check(s)) {
+        return true;
+    }
+
+    t_za = get_tile_rowcol(s, a->esz, a->rs, a->za_imm, a->v);
+    t_pg = pred_full_reg_ptr(s, a->pg);
+    addr = tcg_temp_new_i64();
+
+    tcg_gen_shli_i64(addr, cpu_reg(s, a->rm), a->esz);
+    tcg_gen_add_i64(addr, addr, cpu_reg_sp(s, a->rn));
+
+    if (mte) {
+        desc = FIELD_DP32(desc, MTEDESC, MIDX, get_mem_index(s));
+        desc = FIELD_DP32(desc, MTEDESC, TBI, s->tbid);
+        desc = FIELD_DP32(desc, MTEDESC, TCMA, s->tcma);
+        desc = FIELD_DP32(desc, MTEDESC, WRITE, a->st);
+        desc = FIELD_DP32(desc, MTEDESC, SIZEM1, (1 << a->esz) - 1);
+        desc <<= SVE_MTEDESC_SHIFT;
+    } else {
+        addr = clean_data_tbi(s, addr);
+    }
+    svl = streaming_vec_reg_size(s);
+    desc = simd_desc(svl, svl, desc);
+
+    fns[a->esz][be][a->v][mte][a->st](cpu_env, t_za, t_pg, addr,
+                                      tcg_constant_i32(desc));
+
+    tcg_temp_free_ptr(t_za);
+    tcg_temp_free_ptr(t_pg);
+    tcg_temp_free_i64(addr);
+    return true;
+}
-- 
2.25.1

From: Richard Henderson <richard.henderson@linaro.org>

Add a TCGv_ptr base argument, which will be cpu_env for SVE.
We will reuse this for SME save and restore array insns.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220708151540.18136-22-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/translate-a64.h |  3 +++
 target/arm/translate-sve.c | 48 ++++++++++++++++++++++++++++----------
 2 files changed, 39 insertions(+), 12 deletions(-)

diff --git a/target/arm/translate-a64.h b/target/arm/translate-a64.h
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/translate-a64.h
+++ b/target/arm/translate-a64.h
@@ -XXX,XX +XXX,XX @@ void gen_gvec_xar(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs,
                   uint32_t rm_ofs, int64_t shift,
                   uint32_t opr_sz, uint32_t max_sz);
 
+void gen_sve_ldr(DisasContext *s, TCGv_ptr, int vofs, int len, int rn, int imm);
+void gen_sve_str(DisasContext *s, TCGv_ptr, int vofs, int len, int rn, int imm);
+
 #endif /* TARGET_ARM_TRANSLATE_A64_H */
diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/translate-sve.c
+++ b/target/arm/translate-sve.c
@@ -XXX,XX +XXX,XX @@ TRANS_FEAT(UCVTF_dd, aa64_sve, gen_gvec_fpst_arg_zpz,
  * The load should begin at the address Rn + IMM.
  */
 
-static void do_ldr(DisasContext *s, uint32_t vofs, int len, int rn, int imm)
+void gen_sve_ldr(DisasContext *s, TCGv_ptr base, int vofs,
+                 int len, int rn, int imm)
 {
     int len_align = QEMU_ALIGN_DOWN(len, 8);
     int len_remain = len % 8;
@@ -XXX,XX +XXX,XX @@ static void do_ldr(DisasContext *s, uint32_t vofs, int len, int rn, int imm)
         t0 = tcg_temp_new_i64();
         for (i = 0; i < len_align; i += 8) {
             tcg_gen_qemu_ld_i64(t0, clean_addr, midx, MO_LEUQ);
-            tcg_gen_st_i64(t0, cpu_env, vofs + i);
+            tcg_gen_st_i64(t0, base, vofs + i);
             tcg_gen_addi_i64(clean_addr, clean_addr, 8);
         }
         tcg_temp_free_i64(t0);
@@ -XXX,XX +XXX,XX @@ static void do_ldr(DisasContext *s, uint32_t vofs, int len, int rn, int imm)
         clean_addr = new_tmp_a64_local(s);
         tcg_gen_mov_i64(clean_addr, t0);
 
+        if (base != cpu_env) {
+            TCGv_ptr b = tcg_temp_local_new_ptr();
+            tcg_gen_mov_ptr(b, base);
+            base = b;
+        }
+
         gen_set_label(loop);
 
         t0 = tcg_temp_new_i64();
@@ -XXX,XX +XXX,XX @@ static void do_ldr(DisasContext *s, uint32_t vofs, int len, int rn, int imm)
         tcg_gen_addi_i64(clean_addr, clean_addr, 8);
 
         tp = tcg_temp_new_ptr();
-        tcg_gen_add_ptr(tp, cpu_env, i);
+        tcg_gen_add_ptr(tp, base, i);
         tcg_gen_addi_ptr(i, i, 8);
         tcg_gen_st_i64(t0, tp, vofs);
         tcg_temp_free_ptr(tp);
@@ -XXX,XX +XXX,XX @@ static void do_ldr(DisasContext *s, uint32_t vofs, int len, int rn, int imm)
 
         tcg_gen_brcondi_ptr(TCG_COND_LTU, i, len_align, loop);
         tcg_temp_free_ptr(i);
+
+        if (base != cpu_env) {
+            tcg_temp_free_ptr(base);
+            assert(len_remain == 0);
+        }
     }
 
     /*
@@ -XXX,XX +XXX,XX @@ static void do_ldr(DisasContext *s, uint32_t vofs, int len, int rn, int imm)
         default:
             g_assert_not_reached();
         }
-        tcg_gen_st_i64(t0, cpu_env, vofs + len_align);
+        tcg_gen_st_i64(t0, base, vofs + len_align);
         tcg_temp_free_i64(t0);
     }
 }
 
 /* Similarly for stores.  */
-static void do_str(DisasContext *s, uint32_t vofs, int len, int rn, int imm)
+void gen_sve_str(DisasContext *s, TCGv_ptr base, int vofs,
+                 int len, int rn, int imm)
 {
     int len_align = QEMU_ALIGN_DOWN(len, 8);
     int len_remain = len % 8;
@@ -XXX,XX +XXX,XX @@ static void do_str(DisasContext *s, uint32_t vofs, int len, int rn, int imm)
 
         t0 = tcg_temp_new_i64();
         for (i = 0; i < len_align; i += 8) {
-            tcg_gen_ld_i64(t0, cpu_env, vofs + i);
+            tcg_gen_ld_i64(t0, base, vofs + i);
             tcg_gen_qemu_st_i64(t0, clean_addr, midx, MO_LEUQ);
             tcg_gen_addi_i64(clean_addr, clean_addr, 8);
         }
@@ -XXX,XX +XXX,XX @@ static void do_str(DisasContext *s, uint32_t vofs, int len, int rn, int imm)
         clean_addr = new_tmp_a64_local(s);
         tcg_gen_mov_i64(clean_addr, t0);
 
+        if (base != cpu_env) {
+            TCGv_ptr b = tcg_temp_local_new_ptr();
+            tcg_gen_mov_ptr(b, base);
+            base = b;
+        }
+
         gen_set_label(loop);
 
         t0 = tcg_temp_new_i64();
         tp = tcg_temp_new_ptr();
-        tcg_gen_add_ptr(tp, cpu_env, i);
+        tcg_gen_add_ptr(tp, base, i);
         tcg_gen_ld_i64(t0, tp, vofs);
         tcg_gen_addi_ptr(i, i, 8);
         tcg_temp_free_ptr(tp);
@@ -XXX,XX +XXX,XX @@ static void do_str(DisasContext *s, uint32_t vofs, int len, int rn, int imm)
 
         tcg_gen_brcondi_ptr(TCG_COND_LTU, i, len_align, loop);
         tcg_temp_free_ptr(i);
+
+        if (base != cpu_env) {
+            tcg_temp_free_ptr(base);
+            assert(len_remain == 0);
+        }
     }
 
     /* Predicate register stores can be any multiple of 2.  */
     if (len_remain) {
         t0 = tcg_temp_new_i64();
-        tcg_gen_ld_i64(t0, cpu_env, vofs + len_align);
+        tcg_gen_ld_i64(t0, base, vofs + len_align);
 
         switch (len_remain) {
         case 2:
@@ -XXX,XX +XXX,XX @@ static bool trans_LDR_zri(DisasContext *s, arg_rri *a)
     if (sve_access_check(s)) {
         int size = vec_full_reg_size(s);
         int off = vec_full_reg_offset(s, a->rd);
-        do_ldr(s, off, size, a->rn, a->imm * size);
+        gen_sve_ldr(s, cpu_env, off, size, a->rn, a->imm * size);
     }
     return true;
 }
@@ -XXX,XX +XXX,XX @@ static bool trans_LDR_pri(DisasContext *s, arg_rri *a)
     if (sve_access_check(s)) {
         int size = pred_full_reg_size(s);
         int off = pred_full_reg_offset(s, a->rd);
-        do_ldr(s, off, size, a->rn, a->imm * size);
+        gen_sve_ldr(s, cpu_env, off, size, a->rn, a->imm * size);
     }
     return true;
 }
@@ -XXX,XX +XXX,XX @@ static bool trans_STR_zri(DisasContext *s, arg_rri *a)
     if (sve_access_check(s)) {
         int size = vec_full_reg_size(s);
         int off = vec_full_reg_offset(s, a->rd);
-        do_str(s, off, size, a->rn, a->imm * size);
+        gen_sve_str(s, cpu_env, off, size, a->rn, a->imm * size);
     }
     return true;
 }
@@ -XXX,XX +XXX,XX @@ static bool trans_STR_pri(DisasContext *s, arg_rri *a)
     if (sve_access_check(s)) {
         int size = pred_full_reg_size(s);
         int off = pred_full_reg_offset(s, a->rd);
-        do_str(s, off, size, a->rn, a->imm * size);
+        gen_sve_str(s, cpu_env, off, size, a->rn, a->imm * size);
     }
     return true;
 }
-- 
2.25.1

From: Richard Henderson <richard.henderson@linaro.org>

We can reuse the SVE functions for LDR and STR, passing in the
base of the ZA vector and a zero offset.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220708151540.18136-23-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/sme.decode      |  7 +++++++
 target/arm/translate-sme.c | 24 ++++++++++++++++++++++++
 2 files changed, 31 insertions(+)

diff --git a/target/arm/sme.decode b/target/arm/sme.decode
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/sme.decode
+++ b/target/arm/sme.decode
@@ -XXX,XX +XXX,XX @@ LDST1           1110000 0 esz:2 st:1 rm:5 v:1 .. pg:3 rn:5 0 za_imm:4  \
                 &ldst rs=%mova_rs
 LDST1           1110000 111     st:1 rm:5 v:1 .. pg:3 rn:5 0 za_imm:4  \
                 &ldst esz=4 rs=%mova_rs
+
+&ldstr          rv rn imm
+@ldstr          ....... ... . ...... .. ... rn:5 . imm:4 \
+                &ldstr rv=%mova_rs
+
+LDR             1110000 100 0 000000 .. 000 ..... 0 ....        @ldstr
+STR             1110000 100 1 000000 .. 000 ..... 0 ....        @ldstr
diff --git a/target/arm/translate-sme.c b/target/arm/translate-sme.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/translate-sme.c
+++ b/target/arm/translate-sme.c
@@ -XXX,XX +XXX,XX @@ static bool trans_LDST1(DisasContext *s, arg_LDST1 *a)
     tcg_temp_free_i64(addr);
     return true;
 }
+
+typedef void GenLdStR(DisasContext *, TCGv_ptr, int, int, int, int);
+
+static bool do_ldst_r(DisasContext *s, arg_ldstr *a, GenLdStR *fn)
+{
+    int svl = streaming_vec_reg_size(s);
+    int imm = a->imm;
+    TCGv_ptr base;
+
+    if (!sme_za_enabled_check(s)) {
+        return true;
+    }
+
+    /* ZA[n] equates to ZA0H.B[n]. */
+    base = get_tile_rowcol(s, MO_8, a->rv, imm, false);
+
+    fn(s, base, 0, svl, a->rn, imm * svl);
+
+    tcg_temp_free_ptr(base);
+    return true;
+}
+
+TRANS_FEAT(LDR, aa64_sme, do_ldst_r, a, gen_sve_ldr)
+TRANS_FEAT(STR, aa64_sme, do_ldst_r, a, gen_sve_str)
-- 
2.25.1

From: Richard Henderson <richard.henderson@linaro.org>

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220708151540.18136-24-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/helper-sme.h    |  5 +++
 target/arm/sme.decode      | 11 +++++
 target/arm/sme_helper.c    | 90 ++++++++++++++++++++++++++++++++++++++
 target/arm/translate-sme.c | 31 +++++++++++++
 4 files changed, 137 insertions(+)

From: Richard Henderson <richard.henderson@linaro.org>

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220708151540.18136-25-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/helper-sme.h    |  5 +++
 target/arm/sme.decode      |  9 +++++
 target/arm/sme_helper.c    | 69 ++++++++++++++++++++++++++++++++++++++
 target/arm/translate-sme.c | 32 ++++++++++++++++++
 4 files changed, 115 insertions(+)

From: Richard Henderson <richard.henderson@linaro.org>

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220708151540.18136-26-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/helper-sme.h    |  2 ++
 target/arm/sme.decode      |  2 ++
 target/arm/sme_helper.c    | 56 ++++++++++++++++++++++++++++++++++++++
 target/arm/translate-sme.c | 30 ++++++++++++++++++++
 4 files changed, 90 insertions(+)

From: Richard Henderson <richard.henderson@linaro.org>

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220708151540.18136-27-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/helper-sme.h    |  2 ++
 target/arm/sme.decode      |  1 +
 target/arm/sme_helper.c    | 74 ++++++++++++++++++++++++++++++++++++++
 target/arm/translate-sme.c |  1 +
 4 files changed, 78 insertions(+)

From: Richard Henderson <richard.henderson@linaro.org>

This is SMOPA, SUMOPA, USMOPA_s, UMOPA, for both Int8 and Int16.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220708151540.18136-28-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/helper-sme.h    | 16 ++++++++
 target/arm/sme.decode      | 10 +++++
 target/arm/sme_helper.c    | 82 ++++++++++++++++++++++++++++++++++++++
 target/arm/translate-sme.c | 10 +++++
 4 files changed, 118 insertions(+)

From: Richard Henderson <richard.henderson@linaro.org>

This is an SVE instruction that operates using the SVE vector
length but that it is present only if SME is implemented.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220708151540.18136-29-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/sve.decode      | 20 +++++++++++++
 target/arm/translate-sve.c | 57 ++++++++++++++++++++++++++++++++++++++
 2 files changed, 77 insertions(+)

diff --git a/target/arm/sve.decode b/target/arm/sve.decode
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/sve.decode
+++ b/target/arm/sve.decode
@@ -XXX,XX +XXX,XX @@ BFMLALT_zzxw    01100100 11 1 ..... 0100.1 ..... .....     @rrxr_3a esz=2
 
 ### SVE2 floating-point bfloat16 dot-product (indexed)
 BFDOT_zzxz      01100100 01 1 ..... 010000 ..... .....     @rrxr_2 esz=2
+
+### SVE broadcast predicate element
+
+&psel           esz pd pn pm rv imm
+%psel_rv        16:2 !function=plus_12
+%psel_imm_b     22:2 19:2
+%psel_imm_h     22:2 20:1
+%psel_imm_s     22:2
+%psel_imm_d     23:1
+@psel           ........ .. . ... .. .. pn:4 . pm:4 . pd:4  \
+                &psel rv=%psel_rv
+
+PSEL            00100101 .. 1 ..1 .. 01 .... 0 .... 0 ....  \
+                @psel esz=0 imm=%psel_imm_b
+PSEL            00100101 .. 1 .10 .. 01 .... 0 .... 0 ....  \
+                @psel esz=1 imm=%psel_imm_h
+PSEL            00100101 .. 1 100 .. 01 .... 0 .... 0 ....  \
+                @psel esz=2 imm=%psel_imm_s
+PSEL            00100101 .1 1 000 .. 01 .... 0 .... 0 ....  \
+                @psel esz=3 imm=%psel_imm_d
diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/translate-sve.c
+++ b/target/arm/translate-sve.c
@@ -XXX,XX +XXX,XX @@ static bool do_BFMLAL_zzxw(DisasContext *s, arg_rrxr_esz *a, bool sel)
 
 TRANS_FEAT(BFMLALB_zzxw, aa64_sve_bf16, do_BFMLAL_zzxw, a, false)
 TRANS_FEAT(BFMLALT_zzxw, aa64_sve_bf16, do_BFMLAL_zzxw, a, true)
+
+static bool trans_PSEL(DisasContext *s, arg_psel *a)
+{
+    int vl = vec_full_reg_size(s);
+    int pl = pred_gvec_reg_size(s);
+    int elements = vl >> a->esz;
+    TCGv_i64 tmp, didx, dbit;
+    TCGv_ptr ptr;
+
+    if (!dc_isar_feature(aa64_sme, s)) {
+        return false;
+    }
+    if (!sve_access_check(s)) {
+        return true;
+    }
+
+    tmp = tcg_temp_new_i64();
+    dbit = tcg_temp_new_i64();
+    didx = tcg_temp_new_i64();
+    ptr = tcg_temp_new_ptr();
+
+    /* Compute the predicate element. */
+    tcg_gen_addi_i64(tmp, cpu_reg(s, a->rv), a->imm);
+    if (is_power_of_2(elements)) {
+        tcg_gen_andi_i64(tmp, tmp, elements - 1);
+    } else {
+        tcg_gen_remu_i64(tmp, tmp, tcg_constant_i64(elements));
+    }
+
+    /* Extract the predicate byte and bit indices. */
+    tcg_gen_shli_i64(tmp, tmp, a->esz);
+    tcg_gen_andi_i64(dbit, tmp, 7);
+    tcg_gen_shri_i64(didx, tmp, 3);
+    if (HOST_BIG_ENDIAN) {
+        tcg_gen_xori_i64(didx, didx, 7);
+    }
+
+    /* Load the predicate word. */
+    tcg_gen_trunc_i64_ptr(ptr, didx);
+    tcg_gen_add_ptr(ptr, ptr, cpu_env);
+    tcg_gen_ld8u_i64(tmp, ptr, pred_full_reg_offset(s, a->pm));
+
+    /* Extract the predicate bit and replicate to MO_64. */
+    tcg_gen_shr_i64(tmp, tmp, dbit);
+    tcg_gen_andi_i64(tmp, tmp, 1);
+    tcg_gen_neg_i64(tmp, tmp);
+
+    /* Apply to either copy the source, or write zeros. */
+    tcg_gen_gvec_ands(MO_64, pred_full_reg_offset(s, a->pd),
+                      pred_full_reg_offset(s, a->pn), tmp, pl, pl);
+
+    tcg_temp_free_i64(tmp);
+    tcg_temp_free_i64(dbit);
+    tcg_temp_free_i64(didx);
+    tcg_temp_free_ptr(ptr);
+    return true;
+}
-- 
2.25.1

From: Richard Henderson <richard.henderson@linaro.org>

This is an SVE instruction that operates using the SVE vector
length but that it is present only if SME is implemented.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220708151540.18136-30-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/helper-sve.h    |  2 ++
 target/arm/sve.decode      |  1 +
 target/arm/sve_helper.c    | 16 ++++++++++++++++
 target/arm/translate-sve.c |  2 ++
 4 files changed, 21 insertions(+)

diff --git a/target/arm/helper-sve.h b/target/arm/helper-sve.h
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/helper-sve.h
+++ b/target/arm/helper-sve.h
@@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_4(sve_revh_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
 
 DEF_HELPER_FLAGS_4(sve_revw_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
 
+DEF_HELPER_FLAGS_4(sme_revd_q, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
+
 DEF_HELPER_FLAGS_4(sve_rbit_b, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
 DEF_HELPER_FLAGS_4(sve_rbit_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
 DEF_HELPER_FLAGS_4(sve_rbit_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
diff --git a/target/arm/sve.decode b/target/arm/sve.decode
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/sve.decode
+++ b/target/arm/sve.decode
@@ -XXX,XX +XXX,XX @@ REVB            00000101 .. 1001 00 100 ... ..... .....         @rd_pg_rn
 REVH            00000101 .. 1001 01 100 ... ..... .....         @rd_pg_rn
 REVW            00000101 .. 1001 10 100 ... ..... .....         @rd_pg_rn
 RBIT            00000101 .. 1001 11 100 ... ..... .....         @rd_pg_rn
+REVD            00000101 00 1011 10 100 ... ..... .....         @rd_pg_rn_e0
 
 # SVE vector splice (predicated, destructive)
 SPLICE          00000101 .. 101 100 100 ... ..... .....         @rdn_pg_rm
diff --git a/target/arm/sve_helper.c b/target/arm/sve_helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/sve_helper.c
+++ b/target/arm/sve_helper.c
@@ -XXX,XX +XXX,XX @@ DO_ZPZ_D(sve_revh_d, uint64_t, hswap64)
 
 DO_ZPZ_D(sve_revw_d, uint64_t, wswap64)
 
+void HELPER(sme_revd_q)(void *vd, void *vn, void *vg, uint32_t desc)
+{
+    intptr_t i, opr_sz = simd_oprsz(desc) / 8;
+    uint64_t *d = vd, *n = vn;
+    uint8_t *pg = vg;
+
+    for (i = 0; i < opr_sz; i += 2) {
+        if (pg[H1(i)] & 1) {
+            uint64_t n0 = n[i + 0];
+            uint64_t n1 = n[i + 1];
+            d[i + 0] = n1;
+            d[i + 1] = n0;
+        }
+    }
+}
+
 DO_ZPZ(sve_rbit_b, uint8_t, H1, revbit8)
 DO_ZPZ(sve_rbit_h, uint16_t, H1_2, revbit16)
 DO_ZPZ(sve_rbit_s, uint32_t, H1_4, revbit32)
diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/translate-sve.c
+++ b/target/arm/translate-sve.c
@@ -XXX,XX +XXX,XX @@ TRANS_FEAT(REVH, aa64_sve, gen_gvec_ool_arg_zpz, revh_fns[a->esz], a, 0)
 TRANS_FEAT(REVW, aa64_sve, gen_gvec_ool_arg_zpz,
            a->esz == 3 ? gen_helper_sve_revw_d : NULL, a, 0)
 
+TRANS_FEAT(REVD, aa64_sme, gen_gvec_ool_arg_zpz, gen_helper_sme_revd_q, a, 0)
+
 TRANS_FEAT(SPLICE, aa64_sve, gen_gvec_ool_arg_zpzz,
            gen_helper_sve_splice, a, a->esz)
 
-- 
2.25.1

From: Richard Henderson <richard.henderson@linaro.org>

This is an SVE instruction that operates using the SVE vector
length but that it is present only if SME is implemented.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220708151540.18136-31-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/helper.h        |  18 +++++++
 target/arm/sve.decode      |   5 ++
 target/arm/translate-sve.c | 102 +++++++++++++++++++++++++++++++++++++
 target/arm/vec_helper.c    |  24 +++++++++
 4 files changed, 149 insertions(+)

diff --git a/target/arm/helper.h b/target/arm/helper.h
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/helper.h
+++ b/target/arm/helper.h
@@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_6(gvec_bfmlal, TCG_CALL_NO_RWG,
 DEF_HELPER_FLAGS_6(gvec_bfmlal_idx, TCG_CALL_NO_RWG,
                    void, ptr, ptr, ptr, ptr, ptr, i32)
 
+DEF_HELPER_FLAGS_5(gvec_sclamp_b, TCG_CALL_NO_RWG,
+                   void, ptr, ptr, ptr, ptr, i32)
+DEF_HELPER_FLAGS_5(gvec_sclamp_h, TCG_CALL_NO_RWG,
+                   void, ptr, ptr, ptr, ptr, i32)
+DEF_HELPER_FLAGS_5(gvec_sclamp_s, TCG_CALL_NO_RWG,
+                   void, ptr, ptr, ptr, ptr, i32)
+DEF_HELPER_FLAGS_5(gvec_sclamp_d, TCG_CALL_NO_RWG,
+                   void, ptr, ptr, ptr, ptr, i32)
+
+DEF_HELPER_FLAGS_5(gvec_uclamp_b, TCG_CALL_NO_RWG,
+                   void, ptr, ptr, ptr, ptr, i32)
+DEF_HELPER_FLAGS_5(gvec_uclamp_h, TCG_CALL_NO_RWG,
+                   void, ptr, ptr, ptr, ptr, i32)
+DEF_HELPER_FLAGS_5(gvec_uclamp_s, TCG_CALL_NO_RWG,
+                   void, ptr, ptr, ptr, ptr, i32)
+DEF_HELPER_FLAGS_5(gvec_uclamp_d, TCG_CALL_NO_RWG,
+                   void, ptr, ptr, ptr, ptr, i32)
+
 #ifdef TARGET_AARCH64
 #include "helper-a64.h"
 #include "helper-sve.h"
diff --git a/target/arm/sve.decode b/target/arm/sve.decode
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/sve.decode
+++ b/target/arm/sve.decode
@@ -XXX,XX +XXX,XX @@ PSEL            00100101 .. 1 100 .. 01 .... 0 .... 0 ....  \
                 @psel esz=2 imm=%psel_imm_s
 PSEL            00100101 .1 1 000 .. 01 .... 0 .... 0 ....  \
                 @psel esz=3 imm=%psel_imm_d
+
+### SVE clamp
+
+SCLAMP          01000100 .. 0 ..... 110000 ..... .....          @rda_rn_rm
+UCLAMP          01000100 .. 0 ..... 110001 ..... .....          @rda_rn_rm
diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/translate-sve.c
+++ b/target/arm/translate-sve.c
@@ -XXX,XX +XXX,XX @@ static bool trans_PSEL(DisasContext *s, arg_psel *a)
     tcg_temp_free_ptr(ptr);
     return true;
 }
+
+static void gen_sclamp_i32(TCGv_i32 d, TCGv_i32 n, TCGv_i32 m, TCGv_i32 a)
+{
+    tcg_gen_smax_i32(d, a, n);
+    tcg_gen_smin_i32(d, d, m);
+}
+
+static void gen_sclamp_i64(TCGv_i64 d, TCGv_i64 n, TCGv_i64 m, TCGv_i64 a)
+{
+    tcg_gen_smax_i64(d, a, n);
+    tcg_gen_smin_i64(d, d, m);
+}
+
+static void gen_sclamp_vec(unsigned vece, TCGv_vec d, TCGv_vec n,
+                           TCGv_vec m, TCGv_vec a)
+{
+    tcg_gen_smax_vec(vece, d, a, n);
+    tcg_gen_smin_vec(vece, d, d, m);
+}
+
+static void gen_sclamp(unsigned vece, uint32_t d, uint32_t n, uint32_t m,
+                       uint32_t a, uint32_t oprsz, uint32_t maxsz)
+{
+    static const TCGOpcode vecop[] = {
+        INDEX_op_smin_vec, INDEX_op_smax_vec, 0
+    };
+    static const GVecGen4 ops[4] = {
+        { .fniv = gen_sclamp_vec,
+          .fno  = gen_helper_gvec_sclamp_b,
+          .opt_opc = vecop,
+          .vece = MO_8 },
+        { .fniv = gen_sclamp_vec,
+          .fno  = gen_helper_gvec_sclamp_h,
+          .opt_opc = vecop,
+          .vece = MO_16 },
+        { .fni4 = gen_sclamp_i32,
+          .fniv = gen_sclamp_vec,
+          .fno  = gen_helper_gvec_sclamp_s,
+          .opt_opc = vecop,
+          .vece = MO_32 },
+        { .fni8 = gen_sclamp_i64,
+          .fniv = gen_sclamp_vec,
+          .fno  = gen_helper_gvec_sclamp_d,
+          .opt_opc = vecop,
+          .vece = MO_64,
+          .prefer_i64 = TCG_TARGET_REG_BITS == 64 }
+    };
+    tcg_gen_gvec_4(d, n, m, a, oprsz, maxsz, &ops[vece]);
+}
+
+TRANS_FEAT(SCLAMP, aa64_sme, gen_gvec_fn_arg_zzzz, gen_sclamp, a)
+
+static void gen_uclamp_i32(TCGv_i32 d, TCGv_i32 n, TCGv_i32 m, TCGv_i32 a)
+{
+    tcg_gen_umax_i32(d, a, n);
+    tcg_gen_umin_i32(d, d, m);
+}
+
+static void gen_uclamp_i64(TCGv_i64 d, TCGv_i64 n, TCGv_i64 m, TCGv_i64 a)
+{
+    tcg_gen_umax_i64(d, a, n);
+    tcg_gen_umin_i64(d, d, m);
+}
+
+static void gen_uclamp_vec(unsigned vece, TCGv_vec d, TCGv_vec n,
+                           TCGv_vec m, TCGv_vec a)
+{
+    tcg_gen_umax_vec(vece, d, a, n);
+    tcg_gen_umin_vec(vece, d, d, m);
+}
+
+static void gen_uclamp(unsigned vece, uint32_t d, uint32_t n, uint32_t m,
+                       uint32_t a, uint32_t oprsz, uint32_t maxsz)
+{
+    static const TCGOpcode vecop[] = {
+        INDEX_op_umin_vec, INDEX_op_umax_vec, 0
+    };
+    static const GVecGen4 ops[4] = {
+        { .fniv = gen_uclamp_vec,
+          .fno  = gen_helper_gvec_uclamp_b,
+          .opt_opc = vecop,
+          .vece = MO_8 },
+        { .fniv = gen_uclamp_vec,
+          .fno  = gen_helper_gvec_uclamp_h,
+          .opt_opc = vecop,
+          .vece = MO_16 },
+        { .fni4 = gen_uclamp_i32,
+          .fniv = gen_uclamp_vec,
+          .fno  = gen_helper_gvec_uclamp_s,
+          .opt_opc = vecop,
+          .vece = MO_32 },
+        { .fni8 = gen_uclamp_i64,
+          .fniv = gen_uclamp_vec,
+          .fno  = gen_helper_gvec_uclamp_d,
+          .opt_opc = vecop,
+          .vece = MO_64,
+          .prefer_i64 = TCG_TARGET_REG_BITS == 64 }
+    };
+    tcg_gen_gvec_4(d, n, m, a, oprsz, maxsz, &ops[vece]);
+}
+
+TRANS_FEAT(UCLAMP, aa64_sme, gen_gvec_fn_arg_zzzz, gen_uclamp, a)
diff --git a/target/arm/vec_helper.c b/target/arm/vec_helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/vec_helper.c
+++ b/target/arm/vec_helper.c
@@ -XXX,XX +XXX,XX @@ void HELPER(gvec_bfmlal_idx)(void *vd, void *vn, void *vm,
     }
     clear_tail(d, opr_sz, simd_maxsz(desc));
 }
+
+#define DO_CLAMP(NAME, TYPE) \
+void HELPER(NAME)(void *d, void *n, void *m, void *a, uint32_t desc)    \
+{                                                                       \
+    intptr_t i, opr_sz = simd_oprsz(desc);                              \
+    for (i = 0; i < opr_sz; i += sizeof(TYPE)) {                        \
+        TYPE aa = *(TYPE *)(a + i);                                     \
+        TYPE nn = *(TYPE *)(n + i);                                     \
+        TYPE mm = *(TYPE *)(m + i);                                     \
+        TYPE dd = MIN(MAX(aa, nn), mm);                                 \
+        *(TYPE *)(d + i) = dd;                                          \
+    }                                                                   \
+    clear_tail(d, opr_sz, simd_maxsz(desc));                            \
+}
+
+DO_CLAMP(gvec_sclamp_b, int8_t)
+DO_CLAMP(gvec_sclamp_h, int16_t)
+DO_CLAMP(gvec_sclamp_s, int32_t)
+DO_CLAMP(gvec_sclamp_d, int64_t)
+
+DO_CLAMP(gvec_uclamp_b, uint8_t)
+DO_CLAMP(gvec_uclamp_h, uint16_t)
+DO_CLAMP(gvec_uclamp_s, uint32_t)
+DO_CLAMP(gvec_uclamp_d, uint64_t)
-- 
2.25.1

From: Richard Henderson <richard.henderson@linaro.org>

We can handle both exception entry and exception return by
hooking into aarch64_sve_change_el.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220708151540.18136-32-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/helper.c | 15 +++++++++++++--
 1 file changed, 13 insertions(+), 2 deletions(-)

diff --git a/target/arm/helper.c b/target/arm/helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -XXX,XX +XXX,XX @@ void aarch64_sve_change_el(CPUARMState *env, int old_el,
         return;
     }
 
+    old_a64 = old_el ? arm_el_is_aa64(env, old_el) : el0_a64;
+    new_a64 = new_el ? arm_el_is_aa64(env, new_el) : el0_a64;
+
+    /*
+     * Both AArch64.TakeException and AArch64.ExceptionReturn
+     * invoke ResetSVEState when taking an exception from, or
+     * returning to, AArch32 state when PSTATE.SM is enabled.
+     */
+    if (old_a64 != new_a64 && FIELD_EX64(env->svcr, SVCR, SM)) {
+        arm_reset_sve_state(env);
+        return;
+    }
+
     /*
      * DDI0584A.d sec 3.2: "If SVE instructions are disabled or trapped
      * at ELx, or not available because the EL is in AArch32 state, then
@@ -XXX,XX +XXX,XX @@ void aarch64_sve_change_el(CPUARMState *env, int old_el,
      * we already have the correct register contents when encountering the
      * vq0->vq0 transition between EL0->EL1.
      */
-    old_a64 = old_el ? arm_el_is_aa64(env, old_el) : el0_a64;
     old_len = (old_a64 && !sve_exception_el(env, old_el)
                ? sve_vqm1_for_el(env, old_el) : 0);
-    new_a64 = new_el ? arm_el_is_aa64(env, new_el) : el0_a64;
     new_len = (new_a64 && !sve_exception_el(env, new_el)
                ? sve_vqm1_for_el(env, new_el) : 0);
 
-- 
2.25.1

From: Richard Henderson <richard.henderson@linaro.org>

Note that SME remains effectively disabled for user-only,
because we do not yet set CPACR_EL1.SMEN.  This needs to
wait until the kernel ABI is implemented.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220708151540.18136-33-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 docs/system/arm/emulation.rst |  4 ++++
 target/arm/cpu64.c            | 11 +++++++++++
 2 files changed, 15 insertions(+)

diff --git a/docs/system/arm/emulation.rst b/docs/system/arm/emulation.rst
index XXXXXXX..XXXXXXX 100644
--- a/docs/system/arm/emulation.rst
+++ b/docs/system/arm/emulation.rst
@@ -XXX,XX +XXX,XX @@ the following architecture extensions:
 - FEAT_SHA512 (Advanced SIMD SHA512 instructions)
 - FEAT_SM3 (Advanced SIMD SM3 instructions)
 - FEAT_SM4 (Advanced SIMD SM4 instructions)
+- FEAT_SME (Scalable Matrix Extension)
+- FEAT_SME_FA64 (Full A64 instruction set in Streaming SVE mode)
+- FEAT_SME_F64F64 (Double-precision floating-point outer product instructions)
+- FEAT_SME_I16I64 (16-bit to 64-bit integer widening outer product instructions)
 - FEAT_SPECRES (Speculation restriction instructions)
 - FEAT_SSBS (Speculative Store Bypass Safe)
 - FEAT_TLBIOS (TLB invalidate instructions in Outer Shareable domain)
diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/cpu64.c
+++ b/target/arm/cpu64.c
@@ -XXX,XX +XXX,XX @@ static void aarch64_max_initfn(Object *obj)
      */
     t = FIELD_DP64(t, ID_AA64PFR1, MTE, 3);       /* FEAT_MTE3 */
     t = FIELD_DP64(t, ID_AA64PFR1, RAS_FRAC, 0);  /* FEAT_RASv1p1 + FEAT_DoubleFault */
+    t = FIELD_DP64(t, ID_AA64PFR1, SME, 1);       /* FEAT_SME */
     t = FIELD_DP64(t, ID_AA64PFR1, CSV2_FRAC, 0); /* FEAT_CSV2_2 */
     cpu->isar.id_aa64pfr1 = t;
 
@@ -XXX,XX +XXX,XX @@ static void aarch64_max_initfn(Object *obj)
     t = FIELD_DP64(t, ID_AA64DFR0, PMUVER, 5);    /* FEAT_PMUv3p4 */
     cpu->isar.id_aa64dfr0 = t;
 
+    t = cpu->isar.id_aa64smfr0;
+    t = FIELD_DP64(t, ID_AA64SMFR0, F32F32, 1);   /* FEAT_SME */
+    t = FIELD_DP64(t, ID_AA64SMFR0, B16F32, 1);   /* FEAT_SME */
+    t = FIELD_DP64(t, ID_AA64SMFR0, F16F32, 1);   /* FEAT_SME */
+    t = FIELD_DP64(t, ID_AA64SMFR0, I8I32, 0xf);  /* FEAT_SME */
+    t = FIELD_DP64(t, ID_AA64SMFR0, F64F64, 1);   /* FEAT_SME_F64F64 */
+    t = FIELD_DP64(t, ID_AA64SMFR0, I16I64, 0xf); /* FEAT_SME_I16I64 */
+    t = FIELD_DP64(t, ID_AA64SMFR0, FA64, 1);     /* FEAT_SME_FA64 */
+    cpu->isar.id_aa64smfr0 = t;
+
     /* Replicate the same data to the 32-bit id registers.  */
     aa32_max_features(cpu);
 
-- 
2.25.1

From: Richard Henderson <richard.henderson@linaro.org>

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220708151540.18136-34-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 linux-user/aarch64/target_cpu.h | 5 ++++-
 1 file changed, 4 insertions(+), 1 deletion(-)

diff --git a/linux-user/aarch64/target_cpu.h b/linux-user/aarch64/target_cpu.h
index XXXXXXX..XXXXXXX 100644
--- a/linux-user/aarch64/target_cpu.h
+++ b/linux-user/aarch64/target_cpu.h
@@ -XXX,XX +XXX,XX @@ static inline void cpu_clone_regs_parent(CPUARMState *env, unsigned flags)
 
 static inline void cpu_set_tls(CPUARMState *env, target_ulong newtls)
 {
-    /* Note that AArch64 Linux keeps the TLS pointer in TPIDR; this is
+    /*
+     * Note that AArch64 Linux keeps the TLS pointer in TPIDR; this is
      * different from AArch32 Linux, which uses TPIDRRO.
      */
     env->cp15.tpidr_el[0] = newtls;
+    /* TPIDR2_EL0 is cleared with CLONE_SETTLS. */
+    env->cp15.tpidr2_el0 = 0;
 }
 
 static inline abi_ulong get_sp_from_cpustate(CPUARMState *state)
-- 
2.25.1

From: Richard Henderson <richard.henderson@linaro.org>

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220708151540.18136-35-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 linux-user/aarch64/cpu_loop.c | 9 +++++++++
 1 file changed, 9 insertions(+)

diff --git a/linux-user/aarch64/cpu_loop.c b/linux-user/aarch64/cpu_loop.c
index XXXXXXX..XXXXXXX 100644
--- a/linux-user/aarch64/cpu_loop.c
+++ b/linux-user/aarch64/cpu_loop.c
@@ -XXX,XX +XXX,XX @@ void cpu_loop(CPUARMState *env)
 
         switch (trapnr) {
         case EXCP_SWI:
+            /*
+             * On syscall, PSTATE.ZA is preserved, along with the ZA matrix.
+             * PSTATE.SM is cleared, per SMSTOP, which does ResetSVEState.
+             */
+            if (FIELD_EX64(env->svcr, SVCR, SM)) {
+                env->svcr = FIELD_DP64(env->svcr, SVCR, SM, 0);
+                arm_rebuild_hflags(env);
+                arm_reset_sve_state(env);
+            }
             ret = do_syscall(env,
                              env->xregs[8],
                              env->xregs[0],
-- 
2.25.1

From: Richard Henderson <richard.henderson@linaro.org>

Make sure to zero the currently reserved fields.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220708151540.18136-36-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 linux-user/aarch64/signal.c | 9 ++++++++-
 1 file changed, 8 insertions(+), 1 deletion(-)

diff --git a/linux-user/aarch64/signal.c b/linux-user/aarch64/signal.c
index XXXXXXX..XXXXXXX 100644
--- a/linux-user/aarch64/signal.c
+++ b/linux-user/aarch64/signal.c
@@ -XXX,XX +XXX,XX @@ struct target_extra_context {
 struct target_sve_context {
     struct target_aarch64_ctx head;
     uint16_t vl;
-    uint16_t reserved[3];
+    uint16_t flags;
+    uint16_t reserved[2];
     /* The actual SVE data immediately follows.  It is laid out
      * according to TARGET_SVE_SIG_{Z,P}REG_OFFSET, based off of
      * the original struct pointer.
@@ -XXX,XX +XXX,XX @@ struct target_sve_context {
 #define TARGET_SVE_SIG_CONTEXT_SIZE(VQ) \
     (TARGET_SVE_SIG_PREG_OFFSET(VQ, 17))
 
+#define TARGET_SVE_SIG_FLAG_SM  1
+
 struct target_rt_sigframe {
     struct target_siginfo info;
     struct target_ucontext uc;
@@ -XXX,XX +XXX,XX @@ static void target_setup_sve_record(struct target_sve_context *sve,
 {
     int i, j;
 
+    memset(sve, 0, sizeof(*sve));
     __put_user(TARGET_SVE_MAGIC, &sve->head.magic);
     __put_user(size, &sve->head.size);
     __put_user(vq * TARGET_SVE_VQ_BYTES, &sve->vl);
+    if (FIELD_EX64(env->svcr, SVCR, SM)) {
+        __put_user(TARGET_SVE_SIG_FLAG_SM, &sve->flags);
+    }
 
     /* Note that SVE regs are stored as a byte stream, with each byte element
      * at a subsequent address.  This corresponds to a little-endian store
-- 
2.25.1

From: Richard Henderson <richard.henderson@linaro.org>

Fold the return value setting into the goto, so each
point of failure need not do both.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220708151540.18136-37-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 linux-user/aarch64/signal.c | 26 +++++++++++---------------
 1 file changed, 11 insertions(+), 15 deletions(-)

diff --git a/linux-user/aarch64/signal.c b/linux-user/aarch64/signal.c
index XXXXXXX..XXXXXXX 100644
--- a/linux-user/aarch64/signal.c
+++ b/linux-user/aarch64/signal.c
@@ -XXX,XX +XXX,XX @@ static int target_restore_sigframe(CPUARMState *env,
     struct target_sve_context *sve = NULL;
     uint64_t extra_datap = 0;
     bool used_extra = false;
-    bool err = false;
     int vq = 0, sve_size = 0;
 
     target_restore_general_frame(env, sf);
@@ -XXX,XX +XXX,XX @@ static int target_restore_sigframe(CPUARMState *env,
         switch (magic) {
         case 0:
             if (size != 0) {
-                err = true;
-                goto exit;
+                goto err;
             }
             if (used_extra) {
                 ctx = NULL;
@@ -XXX,XX +XXX,XX @@ static int target_restore_sigframe(CPUARMState *env,
 
         case TARGET_FPSIMD_MAGIC:
             if (fpsimd || size != sizeof(struct target_fpsimd_context)) {
-                err = true;
-                goto exit;
+                goto err;
             }
             fpsimd = (struct target_fpsimd_context *)ctx;
             break;
@@ -XXX,XX +XXX,XX @@ static int target_restore_sigframe(CPUARMState *env,
                     break;
                 }
             }
-            err = true;
-            goto exit;
+            goto err;
 
         case TARGET_EXTRA_MAGIC:
             if (extra || size != sizeof(struct target_extra_context)) {
-                err = true;
-                goto exit;
+                goto err;
             }
             __get_user(extra_datap,
                        &((struct target_extra_context *)ctx)->datap);
@@ -XXX,XX +XXX,XX @@ static int target_restore_sigframe(CPUARMState *env,
             /* Unknown record -- we certainly didn't generate it.
              * Did we in fact get out of sync?
              */
-            err = true;
-            goto exit;
+            goto err;
         }
         ctx = (void *)ctx + size;
     }
@@ -XXX,XX +XXX,XX @@ static int target_restore_sigframe(CPUARMState *env,
     if (fpsimd) {
         target_restore_fpsimd_record(env, fpsimd);
     } else {
-        err = true;
+        goto err;
     }
 
     /* SVE data, if present, overwrites FPSIMD data.  */
     if (sve) {
         target_restore_sve_record(env, sve, vq);
     }
-
- exit:
     unlock_user(extra, extra_datap, 0);
-    return err;
+    return 0;
+
+ err:
+    unlock_user(extra, extra_datap, 0);
+    return 1;
 }
 
 static abi_ulong get_sigframe(struct target_sigaction *ka,
-- 
2.25.1

From: Richard Henderson <richard.henderson@linaro.org>

In parse_user_sigframe, the kernel rejects duplicate sve records,
or records that are smaller than the header.  We were silently
allowing these cases to pass, dropping the record.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220708151540.18136-38-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 linux-user/aarch64/signal.c | 5 ++++-
 1 file changed, 4 insertions(+), 1 deletion(-)

diff --git a/linux-user/aarch64/signal.c b/linux-user/aarch64/signal.c
index XXXXXXX..XXXXXXX 100644
--- a/linux-user/aarch64/signal.c
+++ b/linux-user/aarch64/signal.c
@@ -XXX,XX +XXX,XX @@ static int target_restore_sigframe(CPUARMState *env,
             break;
 
         case TARGET_SVE_MAGIC:
+            if (sve || size < sizeof(struct target_sve_context)) {
+                goto err;
+            }
             if (cpu_isar_feature(aa64_sve, env_archcpu(env))) {
                 vq = sve_vq(env);
                 sve_size = QEMU_ALIGN_UP(TARGET_SVE_SIG_CONTEXT_SIZE(vq), 16);
-                if (!sve && size == sve_size) {
+                if (size == sve_size) {
                     sve = (struct target_sve_context *)ctx;
                     break;
                 }
-- 
2.25.1

From: Richard Henderson <richard.henderson@linaro.org>

Move the checks out of the parsing loop and into the
restore function.  This more closely mirrors the code
structure in the kernel, and is slightly clearer.

Reject rather than silently skip incorrect VL and SVE record sizes,
bringing our checks in to line with those the kernel does.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220708151540.18136-40-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 linux-user/aarch64/signal.c | 51 +++++++++++++++++++++++++------------
 1 file changed, 35 insertions(+), 16 deletions(-)

diff --git a/linux-user/aarch64/signal.c b/linux-user/aarch64/signal.c
index XXXXXXX..XXXXXXX 100644
--- a/linux-user/aarch64/signal.c
+++ b/linux-user/aarch64/signal.c
@@ -XXX,XX +XXX,XX @@ static void target_restore_fpsimd_record(CPUARMState *env,
     }
 }
 
-static void target_restore_sve_record(CPUARMState *env,
-                                      struct target_sve_context *sve, int vq)
+static bool target_restore_sve_record(CPUARMState *env,
+                                      struct target_sve_context *sve,
+                                      int size)
 {
-    int i, j;
+    int i, j, vl, vq;
 
-    /* Note that SVE regs are stored as a byte stream, with each byte element
+    if (!cpu_isar_feature(aa64_sve, env_archcpu(env))) {
+        return false;
+    }
+
+    __get_user(vl, &sve->vl);
+    vq = sve_vq(env);
+
+    /* Reject mismatched VL. */
+    if (vl != vq * TARGET_SVE_VQ_BYTES) {
+        return false;
+    }
+
+    /* Accept empty record -- used to clear PSTATE.SM. */
+    if (size <= sizeof(*sve)) {
+        return true;
+    }
+
+    /* Reject non-empty but incomplete record. */
+    if (size < TARGET_SVE_SIG_CONTEXT_SIZE(vq)) {
+        return false;
+    }
+
+    /*
+     * Note that SVE regs are stored as a byte stream, with each byte element
      * at a subsequent address.  This corresponds to a little-endian load
      * of our 64-bit hunks.
      */
@@ -XXX,XX +XXX,XX @@ static void target_restore_sve_record(CPUARMState *env,
             }
         }
     }
+    return true;
 }
 
 static int target_restore_sigframe(CPUARMState *env,
@@ -XXX,XX +XXX,XX @@ static int target_restore_sigframe(CPUARMState *env,
     struct target_sve_context *sve = NULL;
     uint64_t extra_datap = 0;
     bool used_extra = false;
-    int vq = 0, sve_size = 0;
+    int sve_size = 0;
 
     target_restore_general_frame(env, sf);
 
@@ -XXX,XX +XXX,XX @@ static int target_restore_sigframe(CPUARMState *env,
             if (sve || size < sizeof(struct target_sve_context)) {
                 goto err;
             }
-            if (cpu_isar_feature(aa64_sve, env_archcpu(env))) {
-                vq = sve_vq(env);
-                sve_size = QEMU_ALIGN_UP(TARGET_SVE_SIG_CONTEXT_SIZE(vq), 16);
-                if (size == sve_size) {
-                    sve = (struct target_sve_context *)ctx;
-                    break;
-                }
-            }
-            goto err;
+            sve = (struct target_sve_context *)ctx;
+            sve_size = size;
+            break;
 
         case TARGET_EXTRA_MAGIC:
             if (extra || size != sizeof(struct target_extra_context)) {
@@ -XXX,XX +XXX,XX @@ static int target_restore_sigframe(CPUARMState *env,
     }
 
     /* SVE data, if present, overwrites FPSIMD data.  */
-    if (sve) {
-        target_restore_sve_record(env, sve, vq);
+    if (sve && !target_restore_sve_record(env, sve, sve_size)) {
+        goto err;
     }
     unlock_user(extra, extra_datap, 0);
     return 0;
-- 
2.25.1

From: Richard Henderson <richard.henderson@linaro.org>

Set the SM bit in the SVE record on signal delivery, create the ZA record.
Restore SM and ZA state according to the records present on return.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220708151540.18136-41-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 linux-user/aarch64/signal.c | 167 +++++++++++++++++++++++++++++++++---
 1 file changed, 154 insertions(+), 13 deletions(-)

diff --git a/linux-user/aarch64/signal.c b/linux-user/aarch64/signal.c
index XXXXXXX..XXXXXXX 100644
--- a/linux-user/aarch64/signal.c
+++ b/linux-user/aarch64/signal.c
@@ -XXX,XX +XXX,XX @@ struct target_sve_context {
 
 #define TARGET_SVE_SIG_FLAG_SM  1
 
+#define TARGET_ZA_MAGIC        0x54366345
+
+struct target_za_context {
+    struct target_aarch64_ctx head;
+    uint16_t vl;
+    uint16_t reserved[3];
+    /* The actual ZA data immediately follows. */
+};
+
+#define TARGET_ZA_SIG_REGS_OFFSET \
+    QEMU_ALIGN_UP(sizeof(struct target_za_context), TARGET_SVE_VQ_BYTES)
+#define TARGET_ZA_SIG_ZAV_OFFSET(VQ, N) \
+    (TARGET_ZA_SIG_REGS_OFFSET + (VQ) * TARGET_SVE_VQ_BYTES * (N))
+#define TARGET_ZA_SIG_CONTEXT_SIZE(VQ) \
+    TARGET_ZA_SIG_ZAV_OFFSET(VQ, VQ * TARGET_SVE_VQ_BYTES)
+
 struct target_rt_sigframe {
     struct target_siginfo info;
     struct target_ucontext uc;
@@ -XXX,XX +XXX,XX @@ static void target_setup_end_record(struct target_aarch64_ctx *end)
 }
 
 static void target_setup_sve_record(struct target_sve_context *sve,
-                                    CPUARMState *env, int vq, int size)
+                                    CPUARMState *env, int size)
 {
-    int i, j;
+    int i, j, vq = sve_vq(env);
 
     memset(sve, 0, sizeof(*sve));
     __put_user(TARGET_SVE_MAGIC, &sve->head.magic);
@@ -XXX,XX +XXX,XX @@ static void target_setup_sve_record(struct target_sve_context *sve,
     }
 }
 
+static void target_setup_za_record(struct target_za_context *za,
+                                   CPUARMState *env, int size)
+{
+    int vq = sme_vq(env);
+    int vl = vq * TARGET_SVE_VQ_BYTES;
+    int i, j;
+
+    memset(za, 0, sizeof(*za));
+    __put_user(TARGET_ZA_MAGIC, &za->head.magic);
+    __put_user(size, &za->head.size);
+    __put_user(vl, &za->vl);
+
+    if (size == TARGET_ZA_SIG_CONTEXT_SIZE(0)) {
+        return;
+    }
+    assert(size == TARGET_ZA_SIG_CONTEXT_SIZE(vq));
+
+    /*
+     * Note that ZA vectors are stored as a byte stream,
+     * with each byte element at a subsequent address.
+     */
+    for (i = 0; i < vl; ++i) {
+        uint64_t *z = (void *)za + TARGET_ZA_SIG_ZAV_OFFSET(vq, i);
+        for (j = 0; j < vq * 2; ++j) {
+            __put_user_e(env->zarray[i].d[j], z + j, le);
+        }
+    }
+}
+
 static void target_restore_general_frame(CPUARMState *env,
                                          struct target_rt_sigframe *sf)
 {
@@ -XXX,XX +XXX,XX @@ static void target_restore_fpsimd_record(CPUARMState *env,
 
 static bool target_restore_sve_record(CPUARMState *env,
                                       struct target_sve_context *sve,
-                                      int size)
+                                      int size, int *svcr)
 {
-    int i, j, vl, vq;
+    int i, j, vl, vq, flags;
+    bool sm;
 
-    if (!cpu_isar_feature(aa64_sve, env_archcpu(env))) {
+    __get_user(vl, &sve->vl);
+    __get_user(flags, &sve->flags);
+
+    sm = flags & TARGET_SVE_SIG_FLAG_SM;
+
+    /* The cpu must support Streaming or Non-streaming SVE. */
+    if (sm
+        ? !cpu_isar_feature(aa64_sme, env_archcpu(env))
+        : !cpu_isar_feature(aa64_sve, env_archcpu(env))) {
         return false;
     }
 
-    __get_user(vl, &sve->vl);
-    vq = sve_vq(env);
+    /*
+     * Note that we cannot use sve_vq() because that depends on the
+     * current setting of PSTATE.SM, not the state to be restored.
+     */
+    vq = sve_vqm1_for_el_sm(env, 0, sm) + 1;
 
     /* Reject mismatched VL. */
     if (vl != vq * TARGET_SVE_VQ_BYTES) {
@@ -XXX,XX +XXX,XX @@ static bool target_restore_sve_record(CPUARMState *env,
         return false;
     }
 
+    *svcr = FIELD_DP64(*svcr, SVCR, SM, sm);
+
     /*
      * Note that SVE regs are stored as a byte stream, with each byte element
      * at a subsequent address.  This corresponds to a little-endian load
@@ -XXX,XX +XXX,XX @@ static bool target_restore_sve_record(CPUARMState *env,
     return true;
 }
 
+static bool target_restore_za_record(CPUARMState *env,
+                                     struct target_za_context *za,
+                                     int size, int *svcr)
+{
+    int i, j, vl, vq;
+
+    if (!cpu_isar_feature(aa64_sme, env_archcpu(env))) {
+        return false;
+    }
+
+    __get_user(vl, &za->vl);
+    vq = sme_vq(env);
+
+    /* Reject mismatched VL. */
+    if (vl != vq * TARGET_SVE_VQ_BYTES) {
+        return false;
+    }
+
+    /* Accept empty record -- used to clear PSTATE.ZA. */
+    if (size <= TARGET_ZA_SIG_CONTEXT_SIZE(0)) {
+        return true;
+    }
+
+    /* Reject non-empty but incomplete record. */
+    if (size < TARGET_ZA_SIG_CONTEXT_SIZE(vq)) {
+        return false;
+    }
+
+    *svcr = FIELD_DP64(*svcr, SVCR, ZA, 1);
+
+    for (i = 0; i < vl; ++i) {
+        uint64_t *z = (void *)za + TARGET_ZA_SIG_ZAV_OFFSET(vq, i);
+        for (j = 0; j < vq * 2; ++j) {
+            __get_user_e(env->zarray[i].d[j], z + j, le);
+        }
+    }
+    return true;
+}
+
 static int target_restore_sigframe(CPUARMState *env,
                                    struct target_rt_sigframe *sf)
 {
     struct target_aarch64_ctx *ctx, *extra = NULL;
     struct target_fpsimd_context *fpsimd = NULL;
     struct target_sve_context *sve = NULL;
+    struct target_za_context *za = NULL;
     uint64_t extra_datap = 0;
     bool used_extra = false;
     int sve_size = 0;
+    int za_size = 0;
+    int svcr = 0;
 
     target_restore_general_frame(env, sf);
 
@@ -XXX,XX +XXX,XX @@ static int target_restore_sigframe(CPUARMState *env,
             sve_size = size;
             break;
 
+        case TARGET_ZA_MAGIC:
+            if (za || size < sizeof(struct target_za_context)) {
+                goto err;
+            }
+            za = (struct target_za_context *)ctx;
+            za_size = size;
+            break;
+
         case TARGET_EXTRA_MAGIC:
             if (extra || size != sizeof(struct target_extra_context)) {
                 goto err;
@@ -XXX,XX +XXX,XX @@ static int target_restore_sigframe(CPUARMState *env,
     }
 
     /* SVE data, if present, overwrites FPSIMD data.  */
-    if (sve && !target_restore_sve_record(env, sve, sve_size)) {
+    if (sve && !target_restore_sve_record(env, sve, sve_size, &svcr)) {
         goto err;
     }
+    if (za && !target_restore_za_record(env, za, za_size, &svcr)) {
+        goto err;
+    }
+    if (env->svcr != svcr) {
+        env->svcr = svcr;
+        arm_rebuild_hflags(env);
+    }
     unlock_user(extra, extra_datap, 0);
     return 0;
 
@@ -XXX,XX +XXX,XX @@ static void target_setup_frame(int usig, struct target_sigaction *ka,
         .total_size = offsetof(struct target_rt_sigframe,
                                uc.tuc_mcontext.__reserved),
     };
-    int fpsimd_ofs, fr_ofs, sve_ofs = 0, vq = 0, sve_size = 0;
+    int fpsimd_ofs, fr_ofs, sve_ofs = 0, za_ofs = 0;
+    int sve_size = 0, za_size = 0;
     struct target_rt_sigframe *frame;
     struct target_rt_frame_record *fr;
     abi_ulong frame_addr, return_addr;
@@ -XXX,XX +XXX,XX @@ static void target_setup_frame(int usig, struct target_sigaction *ka,
                                       &layout);
 
     /* SVE state needs saving only if it exists.  */
-    if (cpu_isar_feature(aa64_sve, env_archcpu(env))) {
-        vq = sve_vq(env);
-        sve_size = QEMU_ALIGN_UP(TARGET_SVE_SIG_CONTEXT_SIZE(vq), 16);
+    if (cpu_isar_feature(aa64_sve, env_archcpu(env)) ||
+        cpu_isar_feature(aa64_sme, env_archcpu(env))) {
+        sve_size = QEMU_ALIGN_UP(TARGET_SVE_SIG_CONTEXT_SIZE(sve_vq(env)), 16);
         sve_ofs = alloc_sigframe_space(sve_size, &layout);
     }
+    if (cpu_isar_feature(aa64_sme, env_archcpu(env))) {
+        /* ZA state needs saving only if it is enabled.  */
+        if (FIELD_EX64(env->svcr, SVCR, ZA)) {
+            za_size = TARGET_ZA_SIG_CONTEXT_SIZE(sme_vq(env));
+        } else {
+            za_size = TARGET_ZA_SIG_CONTEXT_SIZE(0);
+        }
+        za_ofs = alloc_sigframe_space(za_size, &layout);
+    }
 
     if (layout.extra_ofs) {
         /* Reserve space for the extra end marker.  The standard end marker
@@ -XXX,XX +XXX,XX @@ static void target_setup_frame(int usig, struct target_sigaction *ka,
         target_setup_end_record((void *)frame + layout.extra_end_ofs);
     }
     if (sve_ofs) {
-        target_setup_sve_record((void *)frame + sve_ofs, env, vq, sve_size);
+        target_setup_sve_record((void *)frame + sve_ofs, env, sve_size);
+    }
+    if (za_ofs) {
+        target_setup_za_record((void *)frame + za_ofs, env, za_size);
     }
 
     /* Set up the stack frame for unwinding.  */
@@ -XXX,XX +XXX,XX @@ static void target_setup_frame(int usig, struct target_sigaction *ka,
         env->btype = 2;
     }
 
+    /*
+     * Invoke the signal handler with both SM and ZA disabled.
+     * When clearing SM, ResetSVEState, per SMSTOP.
+     */
+    if (FIELD_EX64(env->svcr, SVCR, SM)) {
+        arm_reset_sve_state(env);
+    }
+    if (env->svcr) {
+        env->svcr = 0;
+        arm_rebuild_hflags(env);
+    }
+
     if (info) {
         tswap_siginfo(&frame->info, info);
         env->xregs[1] = frame_addr + offsetof(struct target_rt_sigframe, info);
-- 
2.25.1

From: Richard Henderson <richard.henderson@linaro.org>

Add "sve" to the sve prctl functions, to distinguish
them from the coming "sme" prctls with similar names.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220708151540.18136-42-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 linux-user/aarch64/target_prctl.h |  8 ++++----
 linux-user/syscall.c              | 12 ++++++------
 2 files changed, 10 insertions(+), 10 deletions(-)

diff --git a/linux-user/aarch64/target_prctl.h b/linux-user/aarch64/target_prctl.h
index XXXXXXX..XXXXXXX 100644
--- a/linux-user/aarch64/target_prctl.h
+++ b/linux-user/aarch64/target_prctl.h
@@ -XXX,XX +XXX,XX @@
 #ifndef AARCH64_TARGET_PRCTL_H
 #define AARCH64_TARGET_PRCTL_H
 
-static abi_long do_prctl_get_vl(CPUArchState *env)
+static abi_long do_prctl_sve_get_vl(CPUArchState *env)
 {
     ARMCPU *cpu = env_archcpu(env);
     if (cpu_isar_feature(aa64_sve, cpu)) {
@@ -XXX,XX +XXX,XX @@ static abi_long do_prctl_get_vl(CPUArchState *env)
     }
     return -TARGET_EINVAL;
 }
-#define do_prctl_get_vl do_prctl_get_vl
+#define do_prctl_sve_get_vl do_prctl_sve_get_vl
 
-static abi_long do_prctl_set_vl(CPUArchState *env, abi_long arg2)
+static abi_long do_prctl_sve_set_vl(CPUArchState *env, abi_long arg2)
 {
     /*
      * We cannot support either PR_SVE_SET_VL_ONEXEC or PR_SVE_VL_INHERIT.
@@ -XXX,XX +XXX,XX @@ static abi_long do_prctl_set_vl(CPUArchState *env, abi_long arg2)
     }
     return -TARGET_EINVAL;
 }
-#define do_prctl_set_vl do_prctl_set_vl
+#define do_prctl_sve_set_vl do_prctl_sve_set_vl
 
 static abi_long do_prctl_reset_keys(CPUArchState *env, abi_long arg2)
 {
diff --git a/linux-user/syscall.c b/linux-user/syscall.c
index XXXXXXX..XXXXXXX 100644
--- a/linux-user/syscall.c
+++ b/linux-user/syscall.c
@@ -XXX,XX +XXX,XX @@ static abi_long do_prctl_inval1(CPUArchState *env, abi_long arg2)
 #ifndef do_prctl_set_fp_mode
 #define do_prctl_set_fp_mode do_prctl_inval1
 #endif
-#ifndef do_prctl_get_vl
-#define do_prctl_get_vl do_prctl_inval0
+#ifndef do_prctl_sve_get_vl
+#define do_prctl_sve_get_vl do_prctl_inval0
 #endif
-#ifndef do_prctl_set_vl
-#define do_prctl_set_vl do_prctl_inval1
+#ifndef do_prctl_sve_set_vl
+#define do_prctl_sve_set_vl do_prctl_inval1
 #endif
 #ifndef do_prctl_reset_keys
 #define do_prctl_reset_keys do_prctl_inval1
@@ -XXX,XX +XXX,XX @@ static abi_long do_prctl(CPUArchState *env, abi_long option, abi_long arg2,
     case PR_SET_FP_MODE:
         return do_prctl_set_fp_mode(env, arg2);
     case PR_SVE_GET_VL:
-        return do_prctl_get_vl(env);
+        return do_prctl_sve_get_vl(env);
     case PR_SVE_SET_VL:
-        return do_prctl_set_vl(env, arg2);
+        return do_prctl_sve_set_vl(env, arg2);
     case PR_PAC_RESET_KEYS:
         if (arg3 || arg4 || arg5) {
             return -TARGET_EINVAL;
-- 
2.25.1

From: Richard Henderson <richard.henderson@linaro.org>

These prctl set the Streaming SVE vector length, which may
be completely different from the Normal SVE vector length.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220708151540.18136-43-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 linux-user/aarch64/target_prctl.h | 54 +++++++++++++++++++++++++++++++
 linux-user/syscall.c              | 16 +++++++++
 2 files changed, 70 insertions(+)

diff --git a/linux-user/aarch64/target_prctl.h b/linux-user/aarch64/target_prctl.h
index XXXXXXX..XXXXXXX 100644
--- a/linux-user/aarch64/target_prctl.h
+++ b/linux-user/aarch64/target_prctl.h
@@ -XXX,XX +XXX,XX @@ static abi_long do_prctl_sve_get_vl(CPUArchState *env)
 {
     ARMCPU *cpu = env_archcpu(env);
     if (cpu_isar_feature(aa64_sve, cpu)) {
+        /* PSTATE.SM is always unset on syscall entry. */
         return sve_vq(env) * 16;
     }
     return -TARGET_EINVAL;
@@ -XXX,XX +XXX,XX @@ static abi_long do_prctl_sve_set_vl(CPUArchState *env, abi_long arg2)
         && arg2 >= 0 && arg2 <= 512 * 16 && !(arg2 & 15)) {
         uint32_t vq, old_vq;
 
+        /* PSTATE.SM is always unset on syscall entry. */
         old_vq = sve_vq(env);
 
         /*
@@ -XXX,XX +XXX,XX @@ static abi_long do_prctl_sve_set_vl(CPUArchState *env, abi_long arg2)
 }
 #define do_prctl_sve_set_vl do_prctl_sve_set_vl
 
+static abi_long do_prctl_sme_get_vl(CPUArchState *env)
+{
+    ARMCPU *cpu = env_archcpu(env);
+    if (cpu_isar_feature(aa64_sme, cpu)) {
+        return sme_vq(env) * 16;
+    }
+    return -TARGET_EINVAL;
+}
+#define do_prctl_sme_get_vl do_prctl_sme_get_vl
+
+static abi_long do_prctl_sme_set_vl(CPUArchState *env, abi_long arg2)
+{
+    /*
+     * We cannot support either PR_SME_SET_VL_ONEXEC or PR_SME_VL_INHERIT.
+     * Note the kernel definition of sve_vl_valid allows for VQ=512,
+     * i.e. VL=8192, even though the architectural maximum is VQ=16.
+     */
+    if (cpu_isar_feature(aa64_sme, env_archcpu(env))
+        && arg2 >= 0 && arg2 <= 512 * 16 && !(arg2 & 15)) {
+        int vq, old_vq;
+
+        old_vq = sme_vq(env);
+
+        /*
+         * Bound the value of vq, so that we know that it fits into
+         * the 4-bit field in SMCR_EL1.  Because PSTATE.SM is cleared
+         * on syscall entry, we are not modifying the current SVE
+         * vector length.
+         */
+        vq = MAX(arg2 / 16, 1);
+        vq = MIN(vq, 16);
+        env->vfp.smcr_el[1] =
+            FIELD_DP64(env->vfp.smcr_el[1], SMCR, LEN, vq - 1);
+
+        /* Delay rebuilding hflags until we know if ZA must change. */
+        vq = sve_vqm1_for_el_sm(env, 0, true) + 1;
+
+        if (vq != old_vq) {
+            /*
+             * PSTATE.ZA state is cleared on any change to SVL.
+             * We need not call arm_rebuild_hflags because PSTATE.SM was
+             * cleared on syscall entry, so this hasn't changed VL.
+             */
+            env->svcr = FIELD_DP64(env->svcr, SVCR, ZA, 0);
+            arm_rebuild_hflags(env);
+        }
+        return vq * 16;
+    }
+    return -TARGET_EINVAL;
+}
+#define do_prctl_sme_set_vl do_prctl_sme_set_vl
+
 static abi_long do_prctl_reset_keys(CPUArchState *env, abi_long arg2)
 {
     ARMCPU *cpu = env_archcpu(env);
diff --git a/linux-user/syscall.c b/linux-user/syscall.c
index XXXXXXX..XXXXXXX 100644
--- a/linux-user/syscall.c
+++ b/linux-user/syscall.c
@@ -XXX,XX +XXX,XX @@ abi_long do_arch_prctl(CPUX86State *env, int code, abi_ulong addr)
 #ifndef PR_SET_SYSCALL_USER_DISPATCH
 # define PR_SET_SYSCALL_USER_DISPATCH 59
 #endif
+#ifndef PR_SME_SET_VL
+# define PR_SME_SET_VL  63
+# define PR_SME_GET_VL  64
+# define PR_SME_VL_LEN_MASK  0xffff
+# define PR_SME_VL_INHERIT   (1 << 17)
+#endif
 
 #include "target_prctl.h"
 
@@ -XXX,XX +XXX,XX @@ static abi_long do_prctl_inval1(CPUArchState *env, abi_long arg2)
 #ifndef do_prctl_set_unalign
 #define do_prctl_set_unalign do_prctl_inval1
 #endif
+#ifndef do_prctl_sme_get_vl
+#define do_prctl_sme_get_vl do_prctl_inval0
+#endif
+#ifndef do_prctl_sme_set_vl
+#define do_prctl_sme_set_vl do_prctl_inval1
+#endif
 
 static abi_long do_prctl(CPUArchState *env, abi_long option, abi_long arg2,
                          abi_long arg3, abi_long arg4, abi_long arg5)
@@ -XXX,XX +XXX,XX @@ static abi_long do_prctl(CPUArchState *env, abi_long option, abi_long arg2,
         return do_prctl_sve_get_vl(env);
     case PR_SVE_SET_VL:
         return do_prctl_sve_set_vl(env, arg2);
+    case PR_SME_GET_VL:
+        return do_prctl_sme_get_vl(env);
+    case PR_SME_SET_VL:
+        return do_prctl_sme_set_vl(env, arg2);
     case PR_PAC_RESET_KEYS:
         if (arg3 || arg4 || arg5) {
             return -TARGET_EINVAL;
-- 
2.25.1

From: Richard Henderson <richard.henderson@linaro.org>

There's no reason to set CPACR_EL1.ZEN if SVE disabled.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220708151540.18136-44-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/cpu.c | 7 +++----
 1 file changed, 3 insertions(+), 4 deletions(-)

diff --git a/target/arm/cpu.c b/target/arm/cpu.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/cpu.c
+++ b/target/arm/cpu.c
@@ -XXX,XX +XXX,XX @@ static void arm_cpu_reset(DeviceState *dev)
         /* and to the FP/Neon instructions */
         env->cp15.cpacr_el1 = FIELD_DP64(env->cp15.cpacr_el1,
                                          CPACR_EL1, FPEN, 3);
-        /* and to the SVE instructions */
-        env->cp15.cpacr_el1 = FIELD_DP64(env->cp15.cpacr_el1,
-                                         CPACR_EL1, ZEN, 3);
-        /* with reasonable vector length */
+        /* and to the SVE instructions, with default vector length */
         if (cpu_isar_feature(aa64_sve, cpu)) {
+            env->cp15.cpacr_el1 = FIELD_DP64(env->cp15.cpacr_el1,
+                                             CPACR_EL1, ZEN, 3);
             env->vfp.zcr_el[1] = cpu->sve_default_vq - 1;
         }
         /*
-- 
2.25.1

From: Richard Henderson <richard.henderson@linaro.org>

Enable SME, TPIDR2_EL0, and FA64 if supported by the cpu.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220708151540.18136-45-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/cpu.c | 11 +++++++++++
 1 file changed, 11 insertions(+)

diff --git a/target/arm/cpu.c b/target/arm/cpu.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/cpu.c
+++ b/target/arm/cpu.c
@@ -XXX,XX +XXX,XX @@ static void arm_cpu_reset(DeviceState *dev)
                                              CPACR_EL1, ZEN, 3);
             env->vfp.zcr_el[1] = cpu->sve_default_vq - 1;
         }
+        /* and for SME instructions, with default vector length, and TPIDR2 */
+        if (cpu_isar_feature(aa64_sme, cpu)) {
+            env->cp15.sctlr_el[1] |= SCTLR_EnTP2;
+            env->cp15.cpacr_el1 = FIELD_DP64(env->cp15.cpacr_el1,
+                                             CPACR_EL1, SMEN, 3);
+            env->vfp.smcr_el[1] = cpu->sme_default_vq - 1;
+            if (cpu_isar_feature(aa64_sme_fa64, cpu)) {
+                env->vfp.smcr_el[1] = FIELD_DP64(env->vfp.smcr_el[1],
+                                                 SMCR, FA64, 1);
+            }
+        }
         /*
          * Enable 48-bit address space (TODO: take reserved_va into account).
          * Enable TBI0 but not TBI1.
-- 
2.25.1

From: Richard Henderson <richard.henderson@linaro.org>

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220708151540.18136-46-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 linux-user/elfload.c | 20 ++++++++++++++++++++
 1 file changed, 20 insertions(+)

diff --git a/linux-user/elfload.c b/linux-user/elfload.c
index XXXXXXX..XXXXXXX 100644
--- a/linux-user/elfload.c
+++ b/linux-user/elfload.c
@@ -XXX,XX +XXX,XX @@ enum {
     ARM_HWCAP2_A64_RNG          = 1 << 16,
     ARM_HWCAP2_A64_BTI          = 1 << 17,
     ARM_HWCAP2_A64_MTE          = 1 << 18,
+    ARM_HWCAP2_A64_ECV          = 1 << 19,
+    ARM_HWCAP2_A64_AFP          = 1 << 20,
+    ARM_HWCAP2_A64_RPRES        = 1 << 21,
+    ARM_HWCAP2_A64_MTE3         = 1 << 22,
+    ARM_HWCAP2_A64_SME          = 1 << 23,
+    ARM_HWCAP2_A64_SME_I16I64   = 1 << 24,
+    ARM_HWCAP2_A64_SME_F64F64   = 1 << 25,
+    ARM_HWCAP2_A64_SME_I8I32    = 1 << 26,
+    ARM_HWCAP2_A64_SME_F16F32   = 1 << 27,
+    ARM_HWCAP2_A64_SME_B16F32   = 1 << 28,
+    ARM_HWCAP2_A64_SME_F32F32   = 1 << 29,
+    ARM_HWCAP2_A64_SME_FA64     = 1 << 30,
 };
 
 #define ELF_HWCAP   get_elf_hwcap()
@@ -XXX,XX +XXX,XX @@ static uint32_t get_elf_hwcap2(void)
     GET_FEATURE_ID(aa64_rndr, ARM_HWCAP2_A64_RNG);
     GET_FEATURE_ID(aa64_bti, ARM_HWCAP2_A64_BTI);
     GET_FEATURE_ID(aa64_mte, ARM_HWCAP2_A64_MTE);
+    GET_FEATURE_ID(aa64_sme, (ARM_HWCAP2_A64_SME |
+                              ARM_HWCAP2_A64_SME_F32F32 |
+                              ARM_HWCAP2_A64_SME_B16F32 |
+                              ARM_HWCAP2_A64_SME_F16F32 |
+                              ARM_HWCAP2_A64_SME_I8I32));
+    GET_FEATURE_ID(aa64_sme_f64f64, ARM_HWCAP2_A64_SME_F64F64);
+    GET_FEATURE_ID(aa64_sme_i16i64, ARM_HWCAP2_A64_SME_I16I64);
+    GET_FEATURE_ID(aa64_sme_fa64, ARM_HWCAP2_A64_SME_FA64);
 
     return hwcaps;
 }
-- 
2.25.1

Hi; here's the latest round of arm patches. I have included also
my patchset for the RTC devices to avoid keeping time_t and
time_t diffs in 32-bit variables.

thanks
-- PMM

The following changes since commit 156618d9ea67f2f2e31d9dedd97f2dcccbe6808c:

Merge tag 'block-pull-request' of https://gitlab.com/stefanha/qemu into staging (2023-08-30 09:20:27 -0400)

are available in the Git repository at:

https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20230831

for you to fetch changes up to e73b8bb8a3e9a162f70e9ffbf922d4fafc96bbfb:

hw/arm: Set number of MPU regions correctly for an505, an521, an524 (2023-08-31 11:07:02 +0100)

----------------------------------------------------------------
target-arm queue:
 * Some of the preliminary patches for Cortex-A710 support
 * i.MX7 and i.MX6UL refactoring
 * Implement SRC device for i.MX7
 * Catch illegal-exception-return from EL3 with bad NSE/NS
 * Use 64-bit offsets for holding time_t differences in RTC devices
 * Model correct number of MPU regions for an505, an521, an524 boards

----------------------------------------------------------------
Alex Bennée (1):
      target/arm: properly document FEAT_CRC32

Jean-Christophe Dubois (6):
      Remove i.MX7 IOMUX GPR device from i.MX6UL
      Refactor i.MX6UL processor code
      Add i.MX6UL missing devices.
      Refactor i.MX7 processor code
      Add i.MX7 missing TZ devices and memory regions
      Add i.MX7 SRC device implementation

Peter Maydell (8):
      target/arm: Catch illegal-exception-return from EL3 with bad NSE/NS
      hw/rtc/m48t59: Use 64-bit arithmetic in set_alarm()
      hw/rtc/twl92230: Use int64_t for sec_offset and alm_sec
      hw/rtc/aspeed_rtc: Use 64-bit offset for holding time_t difference
      rtc: Use time_t for passing and returning time offsets
      target/arm: Do all "ARM_FEATURE_X implies Y" checks in post_init
      hw/arm/armv7m: Add mpu-ns-regions and mpu-s-regions properties
      hw/arm: Set number of MPU regions correctly for an505, an521, an524

Richard Henderson (9):
      target/arm: Reduce dcz_blocksize to uint8_t
      target/arm: Allow cpu to configure GM blocksize
      target/arm: Support more GM blocksizes
      target/arm: When tag memory is not present, set MTE=1
      target/arm: Introduce make_ccsidr64
      target/arm: Apply access checks to neoverse-n1 special registers
      target/arm: Apply access checks to neoverse-v1 special registers
      target/arm: Suppress FEAT_TRBE (Trace Buffer Extension)
      target/arm: Implement FEAT_HPDS2 as a no-op

From: Richard Henderson <richard.henderson@linaro.org>

Previously we hard-coded the blocksize with GMID_EL1_BS.
But the value we choose for -cpu max does not match the
value that cortex-a710 uses.

Mirror the way we handle dcz_blocksize.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20230811214031.171020-3-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/cpu.h               |  2 ++
 target/arm/internals.h         |  6 -----
 target/arm/tcg/translate.h     |  2 ++
 target/arm/helper.c            | 11 +++++---
 target/arm/tcg/cpu64.c         |  1 +
 target/arm/tcg/mte_helper.c    | 46 ++++++++++++++++++++++------------
 target/arm/tcg/translate-a64.c |  5 ++--
 7 files changed, 45 insertions(+), 28 deletions(-)

diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -XXX,XX +XXX,XX @@ struct ArchCPU {
 
     /* DCZ blocksize, in log_2(words), ie low 4 bits of DCZID_EL0 */
     uint8_t dcz_blocksize;
+    /* GM blocksize, in log_2(words), ie low 4 bits of GMID_EL0 */
+    uint8_t gm_blocksize;
 
     uint64_t rvbar_prop; /* Property/input signals.  */
 
diff --git a/target/arm/internals.h b/target/arm/internals.h
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/internals.h
+++ b/target/arm/internals.h
@@ -XXX,XX +XXX,XX @@ void arm_log_exception(CPUState *cs);
 
 #endif /* !CONFIG_USER_ONLY */
 
-/*
- * The log2 of the words in the tag block, for GMID_EL1.BS.
- * The is the maximum, 256 bytes, which manipulates 64-bits of tags.
- */
-#define GMID_EL1_BS  6
-
 /*
  * SVE predicates are 1/8 the size of SVE vectors, and cannot use
  * the same simd_desc() encoding due to restrictions on size.
diff --git a/target/arm/tcg/translate.h b/target/arm/tcg/translate.h
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/tcg/translate.h
+++ b/target/arm/tcg/translate.h
@@ -XXX,XX +XXX,XX @@ typedef struct DisasContext {
     int8_t btype;
     /* A copy of cpu->dcz_blocksize. */
     uint8_t dcz_blocksize;
+    /* A copy of cpu->gm_blocksize. */
+    uint8_t gm_blocksize;
     /* True if this page is guarded.  */
     bool guarded_page;
     /* Bottom two bits of XScale c15_cpar coprocessor access control reg */
diff --git a/target/arm/helper.c b/target/arm/helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo mte_reginfo[] = {
       .opc0 = 3, .opc1 = 0, .crn = 1, .crm = 0, .opc2 = 6,
       .access = PL1_RW, .accessfn = access_mte,
       .fieldoffset = offsetof(CPUARMState, cp15.gcr_el1) },
-    { .name = "GMID_EL1", .state = ARM_CP_STATE_AA64,
-      .opc0 = 3, .opc1 = 1, .crn = 0, .crm = 0, .opc2 = 4,
-      .access = PL1_R, .accessfn = access_aa64_tid5,
-      .type = ARM_CP_CONST, .resetvalue = GMID_EL1_BS },
     { .name = "TCO", .state = ARM_CP_STATE_AA64,
       .opc0 = 3, .opc1 = 3, .crn = 4, .crm = 2, .opc2 = 7,
       .type = ARM_CP_NO_RAW,
@@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu)
      * then define only a RAZ/WI version of PSTATE.TCO.
      */
     if (cpu_isar_feature(aa64_mte, cpu)) {
+        ARMCPRegInfo gmid_reginfo = {
+            .name = "GMID_EL1", .state = ARM_CP_STATE_AA64,
+            .opc0 = 3, .opc1 = 1, .crn = 0, .crm = 0, .opc2 = 4,
+            .access = PL1_R, .accessfn = access_aa64_tid5,
+            .type = ARM_CP_CONST, .resetvalue = cpu->gm_blocksize,
+        };
+        define_one_arm_cp_reg(cpu, &gmid_reginfo);
         define_arm_cp_regs(cpu, mte_reginfo);
         define_arm_cp_regs(cpu, mte_el0_cacheop_reginfo);
     } else if (cpu_isar_feature(aa64_mte_insn_reg, cpu)) {
diff --git a/target/arm/tcg/cpu64.c b/target/arm/tcg/cpu64.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/tcg/cpu64.c
+++ b/target/arm/tcg/cpu64.c
@@ -XXX,XX +XXX,XX @@ void aarch64_max_tcg_initfn(Object *obj)
     cpu->ctr = 0x80038003; /* 32 byte I and D cacheline size, VIPT icache */
     cpu->dcz_blocksize = 7; /*  512 bytes */
 #endif
+    cpu->gm_blocksize = 6;  /*  256 bytes */
 
     cpu->sve_vq.supported = MAKE_64BIT_MASK(0, ARM_MAX_VQ);
     cpu->sme_vq.supported = SVE_VQ_POW2_MAP;
diff --git a/target/arm/tcg/mte_helper.c b/target/arm/tcg/mte_helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/tcg/mte_helper.c
+++ b/target/arm/tcg/mte_helper.c
@@ -XXX,XX +XXX,XX @@ void HELPER(st2g_stub)(CPUARMState *env, uint64_t ptr)
     }
 }
 
-#define LDGM_STGM_SIZE  (4 << GMID_EL1_BS)
-
 uint64_t HELPER(ldgm)(CPUARMState *env, uint64_t ptr)
 {
     int mmu_idx = cpu_mmu_index(env, false);
     uintptr_t ra = GETPC();
+    int gm_bs = env_archcpu(env)->gm_blocksize;
+    int gm_bs_bytes = 4 << gm_bs;
     void *tag_mem;
 
-    ptr = QEMU_ALIGN_DOWN(ptr, LDGM_STGM_SIZE);
+    ptr = QEMU_ALIGN_DOWN(ptr, gm_bs_bytes);
 
     /* Trap if accessing an invalid page.  */
     tag_mem = allocation_tag_mem(env, mmu_idx, ptr, MMU_DATA_LOAD,
-                                 LDGM_STGM_SIZE, MMU_DATA_LOAD,
-                                 LDGM_STGM_SIZE / (2 * TAG_GRANULE), ra);
+                                 gm_bs_bytes, MMU_DATA_LOAD,
+                                 gm_bs_bytes / (2 * TAG_GRANULE), ra);
 
     /* The tag is squashed to zero if the page does not support tags.  */
     if (!tag_mem) {
         return 0;
     }
 
-    QEMU_BUILD_BUG_ON(GMID_EL1_BS != 6);
     /*
-     * We are loading 64-bits worth of tags.  The ordering of elements
-     * within the word corresponds to a 64-bit little-endian operation.
+     * The ordering of elements within the word corresponds to
+     * a little-endian operation.
      */
-    return ldq_le_p(tag_mem);
+    switch (gm_bs) {
+    case 6:
+        /* 256 bytes -> 16 tags -> 64 result bits */
+        return ldq_le_p(tag_mem);
+    default:
+        /* cpu configured with unsupported gm blocksize. */
+        g_assert_not_reached();
+    }
 }
 
 void HELPER(stgm)(CPUARMState *env, uint64_t ptr, uint64_t val)
 {
     int mmu_idx = cpu_mmu_index(env, false);
     uintptr_t ra = GETPC();
+    int gm_bs = env_archcpu(env)->gm_blocksize;
+    int gm_bs_bytes = 4 << gm_bs;
     void *tag_mem;
 
-    ptr = QEMU_ALIGN_DOWN(ptr, LDGM_STGM_SIZE);
+    ptr = QEMU_ALIGN_DOWN(ptr, gm_bs_bytes);
 
     /* Trap if accessing an invalid page.  */
     tag_mem = allocation_tag_mem(env, mmu_idx, ptr, MMU_DATA_STORE,
-                                 LDGM_STGM_SIZE, MMU_DATA_LOAD,
-                                 LDGM_STGM_SIZE / (2 * TAG_GRANULE), ra);
+                                 gm_bs_bytes, MMU_DATA_LOAD,
+                                 gm_bs_bytes / (2 * TAG_GRANULE), ra);
 
     /*
      * Tag store only happens if the page support tags,
@@ -XXX,XX +XXX,XX @@ void HELPER(stgm)(CPUARMState *env, uint64_t ptr, uint64_t val)
         return;
     }
 
-    QEMU_BUILD_BUG_ON(GMID_EL1_BS != 6);
     /*
-     * We are storing 64-bits worth of tags.  The ordering of elements
-     * within the word corresponds to a 64-bit little-endian operation.
+     * The ordering of elements within the word corresponds to
+     * a little-endian operation.
      */
-    stq_le_p(tag_mem, val);
+    switch (gm_bs) {
+    case 6:
+        stq_le_p(tag_mem, val);
+        break;
+    default:
+        /* cpu configured with unsupported gm blocksize. */
+        g_assert_not_reached();
+    }
 }
 
 void HELPER(stzgm_tags)(CPUARMState *env, uint64_t ptr, uint64_t val)
diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/tcg/translate-a64.c
+++ b/target/arm/tcg/translate-a64.c
@@ -XXX,XX +XXX,XX @@ static bool trans_STGM(DisasContext *s, arg_ldst_tag *a)
         gen_helper_stgm(cpu_env, addr, tcg_rt);
     } else {
         MMUAccessType acc = MMU_DATA_STORE;
-        int size = 4 << GMID_EL1_BS;
+        int size = 4 << s->gm_blocksize;
 
         clean_addr = clean_data_tbi(s, addr);
         tcg_gen_andi_i64(clean_addr, clean_addr, -size);
@@ -XXX,XX +XXX,XX @@ static bool trans_LDGM(DisasContext *s, arg_ldst_tag *a)
         gen_helper_ldgm(tcg_rt, cpu_env, addr);
     } else {
         MMUAccessType acc = MMU_DATA_LOAD;
-        int size = 4 << GMID_EL1_BS;
+        int size = 4 << s->gm_blocksize;
 
         clean_addr = clean_data_tbi(s, addr);
         tcg_gen_andi_i64(clean_addr, clean_addr, -size);
@@ -XXX,XX +XXX,XX @@ static void aarch64_tr_init_disas_context(DisasContextBase *dcbase,
     dc->cp_regs = arm_cpu->cp_regs;
     dc->features = env->features;
     dc->dcz_blocksize = arm_cpu->dcz_blocksize;
+    dc->gm_blocksize = arm_cpu->gm_blocksize;
 
 #ifdef CONFIG_USER_ONLY
     /* In sve_probe_page, we assume TBI is enabled. */
-- 
2.34.1

From: Richard Henderson <richard.henderson@linaro.org>

Support all of the easy GM block sizes.
Use direct memory operations, since the pointers are aligned.

While BS=2 (16 bytes, 1 tag) is a legal setting, that requires
an atomic store of one nibble.  This is not difficult, but there
is also no point in supporting it until required.

Note that cortex-a710 sets GM blocksize to match its cacheline
size of 64 bytes.  I expect many implementations will also
match the cacheline, which makes 16 bytes very unlikely.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20230811214031.171020-4-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/cpu.c            | 18 +++++++++---
 target/arm/tcg/mte_helper.c | 56 +++++++++++++++++++++++++++++++------
 2 files changed, 62 insertions(+), 12 deletions(-)

diff --git a/target/arm/cpu.c b/target/arm/cpu.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/cpu.c
+++ b/target/arm/cpu.c
@@ -XXX,XX +XXX,XX @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp)
                                        ID_PFR1, VIRTUALIZATION, 0);
     }
 
+    if (cpu_isar_feature(aa64_mte, cpu)) {
+        /*
+         * The architectural range of GM blocksize is 2-6, however qemu
+         * doesn't support blocksize of 2 (see HELPER(ldgm)).
+         */
+        if (tcg_enabled()) {
+            assert(cpu->gm_blocksize >= 3 && cpu->gm_blocksize <= 6);
+        }
+
 #ifndef CONFIG_USER_ONLY
-    if (cpu->tag_memory == NULL && cpu_isar_feature(aa64_mte, cpu)) {
         /*
          * Disable the MTE feature bits if we do not have tag-memory
          * provided by the machine.
          */
-        cpu->isar.id_aa64pfr1 =
-            FIELD_DP64(cpu->isar.id_aa64pfr1, ID_AA64PFR1, MTE, 0);
-    }
+        if (cpu->tag_memory == NULL) {
+            cpu->isar.id_aa64pfr1 =
+                FIELD_DP64(cpu->isar.id_aa64pfr1, ID_AA64PFR1, MTE, 0);
+        }
 #endif
+    }
 
     if (tcg_enabled()) {
         /*
diff --git a/target/arm/tcg/mte_helper.c b/target/arm/tcg/mte_helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/tcg/mte_helper.c
+++ b/target/arm/tcg/mte_helper.c
@@ -XXX,XX +XXX,XX @@ uint64_t HELPER(ldgm)(CPUARMState *env, uint64_t ptr)
     int gm_bs = env_archcpu(env)->gm_blocksize;
     int gm_bs_bytes = 4 << gm_bs;
     void *tag_mem;
+    uint64_t ret;
+    int shift;
 
     ptr = QEMU_ALIGN_DOWN(ptr, gm_bs_bytes);
 
@@ -XXX,XX +XXX,XX @@ uint64_t HELPER(ldgm)(CPUARMState *env, uint64_t ptr)
 
     /*
      * The ordering of elements within the word corresponds to
-     * a little-endian operation.
+     * a little-endian operation.  Computation of shift comes from
+     *
+     *     index = address<LOG2_TAG_GRANULE+3:LOG2_TAG_GRANULE>
+     *     data<index*4+3:index*4> = tag
+     *
+     * Because of the alignment of ptr above, BS=6 has shift=0.
+     * All memory operations are aligned.  Defer support for BS=2,
+     * requiring insertion or extraction of a nibble, until we
+     * support a cpu that requires it.
      */
     switch (gm_bs) {
+    case 3:
+        /* 32 bytes -> 2 tags -> 8 result bits */
+        ret = *(uint8_t *)tag_mem;
+        break;
+    case 4:
+        /* 64 bytes -> 4 tags -> 16 result bits */
+        ret = cpu_to_le16(*(uint16_t *)tag_mem);
+        break;
+    case 5:
+        /* 128 bytes -> 8 tags -> 32 result bits */
+        ret = cpu_to_le32(*(uint32_t *)tag_mem);
+        break;
     case 6:
         /* 256 bytes -> 16 tags -> 64 result bits */
-        return ldq_le_p(tag_mem);
+        return cpu_to_le64(*(uint64_t *)tag_mem);
     default:
-        /* cpu configured with unsupported gm blocksize. */
+        /*
+         * CPU configured with unsupported/invalid gm blocksize.
+         * This is detected early in arm_cpu_realizefn.
+         */
         g_assert_not_reached();
     }
+    shift = extract64(ptr, LOG2_TAG_GRANULE, 4) * 4;
+    return ret << shift;
 }
 
 void HELPER(stgm)(CPUARMState *env, uint64_t ptr, uint64_t val)
@@ -XXX,XX +XXX,XX @@ void HELPER(stgm)(CPUARMState *env, uint64_t ptr, uint64_t val)
     int gm_bs = env_archcpu(env)->gm_blocksize;
     int gm_bs_bytes = 4 << gm_bs;
     void *tag_mem;
+    int shift;
 
     ptr = QEMU_ALIGN_DOWN(ptr, gm_bs_bytes);
 
@@ -XXX,XX +XXX,XX @@ void HELPER(stgm)(CPUARMState *env, uint64_t ptr, uint64_t val)
         return;
     }
 
-    /*
-     * The ordering of elements within the word corresponds to
-     * a little-endian operation.
-     */
+    /* See LDGM for comments on BS and on shift.  */
+    shift = extract64(ptr, LOG2_TAG_GRANULE, 4) * 4;
+    val >>= shift;
     switch (gm_bs) {
+    case 3:
+        /* 32 bytes -> 2 tags -> 8 result bits */
+        *(uint8_t *)tag_mem = val;
+        break;
+    case 4:
+        /* 64 bytes -> 4 tags -> 16 result bits */
+        *(uint16_t *)tag_mem = cpu_to_le16(val);
+        break;
+    case 5:
+        /* 128 bytes -> 8 tags -> 32 result bits */
+        *(uint32_t *)tag_mem = cpu_to_le32(val);
+        break;
     case 6:
-        stq_le_p(tag_mem, val);
+        /* 256 bytes -> 16 tags -> 64 result bits */
+        *(uint64_t *)tag_mem = cpu_to_le64(val);
         break;
     default:
         /* cpu configured with unsupported gm blocksize. */
-- 
2.34.1

From: Richard Henderson <richard.henderson@linaro.org>

When the cpu support MTE, but the system does not, reduce cpu
support to user instructions at EL0 instead of completely
disabling MTE.  If we encounter a cpu implementation which does
something else, we can revisit this setting.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20230811214031.171020-5-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/cpu.c | 7 ++++---
 1 file changed, 4 insertions(+), 3 deletions(-)

diff --git a/target/arm/cpu.c b/target/arm/cpu.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/cpu.c
+++ b/target/arm/cpu.c
@@ -XXX,XX +XXX,XX @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp)
 
 #ifndef CONFIG_USER_ONLY
         /*
-         * Disable the MTE feature bits if we do not have tag-memory
-         * provided by the machine.
+         * If we do not have tag-memory provided by the machine,
+         * reduce MTE support to instructions enabled at EL0.
+         * This matches Cortex-A710 BROADCASTMTE input being LOW.
          */
         if (cpu->tag_memory == NULL) {
             cpu->isar.id_aa64pfr1 =
-                FIELD_DP64(cpu->isar.id_aa64pfr1, ID_AA64PFR1, MTE, 0);
+                FIELD_DP64(cpu->isar.id_aa64pfr1, ID_AA64PFR1, MTE, 1);
         }
 #endif
     }
-- 
2.34.1

From: Richard Henderson <richard.henderson@linaro.org>

Do not hard-code the constants for Neoverse V1.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20230811214031.171020-6-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/tcg/cpu64.c | 48 ++++++++++++++++++++++++++++--------------
 1 file changed, 32 insertions(+), 16 deletions(-)

diff --git a/target/arm/tcg/cpu64.c b/target/arm/tcg/cpu64.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/tcg/cpu64.c
+++ b/target/arm/tcg/cpu64.c
@@ -XXX,XX +XXX,XX @@
 #include "qemu/module.h"
 #include "qapi/visitor.h"
 #include "hw/qdev-properties.h"
+#include "qemu/units.h"
 #include "internals.h"
 #include "cpregs.h"
 
+static uint64_t make_ccsidr64(unsigned assoc, unsigned linesize,
+                              unsigned cachesize)
+{
+    unsigned lg_linesize = ctz32(linesize);
+    unsigned sets;
+
+    /*
+     * The 64-bit CCSIDR_EL1 format is:
+     *   [55:32] number of sets - 1
+     *   [23:3]  associativity - 1
+     *   [2:0]   log2(linesize) - 4
+     *           so 0 == 16 bytes, 1 == 32 bytes, 2 == 64 bytes, etc
+     */
+    assert(assoc != 0);
+    assert(is_power_of_2(linesize));
+    assert(lg_linesize >= 4 && lg_linesize <= 7 + 4);
+
+    /* sets * associativity * linesize == cachesize. */
+    sets = cachesize / (assoc * linesize);
+    assert(cachesize % (assoc * linesize) == 0);
+
+    return ((uint64_t)(sets - 1) << 32)
+         | ((assoc - 1) << 3)
+         | (lg_linesize - 4);
+}
+
 static void aarch64_a35_initfn(Object *obj)
 {
     ARMCPU *cpu = ARM_CPU(obj);
@@ -XXX,XX +XXX,XX @@ static void aarch64_neoverse_v1_initfn(Object *obj)
      * The Neoverse-V1 r1p2 TRM lists 32-bit format CCSIDR_EL1 values,
      * but also says it implements CCIDX, which means they should be
      * 64-bit format. So we here use values which are based on the textual
-     * information in chapter 2 of the TRM (and on the fact that
-     * sets * associativity * linesize == cachesize).
-     *
-     * The 64-bit CCSIDR_EL1 format is:
-     *   [55:32] number of sets - 1
-     *   [23:3]  associativity - 1
-     *   [2:0]   log2(linesize) - 4
-     *           so 0 == 16 bytes, 1 == 32 bytes, 2 == 64 bytes, etc
-     *
-     * L1: 4-way set associative 64-byte line size, total size 64K,
-     * so sets is 256.
+     * information in chapter 2 of the TRM:
      *
+     * L1: 4-way set associative 64-byte line size, total size 64K.
      * L2: 8-way set associative, 64 byte line size, either 512K or 1MB.
-     * We pick 1MB, so this has 2048 sets.
-     *
      * L3: No L3 (this matches the CLIDR_EL1 value).
      */
-    cpu->ccsidr[0] = 0x000000ff0000001aull; /* 64KB L1 dcache */
-    cpu->ccsidr[1] = 0x000000ff0000001aull; /* 64KB L1 icache */
-    cpu->ccsidr[2] = 0x000007ff0000003aull; /* 1MB L2 cache */
+    cpu->ccsidr[0] = make_ccsidr64(4, 64, 64 * KiB); /* L1 dcache */
+    cpu->ccsidr[1] = cpu->ccsidr[0];                 /* L1 icache */
+    cpu->ccsidr[2] = make_ccsidr64(8, 64, 1 * MiB);  /* L2 cache */
 
     /* From 3.2.115 SCTLR_EL3 */
     cpu->reset_sctlr = 0x30c50838;
-- 
2.34.1

From: Richard Henderson <richard.henderson@linaro.org>

Access to many of the special registers is enabled or disabled
by ACTLR_EL[23], which we implement as constant 0, which means
that all writes outside EL3 should trap.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20230811214031.171020-7-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/cpregs.h    |  2 ++
 target/arm/helper.c    |  4 ++--
 target/arm/tcg/cpu64.c | 46 +++++++++++++++++++++++++++++++++---------
 3 files changed, 41 insertions(+), 11 deletions(-)

diff --git a/target/arm/cpregs.h b/target/arm/cpregs.h
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/cpregs.h
+++ b/target/arm/cpregs.h
@@ -XXX,XX +XXX,XX @@ static inline void define_cortex_a72_a57_a53_cp_reginfo(ARMCPU *cpu) { }
 void define_cortex_a72_a57_a53_cp_reginfo(ARMCPU *cpu);
 #endif
 
+CPAccessResult access_tvm_trvm(CPUARMState *, const ARMCPRegInfo *, bool);
+
 #endif /* TARGET_ARM_CPREGS_H */
diff --git a/target/arm/helper.c b/target/arm/helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -XXX,XX +XXX,XX @@ static CPAccessResult access_tpm(CPUARMState *env, const ARMCPRegInfo *ri,
 }
 
 /* Check for traps from EL1 due to HCR_EL2.TVM and HCR_EL2.TRVM.  */
-static CPAccessResult access_tvm_trvm(CPUARMState *env, const ARMCPRegInfo *ri,
-                                      bool isread)
+CPAccessResult access_tvm_trvm(CPUARMState *env, const ARMCPRegInfo *ri,
+                               bool isread)
 {
     if (arm_current_el(env) == 1) {
         uint64_t trap = isread ? HCR_TRVM : HCR_TVM;
diff --git a/target/arm/tcg/cpu64.c b/target/arm/tcg/cpu64.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/tcg/cpu64.c
+++ b/target/arm/tcg/cpu64.c
@@ -XXX,XX +XXX,XX @@ static void aarch64_a64fx_initfn(Object *obj)
     /* TODO:  Add A64FX specific HPC extension registers */
 }
 
+static CPAccessResult access_actlr_w(CPUARMState *env, const ARMCPRegInfo *r,
+                                     bool read)
+{
+    if (!read) {
+        int el = arm_current_el(env);
+
+        /* Because ACTLR_EL2 is constant 0, writes below EL2 trap to EL2. */
+        if (el < 2 && arm_is_el2_enabled(env)) {
+            return CP_ACCESS_TRAP_EL2;
+        }
+        /* Because ACTLR_EL3 is constant 0, writes below EL3 trap to EL3. */
+        if (el < 3 && arm_feature(env, ARM_FEATURE_EL3)) {
+            return CP_ACCESS_TRAP_EL3;
+        }
+    }
+    return CP_ACCESS_OK;
+}
+
 static const ARMCPRegInfo neoverse_n1_cp_reginfo[] = {
     { .name = "ATCR_EL1", .state = ARM_CP_STATE_AA64,
       .opc0 = 3, .opc1 = 0, .crn = 15, .crm = 7, .opc2 = 0,
-      .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
+      .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0,
+      /* Traps and enables are the same as for TCR_EL1. */
+      .accessfn = access_tvm_trvm, .fgt = FGT_TCR_EL1, },
     { .name = "ATCR_EL2", .state = ARM_CP_STATE_AA64,
       .opc0 = 3, .opc1 = 4, .crn = 15, .crm = 7, .opc2 = 0,
       .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo neoverse_n1_cp_reginfo[] = {
       .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
     { .name = "CPUACTLR_EL1", .state = ARM_CP_STATE_AA64,
       .opc0 = 3, .opc1 = 0, .crn = 15, .crm = 1, .opc2 = 0,
-      .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
+      .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0,
+      .accessfn = access_actlr_w },
     { .name = "CPUACTLR2_EL1", .state = ARM_CP_STATE_AA64,
       .opc0 = 3, .opc1 = 0, .crn = 15, .crm = 1, .opc2 = 1,
-      .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
+      .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0,
+      .accessfn = access_actlr_w },
     { .name = "CPUACTLR3_EL1", .state = ARM_CP_STATE_AA64,
       .opc0 = 3, .opc1 = 0, .crn = 15, .crm = 1, .opc2 = 2,
-      .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
+      .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0,
+      .accessfn = access_actlr_w },
     /*
      * Report CPUCFR_EL1.SCU as 1, as we do not implement the DSU
      * (and in particular its system registers).
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo neoverse_n1_cp_reginfo[] = {
       .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 4 },
     { .name = "CPUECTLR_EL1", .state = ARM_CP_STATE_AA64,
       .opc0 = 3, .opc1 = 0, .crn = 15, .crm = 1, .opc2 = 4,
-      .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0x961563010 },
+      .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0x961563010,
+      .accessfn = access_actlr_w },
     { .name = "CPUPCR_EL3", .state = ARM_CP_STATE_AA64,
       .opc0 = 3, .opc1 = 6, .crn = 15, .crm = 8, .opc2 = 1,
       .access = PL3_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo neoverse_n1_cp_reginfo[] = {
       .access = PL3_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
     { .name = "CPUPWRCTLR_EL1", .state = ARM_CP_STATE_AA64,
       .opc0 = 3, .opc1 = 0, .crn = 15, .crm = 2, .opc2 = 7,
-      .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
+      .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0,
+      .accessfn = access_actlr_w },
     { .name = "ERXPFGCDN_EL1", .state = ARM_CP_STATE_AA64,
       .opc0 = 3, .opc1 = 0, .crn = 15, .crm = 2, .opc2 = 2,
-      .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
+      .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0,
+      .accessfn = access_actlr_w },
     { .name = "ERXPFGCTL_EL1", .state = ARM_CP_STATE_AA64,
       .opc0 = 3, .opc1 = 0, .crn = 15, .crm = 2, .opc2 = 1,
-      .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
+      .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0,
+      .accessfn = access_actlr_w },
     { .name = "ERXPFGF_EL1", .state = ARM_CP_STATE_AA64,
       .opc0 = 3, .opc1 = 0, .crn = 15, .crm = 2, .opc2 = 0,
-      .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
+      .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0,
+      .accessfn = access_actlr_w },
 };
 
 static void define_neoverse_n1_cp_reginfo(ARMCPU *cpu)
-- 
2.34.1

From: Richard Henderson <richard.henderson@linaro.org>

There is only one additional EL1 register modeled, which
also needs to use access_actlr_w.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20230811214031.171020-8-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/tcg/cpu64.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/target/arm/tcg/cpu64.c b/target/arm/tcg/cpu64.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/tcg/cpu64.c
+++ b/target/arm/tcg/cpu64.c
@@ -XXX,XX +XXX,XX @@ static void define_neoverse_n1_cp_reginfo(ARMCPU *cpu)
 static const ARMCPRegInfo neoverse_v1_cp_reginfo[] = {
     { .name = "CPUECTLR2_EL1", .state = ARM_CP_STATE_AA64,
       .opc0 = 3, .opc1 = 0, .crn = 15, .crm = 1, .opc2 = 5,
-      .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
+      .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0,
+      .accessfn = access_actlr_w },
     { .name = "CPUPPMCR_EL3", .state = ARM_CP_STATE_AA64,
       .opc0 = 3, .opc1 = 6, .crn = 15, .crm = 2, .opc2 = 0,
       .access = PL3_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
-- 
2.34.1

From: Richard Henderson <richard.henderson@linaro.org>

Like FEAT_TRF (Self-hosted Trace Extension), suppress tracing
external to the cpu, which is out of scope for QEMU.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20230811214031.171020-10-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/cpu.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/target/arm/cpu.c b/target/arm/cpu.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/cpu.c
+++ b/target/arm/cpu.c
@@ -XXX,XX +XXX,XX @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp)
         /* FEAT_SPE (Statistical Profiling Extension) */
         cpu->isar.id_aa64dfr0 =
             FIELD_DP64(cpu->isar.id_aa64dfr0, ID_AA64DFR0, PMSVER, 0);
+        /* FEAT_TRBE (Trace Buffer Extension) */
+        cpu->isar.id_aa64dfr0 =
+            FIELD_DP64(cpu->isar.id_aa64dfr0, ID_AA64DFR0, TRACEBUFFER, 0);
         /* FEAT_TRF (Self-hosted Trace Extension) */
         cpu->isar.id_aa64dfr0 =
             FIELD_DP64(cpu->isar.id_aa64dfr0, ID_AA64DFR0, TRACEFILT, 0);
-- 
2.34.1

From: Richard Henderson <richard.henderson@linaro.org>

This feature allows the operating system to set TCR_ELx.HWU*
to allow the implementation to use the PBHA bits from the
block and page descriptors for for IMPLEMENTATION DEFINED
purposes.  Since QEMU has no need to use these bits, we may
simply ignore them.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20230811214031.171020-11-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 docs/system/arm/emulation.rst | 1 +
 target/arm/tcg/cpu32.c        | 2 +-
 target/arm/tcg/cpu64.c        | 2 +-
 3 files changed, 3 insertions(+), 2 deletions(-)

diff --git a/docs/system/arm/emulation.rst b/docs/system/arm/emulation.rst
index XXXXXXX..XXXXXXX 100644
--- a/docs/system/arm/emulation.rst
+++ b/docs/system/arm/emulation.rst
@@ -XXX,XX +XXX,XX @@ the following architecture extensions:
 - FEAT_HAFDBS (Hardware management of the access flag and dirty bit state)
 - FEAT_HCX (Support for the HCRX_EL2 register)
 - FEAT_HPDS (Hierarchical permission disables)
+- FEAT_HPDS2 (Translation table page-based hardware attributes)
 - FEAT_I8MM (AArch64 Int8 matrix multiplication instructions)
 - FEAT_IDST (ID space trap handling)
 - FEAT_IESB (Implicit error synchronization event)
diff --git a/target/arm/tcg/cpu32.c b/target/arm/tcg/cpu32.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/tcg/cpu32.c
+++ b/target/arm/tcg/cpu32.c
@@ -XXX,XX +XXX,XX @@ void aa32_max_features(ARMCPU *cpu)
     cpu->isar.id_mmfr3 = t;
 
     t = cpu->isar.id_mmfr4;
-    t = FIELD_DP32(t, ID_MMFR4, HPDS, 1);         /* FEAT_AA32HPD */
+    t = FIELD_DP32(t, ID_MMFR4, HPDS, 2);         /* FEAT_HPDS2 */
     t = FIELD_DP32(t, ID_MMFR4, AC2, 1);          /* ACTLR2, HACTLR2 */
     t = FIELD_DP32(t, ID_MMFR4, CNP, 1);          /* FEAT_TTCNP */
     t = FIELD_DP32(t, ID_MMFR4, XNX, 1);          /* FEAT_XNX */
diff --git a/target/arm/tcg/cpu64.c b/target/arm/tcg/cpu64.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/tcg/cpu64.c
+++ b/target/arm/tcg/cpu64.c
@@ -XXX,XX +XXX,XX @@ void aarch64_max_tcg_initfn(Object *obj)
     t = FIELD_DP64(t, ID_AA64MMFR1, HAFDBS, 2);   /* FEAT_HAFDBS */
     t = FIELD_DP64(t, ID_AA64MMFR1, VMIDBITS, 2); /* FEAT_VMID16 */
     t = FIELD_DP64(t, ID_AA64MMFR1, VH, 1);       /* FEAT_VHE */
-    t = FIELD_DP64(t, ID_AA64MMFR1, HPDS, 1);     /* FEAT_HPDS */
+    t = FIELD_DP64(t, ID_AA64MMFR1, HPDS, 2);     /* FEAT_HPDS2 */
     t = FIELD_DP64(t, ID_AA64MMFR1, LO, 1);       /* FEAT_LOR */
     t = FIELD_DP64(t, ID_AA64MMFR1, PAN, 3);      /* FEAT_PAN3 */
     t = FIELD_DP64(t, ID_AA64MMFR1, XNX, 1);      /* FEAT_XNX */
-- 
2.34.1

From: Alex Bennée <alex.bennee@linaro.org>

This is a mandatory feature for Armv8.1 architectures but we don't
state the feature clearly in our emulation list. Also include
FEAT_CRC32 comment in aarch64_max_tcg_initfn for ease of grepping.

Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Message-id: 20230824075406.1515566-1-alex.bennee@linaro.org
Cc: qemu-stable@nongnu.org
Message-Id: <20230222110104.3996971-1-alex.bennee@linaro.org>
[PMM: pluralize 'instructions' in docs]
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 docs/system/arm/emulation.rst | 1 +
 target/arm/tcg/cpu64.c        | 2 +-
 2 files changed, 2 insertions(+), 1 deletion(-)

From: Jean-Christophe Dubois <jcd@tribudubois.net>

i.MX7 IOMUX GPR device is not equivalent to i.MX6UL IOMUXC GPR device.
In particular, register 22 is not present on i.MX6UL and this is actualy
The only register that is really emulated in the i.MX7 IOMUX GPR device.

Note: The i.MX6UL code is actually also implementing the IOMUX GPR device
as an unimplemented device at the same bus adress and the 2 instantiations
were actualy colliding. So we go back to the unimplemented device for now.

Signed-off-by: Jean-Christophe Dubois <jcd@tribudubois.net>
Message-id: 48681bf51ee97646479bb261bee19abebbc8074e.1692964892.git.jcd@tribudubois.net
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 include/hw/arm/fsl-imx6ul.h |  2 --
 hw/arm/fsl-imx6ul.c         | 11 -----------
 2 files changed, 13 deletions(-)

diff --git a/include/hw/arm/fsl-imx6ul.h b/include/hw/arm/fsl-imx6ul.h
index XXXXXXX..XXXXXXX 100644
--- a/include/hw/arm/fsl-imx6ul.h
+++ b/include/hw/arm/fsl-imx6ul.h
@@ -XXX,XX +XXX,XX @@
 #include "hw/misc/imx6ul_ccm.h"
 #include "hw/misc/imx6_src.h"
 #include "hw/misc/imx7_snvs.h"
-#include "hw/misc/imx7_gpr.h"
 #include "hw/intc/imx_gpcv2.h"
 #include "hw/watchdog/wdt_imx2.h"
 #include "hw/gpio/imx_gpio.h"
@@ -XXX,XX +XXX,XX @@ struct FslIMX6ULState {
     IMX6SRCState       src;
     IMX7SNVSState      snvs;
     IMXGPCv2State      gpcv2;
-    IMX7GPRState       gpr;
     IMXSPIState        spi[FSL_IMX6UL_NUM_ECSPIS];
     IMXI2CState        i2c[FSL_IMX6UL_NUM_I2CS];
     IMXSerialState     uart[FSL_IMX6UL_NUM_UARTS];
diff --git a/hw/arm/fsl-imx6ul.c b/hw/arm/fsl-imx6ul.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/fsl-imx6ul.c
+++ b/hw/arm/fsl-imx6ul.c
@@ -XXX,XX +XXX,XX @@ static void fsl_imx6ul_init(Object *obj)
      */
     object_initialize_child(obj, "snvs", &s->snvs, TYPE_IMX7_SNVS);
 
-    /*
-     * GPR
-     */
-    object_initialize_child(obj, "gpr", &s->gpr, TYPE_IMX7_GPR);
-
     /*
      * GPIOs 1 to 5
      */
@@ -XXX,XX +XXX,XX @@ static void fsl_imx6ul_realize(DeviceState *dev, Error **errp)
                                             FSL_IMX6UL_WDOGn_IRQ[i]));
     }
 
-    /*
-     * GPR
-     */
-    sysbus_realize(SYS_BUS_DEVICE(&s->gpr), &error_abort);
-    sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpr), 0, FSL_IMX6UL_IOMUXC_GPR_ADDR);
-
     /*
      * SDMA
      */
-- 
2.34.1

From: Jean-Christophe Dubois <jcd@tribudubois.net>

* Add Addr and size definition for most i.MX6UL devices in i.MX6UL header file.
* Use those newly defined named constants whenever possible.
* Standardize the way we init a familly of unimplemented devices
  - SAI
  - PWM
  - CAN
* Add/rework few comments

Signed-off-by: Jean-Christophe Dubois <jcd@tribudubois.net>
Message-id: d579043fbd4e4b490370783fda43fc02c8e9be75.1692964892.git.jcd@tribudubois.net
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 include/hw/arm/fsl-imx6ul.h | 156 +++++++++++++++++++++++++++++++-----
 hw/arm/fsl-imx6ul.c         | 147 ++++++++++++++++++++++-----------
 2 files changed, 232 insertions(+), 71 deletions(-)

diff --git a/include/hw/arm/fsl-imx6ul.h b/include/hw/arm/fsl-imx6ul.h
index XXXXXXX..XXXXXXX 100644
--- a/include/hw/arm/fsl-imx6ul.h
+++ b/include/hw/arm/fsl-imx6ul.h
@@ -XXX,XX +XXX,XX @@
 #include "exec/memory.h"
 #include "cpu.h"
 #include "qom/object.h"
+#include "qemu/units.h"
 
 #define TYPE_FSL_IMX6UL "fsl-imx6ul"
 OBJECT_DECLARE_SIMPLE_TYPE(FslIMX6ULState, FSL_IMX6UL)
@@ -XXX,XX +XXX,XX @@ enum FslIMX6ULConfiguration {
     FSL_IMX6UL_NUM_ADCS         = 2,
     FSL_IMX6UL_NUM_USB_PHYS     = 2,
     FSL_IMX6UL_NUM_USBS         = 2,
+    FSL_IMX6UL_NUM_SAIS         = 3,
+    FSL_IMX6UL_NUM_CANS         = 2,
+    FSL_IMX6UL_NUM_PWMS         = 4,
 };
 
 struct FslIMX6ULState {
@@ -XXX,XX +XXX,XX @@ struct FslIMX6ULState {
 
 enum FslIMX6ULMemoryMap {
     FSL_IMX6UL_MMDC_ADDR            = 0x80000000,
-    FSL_IMX6UL_MMDC_SIZE            = 2 * 1024 * 1024 * 1024UL,
+    FSL_IMX6UL_MMDC_SIZE            = (2 * GiB),
 
     FSL_IMX6UL_QSPI1_MEM_ADDR       = 0x60000000,
-    FSL_IMX6UL_EIM_ALIAS_ADDR       = 0x58000000,
-    FSL_IMX6UL_EIM_CS_ADDR          = 0x50000000,
-    FSL_IMX6UL_AES_ENCRYPT_ADDR     = 0x10000000,
-    FSL_IMX6UL_QSPI1_RX_ADDR        = 0x0C000000,
+    FSL_IMX6UL_QSPI1_MEM_SIZE       = (256 * MiB),
 
-    /* AIPS-2 */
+    FSL_IMX6UL_EIM_ALIAS_ADDR       = 0x58000000,
+    FSL_IMX6UL_EIM_ALIAS_SIZE       = (128 * MiB),
+
+    FSL_IMX6UL_EIM_CS_ADDR          = 0x50000000,
+    FSL_IMX6UL_EIM_CS_SIZE          = (128 * MiB),
+
+    FSL_IMX6UL_AES_ENCRYPT_ADDR     = 0x10000000,
+    FSL_IMX6UL_AES_ENCRYPT_SIZE     = (1 * MiB),
+
+    FSL_IMX6UL_QSPI1_RX_ADDR        = 0x0C000000,
+    FSL_IMX6UL_QSPI1_RX_SIZE        = (32 * MiB),
+
+    /* AIPS-2 Begin */
     FSL_IMX6UL_UART6_ADDR           = 0x021FC000,
+
     FSL_IMX6UL_I2C4_ADDR            = 0x021F8000,
+
     FSL_IMX6UL_UART5_ADDR           = 0x021F4000,
     FSL_IMX6UL_UART4_ADDR           = 0x021F0000,
     FSL_IMX6UL_UART3_ADDR           = 0x021EC000,
     FSL_IMX6UL_UART2_ADDR           = 0x021E8000,
+
     FSL_IMX6UL_WDOG3_ADDR           = 0x021E4000,
+
     FSL_IMX6UL_QSPI_ADDR            = 0x021E0000,
+    FSL_IMX6UL_QSPI_SIZE            = 0x500,
+
     FSL_IMX6UL_SYS_CNT_CTRL_ADDR    = 0x021DC000,
+    FSL_IMX6UL_SYS_CNT_CTRL_SIZE    = (16 * KiB),
+
     FSL_IMX6UL_SYS_CNT_CMP_ADDR     = 0x021D8000,
+    FSL_IMX6UL_SYS_CNT_CMP_SIZE     = (16 * KiB),
+
     FSL_IMX6UL_SYS_CNT_RD_ADDR      = 0x021D4000,
+    FSL_IMX6UL_SYS_CNT_RD_SIZE      = (16 * KiB),
+
     FSL_IMX6UL_TZASC_ADDR           = 0x021D0000,
+    FSL_IMX6UL_TZASC_SIZE           = (16 * KiB),
+
     FSL_IMX6UL_PXP_ADDR             = 0x021CC000,
+    FSL_IMX6UL_PXP_SIZE             = (16 * KiB),
+
     FSL_IMX6UL_LCDIF_ADDR           = 0x021C8000,
+    FSL_IMX6UL_LCDIF_SIZE           = 0x100,
+
     FSL_IMX6UL_CSI_ADDR             = 0x021C4000,
+    FSL_IMX6UL_CSI_SIZE             = 0x100,
+
     FSL_IMX6UL_CSU_ADDR             = 0x021C0000,
+    FSL_IMX6UL_CSU_SIZE             = (16 * KiB),
+
     FSL_IMX6UL_OCOTP_CTRL_ADDR      = 0x021BC000,
+    FSL_IMX6UL_OCOTP_CTRL_SIZE      = (4 * KiB),
+
     FSL_IMX6UL_EIM_ADDR             = 0x021B8000,
+    FSL_IMX6UL_EIM_SIZE             = 0x100,
+
     FSL_IMX6UL_SIM2_ADDR            = 0x021B4000,
+
     FSL_IMX6UL_MMDC_CFG_ADDR        = 0x021B0000,
+    FSL_IMX6UL_MMDC_CFG_SIZE        = (4 * KiB),
+
     FSL_IMX6UL_ROMCP_ADDR           = 0x021AC000,
+    FSL_IMX6UL_ROMCP_SIZE           = 0x300,
+
     FSL_IMX6UL_I2C3_ADDR            = 0x021A8000,
     FSL_IMX6UL_I2C2_ADDR            = 0x021A4000,
     FSL_IMX6UL_I2C1_ADDR            = 0x021A0000,
+
     FSL_IMX6UL_ADC2_ADDR            = 0x0219C000,
     FSL_IMX6UL_ADC1_ADDR            = 0x02198000,
+    FSL_IMX6UL_ADCn_SIZE            = 0x100,
+
     FSL_IMX6UL_USDHC2_ADDR          = 0x02194000,
     FSL_IMX6UL_USDHC1_ADDR          = 0x02190000,
-    FSL_IMX6UL_SIM1_ADDR            = 0x0218C000,
-    FSL_IMX6UL_ENET1_ADDR           = 0x02188000,
-    FSL_IMX6UL_USBO2_USBMISC_ADDR   = 0x02184800,
-    FSL_IMX6UL_USBO2_USB_ADDR       = 0x02184000,
-    FSL_IMX6UL_USBO2_PL301_ADDR     = 0x02180000,
-    FSL_IMX6UL_AIPS2_CFG_ADDR       = 0x0217C000,
-    FSL_IMX6UL_CAAM_ADDR            = 0x02140000,
-    FSL_IMX6UL_A7MPCORE_DAP_ADDR    = 0x02100000,
 
-    /* AIPS-1 */
+    FSL_IMX6UL_SIM1_ADDR            = 0x0218C000,
+    FSL_IMX6UL_SIMn_SIZE            = (16 * KiB),
+
+    FSL_IMX6UL_ENET1_ADDR           = 0x02188000,
+
+    FSL_IMX6UL_USBO2_USBMISC_ADDR   = 0x02184800,
+    FSL_IMX6UL_USBO2_USB1_ADDR      = 0x02184000,
+    FSL_IMX6UL_USBO2_USB2_ADDR      = 0x02184200,
+
+    FSL_IMX6UL_USBO2_PL301_ADDR     = 0x02180000,
+    FSL_IMX6UL_USBO2_PL301_SIZE     = (16 * KiB),
+
+    FSL_IMX6UL_AIPS2_CFG_ADDR       = 0x0217C000,
+    FSL_IMX6UL_AIPS2_CFG_SIZE       = 0x100,
+
+    FSL_IMX6UL_CAAM_ADDR            = 0x02140000,
+    FSL_IMX6UL_CAAM_SIZE            = (16 * KiB),
+
+    FSL_IMX6UL_A7MPCORE_DAP_ADDR    = 0x02100000,
+    FSL_IMX6UL_A7MPCORE_DAP_SIZE    = (4 * KiB),
+    /* AIPS-2 End */
+
+    /* AIPS-1 Begin */
     FSL_IMX6UL_PWM8_ADDR            = 0x020FC000,
     FSL_IMX6UL_PWM7_ADDR            = 0x020F8000,
     FSL_IMX6UL_PWM6_ADDR            = 0x020F4000,
     FSL_IMX6UL_PWM5_ADDR            = 0x020F0000,
+
     FSL_IMX6UL_SDMA_ADDR            = 0x020EC000,
+    FSL_IMX6UL_SDMA_SIZE            = 0x300,
+
     FSL_IMX6UL_GPT2_ADDR            = 0x020E8000,
+
     FSL_IMX6UL_IOMUXC_GPR_ADDR      = 0x020E4000,
+    FSL_IMX6UL_IOMUXC_GPR_SIZE      = 0x40,
+
     FSL_IMX6UL_IOMUXC_ADDR          = 0x020E0000,
+    FSL_IMX6UL_IOMUXC_SIZE          = 0x700,
+
     FSL_IMX6UL_GPC_ADDR             = 0x020DC000,
+
     FSL_IMX6UL_SRC_ADDR             = 0x020D8000,
+
     FSL_IMX6UL_EPIT2_ADDR           = 0x020D4000,
     FSL_IMX6UL_EPIT1_ADDR           = 0x020D0000,
+
     FSL_IMX6UL_SNVS_HP_ADDR         = 0x020CC000,
+
     FSL_IMX6UL_USBPHY2_ADDR         = 0x020CA000,
-    FSL_IMX6UL_USBPHY2_SIZE         = (4 * 1024),
     FSL_IMX6UL_USBPHY1_ADDR         = 0x020C9000,
-    FSL_IMX6UL_USBPHY1_SIZE         = (4 * 1024),
+
     FSL_IMX6UL_ANALOG_ADDR          = 0x020C8000,
+    FSL_IMX6UL_ANALOG_SIZE          = 0x300,
+
     FSL_IMX6UL_CCM_ADDR             = 0x020C4000,
+
     FSL_IMX6UL_WDOG2_ADDR           = 0x020C0000,
     FSL_IMX6UL_WDOG1_ADDR           = 0x020BC000,
+
     FSL_IMX6UL_KPP_ADDR             = 0x020B8000,
+    FSL_IMX6UL_KPP_SIZE             = 0x10,
+
     FSL_IMX6UL_ENET2_ADDR           = 0x020B4000,
+
     FSL_IMX6UL_SNVS_LP_ADDR         = 0x020B0000,
+    FSL_IMX6UL_SNVS_LP_SIZE         = (16 * KiB),
+
     FSL_IMX6UL_GPIO5_ADDR           = 0x020AC000,
     FSL_IMX6UL_GPIO4_ADDR           = 0x020A8000,
     FSL_IMX6UL_GPIO3_ADDR           = 0x020A4000,
     FSL_IMX6UL_GPIO2_ADDR           = 0x020A0000,
     FSL_IMX6UL_GPIO1_ADDR           = 0x0209C000,
+
     FSL_IMX6UL_GPT1_ADDR            = 0x02098000,
+
     FSL_IMX6UL_CAN2_ADDR            = 0x02094000,
     FSL_IMX6UL_CAN1_ADDR            = 0x02090000,
+    FSL_IMX6UL_CANn_SIZE            = (4 * KiB),
+
     FSL_IMX6UL_PWM4_ADDR            = 0x0208C000,
     FSL_IMX6UL_PWM3_ADDR            = 0x02088000,
     FSL_IMX6UL_PWM2_ADDR            = 0x02084000,
     FSL_IMX6UL_PWM1_ADDR            = 0x02080000,
+    FSL_IMX6UL_PWMn_SIZE            = 0x20,
+
     FSL_IMX6UL_AIPS1_CFG_ADDR       = 0x0207C000,
+    FSL_IMX6UL_AIPS1_CFG_SIZE       = (16 * KiB),
+
     FSL_IMX6UL_BEE_ADDR             = 0x02044000,
+    FSL_IMX6UL_BEE_SIZE             = (16 * KiB),
+
     FSL_IMX6UL_TOUCH_CTRL_ADDR      = 0x02040000,
+    FSL_IMX6UL_TOUCH_CTRL_SIZE      = 0x100,
+
     FSL_IMX6UL_SPBA_ADDR            = 0x0203C000,
+    FSL_IMX6UL_SPBA_SIZE            = 0x100,
+
     FSL_IMX6UL_ASRC_ADDR            = 0x02034000,
+    FSL_IMX6UL_ASRC_SIZE            = 0x100,
+
     FSL_IMX6UL_SAI3_ADDR            = 0x02030000,
     FSL_IMX6UL_SAI2_ADDR            = 0x0202C000,
     FSL_IMX6UL_SAI1_ADDR            = 0x02028000,
+    FSL_IMX6UL_SAIn_SIZE            = 0x200,
+
     FSL_IMX6UL_UART8_ADDR           = 0x02024000,
     FSL_IMX6UL_UART1_ADDR           = 0x02020000,
     FSL_IMX6UL_UART7_ADDR           = 0x02018000,
+
     FSL_IMX6UL_ECSPI4_ADDR          = 0x02014000,
     FSL_IMX6UL_ECSPI3_ADDR          = 0x02010000,
     FSL_IMX6UL_ECSPI2_ADDR          = 0x0200C000,
     FSL_IMX6UL_ECSPI1_ADDR          = 0x02008000,
+
     FSL_IMX6UL_SPDIF_ADDR           = 0x02004000,
+    FSL_IMX6UL_SPDIF_SIZE           = 0x100,
+    /* AIPS-1 End */
+
+    FSL_IMX6UL_BCH_ADDR             = 0x01808000,
+    FSL_IMX6UL_BCH_SIZE             = 0x200,
+
+    FSL_IMX6UL_GPMI_ADDR            = 0x01806000,
+    FSL_IMX6UL_GPMI_SIZE            = 0x200,
 
     FSL_IMX6UL_APBH_DMA_ADDR        = 0x01804000,
-    FSL_IMX6UL_APBH_DMA_SIZE        = (32 * 1024),
+    FSL_IMX6UL_APBH_DMA_SIZE        = (4 * KiB),
 
     FSL_IMX6UL_A7MPCORE_ADDR        = 0x00A00000,
 
     FSL_IMX6UL_OCRAM_ALIAS_ADDR     = 0x00920000,
-    FSL_IMX6UL_OCRAM_ALIAS_SIZE     = 0x00060000,
+    FSL_IMX6UL_OCRAM_ALIAS_SIZE     = (384 * KiB),
+
     FSL_IMX6UL_OCRAM_MEM_ADDR       = 0x00900000,
-    FSL_IMX6UL_OCRAM_MEM_SIZE       = 0x00020000,
+    FSL_IMX6UL_OCRAM_MEM_SIZE       = (128 * KiB),
+
     FSL_IMX6UL_CAAM_MEM_ADDR        = 0x00100000,
-    FSL_IMX6UL_CAAM_MEM_SIZE        = 0x00008000,
+    FSL_IMX6UL_CAAM_MEM_SIZE        = (32 * KiB),
+
     FSL_IMX6UL_ROM_ADDR             = 0x00000000,
-    FSL_IMX6UL_ROM_SIZE             = 0x00018000,
+    FSL_IMX6UL_ROM_SIZE             = (96 * KiB),
 };
 
 enum FslIMX6ULIRQs {
diff --git a/hw/arm/fsl-imx6ul.c b/hw/arm/fsl-imx6ul.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/fsl-imx6ul.c
+++ b/hw/arm/fsl-imx6ul.c
@@ -XXX,XX +XXX,XX @@ static void fsl_imx6ul_init(Object *obj)
     object_initialize_child(obj, "snvs", &s->snvs, TYPE_IMX7_SNVS);
 
     /*
-     * GPIOs 1 to 5
+     * GPIOs
      */
     for (i = 0; i < FSL_IMX6UL_NUM_GPIOS; i++) {
         snprintf(name, NAME_SIZE, "gpio%d", i);
@@ -XXX,XX +XXX,XX @@ static void fsl_imx6ul_init(Object *obj)
     }
 
     /*
-     * GPT 1, 2
+     * GPTs
      */
     for (i = 0; i < FSL_IMX6UL_NUM_GPTS; i++) {
         snprintf(name, NAME_SIZE, "gpt%d", i);
@@ -XXX,XX +XXX,XX @@ static void fsl_imx6ul_init(Object *obj)
     }
 
     /*
-     * EPIT 1, 2
+     * EPITs
      */
     for (i = 0; i < FSL_IMX6UL_NUM_EPITS; i++) {
         snprintf(name, NAME_SIZE, "epit%d", i + 1);
@@ -XXX,XX +XXX,XX @@ static void fsl_imx6ul_init(Object *obj)
     }
 
     /*
-     * eCSPI
+     * eCSPIs
      */
     for (i = 0; i < FSL_IMX6UL_NUM_ECSPIS; i++) {
         snprintf(name, NAME_SIZE, "spi%d", i + 1);
@@ -XXX,XX +XXX,XX @@ static void fsl_imx6ul_init(Object *obj)
     }
 
     /*
-     * I2C
+     * I2Cs
      */
     for (i = 0; i < FSL_IMX6UL_NUM_I2CS; i++) {
         snprintf(name, NAME_SIZE, "i2c%d", i + 1);
@@ -XXX,XX +XXX,XX @@ static void fsl_imx6ul_init(Object *obj)
     }
 
     /*
-     * UART
+     * UARTs
      */
     for (i = 0; i < FSL_IMX6UL_NUM_UARTS; i++) {
         snprintf(name, NAME_SIZE, "uart%d", i);
@@ -XXX,XX +XXX,XX @@ static void fsl_imx6ul_init(Object *obj)
     }
 
     /*
-     * Ethernet
+     * Ethernets
      */
     for (i = 0; i < FSL_IMX6UL_NUM_ETHS; i++) {
         snprintf(name, NAME_SIZE, "eth%d", i);
         object_initialize_child(obj, name, &s->eth[i], TYPE_IMX_ENET);
     }
 
-    /* USB */
+    /*
+     * USB PHYs
+     */
     for (i = 0; i < FSL_IMX6UL_NUM_USB_PHYS; i++) {
         snprintf(name, NAME_SIZE, "usbphy%d", i);
         object_initialize_child(obj, name, &s->usbphy[i], TYPE_IMX_USBPHY);
     }
+
+    /*
+     * USBs
+     */
     for (i = 0; i < FSL_IMX6UL_NUM_USBS; i++) {
         snprintf(name, NAME_SIZE, "usb%d", i);
         object_initialize_child(obj, name, &s->usb[i], TYPE_CHIPIDEA);
     }
 
     /*
-     * SDHCI
+     * SDHCIs
      */
     for (i = 0; i < FSL_IMX6UL_NUM_USDHCS; i++) {
         snprintf(name, NAME_SIZE, "usdhc%d", i);
@@ -XXX,XX +XXX,XX @@ static void fsl_imx6ul_init(Object *obj)
     }
 
     /*
-     * Watchdog
+     * Watchdogs
      */
     for (i = 0; i < FSL_IMX6UL_NUM_WDTS; i++) {
         snprintf(name, NAME_SIZE, "wdt%d", i);
@@ -XXX,XX +XXX,XX @@ static void fsl_imx6ul_realize(DeviceState *dev, Error **errp)
      * A7MPCORE DAP
      */
     create_unimplemented_device("a7mpcore-dap", FSL_IMX6UL_A7MPCORE_DAP_ADDR,
-                                0x100000);
+                                FSL_IMX6UL_A7MPCORE_DAP_SIZE);
 
     /*
-     * GPT 1, 2
+     * GPTs
      */
     for (i = 0; i < FSL_IMX6UL_NUM_GPTS; i++) {
         static const hwaddr FSL_IMX6UL_GPTn_ADDR[FSL_IMX6UL_NUM_GPTS] = {
@@ -XXX,XX +XXX,XX @@ static void fsl_imx6ul_realize(DeviceState *dev, Error **errp)
     }
 
     /*
-     * EPIT 1, 2
+     * EPITs
      */
     for (i = 0; i < FSL_IMX6UL_NUM_EPITS; i++) {
         static const hwaddr FSL_IMX6UL_EPITn_ADDR[FSL_IMX6UL_NUM_EPITS] = {
@@ -XXX,XX +XXX,XX @@ static void fsl_imx6ul_realize(DeviceState *dev, Error **errp)
     }
 
     /*
-     * GPIO
+     * GPIOs
      */
     for (i = 0; i < FSL_IMX6UL_NUM_GPIOS; i++) {
         static const hwaddr FSL_IMX6UL_GPIOn_ADDR[FSL_IMX6UL_NUM_GPIOS] = {
@@ -XXX,XX +XXX,XX @@ static void fsl_imx6ul_realize(DeviceState *dev, Error **errp)
     }
 
     /*
-     * IOMUXC and IOMUXC_GPR
+     * IOMUXC
      */
-    for (i = 0; i < 1; i++) {
-        static const hwaddr FSL_IMX6UL_IOMUXCn_ADDR[FSL_IMX6UL_NUM_IOMUXCS] = {
-            FSL_IMX6UL_IOMUXC_ADDR,
-            FSL_IMX6UL_IOMUXC_GPR_ADDR,
-        };
-
-        snprintf(name, NAME_SIZE, "iomuxc%d", i);
-        create_unimplemented_device(name, FSL_IMX6UL_IOMUXCn_ADDR[i], 0x4000);
-    }
+    create_unimplemented_device("iomuxc", FSL_IMX6UL_IOMUXC_ADDR,
+                                FSL_IMX6UL_IOMUXC_SIZE);
+    create_unimplemented_device("iomuxc_gpr", FSL_IMX6UL_IOMUXC_GPR_ADDR,
+                                FSL_IMX6UL_IOMUXC_GPR_SIZE);
 
     /*
      * CCM
@@ -XXX,XX +XXX,XX @@ static void fsl_imx6ul_realize(DeviceState *dev, Error **errp)
     sysbus_realize(SYS_BUS_DEVICE(&s->gpcv2), &error_abort);
     sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpcv2), 0, FSL_IMX6UL_GPC_ADDR);
 
-    /* Initialize all ECSPI */
+    /*
+     * ECSPIs
+     */
     for (i = 0; i < FSL_IMX6UL_NUM_ECSPIS; i++) {
         static const hwaddr FSL_IMX6UL_SPIn_ADDR[FSL_IMX6UL_NUM_ECSPIS] = {
             FSL_IMX6UL_ECSPI1_ADDR,
@@ -XXX,XX +XXX,XX @@ static void fsl_imx6ul_realize(DeviceState *dev, Error **errp)
     }
 
     /*
-     * I2C
+     * I2Cs
      */
     for (i = 0; i < FSL_IMX6UL_NUM_I2CS; i++) {
         static const hwaddr FSL_IMX6UL_I2Cn_ADDR[FSL_IMX6UL_NUM_I2CS] = {
@@ -XXX,XX +XXX,XX @@ static void fsl_imx6ul_realize(DeviceState *dev, Error **errp)
     }
 
     /*
-     * UART
+     * UARTs
      */
     for (i = 0; i < FSL_IMX6UL_NUM_UARTS; i++) {
         static const hwaddr FSL_IMX6UL_UARTn_ADDR[FSL_IMX6UL_NUM_UARTS] = {
@@ -XXX,XX +XXX,XX @@ static void fsl_imx6ul_realize(DeviceState *dev, Error **errp)
     }
 
     /*
-     * Ethernet
+     * Ethernets
      *
      * We must use two loops since phy_connected affects the other interface
      * and we have to set all properties before calling sysbus_realize().
@@ -XXX,XX +XXX,XX @@ static void fsl_imx6ul_realize(DeviceState *dev, Error **errp)
                                             FSL_IMX6UL_ENETn_TIMER_IRQ[i]));
     }
 
-    /* USB */
+    /*
+     * USB PHYs
+     */
     for (i = 0; i < FSL_IMX6UL_NUM_USB_PHYS; i++) {
+        static const hwaddr
+                     FSL_IMX6UL_USB_PHYn_ADDR[FSL_IMX6UL_NUM_USB_PHYS] = {
+            FSL_IMX6UL_USBPHY1_ADDR,
+            FSL_IMX6UL_USBPHY2_ADDR,
+        };
+
         sysbus_realize(SYS_BUS_DEVICE(&s->usbphy[i]), &error_abort);
         sysbus_mmio_map(SYS_BUS_DEVICE(&s->usbphy[i]), 0,
-                        FSL_IMX6UL_USBPHY1_ADDR + i * 0x1000);
+                        FSL_IMX6UL_USB_PHYn_ADDR[i]);
     }
 
+    /*
+     * USBs
+     */
     for (i = 0; i < FSL_IMX6UL_NUM_USBS; i++) {
+        static const hwaddr FSL_IMX6UL_USB02_USBn_ADDR[FSL_IMX6UL_NUM_USBS] = {
+            FSL_IMX6UL_USBO2_USB1_ADDR,
+            FSL_IMX6UL_USBO2_USB2_ADDR,
+        };
+
         static const int FSL_IMX6UL_USBn_IRQ[] = {
             FSL_IMX6UL_USB1_IRQ,
             FSL_IMX6UL_USB2_IRQ,
         };
+
         sysbus_realize(SYS_BUS_DEVICE(&s->usb[i]), &error_abort);
         sysbus_mmio_map(SYS_BUS_DEVICE(&s->usb[i]), 0,
-                        FSL_IMX6UL_USBO2_USB_ADDR + i * 0x200);
+                        FSL_IMX6UL_USB02_USBn_ADDR[i]);
         sysbus_connect_irq(SYS_BUS_DEVICE(&s->usb[i]), 0,
                            qdev_get_gpio_in(DEVICE(&s->a7mpcore),
                                             FSL_IMX6UL_USBn_IRQ[i]));
     }
 
     /*
-     * USDHC
+     * USDHCs
      */
     for (i = 0; i < FSL_IMX6UL_NUM_USDHCS; i++) {
         static const hwaddr FSL_IMX6UL_USDHCn_ADDR[FSL_IMX6UL_NUM_USDHCS] = {
@@ -XXX,XX +XXX,XX @@ static void fsl_imx6ul_realize(DeviceState *dev, Error **errp)
     sysbus_mmio_map(SYS_BUS_DEVICE(&s->snvs), 0, FSL_IMX6UL_SNVS_HP_ADDR);
 
     /*
-     * Watchdog
+     * Watchdogs
      */
     for (i = 0; i < FSL_IMX6UL_NUM_WDTS; i++) {
         static const hwaddr FSL_IMX6UL_WDOGn_ADDR[FSL_IMX6UL_NUM_WDTS] = {
@@ -XXX,XX +XXX,XX @@ static void fsl_imx6ul_realize(DeviceState *dev, Error **errp)
             FSL_IMX6UL_WDOG2_ADDR,
             FSL_IMX6UL_WDOG3_ADDR,
         };
+
         static const int FSL_IMX6UL_WDOGn_IRQ[FSL_IMX6UL_NUM_WDTS] = {
             FSL_IMX6UL_WDOG1_IRQ,
             FSL_IMX6UL_WDOG2_IRQ,
@@ -XXX,XX +XXX,XX @@ static void fsl_imx6ul_realize(DeviceState *dev, Error **errp)
     /*
      * SDMA
      */
-    create_unimplemented_device("sdma", FSL_IMX6UL_SDMA_ADDR, 0x4000);
+    create_unimplemented_device("sdma", FSL_IMX6UL_SDMA_ADDR,
+                                FSL_IMX6UL_SDMA_SIZE);
 
     /*
-     * SAI (Audio SSI (Synchronous Serial Interface))
+     * SAIs (Audio SSI (Synchronous Serial Interface))
      */
-    create_unimplemented_device("sai1", FSL_IMX6UL_SAI1_ADDR, 0x4000);
-    create_unimplemented_device("sai2", FSL_IMX6UL_SAI2_ADDR, 0x4000);
-    create_unimplemented_device("sai3", FSL_IMX6UL_SAI3_ADDR, 0x4000);
+    for (i = 0; i < FSL_IMX6UL_NUM_SAIS; i++) {
+        static const hwaddr FSL_IMX6UL_SAIn_ADDR[FSL_IMX6UL_NUM_SAIS] = {
+            FSL_IMX6UL_SAI1_ADDR,
+            FSL_IMX6UL_SAI2_ADDR,
+            FSL_IMX6UL_SAI3_ADDR,
+        };
+
+        snprintf(name, NAME_SIZE, "sai%d", i);
+        create_unimplemented_device(name, FSL_IMX6UL_SAIn_ADDR[i],
+                                    FSL_IMX6UL_SAIn_SIZE);
+    }
 
     /*
-     * PWM
+     * PWMs
      */
-    create_unimplemented_device("pwm1", FSL_IMX6UL_PWM1_ADDR, 0x4000);
-    create_unimplemented_device("pwm2", FSL_IMX6UL_PWM2_ADDR, 0x4000);
-    create_unimplemented_device("pwm3", FSL_IMX6UL_PWM3_ADDR, 0x4000);
-    create_unimplemented_device("pwm4", FSL_IMX6UL_PWM4_ADDR, 0x4000);
+    for (i = 0; i < FSL_IMX6UL_NUM_PWMS; i++) {
+        static const hwaddr FSL_IMX6UL_PWMn_ADDR[FSL_IMX6UL_NUM_PWMS] = {
+            FSL_IMX6UL_PWM1_ADDR,
+            FSL_IMX6UL_PWM2_ADDR,
+            FSL_IMX6UL_PWM3_ADDR,
+            FSL_IMX6UL_PWM4_ADDR,
+        };
+
+        snprintf(name, NAME_SIZE, "pwm%d", i);
+        create_unimplemented_device(name, FSL_IMX6UL_PWMn_ADDR[i],
+                                    FSL_IMX6UL_PWMn_SIZE);
+    }
 
     /*
      * Audio ASRC (asynchronous sample rate converter)
      */
-    create_unimplemented_device("asrc", FSL_IMX6UL_ASRC_ADDR, 0x4000);
+    create_unimplemented_device("asrc", FSL_IMX6UL_ASRC_ADDR,
+                                FSL_IMX6UL_ASRC_SIZE);
 
     /*
-     * CAN
+     * CANs
      */
-    create_unimplemented_device("can1", FSL_IMX6UL_CAN1_ADDR, 0x4000);
-    create_unimplemented_device("can2", FSL_IMX6UL_CAN2_ADDR, 0x4000);
+    for (i = 0; i < FSL_IMX6UL_NUM_CANS; i++) {
+        static const hwaddr FSL_IMX6UL_CANn_ADDR[FSL_IMX6UL_NUM_CANS] = {
+            FSL_IMX6UL_CAN1_ADDR,
+            FSL_IMX6UL_CAN2_ADDR,
+        };
+
+        snprintf(name, NAME_SIZE, "can%d", i);
+        create_unimplemented_device(name, FSL_IMX6UL_CANn_ADDR[i],
+                                    FSL_IMX6UL_CANn_SIZE);
+    }
 
     /*
      * APHB_DMA
@@ -XXX,XX +XXX,XX @@ static void fsl_imx6ul_realize(DeviceState *dev, Error **errp)
         };
 
         snprintf(name, NAME_SIZE, "adc%d", i);
-        create_unimplemented_device(name, FSL_IMX6UL_ADCn_ADDR[i], 0x4000);
+        create_unimplemented_device(name, FSL_IMX6UL_ADCn_ADDR[i],
+                                    FSL_IMX6UL_ADCn_SIZE);
     }
 
     /*
      * LCD
      */
-    create_unimplemented_device("lcdif", FSL_IMX6UL_LCDIF_ADDR, 0x4000);
+    create_unimplemented_device("lcdif", FSL_IMX6UL_LCDIF_ADDR,
+                                FSL_IMX6UL_LCDIF_SIZE);
 
     /*
      * ROM memory
-- 
2.34.1

From: Jean-Christophe Dubois <jcd@tribudubois.net>

* Add TZASC as unimplemented device.
  - Allow bare metal application to access this (unimplemented) device
* Add CSU as unimplemented device.
  - Allow bare metal application to access this (unimplemented) device
* Add 4 missing PWM devices

Signed-off-by: Jean-Christophe Dubois <jcd@tribudubois.net>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-id: 59e4dc56e14eccfefd379275ec19048dff9c10b3.1692964892.git.jcd@tribudubois.net
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 include/hw/arm/fsl-imx6ul.h |  2 +-
 hw/arm/fsl-imx6ul.c         | 16 ++++++++++++++++
 2 files changed, 17 insertions(+), 1 deletion(-)

diff --git a/include/hw/arm/fsl-imx6ul.h b/include/hw/arm/fsl-imx6ul.h
index XXXXXXX..XXXXXXX 100644
--- a/include/hw/arm/fsl-imx6ul.h
+++ b/include/hw/arm/fsl-imx6ul.h
@@ -XXX,XX +XXX,XX @@ enum FslIMX6ULConfiguration {
     FSL_IMX6UL_NUM_USBS         = 2,
     FSL_IMX6UL_NUM_SAIS         = 3,
     FSL_IMX6UL_NUM_CANS         = 2,
-    FSL_IMX6UL_NUM_PWMS         = 4,
+    FSL_IMX6UL_NUM_PWMS         = 8,
 };
 
 struct FslIMX6ULState {
diff --git a/hw/arm/fsl-imx6ul.c b/hw/arm/fsl-imx6ul.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/fsl-imx6ul.c
+++ b/hw/arm/fsl-imx6ul.c
@@ -XXX,XX +XXX,XX @@ static void fsl_imx6ul_realize(DeviceState *dev, Error **errp)
             FSL_IMX6UL_PWM2_ADDR,
             FSL_IMX6UL_PWM3_ADDR,
             FSL_IMX6UL_PWM4_ADDR,
+            FSL_IMX6UL_PWM5_ADDR,
+            FSL_IMX6UL_PWM6_ADDR,
+            FSL_IMX6UL_PWM7_ADDR,
+            FSL_IMX6UL_PWM8_ADDR,
         };
 
         snprintf(name, NAME_SIZE, "pwm%d", i);
@@ -XXX,XX +XXX,XX @@ static void fsl_imx6ul_realize(DeviceState *dev, Error **errp)
     create_unimplemented_device("lcdif", FSL_IMX6UL_LCDIF_ADDR,
                                 FSL_IMX6UL_LCDIF_SIZE);
 
+    /*
+     * CSU
+     */
+    create_unimplemented_device("csu", FSL_IMX6UL_CSU_ADDR,
+                                FSL_IMX6UL_CSU_SIZE);
+
+    /*
+     * TZASC
+     */
+    create_unimplemented_device("tzasc", FSL_IMX6UL_TZASC_ADDR,
+                                FSL_IMX6UL_TZASC_SIZE);
+
     /*
      * ROM memory
      */
-- 
2.34.1

From: Jean-Christophe Dubois <jcd@tribudubois.net>

* Add Addr and size definition for all i.MX7 devices in i.MX7 header file.
* Use those newly defined named constants whenever possible.
* Standardize the way we init a familly of unimplemented devices
  - SAI
  - PWM
  - CAN
* Add/rework few comments

Signed-off-by: Jean-Christophe Dubois <jcd@tribudubois.net>
Message-id: 59e195d33e4d486a8d131392acd46633c8c10ed7.1692964892.git.jcd@tribudubois.net
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 include/hw/arm/fsl-imx7.h | 330 ++++++++++++++++++++++++++++----------
 hw/arm/fsl-imx7.c         | 130 ++++++++++-----
 2 files changed, 335 insertions(+), 125 deletions(-)

diff --git a/include/hw/arm/fsl-imx7.h b/include/hw/arm/fsl-imx7.h
index XXXXXXX..XXXXXXX 100644
--- a/include/hw/arm/fsl-imx7.h
+++ b/include/hw/arm/fsl-imx7.h
@@ -XXX,XX +XXX,XX @@
 #include "hw/misc/imx7_ccm.h"
 #include "hw/misc/imx7_snvs.h"
 #include "hw/misc/imx7_gpr.h"
-#include "hw/misc/imx6_src.h"
 #include "hw/watchdog/wdt_imx2.h"
 #include "hw/gpio/imx_gpio.h"
 #include "hw/char/imx_serial.h"
@@ -XXX,XX +XXX,XX @@
 #include "hw/usb/chipidea.h"
 #include "cpu.h"
 #include "qom/object.h"
+#include "qemu/units.h"
 
 #define TYPE_FSL_IMX7 "fsl-imx7"
 OBJECT_DECLARE_SIMPLE_TYPE(FslIMX7State, FSL_IMX7)
@@ -XXX,XX +XXX,XX @@ enum FslIMX7Configuration {
     FSL_IMX7_NUM_ECSPIS       = 4,
     FSL_IMX7_NUM_USBS         = 3,
     FSL_IMX7_NUM_ADCS         = 2,
+    FSL_IMX7_NUM_SAIS         = 3,
+    FSL_IMX7_NUM_CANS         = 2,
+    FSL_IMX7_NUM_PWMS         = 4,
 };
 
 struct FslIMX7State {
@@ -XXX,XX +XXX,XX @@ struct FslIMX7State {
 
 enum FslIMX7MemoryMap {
     FSL_IMX7_MMDC_ADDR            = 0x80000000,
-    FSL_IMX7_MMDC_SIZE            = 2 * 1024 * 1024 * 1024UL,
+    FSL_IMX7_MMDC_SIZE            = (2 * GiB),
 
-    FSL_IMX7_GPIO1_ADDR           = 0x30200000,
-    FSL_IMX7_GPIO2_ADDR           = 0x30210000,
-    FSL_IMX7_GPIO3_ADDR           = 0x30220000,
-    FSL_IMX7_GPIO4_ADDR           = 0x30230000,
-    FSL_IMX7_GPIO5_ADDR           = 0x30240000,
-    FSL_IMX7_GPIO6_ADDR           = 0x30250000,
-    FSL_IMX7_GPIO7_ADDR           = 0x30260000,
+    FSL_IMX7_QSPI1_MEM_ADDR       = 0x60000000,
+    FSL_IMX7_QSPI1_MEM_SIZE       = (256 * MiB),
 
-    FSL_IMX7_IOMUXC_LPSR_GPR_ADDR = 0x30270000,
+    FSL_IMX7_PCIE1_MEM_ADDR       = 0x40000000,
+    FSL_IMX7_PCIE1_MEM_SIZE       = (256 * MiB),
 
-    FSL_IMX7_WDOG1_ADDR           = 0x30280000,
-    FSL_IMX7_WDOG2_ADDR           = 0x30290000,
-    FSL_IMX7_WDOG3_ADDR           = 0x302A0000,
-    FSL_IMX7_WDOG4_ADDR           = 0x302B0000,
+    FSL_IMX7_QSPI1_RX_BUF_ADDR    = 0x34000000,
+    FSL_IMX7_QSPI1_RX_BUF_SIZE    = (32 * MiB),
 
-    FSL_IMX7_IOMUXC_LPSR_ADDR     = 0x302C0000,
+    /* PCIe Peripherals */
+    FSL_IMX7_PCIE_REG_ADDR        = 0x33800000,
 
-    FSL_IMX7_GPT1_ADDR            = 0x302D0000,
-    FSL_IMX7_GPT2_ADDR            = 0x302E0000,
-    FSL_IMX7_GPT3_ADDR            = 0x302F0000,
-    FSL_IMX7_GPT4_ADDR            = 0x30300000,
+    /* MMAP Peripherals */
+    FSL_IMX7_DMA_APBH_ADDR        = 0x33000000,
+    FSL_IMX7_DMA_APBH_SIZE        = 0x8000,
 
-    FSL_IMX7_IOMUXC_ADDR          = 0x30330000,
-    FSL_IMX7_IOMUXC_GPR_ADDR      = 0x30340000,
-    FSL_IMX7_IOMUXCn_SIZE         = 0x1000,
+    /* GPV configuration */
+    FSL_IMX7_GPV6_ADDR            = 0x32600000,
+    FSL_IMX7_GPV5_ADDR            = 0x32500000,
+    FSL_IMX7_GPV4_ADDR            = 0x32400000,
+    FSL_IMX7_GPV3_ADDR            = 0x32300000,
+    FSL_IMX7_GPV2_ADDR            = 0x32200000,
+    FSL_IMX7_GPV1_ADDR            = 0x32100000,
+    FSL_IMX7_GPV0_ADDR            = 0x32000000,
+    FSL_IMX7_GPVn_SIZE            = (1 * MiB),
 
-    FSL_IMX7_OCOTP_ADDR           = 0x30350000,
-    FSL_IMX7_OCOTP_SIZE           = 0x10000,
+    /* Arm Peripherals */
+    FSL_IMX7_A7MPCORE_ADDR        = 0x31000000,
 
-    FSL_IMX7_ANALOG_ADDR          = 0x30360000,
-    FSL_IMX7_SNVS_ADDR            = 0x30370000,
-    FSL_IMX7_CCM_ADDR             = 0x30380000,
+    /* AIPS-3 Begin */
 
-    FSL_IMX7_SRC_ADDR             = 0x30390000,
-    FSL_IMX7_SRC_SIZE             = 0x1000,
+    FSL_IMX7_ENET2_ADDR           = 0x30BF0000,
+    FSL_IMX7_ENET1_ADDR           = 0x30BE0000,
 
-    FSL_IMX7_ADC1_ADDR            = 0x30610000,
-    FSL_IMX7_ADC2_ADDR            = 0x30620000,
-    FSL_IMX7_ADCn_SIZE            = 0x1000,
+    FSL_IMX7_SDMA_ADDR            = 0x30BD0000,
+    FSL_IMX7_SDMA_SIZE            = (4 * KiB),
 
-    FSL_IMX7_PWM1_ADDR            = 0x30660000,
-    FSL_IMX7_PWM2_ADDR            = 0x30670000,
-    FSL_IMX7_PWM3_ADDR            = 0x30680000,
-    FSL_IMX7_PWM4_ADDR            = 0x30690000,
-    FSL_IMX7_PWMn_SIZE            = 0x10000,
+    FSL_IMX7_EIM_ADDR             = 0x30BC0000,
+    FSL_IMX7_EIM_SIZE             = (4 * KiB),
 
-    FSL_IMX7_PCIE_PHY_ADDR        = 0x306D0000,
-    FSL_IMX7_PCIE_PHY_SIZE        = 0x10000,
+    FSL_IMX7_QSPI_ADDR            = 0x30BB0000,
+    FSL_IMX7_QSPI_SIZE            = 0x8000,
 
-    FSL_IMX7_GPC_ADDR             = 0x303A0000,
+    FSL_IMX7_SIM2_ADDR            = 0x30BA0000,
+    FSL_IMX7_SIM1_ADDR            = 0x30B90000,
+    FSL_IMX7_SIMn_SIZE            = (4 * KiB),
+
+    FSL_IMX7_USDHC3_ADDR          = 0x30B60000,
+    FSL_IMX7_USDHC2_ADDR          = 0x30B50000,
+    FSL_IMX7_USDHC1_ADDR          = 0x30B40000,
+
+    FSL_IMX7_USB3_ADDR            = 0x30B30000,
+    FSL_IMX7_USBMISC3_ADDR        = 0x30B30200,
+    FSL_IMX7_USB2_ADDR            = 0x30B20000,
+    FSL_IMX7_USBMISC2_ADDR        = 0x30B20200,
+    FSL_IMX7_USB1_ADDR            = 0x30B10000,
+    FSL_IMX7_USBMISC1_ADDR        = 0x30B10200,
+    FSL_IMX7_USBMISCn_SIZE        = 0x200,
+
+    FSL_IMX7_USB_PL301_ADDR       = 0x30AD0000,
+    FSL_IMX7_USB_PL301_SIZE       = (64 * KiB),
+
+    FSL_IMX7_SEMAPHORE_HS_ADDR    = 0x30AC0000,
+    FSL_IMX7_SEMAPHORE_HS_SIZE    = (64 * KiB),
+
+    FSL_IMX7_MUB_ADDR             = 0x30AB0000,
+    FSL_IMX7_MUA_ADDR             = 0x30AA0000,
+    FSL_IMX7_MUn_SIZE             = (KiB),
+
+    FSL_IMX7_UART7_ADDR           = 0x30A90000,
+    FSL_IMX7_UART6_ADDR           = 0x30A80000,
+    FSL_IMX7_UART5_ADDR           = 0x30A70000,
+    FSL_IMX7_UART4_ADDR           = 0x30A60000,
+
+    FSL_IMX7_I2C4_ADDR            = 0x30A50000,
+    FSL_IMX7_I2C3_ADDR            = 0x30A40000,
+    FSL_IMX7_I2C2_ADDR            = 0x30A30000,
+    FSL_IMX7_I2C1_ADDR            = 0x30A20000,
+
+    FSL_IMX7_CAN2_ADDR            = 0x30A10000,
+    FSL_IMX7_CAN1_ADDR            = 0x30A00000,
+    FSL_IMX7_CANn_SIZE            = (4 * KiB),
+
+    FSL_IMX7_AIPS3_CONF_ADDR      = 0x309F0000,
+    FSL_IMX7_AIPS3_CONF_SIZE      = (64 * KiB),
 
     FSL_IMX7_CAAM_ADDR            = 0x30900000,
-    FSL_IMX7_CAAM_SIZE            = 0x40000,
+    FSL_IMX7_CAAM_SIZE            = (256 * KiB),
 
-    FSL_IMX7_CAN1_ADDR            = 0x30A00000,
-    FSL_IMX7_CAN2_ADDR            = 0x30A10000,
-    FSL_IMX7_CANn_SIZE            = 0x10000,
+    FSL_IMX7_SPBA_ADDR            = 0x308F0000,
+    FSL_IMX7_SPBA_SIZE            = (4 * KiB),
 
-    FSL_IMX7_I2C1_ADDR            = 0x30A20000,
-    FSL_IMX7_I2C2_ADDR            = 0x30A30000,
-    FSL_IMX7_I2C3_ADDR            = 0x30A40000,
-    FSL_IMX7_I2C4_ADDR            = 0x30A50000,
+    FSL_IMX7_SAI3_ADDR            = 0x308C0000,
+    FSL_IMX7_SAI2_ADDR            = 0x308B0000,
+    FSL_IMX7_SAI1_ADDR            = 0x308A0000,
+    FSL_IMX7_SAIn_SIZE            = (4 * KiB),
 
-    FSL_IMX7_ECSPI1_ADDR          = 0x30820000,
-    FSL_IMX7_ECSPI2_ADDR          = 0x30830000,
-    FSL_IMX7_ECSPI3_ADDR          = 0x30840000,
-    FSL_IMX7_ECSPI4_ADDR          = 0x30630000,
-
-    FSL_IMX7_LCDIF_ADDR           = 0x30730000,
-    FSL_IMX7_LCDIF_SIZE           = 0x1000,
-
-    FSL_IMX7_UART1_ADDR           = 0x30860000,
+    FSL_IMX7_UART3_ADDR           = 0x30880000,
     /*
      * Some versions of the reference manual claim that UART2 is @
      * 0x30870000, but experiments with HW + DT files in upstream
@@ -XXX,XX +XXX,XX @@ enum FslIMX7MemoryMap {
      * actually located @ 0x30890000
      */
     FSL_IMX7_UART2_ADDR           = 0x30890000,
-    FSL_IMX7_UART3_ADDR           = 0x30880000,
-    FSL_IMX7_UART4_ADDR           = 0x30A60000,
-    FSL_IMX7_UART5_ADDR           = 0x30A70000,
-    FSL_IMX7_UART6_ADDR           = 0x30A80000,
-    FSL_IMX7_UART7_ADDR           = 0x30A90000,
+    FSL_IMX7_UART1_ADDR           = 0x30860000,
 
-    FSL_IMX7_SAI1_ADDR            = 0x308A0000,
-    FSL_IMX7_SAI2_ADDR            = 0x308B0000,
-    FSL_IMX7_SAI3_ADDR            = 0x308C0000,
-    FSL_IMX7_SAIn_SIZE            = 0x10000,
+    FSL_IMX7_ECSPI3_ADDR          = 0x30840000,
+    FSL_IMX7_ECSPI2_ADDR          = 0x30830000,
+    FSL_IMX7_ECSPI1_ADDR          = 0x30820000,
+    FSL_IMX7_ECSPIn_SIZE          = (4 * KiB),
 
-    FSL_IMX7_ENET1_ADDR           = 0x30BE0000,
-    FSL_IMX7_ENET2_ADDR           = 0x30BF0000,
+    /* AIPS-3 End */
 
-    FSL_IMX7_USB1_ADDR            = 0x30B10000,
-    FSL_IMX7_USBMISC1_ADDR        = 0x30B10200,
-    FSL_IMX7_USB2_ADDR            = 0x30B20000,
-    FSL_IMX7_USBMISC2_ADDR        = 0x30B20200,
-    FSL_IMX7_USB3_ADDR            = 0x30B30000,
-    FSL_IMX7_USBMISC3_ADDR        = 0x30B30200,
-    FSL_IMX7_USBMISCn_SIZE        = 0x200,
+    /* AIPS-2 Begin */
 
-    FSL_IMX7_USDHC1_ADDR          = 0x30B40000,
-    FSL_IMX7_USDHC2_ADDR          = 0x30B50000,
-    FSL_IMX7_USDHC3_ADDR          = 0x30B60000,
+    FSL_IMX7_AXI_DEBUG_MON_ADDR   = 0x307E0000,
+    FSL_IMX7_AXI_DEBUG_MON_SIZE   = (64 * KiB),
 
-    FSL_IMX7_SDMA_ADDR            = 0x30BD0000,
-    FSL_IMX7_SDMA_SIZE            = 0x1000,
+    FSL_IMX7_PERFMON2_ADDR        = 0x307D0000,
+    FSL_IMX7_PERFMON1_ADDR        = 0x307C0000,
+    FSL_IMX7_PERFMONn_SIZE        = (64 * KiB),
+
+    FSL_IMX7_DDRC_ADDR            = 0x307A0000,
+    FSL_IMX7_DDRC_SIZE            = (4 * KiB),
+
+    FSL_IMX7_DDRC_PHY_ADDR        = 0x30790000,
+    FSL_IMX7_DDRC_PHY_SIZE        = (4 * KiB),
+
+    FSL_IMX7_TZASC_ADDR           = 0x30780000,
+    FSL_IMX7_TZASC_SIZE           = (64 * KiB),
+
+    FSL_IMX7_MIPI_DSI_ADDR        = 0x30760000,
+    FSL_IMX7_MIPI_DSI_SIZE        = (4 * KiB),
+
+    FSL_IMX7_MIPI_CSI_ADDR        = 0x30750000,
+    FSL_IMX7_MIPI_CSI_SIZE        = 0x4000,
+
+    FSL_IMX7_LCDIF_ADDR           = 0x30730000,
+    FSL_IMX7_LCDIF_SIZE           = 0x8000,
+
+    FSL_IMX7_CSI_ADDR             = 0x30710000,
+    FSL_IMX7_CSI_SIZE             = (4 * KiB),
+
+    FSL_IMX7_PXP_ADDR             = 0x30700000,
+    FSL_IMX7_PXP_SIZE             = 0x4000,
+
+    FSL_IMX7_EPDC_ADDR            = 0x306F0000,
+    FSL_IMX7_EPDC_SIZE            = (4 * KiB),
+
+    FSL_IMX7_PCIE_PHY_ADDR        = 0x306D0000,
+    FSL_IMX7_PCIE_PHY_SIZE        = (4 * KiB),
+
+    FSL_IMX7_SYSCNT_CTRL_ADDR     = 0x306C0000,
+    FSL_IMX7_SYSCNT_CMP_ADDR      = 0x306B0000,
+    FSL_IMX7_SYSCNT_RD_ADDR       = 0x306A0000,
+
+    FSL_IMX7_PWM4_ADDR            = 0x30690000,
+    FSL_IMX7_PWM3_ADDR            = 0x30680000,
+    FSL_IMX7_PWM2_ADDR            = 0x30670000,
+    FSL_IMX7_PWM1_ADDR            = 0x30660000,
+    FSL_IMX7_PWMn_SIZE            = (4 * KiB),
+
+    FSL_IMX7_FlEXTIMER2_ADDR      = 0x30650000,
+    FSL_IMX7_FlEXTIMER1_ADDR      = 0x30640000,
+    FSL_IMX7_FLEXTIMERn_SIZE      = (4 * KiB),
+
+    FSL_IMX7_ECSPI4_ADDR          = 0x30630000,
+
+    FSL_IMX7_ADC2_ADDR            = 0x30620000,
+    FSL_IMX7_ADC1_ADDR            = 0x30610000,
+    FSL_IMX7_ADCn_SIZE            = (4 * KiB),
+
+    FSL_IMX7_AIPS2_CONF_ADDR      = 0x305F0000,
+    FSL_IMX7_AIPS2_CONF_SIZE      = (64 * KiB),
+
+    /* AIPS-2 End */
+
+    /* AIPS-1 Begin */
+
+    FSL_IMX7_CSU_ADDR             = 0x303E0000,
+    FSL_IMX7_CSU_SIZE             = (64 * KiB),
+
+    FSL_IMX7_RDC_ADDR             = 0x303D0000,
+    FSL_IMX7_RDC_SIZE             = (4 * KiB),
+
+    FSL_IMX7_SEMAPHORE2_ADDR      = 0x303C0000,
+    FSL_IMX7_SEMAPHORE1_ADDR      = 0x303B0000,
+    FSL_IMX7_SEMAPHOREn_SIZE      = (4 * KiB),
+
+    FSL_IMX7_GPC_ADDR             = 0x303A0000,
+
+    FSL_IMX7_SRC_ADDR             = 0x30390000,
+    FSL_IMX7_SRC_SIZE             = (4 * KiB),
+
+    FSL_IMX7_CCM_ADDR             = 0x30380000,
+
+    FSL_IMX7_SNVS_HP_ADDR         = 0x30370000,
+
+    FSL_IMX7_ANALOG_ADDR          = 0x30360000,
+
+    FSL_IMX7_OCOTP_ADDR           = 0x30350000,
+    FSL_IMX7_OCOTP_SIZE           = 0x10000,
+
+    FSL_IMX7_IOMUXC_GPR_ADDR      = 0x30340000,
+    FSL_IMX7_IOMUXC_GPR_SIZE      = (4 * KiB),
+
+    FSL_IMX7_IOMUXC_ADDR          = 0x30330000,
+    FSL_IMX7_IOMUXC_SIZE          = (4 * KiB),
+
+    FSL_IMX7_KPP_ADDR             = 0x30320000,
+    FSL_IMX7_KPP_SIZE             = (4 * KiB),
+
+    FSL_IMX7_ROMCP_ADDR           = 0x30310000,
+    FSL_IMX7_ROMCP_SIZE           = (4 * KiB),
+
+    FSL_IMX7_GPT4_ADDR            = 0x30300000,
+    FSL_IMX7_GPT3_ADDR            = 0x302F0000,
+    FSL_IMX7_GPT2_ADDR            = 0x302E0000,
+    FSL_IMX7_GPT1_ADDR            = 0x302D0000,
+
+    FSL_IMX7_IOMUXC_LPSR_ADDR     = 0x302C0000,
+    FSL_IMX7_IOMUXC_LPSR_SIZE     = (4 * KiB),
+
+    FSL_IMX7_WDOG4_ADDR           = 0x302B0000,
+    FSL_IMX7_WDOG3_ADDR           = 0x302A0000,
+    FSL_IMX7_WDOG2_ADDR           = 0x30290000,
+    FSL_IMX7_WDOG1_ADDR           = 0x30280000,
+
+    FSL_IMX7_IOMUXC_LPSR_GPR_ADDR = 0x30270000,
+
+    FSL_IMX7_GPIO7_ADDR           = 0x30260000,
+    FSL_IMX7_GPIO6_ADDR           = 0x30250000,
+    FSL_IMX7_GPIO5_ADDR           = 0x30240000,
+    FSL_IMX7_GPIO4_ADDR           = 0x30230000,
+    FSL_IMX7_GPIO3_ADDR           = 0x30220000,
+    FSL_IMX7_GPIO2_ADDR           = 0x30210000,
+    FSL_IMX7_GPIO1_ADDR           = 0x30200000,
+
+    FSL_IMX7_AIPS1_CONF_ADDR      = 0x301F0000,
+    FSL_IMX7_AIPS1_CONF_SIZE      = (64 * KiB),
 
-    FSL_IMX7_A7MPCORE_ADDR        = 0x31000000,
     FSL_IMX7_A7MPCORE_DAP_ADDR    = 0x30000000,
+    FSL_IMX7_A7MPCORE_DAP_SIZE    = (1 * MiB),
 
-    FSL_IMX7_PCIE_REG_ADDR        = 0x33800000,
-    FSL_IMX7_PCIE_REG_SIZE        = 16 * 1024,
+    /* AIPS-1 End */
 
-    FSL_IMX7_GPR_ADDR             = 0x30340000,
+    FSL_IMX7_EIM_CS0_ADDR         = 0x28000000,
+    FSL_IMX7_EIM_CS0_SIZE         = (128 * MiB),
 
-    FSL_IMX7_DMA_APBH_ADDR        = 0x33000000,
-    FSL_IMX7_DMA_APBH_SIZE        = 0x2000,
+    FSL_IMX7_OCRAM_PXP_ADDR       = 0x00940000,
+    FSL_IMX7_OCRAM_PXP_SIZE       = (32 * KiB),
+
+    FSL_IMX7_OCRAM_EPDC_ADDR      = 0x00920000,
+    FSL_IMX7_OCRAM_EPDC_SIZE      = (128 * KiB),
+
+    FSL_IMX7_OCRAM_MEM_ADDR       = 0x00900000,
+    FSL_IMX7_OCRAM_MEM_SIZE       = (128 * KiB),
+
+    FSL_IMX7_TCMU_ADDR            = 0x00800000,
+    FSL_IMX7_TCMU_SIZE            = (32 * KiB),
+
+    FSL_IMX7_TCML_ADDR            = 0x007F8000,
+    FSL_IMX7_TCML_SIZE            = (32 * KiB),
+
+    FSL_IMX7_OCRAM_S_ADDR         = 0x00180000,
+    FSL_IMX7_OCRAM_S_SIZE         = (32 * KiB),
+
+    FSL_IMX7_CAAM_MEM_ADDR        = 0x00100000,
+    FSL_IMX7_CAAM_MEM_SIZE        = (32 * KiB),
+
+    FSL_IMX7_ROM_ADDR             = 0x00000000,
+    FSL_IMX7_ROM_SIZE             = (96 * KiB),
 };
 
 enum FslIMX7IRQs {
diff --git a/hw/arm/fsl-imx7.c b/hw/arm/fsl-imx7.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/fsl-imx7.c
+++ b/hw/arm/fsl-imx7.c
@@ -XXX,XX +XXX,XX @@ static void fsl_imx7_init(Object *obj)
     char name[NAME_SIZE];
     int i;
 
+    /*
+     * CPUs
+     */
     for (i = 0; i < MIN(ms->smp.cpus, FSL_IMX7_NUM_CPUS); i++) {
         snprintf(name, NAME_SIZE, "cpu%d", i);
         object_initialize_child(obj, name, &s->cpu[i],
@@ -XXX,XX +XXX,XX @@ static void fsl_imx7_init(Object *obj)
                             TYPE_A15MPCORE_PRIV);
 
     /*
-     * GPIOs 1 to 7
+     * GPIOs
      */
     for (i = 0; i < FSL_IMX7_NUM_GPIOS; i++) {
         snprintf(name, NAME_SIZE, "gpio%d", i);
@@ -XXX,XX +XXX,XX @@ static void fsl_imx7_init(Object *obj)
     }
 
     /*
-     * GPT1, 2, 3, 4
+     * GPTs
      */
     for (i = 0; i < FSL_IMX7_NUM_GPTS; i++) {
         snprintf(name, NAME_SIZE, "gpt%d", i);
@@ -XXX,XX +XXX,XX @@ static void fsl_imx7_init(Object *obj)
      */
     object_initialize_child(obj, "gpcv2", &s->gpcv2, TYPE_IMX_GPCV2);
 
+    /*
+     * ECSPIs
+     */
     for (i = 0; i < FSL_IMX7_NUM_ECSPIS; i++) {
         snprintf(name, NAME_SIZE, "spi%d", i + 1);
         object_initialize_child(obj, name, &s->spi[i], TYPE_IMX_SPI);
     }
 
-
+    /*
+     * I2Cs
+     */
     for (i = 0; i < FSL_IMX7_NUM_I2CS; i++) {
         snprintf(name, NAME_SIZE, "i2c%d", i + 1);
         object_initialize_child(obj, name, &s->i2c[i], TYPE_IMX_I2C);
     }
 
     /*
-     * UART
+     * UARTs
      */
     for (i = 0; i < FSL_IMX7_NUM_UARTS; i++) {
             snprintf(name, NAME_SIZE, "uart%d", i);
@@ -XXX,XX +XXX,XX @@ static void fsl_imx7_init(Object *obj)
     }
 
     /*
-     * Ethernet
+     * Ethernets
      */
     for (i = 0; i < FSL_IMX7_NUM_ETHS; i++) {
             snprintf(name, NAME_SIZE, "eth%d", i);
@@ -XXX,XX +XXX,XX @@ static void fsl_imx7_init(Object *obj)
     }
 
     /*
-     * SDHCI
+     * SDHCIs
      */
     for (i = 0; i < FSL_IMX7_NUM_USDHCS; i++) {
             snprintf(name, NAME_SIZE, "usdhc%d", i);
@@ -XXX,XX +XXX,XX @@ static void fsl_imx7_init(Object *obj)
     object_initialize_child(obj, "snvs", &s->snvs, TYPE_IMX7_SNVS);
 
     /*
-     * Watchdog
+     * Watchdogs
      */
     for (i = 0; i < FSL_IMX7_NUM_WDTS; i++) {
             snprintf(name, NAME_SIZE, "wdt%d", i);
@@ -XXX,XX +XXX,XX @@ static void fsl_imx7_init(Object *obj)
      */
     object_initialize_child(obj, "gpr", &s->gpr, TYPE_IMX7_GPR);
 
+    /*
+     * PCIE
+     */
     object_initialize_child(obj, "pcie", &s->pcie, TYPE_DESIGNWARE_PCIE_HOST);
 
+    /*
+     * USBs
+     */
     for (i = 0; i < FSL_IMX7_NUM_USBS; i++) {
         snprintf(name, NAME_SIZE, "usb%d", i);
         object_initialize_child(obj, name, &s->usb[i], TYPE_CHIPIDEA);
@@ -XXX,XX +XXX,XX @@ static void fsl_imx7_realize(DeviceState *dev, Error **errp)
         return;
     }
 
+    /*
+     * CPUs
+     */
     for (i = 0; i < smp_cpus; i++) {
         o = OBJECT(&s->cpu[i]);
 
@@ -XXX,XX +XXX,XX @@ static void fsl_imx7_realize(DeviceState *dev, Error **errp)
      * A7MPCORE DAP
      */
     create_unimplemented_device("a7mpcore-dap", FSL_IMX7_A7MPCORE_DAP_ADDR,
-                                0x100000);
+                                FSL_IMX7_A7MPCORE_DAP_SIZE);
 
     /*
-     * GPT1, 2, 3, 4
+     * GPTs
      */
     for (i = 0; i < FSL_IMX7_NUM_GPTS; i++) {
         static const hwaddr FSL_IMX7_GPTn_ADDR[FSL_IMX7_NUM_GPTS] = {
@@ -XXX,XX +XXX,XX @@ static void fsl_imx7_realize(DeviceState *dev, Error **errp)
                                             FSL_IMX7_GPTn_IRQ[i]));
     }
 
+    /*
+     * GPIOs
+     */
     for (i = 0; i < FSL_IMX7_NUM_GPIOS; i++) {
         static const hwaddr FSL_IMX7_GPIOn_ADDR[FSL_IMX7_NUM_GPIOS] = {
             FSL_IMX7_GPIO1_ADDR,
@@ -XXX,XX +XXX,XX @@ static void fsl_imx7_realize(DeviceState *dev, Error **errp)
     /*
      * IOMUXC and IOMUXC_LPSR
      */
-    for (i = 0; i < FSL_IMX7_NUM_IOMUXCS; i++) {
-        static const hwaddr FSL_IMX7_IOMUXCn_ADDR[FSL_IMX7_NUM_IOMUXCS] = {
-            FSL_IMX7_IOMUXC_ADDR,
-            FSL_IMX7_IOMUXC_LPSR_ADDR,
-        };
-
-        snprintf(name, NAME_SIZE, "iomuxc%d", i);
-        create_unimplemented_device(name, FSL_IMX7_IOMUXCn_ADDR[i],
-                                    FSL_IMX7_IOMUXCn_SIZE);
-    }
+    create_unimplemented_device("iomuxc", FSL_IMX7_IOMUXC_ADDR,
+                                FSL_IMX7_IOMUXC_SIZE);
+    create_unimplemented_device("iomuxc_lspr", FSL_IMX7_IOMUXC_LPSR_ADDR,
+                                FSL_IMX7_IOMUXC_LPSR_SIZE);
 
     /*
      * CCM
@@ -XXX,XX +XXX,XX @@ static void fsl_imx7_realize(DeviceState *dev, Error **errp)
     sysbus_realize(SYS_BUS_DEVICE(&s->gpcv2), &error_abort);
     sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpcv2), 0, FSL_IMX7_GPC_ADDR);
 
-    /* Initialize all ECSPI */
+    /*
+     * ECSPIs
+     */
     for (i = 0; i < FSL_IMX7_NUM_ECSPIS; i++) {
         static const hwaddr FSL_IMX7_SPIn_ADDR[FSL_IMX7_NUM_ECSPIS] = {
             FSL_IMX7_ECSPI1_ADDR,
@@ -XXX,XX +XXX,XX @@ static void fsl_imx7_realize(DeviceState *dev, Error **errp)
                                             FSL_IMX7_SPIn_IRQ[i]));
     }
 
+    /*
+     * I2Cs
+     */
     for (i = 0; i < FSL_IMX7_NUM_I2CS; i++) {
         static const hwaddr FSL_IMX7_I2Cn_ADDR[FSL_IMX7_NUM_I2CS] = {
             FSL_IMX7_I2C1_ADDR,
@@ -XXX,XX +XXX,XX @@ static void fsl_imx7_realize(DeviceState *dev, Error **errp)
     }
 
     /*
-     * UART
+     * UARTs
      */
     for (i = 0; i < FSL_IMX7_NUM_UARTS; i++) {
         static const hwaddr FSL_IMX7_UARTn_ADDR[FSL_IMX7_NUM_UARTS] = {
@@ -XXX,XX +XXX,XX @@ static void fsl_imx7_realize(DeviceState *dev, Error **errp)
     }
 
     /*
-     * Ethernet
+     * Ethernets
      *
      * We must use two loops since phy_connected affects the other interface
      * and we have to set all properties before calling sysbus_realize().
@@ -XXX,XX +XXX,XX @@ static void fsl_imx7_realize(DeviceState *dev, Error **errp)
     }
 
     /*
-     * USDHC
+     * USDHCs
      */
     for (i = 0; i < FSL_IMX7_NUM_USDHCS; i++) {
         static const hwaddr FSL_IMX7_USDHCn_ADDR[FSL_IMX7_NUM_USDHCS] = {
@@ -XXX,XX +XXX,XX @@ static void fsl_imx7_realize(DeviceState *dev, Error **errp)
      * SNVS
      */
     sysbus_realize(SYS_BUS_DEVICE(&s->snvs), &error_abort);
-    sysbus_mmio_map(SYS_BUS_DEVICE(&s->snvs), 0, FSL_IMX7_SNVS_ADDR);
+    sysbus_mmio_map(SYS_BUS_DEVICE(&s->snvs), 0, FSL_IMX7_SNVS_HP_ADDR);
 
     /*
      * SRC
@@ -XXX,XX +XXX,XX @@ static void fsl_imx7_realize(DeviceState *dev, Error **errp)
     create_unimplemented_device("src", FSL_IMX7_SRC_ADDR, FSL_IMX7_SRC_SIZE);
 
     /*
-     * Watchdog
+     * Watchdogs
      */
     for (i = 0; i < FSL_IMX7_NUM_WDTS; i++) {
         static const hwaddr FSL_IMX7_WDOGn_ADDR[FSL_IMX7_NUM_WDTS] = {
@@ -XXX,XX +XXX,XX @@ static void fsl_imx7_realize(DeviceState *dev, Error **errp)
     create_unimplemented_device("caam", FSL_IMX7_CAAM_ADDR, FSL_IMX7_CAAM_SIZE);
 
     /*
-     * PWM
+     * PWMs
      */
-    create_unimplemented_device("pwm1", FSL_IMX7_PWM1_ADDR, FSL_IMX7_PWMn_SIZE);
-    create_unimplemented_device("pwm2", FSL_IMX7_PWM2_ADDR, FSL_IMX7_PWMn_SIZE);
-    create_unimplemented_device("pwm3", FSL_IMX7_PWM3_ADDR, FSL_IMX7_PWMn_SIZE);
-    create_unimplemented_device("pwm4", FSL_IMX7_PWM4_ADDR, FSL_IMX7_PWMn_SIZE);
+    for (i = 0; i < FSL_IMX7_NUM_PWMS; i++) {
+        static const hwaddr FSL_IMX7_PWMn_ADDR[FSL_IMX7_NUM_PWMS] = {
+            FSL_IMX7_PWM1_ADDR,
+            FSL_IMX7_PWM2_ADDR,
+            FSL_IMX7_PWM3_ADDR,
+            FSL_IMX7_PWM4_ADDR,
+        };
+
+        snprintf(name, NAME_SIZE, "pwm%d", i);
+        create_unimplemented_device(name, FSL_IMX7_PWMn_ADDR[i],
+                                    FSL_IMX7_PWMn_SIZE);
+    }
 
     /*
-     * CAN
+     * CANs
      */
-    create_unimplemented_device("can1", FSL_IMX7_CAN1_ADDR, FSL_IMX7_CANn_SIZE);
-    create_unimplemented_device("can2", FSL_IMX7_CAN2_ADDR, FSL_IMX7_CANn_SIZE);
+    for (i = 0; i < FSL_IMX7_NUM_CANS; i++) {
+        static const hwaddr FSL_IMX7_CANn_ADDR[FSL_IMX7_NUM_CANS] = {
+            FSL_IMX7_CAN1_ADDR,
+            FSL_IMX7_CAN2_ADDR,
+        };
+
+        snprintf(name, NAME_SIZE, "can%d", i);
+        create_unimplemented_device(name, FSL_IMX7_CANn_ADDR[i],
+                                    FSL_IMX7_CANn_SIZE);
+    }
 
     /*
-     * SAI (Audio SSI (Synchronous Serial Interface))
+     * SAIs (Audio SSI (Synchronous Serial Interface))
      */
-    create_unimplemented_device("sai1", FSL_IMX7_SAI1_ADDR, FSL_IMX7_SAIn_SIZE);
-    create_unimplemented_device("sai2", FSL_IMX7_SAI2_ADDR, FSL_IMX7_SAIn_SIZE);
-    create_unimplemented_device("sai2", FSL_IMX7_SAI3_ADDR, FSL_IMX7_SAIn_SIZE);
+    for (i = 0; i < FSL_IMX7_NUM_SAIS; i++) {
+        static const hwaddr FSL_IMX7_SAIn_ADDR[FSL_IMX7_NUM_SAIS] = {
+            FSL_IMX7_SAI1_ADDR,
+            FSL_IMX7_SAI2_ADDR,
+            FSL_IMX7_SAI3_ADDR,
+        };
+
+        snprintf(name, NAME_SIZE, "sai%d", i);
+        create_unimplemented_device(name, FSL_IMX7_SAIn_ADDR[i],
+                                    FSL_IMX7_SAIn_SIZE);
+    }
 
     /*
      * OCOTP
@@ -XXX,XX +XXX,XX @@ static void fsl_imx7_realize(DeviceState *dev, Error **errp)
     create_unimplemented_device("ocotp", FSL_IMX7_OCOTP_ADDR,
                                 FSL_IMX7_OCOTP_SIZE);
 
+    /*
+     * GPR
+     */
     sysbus_realize(SYS_BUS_DEVICE(&s->gpr), &error_abort);
-    sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpr), 0, FSL_IMX7_GPR_ADDR);
+    sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpr), 0, FSL_IMX7_IOMUXC_GPR_ADDR);
 
+    /*
+     * PCIE
+     */
     sysbus_realize(SYS_BUS_DEVICE(&s->pcie), &error_abort);
     sysbus_mmio_map(SYS_BUS_DEVICE(&s->pcie), 0, FSL_IMX7_PCIE_REG_ADDR);
 
@@ -XXX,XX +XXX,XX @@ static void fsl_imx7_realize(DeviceState *dev, Error **errp)
     irq = qdev_get_gpio_in(DEVICE(&s->a7mpcore), FSL_IMX7_PCI_INTD_IRQ);
     sysbus_connect_irq(SYS_BUS_DEVICE(&s->pcie), 3, irq);
 
-
+    /*
+     * USBs
+     */
     for (i = 0; i < FSL_IMX7_NUM_USBS; i++) {
         static const hwaddr FSL_IMX7_USBMISCn_ADDR[FSL_IMX7_NUM_USBS] = {
             FSL_IMX7_USBMISC1_ADDR,
@@ -XXX,XX +XXX,XX @@ static void fsl_imx7_realize(DeviceState *dev, Error **errp)
      */
     create_unimplemented_device("pcie-phy", FSL_IMX7_PCIE_PHY_ADDR,
                                 FSL_IMX7_PCIE_PHY_SIZE);
+
 }
 
 static Property fsl_imx7_properties[] = {
-- 
2.34.1

From: Jean-Christophe Dubois <jcd@tribudubois.net>

Signed-off-by: Jean-Christophe Dubois <jcd@tribudubois.net>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-id: f887a3483996ba06d40bd62ffdfb0ecf68621987.1692964892.git.jcd@tribudubois.net
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 include/hw/arm/fsl-imx7.h |  7 +++++
 hw/arm/fsl-imx7.c         | 63 +++++++++++++++++++++++++++++++++++++++
 2 files changed, 70 insertions(+)

diff --git a/include/hw/arm/fsl-imx7.h b/include/hw/arm/fsl-imx7.h
index XXXXXXX..XXXXXXX 100644
--- a/include/hw/arm/fsl-imx7.h
+++ b/include/hw/arm/fsl-imx7.h
@@ -XXX,XX +XXX,XX @@ struct FslIMX7State {
     IMX7GPRState       gpr;
     ChipideaState      usb[FSL_IMX7_NUM_USBS];
     DesignwarePCIEHost pcie;
+    MemoryRegion       rom;
+    MemoryRegion       caam;
+    MemoryRegion       ocram;
+    MemoryRegion       ocram_epdc;
+    MemoryRegion       ocram_pxp;
+    MemoryRegion       ocram_s;
+
     uint32_t           phy_num[FSL_IMX7_NUM_ETHS];
     bool               phy_connected[FSL_IMX7_NUM_ETHS];
 };
diff --git a/hw/arm/fsl-imx7.c b/hw/arm/fsl-imx7.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/fsl-imx7.c
+++ b/hw/arm/fsl-imx7.c
@@ -XXX,XX +XXX,XX @@ static void fsl_imx7_realize(DeviceState *dev, Error **errp)
     create_unimplemented_device("pcie-phy", FSL_IMX7_PCIE_PHY_ADDR,
                                 FSL_IMX7_PCIE_PHY_SIZE);
 
+    /*
+     * CSU
+     */
+    create_unimplemented_device("csu", FSL_IMX7_CSU_ADDR,
+                                FSL_IMX7_CSU_SIZE);
+
+    /*
+     * TZASC
+     */
+    create_unimplemented_device("tzasc", FSL_IMX7_TZASC_ADDR,
+                                FSL_IMX7_TZASC_SIZE);
+
+    /*
+     * OCRAM memory
+     */
+    memory_region_init_ram(&s->ocram, NULL, "imx7.ocram",
+                           FSL_IMX7_OCRAM_MEM_SIZE,
+                           &error_abort);
+    memory_region_add_subregion(get_system_memory(), FSL_IMX7_OCRAM_MEM_ADDR,
+                                &s->ocram);
+
+    /*
+     * OCRAM EPDC memory
+     */
+    memory_region_init_ram(&s->ocram_epdc, NULL, "imx7.ocram_epdc",
+                           FSL_IMX7_OCRAM_EPDC_SIZE,
+                           &error_abort);
+    memory_region_add_subregion(get_system_memory(), FSL_IMX7_OCRAM_EPDC_ADDR,
+                                &s->ocram_epdc);
+
+    /*
+     * OCRAM PXP memory
+     */
+    memory_region_init_ram(&s->ocram_pxp, NULL, "imx7.ocram_pxp",
+                           FSL_IMX7_OCRAM_PXP_SIZE,
+                           &error_abort);
+    memory_region_add_subregion(get_system_memory(), FSL_IMX7_OCRAM_PXP_ADDR,
+                                &s->ocram_pxp);
+
+    /*
+     * OCRAM_S memory
+     */
+    memory_region_init_ram(&s->ocram_s, NULL, "imx7.ocram_s",
+                           FSL_IMX7_OCRAM_S_SIZE,
+                           &error_abort);
+    memory_region_add_subregion(get_system_memory(), FSL_IMX7_OCRAM_S_ADDR,
+                                &s->ocram_s);
+
+    /*
+     * ROM memory
+     */
+    memory_region_init_rom(&s->rom, OBJECT(dev), "imx7.rom",
+                           FSL_IMX7_ROM_SIZE, &error_abort);
+    memory_region_add_subregion(get_system_memory(), FSL_IMX7_ROM_ADDR,
+                                &s->rom);
+
+    /*
+     * CAAM memory
+     */
+    memory_region_init_rom(&s->caam, OBJECT(dev), "imx7.caam",
+                           FSL_IMX7_CAAM_MEM_SIZE, &error_abort);
+    memory_region_add_subregion(get_system_memory(), FSL_IMX7_CAAM_MEM_ADDR,
+                                &s->caam);
 }
 
 static Property fsl_imx7_properties[] = {
-- 
2.34.1

From: Jean-Christophe Dubois <jcd@tribudubois.net>

The SRC device is normally used to start the secondary CPU.

When running Linux directly, QEMU is emulating a PSCI interface that UBOOT
is installing at boot time and therefore the fact that the SRC device is
unimplemented is hidden as Qemu respond directly to PSCI requets without
using the SRC device.

But if you try to run a more bare metal application (maybe uboot itself),
then it is not possible to start the secondary CPU as the SRC is an
unimplemented device.

This patch adds the ability to start the secondary CPU through the SRC
device so that you can use this feature in bare metal applications.

Signed-off-by: Jean-Christophe Dubois <jcd@tribudubois.net>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: ce9a0162defd2acee5dc7f8a674743de0cded569.1692964892.git.jcd@tribudubois.net
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 include/hw/arm/fsl-imx7.h  |   3 +-
 include/hw/misc/imx7_src.h |  66 +++++++++
 hw/arm/fsl-imx7.c          |   8 +-
 hw/misc/imx7_src.c         | 276 +++++++++++++++++++++++++++++++++++++
 hw/misc/meson.build        |   1 +
 hw/misc/trace-events       |   4 +
 6 files changed, 356 insertions(+), 2 deletions(-)
 create mode 100644 include/hw/misc/imx7_src.h
 create mode 100644 hw/misc/imx7_src.c

The architecture requires (R_TYTWB) that an attempt to return from EL3
when SCR_EL3.{NSE,NS} are {1,0} is an illegal exception return. (This
enforces that the CPU can't ever be executing below EL3 with the
NSE,NS bits indicating an invalid security state.)

We were missing this check; add it.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20230807150618.101357-1-peter.maydell@linaro.org
---
 target/arm/tcg/helper-a64.c | 9 +++++++++
 1 file changed, 9 insertions(+)

diff --git a/target/arm/tcg/helper-a64.c b/target/arm/tcg/helper-a64.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/tcg/helper-a64.c
+++ b/target/arm/tcg/helper-a64.c
@@ -XXX,XX +XXX,XX @@ void HELPER(exception_return)(CPUARMState *env, uint64_t new_pc)
         spsr &= ~PSTATE_SS;
     }
 
+    /*
+     * FEAT_RME forbids return from EL3 with an invalid security state.
+     * We don't need an explicit check for FEAT_RME here because we enforce
+     * in scr_write() that you can't set the NSE bit without it.
+     */
+    if (cur_el == 3 && (env->cp15.scr_el3 & (SCR_NS | SCR_NSE)) == SCR_NSE) {
+        goto illegal_return;
+    }
+
     new_el = el_from_spsr(spsr);
     if (new_el == -1) {
         goto illegal_return;
-- 
2.34.1

In the aspeed_rtc device we store a difference between two time_t
values in an 'int'. This is not really correct when time_t could
be 64 bits. Enlarge the field to 'int64_t'.

This is a migration compatibility break for the aspeed boards.
While we are changing the vmstate, remove the accidental
duplicate of the offset field.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
---
 include/hw/rtc/aspeed_rtc.h | 2 +-
 hw/rtc/aspeed_rtc.c         | 5 ++---
 2 files changed, 3 insertions(+), 4 deletions(-)

diff --git a/include/hw/rtc/aspeed_rtc.h b/include/hw/rtc/aspeed_rtc.h
index XXXXXXX..XXXXXXX 100644
--- a/include/hw/rtc/aspeed_rtc.h
+++ b/include/hw/rtc/aspeed_rtc.h
@@ -XXX,XX +XXX,XX @@ struct AspeedRtcState {
     qemu_irq irq;
 
     uint32_t reg[0x18];
-    int offset;
+    int64_t offset;
 
 };
 
diff --git a/hw/rtc/aspeed_rtc.c b/hw/rtc/aspeed_rtc.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/rtc/aspeed_rtc.c
+++ b/hw/rtc/aspeed_rtc.c
@@ -XXX,XX +XXX,XX @@ static const MemoryRegionOps aspeed_rtc_ops = {
 
 static const VMStateDescription vmstate_aspeed_rtc = {
     .name = TYPE_ASPEED_RTC,
-    .version_id = 1,
+    .version_id = 2,
     .fields = (VMStateField[]) {
         VMSTATE_UINT32_ARRAY(reg, AspeedRtcState, 0x18),
-        VMSTATE_INT32(offset, AspeedRtcState),
-        VMSTATE_INT32(offset, AspeedRtcState),
+        VMSTATE_INT64(offset, AspeedRtcState),
         VMSTATE_END_OF_LIST()
     }
 };
-- 
2.34.1

The functions qemu_get_timedate() and qemu_timedate_diff() take
and return a time offset as an integer. Coverity points out that
means that when an RTC device implementation holds an offset
as a time_t, as the m48t59 does, the time_t will get truncated.
(CID 1507157, 1517772).

The functions work with time_t internally, so make them use that type
in their APIs.

Note that this won't help any Y2038 issues where either the device
model itself is keeping the offset in a 32-bit integer, or where the
hardware under emulation has Y2038 or other rollover problems.  If we
missed any cases of the former then hopefully Coverity will warn us
about them since after this patch we'd be truncating a time_t in
assignments from qemu_timedate_diff().)

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
 include/sysemu/rtc.h | 4 ++--
 softmmu/rtc.c        | 4 ++--
 2 files changed, 4 insertions(+), 4 deletions(-)

diff --git a/include/sysemu/rtc.h b/include/sysemu/rtc.h
index XXXXXXX..XXXXXXX 100644
--- a/include/sysemu/rtc.h
+++ b/include/sysemu/rtc.h
@@ -XXX,XX +XXX,XX @@
  * The behaviour of the clock whose value this function returns will
  * depend on the -rtc command line option passed by the user.
  */
-void qemu_get_timedate(struct tm *tm, int offset);
+void qemu_get_timedate(struct tm *tm, time_t offset);
 
 /**
  * qemu_timedate_diff: Return difference between a struct tm and the RTC
@@ -XXX,XX +XXX,XX @@ void qemu_get_timedate(struct tm *tm, int offset);
  * a timestamp one hour further ahead than the current RTC time
  * then this function will return 3600.
  */
-int qemu_timedate_diff(struct tm *tm);
+time_t qemu_timedate_diff(struct tm *tm);
 
 #endif
diff --git a/softmmu/rtc.c b/softmmu/rtc.c
index XXXXXXX..XXXXXXX 100644
--- a/softmmu/rtc.c
+++ b/softmmu/rtc.c
@@ -XXX,XX +XXX,XX @@ static time_t qemu_ref_timedate(QEMUClockType clock)
     return value;
 }
 
-void qemu_get_timedate(struct tm *tm, int offset)
+void qemu_get_timedate(struct tm *tm, time_t offset)
 {
     time_t ti = qemu_ref_timedate(rtc_clock);
 
@@ -XXX,XX +XXX,XX @@ void qemu_get_timedate(struct tm *tm, int offset)
     }
 }
 
-int qemu_timedate_diff(struct tm *tm)
+time_t qemu_timedate_diff(struct tm *tm)
 {
     time_t seconds;
 
-- 
2.34.1

Where architecturally one ARM_FEATURE_X flag implies another
ARM_FEATURE_Y, we allow the CPU init function to only set X, and then
set Y for it.  Currently we do this in two places -- we set a few
flags in arm_cpu_post_init() because we need them to decide which
properties to create on the CPU object, and then we do the rest in
arm_cpu_realizefn().  However, this is fragile, because it's easy to
add a new property and not notice that this means that an X-implies-Y
check now has to move from realize to post-init.

As a specific example, the pmsav7-dregion property is conditional
on ARM_FEATURE_PMSA && ARM_FEATURE_V7, which means it won't appear
on the Cortex-M33 and -M55, because they set ARM_FEATURE_V8 and
rely on V8-implies-V7, which doesn't happen until the realizefn.

Move all of these X-implies-Y checks into a new function, which
we call at the top of arm_cpu_post_init(), so the feature bits
are available at that point.

This does now give us the reverse issue, that if there's a feature
bit which is enabled or disabled by the setting of a property then
then X-implies-Y features that are dependent on that property need to
be in realize, not in this new function.  But the only one of those
is the "EL3 implies VBAR" which is already in the right place, so
putting things this way round seems better to me.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20230724174335.2150499-2-peter.maydell@linaro.org
---
 target/arm/cpu.c | 179 +++++++++++++++++++++++++----------------------
 1 file changed, 97 insertions(+), 82 deletions(-)

diff --git a/target/arm/cpu.c b/target/arm/cpu.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/cpu.c
+++ b/target/arm/cpu.c
@@ -XXX,XX +XXX,XX @@ unsigned int gt_cntfrq_period_ns(ARMCPU *cpu)
       NANOSECONDS_PER_SECOND / cpu->gt_cntfrq_hz : 1;
 }
 
+static void arm_cpu_propagate_feature_implications(ARMCPU *cpu)
+{
+    CPUARMState *env = &cpu->env;
+    bool no_aa32 = false;
+
+    /*
+     * Some features automatically imply others: set the feature
+     * bits explicitly for these cases.
+     */
+
+    if (arm_feature(env, ARM_FEATURE_M)) {
+        set_feature(env, ARM_FEATURE_PMSA);
+    }
+
+    if (arm_feature(env, ARM_FEATURE_V8)) {
+        if (arm_feature(env, ARM_FEATURE_M)) {
+            set_feature(env, ARM_FEATURE_V7);
+        } else {
+            set_feature(env, ARM_FEATURE_V7VE);
+        }
+    }
+
+    /*
+     * There exist AArch64 cpus without AArch32 support.  When KVM
+     * queries ID_ISAR0_EL1 on such a host, the value is UNKNOWN.
+     * Similarly, we cannot check ID_AA64PFR0 without AArch64 support.
+     * As a general principle, we also do not make ID register
+     * consistency checks anywhere unless using TCG, because only
+     * for TCG would a consistency-check failure be a QEMU bug.
+     */
+    if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) {
+        no_aa32 = !cpu_isar_feature(aa64_aa32, cpu);
+    }
+
+    if (arm_feature(env, ARM_FEATURE_V7VE)) {
+        /*
+         * v7 Virtualization Extensions. In real hardware this implies
+         * EL2 and also the presence of the Security Extensions.
+         * For QEMU, for backwards-compatibility we implement some
+         * CPUs or CPU configs which have no actual EL2 or EL3 but do
+         * include the various other features that V7VE implies.
+         * Presence of EL2 itself is ARM_FEATURE_EL2, and of the
+         * Security Extensions is ARM_FEATURE_EL3.
+         */
+        assert(!tcg_enabled() || no_aa32 ||
+               cpu_isar_feature(aa32_arm_div, cpu));
+        set_feature(env, ARM_FEATURE_LPAE);
+        set_feature(env, ARM_FEATURE_V7);
+    }
+    if (arm_feature(env, ARM_FEATURE_V7)) {
+        set_feature(env, ARM_FEATURE_VAPA);
+        set_feature(env, ARM_FEATURE_THUMB2);
+        set_feature(env, ARM_FEATURE_MPIDR);
+        if (!arm_feature(env, ARM_FEATURE_M)) {
+            set_feature(env, ARM_FEATURE_V6K);
+        } else {
+            set_feature(env, ARM_FEATURE_V6);
+        }
+
+        /*
+         * Always define VBAR for V7 CPUs even if it doesn't exist in
+         * non-EL3 configs. This is needed by some legacy boards.
+         */
+        set_feature(env, ARM_FEATURE_VBAR);
+    }
+    if (arm_feature(env, ARM_FEATURE_V6K)) {
+        set_feature(env, ARM_FEATURE_V6);
+        set_feature(env, ARM_FEATURE_MVFR);
+    }
+    if (arm_feature(env, ARM_FEATURE_V6)) {
+        set_feature(env, ARM_FEATURE_V5);
+        if (!arm_feature(env, ARM_FEATURE_M)) {
+            assert(!tcg_enabled() || no_aa32 ||
+                   cpu_isar_feature(aa32_jazelle, cpu));
+            set_feature(env, ARM_FEATURE_AUXCR);
+        }
+    }
+    if (arm_feature(env, ARM_FEATURE_V5)) {
+        set_feature(env, ARM_FEATURE_V4T);
+    }
+    if (arm_feature(env, ARM_FEATURE_LPAE)) {
+        set_feature(env, ARM_FEATURE_V7MP);
+    }
+    if (arm_feature(env, ARM_FEATURE_CBAR_RO)) {
+        set_feature(env, ARM_FEATURE_CBAR);
+    }
+    if (arm_feature(env, ARM_FEATURE_THUMB2) &&
+        !arm_feature(env, ARM_FEATURE_M)) {
+        set_feature(env, ARM_FEATURE_THUMB_DSP);
+    }
+}
+
 void arm_cpu_post_init(Object *obj)
 {
     ARMCPU *cpu = ARM_CPU(obj);
 
-    /* M profile implies PMSA. We have to do this here rather than
-     * in realize with the other feature-implication checks because
-     * we look at the PMSA bit to see if we should add some properties.
+    /*
+     * Some features imply others. Figure this out now, because we
+     * are going to look at the feature bits in deciding which
+     * properties to add.
      */
-    if (arm_feature(&cpu->env, ARM_FEATURE_M)) {
-        set_feature(&cpu->env, ARM_FEATURE_PMSA);
-    }
+    arm_cpu_propagate_feature_implications(cpu);
 
     if (arm_feature(&cpu->env, ARM_FEATURE_CBAR) ||
         arm_feature(&cpu->env, ARM_FEATURE_CBAR_RO)) {
@@ -XXX,XX +XXX,XX @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp)
     CPUARMState *env = &cpu->env;
     int pagebits;
     Error *local_err = NULL;
-    bool no_aa32 = false;
 
     /* Use pc-relative instructions in system-mode */
 #ifndef CONFIG_USER_ONLY
@@ -XXX,XX +XXX,XX @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp)
         cpu->isar.id_isar3 = u;
     }
 
-    /* Some features automatically imply others: */
-    if (arm_feature(env, ARM_FEATURE_V8)) {
-        if (arm_feature(env, ARM_FEATURE_M)) {
-            set_feature(env, ARM_FEATURE_V7);
-        } else {
-            set_feature(env, ARM_FEATURE_V7VE);
-        }
-    }
-
-    /*
-     * There exist AArch64 cpus without AArch32 support.  When KVM
-     * queries ID_ISAR0_EL1 on such a host, the value is UNKNOWN.
-     * Similarly, we cannot check ID_AA64PFR0 without AArch64 support.
-     * As a general principle, we also do not make ID register
-     * consistency checks anywhere unless using TCG, because only
-     * for TCG would a consistency-check failure be a QEMU bug.
-     */
-    if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) {
-        no_aa32 = !cpu_isar_feature(aa64_aa32, cpu);
-    }
-
-    if (arm_feature(env, ARM_FEATURE_V7VE)) {
-        /* v7 Virtualization Extensions. In real hardware this implies
-         * EL2 and also the presence of the Security Extensions.
-         * For QEMU, for backwards-compatibility we implement some
-         * CPUs or CPU configs which have no actual EL2 or EL3 but do
-         * include the various other features that V7VE implies.
-         * Presence of EL2 itself is ARM_FEATURE_EL2, and of the
-         * Security Extensions is ARM_FEATURE_EL3.
-         */
-        assert(!tcg_enabled() || no_aa32 ||
-               cpu_isar_feature(aa32_arm_div, cpu));
-        set_feature(env, ARM_FEATURE_LPAE);
-        set_feature(env, ARM_FEATURE_V7);
-    }
-    if (arm_feature(env, ARM_FEATURE_V7)) {
-        set_feature(env, ARM_FEATURE_VAPA);
-        set_feature(env, ARM_FEATURE_THUMB2);
-        set_feature(env, ARM_FEATURE_MPIDR);
-        if (!arm_feature(env, ARM_FEATURE_M)) {
-            set_feature(env, ARM_FEATURE_V6K);
-        } else {
-            set_feature(env, ARM_FEATURE_V6);
-        }
-
-        /* Always define VBAR for V7 CPUs even if it doesn't exist in
-         * non-EL3 configs. This is needed by some legacy boards.
-         */
-        set_feature(env, ARM_FEATURE_VBAR);
-    }
-    if (arm_feature(env, ARM_FEATURE_V6K)) {
-        set_feature(env, ARM_FEATURE_V6);
-        set_feature(env, ARM_FEATURE_MVFR);
-    }
-    if (arm_feature(env, ARM_FEATURE_V6)) {
-        set_feature(env, ARM_FEATURE_V5);
-        if (!arm_feature(env, ARM_FEATURE_M)) {
-            assert(!tcg_enabled() || no_aa32 ||
-                   cpu_isar_feature(aa32_jazelle, cpu));
-            set_feature(env, ARM_FEATURE_AUXCR);
-        }
-    }
-    if (arm_feature(env, ARM_FEATURE_V5)) {
-        set_feature(env, ARM_FEATURE_V4T);
-    }
-    if (arm_feature(env, ARM_FEATURE_LPAE)) {
-        set_feature(env, ARM_FEATURE_V7MP);
-    }
-    if (arm_feature(env, ARM_FEATURE_CBAR_RO)) {
-        set_feature(env, ARM_FEATURE_CBAR);
-    }
-    if (arm_feature(env, ARM_FEATURE_THUMB2) &&
-        !arm_feature(env, ARM_FEATURE_M)) {
-        set_feature(env, ARM_FEATURE_THUMB_DSP);
-    }
 
     /*
      * We rely on no XScale CPU having VFP so we can use the same bits in the
-- 
2.34.1

M-profile CPUs generally allow configuration of the number of MPU
regions that they have.  We don't currently model this, so our
implementations of some of the board models provide CPUs with the
wrong number of regions.  RTOSes like Zephyr that hardcode the
expected number of regions may therefore not run on the model if they
are set up to run on real hardware.

Add properties mpu-ns-regions and mpu-s-regions to the ARMV7M object,
matching the ability of hardware to configure the number of Secure
and NonSecure regions separately.  Our actual CPU implementation
doesn't currently support that, and it happens that none of the MPS
boards we model set the number of regions differently for Secure vs
NonSecure, so we provide an interface to the boards and SoCs that
won't need to change if we ever do add that functionality in future,
but make it an error to configure the two properties to different
values.

(The property name on the CPU is the somewhat misnamed-for-M-profile
"pmsav7-dregion", so we don't follow that naming convention for
the properties here. The TRM doesn't say what the CPU configuration
variable names are, so we pick something, and follow the lowercase
convention we already have for properties here.)

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-id: 20230724174335.2150499-3-peter.maydell@linaro.org
---
 include/hw/arm/armv7m.h |  8 ++++++++
 hw/arm/armv7m.c         | 21 +++++++++++++++++++++
 2 files changed, 29 insertions(+)

diff --git a/include/hw/arm/armv7m.h b/include/hw/arm/armv7m.h
index XXXXXXX..XXXXXXX 100644
--- a/include/hw/arm/armv7m.h
+++ b/include/hw/arm/armv7m.h
@@ -XXX,XX +XXX,XX @@ OBJECT_DECLARE_SIMPLE_TYPE(ARMv7MState, ARMV7M)
  * + Property "vfp": enable VFP (forwarded to CPU object)
  * + Property "dsp": enable DSP (forwarded to CPU object)
  * + Property "enable-bitband": expose bitbanded IO
+ * + Property "mpu-ns-regions": number of Non-Secure MPU regions (forwarded
+ *   to CPU object pmsav7-dregion property; default is whatever the default
+ *   for the CPU is)
+ * + Property "mpu-s-regions": number of Secure MPU regions (default is
+ *   whatever the default for the CPU is; must currently be set to the same
+ *   value as mpu-ns-regions if the CPU implements the Security Extension)
  * + Clock input "refclk" is the external reference clock for the systick timers
  * + Clock input "cpuclk" is the main CPU clock
  */
@@ -XXX,XX +XXX,XX @@ struct ARMv7MState {
     Object *idau;
     uint32_t init_svtor;
     uint32_t init_nsvtor;
+    uint32_t mpu_ns_regions;
+    uint32_t mpu_s_regions;
     bool enable_bitband;
     bool start_powered_off;
     bool vfp;
diff --git a/hw/arm/armv7m.c b/hw/arm/armv7m.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/armv7m.c
+++ b/hw/arm/armv7m.c
@@ -XXX,XX +XXX,XX @@ static void armv7m_realize(DeviceState *dev, Error **errp)
         }
     }
 
+    /*
+     * Real M-profile hardware can be configured with a different number of
+     * MPU regions for Secure vs NonSecure. QEMU's CPU implementation doesn't
+     * support that yet, so catch attempts to select that.
+     */
+    if (arm_feature(&s->cpu->env, ARM_FEATURE_M_SECURITY) &&
+        s->mpu_ns_regions != s->mpu_s_regions) {
+        error_setg(errp,
+                   "mpu-ns-regions and mpu-s-regions properties must have the same value");
+        return;
+    }
+    if (s->mpu_ns_regions != UINT_MAX &&
+        object_property_find(OBJECT(s->cpu), "pmsav7-dregion")) {
+        if (!object_property_set_uint(OBJECT(s->cpu), "pmsav7-dregion",
+                                      s->mpu_ns_regions, errp)) {
+            return;
+        }
+    }
+
     /*
      * Tell the CPU where the NVIC is; it will fail realize if it doesn't
      * have one. Similarly, tell the NVIC where its CPU is.
@@ -XXX,XX +XXX,XX @@ static Property armv7m_properties[] = {
                      false),
     DEFINE_PROP_BOOL("vfp", ARMv7MState, vfp, true),
     DEFINE_PROP_BOOL("dsp", ARMv7MState, dsp, true),
+    DEFINE_PROP_UINT32("mpu-ns-regions", ARMv7MState, mpu_ns_regions, UINT_MAX),
+    DEFINE_PROP_UINT32("mpu-s-regions", ARMv7MState, mpu_s_regions, UINT_MAX),
     DEFINE_PROP_END_OF_LIST(),
 };
 
-- 
2.34.1

The IoTKit, SSE200 and SSE300 all default to 8 MPU regions.  The
MPS2/MPS3 FPGA images don't override these except in the case of
AN547, which uses 16 MPU regions.

Define properties on the ARMSSE object for the MPU regions (using the
same names as the documented RTL configuration settings, and
following the pattern we already have for this device of using
all-caps names as the RTL does), and set them in the board code.

We don't actually need to override the default except on AN547,
but it's simpler code to have the board code set them always
rather than tracking which board subtypes want to set them to
a non-default value separately from what that value is.

Tho overall effect is that for mps2-an505, mps2-an521 and mps3-an524
we now correctly use 8 MPU regions, while mps3-an547 stays at its
current 16 regions.

It's possible some guest code wrongly depended on the previous
incorrectly modeled number of memory regions. (Such guest code
should ideally check the number of regions via the MPU_TYPE
register.) The old behaviour can be obtained with additional
-global arguments to QEMU:

For mps2-an521 and mps2-an524:
 -global sse-200.CPU0_MPU_NS=16 -global sse-200.CPU0_MPU_S=16 -global sse-200.CPU1_MPU_NS=16 -global sse-200.CPU1_MPU_S=16

For mps2-an505:
 -global sse-200.CPU0_MPU_NS=16 -global sse-200.CPU0_MPU_S=16

NB that the way the implementation allows this use of -global
is slightly fragile: if the board code explicitly sets the
properties on the sse-200 object, this overrides the -global
command line option. So we rely on:
 - the boards that need fixing all happen to use the SSE defaults
 - we can write the board code to only set the property if it
   is different from the default, rather than having all boards
   explicitly set the property
 - the board that does need to use a non-default value happens
   to need to set it to the same value (16) we previously used
This works, but there are some kinds of refactoring of the
mps2-tz.c code that would break the support for -global here.

Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1772
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-id: 20230724174335.2150499-4-peter.maydell@linaro.org
---
 include/hw/arm/armsse.h |  5 +++++
 hw/arm/armsse.c         | 16 ++++++++++++++++
 hw/arm/mps2-tz.c        | 29 +++++++++++++++++++++++++++++
 3 files changed, 50 insertions(+)

diff --git a/include/hw/arm/armsse.h b/include/hw/arm/armsse.h
index XXXXXXX..XXXXXXX 100644
--- a/include/hw/arm/armsse.h
+++ b/include/hw/arm/armsse.h
@@ -XXX,XX +XXX,XX @@
  *    (matching the hardware) is that for CPU0 in an IoTKit and CPU1 in an
  *    SSE-200 both are present; CPU0 in an SSE-200 has neither.
  *    Since the IoTKit has only one CPU, it does not have the CPU1_* properties.
+ *  + QOM properties "CPU0_MPU_NS", "CPU0_MPU_S", "CPU1_MPU_NS" and "CPU1_MPU_S"
+ *    which set the number of MPU regions on the CPUs. If there is only one
+ *    CPU the CPU1 properties are not present.
  *  + Named GPIO inputs "EXP_IRQ" 0..n are the expansion interrupts for CPU 0,
  *    which are wired to its NVIC lines 32 .. n+32
  *  + Named GPIO inputs "EXP_CPU1_IRQ" 0..n are the expansion interrupts for
@@ -XXX,XX +XXX,XX @@ struct ARMSSE {
     uint32_t exp_numirq;
     uint32_t sram_addr_width;
     uint32_t init_svtor;
+    uint32_t cpu_mpu_ns[SSE_MAX_CPUS];
+    uint32_t cpu_mpu_s[SSE_MAX_CPUS];
     bool cpu_fpu[SSE_MAX_CPUS];
     bool cpu_dsp[SSE_MAX_CPUS];
 };
diff --git a/hw/arm/armsse.c b/hw/arm/armsse.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/armsse.c
+++ b/hw/arm/armsse.c
@@ -XXX,XX +XXX,XX @@ static Property iotkit_properties[] = {
     DEFINE_PROP_UINT32("init-svtor", ARMSSE, init_svtor, 0x10000000),
     DEFINE_PROP_BOOL("CPU0_FPU", ARMSSE, cpu_fpu[0], true),
     DEFINE_PROP_BOOL("CPU0_DSP", ARMSSE, cpu_dsp[0], true),
+    DEFINE_PROP_UINT32("CPU0_MPU_NS", ARMSSE, cpu_mpu_ns[0], 8),
+    DEFINE_PROP_UINT32("CPU0_MPU_S", ARMSSE, cpu_mpu_s[0], 8),
     DEFINE_PROP_END_OF_LIST()
 };
 
@@ -XXX,XX +XXX,XX @@ static Property sse200_properties[] = {
     DEFINE_PROP_BOOL("CPU0_DSP", ARMSSE, cpu_dsp[0], false),
     DEFINE_PROP_BOOL("CPU1_FPU", ARMSSE, cpu_fpu[1], true),
     DEFINE_PROP_BOOL("CPU1_DSP", ARMSSE, cpu_dsp[1], true),
+    DEFINE_PROP_UINT32("CPU0_MPU_NS", ARMSSE, cpu_mpu_ns[0], 8),
+    DEFINE_PROP_UINT32("CPU0_MPU_S", ARMSSE, cpu_mpu_s[0], 8),
+    DEFINE_PROP_UINT32("CPU1_MPU_NS", ARMSSE, cpu_mpu_ns[1], 8),
+    DEFINE_PROP_UINT32("CPU1_MPU_S", ARMSSE, cpu_mpu_s[1], 8),
     DEFINE_PROP_END_OF_LIST()
 };
 
@@ -XXX,XX +XXX,XX @@ static Property sse300_properties[] = {
     DEFINE_PROP_UINT32("init-svtor", ARMSSE, init_svtor, 0x10000000),
     DEFINE_PROP_BOOL("CPU0_FPU", ARMSSE, cpu_fpu[0], true),
     DEFINE_PROP_BOOL("CPU0_DSP", ARMSSE, cpu_dsp[0], true),
+    DEFINE_PROP_UINT32("CPU0_MPU_NS", ARMSSE, cpu_mpu_ns[0], 8),
+    DEFINE_PROP_UINT32("CPU0_MPU_S", ARMSSE, cpu_mpu_s[0], 8),
     DEFINE_PROP_END_OF_LIST()
 };
 
@@ -XXX,XX +XXX,XX @@ static void armsse_realize(DeviceState *dev, Error **errp)
                 return;
             }
         }
+        if (!object_property_set_uint(cpuobj, "mpu-ns-regions",
+                                      s->cpu_mpu_ns[i], errp)) {
+            return;
+        }
+        if (!object_property_set_uint(cpuobj, "mpu-s-regions",
+                                      s->cpu_mpu_s[i], errp)) {
+            return;
+        }
 
         if (i > 0) {
             memory_region_add_subregion_overlap(&s->cpu_container[i], 0,
diff --git a/hw/arm/mps2-tz.c b/hw/arm/mps2-tz.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/mps2-tz.c
+++ b/hw/arm/mps2-tz.c
@@ -XXX,XX +XXX,XX @@ struct MPS2TZMachineClass {
     int uart_overflow_irq; /* number of the combined UART overflow IRQ */
     uint32_t init_svtor; /* init-svtor setting for SSE */
     uint32_t sram_addr_width; /* SRAM_ADDR_WIDTH setting for SSE */
+    uint32_t cpu0_mpu_ns; /* CPU0_MPU_NS setting for SSE */
+    uint32_t cpu0_mpu_s; /* CPU0_MPU_S setting for SSE */
+    uint32_t cpu1_mpu_ns; /* CPU1_MPU_NS setting for SSE */
+    uint32_t cpu1_mpu_s; /* CPU1_MPU_S setting for SSE */
     const RAMInfo *raminfo;
     const char *armsse_type;
     uint32_t boot_ram_size; /* size of ram at address 0; 0 == find in raminfo */
@@ -XXX,XX +XXX,XX @@ OBJECT_DECLARE_TYPE(MPS2TZMachineState, MPS2TZMachineClass, MPS2TZ_MACHINE)
 #define MPS3_DDR_SIZE (2 * GiB)
 #endif
 
+/* For cpu{0,1}_mpu_{ns,s}, means "leave at SSE's default value" */
+#define MPU_REGION_DEFAULT UINT32_MAX
+
 static const uint32_t an505_oscclk[] = {
     40000000,
     24580000,
@@ -XXX,XX +XXX,XX @@ static void mps2tz_common_init(MachineState *machine)
                              OBJECT(system_memory), &error_abort);
     qdev_prop_set_uint32(iotkitdev, "EXP_NUMIRQ", mmc->numirq);
     qdev_prop_set_uint32(iotkitdev, "init-svtor", mmc->init_svtor);
+    if (mmc->cpu0_mpu_ns != MPU_REGION_DEFAULT) {
+        qdev_prop_set_uint32(iotkitdev, "CPU0_MPU_NS", mmc->cpu0_mpu_ns);
+    }
+    if (mmc->cpu0_mpu_s != MPU_REGION_DEFAULT) {
+        qdev_prop_set_uint32(iotkitdev, "CPU0_MPU_S", mmc->cpu0_mpu_s);
+    }
+    if (object_property_find(OBJECT(iotkitdev), "CPU1_MPU_NS")) {
+        if (mmc->cpu1_mpu_ns != MPU_REGION_DEFAULT) {
+            qdev_prop_set_uint32(iotkitdev, "CPU1_MPU_NS", mmc->cpu1_mpu_ns);
+        }
+        if (mmc->cpu1_mpu_s != MPU_REGION_DEFAULT) {
+            qdev_prop_set_uint32(iotkitdev, "CPU1_MPU_S", mmc->cpu1_mpu_s);
+        }
+    }
     qdev_prop_set_uint32(iotkitdev, "SRAM_ADDR_WIDTH", mmc->sram_addr_width);
     qdev_connect_clock_in(iotkitdev, "MAINCLK", mms->sysclk);
     qdev_connect_clock_in(iotkitdev, "S32KCLK", mms->s32kclk);
@@ -XXX,XX +XXX,XX @@ static void mps2tz_class_init(ObjectClass *oc, void *data)
 {
     MachineClass *mc = MACHINE_CLASS(oc);
     IDAUInterfaceClass *iic = IDAU_INTERFACE_CLASS(oc);
+    MPS2TZMachineClass *mmc = MPS2TZ_MACHINE_CLASS(oc);
 
     mc->init = mps2tz_common_init;
     mc->reset = mps2_machine_reset;
     iic->check = mps2_tz_idau_check;
+
+    /* Most machines leave these at the SSE defaults */
+    mmc->cpu0_mpu_ns = MPU_REGION_DEFAULT;
+    mmc->cpu0_mpu_s = MPU_REGION_DEFAULT;
+    mmc->cpu1_mpu_ns = MPU_REGION_DEFAULT;
+    mmc->cpu1_mpu_s = MPU_REGION_DEFAULT;
 }
 
 static void mps2tz_set_default_ram_info(MPS2TZMachineClass *mmc)
@@ -XXX,XX +XXX,XX @@ static void mps3tz_an547_class_init(ObjectClass *oc, void *data)
     mmc->numirq = 96;
     mmc->uart_overflow_irq = 48;
     mmc->init_svtor = 0x00000000;
+    mmc->cpu0_mpu_s = mmc->cpu0_mpu_ns = 16;
     mmc->sram_addr_width = 21;
     mmc->raminfo = an547_raminfo;
     mmc->armsse_type = TYPE_SSE300;
-- 
2.34.1