[v2] VSX MMA Implementation

[RFC PATCH v2 0/7] VSX MMA Implementation

Lucas Mateus Castro(alqotel) posted 7 patches 2 years ago

Diff against v1 v3 v4 v5 v6
Download series mbox

Patches applied successfully (tree, apply log)
git fetch https://github.com/patchew-project/qemu tags/patchew/20220506121844.18969-1-lucas.araujo@eldorado.org.br

Maintainers: Aurelien Jarno <aurelien@aurel32.net>, Peter Maydell <peter.maydell@linaro.org>, "Alex Bennée" <alex.bennee@linaro.org>, "Cédric Le Goater" <clg@kaod.org>, Daniel Henrique Barboza <danielhb413@gmail.com>, David Gibson <david@gibson.dropbear.id.au>, Greg Kurz <groug@kaod.org>

There is a newer version of this series

include/fpu/softfloat.h             |   9 +
target/ppc/cpu.h                    |  13 ++
target/ppc/fpu_helper.c             | 303 ++++++++++++++++++++++++++++
target/ppc/helper.h                 |  29 +++
target/ppc/insn32.decode            |  49 +++++
target/ppc/insn64.decode            |  79 ++++++++
target/ppc/int_helper.c             | 130 ++++++++++++
target/ppc/internal.h               |  15 ++
target/ppc/translate/vsx-impl.c.inc | 145 +++++++++++++
9 files changed, 772 insertions(+)

Expand all Fold all

[RFC PATCH v2 0/7] VSX MMA Implementation

Posted by Lucas Mateus Castro(alqotel) 2 years ago

From: "Lucas Mateus Castro (alqotel)" <lucas.araujo@eldorado.org.br>

This patch series is an RFC of the Matrix-Multiply Assist (MMA)
instructions implementation from the PowerISA 3.1

These and the VDIV/VMOD implementation are the last new PowerISA 3.1
instructions left to be implemented.

The XVFGER instructions accumulate the exception status and at the end
set the FPSCR and take a Program interrupt on a trap-enabled exception,
but as the exception functions are currently set up in
target/ppc/fpu_helper.c a call to set a FPSCR bit could raise an
exception before all bits could be set and it doesn't set the invalid
operation bits.

Victor is working on a patch series to fix the FPSCR.FI bit that will
reorganize do_float_check_status (in a way that would solve the
aforementioned problem), so for now I sent thin RFC without trying to
solve that problem.

v2 changes:
    - Changed VSXGER, VSXGER16 and XVIGER macros to functions
    - Set rounding mode in floating-point instructions based on RN
      before operations
    - Separated accumulate and with saturations instructions in
      different helpers
    - Used FIELD, FIELD_EX32 and FIELD_DP32 for packing/unpacking masks

Lucas Mateus Castro (alqotel) (7):
  target/ppc: Implement xxm[tf]acc and xxsetaccz
  target/ppc: Implemented xvi*ger* instructions
  target/ppc: Implemented pmxvi*ger* instructions
  target/ppc: Implemented xvf*ger*
  target/ppc: Implemented xvf16ger*
  target/ppc: Implemented pmxvf*ger*
  target/ppc: Implemented [pm]xvbf16ger2*

 include/fpu/softfloat.h             |   9 +
 target/ppc/cpu.h                    |  13 ++
 target/ppc/fpu_helper.c             | 303 ++++++++++++++++++++++++++++
 target/ppc/helper.h                 |  29 +++
 target/ppc/insn32.decode            |  49 +++++
 target/ppc/insn64.decode            |  79 ++++++++
 target/ppc/int_helper.c             | 130 ++++++++++++
 target/ppc/internal.h               |  15 ++
 target/ppc/translate/vsx-impl.c.inc | 145 +++++++++++++
 9 files changed, 772 insertions(+)

-- 
2.31.1